FreeBSD kernel E1000 device code
if_em.c
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1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/* $FreeBSD$ */
30#include "if_em.h"
31#include <sys/sbuf.h>
32#include <machine/_inttypes.h>
33
34#define em_mac_min e1000_82571
35#define igb_mac_min e1000_82575
36
37/*********************************************************************
38 * Driver version:
39 *********************************************************************/
40char em_driver_version[] = "7.6.1-k";
41
42/*********************************************************************
43 * PCI Device ID Table
44 *
45 * Used by probe to select devices to load on
46 * Last field stores an index into e1000_strings
47 * Last entry must be all 0s
48 *
49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
50 *********************************************************************/
51
52static pci_vendor_info_t em_vendor_info_array[] =
53{
54 /* Intel(R) - lem-class legacy devices */
55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
60
61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
68
69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
70
71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
73
74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
78
79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
84
85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
94
95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
98
99 /* Intel(R) - em-class devices */
100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
197 /* required last entry */
198 PVID_END
199};
200
201static pci_vendor_info_t igb_vendor_info_array[] =
202{
203 /* Intel(R) - igb-class devices */
204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"),
237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
244 /* required last entry */
245 PVID_END
246};
247
248/*********************************************************************
249 * Function prototypes
250 *********************************************************************/
251static void *em_register(device_t);
252static void *igb_register(device_t);
253static int em_if_attach_pre(if_ctx_t);
254static int em_if_attach_post(if_ctx_t);
255static int em_if_detach(if_ctx_t);
256static int em_if_shutdown(if_ctx_t);
257static int em_if_suspend(if_ctx_t);
258static int em_if_resume(if_ctx_t);
259
260static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
261static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
262static void em_if_queues_free(if_ctx_t);
263
264static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
265static void em_if_init(if_ctx_t);
266static void em_if_stop(if_ctx_t);
267static void em_if_media_status(if_ctx_t, struct ifmediareq *);
268static int em_if_media_change(if_ctx_t);
269static int em_if_mtu_set(if_ctx_t, uint32_t);
270static void em_if_timer(if_ctx_t, uint16_t);
271static void em_if_vlan_register(if_ctx_t, u16);
272static void em_if_vlan_unregister(if_ctx_t, u16);
273static void em_if_watchdog_reset(if_ctx_t);
274static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event);
275
276static void em_identify_hardware(if_ctx_t);
277static int em_allocate_pci_resources(if_ctx_t);
278static void em_free_pci_resources(if_ctx_t);
279static void em_reset(if_ctx_t);
280static int em_setup_interface(if_ctx_t);
281static int em_setup_msix(if_ctx_t);
282
283static void em_initialize_transmit_unit(if_ctx_t);
284static void em_initialize_receive_unit(if_ctx_t);
285
286static void em_if_intr_enable(if_ctx_t);
287static void em_if_intr_disable(if_ctx_t);
288static void igb_if_intr_enable(if_ctx_t);
289static void igb_if_intr_disable(if_ctx_t);
290static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
291static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
292static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
293static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
294static void em_if_multi_set(if_ctx_t);
295static void em_if_update_admin_status(if_ctx_t);
296static void em_if_debug(if_ctx_t);
297static void em_update_stats_counters(struct e1000_softc *);
298static void em_add_hw_stats(struct e1000_softc *);
299static int em_if_set_promisc(if_ctx_t, int);
300static bool em_if_vlan_filter_capable(if_ctx_t);
301static bool em_if_vlan_filter_used(if_ctx_t);
302static void em_if_vlan_filter_enable(struct e1000_softc *);
303static void em_if_vlan_filter_disable(struct e1000_softc *);
304static void em_if_vlan_filter_write(struct e1000_softc *);
305static void em_setup_vlan_hw_support(if_ctx_t ctx);
306static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
307static void em_print_nvm_info(struct e1000_softc *);
308static void em_fw_version_locked(if_ctx_t);
309static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *);
310static void em_print_fw_version(struct e1000_softc *);
311static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
312static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
313static int em_get_rs(SYSCTL_HANDLER_ARGS);
314static void em_print_debug_info(struct e1000_softc *);
315static int em_is_valid_ether_addr(u8 *);
316static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
317static void em_add_int_delay_sysctl(struct e1000_softc *, const char *,
318 const char *, struct em_int_delay_info *, int, int);
319/* Management and WOL Support */
320static void em_init_manageability(struct e1000_softc *);
321static void em_release_manageability(struct e1000_softc *);
322static void em_get_hw_control(struct e1000_softc *);
323static void em_release_hw_control(struct e1000_softc *);
324static void em_get_wakeup(if_ctx_t);
325static void em_enable_wakeup(if_ctx_t);
326static int em_enable_phy_wakeup(struct e1000_softc *);
327static void em_disable_aspm(struct e1000_softc *);
328
329int em_intr(void *);
330
331/* MSI-X handlers */
332static int em_if_msix_intr_assign(if_ctx_t, int);
333static int em_msix_link(void *);
334static void em_handle_link(void *);
335
336static void em_enable_vectors_82574(if_ctx_t);
337
338static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
339static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
340static void em_if_led_func(if_ctx_t, int);
341
342static int em_get_regs(SYSCTL_HANDLER_ARGS);
343
344static void lem_smartspeed(struct e1000_softc *);
345static void igb_configure_queues(struct e1000_softc *);
346
347
348/*********************************************************************
349 * FreeBSD Device Interface Entry Points
350 *********************************************************************/
351static device_method_t em_methods[] = {
352 /* Device interface */
353 DEVMETHOD(device_register, em_register),
354 DEVMETHOD(device_probe, iflib_device_probe),
355 DEVMETHOD(device_attach, iflib_device_attach),
356 DEVMETHOD(device_detach, iflib_device_detach),
357 DEVMETHOD(device_shutdown, iflib_device_shutdown),
358 DEVMETHOD(device_suspend, iflib_device_suspend),
359 DEVMETHOD(device_resume, iflib_device_resume),
360 DEVMETHOD_END
361};
362
363static device_method_t igb_methods[] = {
364 /* Device interface */
365 DEVMETHOD(device_register, igb_register),
366 DEVMETHOD(device_probe, iflib_device_probe),
367 DEVMETHOD(device_attach, iflib_device_attach),
368 DEVMETHOD(device_detach, iflib_device_detach),
369 DEVMETHOD(device_shutdown, iflib_device_shutdown),
370 DEVMETHOD(device_suspend, iflib_device_suspend),
371 DEVMETHOD(device_resume, iflib_device_resume),
372 DEVMETHOD_END
373};
374
375
376static driver_t em_driver = {
377 "em", em_methods, sizeof(struct e1000_softc),
378};
379
380static devclass_t em_devclass;
381DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
382
383MODULE_DEPEND(em, pci, 1, 1, 1);
384MODULE_DEPEND(em, ether, 1, 1, 1);
385MODULE_DEPEND(em, iflib, 1, 1, 1);
386
387IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
388
389static driver_t igb_driver = {
390 "igb", igb_methods, sizeof(struct e1000_softc),
391};
392
393static devclass_t igb_devclass;
394DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
395
396MODULE_DEPEND(igb, pci, 1, 1, 1);
397MODULE_DEPEND(igb, ether, 1, 1, 1);
398MODULE_DEPEND(igb, iflib, 1, 1, 1);
399
400IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
401
402static device_method_t em_if_methods[] = {
403 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
404 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
405 DEVMETHOD(ifdi_detach, em_if_detach),
406 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
407 DEVMETHOD(ifdi_suspend, em_if_suspend),
408 DEVMETHOD(ifdi_resume, em_if_resume),
409 DEVMETHOD(ifdi_init, em_if_init),
410 DEVMETHOD(ifdi_stop, em_if_stop),
411 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
412 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
413 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
414 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
415 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
416 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
417 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
418 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
419 DEVMETHOD(ifdi_media_status, em_if_media_status),
420 DEVMETHOD(ifdi_media_change, em_if_media_change),
421 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
422 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
423 DEVMETHOD(ifdi_timer, em_if_timer),
424 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
425 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
426 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
427 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
428 DEVMETHOD(ifdi_led_func, em_if_led_func),
429 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
430 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
431 DEVMETHOD(ifdi_debug, em_if_debug),
432 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
433 DEVMETHOD_END
434};
435
436static driver_t em_if_driver = {
437 "em_if", em_if_methods, sizeof(struct e1000_softc)
438};
439
440static device_method_t igb_if_methods[] = {
441 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
442 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
443 DEVMETHOD(ifdi_detach, em_if_detach),
444 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
445 DEVMETHOD(ifdi_suspend, em_if_suspend),
446 DEVMETHOD(ifdi_resume, em_if_resume),
447 DEVMETHOD(ifdi_init, em_if_init),
448 DEVMETHOD(ifdi_stop, em_if_stop),
449 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
450 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
451 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
452 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
453 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
454 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
455 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
456 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
457 DEVMETHOD(ifdi_media_status, em_if_media_status),
458 DEVMETHOD(ifdi_media_change, em_if_media_change),
459 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
460 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
461 DEVMETHOD(ifdi_timer, em_if_timer),
462 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
463 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
464 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
465 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
466 DEVMETHOD(ifdi_led_func, em_if_led_func),
467 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
468 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
469 DEVMETHOD(ifdi_debug, em_if_debug),
470 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
471 DEVMETHOD_END
472};
473
474static driver_t igb_if_driver = {
475 "igb_if", igb_if_methods, sizeof(struct e1000_softc)
476};
477
478/*********************************************************************
479 * Tunable default values.
480 *********************************************************************/
481
482#define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
483#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
484
485#define MAX_INTS_PER_SEC 8000
486#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
487
488/* Allow common code without TSO */
489#ifndef CSUM_TSO
490#define CSUM_TSO 0
491#endif
492
493static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
494 "EM driver parameters");
495
496static int em_disable_crc_stripping = 0;
497SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
498 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
499
500static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
501static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
502SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
503 0, "Default transmit interrupt delay in usecs");
504SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
505 0, "Default receive interrupt delay in usecs");
506
507static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
508static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
509SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
510 &em_tx_abs_int_delay_dflt, 0,
511 "Default transmit interrupt delay limit in usecs");
512SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
513 &em_rx_abs_int_delay_dflt, 0,
514 "Default receive interrupt delay limit in usecs");
515
516static int em_smart_pwr_down = false;
517SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
518 0, "Set to true to leave smart power down enabled on newer adapters");
519
520/* Controls whether promiscuous also shows bad packets */
521static int em_debug_sbp = false;
522SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
523 "Show bad packets in promiscuous mode");
524
525/* How many packets rxeof tries to clean at a time */
526static int em_rx_process_limit = 100;
527SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
528 &em_rx_process_limit, 0,
529 "Maximum number of received packets to process "
530 "at a time, -1 means unlimited");
531
532/* Energy efficient ethernet - default to OFF */
533static int eee_setting = 1;
534SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
535 "Enable Energy Efficient Ethernet");
536
537/*
538** Tuneable Interrupt rate
539*/
540static int em_max_interrupt_rate = 8000;
541SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
542 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
543
544
545
546/* Global used in WOL setup with multiport cards */
547static int global_quad_port_a = 0;
548
549extern struct if_txrx igb_txrx;
550extern struct if_txrx em_txrx;
551extern struct if_txrx lem_txrx;
552
553static struct if_shared_ctx em_sctx_init = {
554 .isc_magic = IFLIB_MAGIC,
555 .isc_q_align = PAGE_SIZE,
556 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
557 .isc_tx_maxsegsize = PAGE_SIZE,
558 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
559 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
560 .isc_rx_maxsize = MJUM9BYTES,
561 .isc_rx_nsegments = 1,
562 .isc_rx_maxsegsize = MJUM9BYTES,
563 .isc_nfl = 1,
564 .isc_nrxqs = 1,
565 .isc_ntxqs = 1,
566 .isc_admin_intrcnt = 1,
567 .isc_vendor_info = em_vendor_info_array,
568 .isc_driver_version = em_driver_version,
569 .isc_driver = &em_if_driver,
570 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
571
572 .isc_nrxd_min = {EM_MIN_RXD},
573 .isc_ntxd_min = {EM_MIN_TXD},
574 .isc_nrxd_max = {EM_MAX_RXD},
575 .isc_ntxd_max = {EM_MAX_TXD},
576 .isc_nrxd_default = {EM_DEFAULT_RXD},
577 .isc_ntxd_default = {EM_DEFAULT_TXD},
578};
579
580static struct if_shared_ctx igb_sctx_init = {
581 .isc_magic = IFLIB_MAGIC,
582 .isc_q_align = PAGE_SIZE,
583 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
584 .isc_tx_maxsegsize = PAGE_SIZE,
585 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
586 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
587 .isc_rx_maxsize = MJUM9BYTES,
588 .isc_rx_nsegments = 1,
589 .isc_rx_maxsegsize = MJUM9BYTES,
590 .isc_nfl = 1,
591 .isc_nrxqs = 1,
592 .isc_ntxqs = 1,
593 .isc_admin_intrcnt = 1,
594 .isc_vendor_info = igb_vendor_info_array,
595 .isc_driver_version = em_driver_version,
596 .isc_driver = &igb_if_driver,
597 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
598
599 .isc_nrxd_min = {EM_MIN_RXD},
600 .isc_ntxd_min = {EM_MIN_TXD},
601 .isc_nrxd_max = {IGB_MAX_RXD},
602 .isc_ntxd_max = {IGB_MAX_TXD},
603 .isc_nrxd_default = {EM_DEFAULT_RXD},
604 .isc_ntxd_default = {EM_DEFAULT_TXD},
605};
606
607/*****************************************************************
608 *
609 * Dump Registers
610 *
611 ****************************************************************/
612#define IGB_REGS_LEN 739
613
614static int em_get_regs(SYSCTL_HANDLER_ARGS)
615{
616 struct e1000_softc *sc = (struct e1000_softc *)arg1;
617 struct e1000_hw *hw = &sc->hw;
618 struct sbuf *sb;
619 u32 *regs_buff;
620 int rc;
621
622 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
623 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
624
625 rc = sysctl_wire_old_buffer(req, 0);
626 MPASS(rc == 0);
627 if (rc != 0) {
628 free(regs_buff, M_DEVBUF);
629 return (rc);
630 }
631
632 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
633 MPASS(sb != NULL);
634 if (sb == NULL) {
635 free(regs_buff, M_DEVBUF);
636 return (ENOMEM);
637 }
638
639 /* General Registers */
640 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
641 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
642 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
643 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
644 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
645 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
646 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
647 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
648 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
649 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
650 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
651 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
652 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
653 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
654 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
655 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
656 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
657 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
658 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
659 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
660 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
661 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
662
663 sbuf_printf(sb, "General Registers\n");
664 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
665 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
666 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
667
668 sbuf_printf(sb, "Interrupt Registers\n");
669 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
670
671 sbuf_printf(sb, "RX Registers\n");
672 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
673 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
674 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
675 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
676 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
677 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
678 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
679
680 sbuf_printf(sb, "TX Registers\n");
681 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
682 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
683 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
684 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
685 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
686 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
687 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
688 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
689 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
690 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
691 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
692
693 free(regs_buff, M_DEVBUF);
694
695#ifdef DUMP_DESCS
696 {
697 if_softc_ctx_t scctx = sc->shared;
698 struct rx_ring *rxr = &rx_que->rxr;
699 struct tx_ring *txr = &tx_que->txr;
700 int ntxd = scctx->isc_ntxd[0];
701 int nrxd = scctx->isc_nrxd[0];
702 int j;
703
704 for (j = 0; j < nrxd; j++) {
705 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
706 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
707 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
708 }
709
710 for (j = 0; j < min(ntxd, 256); j++) {
711 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
712
713 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
714 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
715 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
716
717 }
718 }
719#endif
720
721 rc = sbuf_finish(sb);
722 sbuf_delete(sb);
723 return(rc);
724}
725
726static void *
727em_register(device_t dev)
728{
729 return (&em_sctx_init);
730}
731
732static void *
733igb_register(device_t dev)
734{
735 return (&igb_sctx_init);
736}
737
738static int
739em_set_num_queues(if_ctx_t ctx)
740{
741 struct e1000_softc *sc = iflib_get_softc(ctx);
742 int maxqueues;
743
744 /* Sanity check based on HW */
745 switch (sc->hw.mac.type) {
746 case e1000_82576:
747 case e1000_82580:
748 case e1000_i350:
749 case e1000_i354:
750 maxqueues = 8;
751 break;
752 case e1000_i210:
753 case e1000_82575:
754 maxqueues = 4;
755 break;
756 case e1000_i211:
757 case e1000_82574:
758 maxqueues = 2;
759 break;
760 default:
761 maxqueues = 1;
762 break;
763 }
764
765 return (maxqueues);
766}
767
768#define LEM_CAPS \
769 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
770 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
771
772#define EM_CAPS \
773 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
774 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
775 IFCAP_LRO | IFCAP_VLAN_HWTSO
776
777#define IGB_CAPS \
778 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
779 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
780 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
781 IFCAP_TSO6
782
783/*********************************************************************
784 * Device initialization routine
785 *
786 * The attach entry point is called when the driver is being loaded.
787 * This routine identifies the type of hardware, allocates all resources
788 * and initializes the hardware.
789 *
790 * return 0 on success, positive on failure
791 *********************************************************************/
792static int
793em_if_attach_pre(if_ctx_t ctx)
794{
795 struct e1000_softc *sc;
796 if_softc_ctx_t scctx;
797 device_t dev;
798 struct e1000_hw *hw;
799 struct sysctl_oid_list *child;
800 struct sysctl_ctx_list *ctx_list;
801 int error = 0;
802
803 INIT_DEBUGOUT("em_if_attach_pre: begin");
804 dev = iflib_get_dev(ctx);
805 sc = iflib_get_softc(ctx);
806
807 sc->ctx = sc->osdep.ctx = ctx;
808 sc->dev = sc->osdep.dev = dev;
809 scctx = sc->shared = iflib_get_softc_ctx(ctx);
810 sc->media = iflib_get_media(ctx);
811 hw = &sc->hw;
812
813 sc->tx_process_limit = scctx->isc_ntxd[0];
814
815 /* Determine hardware and mac info */
816 em_identify_hardware(ctx);
817
818 /* SYSCTL stuff */
819 ctx_list = device_get_sysctl_ctx(dev);
820 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
821
822 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm",
823 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
824 em_sysctl_nvm_info, "I", "NVM Information");
825
826 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
827 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
828 em_sysctl_print_fw_version, "A",
829 "Prints FW/NVM Versions");
830
831 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug",
832 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
833 em_sysctl_debug_info, "I", "Debug Information");
834
835 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc",
836 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
837 em_set_flowcntl, "I", "Flow Control");
838
839 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump",
840 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
841 em_get_regs, "A", "Dump Registers");
842
843 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump",
844 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
845 em_get_rs, "I", "Dump RS indexes");
846
847 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
848 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
849 if (bootverbose)
850 device_printf(dev, "attach_pre capping queues at %d\n",
851 scctx->isc_ntxqsets_max);
852
853 if (hw->mac.type >= igb_mac_min) {
854 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
855 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
856 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
857 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
858 scctx->isc_txrx = &igb_txrx;
859 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
860 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
861 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
862 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
863 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
864 CSUM_IP6_TCP | CSUM_IP6_UDP;
865 if (hw->mac.type != e1000_82575)
866 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
867 /*
868 ** Some new devices, as with ixgbe, now may
869 ** use a different BAR, so we need to keep
870 ** track of which is used.
871 */
872 scctx->isc_msix_bar = pci_msix_table_bar(dev);
873 } else if (hw->mac.type >= em_mac_min) {
874 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
875 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
876 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
877 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
878 scctx->isc_txrx = &em_txrx;
879 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
880 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
881 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
882 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
883 /*
884 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
885 * by default as we don't have workarounds for all associated
886 * silicon errata. E. g., with several MACs such as 82573E,
887 * TSO only works at Gigabit speed and otherwise can cause the
888 * hardware to hang (which also would be next to impossible to
889 * work around given that already queued TSO-using descriptors
890 * would need to be flushed and vlan(4) reconfigured at runtime
891 * in case of a link speed change). Moreover, MACs like 82579
892 * still can hang at Gigabit even with all publicly documented
893 * TSO workarounds implemented. Generally, the penality of
894 * these workarounds is rather high and may involve copying
895 * mbuf data around so advantages of TSO lapse. Still, TSO may
896 * work for a few MACs of this class - at least when sticking
897 * with Gigabit - in which case users may enable TSO manually.
898 */
899 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
900 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
901 /*
902 * We support MSI-X with 82574 only, but indicate to iflib(4)
903 * that it shall give MSI at least a try with other devices.
904 */
905 if (hw->mac.type == e1000_82574) {
906 scctx->isc_msix_bar = pci_msix_table_bar(dev);;
907 } else {
908 scctx->isc_msix_bar = -1;
909 scctx->isc_disable_msix = 1;
910 }
911 } else {
912 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
913 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
914 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
915 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
916 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
917 scctx->isc_txrx = &lem_txrx;
918 scctx->isc_capabilities = LEM_CAPS;
919 if (hw->mac.type < e1000_82543)
920 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
921 /* 82541ER doesn't do HW tagging */
922 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM)
923 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING;
924 /* INTx only */
925 scctx->isc_msix_bar = 0;
926 scctx->isc_capenable = scctx->isc_capabilities;
927 }
928
929 /* Setup PCI resources */
930 if (em_allocate_pci_resources(ctx)) {
931 device_printf(dev, "Allocation of PCI resources failed\n");
932 error = ENXIO;
933 goto err_pci;
934 }
935
936 /*
937 ** For ICH8 and family we need to
938 ** map the flash memory, and this
939 ** must happen after the MAC is
940 ** identified
941 */
942 if ((hw->mac.type == e1000_ich8lan) ||
943 (hw->mac.type == e1000_ich9lan) ||
944 (hw->mac.type == e1000_ich10lan) ||
945 (hw->mac.type == e1000_pchlan) ||
946 (hw->mac.type == e1000_pch2lan) ||
947 (hw->mac.type == e1000_pch_lpt)) {
948 int rid = EM_BAR_TYPE_FLASH;
949 sc->flash = bus_alloc_resource_any(dev,
950 SYS_RES_MEMORY, &rid, RF_ACTIVE);
951 if (sc->flash == NULL) {
952 device_printf(dev, "Mapping of Flash failed\n");
953 error = ENXIO;
954 goto err_pci;
955 }
956 /* This is used in the shared code */
957 hw->flash_address = (u8 *)sc->flash;
958 sc->osdep.flash_bus_space_tag =
959 rman_get_bustag(sc->flash);
960 sc->osdep.flash_bus_space_handle =
961 rman_get_bushandle(sc->flash);
962 }
963 /*
964 ** In the new SPT device flash is not a
965 ** separate BAR, rather it is also in BAR0,
966 ** so use the same tag and an offset handle for the
967 ** FLASH read/write macros in the shared code.
968 */
969 else if (hw->mac.type >= e1000_pch_spt) {
970 sc->osdep.flash_bus_space_tag =
971 sc->osdep.mem_bus_space_tag;
972 sc->osdep.flash_bus_space_handle =
973 sc->osdep.mem_bus_space_handle
974 + E1000_FLASH_BASE_ADDR;
975 }
976
977 /* Do Shared Code initialization */
978 error = e1000_setup_init_funcs(hw, true);
979 if (error) {
980 device_printf(dev, "Setup of Shared code failed, error %d\n",
981 error);
982 error = ENXIO;
983 goto err_pci;
984 }
985
986 em_setup_msix(ctx);
987 e1000_get_bus_info(hw);
988
989 /* Set up some sysctls for the tunable interrupt delays */
990 em_add_int_delay_sysctl(sc, "rx_int_delay",
991 "receive interrupt delay in usecs", &sc->rx_int_delay,
992 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
993 em_add_int_delay_sysctl(sc, "tx_int_delay",
994 "transmit interrupt delay in usecs", &sc->tx_int_delay,
995 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
996 em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
997 "receive interrupt delay limit in usecs",
998 &sc->rx_abs_int_delay,
999 E1000_REGISTER(hw, E1000_RADV),
1000 em_rx_abs_int_delay_dflt);
1001 em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
1002 "transmit interrupt delay limit in usecs",
1003 &sc->tx_abs_int_delay,
1004 E1000_REGISTER(hw, E1000_TADV),
1005 em_tx_abs_int_delay_dflt);
1006 em_add_int_delay_sysctl(sc, "itr",
1007 "interrupt delay limit in usecs/4",
1008 &sc->tx_itr,
1009 E1000_REGISTER(hw, E1000_ITR),
1010 DEFAULT_ITR);
1011
1012 hw->mac.autoneg = DO_AUTO_NEG;
1013 hw->phy.autoneg_wait_to_complete = false;
1014 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1015
1016 if (hw->mac.type < em_mac_min) {
1017 e1000_init_script_state_82541(hw, true);
1018 e1000_set_tbi_compatibility_82543(hw, true);
1019 }
1020 /* Copper options */
1021 if (hw->phy.media_type == e1000_media_type_copper) {
1022 hw->phy.mdix = AUTO_ALL_MODES;
1023 hw->phy.disable_polarity_correction = false;
1024 hw->phy.ms_type = EM_MASTER_SLAVE;
1025 }
1026
1027 /*
1028 * Set the frame limits assuming
1029 * standard ethernet sized frames.
1030 */
1031 scctx->isc_max_frame_size = hw->mac.max_frame_size =
1032 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1033
1034 /*
1035 * This controls when hardware reports transmit completion
1036 * status.
1037 */
1038 hw->mac.report_tx_early = 1;
1039
1040 /* Allocate multicast array memory. */
1041 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1042 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1043 if (sc->mta == NULL) {
1044 device_printf(dev, "Can not allocate multicast setup array\n");
1045 error = ENOMEM;
1046 goto err_late;
1047 }
1048
1049 /* Check SOL/IDER usage */
1050 if (e1000_check_reset_block(hw))
1051 device_printf(dev, "PHY reset is blocked"
1052 " due to SOL/IDER session.\n");
1053
1054 /* Sysctl for setting Energy Efficient Ethernet */
1055 hw->dev_spec.ich8lan.eee_disable = eee_setting;
1056 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control",
1057 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
1058 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet");
1059
1060 /*
1061 ** Start from a known state, this is
1062 ** important in reading the nvm and
1063 ** mac from that.
1064 */
1065 e1000_reset_hw(hw);
1066
1067 /* Make sure we have a good EEPROM before we read from it */
1068 if (e1000_validate_nvm_checksum(hw) < 0) {
1069 /*
1070 ** Some PCI-E parts fail the first check due to
1071 ** the link being in sleep state, call it again,
1072 ** if it fails a second time its a real issue.
1073 */
1074 if (e1000_validate_nvm_checksum(hw) < 0) {
1075 device_printf(dev,
1076 "The EEPROM Checksum Is Not Valid\n");
1077 error = EIO;
1078 goto err_late;
1079 }
1080 }
1081
1082 /* Copy the permanent MAC address out of the EEPROM */
1083 if (e1000_read_mac_addr(hw) < 0) {
1084 device_printf(dev, "EEPROM read error while reading MAC"
1085 " address\n");
1086 error = EIO;
1087 goto err_late;
1088 }
1089
1090 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1091 if (sc->vf_ifp) {
1092 ether_gen_addr(iflib_get_ifp(ctx),
1093 (struct ether_addr *)hw->mac.addr);
1094 } else {
1095 device_printf(dev, "Invalid MAC address\n");
1096 error = EIO;
1097 goto err_late;
1098 }
1099 }
1100
1101 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */
1102 em_fw_version_locked(ctx);
1103
1104 em_print_fw_version(sc);
1105
1106 /* Disable ULP support */
1107 e1000_disable_ulp_lpt_lp(hw, true);
1108
1109 /*
1110 * Get Wake-on-Lan and Management info for later use
1111 */
1112 em_get_wakeup(ctx);
1113
1114 /* Enable only WOL MAGIC by default */
1115 scctx->isc_capenable &= ~IFCAP_WOL;
1116 if (sc->wol != 0)
1117 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1118
1119 iflib_set_mac(ctx, hw->mac.addr);
1120
1121 return (0);
1122
1123err_late:
1124 em_release_hw_control(sc);
1125err_pci:
1126 em_free_pci_resources(ctx);
1127 free(sc->mta, M_DEVBUF);
1128
1129 return (error);
1130}
1131
1132static int
1133em_if_attach_post(if_ctx_t ctx)
1134{
1135 struct e1000_softc *sc = iflib_get_softc(ctx);
1136 struct e1000_hw *hw = &sc->hw;
1137 int error = 0;
1138
1139 /* Setup OS specific network interface */
1140 error = em_setup_interface(ctx);
1141 if (error != 0) {
1142 device_printf(sc->dev, "Interface setup failed: %d\n", error);
1143 goto err_late;
1144 }
1145
1146 em_reset(ctx);
1147
1148 /* Initialize statistics */
1149 em_update_stats_counters(sc);
1150 hw->mac.get_link_status = 1;
1151 em_if_update_admin_status(ctx);
1152 em_add_hw_stats(sc);
1153
1154 /* Non-AMT based hardware can now take control from firmware */
1155 if (sc->has_manage && !sc->has_amt)
1156 em_get_hw_control(sc);
1157
1158 INIT_DEBUGOUT("em_if_attach_post: end");
1159
1160 return (0);
1161
1162err_late:
1163 /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1164 return (error);
1165}
1166
1167/*********************************************************************
1168 * Device removal routine
1169 *
1170 * The detach entry point is called when the driver is being removed.
1171 * This routine stops the adapter and deallocates all the resources
1172 * that were allocated for driver operation.
1173 *
1174 * return 0 on success, positive on failure
1175 *********************************************************************/
1176static int
1177em_if_detach(if_ctx_t ctx)
1178{
1179 struct e1000_softc *sc = iflib_get_softc(ctx);
1180
1181 INIT_DEBUGOUT("em_if_detach: begin");
1182
1183 e1000_phy_hw_reset(&sc->hw);
1184
1185 em_release_manageability(sc);
1186 em_release_hw_control(sc);
1187 em_free_pci_resources(ctx);
1188 free(sc->mta, M_DEVBUF);
1189 sc->mta = NULL;
1190
1191 return (0);
1192}
1193
1194/*********************************************************************
1195 *
1196 * Shutdown entry point
1197 *
1198 **********************************************************************/
1199
1200static int
1201em_if_shutdown(if_ctx_t ctx)
1202{
1203 return em_if_suspend(ctx);
1204}
1205
1206/*
1207 * Suspend/resume device methods.
1208 */
1209static int
1210em_if_suspend(if_ctx_t ctx)
1211{
1212 struct e1000_softc *sc = iflib_get_softc(ctx);
1213
1214 em_release_manageability(sc);
1215 em_release_hw_control(sc);
1216 em_enable_wakeup(ctx);
1217 return (0);
1218}
1219
1220static int
1221em_if_resume(if_ctx_t ctx)
1222{
1223 struct e1000_softc *sc = iflib_get_softc(ctx);
1224
1225 if (sc->hw.mac.type == e1000_pch2lan)
1226 e1000_resume_workarounds_pchlan(&sc->hw);
1227 em_if_init(ctx);
1228 em_init_manageability(sc);
1229
1230 return(0);
1231}
1232
1233static int
1234em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1235{
1236 int max_frame_size;
1237 struct e1000_softc *sc = iflib_get_softc(ctx);
1238 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1239
1240 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1241
1242 switch (sc->hw.mac.type) {
1243 case e1000_82571:
1244 case e1000_82572:
1245 case e1000_ich9lan:
1246 case e1000_ich10lan:
1247 case e1000_pch2lan:
1248 case e1000_pch_lpt:
1249 case e1000_pch_spt:
1250 case e1000_pch_cnp:
1251 case e1000_pch_tgp:
1252 case e1000_pch_adp:
1253 case e1000_pch_mtp:
1254 case e1000_82574:
1255 case e1000_82583:
1256 case e1000_80003es2lan:
1257 /* 9K Jumbo Frame size */
1258 max_frame_size = 9234;
1259 break;
1260 case e1000_pchlan:
1261 max_frame_size = 4096;
1262 break;
1263 case e1000_82542:
1264 case e1000_ich8lan:
1265 /* Adapters that do not support jumbo frames */
1266 max_frame_size = ETHER_MAX_LEN;
1267 break;
1268 default:
1269 if (sc->hw.mac.type >= igb_mac_min)
1270 max_frame_size = 9234;
1271 else /* lem */
1272 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1273 }
1274 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1275 return (EINVAL);
1276 }
1277
1278 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
1279 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1280 return (0);
1281}
1282
1283/*********************************************************************
1284 * Init entry point
1285 *
1286 * This routine is used in two ways. It is used by the stack as
1287 * init entry point in network interface structure. It is also used
1288 * by the driver as a hw/sw initialization routine to get to a
1289 * consistent state.
1290 *
1291 **********************************************************************/
1292static void
1293em_if_init(if_ctx_t ctx)
1294{
1295 struct e1000_softc *sc = iflib_get_softc(ctx);
1296 if_softc_ctx_t scctx = sc->shared;
1297 struct ifnet *ifp = iflib_get_ifp(ctx);
1298 struct em_tx_queue *tx_que;
1299 int i;
1300
1301 INIT_DEBUGOUT("em_if_init: begin");
1302
1303 /* Get the latest mac address, User can use a LAA */
1304 bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
1305 ETHER_ADDR_LEN);
1306
1307 /* Put the address into the Receive Address Array */
1308 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1309
1310 /*
1311 * With the 82571 adapter, RAR[0] may be overwritten
1312 * when the other port is reset, we make a duplicate
1313 * in RAR[14] for that eventuality, this assures
1314 * the interface continues to function.
1315 */
1316 if (sc->hw.mac.type == e1000_82571) {
1317 e1000_set_laa_state_82571(&sc->hw, true);
1318 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1319 E1000_RAR_ENTRIES - 1);
1320 }
1321
1322
1323 /* Initialize the hardware */
1324 em_reset(ctx);
1325 em_if_update_admin_status(ctx);
1326
1327 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) {
1328 struct tx_ring *txr = &tx_que->txr;
1329
1330 txr->tx_rs_cidx = txr->tx_rs_pidx;
1331
1332 /* Initialize the last processed descriptor to be the end of
1333 * the ring, rather than the start, so that we avoid an
1334 * off-by-one error when calculating how many descriptors are
1335 * done in the credits_update function.
1336 */
1337 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1338 }
1339
1340 /* Setup VLAN support, basic and offload if available */
1341 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1342
1343 /* Clear bad data from Rx FIFOs */
1344 if (sc->hw.mac.type >= igb_mac_min)
1345 e1000_rx_fifo_flush_base(&sc->hw);
1346
1347 /* Configure for OS presence */
1348 em_init_manageability(sc);
1349
1350 /* Prepare transmit descriptors and buffers */
1351 em_initialize_transmit_unit(ctx);
1352
1353 /* Setup Multicast table */
1354 em_if_multi_set(ctx);
1355
1356 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1357 em_initialize_receive_unit(ctx);
1358
1359 /* Set up VLAN support and filter */
1360 em_setup_vlan_hw_support(ctx);
1361
1362 /* Don't lose promiscuous settings */
1363 em_if_set_promisc(ctx, if_getflags(ifp));
1364 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1365
1366 /* MSI-X configuration for 82574 */
1367 if (sc->hw.mac.type == e1000_82574) {
1368 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1369
1370 tmp |= E1000_CTRL_EXT_PBA_CLR;
1371 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1372 /* Set the IVAR - interrupt vector routing. */
1373 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
1374 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1375 igb_configure_queues(sc);
1376
1377 /* this clears any pending interrupts */
1378 E1000_READ_REG(&sc->hw, E1000_ICR);
1379 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1380
1381 /* AMT based hardware can now take control from firmware */
1382 if (sc->has_manage && sc->has_amt)
1383 em_get_hw_control(sc);
1384
1385 /* Set Energy Efficient Ethernet */
1386 if (sc->hw.mac.type >= igb_mac_min &&
1387 sc->hw.phy.media_type == e1000_media_type_copper) {
1388 if (sc->hw.mac.type == e1000_i354)
1389 e1000_set_eee_i354(&sc->hw, true, true);
1390 else
1391 e1000_set_eee_i350(&sc->hw, true, true);
1392 }
1393}
1394
1395/*********************************************************************
1396 *
1397 * Fast Legacy/MSI Combined Interrupt Service routine
1398 *
1399 *********************************************************************/
1400int
1401em_intr(void *arg)
1402{
1403 struct e1000_softc *sc = arg;
1404 if_ctx_t ctx = sc->ctx;
1405 u32 reg_icr;
1406
1407 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1408
1409 /* Hot eject? */
1410 if (reg_icr == 0xffffffff)
1411 return FILTER_STRAY;
1412
1413 /* Definitely not our interrupt. */
1414 if (reg_icr == 0x0)
1415 return FILTER_STRAY;
1416
1417 /*
1418 * Starting with the 82571 chip, bit 31 should be used to
1419 * determine whether the interrupt belongs to us.
1420 */
1421 if (sc->hw.mac.type >= e1000_82571 &&
1422 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1423 return FILTER_STRAY;
1424
1425 /*
1426 * Only MSI-X interrupts have one-shot behavior by taking advantage
1427 * of the EIAC register. Thus, explicitly disable interrupts. This
1428 * also works around the MSI message reordering errata on certain
1429 * systems.
1430 */
1431 IFDI_INTR_DISABLE(ctx);
1432
1433 /* Link status change */
1434 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1435 em_handle_link(ctx);
1436
1437 if (reg_icr & E1000_ICR_RXO)
1438 sc->rx_overruns++;
1439
1440 return (FILTER_SCHEDULE_THREAD);
1441}
1442
1443static int
1444em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1445{
1446 struct e1000_softc *sc = iflib_get_softc(ctx);
1447 struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1448
1449 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims);
1450 return (0);
1451}
1452
1453static int
1454em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1455{
1456 struct e1000_softc *sc = iflib_get_softc(ctx);
1457 struct em_tx_queue *txq = &sc->tx_queues[txqid];
1458
1459 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims);
1460 return (0);
1461}
1462
1463static int
1464igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1465{
1466 struct e1000_softc *sc = iflib_get_softc(ctx);
1467 struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1468
1469 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims);
1470 return (0);
1471}
1472
1473static int
1474igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1475{
1476 struct e1000_softc *sc = iflib_get_softc(ctx);
1477 struct em_tx_queue *txq = &sc->tx_queues[txqid];
1478
1479 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims);
1480 return (0);
1481}
1482
1483/*********************************************************************
1484 *
1485 * MSI-X RX Interrupt Service routine
1486 *
1487 **********************************************************************/
1488static int
1489em_msix_que(void *arg)
1490{
1491 struct em_rx_queue *que = arg;
1492
1493 ++que->irqs;
1494
1495 return (FILTER_SCHEDULE_THREAD);
1496}
1497
1498/*********************************************************************
1499 *
1500 * MSI-X Link Fast Interrupt Service routine
1501 *
1502 **********************************************************************/
1503static int
1504em_msix_link(void *arg)
1505{
1506 struct e1000_softc *sc = arg;
1507 u32 reg_icr;
1508
1509 ++sc->link_irq;
1510 MPASS(sc->hw.back != NULL);
1511 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1512
1513 if (reg_icr & E1000_ICR_RXO)
1514 sc->rx_overruns++;
1515
1516 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1517 em_handle_link(sc->ctx);
1518
1519 /* Re-arm unconditionally */
1520 if (sc->hw.mac.type >= igb_mac_min) {
1521 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1522 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
1523 } else if (sc->hw.mac.type == e1000_82574) {
1524 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
1525 E1000_IMS_OTHER);
1526 /*
1527 * Because we must read the ICR for this interrupt it may
1528 * clear other causes using autoclear, for this reason we
1529 * simply create a soft interrupt for all these vectors.
1530 */
1531 if (reg_icr)
1532 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims);
1533 } else
1534 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1535
1536 return (FILTER_HANDLED);
1537}
1538
1539static void
1540em_handle_link(void *context)
1541{
1542 if_ctx_t ctx = context;
1543 struct e1000_softc *sc = iflib_get_softc(ctx);
1544
1545 sc->hw.mac.get_link_status = 1;
1546 iflib_admin_intr_deferred(ctx);
1547}
1548
1549/*********************************************************************
1550 *
1551 * Media Ioctl callback
1552 *
1553 * This routine is called whenever the user queries the status of
1554 * the interface using ifconfig.
1555 *
1556 **********************************************************************/
1557static void
1558em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1559{
1560 struct e1000_softc *sc = iflib_get_softc(ctx);
1561 u_char fiber_type = IFM_1000_SX;
1562
1563 INIT_DEBUGOUT("em_if_media_status: begin");
1564
1565 iflib_admin_intr_deferred(ctx);
1566
1567 ifmr->ifm_status = IFM_AVALID;
1568 ifmr->ifm_active = IFM_ETHER;
1569
1570 if (!sc->link_active) {
1571 return;
1572 }
1573
1574 ifmr->ifm_status |= IFM_ACTIVE;
1575
1576 if ((sc->hw.phy.media_type == e1000_media_type_fiber) ||
1577 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1578 if (sc->hw.mac.type == e1000_82545)
1579 fiber_type = IFM_1000_LX;
1580 ifmr->ifm_active |= fiber_type | IFM_FDX;
1581 } else {
1582 switch (sc->link_speed) {
1583 case 10:
1584 ifmr->ifm_active |= IFM_10_T;
1585 break;
1586 case 100:
1587 ifmr->ifm_active |= IFM_100_TX;
1588 break;
1589 case 1000:
1590 ifmr->ifm_active |= IFM_1000_T;
1591 break;
1592 }
1593 if (sc->link_duplex == FULL_DUPLEX)
1594 ifmr->ifm_active |= IFM_FDX;
1595 else
1596 ifmr->ifm_active |= IFM_HDX;
1597 }
1598}
1599
1600/*********************************************************************
1601 *
1602 * Media Ioctl callback
1603 *
1604 * This routine is called when the user changes speed/duplex using
1605 * media/mediopt option with ifconfig.
1606 *
1607 **********************************************************************/
1608static int
1609em_if_media_change(if_ctx_t ctx)
1610{
1611 struct e1000_softc *sc = iflib_get_softc(ctx);
1612 struct ifmedia *ifm = iflib_get_media(ctx);
1613
1614 INIT_DEBUGOUT("em_if_media_change: begin");
1615
1616 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1617 return (EINVAL);
1618
1619 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1620 case IFM_AUTO:
1621 sc->hw.mac.autoneg = DO_AUTO_NEG;
1622 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1623 break;
1624 case IFM_1000_LX:
1625 case IFM_1000_SX:
1626 case IFM_1000_T:
1627 sc->hw.mac.autoneg = DO_AUTO_NEG;
1628 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1629 break;
1630 case IFM_100_TX:
1631 sc->hw.mac.autoneg = false;
1632 sc->hw.phy.autoneg_advertised = 0;
1633 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1634 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1635 else
1636 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1637 break;
1638 case IFM_10_T:
1639 sc->hw.mac.autoneg = false;
1640 sc->hw.phy.autoneg_advertised = 0;
1641 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1642 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1643 else
1644 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1645 break;
1646 default:
1647 device_printf(sc->dev, "Unsupported media type\n");
1648 }
1649
1650 em_if_init(ctx);
1651
1652 return (0);
1653}
1654
1655static int
1656em_if_set_promisc(if_ctx_t ctx, int flags)
1657{
1658 struct e1000_softc *sc = iflib_get_softc(ctx);
1659 struct ifnet *ifp = iflib_get_ifp(ctx);
1660 u32 reg_rctl;
1661 int mcnt = 0;
1662
1663 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1664 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1665 if (flags & IFF_ALLMULTI)
1666 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1667 else
1668 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1669
1670 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1671 reg_rctl &= (~E1000_RCTL_MPE);
1672 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1673
1674 if (flags & IFF_PROMISC) {
1675 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1676 em_if_vlan_filter_disable(sc);
1677 /* Turn this on if you want to see bad packets */
1678 if (em_debug_sbp)
1679 reg_rctl |= E1000_RCTL_SBP;
1680 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1681 } else {
1682 if (flags & IFF_ALLMULTI) {
1683 reg_rctl |= E1000_RCTL_MPE;
1684 reg_rctl &= ~E1000_RCTL_UPE;
1685 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1686 }
1687 if (em_if_vlan_filter_used(ctx))
1688 em_if_vlan_filter_enable(sc);
1689 }
1690 return (0);
1691}
1692
1693static u_int
1694em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1695{
1696 u8 *mta = arg;
1697
1698 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1699 return (0);
1700
1701 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1702
1703 return (1);
1704}
1705
1706/*********************************************************************
1707 * Multicast Update
1708 *
1709 * This routine is called whenever multicast address list is updated.
1710 *
1711 **********************************************************************/
1712static void
1713em_if_multi_set(if_ctx_t ctx)
1714{
1715 struct e1000_softc *sc = iflib_get_softc(ctx);
1716 struct ifnet *ifp = iflib_get_ifp(ctx);
1717 u8 *mta; /* Multicast array memory */
1718 u32 reg_rctl = 0;
1719 int mcnt = 0;
1720
1721 IOCTL_DEBUGOUT("em_set_multi: begin");
1722
1723 mta = sc->mta;
1724 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1725
1726 if (sc->hw.mac.type == e1000_82542 &&
1727 sc->hw.revision_id == E1000_REVISION_2) {
1728 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1729 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1730 e1000_pci_clear_mwi(&sc->hw);
1731 reg_rctl |= E1000_RCTL_RST;
1732 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1733 msec_delay(5);
1734 }
1735
1736 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1737
1738 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1739
1740 if (if_getflags(ifp) & IFF_PROMISC)
1741 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1742 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1743 if_getflags(ifp) & IFF_ALLMULTI) {
1744 reg_rctl |= E1000_RCTL_MPE;
1745 reg_rctl &= ~E1000_RCTL_UPE;
1746 } else
1747 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1748
1749 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1750
1751 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1752 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1753
1754 if (sc->hw.mac.type == e1000_82542 &&
1755 sc->hw.revision_id == E1000_REVISION_2) {
1756 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1757 reg_rctl &= ~E1000_RCTL_RST;
1758 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1759 msec_delay(5);
1760 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1761 e1000_pci_set_mwi(&sc->hw);
1762 }
1763}
1764
1765/*********************************************************************
1766 * Timer routine
1767 *
1768 * This routine schedules em_if_update_admin_status() to check for
1769 * link status and to gather statistics as well as to perform some
1770 * controller-specific hardware patting.
1771 *
1772 **********************************************************************/
1773static void
1774em_if_timer(if_ctx_t ctx, uint16_t qid)
1775{
1776
1777 if (qid != 0)
1778 return;
1779
1780 iflib_admin_intr_deferred(ctx);
1781}
1782
1783static void
1784em_if_update_admin_status(if_ctx_t ctx)
1785{
1786 struct e1000_softc *sc = iflib_get_softc(ctx);
1787 struct e1000_hw *hw = &sc->hw;
1788 device_t dev = iflib_get_dev(ctx);
1789 u32 link_check, thstat, ctrl;
1790
1791 link_check = thstat = ctrl = 0;
1792 /* Get the cached link value or read phy for real */
1793 switch (hw->phy.media_type) {
1794 case e1000_media_type_copper:
1795 if (hw->mac.get_link_status) {
1796 if (hw->mac.type == e1000_pch_spt)
1797 msec_delay(50);
1798 /* Do the work to read phy */
1799 e1000_check_for_link(hw);
1800 link_check = !hw->mac.get_link_status;
1801 if (link_check) /* ESB2 fix */
1802 e1000_cfg_on_link_up(hw);
1803 } else {
1804 link_check = true;
1805 }
1806 break;
1807 case e1000_media_type_fiber:
1808 e1000_check_for_link(hw);
1809 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1810 E1000_STATUS_LU);
1811 break;
1812 case e1000_media_type_internal_serdes:
1813 e1000_check_for_link(hw);
1814 link_check = hw->mac.serdes_has_link;
1815 break;
1816 /* VF device is type_unknown */
1817 case e1000_media_type_unknown:
1818 e1000_check_for_link(hw);
1819 link_check = !hw->mac.get_link_status;
1820 /* FALLTHROUGH */
1821 default:
1822 break;
1823 }
1824
1825 /* Check for thermal downshift or shutdown */
1826 if (hw->mac.type == e1000_i350) {
1827 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1828 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1829 }
1830
1831 /* Now check for a transition */
1832 if (link_check && (sc->link_active == 0)) {
1833 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1834 &sc->link_duplex);
1835 /* Check if we must disable SPEED_MODE bit on PCI-E */
1836 if ((sc->link_speed != SPEED_1000) &&
1837 ((hw->mac.type == e1000_82571) ||
1838 (hw->mac.type == e1000_82572))) {
1839 int tarc0;
1840 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1841 tarc0 &= ~TARC_SPEED_MODE_BIT;
1842 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1843 }
1844 if (bootverbose)
1845 device_printf(dev, "Link is up %d Mbps %s\n",
1846 sc->link_speed,
1847 ((sc->link_duplex == FULL_DUPLEX) ?
1848 "Full Duplex" : "Half Duplex"));
1849 sc->link_active = 1;
1850 sc->smartspeed = 0;
1851 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1852 E1000_CTRL_EXT_LINK_MODE_GMII &&
1853 (thstat & E1000_THSTAT_LINK_THROTTLE))
1854 device_printf(dev, "Link: thermal downshift\n");
1855 /* Delay Link Up for Phy update */
1856 if (((hw->mac.type == e1000_i210) ||
1857 (hw->mac.type == e1000_i211)) &&
1858 (hw->phy.id == I210_I_PHY_ID))
1859 msec_delay(I210_LINK_DELAY);
1860 /* Reset if the media type changed. */
1861 if (hw->dev_spec._82575.media_changed &&
1862 hw->mac.type >= igb_mac_min) {
1863 hw->dev_spec._82575.media_changed = false;
1864 sc->flags |= IGB_MEDIA_RESET;
1865 em_reset(ctx);
1866 }
1867 iflib_link_state_change(ctx, LINK_STATE_UP,
1868 IF_Mbps(sc->link_speed));
1869 } else if (!link_check && (sc->link_active == 1)) {
1870 sc->link_speed = 0;
1871 sc->link_duplex = 0;
1872 sc->link_active = 0;
1873 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1874 }
1875 em_update_stats_counters(sc);
1876
1877 /* Reset LAA into RAR[0] on 82571 */
1878 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1879 e1000_rar_set(hw, hw->mac.addr, 0);
1880
1881 if (hw->mac.type < em_mac_min)
1882 lem_smartspeed(sc);
1883}
1884
1885static void
1886em_if_watchdog_reset(if_ctx_t ctx)
1887{
1888 struct e1000_softc *sc = iflib_get_softc(ctx);
1889
1890 /*
1891 * Just count the event; iflib(4) will already trigger a
1892 * sufficient reset of the controller.
1893 */
1894 sc->watchdog_events++;
1895}
1896
1897/*********************************************************************
1898 *
1899 * This routine disables all traffic on the adapter by issuing a
1900 * global reset on the MAC.
1901 *
1902 **********************************************************************/
1903static void
1904em_if_stop(if_ctx_t ctx)
1905{
1906 struct e1000_softc *sc = iflib_get_softc(ctx);
1907
1908 INIT_DEBUGOUT("em_if_stop: begin");
1909
1910 e1000_reset_hw(&sc->hw);
1911 if (sc->hw.mac.type >= e1000_82544)
1912 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0);
1913
1914 e1000_led_off(&sc->hw);
1915 e1000_cleanup_led(&sc->hw);
1916}
1917
1918/*********************************************************************
1919 *
1920 * Determine hardware revision.
1921 *
1922 **********************************************************************/
1923static void
1924em_identify_hardware(if_ctx_t ctx)
1925{
1926 device_t dev = iflib_get_dev(ctx);
1927 struct e1000_softc *sc = iflib_get_softc(ctx);
1928
1929 /* Make sure our PCI config space has the necessary stuff set */
1930 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1931
1932 /* Save off the information about this board */
1933 sc->hw.vendor_id = pci_get_vendor(dev);
1934 sc->hw.device_id = pci_get_device(dev);
1935 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1936 sc->hw.subsystem_vendor_id =
1937 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1938 sc->hw.subsystem_device_id =
1939 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1940
1941 /* Do Shared Code Init and Setup */
1942 if (e1000_set_mac_type(&sc->hw)) {
1943 device_printf(dev, "Setup init failure\n");
1944 return;
1945 }
1946
1947 /* Are we a VF device? */
1948 if ((sc->hw.mac.type == e1000_vfadapt) ||
1949 (sc->hw.mac.type == e1000_vfadapt_i350))
1950 sc->vf_ifp = 1;
1951 else
1952 sc->vf_ifp = 0;
1953}
1954
1955static int
1956em_allocate_pci_resources(if_ctx_t ctx)
1957{
1958 struct e1000_softc *sc = iflib_get_softc(ctx);
1959 device_t dev = iflib_get_dev(ctx);
1960 int rid, val;
1961
1962 rid = PCIR_BAR(0);
1963 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1964 &rid, RF_ACTIVE);
1965 if (sc->memory == NULL) {
1966 device_printf(dev, "Unable to allocate bus resource: memory\n");
1967 return (ENXIO);
1968 }
1969 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
1970 sc->osdep.mem_bus_space_handle =
1971 rman_get_bushandle(sc->memory);
1972 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
1973
1974 /* Only older adapters use IO mapping */
1975 if (sc->hw.mac.type < em_mac_min &&
1976 sc->hw.mac.type > e1000_82543) {
1977 /* Figure our where our IO BAR is ? */
1978 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1979 val = pci_read_config(dev, rid, 4);
1980 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1981 break;
1982 }
1983 rid += 4;
1984 /* check for 64bit BAR */
1985 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1986 rid += 4;
1987 }
1988 if (rid >= PCIR_CIS) {
1989 device_printf(dev, "Unable to locate IO BAR\n");
1990 return (ENXIO);
1991 }
1992 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1993 &rid, RF_ACTIVE);
1994 if (sc->ioport == NULL) {
1995 device_printf(dev, "Unable to allocate bus resource: "
1996 "ioport\n");
1997 return (ENXIO);
1998 }
1999 sc->hw.io_base = 0;
2000 sc->osdep.io_bus_space_tag =
2001 rman_get_bustag(sc->ioport);
2002 sc->osdep.io_bus_space_handle =
2003 rman_get_bushandle(sc->ioport);
2004 }
2005
2006 sc->hw.back = &sc->osdep;
2007
2008 return (0);
2009}
2010
2011/*********************************************************************
2012 *
2013 * Set up the MSI-X Interrupt handlers
2014 *
2015 **********************************************************************/
2016static int
2017em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2018{
2019 struct e1000_softc *sc = iflib_get_softc(ctx);
2020 struct em_rx_queue *rx_que = sc->rx_queues;
2021 struct em_tx_queue *tx_que = sc->tx_queues;
2022 int error, rid, i, vector = 0, rx_vectors;
2023 char buf[16];
2024
2025 /* First set up ring resources */
2026 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
2027 rid = vector + 1;
2028 snprintf(buf, sizeof(buf), "rxq%d", i);
2029 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2030 if (error) {
2031 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2032 sc->rx_num_queues = i + 1;
2033 goto fail;
2034 }
2035
2036 rx_que->msix = vector;
2037
2038 /*
2039 * Set the bit to enable interrupt
2040 * in E1000_IMS -- bits 20 and 21
2041 * are for RX0 and RX1, note this has
2042 * NOTHING to do with the MSI-X vector
2043 */
2044 if (sc->hw.mac.type == e1000_82574) {
2045 rx_que->eims = 1 << (20 + i);
2046 sc->ims |= rx_que->eims;
2047 sc->ivars |= (8 | rx_que->msix) << (i * 4);
2048 } else if (sc->hw.mac.type == e1000_82575)
2049 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2050 else
2051 rx_que->eims = 1 << vector;
2052 }
2053 rx_vectors = vector;
2054
2055 vector = 0;
2056 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
2057 snprintf(buf, sizeof(buf), "txq%d", i);
2058 tx_que = &sc->tx_queues[i];
2059 iflib_softirq_alloc_generic(ctx,
2060 &sc->rx_queues[i % sc->rx_num_queues].que_irq,
2061 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2062
2063 tx_que->msix = (vector % sc->rx_num_queues);
2064
2065 /*
2066 * Set the bit to enable interrupt
2067 * in E1000_IMS -- bits 22 and 23
2068 * are for TX0 and TX1, note this has
2069 * NOTHING to do with the MSI-X vector
2070 */
2071 if (sc->hw.mac.type == e1000_82574) {
2072 tx_que->eims = 1 << (22 + i);
2073 sc->ims |= tx_que->eims;
2074 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2075 } else if (sc->hw.mac.type == e1000_82575) {
2076 tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2077 } else {
2078 tx_que->eims = 1 << i;
2079 }
2080 }
2081
2082 /* Link interrupt */
2083 rid = rx_vectors + 1;
2084 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq");
2085
2086 if (error) {
2087 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2088 goto fail;
2089 }
2090 sc->linkvec = rx_vectors;
2091 if (sc->hw.mac.type < igb_mac_min) {
2092 sc->ivars |= (8 | rx_vectors) << 16;
2093 sc->ivars |= 0x80000000;
2094 /* Enable the "Other" interrupt type for link status change */
2095 sc->ims |= E1000_IMS_OTHER;
2096 }
2097
2098 return (0);
2099fail:
2100 iflib_irq_free(ctx, &sc->irq);
2101 rx_que = sc->rx_queues;
2102 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
2103 iflib_irq_free(ctx, &rx_que->que_irq);
2104 return (error);
2105}
2106
2107static void
2108igb_configure_queues(struct e1000_softc *sc)
2109{
2110 struct e1000_hw *hw = &sc->hw;
2111 struct em_rx_queue *rx_que;
2112 struct em_tx_queue *tx_que;
2113 u32 tmp, ivar = 0, newitr = 0;
2114
2115 /* First turn on RSS capability */
2116 if (hw->mac.type != e1000_82575)
2117 E1000_WRITE_REG(hw, E1000_GPIE,
2118 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2119 E1000_GPIE_PBA | E1000_GPIE_NSICR);
2120
2121 /* Turn on MSI-X */
2122 switch (hw->mac.type) {
2123 case e1000_82580:
2124 case e1000_i350:
2125 case e1000_i354:
2126 case e1000_i210:
2127 case e1000_i211:
2128 case e1000_vfadapt:
2129 case e1000_vfadapt_i350:
2130 /* RX entries */
2131 for (int i = 0; i < sc->rx_num_queues; i++) {
2132 u32 index = i >> 1;
2133 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2134 rx_que = &sc->rx_queues[i];
2135 if (i & 1) {
2136 ivar &= 0xFF00FFFF;
2137 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2138 } else {
2139 ivar &= 0xFFFFFF00;
2140 ivar |= rx_que->msix | E1000_IVAR_VALID;
2141 }
2142 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2143 }
2144 /* TX entries */
2145 for (int i = 0; i < sc->tx_num_queues; i++) {
2146 u32 index = i >> 1;
2147 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2148 tx_que = &sc->tx_queues[i];
2149 if (i & 1) {
2150 ivar &= 0x00FFFFFF;
2151 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2152 } else {
2153 ivar &= 0xFFFF00FF;
2154 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2155 }
2156 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2157 sc->que_mask |= tx_que->eims;
2158 }
2159
2160 /* And for the link interrupt */
2161 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2162 sc->link_mask = 1 << sc->linkvec;
2163 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2164 break;
2165 case e1000_82576:
2166 /* RX entries */
2167 for (int i = 0; i < sc->rx_num_queues; i++) {
2168 u32 index = i & 0x7; /* Each IVAR has two entries */
2169 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2170 rx_que = &sc->rx_queues[i];
2171 if (i < 8) {
2172 ivar &= 0xFFFFFF00;
2173 ivar |= rx_que->msix | E1000_IVAR_VALID;
2174 } else {
2175 ivar &= 0xFF00FFFF;
2176 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2177 }
2178 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2179 sc->que_mask |= rx_que->eims;
2180 }
2181 /* TX entries */
2182 for (int i = 0; i < sc->tx_num_queues; i++) {
2183 u32 index = i & 0x7; /* Each IVAR has two entries */
2184 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2185 tx_que = &sc->tx_queues[i];
2186 if (i < 8) {
2187 ivar &= 0xFFFF00FF;
2188 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2189 } else {
2190 ivar &= 0x00FFFFFF;
2191 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2192 }
2193 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2194 sc->que_mask |= tx_que->eims;
2195 }
2196
2197 /* And for the link interrupt */
2198 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2199 sc->link_mask = 1 << sc->linkvec;
2200 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2201 break;
2202
2203 case e1000_82575:
2204 /* enable MSI-X support*/
2205 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2206 tmp |= E1000_CTRL_EXT_PBA_CLR;
2207 /* Auto-Mask interrupts upon ICR read. */
2208 tmp |= E1000_CTRL_EXT_EIAME;
2209 tmp |= E1000_CTRL_EXT_IRCA;
2210 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2211
2212 /* Queues */
2213 for (int i = 0; i < sc->rx_num_queues; i++) {
2214 rx_que = &sc->rx_queues[i];
2215 tmp = E1000_EICR_RX_QUEUE0 << i;
2216 tmp |= E1000_EICR_TX_QUEUE0 << i;
2217 rx_que->eims = tmp;
2218 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2219 i, rx_que->eims);
2220 sc->que_mask |= rx_que->eims;
2221 }
2222
2223 /* Link */
2224 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec),
2225 E1000_EIMS_OTHER);
2226 sc->link_mask |= E1000_EIMS_OTHER;
2227 default:
2228 break;
2229 }
2230
2231 /* Set the starting interrupt rate */
2232 if (em_max_interrupt_rate > 0)
2233 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2234
2235 if (hw->mac.type == e1000_82575)
2236 newitr |= newitr << 16;
2237 else
2238 newitr |= E1000_EITR_CNT_IGNR;
2239
2240 for (int i = 0; i < sc->rx_num_queues; i++) {
2241 rx_que = &sc->rx_queues[i];
2242 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2243 }
2244
2245 return;
2246}
2247
2248static void
2249em_free_pci_resources(if_ctx_t ctx)
2250{
2251 struct e1000_softc *sc = iflib_get_softc(ctx);
2252 struct em_rx_queue *que = sc->rx_queues;
2253 device_t dev = iflib_get_dev(ctx);
2254
2255 /* Release all MSI-X queue resources */
2256 if (sc->intr_type == IFLIB_INTR_MSIX)
2257 iflib_irq_free(ctx, &sc->irq);
2258
2259 if (que != NULL) {
2260 for (int i = 0; i < sc->rx_num_queues; i++, que++) {
2261 iflib_irq_free(ctx, &que->que_irq);
2262 }
2263 }
2264
2265 if (sc->memory != NULL) {
2266 bus_release_resource(dev, SYS_RES_MEMORY,
2267 rman_get_rid(sc->memory), sc->memory);
2268 sc->memory = NULL;
2269 }
2270
2271 if (sc->flash != NULL) {
2272 bus_release_resource(dev, SYS_RES_MEMORY,
2273 rman_get_rid(sc->flash), sc->flash);
2274 sc->flash = NULL;
2275 }
2276
2277 if (sc->ioport != NULL) {
2278 bus_release_resource(dev, SYS_RES_IOPORT,
2279 rman_get_rid(sc->ioport), sc->ioport);
2280 sc->ioport = NULL;
2281 }
2282}
2283
2284/* Set up MSI or MSI-X */
2285static int
2286em_setup_msix(if_ctx_t ctx)
2287{
2288 struct e1000_softc *sc = iflib_get_softc(ctx);
2289
2290 if (sc->hw.mac.type == e1000_82574) {
2291 em_enable_vectors_82574(ctx);
2292 }
2293 return (0);
2294}
2295
2296/*********************************************************************
2297 *
2298 * Workaround for SmartSpeed on 82541 and 82547 controllers
2299 *
2300 **********************************************************************/
2301static void
2302lem_smartspeed(struct e1000_softc *sc)
2303{
2304 u16 phy_tmp;
2305
2306 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) ||
2307 sc->hw.mac.autoneg == 0 ||
2308 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2309 return;
2310
2311 if (sc->smartspeed == 0) {
2312 /* If Master/Slave config fault is asserted twice,
2313 * we assume back-to-back */
2314 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2315 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2316 return;
2317 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2318 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2319 e1000_read_phy_reg(&sc->hw,
2320 PHY_1000T_CTRL, &phy_tmp);
2321 if(phy_tmp & CR_1000T_MS_ENABLE) {
2322 phy_tmp &= ~CR_1000T_MS_ENABLE;
2323 e1000_write_phy_reg(&sc->hw,
2324 PHY_1000T_CTRL, phy_tmp);
2325 sc->smartspeed++;
2326 if(sc->hw.mac.autoneg &&
2327 !e1000_copper_link_autoneg(&sc->hw) &&
2328 !e1000_read_phy_reg(&sc->hw,
2329 PHY_CONTROL, &phy_tmp)) {
2330 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2331 MII_CR_RESTART_AUTO_NEG);
2332 e1000_write_phy_reg(&sc->hw,
2333 PHY_CONTROL, phy_tmp);
2334 }
2335 }
2336 }
2337 return;
2338 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2339 /* If still no link, perhaps using 2/3 pair cable */
2340 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2341 phy_tmp |= CR_1000T_MS_ENABLE;
2342 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2343 if(sc->hw.mac.autoneg &&
2344 !e1000_copper_link_autoneg(&sc->hw) &&
2345 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2346 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2347 MII_CR_RESTART_AUTO_NEG);
2348 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2349 }
2350 }
2351 /* Restart process after EM_SMARTSPEED_MAX iterations */
2352 if(sc->smartspeed++ == EM_SMARTSPEED_MAX)
2353 sc->smartspeed = 0;
2354}
2355
2356/*********************************************************************
2357 *
2358 * Initialize the DMA Coalescing feature
2359 *
2360 **********************************************************************/
2361static void
2362igb_init_dmac(struct e1000_softc *sc, u32 pba)
2363{
2364 device_t dev = sc->dev;
2365 struct e1000_hw *hw = &sc->hw;
2366 u32 dmac, reg = ~E1000_DMACR_DMAC_EN;
2367 u16 hwm;
2368 u16 max_frame_size;
2369
2370 if (hw->mac.type == e1000_i211)
2371 return;
2372
2373 max_frame_size = sc->shared->isc_max_frame_size;
2374 if (hw->mac.type > e1000_82580) {
2375
2376 if (sc->dmac == 0) { /* Disabling it */
2377 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2378 return;
2379 } else
2380 device_printf(dev, "DMA Coalescing enabled\n");
2381
2382 /* Set starting threshold */
2383 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2384
2385 hwm = 64 * pba - max_frame_size / 16;
2386 if (hwm < 64 * (pba - 6))
2387 hwm = 64 * (pba - 6);
2388 reg = E1000_READ_REG(hw, E1000_FCRTC);
2389 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2390 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2391 & E1000_FCRTC_RTH_COAL_MASK);
2392 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2393
2394
2395 dmac = pba - max_frame_size / 512;
2396 if (dmac < pba - 10)
2397 dmac = pba - 10;
2398 reg = E1000_READ_REG(hw, E1000_DMACR);
2399 reg &= ~E1000_DMACR_DMACTHR_MASK;
2400 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2401 & E1000_DMACR_DMACTHR_MASK);
2402
2403 /* transition to L0x or L1 if available..*/
2404 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2405
2406 /* Check if status is 2.5Gb backplane connection
2407 * before configuration of watchdog timer, which is
2408 * in msec values in 12.8usec intervals
2409 * watchdog timer= msec values in 32usec intervals
2410 * for non 2.5Gb connection
2411 */
2412 if (hw->mac.type == e1000_i354) {
2413 int status = E1000_READ_REG(hw, E1000_STATUS);
2414 if ((status & E1000_STATUS_2P5_SKU) &&
2415 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2416 reg |= ((sc->dmac * 5) >> 6);
2417 else
2418 reg |= (sc->dmac >> 5);
2419 } else {
2420 reg |= (sc->dmac >> 5);
2421 }
2422
2423 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2424
2425 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2426
2427 /* Set the interval before transition */
2428 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2429 if (hw->mac.type == e1000_i350)
2430 reg |= IGB_DMCTLX_DCFLUSH_DIS;
2431 /*
2432 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2433 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2434 */
2435 if (hw->mac.type == e1000_i354) {
2436 int status = E1000_READ_REG(hw, E1000_STATUS);
2437 if ((status & E1000_STATUS_2P5_SKU) &&
2438 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2439 reg |= 0xA;
2440 else
2441 reg |= 0x4;
2442 } else {
2443 reg |= 0x4;
2444 }
2445
2446 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2447
2448 /* free space in tx packet buffer to wake from DMA coal */
2449 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2450 (2 * max_frame_size)) >> 6);
2451
2452 /* make low power state decision controlled by DMA coal */
2453 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2454 reg &= ~E1000_PCIEMISC_LX_DECISION;
2455 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2456
2457 } else if (hw->mac.type == e1000_82580) {
2458 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2459 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2460 reg & ~E1000_PCIEMISC_LX_DECISION);
2461 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2462 }
2463}
2464
2465/*********************************************************************
2466 *
2467 * Initialize the hardware to a configuration as specified by the
2468 * sc structure.
2469 *
2470 **********************************************************************/
2471static void
2472em_reset(if_ctx_t ctx)
2473{
2474 device_t dev = iflib_get_dev(ctx);
2475 struct e1000_softc *sc = iflib_get_softc(ctx);
2476 struct ifnet *ifp = iflib_get_ifp(ctx);
2477 struct e1000_hw *hw = &sc->hw;
2478 u16 rx_buffer_size;
2479 u32 pba;
2480
2481 INIT_DEBUGOUT("em_reset: begin");
2482 /* Let the firmware know the OS is in control */
2483 em_get_hw_control(sc);
2484
2485 /* Set up smart power down as default off on newer adapters. */
2486 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2487 hw->mac.type == e1000_82572)) {
2488 u16 phy_tmp = 0;
2489
2490 /* Speed up time to link by disabling smart power down. */
2491 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2492 phy_tmp &= ~IGP02E1000_PM_SPD;
2493 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2494 }
2495
2496 /*
2497 * Packet Buffer Allocation (PBA)
2498 * Writing PBA sets the receive portion of the buffer
2499 * the remainder is used for the transmit buffer.
2500 */
2501 switch (hw->mac.type) {
2502 /* 82547: Total Packet Buffer is 40K */
2503 case e1000_82547:
2504 case e1000_82547_rev_2:
2505 if (hw->mac.max_frame_size > 8192)
2506 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2507 else
2508 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2509 break;
2510 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2511 case e1000_82571:
2512 case e1000_82572:
2513 case e1000_80003es2lan:
2514 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2515 break;
2516 /* 82573: Total Packet Buffer is 32K */
2517 case e1000_82573:
2518 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2519 break;
2520 case e1000_82574:
2521 case e1000_82583:
2522 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2523 break;
2524 case e1000_ich8lan:
2525 pba = E1000_PBA_8K;
2526 break;
2527 case e1000_ich9lan:
2528 case e1000_ich10lan:
2529 /* Boost Receive side for jumbo frames */
2530 if (hw->mac.max_frame_size > 4096)
2531 pba = E1000_PBA_14K;
2532 else
2533 pba = E1000_PBA_10K;
2534 break;
2535 case e1000_pchlan:
2536 case e1000_pch2lan:
2537 case e1000_pch_lpt:
2538 case e1000_pch_spt:
2539 case e1000_pch_cnp:
2540 case e1000_pch_tgp:
2541 case e1000_pch_adp:
2542 case e1000_pch_mtp:
2543 pba = E1000_PBA_26K;
2544 break;
2545 case e1000_82575:
2546 pba = E1000_PBA_32K;
2547 break;
2548 case e1000_82576:
2549 case e1000_vfadapt:
2550 pba = E1000_READ_REG(hw, E1000_RXPBS);
2551 pba &= E1000_RXPBS_SIZE_MASK_82576;
2552 break;
2553 case e1000_82580:
2554 case e1000_i350:
2555 case e1000_i354:
2556 case e1000_vfadapt_i350:
2557 pba = E1000_READ_REG(hw, E1000_RXPBS);
2558 pba = e1000_rxpbs_adjust_82580(pba);
2559 break;
2560 case e1000_i210:
2561 case e1000_i211:
2562 pba = E1000_PBA_34K;
2563 break;
2564 default:
2565 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2566 if (hw->mac.max_frame_size > 8192)
2567 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2568 else
2569 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2570 }
2571
2572 /* Special needs in case of Jumbo frames */
2573 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2574 u32 tx_space, min_tx, min_rx;
2575 pba = E1000_READ_REG(hw, E1000_PBA);
2576 tx_space = pba >> 16;
2577 pba &= 0xffff;
2578 min_tx = (hw->mac.max_frame_size +
2579 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2580 min_tx = roundup2(min_tx, 1024);
2581 min_tx >>= 10;
2582 min_rx = hw->mac.max_frame_size;
2583 min_rx = roundup2(min_rx, 1024);
2584 min_rx >>= 10;
2585 if (tx_space < min_tx &&
2586 ((min_tx - tx_space) < pba)) {
2587 pba = pba - (min_tx - tx_space);
2588 /*
2589 * if short on rx space, rx wins
2590 * and must trump tx adjustment
2591 */
2592 if (pba < min_rx)
2593 pba = min_rx;
2594 }
2595 E1000_WRITE_REG(hw, E1000_PBA, pba);
2596 }
2597
2598 if (hw->mac.type < igb_mac_min)
2599 E1000_WRITE_REG(hw, E1000_PBA, pba);
2600
2601 INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2602
2603 /*
2604 * These parameters control the automatic generation (Tx) and
2605 * response (Rx) to Ethernet PAUSE frames.
2606 * - High water mark should allow for at least two frames to be
2607 * received after sending an XOFF.
2608 * - Low water mark works best when it is very near the high water mark.
2609 * This allows the receiver to restart by sending XON when it has
2610 * drained a bit. Here we use an arbitrary value of 1500 which will
2611 * restart after one full frame is pulled from the buffer. There
2612 * could be several smaller frames in the buffer and if so they will
2613 * not trigger the XON until their total number reduces the buffer
2614 * by 1500.
2615 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2616 */
2617 rx_buffer_size = (pba & 0xffff) << 10;
2618 hw->fc.high_water = rx_buffer_size -
2619 roundup2(hw->mac.max_frame_size, 1024);
2620 hw->fc.low_water = hw->fc.high_water - 1500;
2621
2622 if (sc->fc) /* locally set flow control value? */
2623 hw->fc.requested_mode = sc->fc;
2624 else
2625 hw->fc.requested_mode = e1000_fc_full;
2626
2627 if (hw->mac.type == e1000_80003es2lan)
2628 hw->fc.pause_time = 0xFFFF;
2629 else
2630 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2631
2632 hw->fc.send_xon = true;
2633
2634 /* Device specific overrides/settings */
2635 switch (hw->mac.type) {
2636 case e1000_pchlan:
2637 /* Workaround: no TX flow ctrl for PCH */
2638 hw->fc.requested_mode = e1000_fc_rx_pause;
2639 hw->fc.pause_time = 0xFFFF; /* override */
2640 if (if_getmtu(ifp) > ETHERMTU) {
2641 hw->fc.high_water = 0x3500;
2642 hw->fc.low_water = 0x1500;
2643 } else {
2644 hw->fc.high_water = 0x5000;
2645 hw->fc.low_water = 0x3000;
2646 }
2647 hw->fc.refresh_time = 0x1000;
2648 break;
2649 case e1000_pch2lan:
2650 case e1000_pch_lpt:
2651 case e1000_pch_spt:
2652 case e1000_pch_cnp:
2653 case e1000_pch_tgp:
2654 case e1000_pch_adp:
2655 case e1000_pch_mtp:
2656 hw->fc.high_water = 0x5C20;
2657 hw->fc.low_water = 0x5048;
2658 hw->fc.pause_time = 0x0650;
2659 hw->fc.refresh_time = 0x0400;
2660 /* Jumbos need adjusted PBA */
2661 if (if_getmtu(ifp) > ETHERMTU)
2662 E1000_WRITE_REG(hw, E1000_PBA, 12);
2663 else
2664 E1000_WRITE_REG(hw, E1000_PBA, 26);
2665 break;
2666 case e1000_82575:
2667 case e1000_82576:
2668 /* 8-byte granularity */
2669 hw->fc.low_water = hw->fc.high_water - 8;
2670 break;
2671 case e1000_82580:
2672 case e1000_i350:
2673 case e1000_i354:
2674 case e1000_i210:
2675 case e1000_i211:
2676 case e1000_vfadapt:
2677 case e1000_vfadapt_i350:
2678 /* 16-byte granularity */
2679 hw->fc.low_water = hw->fc.high_water - 16;
2680 break;
2681 case e1000_ich9lan:
2682 case e1000_ich10lan:
2683 if (if_getmtu(ifp) > ETHERMTU) {
2684 hw->fc.high_water = 0x2800;
2685 hw->fc.low_water = hw->fc.high_water - 8;
2686 break;
2687 }
2688 /* FALLTHROUGH */
2689 default:
2690 if (hw->mac.type == e1000_80003es2lan)
2691 hw->fc.pause_time = 0xFFFF;
2692 break;
2693 }
2694
2695 /* Issue a global reset */
2696 e1000_reset_hw(hw);
2697 if (hw->mac.type >= igb_mac_min) {
2698 E1000_WRITE_REG(hw, E1000_WUC, 0);
2699 } else {
2700 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2701 em_disable_aspm(sc);
2702 }
2703 if (sc->flags & IGB_MEDIA_RESET) {
2704 e1000_setup_init_funcs(hw, true);
2705 e1000_get_bus_info(hw);
2706 sc->flags &= ~IGB_MEDIA_RESET;
2707 }
2708 /* and a re-init */
2709 if (e1000_init_hw(hw) < 0) {
2710 device_printf(dev, "Hardware Initialization Failed\n");
2711 return;
2712 }
2713 if (hw->mac.type >= igb_mac_min)
2714 igb_init_dmac(sc, pba);
2715
2716 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2717 e1000_get_phy_info(hw);
2718 e1000_check_for_link(hw);
2719}
2720
2721/*
2722 * Initialise the RSS mapping for NICs that support multiple transmit/
2723 * receive rings.
2724 */
2725
2726#define RSSKEYLEN 10
2727static void
2728em_initialize_rss_mapping(struct e1000_softc *sc)
2729{
2730 uint8_t rss_key[4 * RSSKEYLEN];
2731 uint32_t reta = 0;
2732 struct e1000_hw *hw = &sc->hw;
2733 int i;
2734
2735 /*
2736 * Configure RSS key
2737 */
2738 arc4rand(rss_key, sizeof(rss_key), 0);
2739 for (i = 0; i < RSSKEYLEN; ++i) {
2740 uint32_t rssrk = 0;
2741
2742 rssrk = EM_RSSRK_VAL(rss_key, i);
2743 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2744 }
2745
2746 /*
2747 * Configure RSS redirect table in following fashion:
2748 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2749 */
2750 for (i = 0; i < sizeof(reta); ++i) {
2751 uint32_t q;
2752
2753 q = (i % sc->rx_num_queues) << 7;
2754 reta |= q << (8 * i);
2755 }
2756
2757 for (i = 0; i < 32; ++i)
2758 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2759
2760 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2761 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2762 E1000_MRQC_RSS_FIELD_IPV4 |
2763 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2764 E1000_MRQC_RSS_FIELD_IPV6_EX |
2765 E1000_MRQC_RSS_FIELD_IPV6);
2766}
2767
2768static void
2769igb_initialize_rss_mapping(struct e1000_softc *sc)
2770{
2771 struct e1000_hw *hw = &sc->hw;
2772 int i;
2773 int queue_id;
2774 u32 reta;
2775 u32 rss_key[10], mrqc, shift = 0;
2776
2777 /* XXX? */
2778 if (hw->mac.type == e1000_82575)
2779 shift = 6;
2780
2781 /*
2782 * The redirection table controls which destination
2783 * queue each bucket redirects traffic to.
2784 * Each DWORD represents four queues, with the LSB
2785 * being the first queue in the DWORD.
2786 *
2787 * This just allocates buckets to queues using round-robin
2788 * allocation.
2789 *
2790 * NOTE: It Just Happens to line up with the default
2791 * RSS allocation method.
2792 */
2793
2794 /* Warning FM follows */
2795 reta = 0;
2796 for (i = 0; i < 128; i++) {
2797#ifdef RSS
2798 queue_id = rss_get_indirection_to_bucket(i);
2799 /*
2800 * If we have more queues than buckets, we'll
2801 * end up mapping buckets to a subset of the
2802 * queues.
2803 *
2804 * If we have more buckets than queues, we'll
2805 * end up instead assigning multiple buckets
2806 * to queues.
2807 *
2808 * Both are suboptimal, but we need to handle
2809 * the case so we don't go out of bounds
2810 * indexing arrays and such.
2811 */
2812 queue_id = queue_id % sc->rx_num_queues;
2813#else
2814 queue_id = (i % sc->rx_num_queues);
2815#endif
2816 /* Adjust if required */
2817 queue_id = queue_id << shift;
2818
2819 /*
2820 * The low 8 bits are for hash value (n+0);
2821 * The next 8 bits are for hash value (n+1), etc.
2822 */
2823 reta = reta >> 8;
2824 reta = reta | ( ((uint32_t) queue_id) << 24);
2825 if ((i & 3) == 3) {
2826 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2827 reta = 0;
2828 }
2829 }
2830
2831 /* Now fill in hash table */
2832
2833 /*
2834 * MRQC: Multiple Receive Queues Command
2835 * Set queuing to RSS control, number depends on the device.
2836 */
2837 mrqc = E1000_MRQC_ENABLE_RSS_MQ;
2838
2839#ifdef RSS
2840 /* XXX ew typecasting */
2841 rss_getkey((uint8_t *) &rss_key);
2842#else
2843 arc4rand(&rss_key, sizeof(rss_key), 0);
2844#endif
2845 for (i = 0; i < 10; i++)
2846 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2847
2848 /*
2849 * Configure the RSS fields to hash upon.
2850 */
2851 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2852 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2853 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2854 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2855 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2856 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2857 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2858 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2859
2860 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2861}
2862
2863/*********************************************************************
2864 *
2865 * Setup networking device structure and register interface media.
2866 *
2867 **********************************************************************/
2868static int
2869em_setup_interface(if_ctx_t ctx)
2870{
2871 struct ifnet *ifp = iflib_get_ifp(ctx);
2872 struct e1000_softc *sc = iflib_get_softc(ctx);
2873 if_softc_ctx_t scctx = sc->shared;
2874
2875 INIT_DEBUGOUT("em_setup_interface: begin");
2876
2877 /* Single Queue */
2878 if (sc->tx_num_queues == 1) {
2879 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2880 if_setsendqready(ifp);
2881 }
2882
2883 /*
2884 * Specify the media types supported by this adapter and register
2885 * callbacks to update media and link information
2886 */
2887 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2888 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2889 u_char fiber_type = IFM_1000_SX; /* default type */
2890
2891 if (sc->hw.mac.type == e1000_82545)
2892 fiber_type = IFM_1000_LX;
2893 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2894 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL);
2895 } else {
2896 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2897 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2898 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2899 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2900 if (sc->hw.phy.type != e1000_phy_ife) {
2901 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2902 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2903 }
2904 }
2905 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2906 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
2907 return (0);
2908}
2909
2910static int
2911em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2912{
2913 struct e1000_softc *sc = iflib_get_softc(ctx);
2914 if_softc_ctx_t scctx = sc->shared;
2915 int error = E1000_SUCCESS;
2916 struct em_tx_queue *que;
2917 int i, j;
2918
2919 MPASS(sc->tx_num_queues > 0);
2920 MPASS(sc->tx_num_queues == ntxqsets);
2921
2922 /* First allocate the top level queue structs */
2923 if (!(sc->tx_queues =
2924 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2925 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2926 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2927 return(ENOMEM);
2928 }
2929
2930 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
2931 /* Set up some basics */
2932
2933 struct tx_ring *txr = &que->txr;
2934 txr->sc = que->sc = sc;
2935 que->me = txr->me = i;
2936
2937 /* Allocate report status array */
2938 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2939 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2940 error = ENOMEM;
2941 goto fail;
2942 }
2943 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2944 txr->tx_rsq[j] = QIDX_INVALID;
2945 /* get the virtual and physical address of the hardware queues */
2946 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2947 txr->tx_paddr = paddrs[i*ntxqs];
2948 }
2949
2950 if (bootverbose)
2951 device_printf(iflib_get_dev(ctx),
2952 "allocated for %d tx_queues\n", sc->tx_num_queues);
2953 return (0);
2954fail:
2955 em_if_queues_free(ctx);
2956 return (error);
2957}
2958
2959static int
2960em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2961{
2962 struct e1000_softc *sc = iflib_get_softc(ctx);
2963 int error = E1000_SUCCESS;
2964 struct em_rx_queue *que;
2965 int i;
2966
2967 MPASS(sc->rx_num_queues > 0);
2968 MPASS(sc->rx_num_queues == nrxqsets);
2969
2970 /* First allocate the top level queue structs */
2971 if (!(sc->rx_queues =
2972 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2973 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2974 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2975 error = ENOMEM;
2976 goto fail;
2977 }
2978
2979 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
2980 /* Set up some basics */
2981 struct rx_ring *rxr = &que->rxr;
2982 rxr->sc = que->sc = sc;
2983 rxr->que = que;
2984 que->me = rxr->me = i;
2985
2986 /* get the virtual and physical address of the hardware queues */
2987 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2988 rxr->rx_paddr = paddrs[i*nrxqs];
2989 }
2990
2991 if (bootverbose)
2992 device_printf(iflib_get_dev(ctx),
2993 "allocated for %d rx_queues\n", sc->rx_num_queues);
2994
2995 return (0);
2996fail:
2997 em_if_queues_free(ctx);
2998 return (error);
2999}
3000
3001static void
3002em_if_queues_free(if_ctx_t ctx)
3003{
3004 struct e1000_softc *sc = iflib_get_softc(ctx);
3005 struct em_tx_queue *tx_que = sc->tx_queues;
3006 struct em_rx_queue *rx_que = sc->rx_queues;
3007
3008 if (tx_que != NULL) {
3009 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
3010 struct tx_ring *txr = &tx_que->txr;
3011 if (txr->tx_rsq == NULL)
3012 break;
3013
3014 free(txr->tx_rsq, M_DEVBUF);
3015 txr->tx_rsq = NULL;
3016 }
3017 free(sc->tx_queues, M_DEVBUF);
3018 sc->tx_queues = NULL;
3019 }
3020
3021 if (rx_que != NULL) {
3022 free(sc->rx_queues, M_DEVBUF);
3023 sc->rx_queues = NULL;
3024 }
3025}
3026
3027/*********************************************************************
3028 *
3029 * Enable transmit unit.
3030 *
3031 **********************************************************************/
3032static void
3033em_initialize_transmit_unit(if_ctx_t ctx)
3034{
3035 struct e1000_softc *sc = iflib_get_softc(ctx);
3036 if_softc_ctx_t scctx = sc->shared;
3037 struct em_tx_queue *que;
3038 struct tx_ring *txr;
3039 struct e1000_hw *hw = &sc->hw;
3040 u32 tctl, txdctl = 0, tarc, tipg = 0;
3041
3042 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3043
3044 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3045 u64 bus_addr;
3046 caddr_t offp, endp;
3047
3048 que = &sc->tx_queues[i];
3049 txr = &que->txr;
3050 bus_addr = txr->tx_paddr;
3051
3052 /* Clear checksum offload context. */
3053 offp = (caddr_t)&txr->csum_flags;
3054 endp = (caddr_t)(txr + 1);
3055 bzero(offp, endp - offp);
3056
3057 /* Base and Len of TX Ring */
3058 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3059 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3060 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3061 (u32)(bus_addr >> 32));
3062 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3063 (u32)bus_addr);
3064 /* Init the HEAD/TAIL indices */
3065 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3066 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3067
3068 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3069 E1000_READ_REG(hw, E1000_TDBAL(i)),
3070 E1000_READ_REG(hw, E1000_TDLEN(i)));
3071
3072 txdctl = 0; /* clear txdctl */
3073 txdctl |= 0x1f; /* PTHRESH */
3074 txdctl |= 1 << 8; /* HTHRESH */
3075 txdctl |= 1 << 16;/* WTHRESH */
3076 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3077 txdctl |= E1000_TXDCTL_GRAN;
3078 txdctl |= 1 << 25; /* LWTHRESH */
3079
3080 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3081 }
3082
3083 /* Set the default values for the Tx Inter Packet Gap timer */
3084 switch (hw->mac.type) {
3085 case e1000_80003es2lan:
3086 tipg = DEFAULT_82543_TIPG_IPGR1;
3087 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3088 E1000_TIPG_IPGR2_SHIFT;
3089 break;
3090 case e1000_82542:
3091 tipg = DEFAULT_82542_TIPG_IPGT;
3092 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3093 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3094 break;
3095 default:
3096 if (hw->phy.media_type == e1000_media_type_fiber ||
3097 hw->phy.media_type == e1000_media_type_internal_serdes)
3098 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3099 else
3100 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3101 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3102 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3103 }
3104
3105 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3106 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
3107
3108 if(hw->mac.type >= e1000_82540)
3109 E1000_WRITE_REG(hw, E1000_TADV,
3110 sc->tx_abs_int_delay.value);
3111
3112 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3113 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3114 tarc |= TARC_SPEED_MODE_BIT;
3115 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3116 } else if (hw->mac.type == e1000_80003es2lan) {
3117 /* errata: program both queues to unweighted RR */
3118 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3119 tarc |= 1;
3120 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3121 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3122 tarc |= 1;
3123 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3124 } else if (hw->mac.type == e1000_82574) {
3125 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3126 tarc |= TARC_ERRATA_BIT;
3127 if ( sc->tx_num_queues > 1) {
3128 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3129 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3130 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3131 } else
3132 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3133 }
3134
3135 if (sc->tx_int_delay.value > 0)
3136 sc->txd_cmd |= E1000_TXD_CMD_IDE;
3137
3138 /* Program the Transmit Control Register */
3139 tctl = E1000_READ_REG(hw, E1000_TCTL);
3140 tctl &= ~E1000_TCTL_CT;
3141 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3142 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3143
3144 if (hw->mac.type >= e1000_82571)
3145 tctl |= E1000_TCTL_MULR;
3146
3147 /* This write will effectively turn on the transmit unit. */
3148 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3149
3150 /* SPT and KBL errata workarounds */
3151 if (hw->mac.type == e1000_pch_spt) {
3152 u32 reg;
3153 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3154 reg |= E1000_RCTL_RDMTS_HEX;
3155 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3156 /* i218-i219 Specification Update 1.5.4.5 */
3157 reg = E1000_READ_REG(hw, E1000_TARC(0));
3158 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3159 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3160 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3161 }
3162}
3163
3164/*********************************************************************
3165 *
3166 * Enable receive unit.
3167 *
3168 **********************************************************************/
3169#define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3170
3171static void
3172em_initialize_receive_unit(if_ctx_t ctx)
3173{
3174 struct e1000_softc *sc = iflib_get_softc(ctx);
3175 if_softc_ctx_t scctx = sc->shared;
3176 struct ifnet *ifp = iflib_get_ifp(ctx);
3177 struct e1000_hw *hw = &sc->hw;
3178 struct em_rx_queue *que;
3179 int i;
3180 uint32_t rctl, rxcsum;
3181
3182 INIT_DEBUGOUT("em_initialize_receive_units: begin");
3183
3184 /*
3185 * Make sure receives are disabled while setting
3186 * up the descriptor ring
3187 */
3188 rctl = E1000_READ_REG(hw, E1000_RCTL);
3189 /* Do not disable if ever enabled on this hardware */
3190 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3191 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3192
3193 /* Setup the Receive Control Register */
3194 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3195 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3196 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3197 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3198
3199 /* Do not store bad packets */
3200 rctl &= ~E1000_RCTL_SBP;
3201
3202 /* Enable Long Packet receive */
3203 if (if_getmtu(ifp) > ETHERMTU)
3204 rctl |= E1000_RCTL_LPE;
3205 else
3206 rctl &= ~E1000_RCTL_LPE;
3207
3208 /* Strip the CRC */
3209 if (!em_disable_crc_stripping)
3210 rctl |= E1000_RCTL_SECRC;
3211
3212 if (hw->mac.type >= e1000_82540) {
3213 E1000_WRITE_REG(hw, E1000_RADV,
3214 sc->rx_abs_int_delay.value);
3215
3216 /*
3217 * Set the interrupt throttling rate. Value is calculated
3218 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3219 */
3220 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3221 }
3222 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value);
3223
3224 if (hw->mac.type >= em_mac_min) {
3225 uint32_t rfctl;
3226 /* Use extended rx descriptor formats */
3227 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3228 rfctl |= E1000_RFCTL_EXTEN;
3229
3230 /*
3231 * When using MSI-X interrupts we need to throttle
3232 * using the EITR register (82574 only)
3233 */
3234 if (hw->mac.type == e1000_82574) {
3235 for (int i = 0; i < 4; i++)
3236 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3237 DEFAULT_ITR);
3238 /* Disable accelerated acknowledge */
3239 rfctl |= E1000_RFCTL_ACK_DIS;
3240 }
3241 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3242 }
3243
3244 /* Set up L3 and L4 csum Rx descriptor offloads */
3245 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3246 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
3247 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3248 if (hw->mac.type > e1000_82575)
3249 rxcsum |= E1000_RXCSUM_CRCOFL;
3250 else if (hw->mac.type < em_mac_min &&
3251 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6)
3252 rxcsum |= E1000_RXCSUM_IPV6OFL;
3253 } else {
3254 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3255 if (hw->mac.type > e1000_82575)
3256 rxcsum &= ~E1000_RXCSUM_CRCOFL;
3257 else if (hw->mac.type < em_mac_min)
3258 rxcsum &= ~E1000_RXCSUM_IPV6OFL;
3259 }
3260
3261 if (sc->rx_num_queues > 1) {
3262 /* RSS hash needed in the Rx descriptor */
3263 rxcsum |= E1000_RXCSUM_PCSD;
3264
3265 if (hw->mac.type >= igb_mac_min)
3266 igb_initialize_rss_mapping(sc);
3267 else
3268 em_initialize_rss_mapping(sc);
3269 }
3270 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3271
3272 /*
3273 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3274 * long latencies are observed, like Lenovo X60. This
3275 * change eliminates the problem, but since having positive
3276 * values in RDTR is a known source of problems on other
3277 * platforms another solution is being sought.
3278 */
3279 if (hw->mac.type == e1000_82573)
3280 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3281
3282 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3283 struct rx_ring *rxr = &que->rxr;
3284 /* Setup the Base and Length of the Rx Descriptor Ring */
3285 u64 bus_addr = rxr->rx_paddr;
3286#if 0
3287 u32 rdt = sc->rx_num_queues -1; /* default */
3288#endif
3289
3290 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3291 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3292 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3293 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3294 /* Setup the Head and Tail Descriptor Pointers */
3295 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3296 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3297 }
3298
3299 /*
3300 * Set PTHRESH for improved jumbo performance
3301 * According to 10.2.5.11 of Intel 82574 Datasheet,
3302 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3303 * Only write to RXDCTL(1) if there is a need for different
3304 * settings.
3305 */
3306 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3307 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3308 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3309 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3310 } else if (hw->mac.type == e1000_82574) {
3311 for (int i = 0; i < sc->rx_num_queues; i++) {
3312 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3313 rxdctl |= 0x20; /* PTHRESH */
3314 rxdctl |= 4 << 8; /* HTHRESH */
3315 rxdctl |= 4 << 16;/* WTHRESH */
3316 rxdctl |= 1 << 24; /* Switch to granularity */
3317 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3318 }
3319 } else if (hw->mac.type >= igb_mac_min) {
3320 u32 psize, srrctl = 0;
3321
3322 if (if_getmtu(ifp) > ETHERMTU) {
3323 psize = scctx->isc_max_frame_size;
3324 /* are we on a vlan? */
3325 if (ifp->if_vlantrunk != NULL)
3326 psize += VLAN_TAG_SIZE;
3327
3328 if (sc->vf_ifp)
3329 e1000_rlpml_set_vf(hw, psize);
3330 else
3331 E1000_WRITE_REG(hw, E1000_RLPML, psize);
3332 }
3333
3334 /* Set maximum packet buffer len */
3335 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3336 E1000_SRRCTL_BSIZEPKT_SHIFT;
3337
3338 /*
3339 * If TX flow control is disabled and there's >1 queue defined,
3340 * enable DROP.
3341 *
3342 * This drops frames rather than hanging the RX MAC for all queues.
3343 */
3344 if ((sc->rx_num_queues > 1) &&
3345 (sc->fc == e1000_fc_none ||
3346 sc->fc == e1000_fc_rx_pause)) {
3347 srrctl |= E1000_SRRCTL_DROP_EN;
3348 }
3349 /* Setup the Base and Length of the Rx Descriptor Rings */
3350 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3351 struct rx_ring *rxr = &que->rxr;
3352 u64 bus_addr = rxr->rx_paddr;
3353 u32 rxdctl;
3354
3355#ifdef notyet
3356 /* Configure for header split? -- ignore for now */
3357 rxr->hdr_split = igb_header_split;
3358#else
3359 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3360#endif
3361
3362 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3363 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3364 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3365 (uint32_t)(bus_addr >> 32));
3366 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3367 (uint32_t)bus_addr);
3368 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3369 /* Enable this Queue */
3370 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3371 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3372 rxdctl &= 0xFFF00000;
3373 rxdctl |= IGB_RX_PTHRESH;
3374 rxdctl |= IGB_RX_HTHRESH << 8;
3375 rxdctl |= IGB_RX_WTHRESH << 16;
3376 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3377 }
3378 } else if (hw->mac.type >= e1000_pch2lan) {
3379 if (if_getmtu(ifp) > ETHERMTU)
3380 e1000_lv_jumbo_workaround_ich8lan(hw, true);
3381 else
3382 e1000_lv_jumbo_workaround_ich8lan(hw, false);
3383 }
3384
3385 /* Make sure VLAN Filters are off */
3386 rctl &= ~E1000_RCTL_VFE;
3387
3388 /* Set up packet buffer size, overridden by per queue srrctl on igb */
3389 if (hw->mac.type < igb_mac_min) {
3390 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096)
3391 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3392 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192)
3393 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3394 else if (sc->rx_mbuf_sz > 8192)
3395 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
3396 else {
3397 rctl |= E1000_RCTL_SZ_2048;
3398 rctl &= ~E1000_RCTL_BSEX;
3399 }
3400 } else
3401 rctl |= E1000_RCTL_SZ_2048;
3402
3403 /*
3404 * rctl bits 11:10 are as follows
3405 * lem: reserved
3406 * em: DTYPE
3407 * igb: reserved
3408 * and should be 00 on all of the above
3409 */
3410 rctl &= ~0x00000C00;
3411
3412 /* Write out the settings */
3413 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3414
3415 return;
3416}
3417
3418static void
3419em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3420{
3421 struct e1000_softc *sc = iflib_get_softc(ctx);
3422 u32 index, bit;
3423
3424 index = (vtag >> 5) & 0x7F;
3425 bit = vtag & 0x1F;
3426 sc->shadow_vfta[index] |= (1 << bit);
3427 ++sc->num_vlans;
3428 em_if_vlan_filter_write(sc);
3429}
3430
3431static void
3432em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3433{
3434 struct e1000_softc *sc = iflib_get_softc(ctx);
3435 u32 index, bit;
3436
3437 index = (vtag >> 5) & 0x7F;
3438 bit = vtag & 0x1F;
3439 sc->shadow_vfta[index] &= ~(1 << bit);
3440 --sc->num_vlans;
3441 em_if_vlan_filter_write(sc);
3442}
3443
3444static bool
3445em_if_vlan_filter_capable(if_ctx_t ctx)
3446{
3447 if_t ifp = iflib_get_ifp(ctx);
3448
3449 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) &&
3450 !em_disable_crc_stripping)
3451 return (true);
3452
3453 return (false);
3454}
3455
3456static bool
3457em_if_vlan_filter_used(if_ctx_t ctx)
3458{
3459 struct e1000_softc *sc = iflib_get_softc(ctx);
3460
3461 if (!em_if_vlan_filter_capable(ctx))
3462 return (false);
3463
3464 for (int i = 0; i < EM_VFTA_SIZE; i++)
3465 if (sc->shadow_vfta[i] != 0)
3466 return (true);
3467
3468 return (false);
3469}
3470
3471static void
3472em_if_vlan_filter_enable(struct e1000_softc *sc)
3473{
3474 struct e1000_hw *hw = &sc->hw;
3475 u32 reg;
3476
3477 reg = E1000_READ_REG(hw, E1000_RCTL);
3478 reg &= ~E1000_RCTL_CFIEN;
3479 reg |= E1000_RCTL_VFE;
3480 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3481}
3482
3483static void
3484em_if_vlan_filter_disable(struct e1000_softc *sc)
3485{
3486 struct e1000_hw *hw = &sc->hw;
3487 u32 reg;
3488
3489 reg = E1000_READ_REG(hw, E1000_RCTL);
3490 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
3491 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3492}
3493
3494static void
3495em_if_vlan_filter_write(struct e1000_softc *sc)
3496{
3497 struct e1000_hw *hw = &sc->hw;
3498
3499 if (sc->vf_ifp)
3500 return;
3501
3502 /* Disable interrupts for lem-class devices during the filter change */
3503 if (hw->mac.type < em_mac_min)
3504 em_if_intr_disable(sc->ctx);
3505
3506 for (int i = 0; i < EM_VFTA_SIZE; i++)
3507 if (sc->shadow_vfta[i] != 0) {
3508 /* XXXKB: incomplete VF support, we return early above */
3509 if (sc->vf_ifp)
3510 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true);
3511 else
3512 e1000_write_vfta(hw, i, sc->shadow_vfta[i]);
3513 }
3514
3515 /* Re-enable interrupts for lem-class devices */
3516 if (hw->mac.type < em_mac_min)
3517 em_if_intr_enable(sc->ctx);
3518}
3519
3520static void
3521em_setup_vlan_hw_support(if_ctx_t ctx)
3522{
3523 struct e1000_softc *sc = iflib_get_softc(ctx);
3524 struct e1000_hw *hw = &sc->hw;
3525 struct ifnet *ifp = iflib_get_ifp(ctx);
3526 u32 reg;
3527
3528 /* XXXKB: Return early if we are a VF until VF decap and filter management
3529 * is ready and tested.
3530 */
3531 if (sc->vf_ifp)
3532 return;
3533
3534 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
3535 !em_disable_crc_stripping) {
3536 reg = E1000_READ_REG(hw, E1000_CTRL);
3537 reg |= E1000_CTRL_VME;
3538 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3539 } else {
3540 reg = E1000_READ_REG(hw, E1000_CTRL);
3541 reg &= ~E1000_CTRL_VME;
3542 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3543 }
3544
3545 /* If we aren't doing HW filtering, we're done */
3546 if (!em_if_vlan_filter_capable(ctx)) {
3547 em_if_vlan_filter_disable(sc);
3548 return;
3549 }
3550
3551 /*
3552 * A soft reset zero's out the VFTA, so
3553 * we need to repopulate it now.
3554 */
3555 em_if_vlan_filter_write(sc);
3556
3557 /* Enable the Filter Table */
3558 em_if_vlan_filter_enable(sc);
3559}
3560
3561static void
3562em_if_intr_enable(if_ctx_t ctx)
3563{
3564 struct e1000_softc *sc = iflib_get_softc(ctx);
3565 struct e1000_hw *hw = &sc->hw;
3566 u32 ims_mask = IMS_ENABLE_MASK;
3567
3568 if (sc->intr_type == IFLIB_INTR_MSIX) {
3569 E1000_WRITE_REG(hw, EM_EIAC, sc->ims);
3570 ims_mask |= sc->ims;
3571 }
3572 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3573 E1000_WRITE_FLUSH(hw);
3574}
3575
3576static void
3577em_if_intr_disable(if_ctx_t ctx)
3578{
3579 struct e1000_softc *sc = iflib_get_softc(ctx);
3580 struct e1000_hw *hw = &sc->hw;
3581
3582 if (sc->intr_type == IFLIB_INTR_MSIX)
3583 E1000_WRITE_REG(hw, EM_EIAC, 0);
3584 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3585 E1000_WRITE_FLUSH(hw);
3586}
3587
3588static void
3589igb_if_intr_enable(if_ctx_t ctx)
3590{
3591 struct e1000_softc *sc = iflib_get_softc(ctx);
3592 struct e1000_hw *hw = &sc->hw;
3593 u32 mask;
3594
3595 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
3596 mask = (sc->que_mask | sc->link_mask);
3597 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3598 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3599 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3600 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3601 } else
3602 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3603 E1000_WRITE_FLUSH(hw);
3604}
3605
3606static void
3607igb_if_intr_disable(if_ctx_t ctx)
3608{
3609 struct e1000_softc *sc = iflib_get_softc(ctx);
3610 struct e1000_hw *hw = &sc->hw;
3611
3612 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
3613 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3614 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3615 }
3616 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3617 E1000_WRITE_FLUSH(hw);
3618}
3619
3620/*
3621 * Bit of a misnomer, what this really means is
3622 * to enable OS management of the system... aka
3623 * to disable special hardware management features
3624 */
3625static void
3626em_init_manageability(struct e1000_softc *sc)
3627{
3628 /* A shared code workaround */
3629#define E1000_82542_MANC2H E1000_MANC2H
3630 if (sc->has_manage) {
3631 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3632 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3633
3634 /* disable hardware interception of ARP */
3635 manc &= ~(E1000_MANC_ARP_EN);
3636
3637 /* enable receiving management packets to the host */
3638 manc |= E1000_MANC_EN_MNG2HOST;
3639#define E1000_MNG2HOST_PORT_623 (1 << 5)
3640#define E1000_MNG2HOST_PORT_664 (1 << 6)
3641 manc2h |= E1000_MNG2HOST_PORT_623;
3642 manc2h |= E1000_MNG2HOST_PORT_664;
3643 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3644 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3645 }
3646}
3647
3648/*
3649 * Give control back to hardware management
3650 * controller if there is one.
3651 */
3652static void
3653em_release_manageability(struct e1000_softc *sc)
3654{
3655 if (sc->has_manage) {
3656 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3657
3658 /* re-enable hardware interception of ARP */
3659 manc |= E1000_MANC_ARP_EN;
3660 manc &= ~E1000_MANC_EN_MNG2HOST;
3661
3662 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3663 }
3664}
3665
3666/*
3667 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3668 * For ASF and Pass Through versions of f/w this means
3669 * that the driver is loaded. For AMT version type f/w
3670 * this means that the network i/f is open.
3671 */
3672static void
3673em_get_hw_control(struct e1000_softc *sc)
3674{
3675 u32 ctrl_ext, swsm;
3676
3677 if (sc->vf_ifp)
3678 return;
3679
3680 if (sc->hw.mac.type == e1000_82573) {
3681 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3682 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3683 swsm | E1000_SWSM_DRV_LOAD);
3684 return;
3685 }
3686 /* else */
3687 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3688 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3689 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3690}
3691
3692/*
3693 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3694 * For ASF and Pass Through versions of f/w this means that
3695 * the driver is no longer loaded. For AMT versions of the
3696 * f/w this means that the network i/f is closed.
3697 */
3698static void
3699em_release_hw_control(struct e1000_softc *sc)
3700{
3701 u32 ctrl_ext, swsm;
3702
3703 if (!sc->has_manage)
3704 return;
3705
3706 if (sc->hw.mac.type == e1000_82573) {
3707 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3708 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3709 swsm & ~E1000_SWSM_DRV_LOAD);
3710 return;
3711 }
3712 /* else */
3713 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3714 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3715 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3716 return;
3717}
3718
3719static int
3720em_is_valid_ether_addr(u8 *addr)
3721{
3722 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3723
3724 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3725 return (false);
3726 }
3727
3728 return (true);
3729}
3730
3731/*
3732** Parse the interface capabilities with regard
3733** to both system management and wake-on-lan for
3734** later use.
3735*/
3736static void
3737em_get_wakeup(if_ctx_t ctx)
3738{
3739 struct e1000_softc *sc = iflib_get_softc(ctx);
3740 device_t dev = iflib_get_dev(ctx);
3741 u16 eeprom_data = 0, device_id, apme_mask;
3742
3743 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
3744 apme_mask = EM_EEPROM_APME;
3745
3746 switch (sc->hw.mac.type) {
3747 case e1000_82542:
3748 case e1000_82543:
3749 break;
3750 case e1000_82544:
3751 e1000_read_nvm(&sc->hw,
3752 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3753 apme_mask = EM_82544_APME;
3754 break;
3755 case e1000_82546:
3756 case e1000_82546_rev_3:
3757 if (sc->hw.bus.func == 1) {
3758 e1000_read_nvm(&sc->hw,
3759 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3760 break;
3761 } else
3762 e1000_read_nvm(&sc->hw,
3763 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3764 break;
3765 case e1000_82573:
3766 case e1000_82583:
3767 sc->has_amt = true;
3768 /* FALLTHROUGH */
3769 case e1000_82571:
3770 case e1000_82572:
3771 case e1000_80003es2lan:
3772 if (sc->hw.bus.func == 1) {
3773 e1000_read_nvm(&sc->hw,
3774 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3775 break;
3776 } else
3777 e1000_read_nvm(&sc->hw,
3778 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3779 break;
3780 case e1000_ich8lan:
3781 case e1000_ich9lan:
3782 case e1000_ich10lan:
3783 case e1000_pchlan:
3784 case e1000_pch2lan:
3785 case e1000_pch_lpt:
3786 case e1000_pch_spt:
3787 case e1000_82575: /* listing all igb devices */
3788 case e1000_82576:
3789 case e1000_82580:
3790 case e1000_i350:
3791 case e1000_i354:
3792 case e1000_i210:
3793 case e1000_i211:
3794 case e1000_vfadapt:
3795 case e1000_vfadapt_i350:
3796 apme_mask = E1000_WUC_APME;
3797 sc->has_amt = true;
3798 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC);
3799 break;
3800 default:
3801 e1000_read_nvm(&sc->hw,
3802 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3803 break;
3804 }
3805 if (eeprom_data & apme_mask)
3806 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3807 /*
3808 * We have the eeprom settings, now apply the special cases
3809 * where the eeprom may be wrong or the board won't support
3810 * wake on lan on a particular port
3811 */
3812 device_id = pci_get_device(dev);
3813 switch (device_id) {
3814 case E1000_DEV_ID_82546GB_PCIE:
3815 sc->wol = 0;
3816 break;
3817 case E1000_DEV_ID_82546EB_FIBER:
3818 case E1000_DEV_ID_82546GB_FIBER:
3819 /* Wake events only supported on port A for dual fiber
3820 * regardless of eeprom setting */
3821 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
3822 E1000_STATUS_FUNC_1)
3823 sc->wol = 0;
3824 break;
3825 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3826 /* if quad port adapter, disable WoL on all but port A */
3827 if (global_quad_port_a != 0)
3828 sc->wol = 0;
3829 /* Reset for multiple quad port adapters */
3830 if (++global_quad_port_a == 4)
3831 global_quad_port_a = 0;
3832 break;
3833 case E1000_DEV_ID_82571EB_FIBER:
3834 /* Wake events only supported on port A for dual fiber
3835 * regardless of eeprom setting */
3836 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
3837 E1000_STATUS_FUNC_1)
3838 sc->wol = 0;
3839 break;
3840 case E1000_DEV_ID_82571EB_QUAD_COPPER:
3841 case E1000_DEV_ID_82571EB_QUAD_FIBER:
3842 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3843 /* if quad port adapter, disable WoL on all but port A */
3844 if (global_quad_port_a != 0)
3845 sc->wol = 0;
3846 /* Reset for multiple quad port adapters */
3847 if (++global_quad_port_a == 4)
3848 global_quad_port_a = 0;
3849 break;
3850 }
3851 return;
3852}
3853
3854
3855/*
3856 * Enable PCI Wake On Lan capability
3857 */
3858static void
3859em_enable_wakeup(if_ctx_t ctx)
3860{
3861 struct e1000_softc *sc = iflib_get_softc(ctx);
3862 device_t dev = iflib_get_dev(ctx);
3863 if_t ifp = iflib_get_ifp(ctx);
3864 int error = 0;
3865 u32 pmc, ctrl, ctrl_ext, rctl;
3866 u16 status;
3867
3868 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3869 return;
3870
3871 /*
3872 * Determine type of Wakeup: note that wol
3873 * is set with all bits on by default.
3874 */
3875 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3876 sc->wol &= ~E1000_WUFC_MAG;
3877
3878 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3879 sc->wol &= ~E1000_WUFC_EX;
3880
3881 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3882 sc->wol &= ~E1000_WUFC_MC;
3883 else {
3884 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
3885 rctl |= E1000_RCTL_MPE;
3886 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3887 }
3888
3889 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3890 goto pme;
3891
3892 /* Advertise the wakeup capability */
3893 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
3894 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3895 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
3896
3897 /* Keep the laser running on Fiber adapters */
3898 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
3899 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
3900 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3901 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3902 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext);
3903 }
3904
3905 if ((sc->hw.mac.type == e1000_ich8lan) ||
3906 (sc->hw.mac.type == e1000_pchlan) ||
3907 (sc->hw.mac.type == e1000_ich9lan) ||
3908 (sc->hw.mac.type == e1000_ich10lan))
3909 e1000_suspend_workarounds_ich8lan(&sc->hw);
3910
3911 if ( sc->hw.mac.type >= e1000_pchlan) {
3912 error = em_enable_phy_wakeup(sc);
3913 if (error)
3914 goto pme;
3915 } else {
3916 /* Enable wakeup by the MAC */
3917 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
3918 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
3919 }
3920
3921 if (sc->hw.phy.type == e1000_phy_igp_3)
3922 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw);
3923
3924pme:
3925 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3926 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3927 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3928 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3929 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3930
3931 return;
3932}
3933
3934/*
3935 * WOL in the newer chipset interfaces (pchlan)
3936 * require thing to be copied into the phy
3937 */
3938static int
3939em_enable_phy_wakeup(struct e1000_softc *sc)
3940{
3941 struct e1000_hw *hw = &sc->hw;
3942 u32 mreg, ret = 0;
3943 u16 preg;
3944
3945 /* copy MAC RARs to PHY RARs */
3946 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3947
3948 /* copy MAC MTA to PHY MTA */
3949 for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3950 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3951 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3952 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3953 (u16)((mreg >> 16) & 0xFFFF));
3954 }
3955
3956 /* configure PHY Rx Control register */
3957 e1000_read_phy_reg(hw, BM_RCTL, &preg);
3958 mreg = E1000_READ_REG(hw, E1000_RCTL);
3959 if (mreg & E1000_RCTL_UPE)
3960 preg |= BM_RCTL_UPE;
3961 if (mreg & E1000_RCTL_MPE)
3962 preg |= BM_RCTL_MPE;
3963 preg &= ~(BM_RCTL_MO_MASK);
3964 if (mreg & E1000_RCTL_MO_3)
3965 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3966 << BM_RCTL_MO_SHIFT);
3967 if (mreg & E1000_RCTL_BAM)
3968 preg |= BM_RCTL_BAM;
3969 if (mreg & E1000_RCTL_PMCF)
3970 preg |= BM_RCTL_PMCF;
3971 mreg = E1000_READ_REG(hw, E1000_CTRL);
3972 if (mreg & E1000_CTRL_RFCE)
3973 preg |= BM_RCTL_RFCE;
3974 e1000_write_phy_reg(hw, BM_RCTL, preg);
3975
3976 /* enable PHY wakeup in MAC register */
3977 E1000_WRITE_REG(hw, E1000_WUC,
3978 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3979 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol);
3980
3981 /* configure and enable PHY wakeup in PHY registers */
3982 e1000_write_phy_reg(hw, BM_WUFC, sc->wol);
3983 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3984
3985 /* activate PHY wakeup */
3986 ret = hw->phy.ops.acquire(hw);
3987 if (ret) {
3988 printf("Could not acquire PHY\n");
3989 return ret;
3990 }
3991 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3992 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3993 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3994 if (ret) {
3995 printf("Could not read PHY page 769\n");
3996 goto out;
3997 }
3998 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3999 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
4000 if (ret)
4001 printf("Could not set PHY Host Wakeup bit\n");
4002out:
4003 hw->phy.ops.release(hw);
4004
4005 return ret;
4006}
4007
4008static void
4009em_if_led_func(if_ctx_t ctx, int onoff)
4010{
4011 struct e1000_softc *sc = iflib_get_softc(ctx);
4012
4013 if (onoff) {
4014 e1000_setup_led(&sc->hw);
4015 e1000_led_on(&sc->hw);
4016 } else {
4017 e1000_led_off(&sc->hw);
4018 e1000_cleanup_led(&sc->hw);
4019 }
4020}
4021
4022/*
4023 * Disable the L0S and L1 LINK states
4024 */
4025static void
4026em_disable_aspm(struct e1000_softc *sc)
4027{
4028 int base, reg;
4029 u16 link_cap,link_ctrl;
4030 device_t dev = sc->dev;
4031
4032 switch (sc->hw.mac.type) {
4033 case e1000_82573:
4034 case e1000_82574:
4035 case e1000_82583:
4036 break;
4037 default:
4038 return;
4039 }
4040 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
4041 return;
4042 reg = base + PCIER_LINK_CAP;
4043 link_cap = pci_read_config(dev, reg, 2);
4044 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
4045 return;
4046 reg = base + PCIER_LINK_CTL;
4047 link_ctrl = pci_read_config(dev, reg, 2);
4048 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
4049 pci_write_config(dev, reg, link_ctrl, 2);
4050 return;
4051}
4052
4053/**********************************************************************
4054 *
4055 * Update the board statistics counters.
4056 *
4057 **********************************************************************/
4058static void
4059em_update_stats_counters(struct e1000_softc *sc)
4060{
4061 u64 prev_xoffrxc = sc->stats.xoffrxc;
4062
4063 if(sc->hw.phy.media_type == e1000_media_type_copper ||
4064 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4065 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
4066 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
4067 }
4068 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
4069 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
4070 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
4071 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
4072
4073 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
4074 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
4075 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
4076 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
4077 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
4078 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
4079 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
4080 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
4081 /*
4082 ** For watchdog management we need to know if we have been
4083 ** paused during the last interval, so capture that here.
4084 */
4085 if (sc->stats.xoffrxc != prev_xoffrxc)
4086 sc->shared->isc_pause_frames = 1;
4087 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
4088 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
4089 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
4090 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
4091 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
4092 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
4093 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
4094 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
4095 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
4096 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
4097 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
4098 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
4099
4100 /* For the 64-bit byte counters the low dword must be read first. */
4101 /* Both registers clear on the read of the high dword */
4102
4103 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) +
4104 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32);
4105 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) +
4106 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32);
4107
4108 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
4109 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
4110 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
4111 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
4112 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
4113
4114 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
4115 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
4116
4117 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
4118 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
4119 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
4120 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
4121 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
4122 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
4123 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
4124 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
4125 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
4126 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
4127
4128 /* Interrupt Counts */
4129
4130 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC);
4131 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC);
4132 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC);
4133 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC);
4134 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC);
4135 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC);
4136 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC);
4137 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC);
4138 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC);
4139
4140 if (sc->hw.mac.type >= e1000_82543) {
4141 sc->stats.algnerrc +=
4142 E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
4143 sc->stats.rxerrc +=
4144 E1000_READ_REG(&sc->hw, E1000_RXERRC);
4145 sc->stats.tncrs +=
4146 E1000_READ_REG(&sc->hw, E1000_TNCRS);
4147 sc->stats.cexterr +=
4148 E1000_READ_REG(&sc->hw, E1000_CEXTERR);
4149 sc->stats.tsctc +=
4150 E1000_READ_REG(&sc->hw, E1000_TSCTC);
4151 sc->stats.tsctfc +=
4152 E1000_READ_REG(&sc->hw, E1000_TSCTFC);
4153 }
4154}
4155
4156static uint64_t
4157em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4158{
4159 struct e1000_softc *sc = iflib_get_softc(ctx);
4160 struct ifnet *ifp = iflib_get_ifp(ctx);
4161
4162 switch (cnt) {
4163 case IFCOUNTER_COLLISIONS:
4164 return (sc->stats.colc);
4165 case IFCOUNTER_IERRORS:
4166 return (sc->dropped_pkts + sc->stats.rxerrc +
4167 sc->stats.crcerrs + sc->stats.algnerrc +
4168 sc->stats.ruc + sc->stats.roc +
4169 sc->stats.mpc + sc->stats.cexterr);
4170 case IFCOUNTER_OERRORS:
4171 return (sc->stats.ecol + sc->stats.latecol +
4172 sc->watchdog_events);
4173 default:
4174 return (if_get_counter_default(ifp, cnt));
4175 }
4176}
4177
4178/* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4179 * @ctx: iflib context
4180 * @event: event code to check
4181 *
4182 * Defaults to returning true for unknown events.
4183 *
4184 * @returns true if iflib needs to reinit the interface
4185 */
4186static bool
4187em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4188{
4189 switch (event) {
4190 case IFLIB_RESTART_VLAN_CONFIG:
4191 return (false);
4192 default:
4193 return (true);
4194 }
4195}
4196
4197/* Export a single 32-bit register via a read-only sysctl. */
4198static int
4199em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4200{
4201 struct e1000_softc *sc;
4202 u_int val;
4203
4204 sc = oidp->oid_arg1;
4205 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2);
4206 return (sysctl_handle_int(oidp, &val, 0, req));
4207}
4208
4209/*
4210 * Add sysctl variables, one per statistic, to the system.
4211 */
4212static void
4213em_add_hw_stats(struct e1000_softc *sc)
4214{
4215 device_t dev = iflib_get_dev(sc->ctx);
4216 struct em_tx_queue *tx_que = sc->tx_queues;
4217 struct em_rx_queue *rx_que = sc->rx_queues;
4218
4219 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4220 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4221 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4222 struct e1000_hw_stats *stats = &sc->stats;
4223
4224 struct sysctl_oid *stat_node, *queue_node, *int_node;
4225 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4226
4227#define QUEUE_NAME_LEN 32
4228 char namebuf[QUEUE_NAME_LEN];
4229
4230 /* Driver Statistics */
4231 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4232 CTLFLAG_RD, &sc->dropped_pkts,
4233 "Driver dropped packets");
4234 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4235 CTLFLAG_RD, &sc->link_irq,
4236 "Link MSI-X IRQ Handled");
4237 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4238 CTLFLAG_RD, &sc->rx_overruns,
4239 "RX overruns");
4240 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4241 CTLFLAG_RD, &sc->watchdog_events,
4242 "Watchdog timeouts");
4243 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4244 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4245 sc, E1000_CTRL, em_sysctl_reg_handler, "IU",
4246 "Device Control Register");
4247 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4248 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4249 sc, E1000_RCTL, em_sysctl_reg_handler, "IU",
4250 "Receiver Control Register");
4251 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4252 CTLFLAG_RD, &sc->hw.fc.high_water, 0,
4253 "Flow Control High Watermark");
4254 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4255 CTLFLAG_RD, &sc->hw.fc.low_water, 0,
4256 "Flow Control Low Watermark");
4257
4258 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
4259 struct tx_ring *txr = &tx_que->txr;
4260 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4261 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4262 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4263 queue_list = SYSCTL_CHILDREN(queue_node);
4264
4265 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4266 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4267 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4268 "Transmit Descriptor Head");
4269 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4270 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4271 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4272 "Transmit Descriptor Tail");
4273 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4274 CTLFLAG_RD, &txr->tx_irq,
4275 "Queue MSI-X Transmit Interrupts");
4276 }
4277
4278 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
4279 struct rx_ring *rxr = &rx_que->rxr;
4280 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4281 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4282 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4283 queue_list = SYSCTL_CHILDREN(queue_node);
4284
4285 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4286 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4287 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4288 "Receive Descriptor Head");
4289 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4290 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4291 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4292 "Receive Descriptor Tail");
4293 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4294 CTLFLAG_RD, &rxr->rx_irq,
4295 "Queue MSI-X Receive Interrupts");
4296 }
4297
4298 /* MAC stats get their own sub node */
4299
4300 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4301 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4302 stat_list = SYSCTL_CHILDREN(stat_node);
4303
4304 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4305 CTLFLAG_RD, &stats->ecol,
4306 "Excessive collisions");
4307 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4308 CTLFLAG_RD, &stats->scc,
4309 "Single collisions");
4310 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4311 CTLFLAG_RD, &stats->mcc,
4312 "Multiple collisions");
4313 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4314 CTLFLAG_RD, &stats->latecol,
4315 "Late collisions");
4316 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4317 CTLFLAG_RD, &stats->colc,
4318 "Collision Count");
4319 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4320 CTLFLAG_RD, &sc->stats.symerrs,
4321 "Symbol Errors");
4322 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4323 CTLFLAG_RD, &sc->stats.sec,
4324 "Sequence Errors");
4325 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4326 CTLFLAG_RD, &sc->stats.dc,
4327 "Defer Count");
4328 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4329 CTLFLAG_RD, &sc->stats.mpc,
4330 "Missed Packets");
4331 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4332 CTLFLAG_RD, &sc->stats.rnbc,
4333 "Receive No Buffers");
4334 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4335 CTLFLAG_RD, &sc->stats.ruc,
4336 "Receive Undersize");
4337 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4338 CTLFLAG_RD, &sc->stats.rfc,
4339 "Fragmented Packets Received ");
4340 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4341 CTLFLAG_RD, &sc->stats.roc,
4342 "Oversized Packets Received");
4343 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4344 CTLFLAG_RD, &sc->stats.rjc,
4345 "Recevied Jabber");
4346 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4347 CTLFLAG_RD, &sc->stats.rxerrc,
4348 "Receive Errors");
4349 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4350 CTLFLAG_RD, &sc->stats.crcerrs,
4351 "CRC errors");
4352 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4353 CTLFLAG_RD, &sc->stats.algnerrc,
4354 "Alignment Errors");
4355 /* On 82575 these are collision counts */
4356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4357 CTLFLAG_RD, &sc->stats.cexterr,
4358 "Collision/Carrier extension errors");
4359 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4360 CTLFLAG_RD, &sc->stats.xonrxc,
4361 "XON Received");
4362 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4363 CTLFLAG_RD, &sc->stats.xontxc,
4364 "XON Transmitted");
4365 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4366 CTLFLAG_RD, &sc->stats.xoffrxc,
4367 "XOFF Received");
4368 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4369 CTLFLAG_RD, &sc->stats.xofftxc,
4370 "XOFF Transmitted");
4371
4372 /* Packet Reception Stats */
4373 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4374 CTLFLAG_RD, &sc->stats.tpr,
4375 "Total Packets Received ");
4376 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4377 CTLFLAG_RD, &sc->stats.gprc,
4378 "Good Packets Received");
4379 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4380 CTLFLAG_RD, &sc->stats.bprc,
4381 "Broadcast Packets Received");
4382 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4383 CTLFLAG_RD, &sc->stats.mprc,
4384 "Multicast Packets Received");
4385 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4386 CTLFLAG_RD, &sc->stats.prc64,
4387 "64 byte frames received ");
4388 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4389 CTLFLAG_RD, &sc->stats.prc127,
4390 "65-127 byte frames received");
4391 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4392 CTLFLAG_RD, &sc->stats.prc255,
4393 "128-255 byte frames received");
4394 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4395 CTLFLAG_RD, &sc->stats.prc511,
4396 "256-511 byte frames received");
4397 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4398 CTLFLAG_RD, &sc->stats.prc1023,
4399 "512-1023 byte frames received");
4400 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4401 CTLFLAG_RD, &sc->stats.prc1522,
4402 "1023-1522 byte frames received");
4403 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4404 CTLFLAG_RD, &sc->stats.gorc,
4405 "Good Octets Received");
4406
4407 /* Packet Transmission Stats */
4408 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4409 CTLFLAG_RD, &sc->stats.gotc,
4410 "Good Octets Transmitted");
4411 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4412 CTLFLAG_RD, &sc->stats.tpt,
4413 "Total Packets Transmitted");
4414 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4415 CTLFLAG_RD, &sc->stats.gptc,
4416 "Good Packets Transmitted");
4417 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4418 CTLFLAG_RD, &sc->stats.bptc,
4419 "Broadcast Packets Transmitted");
4420 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4421 CTLFLAG_RD, &sc->stats.mptc,
4422 "Multicast Packets Transmitted");
4423 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4424 CTLFLAG_RD, &sc->stats.ptc64,
4425 "64 byte frames transmitted ");
4426 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4427 CTLFLAG_RD, &sc->stats.ptc127,
4428 "65-127 byte frames transmitted");
4429 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4430 CTLFLAG_RD, &sc->stats.ptc255,
4431 "128-255 byte frames transmitted");
4432 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4433 CTLFLAG_RD, &sc->stats.ptc511,
4434 "256-511 byte frames transmitted");
4435 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4436 CTLFLAG_RD, &sc->stats.ptc1023,
4437 "512-1023 byte frames transmitted");
4438 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4439 CTLFLAG_RD, &sc->stats.ptc1522,
4440 "1024-1522 byte frames transmitted");
4441 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4442 CTLFLAG_RD, &sc->stats.tsctc,
4443 "TSO Contexts Transmitted");
4444 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4445 CTLFLAG_RD, &sc->stats.tsctfc,
4446 "TSO Contexts Failed");
4447
4448
4449 /* Interrupt Stats */
4450
4451 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4452 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4453 int_list = SYSCTL_CHILDREN(int_node);
4454
4455 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4456 CTLFLAG_RD, &sc->stats.iac,
4457 "Interrupt Assertion Count");
4458
4459 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4460 CTLFLAG_RD, &sc->stats.icrxptc,
4461 "Interrupt Cause Rx Pkt Timer Expire Count");
4462
4463 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4464 CTLFLAG_RD, &sc->stats.icrxatc,
4465 "Interrupt Cause Rx Abs Timer Expire Count");
4466
4467 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4468 CTLFLAG_RD, &sc->stats.ictxptc,
4469 "Interrupt Cause Tx Pkt Timer Expire Count");
4470
4471 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4472 CTLFLAG_RD, &sc->stats.ictxatc,
4473 "Interrupt Cause Tx Abs Timer Expire Count");
4474
4475 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4476 CTLFLAG_RD, &sc->stats.ictxqec,
4477 "Interrupt Cause Tx Queue Empty Count");
4478
4479 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4480 CTLFLAG_RD, &sc->stats.ictxqmtc,
4481 "Interrupt Cause Tx Queue Min Thresh Count");
4482
4483 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4484 CTLFLAG_RD, &sc->stats.icrxdmtc,
4485 "Interrupt Cause Rx Desc Min Thresh Count");
4486
4487 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4488 CTLFLAG_RD, &sc->stats.icrxoc,
4489 "Interrupt Cause Receiver Overrun Count");
4490}
4491
4492static void
4493em_fw_version_locked(if_ctx_t ctx)
4494{
4495 struct e1000_softc *sc = iflib_get_softc(ctx);
4496 struct e1000_hw *hw = &sc->hw;
4497 struct e1000_fw_version *fw_ver = &sc->fw_ver;
4498 uint16_t eep = 0;
4499
4500 /*
4501 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the
4502 * NVM locking model, so we do it in em_if_attach_pre() and store the
4503 * info in the softc
4504 */
4505 ASSERT_CTX_LOCK_HELD(hw);
4506
4507 *fw_ver = (struct e1000_fw_version){0};
4508
4509 if (hw->mac.type >= igb_mac_min) {
4510 /*
4511 * Use the Shared Code for igb(4)
4512 */
4513 e1000_get_fw_version(hw, fw_ver);
4514 } else {
4515 /*
4516 * Otherwise, EEPROM version should be present on (almost?) all
4517 * devices here
4518 */
4519 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) {
4520 INIT_DEBUGOUT("can't get EEPROM version");
4521 return;
4522 }
4523
4524 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
4525 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
4526 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK);
4527 }
4528}
4529
4530static void
4531em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf)
4532{
4533 const char *space = "";
4534
4535 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) {
4536 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major,
4537 fw_ver->eep_minor, fw_ver->eep_build);
4538 space = " ";
4539 }
4540
4541 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) {
4542 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d",
4543 space, fw_ver->invm_major, fw_ver->invm_minor,
4544 fw_ver->invm_img_type);
4545 space = " ";
4546 }
4547
4548 if (fw_ver->or_valid) {
4549 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
4550 space, fw_ver->or_major, fw_ver->or_build,
4551 fw_ver->or_patch);
4552 space = " ";
4553 }
4554
4555 if (fw_ver->etrack_id)
4556 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id);
4557}
4558
4559static void
4560em_print_fw_version(struct e1000_softc *sc )
4561{
4562 device_t dev = sc->dev;
4563 struct sbuf *buf;
4564 int error = 0;
4565
4566 buf = sbuf_new_auto();
4567 if (!buf) {
4568 device_printf(dev, "Could not allocate sbuf for output.\n");
4569 return;
4570 }
4571
4572 em_sbuf_fw_version(&sc->fw_ver, buf);
4573
4574 error = sbuf_finish(buf);
4575 if (error)
4576 device_printf(dev, "Error finishing sbuf: %d\n", error);
4577 else if (sbuf_len(buf))
4578 device_printf(dev, "%s\n", sbuf_data(buf));
4579
4580 sbuf_delete(buf);
4581}
4582
4583static int
4584em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
4585{
4586 struct e1000_softc *sc = (struct e1000_softc *)arg1;
4587 device_t dev = sc->dev;
4588 struct sbuf *buf;
4589 int error = 0;
4590
4591 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
4592 if (!buf) {
4593 device_printf(dev, "Could not allocate sbuf for output.\n");
4594 return (ENOMEM);
4595 }
4596
4597 em_sbuf_fw_version(&sc->fw_ver, buf);
4598
4599 error = sbuf_finish(buf);
4600 if (error)
4601 device_printf(dev, "Error finishing sbuf: %d\n", error);
4602
4603 sbuf_delete(buf);
4604
4605 return (0);
4606}
4607
4608/**********************************************************************
4609 *
4610 * This routine provides a way to dump out the adapter eeprom,
4611 * often a useful debug/service tool. This only dumps the first
4612 * 32 words, stuff that matters is in that extent.
4613 *
4614 **********************************************************************/
4615static int
4616em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4617{
4618 struct e1000_softc *sc = (struct e1000_softc *)arg1;
4619 int error;
4620 int result;
4621
4622 result = -1;
4623 error = sysctl_handle_int(oidp, &result, 0, req);
4624
4625 if (error || !req->newptr)
4626 return (error);
4627
4628 /*
4629 * This value will cause a hex dump of the
4630 * first 32 16-bit words of the EEPROM to
4631 * the screen.
4632 */
4633 if (result == 1)
4634 em_print_nvm_info(sc);
4635
4636 return (error);
4637}
4638
4639static void
4640em_print_nvm_info(struct e1000_softc *sc)
4641{
4642 struct e1000_hw *hw = &sc->hw;
4643 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx);
4644 u16 eeprom_data;
4645 int i, j, row = 0;
4646
4647 /* Its a bit crude, but it gets the job done */
4648 printf("\nInterface EEPROM Dump:\n");
4649 printf("Offset\n0x0000 ");
4650
4651 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */
4652 sx_xlock(iflib_ctx_lock);
4653 ASSERT_CTX_LOCK_HELD(hw);
4654 for (i = 0, j = 0; i < 32; i++, j++) {
4655 if (j == 8) { /* Make the offset block */
4656 j = 0; ++row;
4657 printf("\n0x00%x0 ",row);
4658 }
4659 e1000_read_nvm(hw, i, 1, &eeprom_data);
4660 printf("%04x ", eeprom_data);
4661 }
4662 sx_xunlock(iflib_ctx_lock);
4663 printf("\n");
4664}
4665
4666static int
4667em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4668{
4669 struct em_int_delay_info *info;
4670 struct e1000_softc *sc;
4671 u32 regval;
4672 int error, usecs, ticks;
4673
4674 info = (struct em_int_delay_info *) arg1;
4675 usecs = info->value;
4676 error = sysctl_handle_int(oidp, &usecs, 0, req);
4677 if (error != 0 || req->newptr == NULL)
4678 return (error);
4679 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4680 return (EINVAL);
4681 info->value = usecs;
4682 ticks = EM_USECS_TO_TICKS(usecs);
4683 if (info->offset == E1000_ITR) /* units are 256ns here */
4684 ticks *= 4;
4685
4686 sc = info->sc;
4687
4688 regval = E1000_READ_OFFSET(&sc->hw, info->offset);
4689 regval = (regval & ~0xffff) | (ticks & 0xffff);
4690 /* Handle a few special cases. */
4691 switch (info->offset) {
4692 case E1000_RDTR:
4693 break;
4694 case E1000_TIDV:
4695 if (ticks == 0) {
4696 sc->txd_cmd &= ~E1000_TXD_CMD_IDE;
4697 /* Don't write 0 into the TIDV register. */
4698 regval++;
4699 } else
4700 sc->txd_cmd |= E1000_TXD_CMD_IDE;
4701 break;
4702 }
4703 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval);
4704 return (0);
4705}
4706
4707static void
4708em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name,
4709 const char *description, struct em_int_delay_info *info,
4710 int offset, int value)
4711{
4712 info->sc = sc;
4713 info->offset = offset;
4714 info->value = value;
4715 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
4716 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
4717 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4718 info, 0, em_sysctl_int_delay, "I", description);
4719}
4720
4721/*
4722 * Set flow control using sysctl:
4723 * Flow control values:
4724 * 0 - off
4725 * 1 - rx pause
4726 * 2 - tx pause
4727 * 3 - full
4728 */
4729static int
4730em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4731{
4732 int error;
4733 static int input = 3; /* default is full */
4734 struct e1000_softc *sc = (struct e1000_softc *) arg1;
4735
4736 error = sysctl_handle_int(oidp, &input, 0, req);
4737
4738 if ((error) || (req->newptr == NULL))
4739 return (error);
4740
4741 if (input == sc->fc) /* no change? */
4742 return (error);
4743
4744 switch (input) {
4745 case e1000_fc_rx_pause:
4746 case e1000_fc_tx_pause:
4747 case e1000_fc_full:
4748 case e1000_fc_none:
4749 sc->hw.fc.requested_mode = input;
4750 sc->fc = input;
4751 break;
4752 default:
4753 /* Do nothing */
4754 return (error);
4755 }
4756
4757 sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
4758 e1000_force_mac_fc(&sc->hw);
4759 return (error);
4760}
4761
4762/*
4763 * Manage Energy Efficient Ethernet:
4764 * Control values:
4765 * 0/1 - enabled/disabled
4766 */
4767static int
4768em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4769{
4770 struct e1000_softc *sc = (struct e1000_softc *) arg1;
4771 int error, value;
4772
4773 value = sc->hw.dev_spec.ich8lan.eee_disable;
4774 error = sysctl_handle_int(oidp, &value, 0, req);
4775 if (error || req->newptr == NULL)
4776 return (error);
4777 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4778 em_if_init(sc->ctx);
4779
4780 return (0);
4781}
4782
4783static int
4784em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4785{
4786 struct e1000_softc *sc;
4787 int error;
4788 int result;
4789
4790 result = -1;
4791 error = sysctl_handle_int(oidp, &result, 0, req);
4792
4793 if (error || !req->newptr)
4794 return (error);
4795
4796 if (result == 1) {
4797 sc = (struct e1000_softc *) arg1;
4798 em_print_debug_info(sc);
4799 }
4800
4801 return (error);
4802}
4803
4804static int
4805em_get_rs(SYSCTL_HANDLER_ARGS)
4806{
4807 struct e1000_softc *sc = (struct e1000_softc *) arg1;
4808 int error;
4809 int result;
4810
4811 result = 0;
4812 error = sysctl_handle_int(oidp, &result, 0, req);
4813
4814 if (error || !req->newptr || result != 1)
4815 return (error);
4816 em_dump_rs(sc);
4817
4818 return (error);
4819}
4820
4821static void
4822em_if_debug(if_ctx_t ctx)
4823{
4824 em_dump_rs(iflib_get_softc(ctx));
4825}
4826
4827/*
4828 * This routine is meant to be fluid, add whatever is
4829 * needed for debugging a problem. -jfv
4830 */
4831static void
4832em_print_debug_info(struct e1000_softc *sc)
4833{
4834 device_t dev = iflib_get_dev(sc->ctx);
4835 struct ifnet *ifp = iflib_get_ifp(sc->ctx);
4836 struct tx_ring *txr = &sc->tx_queues->txr;
4837 struct rx_ring *rxr = &sc->rx_queues->rxr;
4838
4839 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4840 printf("Interface is RUNNING ");
4841 else
4842 printf("Interface is NOT RUNNING\n");
4843
4844 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4845 printf("and INACTIVE\n");
4846 else
4847 printf("and ACTIVE\n");
4848
4849 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
4850 device_printf(dev, "TX Queue %d ------\n", i);
4851 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4852 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
4853 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
4854
4855 }
4856 for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
4857 device_printf(dev, "RX Queue %d ------\n", j);
4858 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4859 E1000_READ_REG(&sc->hw, E1000_RDH(j)),
4860 E1000_READ_REG(&sc->hw, E1000_RDT(j)));
4861 }
4862}
4863
4864/*
4865 * 82574 only:
4866 * Write a new value to the EEPROM increasing the number of MSI-X
4867 * vectors from 3 to 5, for proper multiqueue support.
4868 */
4869static void
4870em_enable_vectors_82574(if_ctx_t ctx)
4871{
4872 struct e1000_softc *sc = iflib_get_softc(ctx);
4873 struct e1000_hw *hw = &sc->hw;
4874 device_t dev = iflib_get_dev(ctx);
4875 u16 edata;
4876
4877 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4878 if (bootverbose)
4879 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4880 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4881 device_printf(dev, "Writing to eeprom: increasing "
4882 "reported MSI-X vectors from 3 to 5...\n");
4883 edata &= ~(EM_NVM_MSIX_N_MASK);
4884 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4885 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4886 e1000_update_nvm_checksum(hw);
4887 device_printf(dev, "Writing to eeprom: done\n");
4888 }
4889}
e1000_init_script_state_82541
void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
Definition: e1000_82541.c:1205
e1000_set_tbi_compatibility_82543
void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
Definition: e1000_82543.c:311
e1000_get_laa_state_82571
bool e1000_get_laa_state_82571(struct e1000_hw *hw)
Definition: e1000_82571.c:1726
e1000_set_laa_state_82571
void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
Definition: e1000_82571.c:1743
E1000_EITR_82574
#define E1000_EITR_82574(_n)
Definition: e1000_82571.h:49
e1000_rxpbs_adjust_82580
u16 e1000_rxpbs_adjust_82580(u32 data)
Definition: e1000_82575.c:2323
e1000_set_eee_i350
s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
Definition: e1000_82575.c:2781
e1000_set_eee_i354
s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
Definition: e1000_82575.c:2836
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void e1000_vfta_set_vf(struct e1000_hw *, u16, bool)
Definition: e1000_vf.c:447
E1000_SRRCTL_DROP_EN
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Definition: e1000_82575.h:135
e1000_rlpml_set_vf
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Definition: e1000_vf.c:464
E1000_SRRCTL_DESCTYPE_ADV_ONEBUF
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Definition: e1000_82575.h:128
E1000_MRQC_RSS_FIELD_IPV6_UDP_EX
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Definition: e1000_82575.h:148
E1000_MRQC_ENABLE_RSS_MQ
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Definition: e1000_82575.h:143
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Definition: e1000_82575.h:393
E1000_RXDCTL_QUEUE_ENABLE
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Definition: e1000_82575.h:272
E1000_SRRCTL_BSIZEPKT_SHIFT
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Definition: e1000_82575.h:124
E1000_MRQC_RSS_FIELD_IPV6_UDP
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Definition: e1000_82575.h:147
E1000_MRQC_RSS_FIELD_IPV4_UDP
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Definition: e1000_82575.h:146
e1000_set_mac_type
s32 e1000_set_mac_type(struct e1000_hw *hw)
Definition: e1000_api.c:151
e1000_force_mac_fc
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Definition: e1000_api.c:626
e1000_led_on
s32 e1000_led_on(struct e1000_hw *hw)
Definition: e1000_api.c:808
e1000_check_for_link
s32 e1000_check_for_link(struct e1000_hw *hw)
Definition: e1000_api.c:639
e1000_phy_hw_reset
s32 e1000_phy_hw_reset(struct e1000_hw *hw)
Definition: e1000_api.c:1158
e1000_get_bus_info
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Definition: e1000_api.c:565
e1000_reset_hw
s32 e1000_reset_hw(struct e1000_hw *hw)
Definition: e1000_api.c:682
e1000_get_speed_and_duplex
s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
Definition: e1000_api.c:731
e1000_check_reset_block
s32 e1000_check_reset_block(struct e1000_hw *hw)
Definition: e1000_api.c:1007
e1000_rar_set
int e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
Definition: e1000_api.c:889
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Definition: e1000_api.c:697
e1000_write_vfta
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Definition: e1000_api.c:595
e1000_cleanup_led
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Definition: e1000_api.c:762
e1000_write_nvm
s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_api.c:1358
e1000_get_phy_info
s32 e1000_get_phy_info(struct e1000_hw *hw)
Definition: e1000_api.c:1143
e1000_update_nvm_checksum
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Definition: e1000_api.c:1309
e1000_validate_nvm_checksum
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Definition: e1000_api.c:1294
e1000_led_off
s32 e1000_led_off(struct e1000_hw *hw)
Definition: e1000_api.c:823
e1000_read_nvm
s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_api.c:1340
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Definition: e1000_api.c:433
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Definition: e1000_api.c:1233
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Definition: e1000_api.c:747
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Definition: e1000_api.c:1081
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Definition: e1000_api.c:1041
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Definition: e1000_defines.h:419
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Definition: e1000_defines.h:540
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Definition: e1000_defines.h:92
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Definition: e1000_defines.h:213
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Definition: e1000_defines.h:433
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Definition: e1000_defines.h:654
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Definition: e1000_defines.h:621
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Definition: e1000_defines.h:220
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Definition: e1000_defines.h:512
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Definition: e1000_defines.h:216
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Definition: e1000_defines.h:611
E1000_WUC_PHY_WAKE
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E1000_STATUS_2P5_SKU
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Definition: e1000_defines.h:434
E1000_PBA_34K
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Definition: e1000_defines.h:514
E1000_WUC_APME
#define E1000_WUC_APME
Definition: e1000_defines.h:45
E1000_GPIE_EIAME
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Definition: e1000_defines.h:112
E1000_IVAR_VALID
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Definition: e1000_defines.h:109
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Definition: e1000_defines.h:1463
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Definition: e1000_defines.h:861
SR_1000T_MS_CONFIG_FAULT
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Definition: e1000_defines.h:1012
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Definition: e1000_defines.h:1487
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Definition: e1000_defines.h:329
E1000_STATUS_LU
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E1000_PBA_20K
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Definition: e1000_defines.h:508
E1000_RCTL_LPE
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Definition: e1000_defines.h:195
E1000_RCTL_UPE
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Definition: e1000_defines.h:193
E1000_RCTL_LBM_NO
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Definition: e1000_defines.h:196
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Definition: e1000_defines.h:503
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Definition: e1000_defines.h:691
E1000_RFCTL_EXTEN
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Definition: e1000_defines.h:444
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Definition: e1000_defines.h:53
E1000_CTRL_EXT_IRCA
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Definition: e1000_defines.h:93
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Definition: e1000_defines.h:288
PHY_1000T_STATUS
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Definition: e1000_defines.h:1028
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#define E1000_EICR_TX_QUEUE0
Definition: e1000_defines.h:591
E1000_CT_SHIFT
#define E1000_CT_SHIFT
Definition: e1000_defines.h:450
E1000_IMS_OTHER
#define E1000_IMS_OTHER
Definition: e1000_defines.h:636
NVM_IMAGE_ID_MASK
#define NVM_IMAGE_ID_MASK
Definition: e1000_defines.h:1100
ADVERTISE_10_HALF
#define ADVERTISE_10_HALF
Definition: e1000_defines.h:360
MAX_JUMBO_FRAME_SIZE
#define MAX_JUMBO_FRAME_SIZE
Definition: e1000_defines.h:475
E1000_WUFC_EX
#define E1000_WUFC_EX
Definition: e1000_defines.h:54
MII_CR_RESTART_AUTO_NEG
#define MII_CR_RESTART_AUTO_NEG
Definition: e1000_defines.h:928
E1000_CTRL_EXT_SDP3_DATA
#define E1000_CTRL_EXT_SDP3_DATA
Definition: e1000_defines.h:72
E1000_RCTL_EN
#define E1000_RCTL_EN
Definition: e1000_defines.h:191
E1000_TCTL_EN
#define E1000_TCTL_EN
Definition: e1000_defines.h:418
E1000_PBA_26K
#define E1000_PBA_26K
Definition: e1000_defines.h:511
E1000_DMACR_DMAC_LX_MASK
#define E1000_DMACR_DMAC_LX_MASK
Definition: e1000_defines.h:1466
ADVERTISE_100_FULL
#define ADVERTISE_100_FULL
Definition: e1000_defines.h:363
DEFAULT_82542_TIPG_IPGR1
#define DEFAULT_82542_TIPG_IPGR1
Definition: e1000_defines.h:462
E1000_ICR_RXSEQ
#define E1000_ICR_RXSEQ
Definition: e1000_defines.h:548
E1000_RCTL_VFE
#define E1000_RCTL_VFE
Definition: e1000_defines.h:215
MII_CR_AUTO_NEG_EN
#define MII_CR_AUTO_NEG_EN
Definition: e1000_defines.h:931
E1000_RCTL_SECRC
#define E1000_RCTL_SECRC
Definition: e1000_defines.h:221
NVM_MINOR_SHIFT
#define NVM_MINOR_SHIFT
Definition: e1000_defines.h:1103
E1000_TXDCTL_GRAN
#define E1000_TXDCTL_GRAN
Definition: e1000_defines.h:679
E1000_PBA_8K
#define E1000_PBA_8K
Definition: e1000_defines.h:502
E1000_RAR_ENTRIES
#define E1000_RAR_ENTRIES
Definition: e1000_defines.h:701
E1000_DMACR_DMAC_EN
#define E1000_DMACR_DMAC_EN
Definition: e1000_defines.h:1468
DEFAULT_82543_TIPG_IPGR2
#define DEFAULT_82543_TIPG_IPGR2
Definition: e1000_defines.h:467
E1000_CTRL_RFCE
#define E1000_CTRL_RFCE
Definition: e1000_defines.h:286
E1000_PBA_22K
#define E1000_PBA_22K
Definition: e1000_defines.h:509
DEFAULT_82543_TIPG_IPGT_COPPER
#define DEFAULT_82543_TIPG_IPGT_COPPER
Definition: e1000_defines.h:458
ADVERTISE_100_HALF
#define ADVERTISE_100_HALF
Definition: e1000_defines.h:362
CR_1000T_MS_ENABLE
#define CR_1000T_MS_ENABLE
Definition: e1000_defines.h:997
E1000_ICR_INT_ASSERTED
#define E1000_ICR_INT_ASSERTED
Definition: e1000_defines.h:564
E1000_EITR_CNT_IGNR
#define E1000_EITR_CNT_IGNR
Definition: e1000_defines.h:672
ADVERTISE_1000_FULL
#define ADVERTISE_1000_FULL
Definition: e1000_defines.h:365
E1000_PBA_32K
#define E1000_PBA_32K
Definition: e1000_defines.h:513
E1000_MRQC_RSS_FIELD_IPV6_EX
#define E1000_MRQC_RSS_FIELD_IPV6_EX
Definition: e1000_defines.h:167
E1000_MRQC_RSS_FIELD_IPV6
#define E1000_MRQC_RSS_FIELD_IPV6
Definition: e1000_defines.h:168
E1000_MANC_ARP_EN
#define E1000_MANC_ARP_EN
Definition: e1000_defines.h:176
E1000_RXCSUM_CRCOFL
#define E1000_RXCSUM_CRCOFL
Definition: e1000_defines.h:436
NVM_MAJOR_SHIFT
#define NVM_MAJOR_SHIFT
Definition: e1000_defines.h:1102
E1000_SUCCESS
#define E1000_SUCCESS
Definition: e1000_defines.h:709
NVM_INIT_CONTROL3_PORT_A
#define NVM_INIT_CONTROL3_PORT_A
Definition: e1000_defines.h:1141
E1000_CTRL_EXT_DRV_LOAD
#define E1000_CTRL_EXT_DRV_LOAD
Definition: e1000_defines.h:94
DEFAULT_82542_TIPG_IPGT
#define DEFAULT_82542_TIPG_IPGT
Definition: e1000_defines.h:456
E1000_RCTL_SZ_4096
#define E1000_RCTL_SZ_4096
Definition: e1000_defines.h:214
E1000_RCTL_PMCF
#define E1000_RCTL_PMCF
Definition: e1000_defines.h:219
E1000_EICR_RX_QUEUE0
#define E1000_EICR_RX_QUEUE0
Definition: e1000_defines.h:587
PHY_1000T_CTRL
#define PHY_1000T_CTRL
Definition: e1000_defines.h:1027
E1000_CTRL_SWDPIN3
#define E1000_CTRL_SWDPIN3
Definition: e1000_defines.h:280
FULL_DUPLEX
#define FULL_DUPLEX
Definition: e1000_defines.h:356
E1000_TIPG_IPGR2_SHIFT
#define E1000_TIPG_IPGR2_SHIFT
Definition: e1000_defines.h:469
DEFAULT_80003ES2LAN_TIPG_IPGR2
#define DEFAULT_80003ES2LAN_TIPG_IPGR2
Definition: e1000_defines.h:468
E1000_PBA_48K
#define E1000_PBA_48K
Definition: e1000_defines.h:518
I210_I_PHY_ID
#define I210_I_PHY_ID
Definition: e1000_defines.h:1287
E1000_MRQC_RSS_ENABLE_2Q
#define E1000_MRQC_RSS_ENABLE_2Q
Definition: e1000_defines.h:162
E1000_MRQC_RSS_FIELD_IPV6_TCP
#define E1000_MRQC_RSS_FIELD_IPV6_TCP
Definition: e1000_defines.h:169
E1000_DEV_ID_82571EB_SERDES_DUAL
#define E1000_DEV_ID_82571EB_SERDES_DUAL
Definition: e1000_hw.h:84
E1000_DEV_ID_82572EI
#define E1000_DEV_ID_82572EI
Definition: e1000_hw.h:93
E1000_DEV_ID_PCH_LBG_I219_LM3
#define E1000_DEV_ID_PCH_LBG_I219_LM3
Definition: e1000_hw.h:145
E1000_DEV_ID_PCH_LPT_I217_V
#define E1000_DEV_ID_PCH_LPT_I217_V
Definition: e1000_hw.h:134
E1000_DEV_ID_I210_SERDES
#define E1000_DEV_ID_I210_SERDES
Definition: e1000_hw.h:208
E1000_DEV_ID_PCH_LPTLP_I218_LM
#define E1000_DEV_ID_PCH_LPTLP_I218_LM
Definition: e1000_hw.h:135
E1000_DEV_ID_I350_SGMII
#define E1000_DEV_ID_I350_SGMII
Definition: e1000_hw.h:202
E1000_DEV_ID_PCH_CMP_I219_V12
#define E1000_DEV_ID_PCH_CMP_I219_V12
Definition: e1000_hw.h:163
E1000_DEV_ID_PCH_TGP_I219_LM15
#define E1000_DEV_ID_PCH_TGP_I219_LM15
Definition: e1000_hw.h:168
e1000_phy_igp
@ e1000_phy_igp
Definition: e1000_hw.h:311
e1000_phy_ife
@ e1000_phy_ife
Definition: e1000_hw.h:315
e1000_phy_igp_3
@ e1000_phy_igp_3
Definition: e1000_hw.h:314
E1000_DEV_ID_82574LA
#define E1000_DEV_ID_82574LA
Definition: e1000_hw.h:98
e1000_pci_set_mwi
void e1000_pci_set_mwi(struct e1000_hw *hw)
Definition: e1000_osdep.c:57
E1000_DEV_ID_PCH_TGP_I219_V14
#define E1000_DEV_ID_PCH_TGP_I219_V14
Definition: e1000_hw.h:167
E1000_DEV_ID_82545GM_SERDES
#define E1000_DEV_ID_82545GM_SERDES
Definition: e1000_hw.h:61
E1000_DEV_ID_I211_COPPER
#define E1000_DEV_ID_I211_COPPER
Definition: e1000_hw.h:213
E1000_DEV_ID_I354_BACKPLANE_2_5GBPS
#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS
Definition: e1000_hw.h:216
E1000_DEV_ID_PCH_SPT_I219_V4
#define E1000_DEV_ID_PCH_SPT_I219_V4
Definition: e1000_hw.h:147
E1000_DEV_ID_82540EM_LOM
#define E1000_DEV_ID_82540EM_LOM
Definition: e1000_hw.h:53
E1000_DEV_ID_82547GI
#define E1000_DEV_ID_82547GI
Definition: e1000_hw.h:80
E1000_DEV_ID_PCH_SPT_I219_LM2
#define E1000_DEV_ID_PCH_SPT_I219_LM2
Definition: e1000_hw.h:143
E1000_DEV_ID_PCH_M_HV_LM
#define E1000_DEV_ID_PCH_M_HV_LM
Definition: e1000_hw.h:127
E1000_DEV_ID_ICH8_IFE_G
#define E1000_DEV_ID_ICH8_IFE_G
Definition: e1000_hw.h:110
E1000_DEV_ID_PCH_CMP_I219_LM12
#define E1000_DEV_ID_PCH_CMP_I219_LM12
Definition: e1000_hw.h:162
E1000_DEV_ID_82542
#define E1000_DEV_ID_82542
Definition: e1000_hw.h:45
E1000_DEV_ID_ICH9_IGP_M_V
#define E1000_DEV_ID_ICH9_IGP_M_V
Definition: e1000_hw.h:114
E1000_DEV_ID_ICH10_D_BM_V
#define E1000_DEV_ID_ICH10_D_BM_V
Definition: e1000_hw.h:126
E1000_DEV_ID_PCH_ADL_I219_V16
#define E1000_DEV_ID_PCH_ADL_I219_V16
Definition: e1000_hw.h:171
E1000_DEV_ID_82576_VF
#define E1000_DEV_ID_82576_VF
Definition: e1000_hw.h:186
E1000_DEV_ID_I210_COPPER_OEM1
#define E1000_DEV_ID_I210_COPPER_OEM1
Definition: e1000_hw.h:205
E1000_DEV_ID_PCH_SPT_I219_LM
#define E1000_DEV_ID_PCH_SPT_I219_LM
Definition: e1000_hw.h:141
E1000_DEV_ID_82571PT_QUAD_COPPER
#define E1000_DEV_ID_82571PT_QUAD_COPPER
Definition: e1000_hw.h:87
E1000_DEV_ID_ICH8_IGP_M_AMT
#define E1000_DEV_ID_ICH8_IGP_M_AMT
Definition: e1000_hw.h:105
E1000_DEV_ID_82544GC_LOM
#define E1000_DEV_ID_82544GC_LOM
Definition: e1000_hw.h:51
E1000_DEV_ID_82576_QUAD_COPPER_ET2
#define E1000_DEV_ID_82576_QUAD_COPPER_ET2
Definition: e1000_hw.h:182
E1000_DEV_ID_PCH_SPT_I219_V
#define E1000_DEV_ID_PCH_SPT_I219_V
Definition: e1000_hw.h:142
E1000_DEV_ID_80003ES2LAN_COPPER_DPT
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT
Definition: e1000_hw.h:100
E1000_DEV_ID_ICH9_IGP_AMT
#define E1000_DEV_ID_ICH9_IGP_AMT
Definition: e1000_hw.h:115
E1000_DEV_ID_PCH_ICP_I219_LM9
#define E1000_DEV_ID_PCH_ICP_I219_LM9
Definition: e1000_hw.h:156
E1000_DEV_ID_ICH8_82567V_3
#define E1000_DEV_ID_ICH8_82567V_3
Definition: e1000_hw.h:104
E1000_DEV_ID_82540EP
#define E1000_DEV_ID_82540EP
Definition: e1000_hw.h:55
E1000_DEV_ID_82541ER_LOM
#define E1000_DEV_ID_82541ER_LOM
Definition: e1000_hw.h:73
E1000_DEV_ID_ICH9_IFE_G
#define E1000_DEV_ID_ICH9_IFE_G
Definition: e1000_hw.h:120
E1000_DEV_ID_PCH_SPT_I219_V2
#define E1000_DEV_ID_PCH_SPT_I219_V2
Definition: e1000_hw.h:144
E1000_DEV_ID_PCH_ADL_I219_LM17
#define E1000_DEV_ID_PCH_ADL_I219_LM17
Definition: e1000_hw.h:172
E1000_DEV_ID_82575EB_FIBER_SERDES
#define E1000_DEV_ID_82575EB_FIBER_SERDES
Definition: e1000_hw.h:191
E1000_DEV_ID_ICH9_IGP_M
#define E1000_DEV_ID_ICH9_IGP_M
Definition: e1000_hw.h:112
E1000_DEV_ID_82546GB_COPPER
#define E1000_DEV_ID_82546GB_COPPER
Definition: e1000_hw.h:65
E1000_DEV_ID_82576_QUAD_COPPER
#define E1000_DEV_ID_82576_QUAD_COPPER
Definition: e1000_hw.h:181
E1000_DEV_ID_I350_SERDES
#define E1000_DEV_ID_I350_SERDES
Definition: e1000_hw.h:201
E1000_DEV_ID_ICH10_R_BM_LF
#define E1000_DEV_ID_ICH10_R_BM_LF
Definition: e1000_hw.h:122
E1000_DEV_ID_82541GI_LF
#define E1000_DEV_ID_82541GI_LF
Definition: e1000_hw.h:76
E1000_DEV_ID_PCH_I218_LM2
#define E1000_DEV_ID_PCH_I218_LM2
Definition: e1000_hw.h:137
E1000_DEV_ID_PCH_TGP_I219_LM13
#define E1000_DEV_ID_PCH_TGP_I219_LM13
Definition: e1000_hw.h:164
E1000_DEV_ID_82576
#define E1000_DEV_ID_82576
Definition: e1000_hw.h:178
E1000_DEV_ID_82572EI_FIBER
#define E1000_DEV_ID_82572EI_FIBER
Definition: e1000_hw.h:91
E1000_DEV_ID_PCH_CNP_I219_LM7
#define E1000_DEV_ID_PCH_CNP_I219_LM7
Definition: e1000_hw.h:152
E1000_DEV_ID_82571EB_QUAD_COPPER
#define E1000_DEV_ID_82571EB_QUAD_COPPER
Definition: e1000_hw.h:86
E1000_DEV_ID_82575EB_COPPER
#define E1000_DEV_ID_82575EB_COPPER
Definition: e1000_hw.h:190
E1000_DEV_ID_PCH_D_HV_DM
#define E1000_DEV_ID_PCH_D_HV_DM
Definition: e1000_hw.h:129
E1000_DEV_ID_82545GM_COPPER
#define E1000_DEV_ID_82545GM_COPPER
Definition: e1000_hw.h:59
E1000_DEV_ID_ICH8_IGP_C
#define E1000_DEV_ID_ICH8_IGP_C
Definition: e1000_hw.h:107
E1000_DEV_ID_PCH_MTP_I219_V18
#define E1000_DEV_ID_PCH_MTP_I219_V18
Definition: e1000_hw.h:175
E1000_DEV_ID_82547EI
#define E1000_DEV_ID_82547EI
Definition: e1000_hw.h:78
E1000_DEV_ID_ICH9_BM
#define E1000_DEV_ID_ICH9_BM
Definition: e1000_hw.h:116
E1000_DEV_ID_PCH_CMP_I219_LM11
#define E1000_DEV_ID_PCH_CMP_I219_LM11
Definition: e1000_hw.h:160
E1000_DEV_ID_PCH_MTP_I219_V19
#define E1000_DEV_ID_PCH_MTP_I219_V19
Definition: e1000_hw.h:177
E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3
#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3
Definition: e1000_hw.h:70
E1000_DEV_ID_I354_BACKPLANE_1GBPS
#define E1000_DEV_ID_I354_BACKPLANE_1GBPS
Definition: e1000_hw.h:214
E1000_DEV_ID_80003ES2LAN_SERDES_DPT
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT
Definition: e1000_hw.h:101
E1000_DEV_ID_82545EM_COPPER
#define E1000_DEV_ID_82545EM_COPPER
Definition: e1000_hw.h:57
E1000_DEV_ID_I350_VF
#define E1000_DEV_ID_I350_VF
Definition: e1000_hw.h:188
E1000_DEV_ID_82541GI
#define E1000_DEV_ID_82541GI
Definition: e1000_hw.h:75
E1000_DEV_ID_82573E_IAMT
#define E1000_DEV_ID_82573E_IAMT
Definition: e1000_hw.h:95
E1000_DEV_ID_82571EB_COPPER
#define E1000_DEV_ID_82571EB_COPPER
Definition: e1000_hw.h:81
E1000_DEV_ID_82576_FIBER
#define E1000_DEV_ID_82576_FIBER
Definition: e1000_hw.h:179
E1000_DEV_ID_ICH8_IGP_AMT
#define E1000_DEV_ID_ICH8_IGP_AMT
Definition: e1000_hw.h:106
E1000_DEV_ID_82571EB_QUAD_FIBER
#define E1000_DEV_ID_82571EB_QUAD_FIBER
Definition: e1000_hw.h:88
E1000_DEV_ID_82540EM
#define E1000_DEV_ID_82540EM
Definition: e1000_hw.h:52
E1000_DEV_ID_PCH_SPT_I219_V5
#define E1000_DEV_ID_PCH_SPT_I219_V5
Definition: e1000_hw.h:149
E1000_DEV_ID_82580_COPPER_DUAL
#define E1000_DEV_ID_82580_COPPER_DUAL
Definition: e1000_hw.h:197
E1000_DEV_ID_82576_SERDES
#define E1000_DEV_ID_82576_SERDES
Definition: e1000_hw.h:180
E1000_DEV_ID_82580_FIBER
#define E1000_DEV_ID_82580_FIBER
Definition: e1000_hw.h:194
E1000_DEV_ID_PCH_CMP_I219_V11
#define E1000_DEV_ID_PCH_CMP_I219_V11
Definition: e1000_hw.h:161
E1000_DEV_ID_PCH_ADL_I219_V17
#define E1000_DEV_ID_PCH_ADL_I219_V17
Definition: e1000_hw.h:173
E1000_DEV_ID_PCH_ICP_I219_V9
#define E1000_DEV_ID_PCH_ICP_I219_V9
Definition: e1000_hw.h:157
E1000_DEV_ID_I210_COPPER
#define E1000_DEV_ID_I210_COPPER
Definition: e1000_hw.h:204
E1000_DEV_ID_PCH_TGP_I219_V15
#define E1000_DEV_ID_PCH_TGP_I219_V15
Definition: e1000_hw.h:169
E1000_DEV_ID_PCH_I218_V2
#define E1000_DEV_ID_PCH_I218_V2
Definition: e1000_hw.h:138
E1000_DEV_ID_82574L
#define E1000_DEV_ID_82574L
Definition: e1000_hw.h:97
E1000_DEV_ID_82545EM_FIBER
#define E1000_DEV_ID_82545EM_FIBER
Definition: e1000_hw.h:58
E1000_DEV_ID_ICH10_R_BM_V
#define E1000_DEV_ID_ICH10_R_BM_V
Definition: e1000_hw.h:123
E1000_DEV_ID_82580_COPPER
#define E1000_DEV_ID_82580_COPPER
Definition: e1000_hw.h:193
E1000_DEV_ID_PCH2_LV_LM
#define E1000_DEV_ID_PCH2_LV_LM
Definition: e1000_hw.h:131
E1000_DEV_ID_I210_SERDES_FLASHLESS
#define E1000_DEV_ID_I210_SERDES_FLASHLESS
Definition: e1000_hw.h:211
e1000_82580
@ e1000_82580
Definition: e1000_hw.h:271
e1000_ich8lan
@ e1000_ich8lan
Definition: e1000_hw.h:258
e1000_i354
@ e1000_i354
Definition: e1000_hw.h:273
e1000_i210
@ e1000_i210
Definition: e1000_hw.h:274
e1000_82547_rev_2
@ e1000_82547_rev_2
Definition: e1000_hw.h:251
e1000_i350
@ e1000_i350
Definition: e1000_hw.h:272
e1000_pch_mtp
@ e1000_pch_mtp
Definition: e1000_hw.h:268
e1000_82540
@ e1000_82540
Definition: e1000_hw.h:243
e1000_82573
@ e1000_82573
Definition: e1000_hw.h:254
e1000_pch2lan
@ e1000_pch2lan
Definition: e1000_hw.h:262
e1000_82572
@ e1000_82572
Definition: e1000_hw.h:253
e1000_82575
@ e1000_82575
Definition: e1000_hw.h:269
e1000_82543
@ e1000_82543
Definition: e1000_hw.h:241
e1000_pch_cnp
@ e1000_pch_cnp
Definition: e1000_hw.h:265
e1000_82576
@ e1000_82576
Definition: e1000_hw.h:270
e1000_pch_spt
@ e1000_pch_spt
Definition: e1000_hw.h:264
e1000_82544
@ e1000_82544
Definition: e1000_hw.h:242
e1000_82547
@ e1000_82547
Definition: e1000_hw.h:250
e1000_ich9lan
@ e1000_ich9lan
Definition: e1000_hw.h:259
e1000_82571
@ e1000_82571
Definition: e1000_hw.h:252
e1000_ich10lan
@ e1000_ich10lan
Definition: e1000_hw.h:260
e1000_82546
@ e1000_82546
Definition: e1000_hw.h:246
e1000_80003es2lan
@ e1000_80003es2lan
Definition: e1000_hw.h:257
e1000_i211
@ e1000_i211
Definition: e1000_hw.h:275
e1000_82545
@ e1000_82545
Definition: e1000_hw.h:244
e1000_82574
@ e1000_82574
Definition: e1000_hw.h:255
e1000_82546_rev_3
@ e1000_82546_rev_3
Definition: e1000_hw.h:247
e1000_pch_lpt
@ e1000_pch_lpt
Definition: e1000_hw.h:263
e1000_82583
@ e1000_82583
Definition: e1000_hw.h:256
e1000_pch_adp
@ e1000_pch_adp
Definition: e1000_hw.h:267
e1000_vfadapt_i350
@ e1000_vfadapt_i350
Definition: e1000_hw.h:277
e1000_pchlan
@ e1000_pchlan
Definition: e1000_hw.h:261
e1000_pch_tgp
@ e1000_pch_tgp
Definition: e1000_hw.h:266
e1000_82542
@ e1000_82542
Definition: e1000_hw.h:240
e1000_vfadapt
@ e1000_vfadapt
Definition: e1000_hw.h:276
E1000_DEV_ID_82573E
#define E1000_DEV_ID_82573E
Definition: e1000_hw.h:94
E1000_DEV_ID_80003ES2LAN_SERDES_SPT
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT
Definition: e1000_hw.h:103
E1000_DEV_ID_PCH_CNP_I219_LM6
#define E1000_DEV_ID_PCH_CNP_I219_LM6
Definition: e1000_hw.h:150
E1000_DEV_ID_82573L
#define E1000_DEV_ID_82573L
Definition: e1000_hw.h:96
E1000_DEV_ID_82546GB_FIBER
#define E1000_DEV_ID_82546GB_FIBER
Definition: e1000_hw.h:66
E1000_DEV_ID_DH89XXCC_SGMII
#define E1000_DEV_ID_DH89XXCC_SGMII
Definition: e1000_hw.h:217
E1000_DEV_ID_82544EI_FIBER
#define E1000_DEV_ID_82544EI_FIBER
Definition: e1000_hw.h:49
E1000_DEV_ID_ICH8_IFE
#define E1000_DEV_ID_ICH8_IFE
Definition: e1000_hw.h:108
E1000_REVISION_2
#define E1000_REVISION_2
Definition: e1000_hw.h:224
E1000_DEV_ID_ICH10_D_BM_LM
#define E1000_DEV_ID_ICH10_D_BM_LM
Definition: e1000_hw.h:124
E1000_DEV_ID_PCH_MTP_I219_LM18
#define E1000_DEV_ID_PCH_MTP_I219_LM18
Definition: e1000_hw.h:174
E1000_DEV_ID_82546GB_SERDES
#define E1000_DEV_ID_82546GB_SERDES
Definition: e1000_hw.h:67
E1000_DEV_ID_82546EB_COPPER
#define E1000_DEV_ID_82546EB_COPPER
Definition: e1000_hw.h:62
e1000_fc_none
@ e1000_fc_none
Definition: e1000_hw.h:370
e1000_fc_full
@ e1000_fc_full
Definition: e1000_hw.h:373
e1000_fc_tx_pause
@ e1000_fc_tx_pause
Definition: e1000_hw.h:372
e1000_fc_rx_pause
@ e1000_fc_rx_pause
Definition: e1000_hw.h:371
E1000_DEV_ID_82576_NS_SERDES
#define E1000_DEV_ID_82576_NS_SERDES
Definition: e1000_hw.h:184
E1000_DEV_ID_PCH_I218_LM3
#define E1000_DEV_ID_PCH_I218_LM3
Definition: e1000_hw.h:139
E1000_DEV_ID_82540EP_LOM
#define E1000_DEV_ID_82540EP_LOM
Definition: e1000_hw.h:54
E1000_DEV_ID_PCH_CMP_I219_V10
#define E1000_DEV_ID_PCH_CMP_I219_V10
Definition: e1000_hw.h:159
E1000_DEV_ID_82543GC_FIBER
#define E1000_DEV_ID_82543GC_FIBER
Definition: e1000_hw.h:46
E1000_DEV_ID_PCH_D_HV_DC
#define E1000_DEV_ID_PCH_D_HV_DC
Definition: e1000_hw.h:130
E1000_DEV_ID_ICH9_IFE_GT
#define E1000_DEV_ID_ICH9_IFE_GT
Definition: e1000_hw.h:119
E1000_DEV_ID_ICH9_IGP_M_AMT
#define E1000_DEV_ID_ICH9_IGP_M_AMT
Definition: e1000_hw.h:113
E1000_DEV_ID_82571EB_SERDES_QUAD
#define E1000_DEV_ID_82571EB_SERDES_QUAD
Definition: e1000_hw.h:85
E1000_DEV_ID_82544EI_COPPER
#define E1000_DEV_ID_82544EI_COPPER
Definition: e1000_hw.h:48
E1000_DEV_ID_82544GC_COPPER
#define E1000_DEV_ID_82544GC_COPPER
Definition: e1000_hw.h:50
E1000_DEV_ID_80003ES2LAN_COPPER_SPT
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT
Definition: e1000_hw.h:102
E1000_DEV_ID_PCH_ICP_I219_V8
#define E1000_DEV_ID_PCH_ICP_I219_V8
Definition: e1000_hw.h:155
E1000_DEV_ID_82576_SERDES_QUAD
#define E1000_DEV_ID_82576_SERDES_QUAD
Definition: e1000_hw.h:185
e1000_media_type_unknown
@ e1000_media_type_unknown
Definition: e1000_hw.h:282
e1000_media_type_fiber
@ e1000_media_type_fiber
Definition: e1000_hw.h:284
e1000_media_type_internal_serdes
@ e1000_media_type_internal_serdes
Definition: e1000_hw.h:285
e1000_media_type_copper
@ e1000_media_type_copper
Definition: e1000_hw.h:283
E1000_DEV_ID_PCH_LPTLP_I218_V
#define E1000_DEV_ID_PCH_LPTLP_I218_V
Definition: e1000_hw.h:136
E1000_DEV_ID_PCH_CNP_I219_V7
#define E1000_DEV_ID_PCH_CNP_I219_V7
Definition: e1000_hw.h:153
E1000_DEV_ID_PCH_CNP_I219_V6
#define E1000_DEV_ID_PCH_CNP_I219_V6
Definition: e1000_hw.h:151
E1000_DEV_ID_PCH_SPT_I219_LM5
#define E1000_DEV_ID_PCH_SPT_I219_LM5
Definition: e1000_hw.h:148
E1000_DEV_ID_PCH_ICP_I219_LM8
#define E1000_DEV_ID_PCH_ICP_I219_LM8
Definition: e1000_hw.h:154
E1000_DEV_ID_82541GI_MOBILE
#define E1000_DEV_ID_82541GI_MOBILE
Definition: e1000_hw.h:77
E1000_DEV_ID_I210_FIBER
#define E1000_DEV_ID_I210_FIBER
Definition: e1000_hw.h:207
E1000_DEV_ID_82571EB_SERDES
#define E1000_DEV_ID_82571EB_SERDES
Definition: e1000_hw.h:83
E1000_DEV_ID_I354_SGMII
#define E1000_DEV_ID_I354_SGMII
Definition: e1000_hw.h:215
E1000_DEV_ID_82580_SGMII
#define E1000_DEV_ID_82580_SGMII
Definition: e1000_hw.h:196
E1000_DEV_ID_PCH_LPT_I217_LM
#define E1000_DEV_ID_PCH_LPT_I217_LM
Definition: e1000_hw.h:133
E1000_DEV_ID_PCH2_LV_V
#define E1000_DEV_ID_PCH2_LV_V
Definition: e1000_hw.h:132
E1000_DEV_ID_PCH_TGP_I219_V13
#define E1000_DEV_ID_PCH_TGP_I219_V13
Definition: e1000_hw.h:165
E1000_DEV_ID_82580_QUAD_FIBER
#define E1000_DEV_ID_82580_QUAD_FIBER
Definition: e1000_hw.h:198
E1000_DEV_ID_I350_COPPER
#define E1000_DEV_ID_I350_COPPER
Definition: e1000_hw.h:199
E1000_DEV_ID_DH89XXCC_SERDES
#define E1000_DEV_ID_DH89XXCC_SERDES
Definition: e1000_hw.h:218
E1000_DEV_ID_ICH9_IFE
#define E1000_DEV_ID_ICH9_IFE
Definition: e1000_hw.h:118
E1000_DEV_ID_ICH10_R_BM_LM
#define E1000_DEV_ID_ICH10_R_BM_LM
Definition: e1000_hw.h:121
E1000_DEV_ID_PCH_MTP_I219_LM19
#define E1000_DEV_ID_PCH_MTP_I219_LM19
Definition: e1000_hw.h:176
E1000_DEV_ID_I350_FIBER
#define E1000_DEV_ID_I350_FIBER
Definition: e1000_hw.h:200
E1000_DEV_ID_82546GB_PCIE
#define E1000_DEV_ID_82546GB_PCIE
Definition: e1000_hw.h:68
E1000_DEV_ID_ICH9_IGP_C
#define E1000_DEV_ID_ICH9_IGP_C
Definition: e1000_hw.h:117
E1000_DEV_ID_DH89XXCC_SFP
#define E1000_DEV_ID_DH89XXCC_SFP
Definition: e1000_hw.h:220
E1000_DEV_ID_DH89XXCC_BACKPLANE
#define E1000_DEV_ID_DH89XXCC_BACKPLANE
Definition: e1000_hw.h:219
E1000_DEV_ID_82541EI
#define E1000_DEV_ID_82541EI
Definition: e1000_hw.h:71
e1000_pci_clear_mwi
void e1000_pci_clear_mwi(struct e1000_hw *hw)
Definition: e1000_osdep.c:64
E1000_DEV_ID_PCH_CMP_I219_LM10
#define E1000_DEV_ID_PCH_CMP_I219_LM10
Definition: e1000_hw.h:158
E1000_DEV_ID_82546EB_FIBER
#define E1000_DEV_ID_82546EB_FIBER
Definition: e1000_hw.h:63
E1000_DEV_ID_ICH10_D_BM_LF
#define E1000_DEV_ID_ICH10_D_BM_LF
Definition: e1000_hw.h:125
E1000_DEV_ID_82580_SERDES
#define E1000_DEV_ID_82580_SERDES
Definition: e1000_hw.h:195
E1000_DEV_ID_PCH_ADL_I219_LM16
#define E1000_DEV_ID_PCH_ADL_I219_LM16
Definition: e1000_hw.h:170
E1000_DEV_ID_82546GB_QUAD_COPPER
#define E1000_DEV_ID_82546GB_QUAD_COPPER
Definition: e1000_hw.h:69
E1000_DEV_ID_PCH_TGP_I219_LM14
#define E1000_DEV_ID_PCH_TGP_I219_LM14
Definition: e1000_hw.h:166
E1000_DEV_ID_82575GB_QUAD_COPPER
#define E1000_DEV_ID_82575GB_QUAD_COPPER
Definition: e1000_hw.h:192
E1000_DEV_ID_I210_COPPER_FLASHLESS
#define E1000_DEV_ID_I210_COPPER_FLASHLESS
Definition: e1000_hw.h:210
E1000_DEV_ID_I210_SGMII
#define E1000_DEV_ID_I210_SGMII
Definition: e1000_hw.h:209
E1000_DEV_ID_82571EB_FIBER
#define E1000_DEV_ID_82571EB_FIBER
Definition: e1000_hw.h:82
E1000_DEV_ID_82540EP_LP
#define E1000_DEV_ID_82540EP_LP
Definition: e1000_hw.h:56
E1000_DEV_ID_82541EI_MOBILE
#define E1000_DEV_ID_82541EI_MOBILE
Definition: e1000_hw.h:72
E1000_DEV_ID_82571EB_QUAD_COPPER_LP
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP
Definition: e1000_hw.h:89
E1000_DEV_ID_ICH8_IGP_M
#define E1000_DEV_ID_ICH8_IGP_M
Definition: e1000_hw.h:111
E1000_DEV_ID_I210_SGMII_FLASHLESS
#define E1000_DEV_ID_I210_SGMII_FLASHLESS
Definition: e1000_hw.h:212
E1000_DEV_ID_PCH_SPT_I219_LM4
#define E1000_DEV_ID_PCH_SPT_I219_LM4
Definition: e1000_hw.h:146
E1000_DEV_ID_82547EI_MOBILE
#define E1000_DEV_ID_82547EI_MOBILE
Definition: e1000_hw.h:79
E1000_DEV_ID_82546EB_QUAD_COPPER
#define E1000_DEV_ID_82546EB_QUAD_COPPER
Definition: e1000_hw.h:64
E1000_DEV_ID_82545GM_FIBER
#define E1000_DEV_ID_82545GM_FIBER
Definition: e1000_hw.h:60
E1000_DEV_ID_82576_NS
#define E1000_DEV_ID_82576_NS
Definition: e1000_hw.h:183
E1000_DEV_ID_ICH8_IFE_GT
#define E1000_DEV_ID_ICH8_IFE_GT
Definition: e1000_hw.h:109
E1000_DEV_ID_82543GC_COPPER
#define E1000_DEV_ID_82543GC_COPPER
Definition: e1000_hw.h:47
E1000_DEV_ID_82572EI_SERDES
#define E1000_DEV_ID_82572EI_SERDES
Definition: e1000_hw.h:92
E1000_DEV_ID_I210_COPPER_IT
#define E1000_DEV_ID_I210_COPPER_IT
Definition: e1000_hw.h:206
E1000_DEV_ID_PCH_I218_V3
#define E1000_DEV_ID_PCH_I218_V3
Definition: e1000_hw.h:140
E1000_DEV_ID_82572EI_COPPER
#define E1000_DEV_ID_82572EI_COPPER
Definition: e1000_hw.h:90
E1000_DEV_ID_PCH_M_HV_LC
#define E1000_DEV_ID_PCH_M_HV_LC
Definition: e1000_hw.h:128
E1000_DEV_ID_82583V
#define E1000_DEV_ID_82583V
Definition: e1000_hw.h:99
E1000_DEV_ID_82541ER
#define E1000_DEV_ID_82541ER
Definition: e1000_hw.h:74
e1000_resume_workarounds_pchlan
u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5800
e1000_suspend_workarounds_ich8lan
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5666
e1000_igp3_phy_powerdown_workaround_ich8lan
void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5572
e1000_lv_jumbo_workaround_ich8lan
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
Definition: e1000_ich8lan.c:2782
e1000_disable_ulp_lpt_lp
s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
Definition: e1000_ich8lan.c:1417
e1000_copy_rx_addrs_to_phy_ich8lan
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2721
BM_WUC
#define BM_WUC
Definition: e1000_ich8lan.h:149
E1000_TARC0_CB_MULTIQ_2_REQ
#define E1000_TARC0_CB_MULTIQ_2_REQ
Definition: e1000_ich8lan.h:129
BM_RCTL_BAM
#define BM_RCTL_BAM
Definition: e1000_ich8lan.h:162
BM_RCTL_UPE
#define BM_RCTL_UPE
Definition: e1000_ich8lan.h:158
BM_RCTL_MO_SHIFT
#define BM_RCTL_MO_SHIFT
Definition: e1000_ich8lan.h:160
BM_RCTL
#define BM_RCTL
Definition: e1000_ich8lan.h:148
BM_RCTL_RFCE
#define BM_RCTL_RFCE
Definition: e1000_ich8lan.h:164
BM_RCTL_MO_MASK
#define BM_RCTL_MO_MASK
Definition: e1000_ich8lan.h:161
BM_RCTL_MPE
#define BM_RCTL_MPE
Definition: e1000_ich8lan.h:159
BM_WUFC
#define BM_WUFC
Definition: e1000_ich8lan.h:150
BM_RCTL_PMCF
#define BM_RCTL_PMCF
Definition: e1000_ich8lan.h:163
BM_MTA
#define BM_MTA(_i)
Definition: e1000_ich8lan.h:156
E1000_FLASH_BASE_ADDR
#define E1000_FLASH_BASE_ADDR
Definition: e1000_ich8lan.h:126
e1000_clear_hw_cntrs_base_generic
void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:666
e1000_enable_mng_pass_thru
bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
Definition: e1000_manage.c:343
e1000_get_fw_version
void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
Definition: e1000_nvm.c:1286
msec_delay
#define msec_delay(x)
Definition: e1000_osdep.h:103
CMD_MEM_WRT_INVALIDATE
#define CMD_MEM_WRT_INVALIDATE
Definition: e1000_osdep.h:118
u64
uint64_t u64
Definition: e1000_osdep.h:121
E1000_WRITE_REG_ARRAY
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value)
Definition: e1000_osdep.h:206
E1000_READ_REG_ARRAY
#define E1000_READ_REG_ARRAY(hw, reg, index)
Definition: e1000_osdep.h:201
u8
uint8_t u8
Definition: e1000_osdep.h:124
E1000_REGISTER
#define E1000_REGISTER(hw, reg)
Definition: e1000_osdep.h:174
E1000_READ_OFFSET
#define E1000_READ_OFFSET(hw, offset)
Definition: e1000_osdep.h:180
E1000_WRITE_OFFSET
#define E1000_WRITE_OFFSET(hw, offset, value)
Definition: e1000_osdep.h:185
E1000_WRITE_FLUSH
#define E1000_WRITE_FLUSH(a)
Definition: e1000_osdep.h:177
E1000_WRITE_REG
#define E1000_WRITE_REG(hw, reg, value)
Definition: e1000_osdep.h:196
u16
uint16_t u16
Definition: e1000_osdep.h:123
E1000_READ_REG
#define E1000_READ_REG(hw, reg)
Definition: e1000_osdep.h:191
u32
uint32_t u32
Definition: e1000_osdep.h:122
ASSERT_CTX_LOCK_HELD
#define ASSERT_CTX_LOCK_HELD(hw)
Definition: e1000_osdep.h:149
e1000_read_phy_reg_mdic
s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:291
e1000_copper_link_autoneg
s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
Definition: e1000_phy.c:1635
e1000_write_phy_reg_mdic
s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:356
IGP01E1000_PHY_PAGE_SELECT
#define IGP01E1000_PHY_PAGE_SELECT
Definition: e1000_phy.h:139
BM_WUC_ENABLE_PAGE
#define BM_WUC_ENABLE_PAGE
Definition: e1000_phy.h:159
IGP_PAGE_SHIFT
#define IGP_PAGE_SHIFT
Definition: e1000_phy.h:141
BM_WUC_ENABLE_BIT
#define BM_WUC_ENABLE_BIT
Definition: e1000_phy.h:161
IGP02E1000_PHY_POWER_MGMT
#define IGP02E1000_PHY_POWER_MGMT
Definition: e1000_phy.h:138
BM_WUC_HOST_WU_BIT
#define BM_WUC_HOST_WU_BIT
Definition: e1000_phy.h:162
BM_WUC_ENABLE_REG
#define BM_WUC_ENABLE_REG
Definition: e1000_phy.h:160
E1000_RFC
#define E1000_RFC
Definition: e1000_regs.h:362
E1000_TORH
#define E1000_TORH
Definition: e1000_regs.h:369
E1000_IMS
#define E1000_IMS
Definition: e1000_regs.h:82
E1000_MRQC
#define E1000_MRQC
Definition: e1000_regs.h:557
E1000_GORCH
#define E1000_GORCH
Definition: e1000_regs.h:357
E1000_RXERRC
#define E1000_RXERRC
Definition: e1000_regs.h:329
E1000_TDBAL
#define E1000_TDBAL(_n)
Definition: e1000_regs.h:265
E1000_TOTH
#define E1000_TOTH
Definition: e1000_regs.h:371
E1000_PTC1522
#define E1000_PTC1522
Definition: e1000_regs.h:379
E1000_TDH
#define E1000_TDH(_n)
Definition: e1000_regs.h:271
E1000_PTC255
#define E1000_PTC255
Definition: e1000_regs.h:376
E1000_ECOL
#define E1000_ECOL
Definition: e1000_regs.h:332
E1000_RDLEN
#define E1000_RDLEN(_n)
Definition: e1000_regs.h:250
E1000_ICTXQMTC
#define E1000_ICTXQMTC
Definition: e1000_regs.h:391
E1000_PTC127
#define E1000_PTC127
Definition: e1000_regs.h:375
E1000_TDT
#define E1000_TDT(_n)
Definition: e1000_regs.h:276
E1000_PTC511
#define E1000_PTC511
Definition: e1000_regs.h:377
E1000_DMCTXTH
#define E1000_DMCTXTH
Definition: e1000_regs.h:687
E1000_GORCL
#define E1000_GORCL
Definition: e1000_regs.h:356
E1000_PRC255
#define E1000_PRC255
Definition: e1000_regs.h:348
E1000_ICRXDMTC
#define E1000_ICRXDMTC
Definition: e1000_regs.h:392
E1000_TDFPC
#define E1000_TDFPC
Definition: e1000_regs.h:311
E1000_WUC
#define E1000_WUC
Definition: e1000_regs.h:505
E1000_MANC
#define E1000_MANC
Definition: e1000_regs.h:509
E1000_TPT
#define E1000_TPT
Definition: e1000_regs.h:373
E1000_PRC127
#define E1000_PRC127
Definition: e1000_regs.h:347
E1000_EIAC
#define E1000_EIAC
Definition: e1000_regs.h:99
E1000_SCC
#define E1000_SCC
Definition: e1000_regs.h:331
E1000_DMACR
#define E1000_DMACR
Definition: e1000_regs.h:686
E1000_RETA
#define E1000_RETA(_i)
Definition: e1000_regs.h:563
E1000_XONRXC
#define E1000_XONRXC
Definition: e1000_regs.h:341
E1000_IVAR0
#define E1000_IVAR0
Definition: e1000_regs.h:102
E1000_TPR
#define E1000_TPR
Definition: e1000_regs.h:372
E1000_EIMC
#define E1000_EIMC
Definition: e1000_regs.h:98
E1000_RSSRK
#define E1000_RSSRK(_i)
Definition: e1000_regs.h:565
E1000_PRC64
#define E1000_PRC64
Definition: e1000_regs.h:346
E1000_ICRXPTC
#define E1000_ICRXPTC
Definition: e1000_regs.h:386
E1000_RXPBS
#define E1000_RXPBS
Definition: e1000_regs.h:167
E1000_ICTXATC
#define E1000_ICTXATC
Definition: e1000_regs.h:389
E1000_TNCRS
#define E1000_TNCRS
Definition: e1000_regs.h:337
E1000_RJC
#define E1000_RJC
Definition: e1000_regs.h:364
E1000_EIMS
#define E1000_EIMS
Definition: e1000_regs.h:97
E1000_XONTXC
#define E1000_XONTXC
Definition: e1000_regs.h:342
E1000_COLC
#define E1000_COLC
Definition: e1000_regs.h:335
E1000_MANC2H
#define E1000_MANC2H
Definition: e1000_regs.h:527
E1000_RCTL
#define E1000_RCTL
Definition: e1000_regs.h:89
E1000_RADV
#define E1000_RADV
Definition: e1000_regs.h:171
E1000_RNBC
#define E1000_RNBC
Definition: e1000_regs.h:360
E1000_GOTCH
#define E1000_GOTCH
Definition: e1000_regs.h:359
E1000_GPRC
#define E1000_GPRC
Definition: e1000_regs.h:352
E1000_ICTXQEC
#define E1000_ICTXQEC
Definition: e1000_regs.h:390
E1000_WUFC
#define E1000_WUFC
Definition: e1000_regs.h:506
E1000_BPTC
#define E1000_BPTC
Definition: e1000_regs.h:381
E1000_RXCSUM
#define E1000_RXCSUM
Definition: e1000_regs.h:493
E1000_SWSM
#define E1000_SWSM
Definition: e1000_regs.h:544
E1000_ITR
#define E1000_ITR
Definition: e1000_regs.h:80
E1000_TCTL
#define E1000_TCTL
Definition: e1000_regs.h:104
E1000_ICRXOC
#define E1000_ICRXOC
Definition: e1000_regs.h:393
E1000_GPIE
#define E1000_GPIE
Definition: e1000_regs.h:101
E1000_LATECOL
#define E1000_LATECOL
Definition: e1000_regs.h:334
E1000_STATUS
#define E1000_STATUS
Definition: e1000_regs.h:41
E1000_PCIEMISC
#define E1000_PCIEMISC
Definition: e1000_regs.h:692
E1000_SRRCTL
#define E1000_SRRCTL(_n)
Definition: e1000_regs.h:252
E1000_TDFH
#define E1000_TDFH
Definition: e1000_regs.h:307
E1000_ALGNERRC
#define E1000_ALGNERRC
Definition: e1000_regs.h:327
E1000_TXDCTL
#define E1000_TXDCTL(_n)
Definition: e1000_regs.h:278
E1000_FCRTC
#define E1000_FCRTC
Definition: e1000_regs.h:691
E1000_ICRXATC
#define E1000_ICRXATC
Definition: e1000_regs.h:387
E1000_DC
#define E1000_DC
Definition: e1000_regs.h:336
E1000_SEC
#define E1000_SEC
Definition: e1000_regs.h:338
E1000_TDBAH
#define E1000_TDBAH(_n)
Definition: e1000_regs.h:267
E1000_DMCTLX
#define E1000_DMCTLX
Definition: e1000_regs.h:688
E1000_XOFFTXC
#define E1000_XOFFTXC
Definition: e1000_regs.h:344
E1000_GPTC
#define E1000_GPTC
Definition: e1000_regs.h:355
E1000_RXDCTL
#define E1000_RXDCTL(_n)
Definition: e1000_regs.h:261
E1000_PTC1023
#define E1000_PTC1023
Definition: e1000_regs.h:378
E1000_MPTC
#define E1000_MPTC
Definition: e1000_regs.h:380
E1000_MCC
#define E1000_MCC
Definition: e1000_regs.h:333
E1000_RDBAL
#define E1000_RDBAL(_n)
Definition: e1000_regs.h:246
E1000_TDFHS
#define E1000_TDFHS
Definition: e1000_regs.h:309
E1000_CTRL
#define E1000_CTRL
Definition: e1000_regs.h:39
E1000_TIPG
#define E1000_TIPG
Definition: e1000_regs.h:106
E1000_SYMERRS
#define E1000_SYMERRS
Definition: e1000_regs.h:328
E1000_PRC1522
#define E1000_PRC1522
Definition: e1000_regs.h:351
E1000_RUC
#define E1000_RUC
Definition: e1000_regs.h:361
E1000_IMC
#define E1000_IMC
Definition: e1000_regs.h:83
E1000_RDT
#define E1000_RDT(_n)
Definition: e1000_regs.h:259
E1000_TDFT
#define E1000_TDFT
Definition: e1000_regs.h:308
E1000_RDBAH
#define E1000_RDBAH(_n)
Definition: e1000_regs.h:248
E1000_CRCERRS
#define E1000_CRCERRS
Definition: e1000_regs.h:326
E1000_RDH
#define E1000_RDH(_n)
Definition: e1000_regs.h:254
E1000_EITR
#define E1000_EITR(_n)
Definition: e1000_regs.h:95
E1000_RLEC
#define E1000_RLEC
Definition: e1000_regs.h:340
E1000_ICTXPTC
#define E1000_ICTXPTC
Definition: e1000_regs.h:388
E1000_TIDV
#define E1000_TIDV
Definition: e1000_regs.h:322
E1000_MSIXBM
#define E1000_MSIXBM(_i)
Definition: e1000_regs.h:561
E1000_TARC
#define E1000_TARC(_n)
Definition: e1000_regs.h:284
E1000_TDLEN
#define E1000_TDLEN(_n)
Definition: e1000_regs.h:269
E1000_PRC1023
#define E1000_PRC1023
Definition: e1000_regs.h:350
E1000_IVAR_MISC
#define E1000_IVAR_MISC
Definition: e1000_regs.h:103
E1000_MPC
#define E1000_MPC
Definition: e1000_regs.h:330
E1000_BPRC
#define E1000_BPRC
Definition: e1000_regs.h:353
E1000_EIAM
#define E1000_EIAM
Definition: e1000_regs.h:100
E1000_TADV
#define E1000_TADV
Definition: e1000_regs.h:323
E1000_PRC511
#define E1000_PRC511
Definition: e1000_regs.h:349
E1000_TSCTFC
#define E1000_TSCTFC
Definition: e1000_regs.h:383
E1000_ICS
#define E1000_ICS
Definition: e1000_regs.h:81
E1000_ROC
#define E1000_ROC
Definition: e1000_regs.h:363
E1000_CEXTERR
#define E1000_CEXTERR
Definition: e1000_regs.h:339
E1000_MTA
#define E1000_MTA
Definition: e1000_regs.h:496
E1000_ICR
#define E1000_ICR
Definition: e1000_regs.h:79
E1000_RLPML
#define E1000_RLPML
Definition: e1000_regs.h:494
E1000_IOSFPC
#define E1000_IOSFPC
Definition: e1000_regs.h:118
E1000_THSTAT
#define E1000_THSTAT
Definition: e1000_regs.h:704
E1000_DMCRTRH
#define E1000_DMCRTRH
Definition: e1000_regs.h:689
E1000_FCRUC
#define E1000_FCRUC
Definition: e1000_regs.h:345
E1000_PTC64
#define E1000_PTC64
Definition: e1000_regs.h:374
E1000_MPRC
#define E1000_MPRC
Definition: e1000_regs.h:354
E1000_GOTCL
#define E1000_GOTCL
Definition: e1000_regs.h:358
E1000_IAC
#define E1000_IAC
Definition: e1000_regs.h:384
E1000_PBA
#define E1000_PBA
Definition: e1000_regs.h:115
E1000_VET
#define E1000_VET
Definition: e1000_regs.h:78
E1000_TSCTC
#define E1000_TSCTC
Definition: e1000_regs.h:382
E1000_IVAR
#define E1000_IVAR
Definition: e1000_regs.h:85
E1000_RDTR
#define E1000_RDTR
Definition: e1000_regs.h:170
E1000_CTRL_EXT
#define E1000_CTRL_EXT
Definition: e1000_regs.h:44
E1000_XOFFRXC
#define E1000_XOFFRXC
Definition: e1000_regs.h:343
E1000_RFCTL
#define E1000_RFCTL
Definition: e1000_regs.h:495
em_dump_rs
void em_dump_rs(struct e1000_softc *sc)
Definition: em_txrx.c:94
em_debug_sbp
static int em_debug_sbp
Definition: if_em.c:521
QUEUE_NAME_LEN
#define QUEUE_NAME_LEN
em_sysctl_reg_handler
static int em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4199
em_sysctl_eee
static int em_sysctl_eee(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4768
em_copy_maddr
static u_int em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
Definition: if_em.c:1694
em_release_hw_control
static void em_release_hw_control(struct e1000_softc *)
Definition: if_em.c:3699
em_if_init
static void em_if_init(if_ctx_t)
Definition: if_em.c:1293
em_if_vlan_filter_capable
static bool em_if_vlan_filter_capable(if_ctx_t)
Definition: if_em.c:3445
E1000_MNG2HOST_PORT_623
#define E1000_MNG2HOST_PORT_623
em_methods
static device_method_t em_methods[]
Definition: if_em.c:351
CSUM_TSO
#define CSUM_TSO
Definition: if_em.c:490
em_if_intr_enable
static void em_if_intr_enable(if_ctx_t)
Definition: if_em.c:3562
em_allocate_pci_resources
static int em_allocate_pci_resources(if_ctx_t)
Definition: if_em.c:1956
em_if_stop
static void em_if_stop(if_ctx_t)
Definition: if_em.c:1904
em_get_regs
static int em_get_regs(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:614
em_if_driver
static driver_t em_if_driver
Definition: if_em.c:436
em_fw_version_locked
static void em_fw_version_locked(if_ctx_t)
Definition: if_em.c:4493
em_if_vlan_filter_write
static void em_if_vlan_filter_write(struct e1000_softc *)
Definition: if_em.c:3495
em_msix_link
static int em_msix_link(void *)
Definition: if_em.c:1504
em_setup_vlan_hw_support
static void em_setup_vlan_hw_support(if_ctx_t ctx)
Definition: if_em.c:3521
em_tx_abs_int_delay_dflt
static int em_tx_abs_int_delay_dflt
Definition: if_em.c:507
em_sysctl_int_delay
static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4667
em_intr
int em_intr(void *)
Definition: if_em.c:1401
em_rx_process_limit
static int em_rx_process_limit
Definition: if_em.c:526
em_release_manageability
static void em_release_manageability(struct e1000_softc *)
Definition: if_em.c:3653
em_if_tx_queues_alloc
static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int)
Definition: if_em.c:2911
em_initialize_rss_mapping
static void em_initialize_rss_mapping(struct e1000_softc *sc)
Definition: if_em.c:2728
em_get_rs
static int em_get_rs(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4805
em_tx_int_delay_dflt
static int em_tx_int_delay_dflt
Definition: if_em.c:500
em_if_vlan_filter_disable
static void em_if_vlan_filter_disable(struct e1000_softc *)
Definition: if_em.c:3484
em_if_rx_queue_intr_enable
static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t)
Definition: if_em.c:1444
em_if_set_promisc
static int em_if_set_promisc(if_ctx_t, int)
Definition: if_em.c:1656
igb_if_intr_enable
static void igb_if_intr_enable(if_ctx_t)
Definition: if_em.c:3589
em_if_update_admin_status
static void em_if_update_admin_status(if_ctx_t)
Definition: if_em.c:1784
igb_register
static void * igb_register(device_t)
Definition: if_em.c:733
em_print_fw_version
static void em_print_fw_version(struct e1000_softc *)
Definition: if_em.c:4560
em_max_interrupt_rate
static int em_max_interrupt_rate
Definition: if_em.c:540
em_if_suspend
static int em_if_suspend(if_ctx_t)
Definition: if_em.c:1210
IFLIB_PNP_INFO
IFLIB_PNP_INFO(pci, em, em_vendor_info_array)
em_initialize_receive_unit
static void em_initialize_receive_unit(if_ctx_t)
Definition: if_em.c:3172
em_if_tx_queue_intr_enable
static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t)
Definition: if_em.c:1454
em_set_num_queues
static int em_set_num_queues(if_ctx_t ctx)
Definition: if_em.c:739
em_set_flowcntl
static int em_set_flowcntl(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4730
LEM_CAPS
#define LEM_CAPS
Definition: if_em.c:768
igb_if_rx_queue_intr_enable
static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t)
Definition: if_em.c:1464
em_if_rx_queues_alloc
static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int)
Definition: if_em.c:2960
igb_mac_min
#define igb_mac_min
Definition: if_em.c:35
igb_if_methods
static device_method_t igb_if_methods[]
Definition: if_em.c:440
em_msix_que
static int em_msix_que(void *arg)
Definition: if_em.c:1489
em_if_attach_pre
static int em_if_attach_pre(if_ctx_t)
Definition: if_em.c:793
E1000_MNG2HOST_PORT_664
#define E1000_MNG2HOST_PORT_664
igb_initialize_rss_mapping
static void igb_initialize_rss_mapping(struct e1000_softc *sc)
Definition: if_em.c:2769
em_identify_hardware
static void em_identify_hardware(if_ctx_t)
Definition: if_em.c:1924
eee_setting
static int eee_setting
Definition: if_em.c:533
em_add_hw_stats
static void em_add_hw_stats(struct e1000_softc *)
Definition: if_em.c:4213
SYSCTL_INT
SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, &em_disable_crc_stripping, 0, "Disable CRC Stripping")
em_if_vlan_filter_enable
static void em_if_vlan_filter_enable(struct e1000_softc *)
Definition: if_em.c:3472
lem_txrx
struct if_txrx lem_txrx
Definition: em_txrx.c:80
EM_TICKS_TO_USECS
#define EM_TICKS_TO_USECS(ticks)
Definition: if_em.c:482
em_update_stats_counters
static void em_update_stats_counters(struct e1000_softc *)
Definition: if_em.c:4059
em_vendor_info_array
static pci_vendor_info_t em_vendor_info_array[]
Definition: if_em.c:52
em_free_pci_resources
static void em_free_pci_resources(if_ctx_t)
Definition: if_em.c:2249
em_if_media_status
static void em_if_media_status(if_ctx_t, struct ifmediareq *)
Definition: if_em.c:1558
em_reset
static void em_reset(if_ctx_t)
Definition: if_em.c:2472
igb_if_driver
static driver_t igb_if_driver
Definition: if_em.c:474
em_get_wakeup
static void em_get_wakeup(if_ctx_t)
Definition: if_em.c:3737
em_sbuf_fw_version
static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *)
Definition: if_em.c:4531
em_rx_int_delay_dflt
static int em_rx_int_delay_dflt
Definition: if_em.c:501
EM_CAPS
#define EM_CAPS
Definition: if_em.c:772
igb_sctx_init
static struct if_shared_ctx igb_sctx_init
Definition: if_em.c:580
em_if_get_counter
static uint64_t em_if_get_counter(if_ctx_t, ift_counter)
Definition: if_em.c:4157
em_print_debug_info
static void em_print_debug_info(struct e1000_softc *)
Definition: if_em.c:4832
em_print_nvm_info
static void em_print_nvm_info(struct e1000_softc *)
Definition: if_em.c:4640
em_if_detach
static int em_if_detach(if_ctx_t)
Definition: if_em.c:1177
igb_if_intr_disable
static void igb_if_intr_disable(if_ctx_t)
Definition: if_em.c:3607
igb_driver
static driver_t igb_driver
Definition: if_em.c:389
em_sctx_init
static struct if_shared_ctx em_sctx_init
Definition: if_em.c:553
igb_methods
static device_method_t igb_methods[]
Definition: if_em.c:363
em_setup_interface
static int em_setup_interface(if_ctx_t)
Definition: if_em.c:2869
em_if_timer
static void em_if_timer(if_ctx_t, uint16_t)
Definition: if_em.c:1774
BSIZEPKT_ROUNDUP
#define BSIZEPKT_ROUNDUP
Definition: if_em.c:3169
em_initialize_transmit_unit
static void em_initialize_transmit_unit(if_ctx_t)
Definition: if_em.c:3033
em_rx_abs_int_delay_dflt
static int em_rx_abs_int_delay_dflt
Definition: if_em.c:508
em_if_media_change
static int em_if_media_change(if_ctx_t)
Definition: if_em.c:1609
RSSKEYLEN
#define RSSKEYLEN
Definition: if_em.c:2726
em_disable_crc_stripping
static int em_disable_crc_stripping
Definition: if_em.c:496
em_if_vlan_register
static void em_if_vlan_register(if_ctx_t, u16)
Definition: if_em.c:3419
igb_devclass
static devclass_t igb_devclass
Definition: if_em.c:393
em_enable_wakeup
static void em_enable_wakeup(if_ctx_t)
Definition: if_em.c:3859
igb_init_dmac
static void igb_init_dmac(struct e1000_softc *sc, u32 pba)
Definition: if_em.c:2362
em_driver
static driver_t em_driver
Definition: if_em.c:376
em_if_multi_set
static void em_if_multi_set(if_ctx_t)
Definition: if_em.c:1713
em_sysctl_nvm_info
static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4616
IGB_REGS_LEN
#define IGB_REGS_LEN
Definition: if_em.c:612
igb_if_tx_queue_intr_enable
static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t)
Definition: if_em.c:1474
em_if_needs_restart
static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event)
global_quad_port_a
static int global_quad_port_a
Definition: if_em.c:547
em_if_intr_disable
static void em_if_intr_disable(if_ctx_t)
Definition: if_em.c:3577
em_if_msix_intr_assign
static int em_if_msix_intr_assign(if_ctx_t, int)
Definition: if_em.c:2017
em_if_methods
static device_method_t em_if_methods[]
Definition: if_em.c:402
em_disable_aspm
static void em_disable_aspm(struct e1000_softc *)
Definition: if_em.c:4026
em_enable_vectors_82574
static void em_enable_vectors_82574(if_ctx_t)
Definition: if_em.c:4870
em_if_attach_post
static int em_if_attach_post(if_ctx_t)
Definition: if_em.c:1133
em_register
static void * em_register(device_t)
Definition: if_em.c:727
em_if_resume
static int em_if_resume(if_ctx_t)
Definition: if_em.c:1221
em_sysctl_debug_info
static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4784
EM_USECS_TO_TICKS
#define EM_USECS_TO_TICKS(usecs)
Definition: if_em.c:483
em_sysctl_print_fw_version
static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
Definition: if_em.c:4584
em_if_vlan_filter_used
static bool em_if_vlan_filter_used(if_ctx_t)
Definition: if_em.c:3457
MODULE_DEPEND
MODULE_DEPEND(em, pci, 1, 1, 1)
DEFAULT_ITR
#define DEFAULT_ITR
Definition: if_em.c:486
igb_configure_queues
static void igb_configure_queues(struct e1000_softc *)
Definition: if_em.c:2108
IGB_CAPS
#define IGB_CAPS
Definition: if_em.c:777
igb_txrx
struct if_txrx igb_txrx
Definition: igb_txrx.c:70
em_get_hw_control
static void em_get_hw_control(struct e1000_softc *)
Definition: if_em.c:3673
em_if_vlan_unregister
static void em_if_vlan_unregister(if_ctx_t, u16)
Definition: if_em.c:3432
em_init_manageability
static void em_init_manageability(struct e1000_softc *)
Definition: if_em.c:3626
DRIVER_MODULE
DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0)
em_smart_pwr_down
static int em_smart_pwr_down
Definition: if_em.c:516
lem_smartspeed
static void lem_smartspeed(struct e1000_softc *)
Definition: if_em.c:2302
em_if_led_func
static void em_if_led_func(if_ctx_t, int)
Definition: if_em.c:4009
em_is_valid_ether_addr
static int em_is_valid_ether_addr(u8 *)
Definition: if_em.c:3720
em_if_shutdown
static int em_if_shutdown(if_ctx_t)
Definition: if_em.c:1201
igb_vendor_info_array
static pci_vendor_info_t igb_vendor_info_array[]
Definition: if_em.c:201
em_devclass
static devclass_t em_devclass
Definition: if_em.c:380
em_enable_phy_wakeup
static int em_enable_phy_wakeup(struct e1000_softc *)
Definition: if_em.c:3939
em_driver_version
char em_driver_version[]
Definition: if_em.c:40
SYSCTL_NODE
static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD|CTLFLAG_MPSAFE, 0, "EM driver parameters")
em_if_watchdog_reset
static void em_if_watchdog_reset(if_ctx_t)
Definition: if_em.c:1886
em_handle_link
static void em_handle_link(void *)
Definition: if_em.c:1540
em_txrx
struct if_txrx em_txrx
Definition: em_txrx.c:69
em_add_int_delay_sysctl
static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, const char *, struct em_int_delay_info *, int, int)
Definition: if_em.c:4708
em_if_debug
static void em_if_debug(if_ctx_t)
Definition: if_em.c:4822
em_if_mtu_set
static int em_if_mtu_set(if_ctx_t, uint32_t)
Definition: if_em.c:1234
em_setup_msix
static int em_setup_msix(if_ctx_t)
Definition: if_em.c:2286
em_if_queues_free
static void em_if_queues_free(if_ctx_t)
Definition: if_em.c:3002
em_mac_min
#define em_mac_min
Definition: if_em.c:34
if_em.h
IGB_MAX_RXD
#define IGB_MAX_RXD
Definition: if_em.h:137
tx_num_queues
#define tx_num_queues
Definition: if_em.h:446
EM_DBA_ALIGN
#define EM_DBA_ALIGN
Definition: if_em.h:293
EM_TSO_SEG_SIZE
#define EM_TSO_SEG_SIZE
Definition: if_em.h:334
AUTONEG_ADV_DEFAULT
#define AUTONEG_ADV_DEFAULT
Definition: if_em.h:216
IOCTL_DEBUGOUT
#define IOCTL_DEBUGOUT(S)
Definition: if_em.h:324
EM_BAR_TYPE
#define EM_BAR_TYPE(v)
Definition: if_em.h:306
EM_82544_APME
#define EM_82544_APME
Definition: if_em.h:242
EM_DEFAULT_RXD
#define EM_DEFAULT_RXD
Definition: if_em.h:135
EM_EEPROM_APME
#define EM_EEPROM_APME
Definition: if_em.h:241
EM_EIAC
#define EM_EIAC
Definition: if_em.h:350
EM_MIN_RXD
#define EM_MIN_RXD
Definition: if_em.h:133
MAX_NUM_MULTICAST_ADDRESSES
#define MAX_NUM_MULTICAST_ADDRESSES
Definition: if_em.h:237
TARC_SPEED_MODE_BIT
#define TARC_SPEED_MODE_BIT
Definition: if_em.h:299
EM_SMARTSPEED_MAX
#define EM_SMARTSPEED_MAX
Definition: if_em.h:234
EM_TIDV
#define EM_TIDV
Definition: if_em.h:149
IGB_TXPBSIZE
#define IGB_TXPBSIZE
Definition: if_em.h:254
EM_BAR_MEM_TYPE
#define EM_BAR_MEM_TYPE(v)
Definition: if_em.h:311
I210_LINK_DELAY
#define I210_LINK_DELAY
Definition: if_em.h:252
INIT_DEBUGOUT1
#define INIT_DEBUGOUT1(S, A)
Definition: if_em.h:322
IGB_RX_PTHRESH
#define IGB_RX_PTHRESH
Definition: if_em.h:277
IGB_RX_HTHRESH
#define IGB_RX_HTHRESH
Definition: if_em.h:279
EM_FC_PAUSE_TIME
#define EM_FC_PAUSE_TIME
Definition: if_em.h:240
EM_MAX_TXD
#define EM_MAX_TXD
Definition: if_em.h:115
TARC_COMPENSATION_MODE
#define TARC_COMPENSATION_MODE
Definition: if_em.h:298
IGB_RX_WTHRESH
#define IGB_RX_WTHRESH
Definition: if_em.h:280
IGB_DMCTLX_DCFLUSH_DIS
#define IGB_DMCTLX_DCFLUSH_DIS
Definition: if_em.h:342
INIT_DEBUGOUT
#define INIT_DEBUGOUT(S)
Definition: if_em.h:321
EM_DEFAULT_TXD
#define EM_DEFAULT_TXD
Definition: if_em.h:116
HW_DEBUGOUT2
#define HW_DEBUGOUT2(S, A, B)
Definition: if_em.h:329
EM_MAX_RXD
#define EM_MAX_RXD
Definition: if_em.h:134
DO_AUTO_NEG
#define DO_AUTO_NEG
Definition: if_em.h:204
IGB_MAX_TXD
#define IGB_MAX_TXD
Definition: if_em.h:118
AUTO_ALL_MODES
#define AUTO_ALL_MODES
Definition: if_em.h:220
EM_RADV
#define EM_RADV
Definition: if_em.h:197
EM_MASTER_SLAVE
#define EM_MASTER_SLAVE
Definition: if_em.h:223
EM_MIN_TXD
#define EM_MIN_TXD
Definition: if_em.h:114
EM_RSSRK_VAL
#define EM_RSSRK_VAL(key, i)
Definition: if_em.h:549
EM_BAR_TYPE_FLASH
#define EM_BAR_TYPE_FLASH
Definition: if_em.h:310
IGB_MEDIA_RESET
#define IGB_MEDIA_RESET
Definition: if_em.h:245
EM_BAR_MEM_TYPE_64BIT
#define EM_BAR_MEM_TYPE_64BIT
Definition: if_em.h:314
TARC_ERRATA_BIT
#define TARC_ERRATA_BIT
Definition: if_em.h:303
EM_RDTR
#define EM_RDTR
Definition: if_em.h:184
EM_MAX_SCATTER
#define EM_MAX_SCATTER
Definition: if_em.h:331
EM_NVM_MSIX_N_SHIFT
#define EM_NVM_MSIX_N_SHIFT
Definition: if_em.h:358
EM_TSO_SIZE
#define EM_TSO_SIZE
Definition: if_em.h:333
EM_TADV
#define EM_TADV
Definition: if_em.h:163
rx_num_queues
#define rx_num_queues
Definition: if_em.h:447
EM_SMARTSPEED_DOWNSHIFT
#define EM_SMARTSPEED_DOWNSHIFT
Definition: if_em.h:233
EM_NVM_MSIX_N_MASK
#define EM_NVM_MSIX_N_MASK
Definition: if_em.h:357
TARC_MQ_FIX
#define TARC_MQ_FIX
Definition: if_em.h:300
EM_BAR_TYPE_IO
#define EM_BAR_TYPE_IO
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Definition: e1000_hw.h:1024
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Definition: if_em.h:365
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