e1000_nvm.c

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/******************************************************************************
  SPDX-License-Identifier: BSD-3-Clause
 
  Copyright (c) 2001-2020, Intel Corporation
  All rights reserved.
 
  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions are met:
 
   1. Redistributions of source code must retain the above copyright notice,
      this list of conditions and the following disclaimer.
 
   2. Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
      documentation and/or other materials provided with the distribution.
 
   3. Neither the name of the Intel Corporation nor the names of its
      contributors may be used to endorse or promote products derived from
      this software without specific prior written permission.
 
  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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******************************************************************************/
/*$FreeBSD$*/
 
#include "e1000_api.h"
 
static void e1000_reload_nvm_generic(struct e1000_hw *hw);
 
void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        DEBUGFUNC("e1000_init_nvm_ops_generic");
 
        /* Initialize function pointers */
        nvm->ops.init_params = e1000_null_ops_generic;
        nvm->ops.acquire = e1000_null_ops_generic;
        nvm->ops.read = e1000_null_read_nvm;
        nvm->ops.release = e1000_null_nvm_generic;
        nvm->ops.reload = e1000_reload_nvm_generic;
        nvm->ops.update = e1000_null_ops_generic;
        nvm->ops.valid_led_default = e1000_null_led_default;
        nvm->ops.validate = e1000_null_ops_generic;
        nvm->ops.write = e1000_null_write_nvm;
}
 
s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
                        u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
                        u16 E1000_UNUSEDARG *c)
{
        DEBUGFUNC("e1000_null_read_nvm");
        return E1000_SUCCESS;
}
 
void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
{
        DEBUGFUNC("e1000_null_nvm_generic");
        return;
}
 
s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
                           u16 E1000_UNUSEDARG *data)
{
        DEBUGFUNC("e1000_null_led_default");
        return E1000_SUCCESS;
}
 
s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
                         u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
                         u16 E1000_UNUSEDARG *c)
{
        DEBUGFUNC("e1000_null_write_nvm");
        return E1000_SUCCESS;
}
 
static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
{
        *eecd = *eecd | E1000_EECD_SK;
        E1000_WRITE_REG(hw, E1000_EECD, *eecd);
        E1000_WRITE_FLUSH(hw);
        usec_delay(hw->nvm.delay_usec);
}
 
static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
{
        *eecd = *eecd & ~E1000_EECD_SK;
        E1000_WRITE_REG(hw, E1000_EECD, *eecd);
        E1000_WRITE_FLUSH(hw);
        usec_delay(hw->nvm.delay_usec);
}
 
static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 eecd = E1000_READ_REG(hw, E1000_EECD);
        u32 mask;
 
        DEBUGFUNC("e1000_shift_out_eec_bits");
 
        mask = 0x01 << (count - 1);
        if (nvm->type == e1000_nvm_eeprom_microwire)
                eecd &= ~E1000_EECD_DO;
        else
        if (nvm->type == e1000_nvm_eeprom_spi)
                eecd |= E1000_EECD_DO;
 
        do {
                eecd &= ~E1000_EECD_DI;
 
                if (data & mask)
                        eecd |= E1000_EECD_DI;
 
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                E1000_WRITE_FLUSH(hw);
 
                usec_delay(nvm->delay_usec);
 
                e1000_raise_eec_clk(hw, &eecd);
                e1000_lower_eec_clk(hw, &eecd);
 
                mask >>= 1;
        } while (mask);
 
        eecd &= ~E1000_EECD_DI;
        E1000_WRITE_REG(hw, E1000_EECD, eecd);
}
 
static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
{
        u32 eecd;
        u32 i;
        u16 data;
 
        DEBUGFUNC("e1000_shift_in_eec_bits");
 
        eecd = E1000_READ_REG(hw, E1000_EECD);
 
        eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
        data = 0;
 
        for (i = 0; i < count; i++) {
                data <<= 1;
                e1000_raise_eec_clk(hw, &eecd);
 
                eecd = E1000_READ_REG(hw, E1000_EECD);
 
                eecd &= ~E1000_EECD_DI;
                if (eecd & E1000_EECD_DO)
                        data |= 1;
 
                e1000_lower_eec_clk(hw, &eecd);
        }
 
        return data;
}
 
s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
{
        u32 attempts = 100000;
        u32 i, reg = 0;
 
        DEBUGFUNC("e1000_poll_eerd_eewr_done");
 
        for (i = 0; i < attempts; i++) {
                if (ee_reg == E1000_NVM_POLL_READ)
                        reg = E1000_READ_REG(hw, E1000_EERD);
                else
                        reg = E1000_READ_REG(hw, E1000_EEWR);
 
                if (reg & E1000_NVM_RW_REG_DONE)
                        return E1000_SUCCESS;
 
                usec_delay(5);
        }
 
        return -E1000_ERR_NVM;
}
 
s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
{
        u32 eecd = E1000_READ_REG(hw, E1000_EECD);
        s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 
        DEBUGFUNC("e1000_acquire_nvm_generic");
 
        E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
        eecd = E1000_READ_REG(hw, E1000_EECD);
 
        while (timeout) {
                if (eecd & E1000_EECD_GNT)
                        break;
                usec_delay(5);
                eecd = E1000_READ_REG(hw, E1000_EECD);
                timeout--;
        }
 
        if (!timeout) {
                eecd &= ~E1000_EECD_REQ;
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                DEBUGOUT("Could not acquire NVM grant\n");
                return -E1000_ERR_NVM;
        }
 
        return E1000_SUCCESS;
}
 
static void e1000_standby_nvm(struct e1000_hw *hw)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 
        DEBUGFUNC("e1000_standby_nvm");
 
        if (nvm->type == e1000_nvm_eeprom_microwire) {
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                E1000_WRITE_FLUSH(hw);
                usec_delay(nvm->delay_usec);
 
                e1000_raise_eec_clk(hw, &eecd);
 
                /* Select EEPROM */
                eecd |= E1000_EECD_CS;
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                E1000_WRITE_FLUSH(hw);
                usec_delay(nvm->delay_usec);
 
                e1000_lower_eec_clk(hw, &eecd);
        } else if (nvm->type == e1000_nvm_eeprom_spi) {
                /* Toggle CS to flush commands */
                eecd |= E1000_EECD_CS;
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                E1000_WRITE_FLUSH(hw);
                usec_delay(nvm->delay_usec);
                eecd &= ~E1000_EECD_CS;
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                E1000_WRITE_FLUSH(hw);
                usec_delay(nvm->delay_usec);
        }
}
 
void e1000_stop_nvm(struct e1000_hw *hw)
{
        u32 eecd;
 
        DEBUGFUNC("e1000_stop_nvm");
 
        eecd = E1000_READ_REG(hw, E1000_EECD);
        if (hw->nvm.type == e1000_nvm_eeprom_spi) {
                /* Pull CS high */
                eecd |= E1000_EECD_CS;
                e1000_lower_eec_clk(hw, &eecd);
        } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
                /* CS on Microwire is active-high */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                e1000_raise_eec_clk(hw, &eecd);
                e1000_lower_eec_clk(hw, &eecd);
        }
}
 
void e1000_release_nvm_generic(struct e1000_hw *hw)
{
        u32 eecd;
 
        DEBUGFUNC("e1000_release_nvm_generic");
 
        e1000_stop_nvm(hw);
 
        eecd = E1000_READ_REG(hw, E1000_EECD);
        eecd &= ~E1000_EECD_REQ;
        E1000_WRITE_REG(hw, E1000_EECD, eecd);
}
 
static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 eecd = E1000_READ_REG(hw, E1000_EECD);
        u8 spi_stat_reg;
 
        DEBUGFUNC("e1000_ready_nvm_eeprom");
 
        if (nvm->type == e1000_nvm_eeprom_microwire) {
                /* Clear SK and DI */
                eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                /* Set CS */
                eecd |= E1000_EECD_CS;
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
        } else if (nvm->type == e1000_nvm_eeprom_spi) {
                u16 timeout = NVM_MAX_RETRY_SPI;
 
                /* Clear SK and CS */
                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
                E1000_WRITE_REG(hw, E1000_EECD, eecd);
                E1000_WRITE_FLUSH(hw);
                usec_delay(1);
 
                /* Read "Status Register" repeatedly until the LSB is cleared.
                 * The EEPROM will signal that the command has been completed
                 * by clearing bit 0 of the internal status register.  If it's
                 * not cleared within 'timeout', then error out.
                 */
                while (timeout) {
                        e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
                                                 hw->nvm.opcode_bits);
                        spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
                        if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
                                break;
 
                        usec_delay(5);
                        e1000_standby_nvm(hw);
                        timeout--;
                }
 
                if (!timeout) {
                        DEBUGOUT("SPI NVM Status error\n");
                        return -E1000_ERR_NVM;
                }
        }
 
        return E1000_SUCCESS;
}
 
s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 i = 0;
        s32 ret_val;
        u16 word_in;
        u8 read_opcode = NVM_READ_OPCODE_SPI;
 
        DEBUGFUNC("e1000_read_nvm_spi");
 
        /* A check for invalid values:  offset too large, too many words,
         * and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                DEBUGOUT("nvm parameter(s) out of bounds\n");
                return -E1000_ERR_NVM;
        }
 
        ret_val = nvm->ops.acquire(hw);
        if (ret_val)
                return ret_val;
 
        ret_val = e1000_ready_nvm_eeprom(hw);
        if (ret_val)
                goto release;
 
        e1000_standby_nvm(hw);
 
        if ((nvm->address_bits == 8) && (offset >= 128))
                read_opcode |= NVM_A8_OPCODE_SPI;
 
        /* Send the READ command (opcode + addr) */
        e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
        e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 
        /* Read the data.  SPI NVMs increment the address with each byte
         * read and will roll over if reading beyond the end.  This allows
         * us to read the whole NVM from any offset
         */
        for (i = 0; i < words; i++) {
                word_in = e1000_shift_in_eec_bits(hw, 16);
                data[i] = (word_in >> 8) | (word_in << 8);
        }
 
release:
        nvm->ops.release(hw);
 
        return ret_val;
}
 
s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
                             u16 *data)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 i = 0;
        s32 ret_val;
        u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 
        DEBUGFUNC("e1000_read_nvm_microwire");
 
        /* A check for invalid values:  offset too large, too many words,
         * and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                DEBUGOUT("nvm parameter(s) out of bounds\n");
                return -E1000_ERR_NVM;
        }
 
        ret_val = nvm->ops.acquire(hw);
        if (ret_val)
                return ret_val;
 
        ret_val = e1000_ready_nvm_eeprom(hw);
        if (ret_val)
                goto release;
 
        for (i = 0; i < words; i++) {
                /* Send the READ command (opcode + addr) */
                e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
                e1000_shift_out_eec_bits(hw, (u16)(offset + i),
                                        nvm->address_bits);
 
                /* Read the data.  For microwire, each word requires the
                 * overhead of setup and tear-down.
                 */
                data[i] = e1000_shift_in_eec_bits(hw, 16);
                e1000_standby_nvm(hw);
        }
 
release:
        nvm->ops.release(hw);
 
        return ret_val;
}
 
s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 i, eerd = 0;
        s32 ret_val = E1000_SUCCESS;
 
        DEBUGFUNC("e1000_read_nvm_eerd");
 
        /* A check for invalid values:  offset too large, too many words,
         * too many words for the offset, and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                DEBUGOUT("nvm parameter(s) out of bounds\n");
                return -E1000_ERR_NVM;
        }
 
        for (i = 0; i < words; i++) {
                eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
                       E1000_NVM_RW_REG_START;
 
                E1000_WRITE_REG(hw, E1000_EERD, eerd);
                ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
                if (ret_val)
                        break;
 
                data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
                           E1000_NVM_RW_REG_DATA);
        }
 
        if (ret_val)
                DEBUGOUT1("NVM read error: %d\n", ret_val);
 
        return ret_val;
}
 
s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        s32 ret_val = -E1000_ERR_NVM;
        u16 widx = 0;
 
        DEBUGFUNC("e1000_write_nvm_spi");
 
        /* A check for invalid values:  offset too large, too many words,
         * and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                DEBUGOUT("nvm parameter(s) out of bounds\n");
                return -E1000_ERR_NVM;
        }
 
        while (widx < words) {
                u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 
                ret_val = nvm->ops.acquire(hw);
                if (ret_val)
                        return ret_val;
 
                ret_val = e1000_ready_nvm_eeprom(hw);
                if (ret_val) {
                        nvm->ops.release(hw);
                        return ret_val;
                }
 
                e1000_standby_nvm(hw);
 
                /* Send the WRITE ENABLE command (8 bit opcode) */
                e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
                                         nvm->opcode_bits);
 
                e1000_standby_nvm(hw);
 
                /* Some SPI eeproms use the 8th address bit embedded in the
                 * opcode
                 */
                if ((nvm->address_bits == 8) && (offset >= 128))
                        write_opcode |= NVM_A8_OPCODE_SPI;
 
                /* Send the Write command (8-bit opcode + addr) */
                e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
                e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
                                         nvm->address_bits);
 
                /* Loop to allow for up to whole page write of eeprom */
                while (widx < words) {
                        u16 word_out = data[widx];
                        word_out = (word_out >> 8) | (word_out << 8);
                        e1000_shift_out_eec_bits(hw, word_out, 16);
                        widx++;
 
                        if ((((offset + widx) * 2) % nvm->page_size) == 0) {
                                e1000_standby_nvm(hw);
                                break;
                        }
                }
                msec_delay(10);
                nvm->ops.release(hw);
        }
 
        return ret_val;
}
 
s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
                              u16 *data)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        s32  ret_val;
        u32 eecd;
        u16 words_written = 0;
        u16 widx = 0;
 
        DEBUGFUNC("e1000_write_nvm_microwire");
 
        /* A check for invalid values:  offset too large, too many words,
         * and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                DEBUGOUT("nvm parameter(s) out of bounds\n");
                return -E1000_ERR_NVM;
        }
 
        ret_val = nvm->ops.acquire(hw);
        if (ret_val)
                return ret_val;
 
        ret_val = e1000_ready_nvm_eeprom(hw);
        if (ret_val)
                goto release;
 
        e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
                                 (u16)(nvm->opcode_bits + 2));
 
        e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 
        e1000_standby_nvm(hw);
 
        while (words_written < words) {
                e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
                                         nvm->opcode_bits);
 
                e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
                                         nvm->address_bits);
 
                e1000_shift_out_eec_bits(hw, data[words_written], 16);
 
                e1000_standby_nvm(hw);
 
                for (widx = 0; widx < 200; widx++) {
                        eecd = E1000_READ_REG(hw, E1000_EECD);
                        if (eecd & E1000_EECD_DO)
                                break;
                        usec_delay(50);
                }
 
                if (widx == 200) {
                        DEBUGOUT("NVM Write did not complete\n");
                        ret_val = -E1000_ERR_NVM;
                        goto release;
                }
 
                e1000_standby_nvm(hw);
 
                words_written++;
        }
 
        e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
                                 (u16)(nvm->opcode_bits + 2));
 
        e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 
release:
        nvm->ops.release(hw);
 
        return ret_val;
}
 
s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
                                  u32 pba_num_size)
{
        s32 ret_val;
        u16 nvm_data;
        u16 pba_ptr;
        u16 offset;
        u16 length;
 
        DEBUGFUNC("e1000_read_pba_string_generic");
 
        if ((hw->mac.type == e1000_i210 ||
             hw->mac.type == e1000_i211) &&
             !e1000_get_flash_presence_i210(hw)) {
                DEBUGOUT("Flashless no PBA string\n");
                return -E1000_ERR_NVM_PBA_SECTION;
        }
 
        if (pba_num == NULL) {
                DEBUGOUT("PBA string buffer was null\n");
                return -E1000_ERR_INVALID_ARGUMENT;
        }
 
        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
 
        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
 
        /* if nvm_data is not ptr guard the PBA must be in legacy format which
         * means pba_ptr is actually our second data word for the PBA number
         * and we can decode it into an ascii string
         */
        if (nvm_data != NVM_PBA_PTR_GUARD) {
                DEBUGOUT("NVM PBA number is not stored as string\n");
 
                /* make sure callers buffer is big enough to store the PBA */
                if (pba_num_size < E1000_PBANUM_LENGTH) {
                        DEBUGOUT("PBA string buffer too small\n");
                        return E1000_ERR_NO_SPACE;
                }
 
                /* extract hex string from data and pba_ptr */
                pba_num[0] = (nvm_data >> 12) & 0xF;
                pba_num[1] = (nvm_data >> 8) & 0xF;
                pba_num[2] = (nvm_data >> 4) & 0xF;
                pba_num[3] = nvm_data & 0xF;
                pba_num[4] = (pba_ptr >> 12) & 0xF;
                pba_num[5] = (pba_ptr >> 8) & 0xF;
                pba_num[6] = '-';
                pba_num[7] = 0;
                pba_num[8] = (pba_ptr >> 4) & 0xF;
                pba_num[9] = pba_ptr & 0xF;
 
                /* put a null character on the end of our string */
                pba_num[10] = '\0';
 
                /* switch all the data but the '-' to hex char */
                for (offset = 0; offset < 10; offset++) {
                        if (pba_num[offset] < 0xA)
                                pba_num[offset] += '0';
                        else if (pba_num[offset] < 0x10)
                                pba_num[offset] += 'A' - 0xA;
                }
 
                return E1000_SUCCESS;
        }
 
        ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
 
        if (length == 0xFFFF || length == 0) {
                DEBUGOUT("NVM PBA number section invalid length\n");
                return -E1000_ERR_NVM_PBA_SECTION;
        }
        /* check if pba_num buffer is big enough */
        if (pba_num_size < (((u32)length * 2) - 1)) {
                DEBUGOUT("PBA string buffer too small\n");
                return -E1000_ERR_NO_SPACE;
        }
 
        /* trim pba length from start of string */
        pba_ptr++;
        length--;
 
        for (offset = 0; offset < length; offset++) {
                ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
                if (ret_val) {
                        DEBUGOUT("NVM Read Error\n");
                        return ret_val;
                }
                pba_num[offset * 2] = (u8)(nvm_data >> 8);
                pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
        }
        pba_num[offset * 2] = '\0';
 
        return E1000_SUCCESS;
}
 
s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
{
        s32 ret_val;
        u16 nvm_data;
        u16 pba_ptr;
        u16 length;
 
        DEBUGFUNC("e1000_read_pba_length_generic");
 
        if (pba_num_size == NULL) {
                DEBUGOUT("PBA buffer size was null\n");
                return -E1000_ERR_INVALID_ARGUMENT;
        }
 
        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
 
        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
 
         /* if data is not ptr guard the PBA must be in legacy format */
        if (nvm_data != NVM_PBA_PTR_GUARD) {
                *pba_num_size = E1000_PBANUM_LENGTH;
                return E1000_SUCCESS;
        }
 
        ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
 
        if (length == 0xFFFF || length == 0) {
                DEBUGOUT("NVM PBA number section invalid length\n");
                return -E1000_ERR_NVM_PBA_SECTION;
        }
 
        /* Convert from length in u16 values to u8 chars, add 1 for NULL,
         * and subtract 2 because length field is included in length.
         */
        *pba_num_size = ((u32)length * 2) - 1;
 
        return E1000_SUCCESS;
}
 
s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
{
        s32 ret_val;
        u16 nvm_data;
 
        DEBUGFUNC("e1000_read_pba_num_generic");
 
        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        } else if (nvm_data == NVM_PBA_PTR_GUARD) {
                DEBUGOUT("NVM Not Supported\n");
                return -E1000_NOT_IMPLEMENTED;
        }
        *pba_num = (u32)(nvm_data << 16);
 
        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
        *pba_num |= nvm_data;
 
        return E1000_SUCCESS;
}
 
 
s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
                       u32 eeprom_buf_size, u16 max_pba_block_size,
                       struct e1000_pba *pba)
{
        s32 ret_val;
        u16 pba_block_size;
 
        if (pba == NULL)
                return -E1000_ERR_PARAM;
 
        if (eeprom_buf == NULL) {
                ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
                                         &pba->word[0]);
                if (ret_val)
                        return ret_val;
        } else {
                if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
                        pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
                        pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
                } else {
                        return -E1000_ERR_PARAM;
                }
        }
 
        if (pba->word[0] == NVM_PBA_PTR_GUARD) {
                if (pba->pba_block == NULL)
                        return -E1000_ERR_PARAM;
 
                ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
                                                   eeprom_buf_size,
                                                   &pba_block_size);
                if (ret_val)
                        return ret_val;
 
                if (pba_block_size > max_pba_block_size)
                        return -E1000_ERR_PARAM;
 
                if (eeprom_buf == NULL) {
                        ret_val = e1000_read_nvm(hw, pba->word[1],
                                                 pba_block_size,
                                                 pba->pba_block);
                        if (ret_val)
                                return ret_val;
                } else {
                        if (eeprom_buf_size > (u32)(pba->word[1] +
                                              pba_block_size)) {
                                memcpy(pba->pba_block,
                                       &eeprom_buf[pba->word[1]],
                                       pba_block_size * sizeof(u16));
                        } else {
                                return -E1000_ERR_PARAM;
                        }
                }
        }
 
        return E1000_SUCCESS;
}
 
s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
                        u32 eeprom_buf_size, struct e1000_pba *pba)
{
        s32 ret_val;
 
        if (pba == NULL)
                return -E1000_ERR_PARAM;
 
        if (eeprom_buf == NULL) {
                ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
                                          &pba->word[0]);
                if (ret_val)
                        return ret_val;
        } else {
                if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
                        eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
                        eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
                } else {
                        return -E1000_ERR_PARAM;
                }
        }
 
        if (pba->word[0] == NVM_PBA_PTR_GUARD) {
                if (pba->pba_block == NULL)
                        return -E1000_ERR_PARAM;
 
                if (eeprom_buf == NULL) {
                        ret_val = e1000_write_nvm(hw, pba->word[1],
                                                  pba->pba_block[0],
                                                  pba->pba_block);
                        if (ret_val)
                                return ret_val;
                } else {
                        if (eeprom_buf_size > (u32)(pba->word[1] +
                                              pba->pba_block[0])) {
                                memcpy(&eeprom_buf[pba->word[1]],
                                       pba->pba_block,
                                       pba->pba_block[0] * sizeof(u16));
                        } else {
                                return -E1000_ERR_PARAM;
                        }
                }
        }
 
        return E1000_SUCCESS;
}
 
s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
                             u32 eeprom_buf_size, u16 *pba_block_size)
{
        s32 ret_val;
        u16 pba_word[2];
        u16 length;
 
        DEBUGFUNC("e1000_get_pba_block_size");
 
        if (eeprom_buf == NULL) {
                ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
                if (ret_val)
                        return ret_val;
        } else {
                if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
                        pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
                        pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
                } else {
                        return -E1000_ERR_PARAM;
                }
        }
 
        if (pba_word[0] == NVM_PBA_PTR_GUARD) {
                if (eeprom_buf == NULL) {
                        ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
                                                 &length);
                        if (ret_val)
                                return ret_val;
                } else {
                        if (eeprom_buf_size > pba_word[1])
                                length = eeprom_buf[pba_word[1] + 0];
                        else
                                return -E1000_ERR_PARAM;
                }
 
                if (length == 0xFFFF || length == 0)
                        return -E1000_ERR_NVM_PBA_SECTION;
        } else {
                /* PBA number in legacy format, there is no PBA Block. */
                length = 0;
        }
 
        if (pba_block_size != NULL)
                *pba_block_size = length;
 
        return E1000_SUCCESS;
}
 
s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
{
        u32 rar_high;
        u32 rar_low;
        u16 i;
 
        rar_high = E1000_READ_REG(hw, E1000_RAH(0));
        rar_low = E1000_READ_REG(hw, E1000_RAL(0));
 
        for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
                hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
 
        for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
                hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
 
        for (i = 0; i < ETHER_ADDR_LEN; i++)
                hw->mac.addr[i] = hw->mac.perm_addr[i];
 
        return E1000_SUCCESS;
}
 
s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
{
        s32 ret_val;
        u16 checksum = 0;
        u16 i, nvm_data;
 
        DEBUGFUNC("e1000_validate_nvm_checksum_generic");
 
        for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
                ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
                if (ret_val) {
                        DEBUGOUT("NVM Read Error\n");
                        return ret_val;
                }
                checksum += nvm_data;
        }
 
        if (checksum != (u16) NVM_SUM) {
                DEBUGOUT("NVM Checksum Invalid\n");
                return -E1000_ERR_NVM;
        }
 
        return E1000_SUCCESS;
}
 
s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
{
        s32 ret_val;
        u16 checksum = 0;
        u16 i, nvm_data;
 
        DEBUGFUNC("e1000_update_nvm_checksum");
 
        for (i = 0; i < NVM_CHECKSUM_REG; i++) {
                ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
                if (ret_val) {
                        DEBUGOUT("NVM Read Error while updating checksum.\n");
                        return ret_val;
                }
                checksum += nvm_data;
        }
        checksum = (u16) NVM_SUM - checksum;
        ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
        if (ret_val)
                DEBUGOUT("NVM Write Error while updating checksum.\n");
 
        return ret_val;
}
 
static void e1000_reload_nvm_generic(struct e1000_hw *hw)
{
        u32 ctrl_ext;
 
        DEBUGFUNC("e1000_reload_nvm_generic");
 
        usec_delay(10);
        ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
        E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
        E1000_WRITE_FLUSH(hw);
}
 
void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
{
        u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
        u8 q, hval, rem, result;
        u16 comb_verh, comb_verl, comb_offset;
 
        memset(fw_vers, 0, sizeof(struct e1000_fw_version));
 
        /* basic eeprom version numbers, bits used vary by part and by tool
         * used to create the nvm images */
        /* Check which data format we have */
        switch (hw->mac.type) {
        case e1000_i211:
                e1000_read_invm_version(hw, fw_vers);
                return;
        case e1000_82575:
        case e1000_82576:
        case e1000_82580:
        case e1000_i354:
                hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
                /* Use this format, unless EETRACK ID exists,
                 * then use alternate format
                 */
                if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
                        hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
                        fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
                                              >> NVM_MAJOR_SHIFT;
                        fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
                                              >> NVM_MINOR_SHIFT;
                        fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
                        goto etrack_id;
                }
                break;
        case e1000_i210:
                if (!(e1000_get_flash_presence_i210(hw))) {
                        e1000_read_invm_version(hw, fw_vers);
                        return;
                }
                /* FALLTHROUGH */
        case e1000_i350:
                hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
                /* find combo image version */
                hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
                if ((comb_offset != 0x0) &&
                    (comb_offset != NVM_VER_INVALID)) {
 
                        hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
                                         + 1), 1, &comb_verh);
                        hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
                                         1, &comb_verl);
 
                        /* get Option Rom version if it exists and is valid */
                        if ((comb_verh && comb_verl) &&
                            ((comb_verh != NVM_VER_INVALID) &&
                             (comb_verl != NVM_VER_INVALID))) {
 
                                fw_vers->or_valid = true;
                                fw_vers->or_major =
                                        comb_verl >> NVM_COMB_VER_SHFT;
                                fw_vers->or_build =
                                        (comb_verl << NVM_COMB_VER_SHFT)
                                        | (comb_verh >> NVM_COMB_VER_SHFT);
                                fw_vers->or_patch =
                                        comb_verh & NVM_COMB_VER_MASK;
                        }
                }
                break;
        default:
                hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
                return;
        }
        hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
        fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
                              >> NVM_MAJOR_SHIFT;
 
        /* check for old style version format in newer images*/
        if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
                eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
        } else {
                eeprom_verl = (fw_version & NVM_MINOR_MASK)
                                >> NVM_MINOR_SHIFT;
        }
        /* Convert minor value to hex before assigning to output struct
         * Val to be converted will not be higher than 99, per tool output
         */
        q = eeprom_verl / NVM_HEX_CONV;
        hval = q * NVM_HEX_TENS;
        rem = eeprom_verl % NVM_HEX_CONV;
        result = hval + rem;
        fw_vers->eep_minor = result;
 
etrack_id:
        if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
                hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
                hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
                fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
                        | eeprom_verl;
        } else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
                hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
                hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
                fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
                                     eeprom_verl;
        }
}