e1000_i210.c

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/******************************************************************************
  SPDX-License-Identifier: BSD-3-Clause
 
  Copyright (c) 2001-2020, Intel Corporation
  All rights reserved.
 
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  modification, are permitted provided that the following conditions are met:
 
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      this list of conditions and the following disclaimer.
 
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      contributors may be used to endorse or promote products derived from
      this software without specific prior written permission.
 
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/*$FreeBSD$*/
 
#include "e1000_api.h"
 
 
static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);
static void e1000_release_nvm_i210(struct e1000_hw *hw);
static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
                                u16 *data);
static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);
static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
 
static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw)
{
        s32 ret_val;
 
        DEBUGFUNC("e1000_acquire_nvm_i210");
 
        ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
 
        return ret_val;
}
 
static void e1000_release_nvm_i210(struct e1000_hw *hw)
{
        DEBUGFUNC("e1000_release_nvm_i210");
 
        e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
}
 
s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
                             u16 *data)
{
        s32 status = E1000_SUCCESS;
        u16 i, count;
 
        DEBUGFUNC("e1000_read_nvm_srrd_i210");
 
        /* We cannot hold synchronization semaphores for too long,
         * because of forceful takeover procedure. However it is more efficient
         * to read in bursts than synchronizing access for each word. */
        for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
                count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
                        E1000_EERD_EEWR_MAX_COUNT : (words - i);
                if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
                        status = e1000_read_nvm_eerd(hw, offset, count,
                                                     data + i);
                        hw->nvm.ops.release(hw);
                } else {
                        status = E1000_ERR_SWFW_SYNC;
                }
 
                if (status != E1000_SUCCESS)
                        break;
        }
 
        return status;
}
 
s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
                              u16 *data)
{
        s32 status = E1000_SUCCESS;
        u16 i, count;
 
        DEBUGFUNC("e1000_write_nvm_srwr_i210");
 
        /* We cannot hold synchronization semaphores for too long,
         * because of forceful takeover procedure. However it is more efficient
         * to write in bursts than synchronizing access for each word. */
        for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
                count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
                        E1000_EERD_EEWR_MAX_COUNT : (words - i);
                if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
                        status = e1000_write_nvm_srwr(hw, offset, count,
                                                      data + i);
                        hw->nvm.ops.release(hw);
                } else {
                        status = E1000_ERR_SWFW_SYNC;
                }
 
                if (status != E1000_SUCCESS)
                        break;
        }
 
        return status;
}
 
static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
                                u16 *data)
{
        struct e1000_nvm_info *nvm = &hw->nvm;
        u32 i, k, eewr = 0;
        u32 attempts = 100000;
        s32 ret_val = E1000_SUCCESS;
 
        DEBUGFUNC("e1000_write_nvm_srwr");
 
        /*
         * A check for invalid values:  offset too large, too many words,
         * too many words for the offset, and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                DEBUGOUT("nvm parameter(s) out of bounds\n");
                ret_val = -E1000_ERR_NVM;
                goto out;
        }
 
        for (i = 0; i < words; i++) {
                ret_val = -E1000_ERR_NVM;
 
                eewr = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
                        (data[i] << E1000_NVM_RW_REG_DATA) |
                        E1000_NVM_RW_REG_START;
 
                E1000_WRITE_REG(hw, E1000_SRWR, eewr);
 
                for (k = 0; k < attempts; k++) {
                        if (E1000_NVM_RW_REG_DONE &
                            E1000_READ_REG(hw, E1000_SRWR)) {
                                ret_val = E1000_SUCCESS;
                                break;
                        }
                        usec_delay(5);
                }
 
                if (ret_val != E1000_SUCCESS) {
                        DEBUGOUT("Shadow RAM write EEWR timed out\n");
                        break;
                }
        }
 
out:
        return ret_val;
}
 
static s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)
{
        s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
        u32 invm_dword;
        u16 i;
        u8 record_type, word_address;
 
        DEBUGFUNC("e1000_read_invm_word_i210");
 
        for (i = 0; i < E1000_INVM_SIZE; i++) {
                invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
                /* Get record type */
                record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
                if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
                        break;
                if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
                        i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
                if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
                        i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
                if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
                        word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
                        if (word_address == address) {
                                *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
                                DEBUGOUT2("Read INVM Word 0x%02x = %x",
                                          address, *data);
                                status = E1000_SUCCESS;
                                break;
                        }
                }
        }
        if (status != E1000_SUCCESS)
                DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address);
        return status;
}
 
static s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,
                                u16 E1000_UNUSEDARG words, u16 *data)
{
        s32 ret_val = E1000_SUCCESS;
 
        DEBUGFUNC("e1000_read_invm_i210");
 
        /* Only the MAC addr is required to be present in the iNVM */
        switch (offset) {
        case NVM_MAC_ADDR:
                ret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);
                ret_val |= e1000_read_invm_word_i210(hw, (u8)offset + 1,
                                                     &data[1]);
                ret_val |= e1000_read_invm_word_i210(hw, (u8)offset + 2,
                                                     &data[2]);
                if (ret_val != E1000_SUCCESS)
                        DEBUGOUT("MAC Addr not found in iNVM\n");
                break;
        case NVM_INIT_CTRL_2:
                ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
                if (ret_val != E1000_SUCCESS) {
                        *data = NVM_INIT_CTRL_2_DEFAULT_I211;
                        ret_val = E1000_SUCCESS;
                }
                break;
        case NVM_INIT_CTRL_4:
                ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
                if (ret_val != E1000_SUCCESS) {
                        *data = NVM_INIT_CTRL_4_DEFAULT_I211;
                        ret_val = E1000_SUCCESS;
                }
                break;
        case NVM_LED_1_CFG:
                ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
                if (ret_val != E1000_SUCCESS) {
                        *data = NVM_LED_1_CFG_DEFAULT_I211;
                        ret_val = E1000_SUCCESS;
                }
                break;
        case NVM_LED_0_2_CFG:
                ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
                if (ret_val != E1000_SUCCESS) {
                        *data = NVM_LED_0_2_CFG_DEFAULT_I211;
                        ret_val = E1000_SUCCESS;
                }
                break;
        case NVM_ID_LED_SETTINGS:
                ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
                if (ret_val != E1000_SUCCESS) {
                        *data = ID_LED_RESERVED_FFFF;
                        ret_val = E1000_SUCCESS;
                }
                break;
        case NVM_SUB_DEV_ID:
                *data = hw->subsystem_device_id;
                break;
        case NVM_SUB_VEN_ID:
                *data = hw->subsystem_vendor_id;
                break;
        case NVM_DEV_ID:
                *data = hw->device_id;
                break;
        case NVM_VEN_ID:
                *data = hw->vendor_id;
                break;
        default:
                DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
                *data = NVM_RESERVED_WORD;
                break;
        }
        return ret_val;
}
 
s32 e1000_read_invm_version(struct e1000_hw *hw,
                            struct e1000_fw_version *invm_ver)
{
        u32 *record = NULL;
        u32 *next_record = NULL;
        u32 i = 0;
        u32 invm_dword = 0;
        u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
                                             E1000_INVM_RECORD_SIZE_IN_BYTES);
        u32 buffer[E1000_INVM_SIZE];
        s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
        u16 version = 0;
 
        DEBUGFUNC("e1000_read_invm_version");
 
        /* Read iNVM memory */
        for (i = 0; i < E1000_INVM_SIZE; i++) {
                invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
                buffer[i] = invm_dword;
        }
 
        /* Read version number */
        for (i = 1; i < invm_blocks; i++) {
                record = &buffer[invm_blocks - i];
                next_record = &buffer[invm_blocks - i + 1];
 
                /* Check if we have first version location used */
                if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
                        version = 0;
                        status = E1000_SUCCESS;
                        break;
                }
                /* Check if we have second version location used */
                else if ((i == 1) &&
                         ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
                        version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
                        status = E1000_SUCCESS;
                        break;
                }
                /*
                 * Check if we have odd version location
                 * used and it is the last one used
                 */
                else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
                         ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
                         (i != 1))) {
                        version = (*next_record & E1000_INVM_VER_FIELD_TWO)
                                  >> 13;
                        status = E1000_SUCCESS;
                        break;
                }
                /*
                 * Check if we have even version location
                 * used and it is the last one used
                 */
                else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
                         ((*record & 0x3) == 0)) {
                        version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
                        status = E1000_SUCCESS;
                        break;
                }
        }
 
        if (status == E1000_SUCCESS) {
                invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
                                        >> E1000_INVM_MAJOR_SHIFT;
                invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
        }
        /* Read Image Type */
        for (i = 1; i < invm_blocks; i++) {
                record = &buffer[invm_blocks - i];
                next_record = &buffer[invm_blocks - i + 1];
 
                /* Check if we have image type in first location used */
                if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
                        invm_ver->invm_img_type = 0;
                        status = E1000_SUCCESS;
                        break;
                }
                /* Check if we have image type in first location used */
                else if ((((*record & 0x3) == 0) &&
                         ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
                         ((((*record & 0x3) != 0) && (i != 1)))) {
                        invm_ver->invm_img_type =
                                (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
                        status = E1000_SUCCESS;
                        break;
                }
        }
        return status;
}
 
s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw)
{
        s32 status = E1000_SUCCESS;
        s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
 
        DEBUGFUNC("e1000_validate_nvm_checksum_i210");
 
        if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
 
                /*
                 * Replace the read function with semaphore grabbing with
                 * the one that skips this for a while.
                 * We have semaphore taken already here.
                 */
                read_op_ptr = hw->nvm.ops.read;
                hw->nvm.ops.read = e1000_read_nvm_eerd;
 
                status = e1000_validate_nvm_checksum_generic(hw);
 
                /* Revert original read operation. */
                hw->nvm.ops.read = read_op_ptr;
 
                hw->nvm.ops.release(hw);
        } else {
                status = E1000_ERR_SWFW_SYNC;
        }
 
        return status;
}
 
 
s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw)
{
        s32 ret_val;
        u16 checksum = 0;
        u16 i, nvm_data;
 
        DEBUGFUNC("e1000_update_nvm_checksum_i210");
 
        /*
         * Read the first word from the EEPROM. If this times out or fails, do
         * not continue or we could be in for a very long wait while every
         * EEPROM read fails
         */
        ret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);
        if (ret_val != E1000_SUCCESS) {
                DEBUGOUT("EEPROM read failed\n");
                goto out;
        }
 
        if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
                /*
                 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
                 * because we do not want to take the synchronization
                 * semaphores twice here.
                 */
 
                for (i = 0; i < NVM_CHECKSUM_REG; i++) {
                        ret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);
                        if (ret_val) {
                                hw->nvm.ops.release(hw);
                                DEBUGOUT("NVM Read Error while updating checksum.\n");
                                goto out;
                        }
                        checksum += nvm_data;
                }
                checksum = (u16) NVM_SUM - checksum;
                ret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
                                                &checksum);
                if (ret_val != E1000_SUCCESS) {
                        hw->nvm.ops.release(hw);
                        DEBUGOUT("NVM Write Error while updating checksum.\n");
                        goto out;
                }
 
                hw->nvm.ops.release(hw);
 
                ret_val = e1000_update_flash_i210(hw);
        } else {
                ret_val = E1000_ERR_SWFW_SYNC;
        }
out:
        return ret_val;
}
 
bool e1000_get_flash_presence_i210(struct e1000_hw *hw)
{
        u32 eec = 0;
        bool ret_val = false;
 
        DEBUGFUNC("e1000_get_flash_presence_i210");
 
        eec = E1000_READ_REG(hw, E1000_EECD);
 
        if (eec & E1000_EECD_FLASH_DETECTED_I210)
                ret_val = true;
 
        return ret_val;
}
 
s32 e1000_update_flash_i210(struct e1000_hw *hw)
{
        s32 ret_val;
        u32 flup;
 
        DEBUGFUNC("e1000_update_flash_i210");
 
        ret_val = e1000_pool_flash_update_done_i210(hw);
        if (ret_val == -E1000_ERR_NVM) {
                DEBUGOUT("Flash update time out\n");
                goto out;
        }
 
        flup = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD_I210;
        E1000_WRITE_REG(hw, E1000_EECD, flup);
 
        ret_val = e1000_pool_flash_update_done_i210(hw);
        if (ret_val == E1000_SUCCESS)
                DEBUGOUT("Flash update complete\n");
        else
                DEBUGOUT("Flash update time out\n");
 
out:
        return ret_val;
}
 
s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
{
        s32 ret_val = -E1000_ERR_NVM;
        u32 i, reg;
 
        DEBUGFUNC("e1000_pool_flash_update_done_i210");
 
        for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
                reg = E1000_READ_REG(hw, E1000_EECD);
                if (reg & E1000_EECD_FLUDONE_I210) {
                        ret_val = E1000_SUCCESS;
                        break;
                }
                usec_delay(5);
        }
 
        return ret_val;
}
 
static s32 e1000_init_nvm_params_i210(struct e1000_hw *hw)
{
        s32 ret_val;
        struct e1000_nvm_info *nvm = &hw->nvm;
 
        DEBUGFUNC("e1000_init_nvm_params_i210");
 
        ret_val = e1000_init_nvm_params_82575(hw);
        nvm->ops.acquire = e1000_acquire_nvm_i210;
        nvm->ops.release = e1000_release_nvm_i210;
        nvm->ops.valid_led_default = e1000_valid_led_default_i210;
        if (e1000_get_flash_presence_i210(hw)) {
                hw->nvm.type = e1000_nvm_flash_hw;
                nvm->ops.read    = e1000_read_nvm_srrd_i210;
                nvm->ops.write   = e1000_write_nvm_srwr_i210;
                nvm->ops.validate = e1000_validate_nvm_checksum_i210;
                nvm->ops.update   = e1000_update_nvm_checksum_i210;
        } else {
                hw->nvm.type = e1000_nvm_invm;
                nvm->ops.read     = e1000_read_invm_i210;
                nvm->ops.write    = e1000_null_write_nvm;
                nvm->ops.validate = e1000_null_ops_generic;
                nvm->ops.update   = e1000_null_ops_generic;
        }
        return ret_val;
}
 
void e1000_init_function_pointers_i210(struct e1000_hw *hw)
{
        e1000_init_function_pointers_82575(hw);
        hw->nvm.ops.init_params = e1000_init_nvm_params_i210;
}
 
static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
{
        s32 ret_val;
 
        DEBUGFUNC("e1000_valid_led_default_i210");
 
        ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
        if (ret_val) {
                DEBUGOUT("NVM Read Error\n");
                goto out;
        }
 
        if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
                switch (hw->phy.media_type) {
                case e1000_media_type_internal_serdes:
                        *data = ID_LED_DEFAULT_I210_SERDES;
                        break;
                case e1000_media_type_copper:
                default:
                        *data = ID_LED_DEFAULT_I210;
                        break;
                }
        }
out:
        return ret_val;
}
 
static s32 e1000_pll_workaround_i210(struct e1000_hw *hw)
{
        s32 ret_val;
        u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;
        u16 nvm_word, phy_word, pci_word, tmp_nvm;
        int i;
 
        /* Get PHY semaphore */
        hw->phy.ops.acquire(hw);
        /* Get and set needed register values */
        wuc = E1000_READ_REG(hw, E1000_WUC);
        mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
        reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
        E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val);
 
        /* Get data from NVM, or set default */
        ret_val = e1000_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD,
                                            &nvm_word);
        if (ret_val != E1000_SUCCESS)
                nvm_word = E1000_INVM_DEFAULT_AL;
        tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;
        phy_word = E1000_PHY_PLL_UNCONF;
        for (i = 0; i < E1000_MAX_PLL_TRIES; i++) {
                /* check current state directly from internal PHY */
                e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0xFC);
                usec_delay(20);
                e1000_read_phy_reg_mdic(hw, E1000_PHY_PLL_FREQ_REG, &phy_word);
                usec_delay(20);
                e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0);
                if ((phy_word & E1000_PHY_PLL_UNCONF)
                    != E1000_PHY_PLL_UNCONF) {
                        ret_val = E1000_SUCCESS;
                        break;
                } else {
                        ret_val = -E1000_ERR_PHY;
                }
                /* directly reset the internal PHY */
                ctrl = E1000_READ_REG(hw, E1000_CTRL);
                E1000_WRITE_REG(hw, E1000_CTRL, ctrl|E1000_CTRL_PHY_RST);
 
                ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
                ctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE);
                E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 
                E1000_WRITE_REG(hw, E1000_WUC, 0);
                reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
                E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
 
                e1000_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
                pci_word |= E1000_PCI_PMCSR_D3;
                e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
                msec_delay(1);
                pci_word &= ~E1000_PCI_PMCSR_D3;
                e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
                reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
                E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
 
                /* restore WUC register */
                E1000_WRITE_REG(hw, E1000_WUC, wuc);
        }
        /* restore MDICNFG setting */
        E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
        /* Release PHY semaphore */
        hw->phy.ops.release(hw);
        return ret_val;
}
 
static s32 e1000_get_cfg_done_i210(struct e1000_hw *hw)
{
        s32 timeout = PHY_CFG_TIMEOUT;
        u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 
        DEBUGFUNC("e1000_get_cfg_done_i210");
 
        while (timeout) {
                if (E1000_READ_REG(hw, E1000_EEMNGCTL_I210) & mask)
                        break;
                msec_delay(1);
                timeout--;
        }
        if (!timeout)
                DEBUGOUT("MNG configuration cycle has not completed.\n");
 
        return E1000_SUCCESS;
}
 
s32 e1000_init_hw_i210(struct e1000_hw *hw)
{
        struct e1000_mac_info *mac = &hw->mac;
        s32 ret_val;
 
        DEBUGFUNC("e1000_init_hw_i210");
        if ((hw->mac.type >= e1000_i210) &&
            !(e1000_get_flash_presence_i210(hw))) {
                ret_val = e1000_pll_workaround_i210(hw);
                if (ret_val != E1000_SUCCESS)
                        return ret_val;
        }
        hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210;
 
        /* Initialize identification LED */
        mac->ops.id_led_init(hw);
 
        ret_val = e1000_init_hw_base(hw);
        return ret_val;
}