192 DEBUGFUNC(
"e1000_get_bus_info_pci_generic");
245 u16 pcie_link_status;
247 DEBUGFUNC(
"e1000_get_bus_info_pcie_generic");
381 u8 mac_addr[ETHER_ADDR_LEN] = {0};
383 DEBUGFUNC(
"e1000_init_rx_addrs_generic");
386 DEBUGOUT(
"Programming MAC Address into RAR[0]\n");
391 DEBUGOUT1(
"Clearing RAR[1-%u]\n", rar_count-1);
392 for (i = 1; i < rar_count; i++)
412 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
413 u8 alt_mac_addr[ETHER_ADDR_LEN];
415 DEBUGFUNC(
"e1000_check_alt_mac_addr_generic");
432 &nvm_alt_mac_addr_offset);
438 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
439 (nvm_alt_mac_addr_offset == 0x0000))
450 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
451 offset = nvm_alt_mac_addr_offset + (i >> 1);
452 ret_val = hw->
nvm.
ops.
read(hw, offset, 1, &nvm_data);
458 alt_mac_addr[i] = (
u8)(nvm_data & 0xFF);
459 alt_mac_addr[i + 1] = (
u8)(nvm_data >> 8);
463 if (alt_mac_addr[0] & 0x01) {
464 DEBUGOUT(
"Ignoring Alternate Mac Address with MC bit set\n");
488 u32 rar_low, rar_high;
495 rar_low = ((
u32) addr[0] | ((
u32) addr[1] << 8) |
496 ((
u32) addr[2] << 16) | ((
u32) addr[3] << 24));
498 rar_high = ((
u32) addr[4] | ((
u32) addr[5] << 8));
501 if (rar_low || rar_high)
526 u32 hash_value, hash_mask;
537 while (hash_mask >> bit_shift != 0xFF)
580 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
581 (((
u16) mc_addr[5]) << bit_shift)));
596 u8 *mc_addr_list,
u32 mc_addr_count)
598 u32 hash_value, hash_bit, hash_reg;
601 DEBUGFUNC(
"e1000_update_mc_addr_list_generic");
607 for (i = 0; (
u32) i < mc_addr_count; i++) {
611 hash_bit = hash_value & 0x1F;
614 mc_addr_list += (ETHER_ADDR_LEN);
636 u16 pcix_stat_hi_word;
639 DEBUGFUNC(
"e1000_pcix_mmrbc_workaround_generic");
653 if (cmd_mmrbc > stat_mmrbc) {
654 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
668 DEBUGFUNC(
"e1000_clear_hw_cntrs_base_generic");
723 DEBUGFUNC(
"e1000_check_for_copper_link");
770 DEBUGOUT(
"Error configuring flow control\n");
790 DEBUGFUNC(
"e1000_check_for_fiber_link_generic");
810 DEBUGOUT(
"NOT Rx'ing /C/, disable AutoNeg and force link.\n");
823 DEBUGOUT(
"Error configuring flow control\n");
832 DEBUGOUT(
"Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
857 DEBUGFUNC(
"e1000_check_for_serdes_link_generic");
875 DEBUGOUT(
"NOT Rx'ing /C/, disable AutoNeg and force link.\n");
888 DEBUGOUT(
"Error configuring flow control\n");
897 DEBUGOUT(
"Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
913 DEBUGOUT(
"SERDES: Link up - forced.\n");
917 DEBUGOUT(
"SERDES: Link down - force failed.\n");
930 DEBUGOUT(
"SERDES: Link up - autoneg completed successfully.\n");
933 DEBUGOUT(
"SERDES: Link down - invalid codewords detected in autoneg.\n");
937 DEBUGOUT(
"SERDES: Link down - no sync.\n");
941 DEBUGOUT(
"SERDES: Link down - autoneg failed\n");
961 DEBUGFUNC(
"e1000_set_default_fc_generic");
1036 DEBUGOUT1(
"After fix-ups FlowControl is now = %x\n",
1049 DEBUGOUT(
"Initializing the Flow Control address, type and timer regs\n");
1071 DEBUGFUNC(
"e1000_commit_fc_settings_generic");
1117 DEBUGOUT(
"Flow control param set incorrectly\n");
1141 DEBUGFUNC(
"e1000_poll_fiber_serdes_link_generic");
1156 DEBUGOUT(
"Never got a valid link from auto-neg!!!\n");
1165 DEBUGOUT(
"Error while checking for link\n");
1189 DEBUGFUNC(
"e1000_setup_fiber_serdes_link_generic");
1194 ctrl &= ~E1000_CTRL_LRST;
1208 DEBUGOUT(
"Auto-negotiation enabled\n");
1239 DEBUGFUNC(
"e1000_config_collision_dist_generic");
1243 tctl &= ~E1000_TCTL_COLD;
1260 u32 fcrtl = 0, fcrth = 0;
1262 DEBUGFUNC(
"e1000_set_fc_watermarks_generic");
1301 DEBUGFUNC(
"e1000_force_mac_fc_generic");
1329 ctrl &= (~E1000_CTRL_TFCE);
1333 ctrl &= (~E1000_CTRL_RFCE);
1340 DEBUGOUT(
"Flow control param set incorrectly\n");
1363 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1364 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1367 DEBUGFUNC(
"e1000_config_fc_after_link_up_generic");
1383 DEBUGOUT(
"Error forcing flow control settings\n");
1405 DEBUGOUT(
"Copper PHY and Auto Neg has not completed.\n");
1420 &mii_nway_lp_ability_reg);
1467 DEBUGOUT(
"Flow Control = FULL.\n");
1470 DEBUGOUT(
"Flow Control = Rx PAUSE frames only.\n");
1485 DEBUGOUT(
"Flow Control = Tx PAUSE frames only.\n");
1499 DEBUGOUT(
"Flow Control = Rx PAUSE frames only.\n");
1505 DEBUGOUT(
"Flow Control = NONE.\n");
1514 DEBUGOUT(
"Error getting link speed and duplex\n");
1526 DEBUGOUT(
"Error forcing flow control settings\n");
1544 DEBUGOUT(
"PCS Auto Neg has not completed.\n");
1600 DEBUGOUT(
"Flow Control = FULL.\n");
1603 DEBUGOUT(
"Flow Control = Rx PAUSE frames only.\n");
1618 DEBUGOUT(
"Flow Control = Tx PAUSE frames only.\n");
1632 DEBUGOUT(
"Flow Control = Rx PAUSE frames only.\n");
1638 DEBUGOUT(
"Flow Control = NONE.\n");
1650 DEBUGOUT(
"Error forcing flow control settings\n");
1672 DEBUGFUNC(
"e1000_get_speed_and_duplex_copper_generic");
1709 DEBUGFUNC(
"e1000_get_speed_and_duplex_fiber_serdes_generic");
1727 DEBUGFUNC(
"e1000_get_auto_rd_done_generic");
1737 DEBUGOUT(
"Auto read by HW from NVM has not completed.\n");
1756 DEBUGFUNC(
"e1000_valid_led_default_generic");
1779 const u32 ledctl_mask = 0x000000FF;
1783 const u16 led_mask = 0x0F;
1795 for (i = 0; i < 4; i++) {
1796 temp = (data >> (i << 2)) & led_mask;
1891 u32 ledctl_blink = 0;
1908 for (i = 0; i < 32; i += 8) {
1945 ctrl &= ~E1000_CTRL_SWDPIN0;
1999 DEBUGFUNC(
"e1000_set_pcie_no_snoop_generic");
2028 DEBUGFUNC(
"e1000_disable_pcie_master_generic");
2047 DEBUGOUT(
"Master requests are pending.\n");
2064 DEBUGFUNC(
"e1000_reset_adaptive_generic");
2067 DEBUGOUT(
"Not in Adaptive IFS mode!\n");
2092 DEBUGFUNC(
"e1000_update_adaptive_generic");
2095 DEBUGOUT(
"Not in Adaptive IFS mode!\n");
2131 DEBUGFUNC(
"e1000_validate_mdi_setting_generic");
2134 DEBUGOUT(
"Invalid MDI setting detected\n");
2151 DEBUGFUNC(
"e1000_validate_mdi_setting_crossover_generic");
2168 u32 offset,
u8 data)
2170 u32 i, regvalue = 0;
2172 DEBUGFUNC(
"e1000_write_8bit_ctrl_reg_generic");
2186 DEBUGOUT1(
"Reg %08x did not indicate ready\n", reg);
2221 while (i < sw_timeout) {
2230 if (i == sw_timeout) {
2231 DEBUGOUT(
"Driver can't access device - SMBI bit is set.\n");
2241 for (i = 0; i < fw_timeout; i++) {
2251 for (i = 0; i < fw_timeout; i++) {
2262 if (i == fw_timeout) {
2265 DEBUGOUT(
"Driver can't access the NVM\n");
2305 u32 fwmask = mask << 16;
2307 s32 i = 0, timeout = 200;
2311 while (i < timeout) {
2318 if (!(swfw_sync & (fwmask | swmask)))
2331 DEBUGOUT(
"Driver can't access resource, SW_FW_SYNC timeout.\n");
2336 swfw_sync |= swmask;
2364 swfw_sync &= (
u32)~mask;
#define ID_LED_RESERVED_0000
#define E1000_TXCW_ASM_DIR
#define MII_SR_AUTONEG_COMPLETE
#define NWAY_LPAR_ASM_DIR
#define E1000_STATUS_PCIX_SPEED_133
#define E1000_GEN_CTL_READY
#define NVM_ALT_MAC_ADDR_PTR
#define NVM_WORD0F_PAUSE_MASK
#define FLOW_CONTROL_ADDRESS_LOW
#define E1000_GEN_CTL_ADDRESS_SHIFT
#define E1000_PCS_LSTS_AN_COMPLETE
#define PCIE_LINK_SPEED_5000
#define NVM_INIT_CONTROL2_REG
#define FLOW_CONTROL_ADDRESS_HIGH
#define E1000_STATUS_PCIX_MODE
#define E1000_CTRL_GIO_MASTER_DISABLE
#define E1000_STATUS_FUNC_SHIFT
#define E1000_STATUS_SPEED_1000
#define E1000_LEDCTL_MODE_LED_OFF
#define PCIE_LINK_SPEED_2500
#define PCIX_COMMAND_REGISTER
#define E1000_TXCW_PAUSE_MASK
#define PCIE_LINK_WIDTH_MASK
#define E1000_STATUS_PCIX_SPEED_100
#define MASTER_DISABLE_TIMEOUT
#define PCIE_LINK_SPEED_MASK
#define PCIX_STATUS_HI_MMRBC_2K
#define E1000_STATUS_SPEED_100
#define PCIX_STATUS_HI_MMRBC_SHIFT
#define PCI_HEADER_TYPE_MULTIFUNC
#define E1000_VLAN_FILTER_TBL_SIZE
#define FLOW_CONTROL_TYPE
#define E1000_ERR_MASTER_REQUESTS_PENDING
#define E1000_LEDCTL_LED0_MODE_SHIFT
#define ID_LED_RESERVED_FFFF
#define PCIX_STATUS_HI_MMRBC_4K
#define E1000_STATUS_PCI66
#define NVM_82580_LAN_FUNC_OFFSET(a)
#define E1000_STATUS_PCIX_SPEED_66
#define AUTO_READ_DONE_TIMEOUT
#define PCIX_COMMAND_MMRBC_MASK
#define E1000_LEDCTL_LED0_IVRT
#define PCIE_NO_SNOOP_ALL
#define PCIX_STATUS_REGISTER_HI
#define PCIX_COMMAND_MMRBC_SHIFT
#define E1000_CTRL_SWDPIN1
#define E1000_ERR_SWFW_SYNC
#define E1000_CTRL_SWDPIO0
#define PCI_HEADER_TYPE_REGISTER
#define NVM_WORD0F_ASM_DIR
#define E1000_LEDCTL_LED0_BLINK
#define PCIX_STATUS_HI_MMRBC_MASK
#define E1000_PCS_LCTL_FORCE_FCTRL
#define E1000_CTRL_SWDPIN0
#define E1000_COLLISION_DISTANCE
#define E1000_LEDCTL_LED0_MODE_MASK
#define E1000_SWSM_SWESMBI
#define E1000_STATUS_PCIX_SPEED
#define E1000_STATUS_FUNC_MASK
#define PCIE_LINK_WIDTH_SHIFT
#define E1000_GEN_POLL_TIMEOUT
#define FIBER_LINK_UP_LIMIT
#define E1000_STATUS_GIO_MASTER_ENABLE
#define E1000_EECD_AUTO_RD
#define E1000_LEDCTL_MODE_LED_ON
#define E1000_STATUS_BUS64
#define NVM_ID_LED_SETTINGS
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2
@ e1000_bus_width_unknown
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3
@ e1000_bus_type_pci_express
void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
@ e1000_bus_speed_reserved
@ e1000_bus_speed_unknown
s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1
@ e1000_media_type_internal_serdes
@ e1000_media_type_copper
void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
void e1000_reset_adaptive_generic(struct e1000_hw *hw)
s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, u32 E1000_UNUSEDARG a)
s32 e1000_get_hw_semaphore(struct e1000_hw *hw)
s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
void e1000_init_mac_ops_generic(struct e1000_hw *hw)
void e1000_update_adaptive_generic(struct e1000_hw *hw)
s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
s32 e1000_id_led_init_generic(struct e1000_hw *hw)
bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
s32 e1000_acquire_swfw_sync(struct e1000_hw *hw, u16 mask)
s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
void e1000_put_hw_semaphore(struct e1000_hw *hw)
s32 e1000_led_on_generic(struct e1000_hw *hw)
s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
s32 e1000_setup_link_generic(struct e1000_hw *hw)
void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
void e1000_release_swfw_sync(struct e1000_hw *hw, u16 mask)
s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
s32 e1000_led_off_generic(struct e1000_hw *hw)
void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count)
s32 e1000_blink_led_generic(struct e1000_hw *hw)
s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
void e1000_clear_vfta_generic(struct e1000_hw *hw)
s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, u16 *duplex)
void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, u16 *speed, u16 *duplex)
s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
s32 e1000_setup_led_generic(struct e1000_hw *hw)
s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
void e1000_set_lan_id_single_port(struct e1000_hw *hw)
s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, u32 offset, u8 data)
s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value)
#define ASSERT_NO_LOCKS()
#define E1000_WRITE_FLUSH(a)
#define E1000_WRITE_REG(hw, reg, value)
#define msec_delay_irq(x)
#define E1000_READ_REG(hw, reg)
s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success)
s32 e1000_check_downshift_generic(struct e1000_hw *hw)
enum e1000_bus_speed speed
enum e1000_bus_width width
bool clear_semaphore_once
enum e1000_fc_mode current_mode
enum e1000_fc_mode requested_mode
union e1000_hw::@46 dev_spec
struct e1000_bus_info bus
struct e1000_mac_info mac
struct e1000_dev_spec_82571 _82571
struct e1000_dev_spec_82575 _82575
struct e1000_nvm_info nvm
struct e1000_phy_info phy
struct e1000_mac_operations ops
u32 mta_shadow[MAX_MTA_REG]
s32(* setup_led)(struct e1000_hw *)
s32(* get_link_up_info)(struct e1000_hw *, u16 *, u16 *)
s32(* setup_physical_interface)(struct e1000_hw *)
s32(* validate_mdi_setting)(struct e1000_hw *)
s32(* check_for_link)(struct e1000_hw *)
void(* config_collision_dist)(struct e1000_hw *)
void(* clear_vfta)(struct e1000_hw *)
s32(* blink_led)(struct e1000_hw *)
s32(* reset_hw)(struct e1000_hw *)
s32(* set_obff_timer)(struct e1000_hw *, u32)
s32(* led_on)(struct e1000_hw *)
s32(* read_mac_addr)(struct e1000_hw *)
void(* write_vfta)(struct e1000_hw *, u32, u32)
int(* rar_set)(struct e1000_hw *, u8 *, u32)
s32(* init_hw)(struct e1000_hw *)
s32(* setup_link)(struct e1000_hw *)
s32(* cleanup_led)(struct e1000_hw *)
void(* clear_hw_cntrs)(struct e1000_hw *)
void(* set_lan_id)(struct e1000_hw *)
void(* update_mc_addr_list)(struct e1000_hw *, u8 *, u32)
s32(* led_off)(struct e1000_hw *)
bool(* check_mng_mode)(struct e1000_hw *)
s32(* get_bus_info)(struct e1000_hw *)
s32(* init_params)(struct e1000_hw *)
struct e1000_nvm_operations ops
s32(* read)(struct e1000_hw *, u16, u16, u16 *)
s32(* valid_led_default)(struct e1000_hw *, u16 *)
enum e1000_media_type media_type
struct e1000_phy_operations ops
s32(* read_reg)(struct e1000_hw *, u32, u16 *)
s32(* check_reset_block)(struct e1000_hw *)