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Macros
#define	E1000_CTRL 0x00000 /* Device Control - RW */

#define	E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */

#define	E1000_STATUS 0x00008 /* Device Status - RO */

#define	E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */

#define	E1000_EERD 0x00014 /* EEPROM Read - RW */

#define	E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */

#define	E1000_FLA 0x0001C /* Flash Access - RW */

#define	E1000_MDIC 0x00020 /* MDI Control - RW */

#define	E1000_MDICNFG 0x00E04 /* MDI Config - RW */

#define	E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */

#define	E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */

#define	E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */

#define	E1000_BARCTRL 0x5BBC /* BAR ctrl reg */

#define	E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */

#define	E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */

#define	E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */

#define	E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */

#define	E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */

#define	E1000_PPHY_CTRL 0x5b48 /* PCIe PHY Control */

#define	E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */

#define	E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/

#define	E1000_SCTL 0x00024 /* SerDes Control - RW */

#define	E1000_FCAL 0x00028 /* Flow Control Address Low - RW */

#define	E1000_FCAH 0x0002C /* Flow Control Address High -RW */

#define	E1000_FEXT 0x0002C /* Future Extended - RW */

#define	E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */

#define	E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */

#define	E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */

#define	E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */

#define	E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */

#define	E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */

#define	E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */

#define	E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */

#define	E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */

#define	E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */

#define	E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */

#define	E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */

#define	E1000_FCT 0x00030 /* Flow Control Type - RW */

#define	E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */

#define	E1000_VET 0x00038 /* VLAN Ether Type - RW */

#define	E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */

#define	E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */

#define	E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */

#define	E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */

#define	E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */

#define	E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */

#define	E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */

#define	E1000_SVCR 0x000F0

#define	E1000_SVT 0x000F4

#define	E1000_LPIC 0x000FC /* Low Power IDLE control */

#define	E1000_RCTL 0x00100 /* Rx Control - RW */

#define	E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */

#define	E1000_TXCW 0x00178 /* Tx Configuration Word - RW */

#define	E1000_RXCW 0x00180 /* Rx Configuration Word - RO */

#define	E1000_PBA_ECC 0x01100 /* PBA ECC Register */

#define	E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */

#define	E1000_EITR(_n) (0x01680 + (0x4 * (_n)))

#define	E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */

#define	E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */

#define	E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */

#define	E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */

#define	E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */

#define	E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */

#define	E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */

#define	E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */

#define	E1000_TCTL 0x00400 /* Tx Control - RW */

#define	E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */

#define	E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */

#define	E1000_TBT 0x00448 /* Tx Burst Timer - RW */

#define	E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */

#define	E1000_LEDCTL 0x00E00 /* LED Control - RW */

#define	E1000_LEDMUX 0x08130 /* LED MUX Control */

#define	E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */

#define	E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */

#define	E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */

#define	E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */

#define	E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */

#define	E1000_PBS 0x01008 /* Packet Buffer Size */

#define	E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */

#define	E1000_IOSFPC 0x00F28 /* TX corrupted data */

#define	E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */

#define	E1000_EEMNGCTL_I210 0x01010 /* i210 MNG EEprom Mode Control */

#define	E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */

#define	E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */

#define	E1000_FLASHT 0x01028 /* FLASH Timer Register */

#define	E1000_EEWR 0x0102C /* EEPROM Write Register - RW */

#define	E1000_FLSWCTL 0x01030 /* FLASH control register */

#define	E1000_FLSWDATA 0x01034 /* FLASH data register */

#define	E1000_FLSWCNT 0x01038 /* FLASH Access Counter */

#define	E1000_FLOP 0x0103C /* FLASH Opcode Register */

#define	E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */

#define	E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */

#define	E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */

#define	E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */

#define	E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */

#define	E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */

#define	E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */

#define	E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */

#define	E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */

#define	E1000_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */

#define	E1000_WDSTP 0x01040 /* Watchdog Setup - RW */

#define	E1000_SWDSTS 0x01044 /* SW Device Status - RW */

#define	E1000_FRTIMER 0x01048 /* Free Running Timer - RW */

#define	E1000_TCPTIMER 0x0104C /* TCP Timer - RW */

#define	E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */

#define	E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */

#define	E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */

#define	E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */

#define	E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */

#define	E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */

#define	E1000_ERT 0x02008 /* Early Rx Threshold - RW */

#define	E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */

#define	E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */

#define	E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */

#define	E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */

#define	E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */

#define	E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */

#define	E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */

#define	E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */

#define	E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */

#define	E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */

#define	E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */

#define	E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */

#define	E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */

#define	E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */

#define	E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */

#define	E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */

#define	E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */

#define	E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */

#define	E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */

#define	E1000_RDTR 0x02820 /* Rx Delay Timer - RW */

#define	E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */

#define	E1000_EMIADD 0x10 /* Extended Memory Indirect Address */

#define	E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */

#define	E1000_SRWR 0x12018

#define	E1000_EEC_REG 0x12010

#define	E1000_I210_FLMNGCTL 0x12038

#define	E1000_I210_FLMNGDATA 0x1203C

#define	E1000_I210_FLMNGCNT 0x12040

#define	E1000_I210_FLSWCTL 0x12048

#define	E1000_I210_FLSWDATA 0x1204C

#define	E1000_I210_FLSWCNT 0x12050

#define	E1000_I210_FLA 0x1201C

#define	E1000_SHADOWINF 0x12068

#define	E1000_FLFWUPDATE 0x12108

#define	E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))

#define	E1000_INVM_SIZE 64 /* Number of INVM Data Registers */

#define	E1000_I210_TQAVCTRL 0x3570

#define	E1000_TQAVCTRL_MODE (1 << 0)

#define	E1000_TQAVCTRL_FETCH_ARB (1 << 4)

#define	E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5)

#define	E1000_TQAVCTRL_LAUNCH_ARB (1 << 8)

#define	E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9)

#define	E1000_TQAVCTRL_SP_WAIT_SR (1 << 10)

#define	E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16

#define	E1000_TQAVCTRL_FETCH_TIMER_DELTA (0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)

#define	E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n))

#define	E1000_I210_TQAVARBCTRL 0x3574

#define	E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n)))

#define	E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n))

#define	E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */

#define	E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */

#define	E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */

#define	E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))

#define	E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n)))

#define	E1000_MMDAC 13 /* MMD Access Control */

#define	E1000_MMDAAD 14 /* MMD Access Address/Data */

#define	E1000_RDBAL(_n)

#define	E1000_RDBAH(_n)

#define	E1000_RDLEN(_n)

#define	E1000_SRRCTL(_n)

#define	E1000_RDH(_n)

#define	E1000_RXCTL(_n)

#define	E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)

#define	E1000_RDT(_n)

#define	E1000_RXDCTL(_n)

#define	E1000_RQDPC(_n)

#define	E1000_TDBAL(_n)

#define	E1000_TDBAH(_n)

#define	E1000_TDLEN(_n)

#define	E1000_TDH(_n)

#define	E1000_TXCTL(_n)

#define	E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)

#define	E1000_TDT(_n)

#define	E1000_TXDCTL(_n)

#define	E1000_TDWBAL(_n)

#define	E1000_TDWBAH(_n)

#define	E1000_TARC(_n) (0x03840 + ((_n) * 0x100))

#define	E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */

#define	E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */

#define	E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */

#define	E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */

#define	E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))

#define	E1000_RAL(_i)

#define	E1000_RAH(_i)

#define	E1000_SHRAL(_i) (0x05438 + ((_i) * 8))

#define	E1000_SHRAH(_i) (0x0543C + ((_i) * 8))

#define	E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))

#define	E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))

#define	E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))

#define	E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))

#define	E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))

#define	E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))

#define	E1000_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */

#define	E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */

#define	E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */

#define	E1000_ITPBS 0x03404

#define	E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */

#define	E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */

#define	E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */

#define	E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */

#define	E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */

#define	E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */

#define	E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */

#define	E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */

#define	E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */

#define	E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */

#define	E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */

#define	E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */

#define	E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */

#define	E1000_DTXMXSZRQ 0x03540

#define	E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */

#define	E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */

#define	E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */

#define	E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */

#define	E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */

#define	E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */

#define	E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */

#define	E1000_MPC 0x04010 /* Missed Packet Count - R/clr */

#define	E1000_SCC 0x04014 /* Single Collision Count - R/clr */

#define	E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */

#define	E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */

#define	E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */

#define	E1000_COLC 0x04028 /* Collision Count - R/clr */

#define	E1000_DC 0x04030 /* Defer Count - R/clr */

#define	E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */

#define	E1000_SEC 0x04038 /* Sequence Error Count - R/clr */

#define	E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */

#define	E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */

#define	E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */

#define	E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */

#define	E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */

#define	E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */

#define	E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */

#define	E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */

#define	E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */

#define	E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */

#define	E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */

#define	E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */

#define	E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */

#define	E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */

#define	E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */

#define	E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */

#define	E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */

#define	E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */

#define	E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */

#define	E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */

#define	E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */

#define	E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */

#define	E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */

#define	E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */

#define	E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */

#define	E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */

#define	E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */

#define	E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */

#define	E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */

#define	E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */

#define	E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */

#define	E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */

#define	E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */

#define	E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */

#define	E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */

#define	E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */

#define	E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */

#define	E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */

#define	E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */

#define	E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */

#define	E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */

#define	E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */

#define	E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */

#define	E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */

#define	E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */

#define	E1000_IAC 0x04100 /* Interrupt Assertion Count */

#define	E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */

#define	E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */

#define	E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */

#define	E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */

#define	E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */

#define	E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */

#define	E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */

#define	E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */

#define	E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */

#define	E1000_VFGPRC 0x00F10

#define	E1000_VFGORC 0x00F18

#define	E1000_VFMPRC 0x00F3C

#define	E1000_VFGPTC 0x00F14

#define	E1000_VFGOTC 0x00F34

#define	E1000_VFGOTLBC 0x00F50

#define	E1000_VFGPTLBC 0x00F44

#define	E1000_VFGORLBC 0x00F48

#define	E1000_VFGPRLBC 0x00F40

#define	E1000_PFVFGPRC(_n) (0x010010 + (0x100 * (_n)))

#define	E1000_PFVFGPTC(_n) (0x010014 + (0x100 * (_n)))

#define	E1000_PFVFGORC(_n) (0x010018 + (0x100 * (_n)))

#define	E1000_PFVFGOTC(_n) (0x010034 + (0x100 * (_n)))

#define	E1000_PFVFMPRC(_n) (0x010038 + (0x100 * (_n)))

#define	E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n)))

#define	E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n)))

#define	E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n)))

#define	E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n)))

#define	E1000_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */

#define	E1000_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */

#define	E1000_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */

#define	E1000_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */

#define	E1000_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */

#define	E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */

#define	E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */

#define	E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */

#define	E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */

#define	E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */

#define	E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */

#define	E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */

#define	E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */

#define	E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */

#define	E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */

#define	E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */

#define	E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */

#define	E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */

#define	E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */

#define	E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */

#define	E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */

#define	E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */

#define	E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */

#define	E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */

#define	E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */

#define	E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */

#define	E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */

#define	E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */

#define	E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */

#define	E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */

#define	E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n)))

#define	E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n)))

#define	E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */

#define	E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */

#define	E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))

#define	E1000_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */

#define	E1000_IPSCTRL 0xB430 /* IpSec Control Register */

#define	E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */

#define	E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */

#define	E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n)))

#define	E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n)))

#define	E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */

#define	E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */

#define	E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n)))

#define	E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */

#define	E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */

#define	E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */

#define	E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */

#define	E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */

#define	E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */

#define	E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */

#define	E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */

#define	E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */

#define	E1000_RPTHC 0x04104 /* Rx Packets To Host */

#define	E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */

#define	E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */

#define	E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */

#define	E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */

#define	E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */

#define	E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */

#define	E1000_LENERRS 0x04138 /* Length Errors Count */

#define	E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */

#define	E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */

#define	E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */

#define	E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */

#define	E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */

#define	E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */

#define	E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */

#define	E1000_RLPML 0x05004 /* Rx Long Packet Max Length */

#define	E1000_RFCTL 0x05008 /* Receive Filter Control*/

#define	E1000_MTA 0x05200 /* Multicast Table Array - RW Array */

#define	E1000_RA 0x05400 /* Receive Address - RW Array */

#define	E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */

#define	E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */

#define	E1000_VT_CTL 0x0581C /* VMDq Control - RW */

#define	E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */

#define	E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */

#define	E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */

#define	E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */

#define	E1000_WUC 0x05800 /* Wakeup Control - RW */

#define	E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */

#define	E1000_WUS 0x05810 /* Wakeup Status - RO */

#define	E1000_MANC 0x05820 /* Management Control - RW */

#define	E1000_IPAV 0x05838 /* IP Address Valid - RW */

#define	E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */

#define	E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */

#define	E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */

#define	E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */

#define	E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */

#define	E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */

#define	E1000_HOST_IF 0x08800 /* Host Interface */

#define	E1000_HIBBA 0x8F40 /* Host Interface Buffer Base Address */

#define	E1000_FHFT(_n) (0x09000 + ((_n) * 0x100))

#define	E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100))

#define	E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */

#define	E1000_MANC2H 0x05860 /* Management Control To Host - RW */

#define	E1000_MDEF(_n) (0x05890 + (4 * (_n)))

#define	E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */

#define	E1000_CCMCTL 0x05B48 /* CCM Control Register */

#define	E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */

#define	E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */

#define	E1000_GCR 0x05B00 /* PCI-Ex Control */

#define	E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */

#define	E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */

#define	E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */

#define	E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */

#define	E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */

#define	E1000_FACTPS 0x05B30

#define	E1000_SWSM 0x05B50 /* SW Semaphore */

#define	E1000_FWSM 0x05B54 /* FW Semaphore */

#define	E1000_SWSM2 0x05B58

#define	E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */

#define	E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */

#define	E1000_UFUSE 0x05B78 /* UFUSE - RO */

#define	E1000_FFLT_DBG 0x05F04 /* Debug Register */

#define	E1000_HICR 0x08F00 /* Host Interface Control */

#define	E1000_FWSTS 0x08F0C /* FW Status */

#define	E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */

#define	E1000_MRQC 0x05818 /* Multiple Receive Control - RW */

#define	E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */

#define	E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/

#define	E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */

#define	E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */

#define	E1000_RETA(_i) (0x05C00 + ((_i) * 4))

#define	E1000_RSSRK(_i) (0x05C80 + ((_i) * 4))

#define	E1000_RSSIM 0x05864 /* RSS Interrupt Mask */

#define	E1000_RSSIR 0x05868 /* RSS Interrupt Request */

#define	E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */

#define	E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */

#define	E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */

#define	E1000_VFLRE 0x00C88 /* VF Register Events - RWC */

#define	E1000_VFRE 0x00C8C /* VF Receive Enables */

#define	E1000_VFTE 0x00C90 /* VF Transmit Enables */

#define	E1000_QDE 0x02408 /* Queue Drop Enable - RW */

#define	E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */

#define	E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */

#define	E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */

#define	E1000_UTA 0x0A000 /* Unicast Table Array - RW */

#define	E1000_IOVCTL 0x05BBC /* IOV Control Register */

#define	E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */

#define	E1000_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */

#define	E1000_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */

#define	E1000_MDFB 0x03558 /* Malicious Driver free block */

#define	E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */

#define	E1000_TXSWC 0x05ACC /* Tx Switch Control */

#define	E1000_SCCRL 0x05DB0 /* Storm Control Control */

#define	E1000_BSCTRH 0x05DB8 /* Broadcast Storm Control Threshold */

#define	E1000_MSCTRH 0x05DBC /* Multicast Storm Control Threshold */

#define	E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))

#define	E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))

#define	E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))

#define	E1000_VFVMBMEM(_n) (0x00800 + (_n))

#define	E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))

#define	E1000_VLVF(_n) (0x05D00 + (4 * (_n)))

#define	E1000_VMVIR(_n) (0x03700 + (4 * (_n)))

#define	E1000_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */

#define	E1000_VTCTRL(_n) (0x10000 + (0x100 * (_n))) /* VT Control */

#define	E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */

#define	E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */

#define	E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */

#define	E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */

#define	E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */

#define	E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */

#define	E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */

#define	E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */

#define	E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */

#define	E1000_SYSTIML 0x0B600 /* System time register Low - RO */

#define	E1000_SYSTIMH 0x0B604 /* System time register High - RO */

#define	E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */

#define	E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */

#define	E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */

#define	E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */

#define	E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */

#define	E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */

#define	E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */

#define	E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */

#define	E1000_SYSTIMR 0x0B6F8 /* System time register Residue */

#define	E1000_TSICR 0x0B66C /* Interrupt Cause Register */

#define	E1000_TSIM 0x0B674 /* Interrupt Mask Register */

#define	E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */

#define	E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */

#define	E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */

#define	E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */

#define	E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */

#define	E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */

#define	E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */

#define	E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */

#define	E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */

#define	E1000_ETQF_FILTER_ENABLE (1 << 26)

#define	E1000_ETQF_IMM_INT (1 << 29)

#define	E1000_ETQF_QUEUE_ENABLE (1U << 31)

#define	E1000_ETQF_QUEUE_SHIFT 16

#define	E1000_ETQF_QUEUE_MASK 0x00070000

#define	E1000_ETQF_ETYPE_MASK 0x0000FFFF

#define	E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */

#define	E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */

#define	E1000_RTRPCS 0x2474 /* Rx packet plane control and status */

#define	E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */

#define	E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */

#define	E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4))

#define	E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4))

#define	E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4))

#define	E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4))

#define	E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4))

#define	E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4))

#define	E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4))

#define	E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4))

#define	E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4))

#define	E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4))

#define	E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4))

#define	E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */

#define	E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */

#define	E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */

#define	E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */

#define	E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */

#define	E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */

#define	E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */

#define	E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */

#define	E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */

#define	E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */

#define	E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */

#define	E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */

#define	E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */

#define	E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */

#define	E1000_DMACR 0x02508 /* Control Register */

#define	E1000_DMCTXTH 0x03550 /* Transmit Threshold */

#define	E1000_DMCTLX 0x02514 /* Time to Lx Request */

#define	E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */

#define	E1000_DMCCNT 0x05DD4 /* Current Rx Count */

#define	E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */

#define	E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */

#define	E1000_PCIEERRSTS 0x05BA8

#define	E1000_PROXYS 0x5F64 /* Proxying Status */

#define	E1000_PROXYFC 0x5F60 /* Proxying Filter Control */

#define	E1000_THMJT 0x08100 /* Junction Temperature */

#define	E1000_THLOWTC 0x08104 /* Low Threshold Control */

#define	E1000_THMIDTC 0x08108 /* Mid Threshold Control */

#define	E1000_THHIGHTC 0x0810C /* High Threshold Control */

#define	E1000_THSTAT 0x08110 /* Thermal Sensor Status */

#define	E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */

#define	E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */

#define	E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/

#define	E1000_EEE_SU 0x0E34 /* EEE Setup */

#define	E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */

#define	E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */

#define	E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */

#define	E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */

#define	E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */

#define	E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */

#define	E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */

Macro Definition Documentation

◆ E1000_AIT

#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */

Definition at line 108 of file e1000_regs.h.

◆ E1000_ALGNERRC

#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */

Definition at line 327 of file e1000_regs.h.

◆ E1000_B2OGPRC

#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */

Definition at line 716 of file e1000_regs.h.

◆ E1000_B2OSPC

#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */

Definition at line 715 of file e1000_regs.h.

◆ E1000_BARCTRL

#define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */

Definition at line 51 of file e1000_regs.h.

◆ E1000_BARCTRL_CSRSIZE

#define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */

Definition at line 53 of file e1000_regs.h.

◆ E1000_BARCTRL_FLSIZE

#define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */

Definition at line 52 of file e1000_regs.h.

◆ E1000_BPRC

#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */

Definition at line 353 of file e1000_regs.h.

◆ E1000_BPTC

#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */

Definition at line 381 of file e1000_regs.h.

◆ E1000_BSCTRH

#define E1000_BSCTRH 0x05DB8 /* Broadcast Storm Control Threshold */

Definition at line 588 of file e1000_regs.h.

◆ E1000_CBRDPC

#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */

Definition at line 477 of file e1000_regs.h.

◆ E1000_CBRMPC

#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */

Definition at line 478 of file e1000_regs.h.

◆ E1000_CBTMPC

#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */

Definition at line 475 of file e1000_regs.h.

◆ E1000_CCMCTL

#define E1000_CCMCTL 0x05B48 /* CCM Control Register */

Definition at line 532 of file e1000_regs.h.

◆ E1000_CEXTERR

#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */

Definition at line 339 of file e1000_regs.h.

◆ E1000_CIAA

#define E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */

Definition at line 501 of file e1000_regs.h.

◆ E1000_CIAD

#define E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */

Definition at line 502 of file e1000_regs.h.

◆ E1000_COLC

#define E1000_COLC 0x04028 /* Collision Count - R/clr */

Definition at line 335 of file e1000_regs.h.

◆ E1000_CONNSW

#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */

Definition at line 77 of file e1000_regs.h.

◆ E1000_CPUVEC

#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */

Definition at line 556 of file e1000_regs.h.

◆ E1000_CRC_OFFSET

#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */

Definition at line 394 of file e1000_regs.h.

◆ E1000_CRCERRS

#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */

Definition at line 326 of file e1000_regs.h.

◆ E1000_CTRL

#define E1000_CTRL 0x00000 /* Device Control - RW */

Definition at line 39 of file e1000_regs.h.

◆ E1000_CTRL_DUP

#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */

Definition at line 40 of file e1000_regs.h.

◆ E1000_CTRL_EXT

#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */

Definition at line 44 of file e1000_regs.h.

◆ E1000_DAQF

#define E1000_DAQF ( _n ) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */

Definition at line 628 of file e1000_regs.h.

◆ E1000_DC

#define E1000_DC 0x04030 /* Defer Count - R/clr */

Definition at line 336 of file e1000_regs.h.

◆ E1000_DCA_CTRL

#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */

Definition at line 549 of file e1000_regs.h.

◆ E1000_DCA_ID

#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */

Definition at line 548 of file e1000_regs.h.

◆ E1000_DCA_RXCTRL

#define E1000_DCA_RXCTRL ( _n ) E1000_RXCTL(_n)

Definition at line 258 of file e1000_regs.h.

◆ E1000_DCA_TXCTRL

#define E1000_DCA_TXCTRL ( _n ) E1000_TXCTL(_n)

Definition at line 275 of file e1000_regs.h.

◆ E1000_DMACR

#define E1000_DMACR 0x02508 /* Control Register */

Definition at line 686 of file e1000_regs.h.

◆ E1000_DMCCNT

#define E1000_DMCCNT 0x05DD4 /* Current Rx Count */

Definition at line 690 of file e1000_regs.h.

◆ E1000_DMCRTRH

#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */

Definition at line 689 of file e1000_regs.h.

◆ E1000_DMCTLX

#define E1000_DMCTLX 0x02514 /* Time to Lx Request */

Definition at line 688 of file e1000_regs.h.

◆ E1000_DMCTXTH

#define E1000_DMCTXTH 0x03550 /* Transmit Threshold */

Definition at line 687 of file e1000_regs.h.

◆ E1000_DOBFFCTL

#define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */

Definition at line 720 of file e1000_regs.h.

◆ E1000_DPGFR

#define E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */

Definition at line 75 of file e1000_regs.h.

◆ E1000_DTXCTL

#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */

Definition at line 317 of file e1000_regs.h.

◆ E1000_DTXMXSZRQ

#define E1000_DTXMXSZRQ 0x03540

Definition at line 321 of file e1000_regs.h.

◆ E1000_DTXSWC

#define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */

Definition at line 576 of file e1000_regs.h.

◆ E1000_DTXTCPFLGH

#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */

Definition at line 319 of file e1000_regs.h.

◆ E1000_DTXTCPFLGL

#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */

Definition at line 318 of file e1000_regs.h.

◆ E1000_DVMOLR

#define E1000_DVMOLR ( _n ) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */

Definition at line 599 of file e1000_regs.h.

◆ E1000_ECOL

#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */

Definition at line 332 of file e1000_regs.h.

◆ E1000_EEARBC

#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */

Definition at line 121 of file e1000_regs.h.

◆ E1000_EEARBC_I210

#define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */

Definition at line 122 of file e1000_regs.h.

◆ E1000_EEC_REG

#define E1000_EEC_REG 0x12010

Definition at line 176 of file e1000_regs.h.

◆ E1000_EECD

#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */

Definition at line 42 of file e1000_regs.h.

◆ E1000_EEE_SU

#define E1000_EEE_SU 0x0E34 /* EEE Setup */

Definition at line 710 of file e1000_regs.h.

◆ E1000_EEER

#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/

Definition at line 709 of file e1000_regs.h.

◆ E1000_EEMNGCTL

#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */

Definition at line 119 of file e1000_regs.h.

◆ E1000_EEMNGCTL_I210

#define E1000_EEMNGCTL_I210 0x01010 /* i210 MNG EEprom Mode Control */

Definition at line 120 of file e1000_regs.h.

◆ E1000_EEPROM_INIT_CTRL_WORD_2

#define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */

Definition at line 49 of file e1000_regs.h.

◆ E1000_EEPROM_PCIE_CTRL_WORD_2

#define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */

Definition at line 50 of file e1000_regs.h.

◆ E1000_EERD

#define E1000_EERD 0x00014 /* EEPROM Read - RW */

Definition at line 43 of file e1000_regs.h.

◆ E1000_EEWR

#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */

Definition at line 124 of file e1000_regs.h.

◆ E1000_EIAC

#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */

Definition at line 99 of file e1000_regs.h.

◆ E1000_EIAM

#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */

Definition at line 100 of file e1000_regs.h.

◆ E1000_EICR

#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */

Definition at line 94 of file e1000_regs.h.

◆ E1000_EICS

#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */

Definition at line 96 of file e1000_regs.h.

◆ E1000_EIMC

#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */

Definition at line 98 of file e1000_regs.h.

◆ E1000_EIMS

#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */

Definition at line 97 of file e1000_regs.h.

◆ E1000_EITR

#define E1000_EITR ( _n ) (0x01680 + (0x4 * (_n)))

Definition at line 95 of file e1000_regs.h.

◆ E1000_EMIADD

#define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */

Definition at line 172 of file e1000_regs.h.

◆ E1000_EMIDATA

#define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */

Definition at line 173 of file e1000_regs.h.

◆ E1000_ERT

#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */

Definition at line 149 of file e1000_regs.h.

◆ E1000_ETQF

#define E1000_ETQF ( _n ) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */

Definition at line 633 of file e1000_regs.h.

◆ E1000_ETQF_ETYPE_MASK

#define E1000_ETQF_ETYPE_MASK 0x0000FFFF

Definition at line 641 of file e1000_regs.h.

◆ E1000_ETQF_FILTER_ENABLE

#define E1000_ETQF_FILTER_ENABLE (1 << 26)

Definition at line 636 of file e1000_regs.h.

◆ E1000_ETQF_IMM_INT

#define E1000_ETQF_IMM_INT (1 << 29)

Definition at line 637 of file e1000_regs.h.

◆ E1000_ETQF_QUEUE_ENABLE

#define E1000_ETQF_QUEUE_ENABLE (1U << 31)

Definition at line 638 of file e1000_regs.h.

◆ E1000_ETQF_QUEUE_MASK

#define E1000_ETQF_QUEUE_MASK 0x00070000

Definition at line 640 of file e1000_regs.h.

◆ E1000_ETQF_QUEUE_SHIFT

#define E1000_ETQF_QUEUE_SHIFT 16

Definition at line 639 of file e1000_regs.h.

◆ E1000_EXTCNF_CTRL

#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */

Definition at line 111 of file e1000_regs.h.

◆ E1000_EXTCNF_SIZE

#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */

Definition at line 112 of file e1000_regs.h.

◆ E1000_FACTPS

#define E1000_FACTPS 0x05B30

Definition at line 543 of file e1000_regs.h.

◆ E1000_FCAH

#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */

Definition at line 62 of file e1000_regs.h.

◆ E1000_FCAL

#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */

Definition at line 61 of file e1000_regs.h.

◆ E1000_FCRTC

#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */

Definition at line 691 of file e1000_regs.h.

◆ E1000_FCRTH

#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */

Definition at line 151 of file e1000_regs.h.

◆ E1000_FCRTL

#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */

Definition at line 150 of file e1000_regs.h.

◆ E1000_FCRTV

#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */

Definition at line 159 of file e1000_regs.h.

◆ E1000_FCRUC

#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */

Definition at line 345 of file e1000_regs.h.

◆ E1000_FCT

#define E1000_FCT 0x00030 /* Flow Control Type - RW */

Definition at line 76 of file e1000_regs.h.

◆ E1000_FCTTV

#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */

Definition at line 90 of file e1000_regs.h.

◆ E1000_FEXT

#define E1000_FEXT 0x0002C /* Future Extended - RW */

Definition at line 63 of file e1000_regs.h.

◆ E1000_FEXTNVM

#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */

Definition at line 64 of file e1000_regs.h.

◆ E1000_FEXTNVM11

#define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */

Definition at line 72 of file e1000_regs.h.

◆ E1000_FEXTNVM12

#define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */

Definition at line 73 of file e1000_regs.h.

◆ E1000_FEXTNVM3

#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */

Definition at line 65 of file e1000_regs.h.

◆ E1000_FEXTNVM4

#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */

Definition at line 66 of file e1000_regs.h.

◆ E1000_FEXTNVM5

#define E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */

Definition at line 67 of file e1000_regs.h.

◆ E1000_FEXTNVM6

#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */

Definition at line 68 of file e1000_regs.h.

◆ E1000_FEXTNVM7

#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */

Definition at line 69 of file e1000_regs.h.

◆ E1000_FEXTNVM8

#define E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */

Definition at line 70 of file e1000_regs.h.

◆ E1000_FEXTNVM9

#define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */

Definition at line 71 of file e1000_regs.h.

◆ E1000_FFLT

#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */

Definition at line 517 of file e1000_regs.h.

◆ E1000_FFLT_DBG

#define E1000_FFLT_DBG 0x05F04 /* Debug Register */

Definition at line 551 of file e1000_regs.h.

◆ E1000_FFLT_REG

#define E1000_FFLT_REG ( _i ) (0x05F00 + ((_i) * 8))

Definition at line 301 of file e1000_regs.h.

◆ E1000_FFMT_REG

#define E1000_FFMT_REG ( _i ) (0x09000 + ((_i) * 8))

Definition at line 299 of file e1000_regs.h.

◆ E1000_FFVT_REG

#define E1000_FFVT_REG ( _i ) (0x09800 + ((_i) * 8))

Definition at line 300 of file e1000_regs.h.

◆ E1000_FHFT

#define E1000_FHFT ( _n ) (0x09000 + ((_n) * 0x100))

Definition at line 521 of file e1000_regs.h.

◆ E1000_FHFT_EXT

#define E1000_FHFT_EXT ( _n ) (0x09A00 + ((_n) * 0x100))

Definition at line 523 of file e1000_regs.h.

◆ E1000_FLA

#define E1000_FLA 0x0001C /* Flash Access - RW */

Definition at line 45 of file e1000_regs.h.

◆ E1000_FLASHT

#define E1000_FLASHT 0x01028 /* FLASH Timer Register */

Definition at line 123 of file e1000_regs.h.

◆ E1000_FLFWUPDATE

#define E1000_FLFWUPDATE 0x12108

Definition at line 189 of file e1000_regs.h.

◆ E1000_FLOP

#define E1000_FLOP 0x0103C /* FLASH Opcode Register */

Definition at line 128 of file e1000_regs.h.

◆ E1000_FLSWCNT

#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */

Definition at line 127 of file e1000_regs.h.

◆ E1000_FLSWCTL

#define E1000_FLSWCTL 0x01030 /* FLASH control register */

Definition at line 125 of file e1000_regs.h.

◆ E1000_FLSWDATA

#define E1000_FLSWDATA 0x01034 /* FLASH data register */

Definition at line 126 of file e1000_regs.h.

◆ E1000_FRTIMER

#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */

Definition at line 141 of file e1000_regs.h.

◆ E1000_FTQF

#define E1000_FTQF ( _n ) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */

Definition at line 630 of file e1000_regs.h.

◆ E1000_FWSM

#define E1000_FWSM 0x05B54 /* FW Semaphore */

Definition at line 545 of file e1000_regs.h.

◆ E1000_FWSTS

#define E1000_FWSTS 0x08F0C /* FW Status */

Definition at line 553 of file e1000_regs.h.

◆ E1000_GCR

#define E1000_GCR 0x05B00 /* PCI-Ex Control */

Definition at line 536 of file e1000_regs.h.

◆ E1000_GCR2

#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */

Definition at line 537 of file e1000_regs.h.

◆ E1000_GIOCTL

#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */

Definition at line 533 of file e1000_regs.h.

◆ E1000_GORCH

#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */

Definition at line 357 of file e1000_regs.h.

◆ E1000_GORCL

#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */

Definition at line 356 of file e1000_regs.h.

◆ E1000_GOTCH

#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */

Definition at line 359 of file e1000_regs.h.

◆ E1000_GOTCL

#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */

Definition at line 358 of file e1000_regs.h.

◆ E1000_GPIE

#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */

Definition at line 101 of file e1000_regs.h.

◆ E1000_GPRC

#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */

Definition at line 352 of file e1000_regs.h.

◆ E1000_GPTC

#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */

Definition at line 355 of file e1000_regs.h.

◆ E1000_GSCL_1

#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */

Definition at line 538 of file e1000_regs.h.

◆ E1000_GSCL_2

#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */

Definition at line 539 of file e1000_regs.h.

◆ E1000_GSCL_3

#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */

Definition at line 540 of file e1000_regs.h.

◆ E1000_GSCL_4

#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */

Definition at line 541 of file e1000_regs.h.

◆ E1000_HGORCH

#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */

Definition at line 483 of file e1000_regs.h.

◆ E1000_HGORCL

#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */

Definition at line 482 of file e1000_regs.h.

◆ E1000_HGOTCH

#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */

Definition at line 485 of file e1000_regs.h.

◆ E1000_HGOTCL

#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */

Definition at line 484 of file e1000_regs.h.

◆ E1000_HGPTC

#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */

Definition at line 480 of file e1000_regs.h.

◆ E1000_HIBBA

#define E1000_HIBBA 0x8F40 /* Host Interface Buffer Base Address */

Definition at line 519 of file e1000_regs.h.

◆ E1000_HICR

#define E1000_HICR 0x08F00 /* Host Interface Control */

Definition at line 552 of file e1000_regs.h.

◆ E1000_HOST_IF

#define E1000_HOST_IF 0x08800 /* Host Interface */

Definition at line 518 of file e1000_regs.h.

◆ E1000_HRMPC

#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */

Definition at line 488 of file e1000_regs.h.

◆ E1000_HTCBDPC

#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */

Definition at line 481 of file e1000_regs.h.

◆ E1000_HTDPMC

#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */

Definition at line 476 of file e1000_regs.h.

◆ E1000_I210_FLA

#define E1000_I210_FLA 0x1201C

Definition at line 186 of file e1000_regs.h.

◆ E1000_I210_FLMNGCNT

#define E1000_I210_FLMNGCNT 0x12040

Definition at line 180 of file e1000_regs.h.

◆ E1000_I210_FLMNGCTL

#define E1000_I210_FLMNGCTL 0x12038

Definition at line 178 of file e1000_regs.h.

◆ E1000_I210_FLMNGDATA

#define E1000_I210_FLMNGDATA 0x1203C

Definition at line 179 of file e1000_regs.h.

◆ E1000_I210_FLSWCNT

#define E1000_I210_FLSWCNT 0x12050

Definition at line 184 of file e1000_regs.h.

◆ E1000_I210_FLSWCTL

#define E1000_I210_FLSWCTL 0x12048

Definition at line 182 of file e1000_regs.h.

◆ E1000_I210_FLSWDATA

#define E1000_I210_FLSWDATA 0x1204C

Definition at line 183 of file e1000_regs.h.

◆ E1000_I210_TQAVARBCTRL

#define E1000_I210_TQAVARBCTRL 0x3574

Definition at line 219 of file e1000_regs.h.

◆ E1000_I210_TQAVCC

#define E1000_I210_TQAVCC ( _n ) (0x3004 + 0x40 * (_n))

Definition at line 223 of file e1000_regs.h.

◆ E1000_I210_TQAVCTRL

#define E1000_I210_TQAVCTRL 0x3570

Definition at line 195 of file e1000_regs.h.

◆ E1000_I210_TQAVHC

#define E1000_I210_TQAVHC ( _n ) (0x300C + 0x40 * (_n))

Definition at line 216 of file e1000_regs.h.

◆ E1000_I210_TXPBS_SIZE

#define E1000_I210_TXPBS_SIZE	(	_n,
		_s
	)	((_s) << (6 * (_n)))

Definition at line 234 of file e1000_regs.h.

◆ E1000_I2C_CLK_IN

#define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */

Definition at line 137 of file e1000_regs.h.

◆ E1000_I2C_CLK_OE_N

#define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */

Definition at line 136 of file e1000_regs.h.

◆ E1000_I2C_CLK_OUT

#define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */

Definition at line 132 of file e1000_regs.h.

◆ E1000_I2C_CLK_STRETCH_DIS

#define E1000_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */

Definition at line 138 of file e1000_regs.h.

◆ E1000_I2C_DATA_IN

#define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */

Definition at line 135 of file e1000_regs.h.

◆ E1000_I2C_DATA_OE_N

#define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */

Definition at line 134 of file e1000_regs.h.

◆ E1000_I2C_DATA_OUT

#define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */

Definition at line 133 of file e1000_regs.h.

◆ E1000_I2CBB_EN

#define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */

Definition at line 131 of file e1000_regs.h.

◆ E1000_I2CCMD

#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */

Definition at line 129 of file e1000_regs.h.

◆ E1000_I2CPARAMS

#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */

Definition at line 130 of file e1000_regs.h.

◆ E1000_I350_BARCTRL

#define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */

Definition at line 58 of file e1000_regs.h.

◆ E1000_I350_DTXMXPKTSZ

#define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/

Definition at line 59 of file e1000_regs.h.

◆ E1000_IAC

#define E1000_IAC 0x04100 /* Interrupt Assertion Count */

Definition at line 384 of file e1000_regs.h.

◆ E1000_IAM

#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */

Definition at line 84 of file e1000_regs.h.

◆ E1000_IAM_V2

#define E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */

Definition at line 148 of file e1000_regs.h.

◆ E1000_ICR

#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */

Definition at line 79 of file e1000_regs.h.

◆ E1000_ICR_V2

#define E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */

Definition at line 144 of file e1000_regs.h.

◆ E1000_ICRXATC

#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */

Definition at line 387 of file e1000_regs.h.

◆ E1000_ICRXDMTC

#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */

Definition at line 392 of file e1000_regs.h.

◆ E1000_ICRXOC

#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */

Definition at line 393 of file e1000_regs.h.

◆ E1000_ICRXPTC

#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */

Definition at line 386 of file e1000_regs.h.

◆ E1000_ICS

#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */

Definition at line 81 of file e1000_regs.h.

◆ E1000_ICS_V2

#define E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */

Definition at line 145 of file e1000_regs.h.

◆ E1000_ICTXATC

#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */

Definition at line 389 of file e1000_regs.h.

◆ E1000_ICTXPTC

#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */

Definition at line 388 of file e1000_regs.h.

◆ E1000_ICTXQEC

#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */

Definition at line 390 of file e1000_regs.h.

◆ E1000_ICTXQMTC

#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */

Definition at line 391 of file e1000_regs.h.

◆ E1000_IMC

#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */

Definition at line 83 of file e1000_regs.h.

◆ E1000_IMC_V2

#define E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */

Definition at line 147 of file e1000_regs.h.

◆ E1000_IMIR

#define E1000_IMIR ( _i ) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */

Definition at line 558 of file e1000_regs.h.

◆ E1000_IMIREXT

#define E1000_IMIREXT ( _i ) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/

Definition at line 559 of file e1000_regs.h.

◆ E1000_IMIRVP

#define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */

Definition at line 560 of file e1000_regs.h.

◆ E1000_IMS

#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */

Definition at line 82 of file e1000_regs.h.

◆ E1000_IMS_V2

#define E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */

Definition at line 146 of file e1000_regs.h.

◆ E1000_INVM_DATA_REG

#define E1000_INVM_DATA_REG ( _n ) (0x12120 + 4*(_n))

Definition at line 191 of file e1000_regs.h.

◆ E1000_INVM_SIZE

#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */

Definition at line 192 of file e1000_regs.h.

◆ E1000_IOSFPC

#define E1000_IOSFPC 0x00F28 /* TX corrupted data */

Definition at line 118 of file e1000_regs.h.

◆ E1000_IOVCTL

#define E1000_IOVCTL 0x05BBC /* IOV Control Register */

Definition at line 580 of file e1000_regs.h.

◆ E1000_IP4AT

#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */

Definition at line 511 of file e1000_regs.h.

◆ E1000_IP4AT_REG

#define E1000_IP4AT_REG ( _i ) (0x05840 + ((_i) * 8))

Definition at line 296 of file e1000_regs.h.

◆ E1000_IP6AT

#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */

Definition at line 512 of file e1000_regs.h.

◆ E1000_IP6AT_REG

#define E1000_IP6AT_REG ( _i ) (0x05880 + ((_i) * 4))

Definition at line 297 of file e1000_regs.h.

◆ E1000_IPAV

#define E1000_IPAV 0x05838 /* IP Address Valid - RW */

Definition at line 510 of file e1000_regs.h.

◆ E1000_IPCNFG

#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */

Definition at line 707 of file e1000_regs.h.

◆ E1000_IPSCTRL

#define E1000_IPSCTRL 0xB430 /* IpSec Control Register */

Definition at line 459 of file e1000_regs.h.

◆ E1000_IPSRXCMD

#define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */

Definition at line 460 of file e1000_regs.h.

◆ E1000_IPSRXIDX

#define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */

Definition at line 461 of file e1000_regs.h.

◆ E1000_IPSRXIPADDR

#define E1000_IPSRXIPADDR ( _n ) (0x0B420 + (0x04 * (_n)))

Definition at line 463 of file e1000_regs.h.

◆ E1000_IPSRXKEY

#define E1000_IPSRXKEY ( _n ) (0x0B410 + (0x04 * (_n)))

Definition at line 465 of file e1000_regs.h.

◆ E1000_IPSRXSALT

#define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */

Definition at line 466 of file e1000_regs.h.

◆ E1000_IPSRXSPI

#define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */

Definition at line 467 of file e1000_regs.h.

◆ E1000_IPSTXIDX

#define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */

Definition at line 471 of file e1000_regs.h.

◆ E1000_IPSTXKEY

#define E1000_IPSTXKEY ( _n ) (0x0B460 + (0x04 * (_n)))

Definition at line 469 of file e1000_regs.h.

◆ E1000_IPSTXSALT

#define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */

Definition at line 470 of file e1000_regs.h.

◆ E1000_IRPBS

#define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */

Definition at line 168 of file e1000_regs.h.

◆ E1000_ITPBS

#define E1000_ITPBS 0x03404

Definition at line 306 of file e1000_regs.h.

◆ E1000_ITR

#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */

Definition at line 80 of file e1000_regs.h.

◆ E1000_IVAR

#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */

Definition at line 85 of file e1000_regs.h.

◆ E1000_IVAR0

#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */

Definition at line 102 of file e1000_regs.h.

◆ E1000_IVAR_MISC

#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */

Definition at line 103 of file e1000_regs.h.

◆ E1000_KABGTXD

#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */

Definition at line 288 of file e1000_regs.h.

◆ E1000_KMRNCTRLSTA

#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */

Definition at line 526 of file e1000_regs.h.

◆ E1000_LATECOL

#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */

Definition at line 334 of file e1000_regs.h.

◆ E1000_LEDCTL

#define E1000_LEDCTL 0x00E00 /* LED Control - RW */

Definition at line 109 of file e1000_regs.h.

◆ E1000_LEDMUX

#define E1000_LEDMUX 0x08130 /* LED MUX Control */

Definition at line 110 of file e1000_regs.h.

◆ E1000_LENERRS

#define E1000_LENERRS 0x04138 /* Length Errors Count */

Definition at line 486 of file e1000_regs.h.

◆ E1000_LPIC

#define E1000_LPIC 0x000FC /* Low Power IDLE control */

Definition at line 88 of file e1000_regs.h.

◆ E1000_LSECRXBAD

#define E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */

Definition at line 425 of file e1000_regs.h.

◆ E1000_LSECRXCAP

#define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */

Definition at line 437 of file e1000_regs.h.

◆ E1000_LSECRXCTRL

#define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */

Definition at line 439 of file e1000_regs.h.

◆ E1000_LSECRXDELAY

#define E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */

Definition at line 429 of file e1000_regs.h.

◆ E1000_LSECRXINV

#define E1000_LSECRXINV ( _n ) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */

Definition at line 432 of file e1000_regs.h.

◆ E1000_LSECRXKEY

#define E1000_LSECRXKEY	(	_n,
		_m
	)	(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))

Definition at line 456 of file e1000_regs.h.

◆ E1000_LSECRXLATE

#define E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */

Definition at line 430 of file e1000_regs.h.

◆ E1000_LSECRXNOSCI

#define E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */

Definition at line 426 of file e1000_regs.h.

◆ E1000_LSECRXNUSA

#define E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */

Definition at line 435 of file e1000_regs.h.

◆ E1000_LSECRXNV

#define E1000_LSECRXNV ( _n ) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */

Definition at line 433 of file e1000_regs.h.

◆ E1000_LSECRXOCTD

#define E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */

Definition at line 423 of file e1000_regs.h.

◆ E1000_LSECRXOCTV

#define E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */

Definition at line 424 of file e1000_regs.h.

◆ E1000_LSECRXOK

#define E1000_LSECRXOK ( _n ) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */

Definition at line 431 of file e1000_regs.h.

◆ E1000_LSECRXPN

#define E1000_LSECRXPN ( _n ) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */

Definition at line 452 of file e1000_regs.h.

◆ E1000_LSECRXSA

#define E1000_LSECRXSA ( _n ) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */

Definition at line 451 of file e1000_regs.h.

◆ E1000_LSECRXSCH

#define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */

Definition at line 446 of file e1000_regs.h.

◆ E1000_LSECRXSCL

#define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */

Definition at line 445 of file e1000_regs.h.

◆ E1000_LSECRXUNCH

#define E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */

Definition at line 428 of file e1000_regs.h.

◆ E1000_LSECRXUNSA

#define E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */

Definition at line 434 of file e1000_regs.h.

◆ E1000_LSECRXUNSCI

#define E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */

Definition at line 427 of file e1000_regs.h.

◆ E1000_LSECRXUT

#define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */

Definition at line 422 of file e1000_regs.h.

◆ E1000_LSECTXCAP

#define E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */

Definition at line 436 of file e1000_regs.h.

◆ E1000_LSECTXCTRL

#define E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */

Definition at line 438 of file e1000_regs.h.

◆ E1000_LSECTXKEY0

#define E1000_LSECTXKEY0 ( _n ) (0x0B020 + (0x04 * (_n)))

Definition at line 448 of file e1000_regs.h.

◆ E1000_LSECTXKEY1

#define E1000_LSECTXKEY1 ( _n ) (0x0B030 + (0x04 * (_n)))

Definition at line 450 of file e1000_regs.h.

◆ E1000_LSECTXOCTE

#define E1000_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */

Definition at line 420 of file e1000_regs.h.

◆ E1000_LSECTXOCTP

#define E1000_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */

Definition at line 421 of file e1000_regs.h.

◆ E1000_LSECTXPKTE

#define E1000_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */

Definition at line 418 of file e1000_regs.h.

◆ E1000_LSECTXPKTP

#define E1000_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */

Definition at line 419 of file e1000_regs.h.

◆ E1000_LSECTXPN0

#define E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */

Definition at line 443 of file e1000_regs.h.

◆ E1000_LSECTXPN1

#define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */

Definition at line 444 of file e1000_regs.h.

◆ E1000_LSECTXSA

#define E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */

Definition at line 442 of file e1000_regs.h.

◆ E1000_LSECTXSCH

#define E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */

Definition at line 441 of file e1000_regs.h.

◆ E1000_LSECTXSCL

#define E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */

Definition at line 440 of file e1000_regs.h.

◆ E1000_LSECTXUT

#define E1000_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */

Definition at line 417 of file e1000_regs.h.

◆ E1000_LTRC

#define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */

Definition at line 708 of file e1000_regs.h.

◆ E1000_LVMMC

#define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */

Definition at line 585 of file e1000_regs.h.

◆ E1000_MANC

#define E1000_MANC 0x05820 /* Management Control - RW */

Definition at line 509 of file e1000_regs.h.

◆ E1000_MANC2H

#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */

Definition at line 527 of file e1000_regs.h.

◆ E1000_MBVFICR

#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */

Definition at line 570 of file e1000_regs.h.

◆ E1000_MBVFIMR

#define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */

Definition at line 571 of file e1000_regs.h.

◆ E1000_MCC

#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */

Definition at line 333 of file e1000_regs.h.

◆ E1000_MDEF

#define E1000_MDEF ( _n ) (0x05890 + (4 * (_n)))

Definition at line 529 of file e1000_regs.h.

◆ E1000_MDFB

#define E1000_MDFB 0x03558 /* Malicious Driver free block */

Definition at line 584 of file e1000_regs.h.

◆ E1000_MDIC

#define E1000_MDIC 0x00020 /* MDI Control - RW */

Definition at line 46 of file e1000_regs.h.

◆ E1000_MDICNFG

#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */

Definition at line 47 of file e1000_regs.h.

◆ E1000_MGTPDC

#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */

Definition at line 366 of file e1000_regs.h.

◆ E1000_MGTPRC

#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */

Definition at line 365 of file e1000_regs.h.

◆ E1000_MGTPTC

#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */

Definition at line 367 of file e1000_regs.h.

◆ E1000_MMDAAD

#define E1000_MMDAAD 14 /* MMD Access Address/Data */

Definition at line 237 of file e1000_regs.h.

◆ E1000_MMDAC

#define E1000_MMDAC 13 /* MMD Access Control */

Definition at line 236 of file e1000_regs.h.

◆ E1000_MPC

#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */

Definition at line 330 of file e1000_regs.h.

◆ E1000_MPHY_ADDR_CTRL

#define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */

Definition at line 54 of file e1000_regs.h.

◆ E1000_MPHY_DATA

#define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */

Definition at line 55 of file e1000_regs.h.

◆ E1000_MPHY_STAT

#define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */

Definition at line 56 of file e1000_regs.h.

◆ E1000_MPRC

#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */

Definition at line 354 of file e1000_regs.h.

◆ E1000_MPTC

#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */

Definition at line 380 of file e1000_regs.h.

◆ E1000_MRQC

#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */

Definition at line 557 of file e1000_regs.h.

◆ E1000_MSCTRH

#define E1000_MSCTRH 0x05DBC /* Multicast Storm Control Threshold */

Definition at line 589 of file e1000_regs.h.

◆ E1000_MSIXBM

#define E1000_MSIXBM ( _i ) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */

Definition at line 561 of file e1000_regs.h.

◆ E1000_MTA

#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */

Definition at line 496 of file e1000_regs.h.

◆ E1000_O2BGPTC

#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */

Definition at line 717 of file e1000_regs.h.

◆ E1000_O2BSPC

#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */

Definition at line 718 of file e1000_regs.h.

◆ E1000_P2VMAILBOX

#define E1000_P2VMAILBOX ( _n ) (0x00C00 + (4 * (_n)))

Definition at line 592 of file e1000_regs.h.

◆ E1000_PBA

#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */

Definition at line 115 of file e1000_regs.h.

◆ E1000_PBA_ECC

#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */

Definition at line 93 of file e1000_regs.h.

◆ E1000_PBACL

#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */

Definition at line 516 of file e1000_regs.h.

◆ E1000_PBDIAG

#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */

Definition at line 166 of file e1000_regs.h.

◆ E1000_PBECCSTS

#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */

Definition at line 117 of file e1000_regs.h.

◆ E1000_PBRTH

#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */

Definition at line 158 of file e1000_regs.h.

◆ E1000_PBRWAC

#define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */

Definition at line 169 of file e1000_regs.h.

◆ E1000_PBS

#define E1000_PBS 0x01008 /* Packet Buffer Size */

Definition at line 116 of file e1000_regs.h.

◆ E1000_PBSLAC

#define E1000_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */

Definition at line 302 of file e1000_regs.h.

◆ E1000_PBSLAD

#define E1000_PBSLAD ( _n ) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */

Definition at line 303 of file e1000_regs.h.

◆ E1000_PCIEANACFG

#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */

Definition at line 74 of file e1000_regs.h.

◆ E1000_PCIEERRSTS

#define E1000_PCIEERRSTS 0x05BA8

Definition at line 695 of file e1000_regs.h.

◆ E1000_PCIEMISC

#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */

Definition at line 692 of file e1000_regs.h.

◆ E1000_PCS_ANADV

#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */

Definition at line 489 of file e1000_regs.h.

◆ E1000_PCS_CFG0

#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */

Definition at line 472 of file e1000_regs.h.

◆ E1000_PCS_LCTL

#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */

Definition at line 473 of file e1000_regs.h.

◆ E1000_PCS_LPAB

#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */

Definition at line 490 of file e1000_regs.h.

◆ E1000_PCS_LPABNP

#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */

Definition at line 492 of file e1000_regs.h.

◆ E1000_PCS_LSTAT

#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */

Definition at line 474 of file e1000_regs.h.

◆ E1000_PCS_NPTX

#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */

Definition at line 491 of file e1000_regs.h.

◆ E1000_PFCTOP

#define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */

Definition at line 680 of file e1000_regs.h.

◆ E1000_PFVFGORC

#define E1000_PFVFGORC ( _n ) (0x010018 + (0x100 * (_n)))

Definition at line 408 of file e1000_regs.h.

◆ E1000_PFVFGORLBC

#define E1000_PFVFGORLBC ( _n ) (0x010048 + (0x100 * (_n)))

Definition at line 413 of file e1000_regs.h.

◆ E1000_PFVFGOTC

#define E1000_PFVFGOTC ( _n ) (0x010034 + (0x100 * (_n)))

Definition at line 409 of file e1000_regs.h.

◆ E1000_PFVFGOTLBC

#define E1000_PFVFGOTLBC ( _n ) (0x010050 + (0x100 * (_n)))

Definition at line 414 of file e1000_regs.h.

◆ E1000_PFVFGPRC

#define E1000_PFVFGPRC ( _n ) (0x010010 + (0x100 * (_n)))

Definition at line 406 of file e1000_regs.h.

◆ E1000_PFVFGPRLBC

#define E1000_PFVFGPRLBC ( _n ) (0x010040 + (0x100 * (_n)))

Definition at line 411 of file e1000_regs.h.

◆ E1000_PFVFGPTC

#define E1000_PFVFGPTC ( _n ) (0x010014 + (0x100 * (_n)))

Definition at line 407 of file e1000_regs.h.

◆ E1000_PFVFGPTLBC

#define E1000_PFVFGPTLBC ( _n ) (0x010044 + (0x100 * (_n)))

Definition at line 412 of file e1000_regs.h.

◆ E1000_PFVFMPRC

#define E1000_PFVFMPRC ( _n ) (0x010038 + (0x100 * (_n)))

Definition at line 410 of file e1000_regs.h.

◆ E1000_PHY_CTRL

#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */

Definition at line 113 of file e1000_regs.h.

◆ E1000_PLTSTMPH

#define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */

Definition at line 619 of file e1000_regs.h.

◆ E1000_PLTSTMPL

#define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */

Definition at line 618 of file e1000_regs.h.

◆ E1000_POEMB

#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */

Definition at line 114 of file e1000_regs.h.

◆ E1000_PPHY_CTRL

#define E1000_PPHY_CTRL 0x5b48 /* PCIe PHY Control */

Definition at line 57 of file e1000_regs.h.

◆ E1000_PQGPTC

#define E1000_PQGPTC ( _n ) (0x010014 + (0x100 * (_n)))

Definition at line 231 of file e1000_regs.h.

◆ E1000_PRC1023

#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */

Definition at line 350 of file e1000_regs.h.

◆ E1000_PRC127

#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */

Definition at line 347 of file e1000_regs.h.

◆ E1000_PRC1522

#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */

Definition at line 351 of file e1000_regs.h.

◆ E1000_PRC255

#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */

Definition at line 348 of file e1000_regs.h.

◆ E1000_PRC511

#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */

Definition at line 349 of file e1000_regs.h.

◆ E1000_PRC64

#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */

Definition at line 346 of file e1000_regs.h.

◆ E1000_PROXYFC

#define E1000_PROXYFC 0x5F60 /* Proxying Filter Control */

Definition at line 698 of file e1000_regs.h.

◆ E1000_PROXYS

#define E1000_PROXYS 0x5F64 /* Proxying Status */

Definition at line 697 of file e1000_regs.h.

◆ E1000_PSRCTL

#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */

Definition at line 152 of file e1000_regs.h.

◆ E1000_PSRTYPE

#define E1000_PSRTYPE ( _i ) (0x05480 + ((_i) * 4))

Definition at line 289 of file e1000_regs.h.

◆ E1000_PTC1023

#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */

Definition at line 378 of file e1000_regs.h.

◆ E1000_PTC127

#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */

Definition at line 375 of file e1000_regs.h.

◆ E1000_PTC1522

#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */

Definition at line 379 of file e1000_regs.h.

◆ E1000_PTC255

#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */

Definition at line 376 of file e1000_regs.h.

◆ E1000_PTC511

#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */

Definition at line 377 of file e1000_regs.h.

◆ E1000_PTC64

#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */

Definition at line 374 of file e1000_regs.h.

◆ E1000_QDE

#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */

Definition at line 575 of file e1000_regs.h.

◆ E1000_RA

#define E1000_RA 0x05400 /* Receive Address - RW Array */

Definition at line 497 of file e1000_regs.h.

◆ E1000_RA2

#define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */

Definition at line 498 of file e1000_regs.h.

◆ E1000_RADV

#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */

Definition at line 171 of file e1000_regs.h.

◆ E1000_RAH

#define E1000_RAH ( _i )

Value:

(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \

(0x054E4 + ((_i - 16) * 8)))

Definition at line 292 of file e1000_regs.h.

◆ E1000_RAID

#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */

Definition at line 286 of file e1000_regs.h.

◆ E1000_RAL

#define E1000_RAL ( _i )

Value:

(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \

(0x054E0 + ((_i - 16) * 8)))

Definition at line 290 of file e1000_regs.h.

◆ E1000_RCTL

#define E1000_RCTL 0x00100 /* Rx Control - RW */

Definition at line 89 of file e1000_regs.h.

◆ E1000_RDBAH

#define E1000_RDBAH ( _n )

Value:

((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \

(0x0C004 + ((_n) * 0x40)))

Definition at line 248 of file e1000_regs.h.

◆ E1000_RDBAL

#define E1000_RDBAL ( _n )

Value:

((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \

(0x0C000 + ((_n) * 0x40)))

Definition at line 246 of file e1000_regs.h.

◆ E1000_RDFH

#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */

Definition at line 153 of file e1000_regs.h.

◆ E1000_RDFHS

#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */

Definition at line 155 of file e1000_regs.h.

◆ E1000_RDFPC

#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */

Definition at line 157 of file e1000_regs.h.

◆ E1000_RDFT

#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */

Definition at line 154 of file e1000_regs.h.

◆ E1000_RDFTS

#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */

Definition at line 156 of file e1000_regs.h.

◆ E1000_RDH

#define E1000_RDH ( _n )

Value:

((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \

(0x0C010 + ((_n) * 0x40)))

Definition at line 254 of file e1000_regs.h.

◆ E1000_RDLEN

#define E1000_RDLEN ( _n )

Value:

((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \

(0x0C008 + ((_n) * 0x40)))

Definition at line 250 of file e1000_regs.h.

◆ E1000_RDPUAD

#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */

Definition at line 162 of file e1000_regs.h.

◆ E1000_RDPUCTL

#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */

Definition at line 165 of file e1000_regs.h.

◆ E1000_RDPUMB

#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */

Definition at line 161 of file e1000_regs.h.

◆ E1000_RDPURD

#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */

Definition at line 164 of file e1000_regs.h.

◆ E1000_RDPUWD

#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */

Definition at line 163 of file e1000_regs.h.

◆ E1000_RDT

#define E1000_RDT ( _n )

Value:

((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \

(0x0C018 + ((_n) * 0x40)))

Definition at line 259 of file e1000_regs.h.

◆ E1000_RDTR

#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */

Definition at line 170 of file e1000_regs.h.

◆ E1000_REGISTER_SET_SIZE

#define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */

Definition at line 48 of file e1000_regs.h.

◆ E1000_RETA

#define E1000_RETA ( _i ) (0x05C00 + ((_i) * 4))

Definition at line 563 of file e1000_regs.h.

◆ E1000_RFC

#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */

Definition at line 362 of file e1000_regs.h.

◆ E1000_RFCTL

#define E1000_RFCTL 0x05008 /* Receive Filter Control*/

Definition at line 495 of file e1000_regs.h.

◆ E1000_RJC

#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */

Definition at line 364 of file e1000_regs.h.

◆ E1000_RLEC

#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */

Definition at line 340 of file e1000_regs.h.

◆ E1000_RLPIC

#define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */

Definition at line 712 of file e1000_regs.h.

◆ E1000_RLPML

#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */

Definition at line 494 of file e1000_regs.h.

◆ E1000_RNBC

#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */

Definition at line 360 of file e1000_regs.h.

◆ E1000_ROC

#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */

Definition at line 363 of file e1000_regs.h.

◆ E1000_RPLOLR

#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */

Definition at line 578 of file e1000_regs.h.

◆ E1000_RPTHC

#define E1000_RPTHC 0x04104 /* Rx Packets To Host */

Definition at line 479 of file e1000_regs.h.

◆ E1000_RQDPC

#define E1000_RQDPC ( _n )

Value:

((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \

(0x0C030 + ((_n) * 0x40)))

Definition at line 263 of file e1000_regs.h.

◆ E1000_RSRPD

#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */

Definition at line 285 of file e1000_regs.h.

◆ E1000_RSSIM

#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */

Definition at line 566 of file e1000_regs.h.

◆ E1000_RSSIR

#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */

Definition at line 567 of file e1000_regs.h.

◆ E1000_RSSRK

#define E1000_RSSRK ( _i ) (0x05C80 + ((_i) * 4))

Definition at line 565 of file e1000_regs.h.

◆ E1000_RTRBCNCR

#define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */

Definition at line 678 of file e1000_regs.h.

◆ E1000_RTRPCS

#define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */

Definition at line 645 of file e1000_regs.h.

◆ E1000_RTRPTCRC

#define E1000_RTRPTCRC ( _n ) (0x2480 + ((_n) * 4))

Definition at line 653 of file e1000_regs.h.

◆ E1000_RTRPTCRM

#define E1000_RTRPTCRM ( _n ) (0x24C0 + ((_n) * 4))

Definition at line 665 of file e1000_regs.h.

◆ E1000_RTRPTCRS

#define E1000_RTRPTCRS ( _n ) (0x24A0 + ((_n) * 4))

Definition at line 663 of file e1000_regs.h.

◆ E1000_RTRUP2TC

#define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */

Definition at line 646 of file e1000_regs.h.

◆ E1000_RTTBCNACH

#define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */

Definition at line 682 of file e1000_regs.h.

◆ E1000_RTTBCNACL

#define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */

Definition at line 683 of file e1000_regs.h.

◆ E1000_RTTBCNCP

#define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */

Definition at line 677 of file e1000_regs.h.

◆ E1000_RTTBCNCR

#define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */

Definition at line 675 of file e1000_regs.h.

◆ E1000_RTTBCNIDX

#define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */

Definition at line 681 of file e1000_regs.h.

◆ E1000_RTTBCNRC

#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */

Definition at line 673 of file e1000_regs.h.

◆ E1000_RTTBCNRD

#define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */

Definition at line 679 of file e1000_regs.h.

◆ E1000_RTTBCNRM

#define E1000_RTTBCNRM ( _n ) (0x3690 + ((_n) * 4))

Definition at line 669 of file e1000_regs.h.

◆ E1000_RTTBCNRS

#define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */

Definition at line 674 of file e1000_regs.h.

◆ E1000_RTTBCNTG

#define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */

Definition at line 676 of file e1000_regs.h.

◆ E1000_RTTDCS

#define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */

Definition at line 643 of file e1000_regs.h.

◆ E1000_RTTDQSEL

#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */

Definition at line 670 of file e1000_regs.h.

◆ E1000_RTTDTCRC

#define E1000_RTTDTCRC ( _n ) (0x3610 + ((_n) * 4))

Definition at line 649 of file e1000_regs.h.

◆ E1000_RTTDTCRM

#define E1000_RTTDTCRM ( _n ) (0x3650 + ((_n) * 4))

Definition at line 657 of file e1000_regs.h.

◆ E1000_RTTDTCRS

#define E1000_RTTDTCRS ( _n ) (0x3630 + ((_n) * 4))

Definition at line 655 of file e1000_regs.h.

◆ E1000_RTTDVMRC

#define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */

Definition at line 671 of file e1000_regs.h.

◆ E1000_RTTDVMRM

#define E1000_RTTDVMRM ( _n ) (0x3670 + ((_n) * 4))

Definition at line 667 of file e1000_regs.h.

◆ E1000_RTTDVMRS

#define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */

Definition at line 672 of file e1000_regs.h.

◆ E1000_RTTPCS

#define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */

Definition at line 644 of file e1000_regs.h.

◆ E1000_RTTPTCRC

#define E1000_RTTPTCRC ( _n ) (0x3480 + ((_n) * 4))

Definition at line 651 of file e1000_regs.h.

◆ E1000_RTTPTCRM

#define E1000_RTTPTCRM ( _n ) (0x34C0 + ((_n) * 4))

Definition at line 661 of file e1000_regs.h.

◆ E1000_RTTPTCRS

#define E1000_RTTPTCRS ( _n ) (0x34A0 + ((_n) * 4))

Definition at line 659 of file e1000_regs.h.

◆ E1000_RTTUP2TC

#define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */

Definition at line 647 of file e1000_regs.h.

◆ E1000_RUC

#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */

Definition at line 361 of file e1000_regs.h.

◆ E1000_RXCSUM

#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */

Definition at line 493 of file e1000_regs.h.

◆ E1000_RXCTL

#define E1000_RXCTL ( _n )

Value:

((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \

(0x0C014 + ((_n) * 0x40)))

Definition at line 256 of file e1000_regs.h.

◆ E1000_RXCW

#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */

Definition at line 92 of file e1000_regs.h.

◆ E1000_RXDCTL

#define E1000_RXDCTL ( _n )

Value:

((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \

(0x0C028 + ((_n) * 0x40)))

Definition at line 261 of file e1000_regs.h.

◆ E1000_RXERRC

#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */

Definition at line 329 of file e1000_regs.h.

◆ E1000_RXMTRL

#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */

Definition at line 623 of file e1000_regs.h.

◆ E1000_RXPBS

#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */

Definition at line 167 of file e1000_regs.h.

◆ E1000_RXSATRH

#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */

Definition at line 607 of file e1000_regs.h.

◆ E1000_RXSATRL

#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */

Definition at line 606 of file e1000_regs.h.

◆ E1000_RXSTMPH

#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */

Definition at line 605 of file e1000_regs.h.

◆ E1000_RXSTMPL

#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */

Definition at line 604 of file e1000_regs.h.

◆ E1000_RXUDP

#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */

Definition at line 624 of file e1000_regs.h.

◆ E1000_SAQF

#define E1000_SAQF ( _n ) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */

Definition at line 627 of file e1000_regs.h.

◆ E1000_SCC

#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */

Definition at line 331 of file e1000_regs.h.

◆ E1000_SCCRL

#define E1000_SCCRL 0x05DB0 /* Storm Control Control */

Definition at line 587 of file e1000_regs.h.

◆ E1000_SCCTL

#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */

Definition at line 534 of file e1000_regs.h.

◆ E1000_SCTL

#define E1000_SCTL 0x00024 /* SerDes Control - RW */

Definition at line 60 of file e1000_regs.h.

◆ E1000_SCVPC

#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */

Definition at line 487 of file e1000_regs.h.

◆ E1000_SEC

#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */

Definition at line 338 of file e1000_regs.h.

◆ E1000_SHADOWINF

#define E1000_SHADOWINF 0x12068

Definition at line 188 of file e1000_regs.h.

◆ E1000_SHRAH

#define E1000_SHRAH ( _i ) (0x0543C + ((_i) * 8))

Definition at line 295 of file e1000_regs.h.

◆ E1000_SHRAL

#define E1000_SHRAL ( _i ) (0x05438 + ((_i) * 8))

Definition at line 294 of file e1000_regs.h.

◆ E1000_SPQF

#define E1000_SPQF ( _n ) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */

Definition at line 629 of file e1000_regs.h.

◆ E1000_SRRCTL

#define E1000_SRRCTL ( _n )

Value:

((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \

(0x0C00C + ((_n) * 0x40)))

Definition at line 252 of file e1000_regs.h.

◆ E1000_SRWR

#define E1000_SRWR 0x12018

Definition at line 175 of file e1000_regs.h.

◆ E1000_SSVPC

#define E1000_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */

Definition at line 458 of file e1000_regs.h.

◆ E1000_STATUS

#define E1000_STATUS 0x00008 /* Device Status - RO */

Definition at line 41 of file e1000_regs.h.

◆ E1000_SVCR

#define E1000_SVCR 0x000F0

Definition at line 86 of file e1000_regs.h.

◆ E1000_SVT

#define E1000_SVT 0x000F4

Definition at line 87 of file e1000_regs.h.

◆ E1000_SW_FW_SYNC

#define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */

Definition at line 531 of file e1000_regs.h.

◆ E1000_SWDSTS

#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */

Definition at line 140 of file e1000_regs.h.

◆ E1000_SWPBS

#define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */

Definition at line 569 of file e1000_regs.h.

◆ E1000_SWSM

#define E1000_SWSM 0x05B50 /* SW Semaphore */

Definition at line 544 of file e1000_regs.h.

◆ E1000_SWSM2

#define E1000_SWSM2 0x05B58

Definition at line 547 of file e1000_regs.h.

◆ E1000_SYMERRS

#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */

Definition at line 328 of file e1000_regs.h.

◆ E1000_SYNQF

#define E1000_SYNQF ( _n ) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */

Definition at line 632 of file e1000_regs.h.

◆ E1000_SYSSTMPH

#define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */

Definition at line 617 of file e1000_regs.h.

◆ E1000_SYSSTMPL

#define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */

Definition at line 616 of file e1000_regs.h.

◆ E1000_SYSTIMH

#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */

Definition at line 611 of file e1000_regs.h.

◆ E1000_SYSTIML

#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */

Definition at line 610 of file e1000_regs.h.

◆ E1000_SYSTIMR

#define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */

Definition at line 620 of file e1000_regs.h.

◆ E1000_TADV

#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */

Definition at line 323 of file e1000_regs.h.

◆ E1000_TARC

#define E1000_TARC ( _n ) (0x03840 + ((_n) * 0x100))

Definition at line 284 of file e1000_regs.h.

◆ E1000_TBT

#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */

Definition at line 107 of file e1000_regs.h.

◆ E1000_TCPTIMER

#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */

Definition at line 142 of file e1000_regs.h.

◆ E1000_TCTL

#define E1000_TCTL 0x00400 /* Tx Control - RW */

Definition at line 104 of file e1000_regs.h.

◆ E1000_TCTL_EXT

#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */

Definition at line 105 of file e1000_regs.h.

◆ E1000_TDBAH

#define E1000_TDBAH ( _n )

Value:

((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \

(0x0E004 + ((_n) * 0x40)))

Definition at line 267 of file e1000_regs.h.

◆ E1000_TDBAL

#define E1000_TDBAL ( _n )

Value:

((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \

(0x0E000 + ((_n) * 0x40)))

Definition at line 265 of file e1000_regs.h.

◆ E1000_TDFH

#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */

Definition at line 307 of file e1000_regs.h.

◆ E1000_TDFHS

#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */

Definition at line 309 of file e1000_regs.h.

◆ E1000_TDFPC

#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */

Definition at line 311 of file e1000_regs.h.

◆ E1000_TDFT

#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */

Definition at line 308 of file e1000_regs.h.

◆ E1000_TDFTS

#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */

Definition at line 310 of file e1000_regs.h.

◆ E1000_TDH

#define E1000_TDH ( _n )

Value:

((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \

(0x0E010 + ((_n) * 0x40)))

Definition at line 271 of file e1000_regs.h.

◆ E1000_TDLEN

#define E1000_TDLEN ( _n )

Value:

((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \

(0x0E008 + ((_n) * 0x40)))

Definition at line 269 of file e1000_regs.h.

◆ E1000_TDPUAD

#define E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */

Definition at line 313 of file e1000_regs.h.

◆ E1000_TDPUCTL

#define E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */

Definition at line 316 of file e1000_regs.h.

◆ E1000_TDPUMB

#define E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */

Definition at line 312 of file e1000_regs.h.

◆ E1000_TDPURD

#define E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */

Definition at line 315 of file e1000_regs.h.

◆ E1000_TDPUWD

#define E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */

Definition at line 314 of file e1000_regs.h.

◆ E1000_TDT

#define E1000_TDT ( _n )

Value:

((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \

(0x0E018 + ((_n) * 0x40)))

Definition at line 276 of file e1000_regs.h.

◆ E1000_TDWBAH

#define E1000_TDWBAH ( _n )

Value:

((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \

(0x0E03C + ((_n) * 0x40)))

Definition at line 282 of file e1000_regs.h.

◆ E1000_TDWBAL

#define E1000_TDWBAL ( _n )

Value:

((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \

(0x0E038 + ((_n) * 0x40)))

Definition at line 280 of file e1000_regs.h.

◆ E1000_THHIGHTC

#define E1000_THHIGHTC 0x0810C /* High Threshold Control */

Definition at line 703 of file e1000_regs.h.

◆ E1000_THLOWTC

#define E1000_THLOWTC 0x08104 /* Low Threshold Control */

Definition at line 701 of file e1000_regs.h.

◆ E1000_THMIDTC

#define E1000_THMIDTC 0x08108 /* Mid Threshold Control */

Definition at line 702 of file e1000_regs.h.

◆ E1000_THMJT

#define E1000_THMJT 0x08100 /* Junction Temperature */

Definition at line 700 of file e1000_regs.h.

◆ E1000_THSTAT

#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */

Definition at line 704 of file e1000_regs.h.

◆ E1000_TIDV

#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */

Definition at line 322 of file e1000_regs.h.

◆ E1000_TIMADJH

#define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */

Definition at line 614 of file e1000_regs.h.

◆ E1000_TIMADJL

#define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */

Definition at line 613 of file e1000_regs.h.

◆ E1000_TIMINCA

#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */

Definition at line 612 of file e1000_regs.h.

◆ E1000_TIPG

#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */

Definition at line 106 of file e1000_regs.h.

◆ E1000_TLPIC

#define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */

Definition at line 711 of file e1000_regs.h.

◆ E1000_TNCRS

#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */

Definition at line 337 of file e1000_regs.h.

◆ E1000_TORH

#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */

Definition at line 369 of file e1000_regs.h.

◆ E1000_TORL

#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */

Definition at line 368 of file e1000_regs.h.

◆ E1000_TOTH

#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */

Definition at line 371 of file e1000_regs.h.

◆ E1000_TOTL

#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */

Definition at line 370 of file e1000_regs.h.

◆ E1000_TPR

#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */

Definition at line 372 of file e1000_regs.h.

◆ E1000_TPT

#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */

Definition at line 373 of file e1000_regs.h.

◆ E1000_TQAVARBCTRL_QUEUE_PRI

#define E1000_TQAVARBCTRL_QUEUE_PRI	(	_n,
		_p
	)	((_p) << (2 * (_n)))

Definition at line 221 of file e1000_regs.h.

◆ E1000_TQAVCC_IDLE_SLOPE

#define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */

Definition at line 226 of file e1000_regs.h.

◆ E1000_TQAVCC_KEEP_CREDITS

#define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */

Definition at line 227 of file e1000_regs.h.

◆ E1000_TQAVCC_QUEUE_MODE

#define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */

Definition at line 228 of file e1000_regs.h.

◆ E1000_TQAVCTRL_FETCH_ARB

#define E1000_TQAVCTRL_FETCH_ARB (1 << 4)

Definition at line 201 of file e1000_regs.h.

◆ E1000_TQAVCTRL_FETCH_TIMER_DELTA

#define E1000_TQAVCTRL_FETCH_TIMER_DELTA (0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)

Definition at line 212 of file e1000_regs.h.

◆ E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET

#define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16

Definition at line 211 of file e1000_regs.h.

◆ E1000_TQAVCTRL_FETCH_TIMER_ENABLE

#define E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5)

Definition at line 203 of file e1000_regs.h.

◆ E1000_TQAVCTRL_LAUNCH_ARB

#define E1000_TQAVCTRL_LAUNCH_ARB (1 << 8)

Definition at line 205 of file e1000_regs.h.

◆ E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE

#define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9)

Definition at line 207 of file e1000_regs.h.

◆ E1000_TQAVCTRL_MODE

#define E1000_TQAVCTRL_MODE (1 << 0)

Definition at line 199 of file e1000_regs.h.

◆ E1000_TQAVCTRL_SP_WAIT_SR

#define E1000_TQAVCTRL_SP_WAIT_SR (1 << 10)

Definition at line 209 of file e1000_regs.h.

◆ E1000_TSAUXC

#define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */

Definition at line 615 of file e1000_regs.h.

◆ E1000_TSCTC

#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */

Definition at line 382 of file e1000_regs.h.

◆ E1000_TSCTFC

#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */

Definition at line 383 of file e1000_regs.h.

◆ E1000_TSICR

#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */

Definition at line 621 of file e1000_regs.h.

◆ E1000_TSIM

#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */

Definition at line 622 of file e1000_regs.h.

◆ E1000_TSPMT

#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */

Definition at line 324 of file e1000_regs.h.

◆ E1000_TSYNCRXCFG

#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */

Definition at line 603 of file e1000_regs.h.

◆ E1000_TSYNCRXCTL

#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */

Definition at line 601 of file e1000_regs.h.

◆ E1000_TSYNCTXCTL

#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */

Definition at line 602 of file e1000_regs.h.

◆ E1000_TTQF

#define E1000_TTQF ( _n ) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */

Definition at line 631 of file e1000_regs.h.

◆ E1000_TXCTL

#define E1000_TXCTL ( _n )

Value:

((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \

(0x0E014 + ((_n) * 0x40)))

Definition at line 273 of file e1000_regs.h.

◆ E1000_TXCW

#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */

Definition at line 91 of file e1000_regs.h.

◆ E1000_TXDCTL

#define E1000_TXDCTL ( _n )

Value:

((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \

(0x0E028 + ((_n) * 0x40)))

Definition at line 278 of file e1000_regs.h.

◆ E1000_TXDMAC

#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */

Definition at line 287 of file e1000_regs.h.

◆ E1000_TXPBS

#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */

Definition at line 304 of file e1000_regs.h.

◆ E1000_TXSTMPH

#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */

Definition at line 609 of file e1000_regs.h.

◆ E1000_TXSTMPL

#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */

Definition at line 608 of file e1000_regs.h.

◆ E1000_TXSWC

#define E1000_TXSWC 0x05ACC /* Tx Switch Control */

Definition at line 586 of file e1000_regs.h.

◆ E1000_UFUSE

#define E1000_UFUSE 0x05B78 /* UFUSE - RO */

Definition at line 550 of file e1000_regs.h.

◆ E1000_UTA

#define E1000_UTA 0x0A000 /* Unicast Table Array - RW */

Definition at line 579 of file e1000_regs.h.

◆ E1000_V2PMAILBOX

#define E1000_V2PMAILBOX ( _n ) (0x00C40 + (4 * (_n)))

Definition at line 591 of file e1000_regs.h.

◆ E1000_VET

#define E1000_VET 0x00038 /* VLAN Ether Type - RW */

Definition at line 78 of file e1000_regs.h.

◆ E1000_VFGORC

#define E1000_VFGORC 0x00F18

Definition at line 397 of file e1000_regs.h.

◆ E1000_VFGORLBC

#define E1000_VFGORLBC 0x00F48

Definition at line 403 of file e1000_regs.h.

◆ E1000_VFGOTC

#define E1000_VFGOTC 0x00F34

Definition at line 400 of file e1000_regs.h.

◆ E1000_VFGOTLBC

#define E1000_VFGOTLBC 0x00F50

Definition at line 401 of file e1000_regs.h.

◆ E1000_VFGPRC

#define E1000_VFGPRC 0x00F10

Definition at line 396 of file e1000_regs.h.

◆ E1000_VFGPRLBC

#define E1000_VFGPRLBC 0x00F40

Definition at line 404 of file e1000_regs.h.

◆ E1000_VFGPTC

#define E1000_VFGPTC 0x00F14

Definition at line 399 of file e1000_regs.h.

◆ E1000_VFGPTLBC

#define E1000_VFGPTLBC 0x00F44

Definition at line 402 of file e1000_regs.h.

◆ E1000_VFLRE

#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */

Definition at line 572 of file e1000_regs.h.

◆ E1000_VFMPRC

#define E1000_VFMPRC 0x00F3C

Definition at line 398 of file e1000_regs.h.

◆ E1000_VFQA0

#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */

Definition at line 503 of file e1000_regs.h.

◆ E1000_VFQA1

#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */

Definition at line 504 of file e1000_regs.h.

◆ E1000_VFRE

#define E1000_VFRE 0x00C8C /* VF Receive Enables */

Definition at line 573 of file e1000_regs.h.

◆ E1000_VFTA

#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */

Definition at line 499 of file e1000_regs.h.

◆ E1000_VFTE

#define E1000_VFTE 0x00C90 /* VF Transmit Enables */

Definition at line 574 of file e1000_regs.h.

◆ E1000_VFVMBMEM

#define E1000_VFVMBMEM ( _n ) (0x00800 + (_n))

Definition at line 594 of file e1000_regs.h.

◆ E1000_VLVF

#define E1000_VLVF ( _n ) (0x05D00 + (4 * (_n)))

Definition at line 597 of file e1000_regs.h.

◆ E1000_VMBMEM

#define E1000_VMBMEM ( _n ) (0x00800 + (64 * (_n)))

Definition at line 593 of file e1000_regs.h.

◆ E1000_VMOLR

#define E1000_VMOLR ( _n ) (0x05AD0 + (4 * (_n)))

Definition at line 595 of file e1000_regs.h.

◆ E1000_VMRCTL

#define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */

Definition at line 581 of file e1000_regs.h.

◆ E1000_VMRVLAN

#define E1000_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */

Definition at line 582 of file e1000_regs.h.

◆ E1000_VMRVM

#define E1000_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */

Definition at line 583 of file e1000_regs.h.

◆ E1000_VMVIR

#define E1000_VMVIR ( _n ) (0x03700 + (4 * (_n)))

Definition at line 598 of file e1000_regs.h.

◆ E1000_VPDDIAG

#define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */

Definition at line 143 of file e1000_regs.h.

◆ E1000_VT_CTL

#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */

Definition at line 500 of file e1000_regs.h.

◆ E1000_VTCTRL

#define E1000_VTCTRL ( _n ) (0x10000 + (0x100 * (_n))) /* VT Control */

Definition at line 600 of file e1000_regs.h.

◆ E1000_WDSTP

#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */

Definition at line 139 of file e1000_regs.h.

◆ E1000_WUC

#define E1000_WUC 0x05800 /* Wakeup Control - RW */

Definition at line 505 of file e1000_regs.h.

◆ E1000_WUFC

#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */

Definition at line 506 of file e1000_regs.h.

◆ E1000_WUPL

#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */

Definition at line 513 of file e1000_regs.h.

◆ E1000_WUPM

#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */

Definition at line 514 of file e1000_regs.h.

◆ E1000_WUPM_REG

#define E1000_WUPM_REG ( _i ) (0x05A00 + ((_i) * 4))

Definition at line 298 of file e1000_regs.h.

◆ E1000_WUS

#define E1000_WUS 0x05810 /* Wakeup Status - RO */

Definition at line 507 of file e1000_regs.h.

◆ E1000_WVBR

#define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */

Definition at line 577 of file e1000_regs.h.

◆ E1000_XOFFRXC

#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */

Definition at line 343 of file e1000_regs.h.

◆ E1000_XOFFTXC

#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */

Definition at line 344 of file e1000_regs.h.

◆ E1000_XONRXC

#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */

Definition at line 341 of file e1000_regs.h.

◆ E1000_XONTXC

#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */

Definition at line 342 of file e1000_regs.h.

Macros

Macro Definition Documentation

◆ E1000_AIT

◆ E1000_ALGNERRC

◆ E1000_B2OGPRC

◆ E1000_B2OSPC

◆ E1000_BARCTRL

◆ E1000_BARCTRL_CSRSIZE

◆ E1000_BARCTRL_FLSIZE

◆ E1000_BPRC

◆ E1000_BPTC

◆ E1000_BSCTRH

◆ E1000_CBRDPC

◆ E1000_CBRMPC

◆ E1000_CBTMPC

◆ E1000_CCMCTL

◆ E1000_CEXTERR

◆ E1000_CIAA

◆ E1000_CIAD

◆ E1000_COLC

◆ E1000_CONNSW

◆ E1000_CPUVEC

◆ E1000_CRC_OFFSET

◆ E1000_CRCERRS

◆ E1000_CTRL

◆ E1000_CTRL_DUP

◆ E1000_CTRL_EXT

◆ E1000_DAQF

◆ E1000_DC

◆ E1000_DCA_CTRL

◆ E1000_DCA_ID

◆ E1000_DCA_RXCTRL

◆ E1000_DCA_TXCTRL

◆ E1000_DMACR

◆ E1000_DMCCNT

◆ E1000_DMCRTRH

◆ E1000_DMCTLX

◆ E1000_DMCTXTH

◆ E1000_DOBFFCTL

◆ E1000_DPGFR

◆ E1000_DTXCTL

◆ E1000_DTXMXSZRQ

◆ E1000_DTXSWC

◆ E1000_DTXTCPFLGH

◆ E1000_DTXTCPFLGL

◆ E1000_DVMOLR

◆ E1000_ECOL

◆ E1000_EEARBC

◆ E1000_EEARBC_I210

◆ E1000_EEC_REG

◆ E1000_EECD

◆ E1000_EEE_SU

◆ E1000_EEER

◆ E1000_EEMNGCTL

◆ E1000_EEMNGCTL_I210

◆ E1000_EEPROM_INIT_CTRL_WORD_2

◆ E1000_EEPROM_PCIE_CTRL_WORD_2

◆ E1000_EERD

◆ E1000_EEWR

◆ E1000_EIAC

◆ E1000_EIAM

◆ E1000_EICR

◆ E1000_EICS

◆ E1000_EIMC

◆ E1000_EIMS

◆ E1000_EITR

◆ E1000_EMIADD

◆ E1000_EMIDATA

◆ E1000_ERT

◆ E1000_ETQF

◆ E1000_ETQF_ETYPE_MASK

◆ E1000_ETQF_FILTER_ENABLE

◆ E1000_ETQF_IMM_INT

◆ E1000_ETQF_QUEUE_ENABLE

◆ E1000_ETQF_QUEUE_MASK

◆ E1000_ETQF_QUEUE_SHIFT

◆ E1000_EXTCNF_CTRL

◆ E1000_EXTCNF_SIZE

◆ E1000_FACTPS

◆ E1000_FCAH