FreeBSD kernel E1000 device code
e1000_82575.c
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1/******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
20
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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31 POSSIBILITY OF SUCH DAMAGE.
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33******************************************************************************/
34/*$FreeBSD$*/
35
36/*
37 * 82575EB Gigabit Network Connection
38 * 82575EB Gigabit Backplane Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter
42 * 82580 Gigabit Network Connection
43 * I350 Gigabit Network Connection
44 */
45
46#include "e1000_api.h"
47#include "e1000_i210.h"
48
49static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
50static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
51static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52static void e1000_release_nvm_82575(struct e1000_hw *hw);
53static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
57 u16 *duplex);
58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60 u16 *data);
61static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62static s32 e1000_init_hw_82575(struct e1000_hw *hw);
63static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 u32 offset, u16 *data);
66static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 u32 offset, u16 data);
68static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 bool active);
70static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 bool active);
72static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 bool active);
74static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 u32 offset, u16 data);
81static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
86static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
87static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
88static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
89static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
90static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
91static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
92static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
93static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
94static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
95 u16 offset);
96static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
97 u16 offset);
98static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
99static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
100static void e1000_clear_vfta_i350(struct e1000_hw *hw);
101
102static void e1000_i2c_start(struct e1000_hw *hw);
103static void e1000_i2c_stop(struct e1000_hw *hw);
104static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
105static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
106static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
107static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
108static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
109static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
110static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
111static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
112static bool e1000_get_i2c_data(u32 *i2cctl);
113
114static const u16 e1000_82580_rxpbs_table[] = {
115 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
116#define E1000_82580_RXPBS_TABLE_SIZE \
117 (sizeof(e1000_82580_rxpbs_table) / \
118 sizeof(e1000_82580_rxpbs_table[0]))
119
120
128static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
129{
130 u32 reg = 0;
131 bool ext_mdio = false;
132
133 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
134
135 switch (hw->mac.type) {
136 case e1000_82575:
137 case e1000_82576:
138 reg = E1000_READ_REG(hw, E1000_MDIC);
139 ext_mdio = !!(reg & E1000_MDIC_DEST);
140 break;
141 case e1000_82580:
142 case e1000_i350:
143 case e1000_i354:
144 case e1000_i210:
145 case e1000_i211:
146 reg = E1000_READ_REG(hw, E1000_MDICNFG);
147 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
148 break;
149 default:
150 break;
151 }
152 return ext_mdio;
153}
154
159static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
160{
161 struct e1000_phy_info *phy = &hw->phy;
162 s32 ret_val = E1000_SUCCESS;
163 u32 ctrl_ext;
164
165 DEBUGFUNC("e1000_init_phy_params_82575");
166
167 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
168 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
169
170 if (hw->phy.media_type != e1000_media_type_copper) {
171 phy->type = e1000_phy_none;
172 goto out;
173 }
174
175 phy->ops.power_up = e1000_power_up_phy_copper;
176 phy->ops.power_down = e1000_power_down_phy_copper_base;
177
178 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
179 phy->reset_delay_us = 100;
180
181 phy->ops.acquire = e1000_acquire_phy_base;
182 phy->ops.check_reset_block = e1000_check_reset_block_generic;
183 phy->ops.commit = e1000_phy_sw_reset_generic;
184 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
185 phy->ops.release = e1000_release_phy_base;
186
187 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
188
189 if (e1000_sgmii_active_82575(hw)) {
190 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
191 ctrl_ext |= E1000_CTRL_I2C_ENA;
192 } else {
193 phy->ops.reset = e1000_phy_hw_reset_generic;
194 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
195 }
196
197 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
198 e1000_reset_mdicnfg_82580(hw);
199
200 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
201 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
202 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
203 } else {
204 switch (hw->mac.type) {
205 case e1000_82580:
206 case e1000_i350:
207 case e1000_i354:
208 phy->ops.read_reg = e1000_read_phy_reg_82580;
209 phy->ops.write_reg = e1000_write_phy_reg_82580;
210 break;
211 case e1000_i210:
212 case e1000_i211:
213 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
214 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
215 break;
216 default:
217 phy->ops.read_reg = e1000_read_phy_reg_igp;
218 phy->ops.write_reg = e1000_write_phy_reg_igp;
219 }
220 }
221
222 /* Set phy->phy_addr and phy->id. */
223 ret_val = e1000_get_phy_id_82575(hw);
224
225 /* Verify phy id and set remaining function pointers */
226 switch (phy->id) {
227 case M88E1543_E_PHY_ID:
228 case M88E1512_E_PHY_ID:
229 case I347AT4_E_PHY_ID:
230 case M88E1112_E_PHY_ID:
231 case M88E1340M_E_PHY_ID:
232 phy->type = e1000_phy_m88;
233 phy->ops.check_polarity = e1000_check_polarity_m88;
234 phy->ops.get_info = e1000_get_phy_info_m88;
235 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
236 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
237 break;
238 case M88E1111_I_PHY_ID:
239 phy->type = e1000_phy_m88;
240 phy->ops.check_polarity = e1000_check_polarity_m88;
241 phy->ops.get_info = e1000_get_phy_info_m88;
242 phy->ops.get_cable_length = e1000_get_cable_length_m88;
243 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
244 break;
245 case IGP03E1000_E_PHY_ID:
246 case IGP04E1000_E_PHY_ID:
247 phy->type = e1000_phy_igp_3;
248 phy->ops.check_polarity = e1000_check_polarity_igp;
249 phy->ops.get_info = e1000_get_phy_info_igp;
250 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
251 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
252 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
253 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
254 break;
255 case I82580_I_PHY_ID:
256 case I350_I_PHY_ID:
257 phy->type = e1000_phy_82580;
258 phy->ops.check_polarity = e1000_check_polarity_82577;
259 phy->ops.get_info = e1000_get_phy_info_82577;
260 phy->ops.get_cable_length = e1000_get_cable_length_82577;
261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
263 phy->ops.force_speed_duplex =
264 e1000_phy_force_speed_duplex_82577;
265 break;
266 case I210_I_PHY_ID:
267 phy->type = e1000_phy_i210;
268 phy->ops.check_polarity = e1000_check_polarity_m88;
269 phy->ops.get_info = e1000_get_phy_info_m88;
270 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
273 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
274 break;
275 default:
276 ret_val = -E1000_ERR_PHY;
277 goto out;
278 }
279
280 /* Check if this PHY is configured for media swap. */
281 switch (phy->id) {
282 case M88E1112_E_PHY_ID:
283 {
284 u16 data;
285
286 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
287 if (ret_val)
288 goto out;
289 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
290 &data);
291 if (ret_val)
292 goto out;
293
294 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
295 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
296 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
297 data == E1000_M88E1112_AUTO_COPPER_BASEX)
298 hw->mac.ops.check_for_link =
299 e1000_check_for_link_media_swap;
300 break;
301 }
302 case M88E1512_E_PHY_ID:
303 {
304 ret_val = e1000_initialize_M88E1512_phy(hw);
305 break;
306 }
307 case M88E1543_E_PHY_ID:
308 {
309 ret_val = e1000_initialize_M88E1543_phy(hw);
310 break;
311 }
312 default:
313 goto out;
314 }
315
316out:
317 return ret_val;
318}
319
324static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
325{
326 struct e1000_mac_info *mac = &hw->mac;
327 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
328
329 DEBUGFUNC("e1000_init_mac_params_82575");
330
331 /* Initialize function pointer */
332 e1000_init_mac_ops_generic(hw);
333
334 /* Derives media type */
335 e1000_get_media_type_82575(hw);
336 /* Set MTA register count */
337 mac->mta_reg_count = 128;
338 /* Set UTA register count */
339 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
340 /* Set RAR entry count */
341 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
342 if (mac->type == e1000_82576)
343 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
344 if (mac->type == e1000_82580)
345 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
346 if (mac->type == e1000_i350 || mac->type == e1000_i354)
347 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
348
349 /* Enable EEE default settings for EEE supported devices */
350 if (mac->type >= e1000_i350)
351 dev_spec->eee_disable = false;
352
353 /* Allow a single clear of the SW semaphore on I210 and newer */
354 if (mac->type >= e1000_i210)
355 dev_spec->clear_semaphore_once = true;
356
357 /* Set if part includes ASF firmware */
358 mac->asf_firmware_present = true;
359 /* FWSM register */
360 mac->has_fwsm = true;
361 /* ARC supported; valid only if manageability features are enabled. */
362 mac->arc_subsystem_valid =
363 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
364
365 /* Function pointers */
366
367 /* bus type/speed/width */
368 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
369 /* reset */
370 if (mac->type >= e1000_82580)
371 mac->ops.reset_hw = e1000_reset_hw_82580;
372 else
373 mac->ops.reset_hw = e1000_reset_hw_82575;
374 /* HW initialization */
375 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
376 mac->ops.init_hw = e1000_init_hw_i210;
377 else
378 mac->ops.init_hw = e1000_init_hw_82575;
379 /* link setup */
380 mac->ops.setup_link = e1000_setup_link_generic;
381 /* physical interface link setup */
382 mac->ops.setup_physical_interface =
383 (hw->phy.media_type == e1000_media_type_copper)
384 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
385 /* physical interface shutdown */
386 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
387 /* physical interface power up */
388 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
389 /* check for link */
390 mac->ops.check_for_link = e1000_check_for_link_82575;
391 /* read mac address */
392 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
393 /* configure collision distance */
394 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
395 /* multicast address update */
396 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
397 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
398 /* writing VFTA */
399 mac->ops.write_vfta = e1000_write_vfta_i350;
400 /* clearing VFTA */
401 mac->ops.clear_vfta = e1000_clear_vfta_i350;
402 } else {
403 /* writing VFTA */
404 mac->ops.write_vfta = e1000_write_vfta_generic;
405 /* clearing VFTA */
406 mac->ops.clear_vfta = e1000_clear_vfta_generic;
407 }
408 if (hw->mac.type >= e1000_82580)
409 mac->ops.validate_mdi_setting =
410 e1000_validate_mdi_setting_crossover_generic;
411 /* ID LED init */
412 mac->ops.id_led_init = e1000_id_led_init_generic;
413 /* blink LED */
414 mac->ops.blink_led = e1000_blink_led_generic;
415 /* setup LED */
416 mac->ops.setup_led = e1000_setup_led_generic;
417 /* cleanup LED */
418 mac->ops.cleanup_led = e1000_cleanup_led_generic;
419 /* turn on/off LED */
420 mac->ops.led_on = e1000_led_on_generic;
421 mac->ops.led_off = e1000_led_off_generic;
422 /* clear hardware counters */
423 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
424 /* link info */
425 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
426 /* acquire SW_FW sync */
427 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync;
428 /* release SW_FW sync */
429 mac->ops.release_swfw_sync = e1000_release_swfw_sync;
430
431 /* set lan id for port to determine which phy lock to use */
432 hw->mac.ops.set_lan_id(hw);
433
434 return E1000_SUCCESS;
435}
436
441s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
442{
443 struct e1000_nvm_info *nvm = &hw->nvm;
444 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
445 u16 size;
446
447 DEBUGFUNC("e1000_init_nvm_params_82575");
448
449 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
450 E1000_EECD_SIZE_EX_SHIFT);
451 /* Added to a constant, "size" becomes the left-shift value
452 * for setting word_size.
453 */
454 size += NVM_WORD_SIZE_BASE_SHIFT;
455
456 /* Just in case size is out of range, cap it to the largest
457 * EEPROM size supported
458 */
459 if (size > 15)
460 size = 15;
461
462 nvm->word_size = 1 << size;
463 if (hw->mac.type < e1000_i210) {
464 nvm->opcode_bits = 8;
465 nvm->delay_usec = 1;
466
467 switch (nvm->override) {
468 case e1000_nvm_override_spi_large:
469 nvm->page_size = 32;
470 nvm->address_bits = 16;
471 break;
472 case e1000_nvm_override_spi_small:
473 nvm->page_size = 8;
474 nvm->address_bits = 8;
475 break;
476 default:
477 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
478 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
479 16 : 8;
480 break;
481 }
482 if (nvm->word_size == (1 << 15))
483 nvm->page_size = 128;
484
485 nvm->type = e1000_nvm_eeprom_spi;
486 } else {
487 nvm->type = e1000_nvm_flash_hw;
488 }
489
490 /* Function Pointers */
491 nvm->ops.acquire = e1000_acquire_nvm_82575;
492 nvm->ops.release = e1000_release_nvm_82575;
493 if (nvm->word_size < (1 << 15))
494 nvm->ops.read = e1000_read_nvm_eerd;
495 else
496 nvm->ops.read = e1000_read_nvm_spi;
497
498 nvm->ops.write = e1000_write_nvm_spi;
499 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
500 nvm->ops.update = e1000_update_nvm_checksum_generic;
501 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
502
503 /* override generic family function pointers for specific descendants */
504 switch (hw->mac.type) {
505 case e1000_82580:
506 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
507 nvm->ops.update = e1000_update_nvm_checksum_82580;
508 break;
509 case e1000_i350:
510 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
511 nvm->ops.update = e1000_update_nvm_checksum_i350;
512 break;
513 default:
514 break;
515 }
516
517 return E1000_SUCCESS;
518}
519
526void e1000_init_function_pointers_82575(struct e1000_hw *hw)
527{
528 DEBUGFUNC("e1000_init_function_pointers_82575");
529
530 hw->mac.ops.init_params = e1000_init_mac_params_82575;
531 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
532 hw->phy.ops.init_params = e1000_init_phy_params_82575;
533 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
534}
535
545static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
546 u16 *data)
547{
548 s32 ret_val = -E1000_ERR_PARAM;
549
550 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
551
552 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
553 DEBUGOUT1("PHY Address %u is out of range\n", offset);
554 goto out;
555 }
556
557 ret_val = hw->phy.ops.acquire(hw);
558 if (ret_val)
559 goto out;
560
561 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
562
563 hw->phy.ops.release(hw);
564
565out:
566 return ret_val;
567}
568
578static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
579 u16 data)
580{
581 s32 ret_val = -E1000_ERR_PARAM;
582
583 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
584
585 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
586 DEBUGOUT1("PHY Address %d is out of range\n", offset);
587 goto out;
588 }
589
590 ret_val = hw->phy.ops.acquire(hw);
591 if (ret_val)
592 goto out;
593
594 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
595
596 hw->phy.ops.release(hw);
597
598out:
599 return ret_val;
600}
601
609static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
610{
611 struct e1000_phy_info *phy = &hw->phy;
612 s32 ret_val = E1000_SUCCESS;
613 u16 phy_id;
614 u32 ctrl_ext;
615 u32 mdic;
616
617 DEBUGFUNC("e1000_get_phy_id_82575");
618
619 /* some i354 devices need an extra read for phy id */
620 if (hw->mac.type == e1000_i354)
621 e1000_get_phy_id(hw);
622
623 /*
624 * For SGMII PHYs, we try the list of possible addresses until
625 * we find one that works. For non-SGMII PHYs
626 * (e.g. integrated copper PHYs), an address of 1 should
627 * work. The result of this function should mean phy->phy_addr
628 * and phy->id are set correctly.
629 */
630 if (!e1000_sgmii_active_82575(hw)) {
631 phy->addr = 1;
632 ret_val = e1000_get_phy_id(hw);
633 goto out;
634 }
635
636 if (e1000_sgmii_uses_mdio_82575(hw)) {
637 switch (hw->mac.type) {
638 case e1000_82575:
639 case e1000_82576:
640 mdic = E1000_READ_REG(hw, E1000_MDIC);
641 mdic &= E1000_MDIC_PHY_MASK;
642 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
643 break;
644 case e1000_82580:
645 case e1000_i350:
646 case e1000_i354:
647 case e1000_i210:
648 case e1000_i211:
649 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
650 mdic &= E1000_MDICNFG_PHY_MASK;
651 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
652 break;
653 default:
654 ret_val = -E1000_ERR_PHY;
655 goto out;
656 break;
657 }
658 ret_val = e1000_get_phy_id(hw);
659 goto out;
660 }
661
662 /* Power on sgmii phy if it is disabled */
663 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
664 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
665 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
666 E1000_WRITE_FLUSH(hw);
667 msec_delay(300);
668
669 /*
670 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
671 * Therefore, we need to test 1-7
672 */
673 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
674 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
675 if (ret_val == E1000_SUCCESS) {
676 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
677 phy_id, phy->addr);
678 /*
679 * At the time of this writing, The M88 part is
680 * the only supported SGMII PHY product.
681 */
682 if (phy_id == M88_VENDOR)
683 break;
684 } else {
685 DEBUGOUT1("PHY address %u was unreadable\n",
686 phy->addr);
687 }
688 }
689
690 /* A valid PHY type couldn't be found. */
691 if (phy->addr == 8) {
692 phy->addr = 0;
693 ret_val = -E1000_ERR_PHY;
694 } else {
695 ret_val = e1000_get_phy_id(hw);
696 }
697
698 /* restore previous sfp cage power state */
699 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
700
701out:
702 return ret_val;
703}
704
711static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
712{
713 s32 ret_val = E1000_SUCCESS;
714 struct e1000_phy_info *phy = &hw->phy;
715
716 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
717
718 /*
719 * This isn't a true "hard" reset, but is the only reset
720 * available to us at this time.
721 */
722
723 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
724
725 if (!(hw->phy.ops.write_reg))
726 goto out;
727
728 /*
729 * SFP documentation requires the following to configure the SPF module
730 * to work on SGMII. No further documentation is given.
731 */
732 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
733 if (ret_val)
734 goto out;
735
736 ret_val = hw->phy.ops.commit(hw);
737 if (ret_val)
738 goto out;
739
740 if (phy->id == M88E1512_E_PHY_ID)
741 ret_val = e1000_initialize_M88E1512_phy(hw);
742out:
743 return ret_val;
744}
745
759static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
760{
761 struct e1000_phy_info *phy = &hw->phy;
762 s32 ret_val = E1000_SUCCESS;
763 u16 data;
764
765 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
766
767 if (!(hw->phy.ops.read_reg))
768 goto out;
769
770 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
771 if (ret_val)
772 goto out;
773
774 if (active) {
775 data |= IGP02E1000_PM_D0_LPLU;
776 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
777 data);
778 if (ret_val)
779 goto out;
780
781 /* When LPLU is enabled, we should disable SmartSpeed */
782 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
783 &data);
784 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
785 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
786 data);
787 if (ret_val)
788 goto out;
789 } else {
790 data &= ~IGP02E1000_PM_D0_LPLU;
791 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
792 data);
793 /*
794 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
795 * during Dx states where the power conservation is most
796 * important. During driver activity we should enable
797 * SmartSpeed, so performance is maintained.
798 */
799 if (phy->smart_speed == e1000_smart_speed_on) {
800 ret_val = phy->ops.read_reg(hw,
801 IGP01E1000_PHY_PORT_CONFIG,
802 &data);
803 if (ret_val)
804 goto out;
805
806 data |= IGP01E1000_PSCFR_SMART_SPEED;
807 ret_val = phy->ops.write_reg(hw,
808 IGP01E1000_PHY_PORT_CONFIG,
809 data);
810 if (ret_val)
811 goto out;
812 } else if (phy->smart_speed == e1000_smart_speed_off) {
813 ret_val = phy->ops.read_reg(hw,
814 IGP01E1000_PHY_PORT_CONFIG,
815 &data);
816 if (ret_val)
817 goto out;
818
819 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
820 ret_val = phy->ops.write_reg(hw,
821 IGP01E1000_PHY_PORT_CONFIG,
822 data);
823 if (ret_val)
824 goto out;
825 }
826 }
827
828out:
829 return ret_val;
830}
831
845static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
846{
847 struct e1000_phy_info *phy = &hw->phy;
848 u32 data;
849
850 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
851
852 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
853
854 if (active) {
855 data |= E1000_82580_PM_D0_LPLU;
856
857 /* When LPLU is enabled, we should disable SmartSpeed */
858 data &= ~E1000_82580_PM_SPD;
859 } else {
860 data &= ~E1000_82580_PM_D0_LPLU;
861
862 /*
863 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
864 * during Dx states where the power conservation is most
865 * important. During driver activity we should enable
866 * SmartSpeed, so performance is maintained.
867 */
868 if (phy->smart_speed == e1000_smart_speed_on)
869 data |= E1000_82580_PM_SPD;
870 else if (phy->smart_speed == e1000_smart_speed_off)
871 data &= ~E1000_82580_PM_SPD;
872 }
873
874 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
875 return E1000_SUCCESS;
876}
877
892s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
893{
894 struct e1000_phy_info *phy = &hw->phy;
895 u32 data;
896
897 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
898
899 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
900
901 if (!active) {
902 data &= ~E1000_82580_PM_D3_LPLU;
903 /*
904 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
905 * during Dx states where the power conservation is most
906 * important. During driver activity we should enable
907 * SmartSpeed, so performance is maintained.
908 */
909 if (phy->smart_speed == e1000_smart_speed_on)
910 data |= E1000_82580_PM_SPD;
911 else if (phy->smart_speed == e1000_smart_speed_off)
912 data &= ~E1000_82580_PM_SPD;
913 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
914 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
915 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
916 data |= E1000_82580_PM_D3_LPLU;
917 /* When LPLU is enabled, we should disable SmartSpeed */
918 data &= ~E1000_82580_PM_SPD;
919 }
920
921 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
922 return E1000_SUCCESS;
923}
924
934static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
935{
936 s32 ret_val = E1000_SUCCESS;
937
938 DEBUGFUNC("e1000_acquire_nvm_82575");
939
940 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
941 if (ret_val)
942 goto out;
943
944 /*
945 * Check if there is some access
946 * error this access may hook on
947 */
948 if (hw->mac.type == e1000_i350) {
949 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
950 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
951 E1000_EECD_TIMEOUT)) {
952 /* Clear all access error flags */
953 E1000_WRITE_REG(hw, E1000_EECD, eecd |
954 E1000_EECD_ERROR_CLR);
955 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
956 }
957 }
958
959 if (hw->mac.type == e1000_82580) {
960 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
961 if (eecd & E1000_EECD_BLOCKED) {
962 /* Clear access error flag */
963 E1000_WRITE_REG(hw, E1000_EECD, eecd |
964 E1000_EECD_BLOCKED);
965 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
966 }
967 }
968
969 ret_val = e1000_acquire_nvm_generic(hw);
970 if (ret_val)
971 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
972
973out:
974 return ret_val;
975}
976
984static void e1000_release_nvm_82575(struct e1000_hw *hw)
985{
986 DEBUGFUNC("e1000_release_nvm_82575");
987
988 e1000_release_nvm_generic(hw);
989
990 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
991}
992
1003static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1004{
1005 s32 timeout = PHY_CFG_TIMEOUT;
1006 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1007
1008 DEBUGFUNC("e1000_get_cfg_done_82575");
1009
1010 if (hw->bus.func == E1000_FUNC_1)
1011 mask = E1000_NVM_CFG_DONE_PORT_1;
1012 else if (hw->bus.func == E1000_FUNC_2)
1013 mask = E1000_NVM_CFG_DONE_PORT_2;
1014 else if (hw->bus.func == E1000_FUNC_3)
1015 mask = E1000_NVM_CFG_DONE_PORT_3;
1016 while (timeout) {
1017 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1018 break;
1019 msec_delay(1);
1020 timeout--;
1021 }
1022 if (!timeout)
1023 DEBUGOUT("MNG configuration cycle has not completed.\n");
1024
1025 /* If EEPROM is not marked present, init the PHY manually */
1026 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1027 (hw->phy.type == e1000_phy_igp_3))
1028 e1000_phy_init_script_igp3(hw);
1029
1030 return E1000_SUCCESS;
1031}
1032
1043static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1044 u16 *duplex)
1045{
1046 s32 ret_val;
1047
1048 DEBUGFUNC("e1000_get_link_up_info_82575");
1049
1050 if (hw->phy.media_type != e1000_media_type_copper)
1051 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1052 duplex);
1053 else
1054 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1055 duplex);
1056
1057 return ret_val;
1058}
1059
1067static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1068{
1069 s32 ret_val;
1070 u16 speed, duplex;
1071
1072 DEBUGFUNC("e1000_check_for_link_82575");
1073
1074 if (hw->phy.media_type != e1000_media_type_copper) {
1075 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1076 &duplex);
1077 /*
1078 * Use this flag to determine if link needs to be checked or
1079 * not. If we have link clear the flag so that we do not
1080 * continue to check for link.
1081 */
1082 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1083
1084 /*
1085 * Configure Flow Control now that Auto-Neg has completed.
1086 * First, we need to restore the desired flow control
1087 * settings because we may have had to re-autoneg with a
1088 * different link partner.
1089 */
1090 ret_val = e1000_config_fc_after_link_up_generic(hw);
1091 if (ret_val)
1092 DEBUGOUT("Error configuring flow control\n");
1093 } else {
1094 ret_val = e1000_check_for_copper_link_generic(hw);
1095 }
1096
1097 return ret_val;
1098}
1099
1106static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1107{
1108 struct e1000_phy_info *phy = &hw->phy;
1109 s32 ret_val;
1110 u16 data;
1111 u8 port = 0;
1112
1113 DEBUGFUNC("e1000_check_for_link_media_swap");
1114
1115 /* Check for copper. */
1116 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1117 if (ret_val)
1118 return ret_val;
1119
1120 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1121 if (ret_val)
1122 return ret_val;
1123
1124 if (data & E1000_M88E1112_STATUS_LINK)
1125 port = E1000_MEDIA_PORT_COPPER;
1126
1127 /* Check for other. */
1128 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1129 if (ret_val)
1130 return ret_val;
1131
1132 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1133 if (ret_val)
1134 return ret_val;
1135
1136 if (data & E1000_M88E1112_STATUS_LINK)
1137 port = E1000_MEDIA_PORT_OTHER;
1138
1139 /* Determine if a swap needs to happen. */
1140 if (port && (hw->dev_spec._82575.media_port != port)) {
1141 hw->dev_spec._82575.media_port = port;
1142 hw->dev_spec._82575.media_changed = true;
1143 }
1144
1145 if (port == E1000_MEDIA_PORT_COPPER) {
1146 /* reset page to 0 */
1147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1148 if (ret_val)
1149 return ret_val;
1150 e1000_check_for_link_82575(hw);
1151 } else {
1152 e1000_check_for_link_82575(hw);
1153 /* reset page to 0 */
1154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1155 if (ret_val)
1156 return ret_val;
1157 }
1158
1159 return E1000_SUCCESS;
1160}
1161
1166static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1167{
1168 u32 reg;
1169
1170 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1171
1172 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1173 !e1000_sgmii_active_82575(hw))
1174 return;
1175
1176 /* Enable PCS to turn on link */
1177 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1178 reg |= E1000_PCS_CFG_PCS_EN;
1179 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1180
1181 /* Power up the laser */
1182 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1183 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1184 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1185
1186 /* flush the write to verify completion */
1187 E1000_WRITE_FLUSH(hw);
1188 msec_delay(1);
1189}
1190
1200static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1201 u16 *speed, u16 *duplex)
1202{
1203 struct e1000_mac_info *mac = &hw->mac;
1204 u32 pcs;
1205 u32 status;
1206
1207 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1208
1209 /*
1210 * Read the PCS Status register for link state. For non-copper mode,
1211 * the status register is not accurate. The PCS status register is
1212 * used instead.
1213 */
1214 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1215
1216 /*
1217 * The link up bit determines when link is up on autoneg.
1218 */
1219 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1220 mac->serdes_has_link = true;
1221
1222 /* Detect and store PCS speed */
1223 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1224 *speed = SPEED_1000;
1225 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1226 *speed = SPEED_100;
1227 else
1228 *speed = SPEED_10;
1229
1230 /* Detect and store PCS duplex */
1231 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1232 *duplex = FULL_DUPLEX;
1233 else
1234 *duplex = HALF_DUPLEX;
1235
1236 /* Check if it is an I354 2.5Gb backplane connection. */
1237 if (mac->type == e1000_i354) {
1238 status = E1000_READ_REG(hw, E1000_STATUS);
1239 if ((status & E1000_STATUS_2P5_SKU) &&
1240 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1241 *speed = SPEED_2500;
1242 *duplex = FULL_DUPLEX;
1243 DEBUGOUT("2500 Mbs, ");
1244 DEBUGOUT("Full Duplex\n");
1245 }
1246 }
1247
1248 } else {
1249 mac->serdes_has_link = false;
1250 *speed = 0;
1251 *duplex = 0;
1252 }
1253
1254 return E1000_SUCCESS;
1255}
1256
1264void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1265{
1266 u32 reg;
1267
1268 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1269
1270 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1271 !e1000_sgmii_active_82575(hw))
1272 return;
1273
1274 if (!e1000_enable_mng_pass_thru(hw)) {
1275 /* Disable PCS to turn off link */
1276 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1277 reg &= ~E1000_PCS_CFG_PCS_EN;
1278 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1279
1280 /* shutdown the laser */
1281 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1282 reg |= E1000_CTRL_EXT_SDP3_DATA;
1283 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1284
1285 /* flush the write to verify completion */
1286 E1000_WRITE_FLUSH(hw);
1287 msec_delay(1);
1288 }
1289
1290 return;
1291}
1292
1299static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1300{
1301 u32 ctrl;
1302 s32 ret_val;
1303
1304 DEBUGFUNC("e1000_reset_hw_82575");
1305
1306 /*
1307 * Prevent the PCI-E bus from sticking if there is no TLP connection
1308 * on the last TLP read/write transaction when MAC is reset.
1309 */
1310 ret_val = e1000_disable_pcie_master_generic(hw);
1311 if (ret_val)
1312 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1313
1314 /* set the completion timeout for interface */
1315 ret_val = e1000_set_pcie_completion_timeout(hw);
1316 if (ret_val)
1317 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1318
1319 DEBUGOUT("Masking off all interrupts\n");
1320 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1321
1322 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1323 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1324 E1000_WRITE_FLUSH(hw);
1325
1326 msec_delay(10);
1327
1328 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1329
1330 DEBUGOUT("Issuing a global reset to MAC\n");
1331 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1332
1333 ret_val = e1000_get_auto_rd_done_generic(hw);
1334 if (ret_val) {
1335 /*
1336 * When auto config read does not complete, do not
1337 * return with an error. This can happen in situations
1338 * where there is no eeprom and prevents getting link.
1339 */
1340 DEBUGOUT("Auto Read Done did not complete\n");
1341 }
1342
1343 /* If EEPROM is not present, run manual init scripts */
1344 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1345 e1000_reset_init_script_82575(hw);
1346
1347 /* Clear any pending interrupt events. */
1348 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1349 E1000_READ_REG(hw, E1000_ICR);
1350
1351 /* Install any alternate MAC address into RAR0 */
1352 ret_val = e1000_check_alt_mac_addr_generic(hw);
1353
1354 return ret_val;
1355}
1356
1363static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1364{
1365 struct e1000_mac_info *mac = &hw->mac;
1366 s32 ret_val;
1367
1368 DEBUGFUNC("e1000_init_hw_82575");
1369
1370 /* Initialize identification LED */
1371 ret_val = mac->ops.id_led_init(hw);
1372 if (ret_val) {
1373 DEBUGOUT("Error initializing identification LED\n");
1374 /* This is not fatal and we should not stop init due to this */
1375 }
1376
1377 /* Disabling VLAN filtering */
1378 DEBUGOUT("Initializing the IEEE VLAN\n");
1379 mac->ops.clear_vfta(hw);
1380
1381 ret_val = e1000_init_hw_base(hw);
1382
1383 /* Set the default MTU size */
1384 hw->dev_spec._82575.mtu = 1500;
1385
1386 /* Clear all of the statistics registers (clear on read). It is
1387 * important that we do this after we have tried to establish link
1388 * because the symbol error count will increment wildly if there
1389 * is no link.
1390 */
1391 e1000_clear_hw_cntrs_82575(hw);
1392
1393 return ret_val;
1394}
1403static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1404{
1405 u32 phpm_reg;
1406 u32 ctrl;
1407 s32 ret_val;
1408
1409 DEBUGFUNC("e1000_setup_copper_link_82575");
1410
1411 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1412 ctrl |= E1000_CTRL_SLU;
1413 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1414 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1415
1416 /* Clear Go Link Disconnect bit on supported devices */
1417 switch (hw->mac.type) {
1418 case e1000_82580:
1419 case e1000_i350:
1420 case e1000_i210:
1421 case e1000_i211:
1422 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1423 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1424 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1425 break;
1426 default:
1427 break;
1428 }
1429
1430 ret_val = e1000_setup_serdes_link_82575(hw);
1431 if (ret_val)
1432 goto out;
1433
1434 if (e1000_sgmii_active_82575(hw)) {
1435 /* allow time for SFP cage time to power up phy */
1436 msec_delay(300);
1437
1438 ret_val = hw->phy.ops.reset(hw);
1439 if (ret_val) {
1440 DEBUGOUT("Error resetting the PHY.\n");
1441 goto out;
1442 }
1443 }
1444 switch (hw->phy.type) {
1445 case e1000_phy_i210:
1446 /* FALLTHROUGH */
1447 case e1000_phy_m88:
1448 switch (hw->phy.id) {
1449 case I347AT4_E_PHY_ID:
1450 /* FALLTHROUGH */
1451 case M88E1112_E_PHY_ID:
1452 /* FALLTHROUGH */
1453 case M88E1340M_E_PHY_ID:
1454 /* FALLTHROUGH */
1455 case M88E1543_E_PHY_ID:
1456 /* FALLTHROUGH */
1457 case M88E1512_E_PHY_ID:
1458 /* FALLTHROUGH */
1459 case I210_I_PHY_ID:
1460 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1461 break;
1462 default:
1463 ret_val = e1000_copper_link_setup_m88(hw);
1464 break;
1465 }
1466 break;
1467 case e1000_phy_igp_3:
1468 ret_val = e1000_copper_link_setup_igp(hw);
1469 break;
1470 case e1000_phy_82580:
1471 ret_val = e1000_copper_link_setup_82577(hw);
1472 break;
1473 default:
1474 ret_val = -E1000_ERR_PHY;
1475 break;
1476 }
1477
1478 if (ret_val)
1479 goto out;
1480
1481 ret_val = e1000_setup_copper_link_generic(hw);
1482out:
1483 return ret_val;
1484}
1485
1495static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1496{
1497 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1498 bool pcs_autoneg;
1499 s32 ret_val = E1000_SUCCESS;
1500 u16 data;
1501
1502 DEBUGFUNC("e1000_setup_serdes_link_82575");
1503
1504 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1505 !e1000_sgmii_active_82575(hw))
1506 return ret_val;
1507
1508 /*
1509 * On the 82575, SerDes loopback mode persists until it is
1510 * explicitly turned off or a power cycle is performed. A read to
1511 * the register does not indicate its status. Therefore, we ensure
1512 * loopback mode is disabled during initialization.
1513 */
1514 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1515
1516 /* power on the sfp cage if present */
1517 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1518 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1519 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1520
1521 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1522 ctrl_reg |= E1000_CTRL_SLU;
1523
1524 /* set both sw defined pins on 82575/82576*/
1525 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1526 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1527
1528 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1529
1530 /* default pcs_autoneg to the same setting as mac autoneg */
1531 pcs_autoneg = hw->mac.autoneg;
1532
1533 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1534 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1535 /* sgmii mode lets the phy handle forcing speed/duplex */
1536 pcs_autoneg = true;
1537 /* autoneg time out should be disabled for SGMII mode */
1538 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1539 break;
1540 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1541 /* disable PCS autoneg and support parallel detect only */
1542 pcs_autoneg = false;
1543 /* FALLTHROUGH */
1544 default:
1545 if (hw->mac.type == e1000_82575 ||
1546 hw->mac.type == e1000_82576) {
1547 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1548 if (ret_val) {
1549 DEBUGOUT("NVM Read Error\n");
1550 return ret_val;
1551 }
1552
1553 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1554 pcs_autoneg = false;
1555 }
1556
1557 /*
1558 * non-SGMII modes only supports a speed of 1000/Full for the
1559 * link so it is best to just force the MAC and let the pcs
1560 * link either autoneg or be forced to 1000/Full
1561 */
1562 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1563 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1564
1565 /* set speed of 1000/Full if speed/duplex is forced */
1566 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1567 break;
1568 }
1569
1570 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1571
1572 /*
1573 * New SerDes mode allows for forcing speed or autonegotiating speed
1574 * at 1gb. Autoneg should be default set by most drivers. This is the
1575 * mode that will be compatible with older link partners and switches.
1576 * However, both are supported by the hardware and some drivers/tools.
1577 */
1578 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1579 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1580
1581 if (pcs_autoneg) {
1582 /* Set PCS register for autoneg */
1583 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1584 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1585
1586 /* Disable force flow control for autoneg */
1587 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1588
1589 /* Configure flow control advertisement for autoneg */
1590 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1591 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1592
1593 switch (hw->fc.requested_mode) {
1594 case e1000_fc_full:
1595 case e1000_fc_rx_pause:
1596 anadv_reg |= E1000_TXCW_ASM_DIR;
1597 anadv_reg |= E1000_TXCW_PAUSE;
1598 break;
1599 case e1000_fc_tx_pause:
1600 anadv_reg |= E1000_TXCW_ASM_DIR;
1601 break;
1602 default:
1603 break;
1604 }
1605
1606 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1607
1608 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1609 } else {
1610 /* Set PCS register for forced link */
1611 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1612
1613 /* Force flow control for forced link */
1614 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1615
1616 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1617 }
1618
1619 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1620
1621 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1622 e1000_force_mac_fc_generic(hw);
1623
1624 return ret_val;
1625}
1626
1638static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1639{
1640 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1641 s32 ret_val = E1000_SUCCESS;
1642 u32 ctrl_ext = 0;
1643 u32 link_mode = 0;
1644
1645 /* Set internal phy as default */
1646 dev_spec->sgmii_active = false;
1647 dev_spec->module_plugged = false;
1648
1649 /* Get CSR setting */
1650 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1651
1652 /* extract link mode setting */
1653 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1654
1655 switch (link_mode) {
1656 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1657 hw->phy.media_type = e1000_media_type_internal_serdes;
1658 break;
1659 case E1000_CTRL_EXT_LINK_MODE_GMII:
1660 hw->phy.media_type = e1000_media_type_copper;
1661 break;
1662 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1663 /* Get phy control interface type set (MDIO vs. I2C)*/
1664 if (e1000_sgmii_uses_mdio_82575(hw)) {
1665 hw->phy.media_type = e1000_media_type_copper;
1666 dev_spec->sgmii_active = true;
1667 break;
1668 }
1669 /* fall through for I2C based SGMII */
1670 /* FALLTHROUGH */
1671 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1672 /* read media type from SFP EEPROM */
1673 ret_val = e1000_set_sfp_media_type_82575(hw);
1674 if ((ret_val != E1000_SUCCESS) ||
1675 (hw->phy.media_type == e1000_media_type_unknown)) {
1676 /*
1677 * If media type was not identified then return media
1678 * type defined by the CTRL_EXT settings.
1679 */
1680 hw->phy.media_type = e1000_media_type_internal_serdes;
1681
1682 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1683 hw->phy.media_type = e1000_media_type_copper;
1684 dev_spec->sgmii_active = true;
1685 }
1686
1687 break;
1688 }
1689
1690 /* do not change link mode for 100BaseFX */
1691 if (dev_spec->eth_flags.e100_base_fx)
1692 break;
1693
1694 /* change current link mode setting */
1695 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1696
1697 if (hw->phy.media_type == e1000_media_type_copper)
1698 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1699 else
1700 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1701
1702 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1703
1704 break;
1705 }
1706
1707 return ret_val;
1708}
1709
1717static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1718{
1719 s32 ret_val = E1000_ERR_CONFIG;
1720 u32 ctrl_ext = 0;
1721 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1722 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1723 u8 tranceiver_type = 0;
1724 s32 timeout = 3;
1725
1726 /* Turn I2C interface ON and power on sfp cage */
1727 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1728 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1729 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1730
1731 E1000_WRITE_FLUSH(hw);
1732
1733 /* Read SFP module data */
1734 while (timeout) {
1735 ret_val = e1000_read_sfp_data_byte(hw,
1736 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1737 &tranceiver_type);
1738 if (ret_val == E1000_SUCCESS)
1739 break;
1740 msec_delay(100);
1741 timeout--;
1742 }
1743 if (ret_val != E1000_SUCCESS)
1744 goto out;
1745
1746 ret_val = e1000_read_sfp_data_byte(hw,
1747 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1748 (u8 *)eth_flags);
1749 if (ret_val != E1000_SUCCESS)
1750 goto out;
1751
1752 /* Check if there is some SFP module plugged and powered */
1753 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1754 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1755 dev_spec->module_plugged = true;
1756 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1757 hw->phy.media_type = e1000_media_type_internal_serdes;
1758 } else if (eth_flags->e100_base_fx) {
1759 dev_spec->sgmii_active = true;
1760 hw->phy.media_type = e1000_media_type_internal_serdes;
1761 } else if (eth_flags->e1000_base_t) {
1762 dev_spec->sgmii_active = true;
1763 hw->phy.media_type = e1000_media_type_copper;
1764 } else {
1765 hw->phy.media_type = e1000_media_type_unknown;
1766 DEBUGOUT("PHY module has not been recognized\n");
1767 goto out;
1768 }
1769 } else {
1770 hw->phy.media_type = e1000_media_type_unknown;
1771 }
1772 ret_val = E1000_SUCCESS;
1773out:
1774 /* Restore I2C interface setting */
1775 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1776 return ret_val;
1777}
1778
1787static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1788{
1789 s32 ret_val;
1790
1791 DEBUGFUNC("e1000_valid_led_default_82575");
1792
1793 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1794 if (ret_val) {
1795 DEBUGOUT("NVM Read Error\n");
1796 goto out;
1797 }
1798
1799 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1800 switch (hw->phy.media_type) {
1801 case e1000_media_type_internal_serdes:
1802 *data = ID_LED_DEFAULT_82575_SERDES;
1803 break;
1804 case e1000_media_type_copper:
1805 default:
1806 *data = ID_LED_DEFAULT;
1807 break;
1808 }
1809 }
1810out:
1811 return ret_val;
1812}
1813
1822static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1823{
1824 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1825 return dev_spec->sgmii_active;
1826}
1827
1835s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1836{
1837 DEBUGFUNC("e1000_reset_init_script_82575");
1838
1839 if (hw->mac.type == e1000_82575) {
1840 DEBUGOUT("Running reset init script for 82575\n");
1841 /* SerDes configuration via SERDESCTRL */
1842 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1843 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1844 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1845 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1846
1847 /* CCM configuration via CCMCTL register */
1848 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1849 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1850
1851 /* PCIe lanes configuration */
1852 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1853 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1854 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1855 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1856
1857 /* PCIe PLL Configuration */
1858 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1859 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1860 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1861 }
1862
1863 return E1000_SUCCESS;
1864}
1865
1870static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1871{
1872 s32 ret_val;
1873
1874 DEBUGFUNC("e1000_read_mac_addr_82575");
1875
1876 /*
1877 * If there's an alternate MAC address place it in RAR0
1878 * so that it will override the Si installed default perm
1879 * address.
1880 */
1881 ret_val = e1000_check_alt_mac_addr_generic(hw);
1882 if (ret_val)
1883 goto out;
1884
1885 ret_val = e1000_read_mac_addr_generic(hw);
1886
1887out:
1888 return ret_val;
1889}
1890
1898static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1899{
1900 u32 tctl_ext;
1901
1902 DEBUGFUNC("e1000_config_collision_dist_82575");
1903
1904 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1905
1906 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1907 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1908
1909 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1910 E1000_WRITE_FLUSH(hw);
1911}
1912
1919static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1920{
1921 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1922
1923 e1000_clear_hw_cntrs_base_generic(hw);
1924
1925 E1000_READ_REG(hw, E1000_PRC64);
1926 E1000_READ_REG(hw, E1000_PRC127);
1927 E1000_READ_REG(hw, E1000_PRC255);
1928 E1000_READ_REG(hw, E1000_PRC511);
1929 E1000_READ_REG(hw, E1000_PRC1023);
1930 E1000_READ_REG(hw, E1000_PRC1522);
1931 E1000_READ_REG(hw, E1000_PTC64);
1932 E1000_READ_REG(hw, E1000_PTC127);
1933 E1000_READ_REG(hw, E1000_PTC255);
1934 E1000_READ_REG(hw, E1000_PTC511);
1935 E1000_READ_REG(hw, E1000_PTC1023);
1936 E1000_READ_REG(hw, E1000_PTC1522);
1937
1938 E1000_READ_REG(hw, E1000_ALGNERRC);
1939 E1000_READ_REG(hw, E1000_RXERRC);
1940 E1000_READ_REG(hw, E1000_TNCRS);
1941 E1000_READ_REG(hw, E1000_CEXTERR);
1942 E1000_READ_REG(hw, E1000_TSCTC);
1943 E1000_READ_REG(hw, E1000_TSCTFC);
1944
1945 E1000_READ_REG(hw, E1000_MGTPRC);
1946 E1000_READ_REG(hw, E1000_MGTPDC);
1947 E1000_READ_REG(hw, E1000_MGTPTC);
1948
1949 E1000_READ_REG(hw, E1000_IAC);
1950 E1000_READ_REG(hw, E1000_ICRXOC);
1951
1952 E1000_READ_REG(hw, E1000_ICRXPTC);
1953 E1000_READ_REG(hw, E1000_ICRXATC);
1954 E1000_READ_REG(hw, E1000_ICTXPTC);
1955 E1000_READ_REG(hw, E1000_ICTXATC);
1956 E1000_READ_REG(hw, E1000_ICTXQEC);
1957 E1000_READ_REG(hw, E1000_ICTXQMTC);
1958 E1000_READ_REG(hw, E1000_ICRXDMTC);
1959
1960 E1000_READ_REG(hw, E1000_CBTMPC);
1961 E1000_READ_REG(hw, E1000_HTDPMC);
1962 E1000_READ_REG(hw, E1000_CBRMPC);
1963 E1000_READ_REG(hw, E1000_RPTHC);
1964 E1000_READ_REG(hw, E1000_HGPTC);
1965 E1000_READ_REG(hw, E1000_HTCBDPC);
1966 E1000_READ_REG(hw, E1000_HGORCL);
1967 E1000_READ_REG(hw, E1000_HGORCH);
1968 E1000_READ_REG(hw, E1000_HGOTCL);
1969 E1000_READ_REG(hw, E1000_HGOTCH);
1970 E1000_READ_REG(hw, E1000_LENERRS);
1971
1972 /* This register should not be read in copper configurations */
1973 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1974 e1000_sgmii_active_82575(hw))
1975 E1000_READ_REG(hw, E1000_SCVPC);
1976}
1977
1988static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1989{
1990 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1991 s32 ret_val = E1000_SUCCESS;
1992 u16 pcie_devctl2;
1993
1994 /* only take action if timeout value is defaulted to 0 */
1995 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1996 goto out;
1997
1998 /*
1999 * if capababilities version is type 1 we can write the
2000 * timeout of 10ms to 200ms through the GCR register
2001 */
2002 if (!(gcr & E1000_GCR_CAP_VER2)) {
2003 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2004 goto out;
2005 }
2006
2007 /*
2008 * for version 2 capabilities we need to write the config space
2009 * directly in order to set the completion timeout value for
2010 * 16ms to 55ms
2011 */
2012 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2013 &pcie_devctl2);
2014 if (ret_val)
2015 goto out;
2016
2017 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2018
2019 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2020 &pcie_devctl2);
2021out:
2022 /* disable completion timeout resend */
2023 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2024
2025 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2026 return ret_val;
2027}
2028
2037void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2038{
2039 u32 reg_val, reg_offset;
2040
2041 switch (hw->mac.type) {
2042 case e1000_82576:
2043 reg_offset = E1000_DTXSWC;
2044 break;
2045 case e1000_i350:
2046 case e1000_i354:
2047 reg_offset = E1000_TXSWC;
2048 break;
2049 default:
2050 return;
2051 }
2052
2053 reg_val = E1000_READ_REG(hw, reg_offset);
2054 if (enable) {
2055 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2056 E1000_DTXSWC_VLAN_SPOOF_MASK);
2057 /* The PF can spoof - it has to in order to
2058 * support emulation mode NICs
2059 */
2060 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2061 } else {
2062 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2063 E1000_DTXSWC_VLAN_SPOOF_MASK);
2064 }
2065 E1000_WRITE_REG(hw, reg_offset, reg_val);
2066}
2067
2075void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2076{
2077 u32 dtxswc;
2078
2079 switch (hw->mac.type) {
2080 case e1000_82576:
2081 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2082 if (enable)
2083 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2084 else
2085 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2086 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2087 break;
2088 case e1000_i350:
2089 case e1000_i354:
2090 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2091 if (enable)
2092 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2093 else
2094 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2095 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2096 break;
2097 default:
2098 /* Currently no other hardware supports loopback */
2099 break;
2100 }
2101
2102
2103}
2104
2112void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2113{
2114 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2115
2116 if (enable)
2117 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2118 else
2119 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2120
2121 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2122}
2123
2133static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2134{
2135 s32 ret_val;
2136
2137 DEBUGFUNC("e1000_read_phy_reg_82580");
2138
2139 ret_val = hw->phy.ops.acquire(hw);
2140 if (ret_val)
2141 goto out;
2142
2143 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2144
2145 hw->phy.ops.release(hw);
2146
2147out:
2148 return ret_val;
2149}
2150
2159static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2160{
2161 s32 ret_val;
2162
2163 DEBUGFUNC("e1000_write_phy_reg_82580");
2164
2165 ret_val = hw->phy.ops.acquire(hw);
2166 if (ret_val)
2167 goto out;
2168
2169 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2170
2171 hw->phy.ops.release(hw);
2172
2173out:
2174 return ret_val;
2175}
2176
2185static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2186{
2187 s32 ret_val = E1000_SUCCESS;
2188 u32 mdicnfg;
2189 u16 nvm_data = 0;
2190
2191 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2192
2193 if (hw->mac.type != e1000_82580)
2194 goto out;
2195 if (!e1000_sgmii_active_82575(hw))
2196 goto out;
2197
2198 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2199 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2200 &nvm_data);
2201 if (ret_val) {
2202 DEBUGOUT("NVM Read Error\n");
2203 goto out;
2204 }
2205
2206 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2207 if (nvm_data & NVM_WORD24_EXT_MDIO)
2208 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2209 if (nvm_data & NVM_WORD24_COM_MDIO)
2210 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2211 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2212out:
2213 return ret_val;
2214}
2215
2223static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2224{
2225 s32 ret_val = E1000_SUCCESS;
2226 /* BH SW mailbox bit in SW_FW_SYNC */
2227 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2228 u32 ctrl;
2229 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2230
2231 DEBUGFUNC("e1000_reset_hw_82580");
2232
2233 hw->dev_spec._82575.global_device_reset = false;
2234
2235 /* 82580 does not reliably do global_device_reset due to hw errata */
2236 if (hw->mac.type == e1000_82580)
2237 global_device_reset = false;
2238
2239 /* Get current control state. */
2240 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2241
2242 /*
2243 * Prevent the PCI-E bus from sticking if there is no TLP connection
2244 * on the last TLP read/write transaction when MAC is reset.
2245 */
2246 ret_val = e1000_disable_pcie_master_generic(hw);
2247 if (ret_val)
2248 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2249
2250 DEBUGOUT("Masking off all interrupts\n");
2251 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2252 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2253 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2254 E1000_WRITE_FLUSH(hw);
2255
2256 msec_delay(10);
2257
2258 /* Determine whether or not a global dev reset is requested */
2259 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2260 swmbsw_mask))
2261 global_device_reset = false;
2262
2263 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2264 E1000_STAT_DEV_RST_SET))
2265 ctrl |= E1000_CTRL_DEV_RST;
2266 else
2267 ctrl |= E1000_CTRL_RST;
2268
2269 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2270
2271 switch (hw->device_id) {
2272 case E1000_DEV_ID_DH89XXCC_SGMII:
2273 break;
2274 default:
2275 E1000_WRITE_FLUSH(hw);
2276 break;
2277 }
2278
2279 /* Add delay to insure DEV_RST or RST has time to complete */
2280 msec_delay(5);
2281
2282 ret_val = e1000_get_auto_rd_done_generic(hw);
2283 if (ret_val) {
2284 /*
2285 * When auto config read does not complete, do not
2286 * return with an error. This can happen in situations
2287 * where there is no eeprom and prevents getting link.
2288 */
2289 DEBUGOUT("Auto Read Done did not complete\n");
2290 }
2291
2292 /* clear global device reset status bit */
2293 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2294
2295 /* Clear any pending interrupt events. */
2296 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2297 E1000_READ_REG(hw, E1000_ICR);
2298
2299 ret_val = e1000_reset_mdicnfg_82580(hw);
2300 if (ret_val)
2301 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2302
2303 /* Install any alternate MAC address into RAR0 */
2304 ret_val = e1000_check_alt_mac_addr_generic(hw);
2305
2306 /* Release semaphore */
2307 if (global_device_reset)
2308 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2309
2310 return ret_val;
2311}
2312
2323u16 e1000_rxpbs_adjust_82580(u32 data)
2324{
2325 u16 ret_val = 0;
2326
2327 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2328 ret_val = e1000_82580_rxpbs_table[data];
2329
2330 return ret_val;
2331}
2332
2342s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2343{
2344 s32 ret_val = E1000_SUCCESS;
2345 u16 checksum = 0;
2346 u16 i, nvm_data;
2347
2348 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2349
2350 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2351 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2352 if (ret_val) {
2353 DEBUGOUT("NVM Read Error\n");
2354 goto out;
2355 }
2356 checksum += nvm_data;
2357 }
2358
2359 if (checksum != (u16) NVM_SUM) {
2360 DEBUGOUT("NVM Checksum Invalid\n");
2361 ret_val = -E1000_ERR_NVM;
2362 goto out;
2363 }
2364
2365out:
2366 return ret_val;
2367}
2368
2379s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2380{
2381 s32 ret_val;
2382 u16 checksum = 0;
2383 u16 i, nvm_data;
2384
2385 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2386
2387 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2388 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2389 if (ret_val) {
2390 DEBUGOUT("NVM Read Error while updating checksum.\n");
2391 goto out;
2392 }
2393 checksum += nvm_data;
2394 }
2395 checksum = (u16) NVM_SUM - checksum;
2396 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2397 &checksum);
2398 if (ret_val)
2399 DEBUGOUT("NVM Write Error while updating checksum.\n");
2400
2401out:
2402 return ret_val;
2403}
2404
2413static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2414{
2415 s32 ret_val;
2416 u16 eeprom_regions_count = 1;
2417 u16 j, nvm_data;
2418 u16 nvm_offset;
2419
2420 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2421
2422 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2423 if (ret_val) {
2424 DEBUGOUT("NVM Read Error\n");
2425 goto out;
2426 }
2427
2428 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2429 /* if chekcsums compatibility bit is set validate checksums
2430 * for all 4 ports. */
2431 eeprom_regions_count = 4;
2432 }
2433
2434 for (j = 0; j < eeprom_regions_count; j++) {
2435 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2436 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2437 nvm_offset);
2438 if (ret_val != E1000_SUCCESS)
2439 goto out;
2440 }
2441
2442out:
2443 return ret_val;
2444}
2445
2454static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2455{
2456 s32 ret_val;
2457 u16 j, nvm_data;
2458 u16 nvm_offset;
2459
2460 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2461
2462 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2463 if (ret_val) {
2464 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2465 goto out;
2466 }
2467
2468 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2469 /* set compatibility bit to validate checksums appropriately */
2470 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2471 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2472 &nvm_data);
2473 if (ret_val) {
2474 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2475 goto out;
2476 }
2477 }
2478
2479 for (j = 0; j < 4; j++) {
2480 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2481 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2482 if (ret_val)
2483 goto out;
2484 }
2485
2486out:
2487 return ret_val;
2488}
2489
2498static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2499{
2500 s32 ret_val = E1000_SUCCESS;
2501 u16 j;
2502 u16 nvm_offset;
2503
2504 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2505
2506 for (j = 0; j < 4; j++) {
2507 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2508 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2509 nvm_offset);
2510 if (ret_val != E1000_SUCCESS)
2511 goto out;
2512 }
2513
2514out:
2515 return ret_val;
2516}
2517
2526static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2527{
2528 s32 ret_val = E1000_SUCCESS;
2529 u16 j;
2530 u16 nvm_offset;
2531
2532 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2533
2534 for (j = 0; j < 4; j++) {
2535 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2536 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2537 if (ret_val != E1000_SUCCESS)
2538 goto out;
2539 }
2540
2541out:
2542 return ret_val;
2543}
2544
2552static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2553 u16 *data, bool read)
2554{
2555 s32 ret_val;
2556
2557 DEBUGFUNC("__e1000_access_emi_reg");
2558
2559 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2560 if (ret_val)
2561 return ret_val;
2562
2563 if (read)
2564 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2565 else
2566 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2567
2568 return ret_val;
2569}
2570
2577s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2578{
2579 DEBUGFUNC("e1000_read_emi_reg");
2580
2581 return __e1000_access_emi_reg(hw, addr, data, true);
2582}
2583
2590s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2591{
2592 struct e1000_phy_info *phy = &hw->phy;
2593 s32 ret_val = E1000_SUCCESS;
2594
2595 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2596
2597 /* Check if this is correct PHY. */
2598 if (phy->id != M88E1512_E_PHY_ID)
2599 goto out;
2600
2601 /* Switch to PHY page 0xFF. */
2602 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2603 if (ret_val)
2604 goto out;
2605
2606 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2607 if (ret_val)
2608 goto out;
2609
2610 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2611 if (ret_val)
2612 goto out;
2613
2614 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2615 if (ret_val)
2616 goto out;
2617
2618 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2619 if (ret_val)
2620 goto out;
2621
2622 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2623 if (ret_val)
2624 goto out;
2625
2626 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2627 if (ret_val)
2628 goto out;
2629
2630 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2631 if (ret_val)
2632 goto out;
2633
2634 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2635 if (ret_val)
2636 goto out;
2637
2638 /* Switch to PHY page 0xFB. */
2639 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2640 if (ret_val)
2641 goto out;
2642
2643 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2644 if (ret_val)
2645 goto out;
2646
2647 /* Switch to PHY page 0x12. */
2648 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2649 if (ret_val)
2650 goto out;
2651
2652 /* Change mode to SGMII-to-Copper */
2653 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2654 if (ret_val)
2655 goto out;
2656
2657 /* Return the PHY to page 0. */
2658 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2659 if (ret_val)
2660 goto out;
2661
2662 ret_val = phy->ops.commit(hw);
2663 if (ret_val) {
2664 DEBUGOUT("Error committing the PHY changes\n");
2665 return ret_val;
2666 }
2667
2668 msec_delay(1000);
2669out:
2670 return ret_val;
2671}
2672
2679s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2680{
2681 struct e1000_phy_info *phy = &hw->phy;
2682 s32 ret_val = E1000_SUCCESS;
2683
2684 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2685
2686 /* Check if this is correct PHY. */
2687 if (phy->id != M88E1543_E_PHY_ID)
2688 goto out;
2689
2690 /* Switch to PHY page 0xFF. */
2691 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2692 if (ret_val)
2693 goto out;
2694
2695 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2696 if (ret_val)
2697 goto out;
2698
2699 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2700 if (ret_val)
2701 goto out;
2702
2703 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2704 if (ret_val)
2705 goto out;
2706
2707 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2708 if (ret_val)
2709 goto out;
2710
2711 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2712 if (ret_val)
2713 goto out;
2714
2715 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2716 if (ret_val)
2717 goto out;
2718
2719 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2720 if (ret_val)
2721 goto out;
2722
2723 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2724 if (ret_val)
2725 goto out;
2726
2727 /* Switch to PHY page 0xFB. */
2728 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2729 if (ret_val)
2730 goto out;
2731
2732 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2733 if (ret_val)
2734 goto out;
2735
2736 /* Switch to PHY page 0x12. */
2737 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2738 if (ret_val)
2739 goto out;
2740
2741 /* Change mode to SGMII-to-Copper */
2742 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2743 if (ret_val)
2744 goto out;
2745
2746 /* Switch to PHY page 1. */
2747 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2748 if (ret_val)
2749 goto out;
2750
2751 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2752 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2753 if (ret_val)
2754 goto out;
2755
2756 /* Return the PHY to page 0. */
2757 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2758 if (ret_val)
2759 goto out;
2760
2761 ret_val = phy->ops.commit(hw);
2762 if (ret_val) {
2763 DEBUGOUT("Error committing the PHY changes\n");
2764 return ret_val;
2765 }
2766
2767 msec_delay(1000);
2768out:
2769 return ret_val;
2770}
2771
2781s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2782{
2783 u32 ipcnfg, eeer;
2784
2785 DEBUGFUNC("e1000_set_eee_i350");
2786
2787 if ((hw->mac.type < e1000_i350) ||
2788 (hw->phy.media_type != e1000_media_type_copper))
2789 goto out;
2790 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2791 eeer = E1000_READ_REG(hw, E1000_EEER);
2792
2793 /* enable or disable per user setting */
2794 if (!(hw->dev_spec._82575.eee_disable)) {
2795 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2796
2797 if (adv100M)
2798 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2799 else
2800 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2801
2802 if (adv1G)
2803 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2804 else
2805 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2806
2807 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2808 E1000_EEER_LPI_FC);
2809
2810 /* This bit should not be set in normal operation. */
2811 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2812 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2813 } else {
2814 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2815 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2816 E1000_EEER_LPI_FC);
2817 }
2818 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2819 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2820 E1000_READ_REG(hw, E1000_IPCNFG);
2821 E1000_READ_REG(hw, E1000_EEER);
2822out:
2823
2824 return E1000_SUCCESS;
2825}
2826
2836s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2837{
2838 struct e1000_phy_info *phy = &hw->phy;
2839 s32 ret_val = E1000_SUCCESS;
2840 u16 phy_data;
2841
2842 DEBUGFUNC("e1000_set_eee_i354");
2843
2844 if ((hw->phy.media_type != e1000_media_type_copper) ||
2845 ((phy->id != M88E1543_E_PHY_ID) &&
2846 (phy->id != M88E1512_E_PHY_ID)))
2847 goto out;
2848
2849 if (!hw->dev_spec._82575.eee_disable) {
2850 /* Switch to PHY page 18. */
2851 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2852 if (ret_val)
2853 goto out;
2854
2855 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2856 &phy_data);
2857 if (ret_val)
2858 goto out;
2859
2860 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2861 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2862 phy_data);
2863 if (ret_val)
2864 goto out;
2865
2866 /* Return the PHY to page 0. */
2867 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2868 if (ret_val)
2869 goto out;
2870
2871 /* Turn on EEE advertisement. */
2872 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2873 E1000_EEE_ADV_DEV_I354,
2874 &phy_data);
2875 if (ret_val)
2876 goto out;
2877
2878 if (adv100M)
2879 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2880 else
2881 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2882
2883 if (adv1G)
2884 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2885 else
2886 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2887
2888 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2889 E1000_EEE_ADV_DEV_I354,
2890 phy_data);
2891 } else {
2892 /* Turn off EEE advertisement. */
2893 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2894 E1000_EEE_ADV_DEV_I354,
2895 &phy_data);
2896 if (ret_val)
2897 goto out;
2898
2899 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2900 E1000_EEE_ADV_1000_SUPPORTED);
2901 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2902 E1000_EEE_ADV_DEV_I354,
2903 phy_data);
2904 }
2905
2906out:
2907 return ret_val;
2908}
2909
2918s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2919{
2920 struct e1000_phy_info *phy = &hw->phy;
2921 s32 ret_val = E1000_SUCCESS;
2922 u16 phy_data;
2923
2924 DEBUGFUNC("e1000_get_eee_status_i354");
2925
2926 /* Check if EEE is supported on this device. */
2927 if ((hw->phy.media_type != e1000_media_type_copper) ||
2928 ((phy->id != M88E1543_E_PHY_ID) &&
2929 (phy->id != M88E1512_E_PHY_ID)))
2930 goto out;
2931
2932 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2933 E1000_PCS_STATUS_DEV_I354,
2934 &phy_data);
2935 if (ret_val)
2936 goto out;
2937
2938 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2939 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2940
2941out:
2942 return ret_val;
2943}
2944
2945/* Due to a hw errata, if the host tries to configure the VFTA register
2946 * while performing queries from the BMC or DMA, then the VFTA in some
2947 * cases won't be written.
2948 */
2949
2957void e1000_clear_vfta_i350(struct e1000_hw *hw)
2958{
2959 u32 offset;
2960 int i;
2961
2962 DEBUGFUNC("e1000_clear_vfta_350");
2963
2964 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2965 for (i = 0; i < 10; i++)
2966 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2967
2968 E1000_WRITE_FLUSH(hw);
2969 }
2970}
2971
2981void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2982{
2983 int i;
2984
2985 DEBUGFUNC("e1000_write_vfta_350");
2986
2987 for (i = 0; i < 10; i++)
2988 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2989
2990 E1000_WRITE_FLUSH(hw);
2991}
2992
2993
3001s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3002{
3003 s32 ret_val = E1000_SUCCESS;
3004 u32 ctrl_ext, i2cparams;
3005
3006 DEBUGFUNC("e1000_set_i2c_bb");
3007
3008 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3009 ctrl_ext |= E1000_CTRL_I2C_ENA;
3010 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3011 E1000_WRITE_FLUSH(hw);
3012
3013 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3014 i2cparams |= E1000_I2CBB_EN;
3015 i2cparams |= E1000_I2C_DATA_OE_N;
3016 i2cparams |= E1000_I2C_CLK_OE_N;
3017 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3018 E1000_WRITE_FLUSH(hw);
3019
3020 return ret_val;
3021}
3022
3033s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3034 u8 dev_addr, u8 *data)
3035{
3036 s32 status = E1000_SUCCESS;
3037 u32 max_retry = 10;
3038 u32 retry = 1;
3039 u16 swfw_mask = 0;
3040
3041 bool nack = true;
3042
3043 DEBUGFUNC("e1000_read_i2c_byte_generic");
3044
3045 swfw_mask = E1000_SWFW_PHY0_SM;
3046
3047 do {
3048 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3049 != E1000_SUCCESS) {
3050 status = E1000_ERR_SWFW_SYNC;
3051 goto read_byte_out;
3052 }
3053
3054 e1000_i2c_start(hw);
3055
3056 /* Device Address and write indication */
3057 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3058 if (status != E1000_SUCCESS)
3059 goto fail;
3060
3061 status = e1000_get_i2c_ack(hw);
3062 if (status != E1000_SUCCESS)
3063 goto fail;
3064
3065 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3066 if (status != E1000_SUCCESS)
3067 goto fail;
3068
3069 status = e1000_get_i2c_ack(hw);
3070 if (status != E1000_SUCCESS)
3071 goto fail;
3072
3073 e1000_i2c_start(hw);
3074
3075 /* Device Address and read indication */
3076 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3077 if (status != E1000_SUCCESS)
3078 goto fail;
3079
3080 status = e1000_get_i2c_ack(hw);
3081 if (status != E1000_SUCCESS)
3082 goto fail;
3083
3084 e1000_clock_in_i2c_byte(hw, data);
3085
3086 status = e1000_clock_out_i2c_bit(hw, nack);
3087 if (status != E1000_SUCCESS)
3088 goto fail;
3089
3090 e1000_i2c_stop(hw);
3091 break;
3092
3093fail:
3094 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3095 msec_delay(100);
3096 e1000_i2c_bus_clear(hw);
3097 retry++;
3098 if (retry < max_retry)
3099 DEBUGOUT("I2C byte read error - Retrying.\n");
3100 else
3101 DEBUGOUT("I2C byte read error.\n");
3102
3103 } while (retry < max_retry);
3104
3105 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3106
3107read_byte_out:
3108
3109 return status;
3110}
3111
3122s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3123 u8 dev_addr, u8 data)
3124{
3125 s32 status = E1000_SUCCESS;
3126 u32 max_retry = 1;
3127 u32 retry = 0;
3128 u16 swfw_mask = 0;
3129
3130 DEBUGFUNC("e1000_write_i2c_byte_generic");
3131
3132 swfw_mask = E1000_SWFW_PHY0_SM;
3133
3134 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3135 status = E1000_ERR_SWFW_SYNC;
3136 goto write_byte_out;
3137 }
3138
3139 do {
3140 e1000_i2c_start(hw);
3141
3142 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3143 if (status != E1000_SUCCESS)
3144 goto fail;
3145
3146 status = e1000_get_i2c_ack(hw);
3147 if (status != E1000_SUCCESS)
3148 goto fail;
3149
3150 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3151 if (status != E1000_SUCCESS)
3152 goto fail;
3153
3154 status = e1000_get_i2c_ack(hw);
3155 if (status != E1000_SUCCESS)
3156 goto fail;
3157
3158 status = e1000_clock_out_i2c_byte(hw, data);
3159 if (status != E1000_SUCCESS)
3160 goto fail;
3161
3162 status = e1000_get_i2c_ack(hw);
3163 if (status != E1000_SUCCESS)
3164 goto fail;
3165
3166 e1000_i2c_stop(hw);
3167 break;
3168
3169fail:
3170 e1000_i2c_bus_clear(hw);
3171 retry++;
3172 if (retry < max_retry)
3173 DEBUGOUT("I2C byte write error - Retrying.\n");
3174 else
3175 DEBUGOUT("I2C byte write error.\n");
3176 } while (retry < max_retry);
3177
3178 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3179
3180write_byte_out:
3181
3182 return status;
3183}
3184
3191static void e1000_i2c_start(struct e1000_hw *hw)
3192{
3193 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3194
3195 DEBUGFUNC("e1000_i2c_start");
3196
3197 /* Start condition must begin with data and clock high */
3198 e1000_set_i2c_data(hw, &i2cctl, 1);
3199 e1000_raise_i2c_clk(hw, &i2cctl);
3200
3201 /* Setup time for start condition (4.7us) */
3202 usec_delay(E1000_I2C_T_SU_STA);
3203
3204 e1000_set_i2c_data(hw, &i2cctl, 0);
3205
3206 /* Hold time for start condition (4us) */
3207 usec_delay(E1000_I2C_T_HD_STA);
3208
3209 e1000_lower_i2c_clk(hw, &i2cctl);
3210
3211 /* Minimum low period of clock is 4.7 us */
3212 usec_delay(E1000_I2C_T_LOW);
3213
3214}
3215
3222static void e1000_i2c_stop(struct e1000_hw *hw)
3223{
3224 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3225
3226 DEBUGFUNC("e1000_i2c_stop");
3227
3228 /* Stop condition must begin with data low and clock high */
3229 e1000_set_i2c_data(hw, &i2cctl, 0);
3230 e1000_raise_i2c_clk(hw, &i2cctl);
3231
3232 /* Setup time for stop condition (4us) */
3233 usec_delay(E1000_I2C_T_SU_STO);
3234
3235 e1000_set_i2c_data(hw, &i2cctl, 1);
3236
3237 /* bus free time between stop and start (4.7us)*/
3238 usec_delay(E1000_I2C_T_BUF);
3239}
3240
3248static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3249{
3250 s32 i;
3251 bool bit = 0;
3252
3253 DEBUGFUNC("e1000_clock_in_i2c_byte");
3254
3255 *data = 0;
3256 for (i = 7; i >= 0; i--) {
3257 e1000_clock_in_i2c_bit(hw, &bit);
3258 *data |= bit << i;
3259 }
3260}
3261
3269static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3270{
3271 s32 status = E1000_SUCCESS;
3272 s32 i;
3273 u32 i2cctl;
3274 bool bit = 0;
3275
3276 DEBUGFUNC("e1000_clock_out_i2c_byte");
3277
3278 for (i = 7; i >= 0; i--) {
3279 bit = (data >> i) & 0x1;
3280 status = e1000_clock_out_i2c_bit(hw, bit);
3281
3282 if (status != E1000_SUCCESS)
3283 break;
3284 }
3285
3286 /* Release SDA line (set high) */
3287 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3288
3289 i2cctl |= E1000_I2C_DATA_OE_N;
3290 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3291 E1000_WRITE_FLUSH(hw);
3292
3293 return status;
3294}
3295
3302static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3303{
3304 s32 status = E1000_SUCCESS;
3305 u32 i = 0;
3306 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3307 u32 timeout = 10;
3308 bool ack = true;
3309
3310 DEBUGFUNC("e1000_get_i2c_ack");
3311
3312 e1000_raise_i2c_clk(hw, &i2cctl);
3313
3314 /* Minimum high period of clock is 4us */
3315 usec_delay(E1000_I2C_T_HIGH);
3316
3317 /* Wait until SCL returns high */
3318 for (i = 0; i < timeout; i++) {
3319 usec_delay(1);
3320 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3321 if (i2cctl & E1000_I2C_CLK_IN)
3322 break;
3323 }
3324 if (!(i2cctl & E1000_I2C_CLK_IN))
3325 return E1000_ERR_I2C;
3326
3327 ack = e1000_get_i2c_data(&i2cctl);
3328 if (ack) {
3329 DEBUGOUT("I2C ack was not received.\n");
3330 status = E1000_ERR_I2C;
3331 }
3332
3333 e1000_lower_i2c_clk(hw, &i2cctl);
3334
3335 /* Minimum low period of clock is 4.7 us */
3336 usec_delay(E1000_I2C_T_LOW);
3337
3338 return status;
3339}
3340
3348static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3349{
3350 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3351
3352 DEBUGFUNC("e1000_clock_in_i2c_bit");
3353
3354 e1000_raise_i2c_clk(hw, &i2cctl);
3355
3356 /* Minimum high period of clock is 4us */
3357 usec_delay(E1000_I2C_T_HIGH);
3358
3359 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3360 *data = e1000_get_i2c_data(&i2cctl);
3361
3362 e1000_lower_i2c_clk(hw, &i2cctl);
3363
3364 /* Minimum low period of clock is 4.7 us */
3365 usec_delay(E1000_I2C_T_LOW);
3366}
3367
3375static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3376{
3377 s32 status;
3378 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3379
3380 DEBUGFUNC("e1000_clock_out_i2c_bit");
3381
3382 status = e1000_set_i2c_data(hw, &i2cctl, data);
3383 if (status == E1000_SUCCESS) {
3384 e1000_raise_i2c_clk(hw, &i2cctl);
3385
3386 /* Minimum high period of clock is 4us */
3387 usec_delay(E1000_I2C_T_HIGH);
3388
3389 e1000_lower_i2c_clk(hw, &i2cctl);
3390
3391 /* Minimum low period of clock is 4.7 us.
3392 * This also takes care of the data hold time.
3393 */
3394 usec_delay(E1000_I2C_T_LOW);
3395 } else {
3396 status = E1000_ERR_I2C;
3397 DEBUGOUT1("I2C data was not set to %X\n", data);
3398 }
3399
3400 return status;
3401}
3409static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3410{
3411 DEBUGFUNC("e1000_raise_i2c_clk");
3412
3413 *i2cctl |= E1000_I2C_CLK_OUT;
3414 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3415 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3416 E1000_WRITE_FLUSH(hw);
3417
3418 /* SCL rise time (1000ns) */
3419 usec_delay(E1000_I2C_T_RISE);
3420}
3421
3429static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3430{
3431
3432 DEBUGFUNC("e1000_lower_i2c_clk");
3433
3434 *i2cctl &= ~E1000_I2C_CLK_OUT;
3435 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3436 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3437 E1000_WRITE_FLUSH(hw);
3438
3439 /* SCL fall time (300ns) */
3440 usec_delay(E1000_I2C_T_FALL);
3441}
3442
3451static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3452{
3453 s32 status = E1000_SUCCESS;
3454
3455 DEBUGFUNC("e1000_set_i2c_data");
3456
3457 if (data)
3458 *i2cctl |= E1000_I2C_DATA_OUT;
3459 else
3460 *i2cctl &= ~E1000_I2C_DATA_OUT;
3461
3462 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3463 *i2cctl |= E1000_I2C_CLK_OE_N;
3464 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3465 E1000_WRITE_FLUSH(hw);
3466
3467 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3468 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3469
3470 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3471 if (data != e1000_get_i2c_data(i2cctl)) {
3472 status = E1000_ERR_I2C;
3473 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3474 }
3475
3476 return status;
3477}
3478
3485static bool e1000_get_i2c_data(u32 *i2cctl)
3486{
3487 bool data;
3488
3489 DEBUGFUNC("e1000_get_i2c_data");
3490
3491 if (*i2cctl & E1000_I2C_DATA_IN)
3492 data = 1;
3493 else
3494 data = 0;
3495
3496 return data;
3497}
3498
3506void e1000_i2c_bus_clear(struct e1000_hw *hw)
3507{
3508 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3509 u32 i;
3510
3511 DEBUGFUNC("e1000_i2c_bus_clear");
3512
3513 e1000_i2c_start(hw);
3514
3515 e1000_set_i2c_data(hw, &i2cctl, 1);
3516
3517 for (i = 0; i < 9; i++) {
3518 e1000_raise_i2c_clk(hw, &i2cctl);
3519
3520 /* Min high period of clock is 4us */
3521 usec_delay(E1000_I2C_T_HIGH);
3522
3523 e1000_lower_i2c_clk(hw, &i2cctl);
3524
3525 /* Min low period of clock is 4.7us*/
3526 usec_delay(E1000_I2C_T_LOW);
3527 }
3528
3529 e1000_i2c_start(hw);
3530
3531 /* Put the i2c bus back to default state */
3532 e1000_i2c_stop(hw);
3533}
3534
e1000_get_cfg_done_82575
static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1003
e1000_set_pcie_completion_timeout
static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
Definition: e1000_82575.c:1988
e1000_valid_led_default_82575
static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
Definition: e1000_82575.c:1787
e1000_init_nvm_params_82575
s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:441
e1000_set_d0_lplu_state_82580
static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
Definition: e1000_82575.c:845
e1000_sgmii_active_82575
static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1822
e1000_read_phy_reg_sgmii_82575
static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_82575.c:545
__e1000_access_emi_reg
static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address, u16 *data, bool read)
Definition: e1000_82575.c:2552
e1000_i2c_stop
static void e1000_i2c_stop(struct e1000_hw *hw)
Definition: e1000_82575.c:3222
e1000_reset_hw_82580
static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
Definition: e1000_82575.c:2223
e1000_i2c_bus_clear
void e1000_i2c_bus_clear(struct e1000_hw *hw)
Definition: e1000_82575.c:3506
e1000_vmdq_set_loopback_pf
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
Definition: e1000_82575.c:2075
e1000_get_i2c_ack
static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
Definition: e1000_82575.c:3302
e1000_validate_nvm_checksum_i350
static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
Definition: e1000_82575.c:2498
e1000_rxpbs_adjust_82580
u16 e1000_rxpbs_adjust_82580(u32 data)
Definition: e1000_82575.c:2323
e1000_read_emi_reg
s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
Definition: e1000_82575.c:2577
e1000_power_up_serdes_link_82575
static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1166
E1000_82580_RXPBS_TABLE_SIZE
#define E1000_82580_RXPBS_TABLE_SIZE
Definition: e1000_82575.c:116
e1000_validate_nvm_checksum_with_offset
static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
Definition: e1000_82575.c:2342
e1000_clear_hw_cntrs_82575
static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1919
e1000_init_function_pointers_82575
void e1000_init_function_pointers_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:526
e1000_82580_rxpbs_table
static const u16 e1000_82580_rxpbs_table[]
Definition: e1000_82575.c:114
e1000_i2c_start
static void e1000_i2c_start(struct e1000_hw *hw)
Definition: e1000_82575.c:3191
e1000_set_eee_i350
s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
Definition: e1000_82575.c:2781
e1000_shutdown_serdes_link_82575
static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1264
e1000_get_i2c_data
static bool e1000_get_i2c_data(u32 *i2cctl)
Definition: e1000_82575.c:3485
e1000_release_nvm_82575
static void e1000_release_nvm_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:984
e1000_reset_init_script_82575
s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1835
e1000_clock_in_i2c_bit
static void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
Definition: e1000_82575.c:3348
e1000_vmdq_set_anti_spoofing_pf
void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
Definition: e1000_82575.c:2037
e1000_init_mac_params_82575
static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:324
e1000_set_d0_lplu_state_82575
static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
Definition: e1000_82575.c:759
e1000_update_nvm_checksum_82580
static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
Definition: e1000_82575.c:2454
e1000_clear_vfta_i350
static void e1000_clear_vfta_i350(struct e1000_hw *hw)
Definition: e1000_82575.c:2957
e1000_lower_i2c_clk
static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
Definition: e1000_82575.c:3429
e1000_phy_hw_reset_sgmii_82575
static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:711
e1000_write_phy_reg_82580
static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_82575.c:2159
e1000_write_phy_reg_sgmii_82575
static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_82575.c:578
e1000_reset_hw_82575
static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1299
e1000_setup_copper_link_82575
static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1403
e1000_vmdq_set_replication_pf
void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
Definition: e1000_82575.c:2112
e1000_initialize_M88E1512_phy
s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
Definition: e1000_82575.c:2590
e1000_set_eee_i354
s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
Definition: e1000_82575.c:2836
e1000_check_for_link_82575
static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1067
e1000_write_vfta_i350
void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
Definition: e1000_82575.c:2981
e1000_get_link_up_info_82575
static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex)
Definition: e1000_82575.c:1043
e1000_update_nvm_checksum_i350
static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
Definition: e1000_82575.c:2526
e1000_clock_out_i2c_bit
static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
Definition: e1000_82575.c:3375
e1000_read_i2c_byte_generic
s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data)
Definition: e1000_82575.c:3033
e1000_setup_serdes_link_82575
static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1495
e1000_initialize_M88E1543_phy
s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
Definition: e1000_82575.c:2679
e1000_init_phy_params_82575
static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:159
e1000_set_sfp_media_type_82575
static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1717
e1000_read_phy_reg_82580
static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_82575.c:2133
e1000_validate_nvm_checksum_82580
static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
Definition: e1000_82575.c:2413
e1000_write_i2c_byte_generic
s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr, u8 data)
Definition: e1000_82575.c:3122
e1000_get_phy_id_82575
static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:609
e1000_get_eee_status_i354
s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
Definition: e1000_82575.c:2918
e1000_set_i2c_data
static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
Definition: e1000_82575.c:3451
e1000_acquire_nvm_82575
static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:934
e1000_set_i2c_bb
s32 e1000_set_i2c_bb(struct e1000_hw *hw)
Definition: e1000_82575.c:3001
e1000_check_for_link_media_swap
static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
Definition: e1000_82575.c:1106
e1000_clock_out_i2c_byte
static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
Definition: e1000_82575.c:3269
e1000_raise_i2c_clk
static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
Definition: e1000_82575.c:3409
e1000_set_d3_lplu_state_82580
static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
Definition: e1000_82575.c:892
e1000_reset_mdicnfg_82580
static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
Definition: e1000_82575.c:2185
e1000_init_hw_82575
static s32 e1000_init_hw_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1363
e1000_get_pcs_speed_and_duplex_82575
static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex)
Definition: e1000_82575.c:1200
e1000_get_media_type_82575
static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1638
e1000_config_collision_dist_82575
static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1898
e1000_sgmii_uses_mdio_82575
static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:128
e1000_read_mac_addr_82575
static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
Definition: e1000_82575.c:1870
e1000_update_nvm_checksum_with_offset
static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
Definition: e1000_82575.c:2379
e1000_clock_in_i2c_byte
static void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
Definition: e1000_82575.c:3248
MAX_NUM_VFS
#define MAX_NUM_VFS
Definition: e1000_82575.h:319
E1000_RAR_ENTRIES_82575
#define E1000_RAR_ENTRIES_82575
Definition: e1000_82575.h:53
E1000_I2C_T_LOW
#define E1000_I2C_T_LOW
Definition: e1000_82575.h:420
E1000_DTXSWC_MAC_SPOOF_MASK
#define E1000_DTXSWC_MAC_SPOOF_MASK
Definition: e1000_82575.h:321
E1000_I2C_T_FALL
#define E1000_I2C_T_FALL
Definition: e1000_82575.h:426
E1000_RAR_ENTRIES_82576
#define E1000_RAR_ENTRIES_82576
Definition: e1000_82575.h:54
ID_LED_DEFAULT_82575_SERDES
#define ID_LED_DEFAULT_82575_SERDES
Definition: e1000_82575.h:39
E1000_DTXSWC_VMDQ_LOOPBACK_EN
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN
Definition: e1000_82575.h:326
E1000_I2C_T_SU_DATA
#define E1000_I2C_T_SU_DATA
Definition: e1000_82575.h:424
E1000_STAT_DEV_RST_SET
#define E1000_STAT_DEV_RST_SET
Definition: e1000_82575.h:58
E1000_DTXSWC_VLAN_SPOOF_MASK
#define E1000_DTXSWC_VLAN_SPOOF_MASK
Definition: e1000_82575.h:322
E1000_I2C_T_BUF
#define E1000_I2C_T_BUF
Definition: e1000_82575.h:428
E1000_I2C_T_RISE
#define E1000_I2C_T_RISE
Definition: e1000_82575.h:425
E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT
#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT
Definition: e1000_82575.h:385
E1000_SW_SYNCH_MB
#define E1000_SW_SYNCH_MB
Definition: e1000_82575.h:57
E1000_TCTL_EXT_COLD_SHIFT
#define E1000_TCTL_EXT_COLD_SHIFT
Definition: e1000_82575.h:377
E1000_RAR_ENTRIES_82580
#define E1000_RAR_ENTRIES_82580
Definition: e1000_82575.h:55
E1000_I2C_T_SU_STO
#define E1000_I2C_T_SU_STO
Definition: e1000_82575.h:427
E1000_RAR_ENTRIES_I350
#define E1000_RAR_ENTRIES_I350
Definition: e1000_82575.h:56
E1000_I2C_T_HIGH
#define E1000_I2C_T_HIGH
Definition: e1000_82575.h:421
E1000_VT_CTL_VM_REPL_EN
#define E1000_VT_CTL_VM_REPL_EN
Definition: e1000_82575.h:335
E1000_I2C_T_HD_STA
#define E1000_I2C_T_HD_STA
Definition: e1000_82575.h:419
E1000_I2C_T_SU_STA
#define E1000_I2C_T_SU_STA
Definition: e1000_82575.h:422
e1000_api.h
e1000_init_hw_base
s32 e1000_init_hw_base(struct e1000_hw *hw)
Definition: e1000_base.c:92
e1000_acquire_phy_base
s32 e1000_acquire_phy_base(struct e1000_hw *hw)
Definition: e1000_base.c:48
e1000_power_down_phy_copper_base
void e1000_power_down_phy_copper_base(struct e1000_hw *hw)
Definition: e1000_base.c:133
e1000_release_phy_base
void e1000_release_phy_base(struct e1000_hw *hw)
Definition: e1000_base.c:70
ID_LED_RESERVED_0000
#define ID_LED_RESERVED_0000
Definition: e1000_defines.h:1213
E1000_EEER_RX_LPI_EN
#define E1000_EEER_RX_LPI_EN
Definition: e1000_defines.h:867
E1000_EEE_ADV_1000_SUPPORTED
#define E1000_EEE_ADV_1000_SUPPORTED
Definition: e1000_defines.h:881
E1000_TXCW_ASM_DIR
#define E1000_TXCW_ASM_DIR
Definition: e1000_defines.h:751
E1000_M88E1112_STATUS
#define E1000_M88E1112_STATUS
Definition: e1000_defines.h:855
PCIE_DEVICE_CONTROL2
#define PCIE_DEVICE_CONTROL2
Definition: e1000_defines.h:1239
E1000_M88E1512_CFG_REG_3
#define E1000_M88E1512_CFG_REG_3
Definition: e1000_defines.h:888
E1000_PCS_LSTS_DUPLEX_FULL
#define E1000_PCS_LSTS_DUPLEX_FULL
Definition: e1000_defines.h:320
E1000_ERR_PHY
#define E1000_ERR_PHY
Definition: e1000_defines.h:711
E1000_GCR_CMPL_TMOUT_10ms
#define E1000_GCR_CMPL_TMOUT_10ms
Definition: e1000_defines.h:901
E1000_EEER_LPI_FC
#define E1000_EEER_LPI_FC
Definition: e1000_defines.h:868
E1000_I2CCMD_SFP_DATA_ADDR
#define E1000_I2CCMD_SFP_DATA_ADDR(a)
Definition: e1000_defines.h:105
E1000_M88E1543_EEE_CTRL_1
#define E1000_M88E1543_EEE_CTRL_1
Definition: e1000_defines.h:875
E1000_EEE_ADV_100_SUPPORTED
#define E1000_EEE_ADV_100_SUPPORTED
Definition: e1000_defines.h:880
E1000_CTRL_EXT_LINK_MODE_GMII
#define E1000_CTRL_EXT_LINK_MODE_GMII
Definition: e1000_defines.h:89
E1000_ERR_PARAM
#define E1000_ERR_PARAM
Definition: e1000_defines.h:713
E1000_NVM_CFG_DONE_PORT_3
#define E1000_NVM_CFG_DONE_PORT_3
Definition: e1000_defines.h:1151
E1000_PCS_STATUS_ADDR_I354
#define E1000_PCS_STATUS_ADDR_I354
Definition: e1000_defines.h:883
E1000_CTRL_DEV_RST
#define E1000_CTRL_DEV_RST
Definition: e1000_defines.h:284
E1000_MDIC_PHY_MASK
#define E1000_MDIC_PHY_MASK
Definition: e1000_defines.h:1414
E1000_PCS_LCTL_FSD
#define E1000_PCS_LCTL_FSD
Definition: e1000_defines.h:309
E1000_MDIC_DEST
#define E1000_MDIC_DEST
Definition: e1000_defines.h:1420
E1000_EECD_ABORT
#define E1000_EECD_ABORT
Definition: e1000_defines.h:1043
E1000_PCS_LSTS_LINK_OK
#define E1000_PCS_LSTS_LINK_OK
Definition: e1000_defines.h:317
E1000_EEE_ADV_ADDR_I354
#define E1000_EEE_ADV_ADDR_I354
Definition: e1000_defines.h:879
E1000_PCS_LCTL_AN_TIMEOUT
#define E1000_PCS_LCTL_AN_TIMEOUT
Definition: e1000_defines.h:314
M88_VENDOR
#define M88_VENDOR
Definition: e1000_defines.h:1289
ID_LED_DEFAULT
#define ID_LED_DEFAULT
Definition: e1000_defines.h:1215
E1000_CTRL_EXT_LINK_MODE_SGMII
#define E1000_CTRL_EXT_LINK_MODE_SGMII
Definition: e1000_defines.h:91
E1000_M88E1112_AUTO_COPPER_SGMII
#define E1000_M88E1112_AUTO_COPPER_SGMII
Definition: e1000_defines.h:848
M88E1111_I_PHY_ID
#define M88E1111_I_PHY_ID
Definition: e1000_defines.h:1268
SPEED_100
#define SPEED_100
Definition: e1000_defines.h:352
E1000_M88E1543_FIBER_CTRL
#define E1000_M88E1543_FIBER_CTRL
Definition: e1000_defines.h:877
E1000_CTRL_FRCSPD
#define E1000_CTRL_FRCSPD
Definition: e1000_defines.h:270
E1000_MDICNFG_PHY_MASK
#define E1000_MDICNFG_PHY_MASK
Definition: e1000_defines.h:843
NVM_WORD_SIZE_BASE_SHIFT
#define NVM_WORD_SIZE_BASE_SHIFT
Definition: e1000_defines.h:1191
E1000_MDICNFG_COM_MDIO
#define E1000_MDICNFG_COM_MDIO
Definition: e1000_defines.h:842
E1000_M88E1112_MAC_CTRL_1
#define E1000_M88E1112_MAC_CTRL_1
Definition: e1000_defines.h:851
E1000_EEE_ADV_DEV_I354
#define E1000_EEE_ADV_DEV_I354
Definition: e1000_defines.h:878
E1000_PCS_STATUS_DEV_I354
#define E1000_PCS_STATUS_DEV_I354
Definition: e1000_defines.h:882
I347AT4_E_PHY_ID
#define I347AT4_E_PHY_ID
Definition: e1000_defines.h:1272
E1000_M88E1112_PAGE_ADDR
#define E1000_M88E1112_PAGE_ADDR
Definition: e1000_defines.h:854
E1000_ALL_SPEED_DUPLEX
#define E1000_ALL_SPEED_DUPLEX
Definition: e1000_defines.h:368
SPEED_1000
#define SPEED_1000
Definition: e1000_defines.h:353
E1000_MDICNFG_PHY_SHIFT
#define E1000_MDICNFG_PHY_SHIFT
Definition: e1000_defines.h:844
E1000_CTRL_FD
#define E1000_CTRL_FD
Definition: e1000_defines.h:259
E1000_TCTL_PSP
#define E1000_TCTL_PSP
Definition: e1000_defines.h:419
E1000_MAX_SGMII_PHY_REG_ADDR
#define E1000_MAX_SGMII_PHY_REG_ADDR
Definition: e1000_defines.h:107
E1000_STATUS_2P5_SKU_OVER
#define E1000_STATUS_2P5_SKU_OVER
Definition: e1000_defines.h:341
E1000_EEE_SU_LPI_CLK_STP
#define E1000_EEE_SU_LPI_CLK_STP
Definition: e1000_defines.h:890
E1000_GCR_CAP_VER2
#define E1000_GCR_CAP_VER2
Definition: e1000_defines.h:903
M88E1112_E_PHY_ID
#define M88E1112_E_PHY_ID
Definition: e1000_defines.h:1271
SPEED_2500
#define SPEED_2500
Definition: e1000_defines.h:354
PHY_ID1
#define PHY_ID1
Definition: e1000_defines.h:1020
HALF_DUPLEX
#define HALF_DUPLEX
Definition: e1000_defines.h:355
E1000_CTRL_SLU
#define E1000_CTRL_SLU
Definition: e1000_defines.h:264
E1000_NVM_CFG_DONE_PORT_2
#define E1000_NVM_CFG_DONE_PORT_2
Definition: e1000_defines.h:1150
PCIE_DEVICE_CONTROL2_16ms
#define PCIE_DEVICE_CONTROL2_16ms
Definition: e1000_defines.h:1254
E1000_ALL_10_SPEED
#define E1000_ALL_10_SPEED
Definition: e1000_defines.h:375
NVM_WORD24_COM_MDIO
#define NVM_WORD24_COM_MDIO
Definition: e1000_defines.h:1156
E1000_EECD_BLOCKED
#define E1000_EECD_BLOCKED
Definition: e1000_defines.h:1042
M88E1543_E_PHY_ID
#define M88E1543_E_PHY_ID
Definition: e1000_defines.h:1269
E1000_EECD_SIZE_EX_SHIFT
#define E1000_EECD_SIZE_EX_SHIFT
Definition: e1000_defines.h:1052
E1000_M88E1112_MAC_CTRL_1_MODE_MASK
#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK
Definition: e1000_defines.h:852
E1000_PCS_LSTS_SPEED_100
#define E1000_PCS_LSTS_SPEED_100
Definition: e1000_defines.h:318
E1000_EECD_SIZE_EX_MASK
#define E1000_EECD_SIZE_EX_MASK
Definition: e1000_defines.h:1051
E1000_EECD_TIMEOUT
#define E1000_EECD_TIMEOUT
Definition: e1000_defines.h:1044
E1000_VLAN_FILTER_TBL_SIZE
#define E1000_VLAN_FILTER_TBL_SIZE
Definition: e1000_defines.h:692
E1000_IPCNFG_EEE_1G_AN
#define E1000_IPCNFG_EEE_1G_AN
Definition: e1000_defines.h:864
E1000_PCS_CFG_PCS_EN
#define E1000_PCS_CFG_PCS_EN
Definition: e1000_defines.h:303
E1000_MEDIA_PORT_OTHER
#define E1000_MEDIA_PORT_OTHER
Definition: e1000_defines.h:847
E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
Definition: e1000_defines.h:88
E1000_SWFW_PHY0_SM
#define E1000_SWFW_PHY0_SM
Definition: e1000_defines.h:251
E1000_CTRL_EXT_LINK_MODE_MASK
#define E1000_CTRL_EXT_LINK_MODE_MASK
Definition: e1000_defines.h:85
ID_LED_RESERVED_FFFF
#define ID_LED_RESERVED_FFFF
Definition: e1000_defines.h:1214
E1000_STATUS_2P5_SKU
#define E1000_STATUS_2P5_SKU
Definition: e1000_defines.h:340
NVM_COMPATIBILITY_BIT_MASK
#define NVM_COMPATIBILITY_BIT_MASK
Definition: e1000_defines.h:1146
E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
Definition: e1000_defines.h:90
PHY_CFG_TIMEOUT
#define PHY_CFG_TIMEOUT
Definition: e1000_defines.h:737
E1000_M88E1512_MODE
#define E1000_M88E1512_MODE
Definition: e1000_defines.h:889
E1000_M88E1512_CFG_REG_2
#define E1000_M88E1512_CFG_REG_2
Definition: e1000_defines.h:887
E1000_CTRL_RST
#define E1000_CTRL_RST
Definition: e1000_defines.h:285
E1000_PCS_LCTL_AN_RESTART
#define E1000_PCS_LCTL_AN_RESTART
Definition: e1000_defines.h:313
NVM_82580_LAN_FUNC_OFFSET
#define NVM_82580_LAN_FUNC_OFFSET(a)
Definition: e1000_defines.h:1153
E1000_PCS_LCTL_FSV_1000
#define E1000_PCS_LCTL_FSV_1000
Definition: e1000_defines.h:307
E1000_EEER_TX_LPI_EN
#define E1000_EEER_TX_LPI_EN
Definition: e1000_defines.h:866
E1000_M88E1543_EEE_CTRL_1_MS
#define E1000_M88E1543_EEE_CTRL_1_MS
Definition: e1000_defines.h:876
AUTONEG_ADVERTISE_SPEED_DEFAULT
#define AUTONEG_ADVERTISE_SPEED_DEFAULT
Definition: e1000_defines.h:378
M88E1340M_E_PHY_ID
#define M88E1340M_E_PHY_ID
Definition: e1000_defines.h:1273
I82580_I_PHY_ID
#define I82580_I_PHY_ID
Definition: e1000_defines.h:1285
E1000_NVM_CFG_DONE_PORT_0
#define E1000_NVM_CFG_DONE_PORT_0
Definition: e1000_defines.h:1148
E1000_PCS_LSTS_SPEED_1000
#define E1000_PCS_LSTS_SPEED_1000
Definition: e1000_defines.h:319
E1000_M88E1112_STATUS_LINK
#define E1000_M88E1112_STATUS_LINK
Definition: e1000_defines.h:850
E1000_CTRL_SWDPIN1
#define E1000_CTRL_SWDPIN1
Definition: e1000_defines.h:276
E1000_ERR_SWFW_SYNC
#define E1000_ERR_SWFW_SYNC
Definition: e1000_defines.h:720
E1000_ERR_I2C
#define E1000_ERR_I2C
Definition: e1000_defines.h:726
E1000_CTRL_EXT_SDP3_DATA
#define E1000_CTRL_EXT_SDP3_DATA
Definition: e1000_defines.h:72
NVM_COMPATIBILITY_REG_3
#define NVM_COMPATIBILITY_REG_3
Definition: e1000_defines.h:1145
E1000_TXCW_PAUSE
#define E1000_TXCW_PAUSE
Definition: e1000_defines.h:750
E1000_SWFW_EEP_SM
#define E1000_SWFW_EEP_SM
Definition: e1000_defines.h:250
E1000_GCR_CMPL_TMOUT_MASK
#define E1000_GCR_CMPL_TMOUT_MASK
Definition: e1000_defines.h:900
E1000_ALL_NOT_GIG
#define E1000_ALL_NOT_GIG
Definition: e1000_defines.h:371
SPEED_10
#define SPEED_10
Definition: e1000_defines.h:351
E1000_CTRL_I2C_ENA
#define E1000_CTRL_I2C_ENA
Definition: e1000_defines.h:290
E1000_EECD_ADDR_BITS
#define E1000_EECD_ADDR_BITS
Definition: e1000_defines.h:1047
E1000_NVM_CFG_DONE_PORT_1
#define E1000_NVM_CFG_DONE_PORT_1
Definition: e1000_defines.h:1149
E1000_EECD_PRES
#define E1000_EECD_PRES
Definition: e1000_defines.h:1040
E1000_PCS_LCTL_FORCE_LINK
#define E1000_PCS_LCTL_FORCE_LINK
Definition: e1000_defines.h:310
E1000_EECD_ERROR_CLR
#define E1000_EECD_ERROR_CLR
Definition: e1000_defines.h:1045
E1000_PCS_STATUS_TX_LPI_RCVD
#define E1000_PCS_STATUS_TX_LPI_RCVD
Definition: e1000_defines.h:885
E1000_IPCNFG_EEE_100M_AN
#define E1000_IPCNFG_EEE_100M_AN
Definition: e1000_defines.h:865
E1000_M88E1543_PAGE_ADDR
#define E1000_M88E1543_PAGE_ADDR
Definition: e1000_defines.h:874
NVM_COMPAT
#define NVM_COMPAT
Definition: e1000_defines.h:1084
E1000_M88E1512_CFG_REG_1
#define E1000_M88E1512_CFG_REG_1
Definition: e1000_defines.h:886
E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT
#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT
Definition: e1000_defines.h:853
E1000_PCS_LCTL_FORCE_FCTRL
#define E1000_PCS_LCTL_FORCE_FCTRL
Definition: e1000_defines.h:311
NVM_CHECKSUM_REG
#define NVM_CHECKSUM_REG
Definition: e1000_defines.h:1144
E1000_PCS_LCTL_FLV_LINK_UP
#define E1000_PCS_LCTL_FLV_LINK_UP
Definition: e1000_defines.h:304
E1000_CTRL_SWDPIN0
#define E1000_CTRL_SWDPIN0
Definition: e1000_defines.h:275
E1000_M88E1112_AUTO_COPPER_BASEX
#define E1000_M88E1112_AUTO_COPPER_BASEX
Definition: e1000_defines.h:849
E1000_MDIC_PHY_SHIFT
#define E1000_MDIC_PHY_SHIFT
Definition: e1000_defines.h:1415
NVM_SUM
#define NVM_SUM
Definition: e1000_defines.h:1180
E1000_CTRL_FRCDPX
#define E1000_CTRL_FRCDPX
Definition: e1000_defines.h:271
NVM_WORD24_EXT_MDIO
#define NVM_WORD24_EXT_MDIO
Definition: e1000_defines.h:1157
E1000_SCTL_DISABLE_SERDES_LOOPBACK
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK
Definition: e1000_defines.h:429
E1000_COLLISION_DISTANCE
#define E1000_COLLISION_DISTANCE
Definition: e1000_defines.h:452
IGP04E1000_E_PHY_ID
#define IGP04E1000_E_PHY_ID
Definition: e1000_defines.h:1288
E1000_ERR_CONFIG
#define E1000_ERR_CONFIG
Definition: e1000_defines.h:712
E1000_PCS_LCTL_FDV_FULL
#define E1000_PCS_LCTL_FDV_FULL
Definition: e1000_defines.h:308
E1000_PCS_STATUS_RX_LPI_RCVD
#define E1000_PCS_STATUS_RX_LPI_RCVD
Definition: e1000_defines.h:884
E1000_SUCCESS
#define E1000_SUCCESS
Definition: e1000_defines.h:709
NVM_INIT_CONTROL3_PORT_A
#define NVM_INIT_CONTROL3_PORT_A
Definition: e1000_defines.h:1141
E1000_MDICNFG_EXT_MDIO
#define E1000_MDICNFG_EXT_MDIO
Definition: e1000_defines.h:841
I350_I_PHY_ID
#define I350_I_PHY_ID
Definition: e1000_defines.h:1286
E1000_PCS_LCTL_AN_ENABLE
#define E1000_PCS_LCTL_AN_ENABLE
Definition: e1000_defines.h:312
E1000_CTRL_SPD_1000
#define E1000_CTRL_SPD_1000
Definition: e1000_defines.h:269
M88E1512_E_PHY_ID
#define M88E1512_E_PHY_ID
Definition: e1000_defines.h:1270
E1000_MEDIA_PORT_COPPER
#define E1000_MEDIA_PORT_COPPER
Definition: e1000_defines.h:846
E1000_ERR_NVM
#define E1000_ERR_NVM
Definition: e1000_defines.h:710
FULL_DUPLEX
#define FULL_DUPLEX
Definition: e1000_defines.h:356
I210_I_PHY_ID
#define I210_I_PHY_ID
Definition: e1000_defines.h:1287
NVM_ID_LED_SETTINGS
#define NVM_ID_LED_SETTINGS
Definition: e1000_defines.h:1085
IGP03E1000_E_PHY_ID
#define IGP03E1000_E_PHY_ID
Definition: e1000_defines.h:1275
e1000_phy_m88
@ e1000_phy_m88
Definition: e1000_hw.h:310
e1000_phy_i210
@ e1000_phy_i210
Definition: e1000_hw.h:323
e1000_phy_82580
@ e1000_phy_82580
Definition: e1000_hw.h:321
e1000_phy_none
@ e1000_phy_none
Definition: e1000_hw.h:309
e1000_phy_igp_3
@ e1000_phy_igp_3
Definition: e1000_hw.h:314
e1000_nvm_override_spi_large
@ e1000_nvm_override_spi_large
Definition: e1000_hw.h:302
e1000_nvm_override_spi_small
@ e1000_nvm_override_spi_small
Definition: e1000_hw.h:301
E1000_FUNC_1
#define E1000_FUNC_1
Definition: e1000_hw.h:229
E1000_FUNC_3
#define E1000_FUNC_3
Definition: e1000_hw.h:231
e1000_82580
@ e1000_82580
Definition: e1000_hw.h:271
e1000_i354
@ e1000_i354
Definition: e1000_hw.h:273
e1000_i210
@ e1000_i210
Definition: e1000_hw.h:274
e1000_i350
@ e1000_i350
Definition: e1000_hw.h:272
e1000_82575
@ e1000_82575
Definition: e1000_hw.h:269
e1000_82576
@ e1000_82576
Definition: e1000_hw.h:270
e1000_i211
@ e1000_i211
Definition: e1000_hw.h:275
E1000_DEV_ID_DH89XXCC_SGMII
#define E1000_DEV_ID_DH89XXCC_SGMII
Definition: e1000_hw.h:217
e1000_read_pcie_cap_reg
s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
Definition: e1000_osdep.c:74
e1000_fc_full
@ e1000_fc_full
Definition: e1000_hw.h:373
e1000_fc_tx_pause
@ e1000_fc_tx_pause
Definition: e1000_hw.h:372
e1000_fc_rx_pause
@ e1000_fc_rx_pause
Definition: e1000_hw.h:371
e1000_smart_speed_off
@ e1000_smart_speed_off
Definition: e1000_hw.h:400
e1000_smart_speed_on
@ e1000_smart_speed_on
Definition: e1000_hw.h:399
e1000_write_pcie_cap_reg
s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
Definition: e1000_osdep.c:88
e1000_media_type_unknown
@ e1000_media_type_unknown
Definition: e1000_hw.h:282
e1000_media_type_internal_serdes
@ e1000_media_type_internal_serdes
Definition: e1000_hw.h:285
e1000_media_type_copper
@ e1000_media_type_copper
Definition: e1000_hw.h:283
e1000_nvm_eeprom_spi
@ e1000_nvm_eeprom_spi
Definition: e1000_hw.h:292
e1000_nvm_flash_hw
@ e1000_nvm_flash_hw
Definition: e1000_hw.h:294
E1000_FUNC_2
#define E1000_FUNC_2
Definition: e1000_hw.h:230
e1000_init_hw_i210
s32 e1000_init_hw_i210(struct e1000_hw *hw)
Definition: e1000_i210.c:811
e1000_i210.h
e1000_get_bus_info_pcie_generic
s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:240
e1000_check_for_copper_link_generic
s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:717
e1000_init_mac_ops_generic
void e1000_init_mac_ops_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:48
e1000_validate_mdi_setting_crossover_generic
s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
Definition: e1000_mac.c:2149
e1000_id_led_init_generic
s32 e1000_id_led_init_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1775
e1000_acquire_swfw_sync
s32 e1000_acquire_swfw_sync(struct e1000_hw *hw, u16 mask)
Definition: e1000_mac.c:2301
e1000_force_mac_fc_generic
s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1297
e1000_led_on_generic
s32 e1000_led_on_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1936
e1000_disable_pcie_master_generic
s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:2023
e1000_check_alt_mac_addr_generic
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:408
e1000_setup_link_generic
s32 e1000_setup_link_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1010
e1000_clear_hw_cntrs_base_generic
void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:666
e1000_release_swfw_sync
void e1000_release_swfw_sync(struct e1000_hw *hw, u16 mask)
Definition: e1000_mac.c:2354
e1000_cleanup_led_generic
s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1875
e1000_led_off_generic
s32 e1000_led_off_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1965
e1000_update_mc_addr_list_generic
void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count)
Definition: e1000_mac.c:595
e1000_blink_led_generic
s32 e1000_blink_led_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1889
e1000_clear_vfta_generic
void e1000_clear_vfta_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:340
e1000_get_speed_and_duplex_copper_generic
s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, u16 *duplex)
Definition: e1000_mac.c:1667
e1000_write_vfta_generic
void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
Definition: e1000_mac.c:361
e1000_setup_led_generic
s32 e1000_setup_led_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1843
e1000_config_fc_after_link_up_generic
s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1359
e1000_write_8bit_ctrl_reg_generic
s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, u32 offset, u8 data)
Definition: e1000_mac.c:2167
e1000_get_auto_rd_done_generic
s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1723
e1000_enable_mng_pass_thru
bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
Definition: e1000_manage.c:343
E1000_FWSM_MODE_MASK
#define E1000_FWSM_MODE_MASK
Definition: e1000_manage.h:63
e1000_init_mbx_params_pf
s32 e1000_init_mbx_params_pf(struct e1000_hw *hw)
Definition: e1000_mbx.c:760
e1000_update_nvm_checksum_generic
s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:1235
e1000_read_mac_addr_generic
s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:1174
e1000_write_nvm_spi
s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_nvm.c:611
e1000_read_nvm_eerd
s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_nvm.c:563
e1000_read_nvm_spi
s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_nvm.c:448
e1000_release_nvm_generic
void e1000_release_nvm_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:370
e1000_acquire_nvm_generic
s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:269
e1000_validate_nvm_checksum_generic
s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:1202
DEBUGOUT1
#define DEBUGOUT1(...)
Definition: e1000_osdep.h:111
DEBUGOUT2
#define DEBUGOUT2(...)
Definition: e1000_osdep.h:112
msec_delay
#define msec_delay(x)
Definition: e1000_osdep.h:103
usec_delay
#define usec_delay(x)
Definition: e1000_osdep.h:101
E1000_WRITE_REG_ARRAY
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value)
Definition: e1000_osdep.h:206
u8
uint8_t u8
Definition: e1000_osdep.h:124
DEBUGFUNC
#define DEBUGFUNC(F)
Definition: e1000_osdep.h:115
E1000_WRITE_FLUSH
#define E1000_WRITE_FLUSH(a)
Definition: e1000_osdep.h:177
E1000_WRITE_REG
#define E1000_WRITE_REG(hw, reg, value)
Definition: e1000_osdep.h:196
u16
uint16_t u16
Definition: e1000_osdep.h:123
DEBUGOUT
#define DEBUGOUT(...)
Definition: e1000_osdep.h:109
E1000_READ_REG
#define E1000_READ_REG(hw, reg)
Definition: e1000_osdep.h:191
s32
int32_t s32
Definition: e1000_osdep.h:126
u32
uint32_t u32
Definition: e1000_osdep.h:122
e1000_phy_force_speed_duplex_igp
s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:1752
e1000_check_reset_block_generic
s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:206
e1000_get_cable_length_m88
s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:2418
e1000_write_xmdio_reg
s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
Definition: e1000_phy.c:4332
e1000_read_sfp_data_byte
s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
Definition: e1000_phy.c:530
e1000_read_phy_reg_igp
s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:777
e1000_read_xmdio_reg
s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
Definition: e1000_phy.c:4318
e1000_read_phy_reg_mdic
s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:291
e1000_get_cable_length_igp_2
s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
Definition: e1000_phy.c:2567
e1000_write_phy_reg_mdic
s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:356
e1000_get_phy_id
s32 e1000_get_phy_id(struct e1000_hw *hw)
Definition: e1000_phy.c:225
e1000_get_phy_info_82577
s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:3964
e1000_get_phy_info_m88
s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:2637
e1000_get_phy_info_igp
s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:2712
e1000_check_polarity_igp
s32 e1000_check_polarity_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:2244
e1000_phy_force_speed_duplex_82577
s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:3915
e1000_write_phy_reg_gs40g
s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:4059
e1000_power_up_phy_copper
void e1000_power_up_phy_copper(struct e1000_hw *hw)
Definition: e1000_phy.c:3504
e1000_write_phy_reg_i2c
s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:469
e1000_get_cable_length_m88_gen2
s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
Definition: e1000_phy.c:2444
e1000_phy_sw_reset_generic
s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:2829
e1000_phy_force_speed_duplex_m88
s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:1818
e1000_read_phy_reg_gs40g
s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:4091
e1000_copper_link_setup_m88_gen2
s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
Definition: e1000_phy.c:1273
e1000_read_phy_reg_i2c
s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:422
e1000_check_polarity_m88
s32 e1000_check_polarity_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:2217
e1000_phy_hw_reset_generic
s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:2862
e1000_copper_link_setup_82577
s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:1055
e1000_set_d3_lplu_state_generic
s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
Definition: e1000_phy.c:2088
e1000_check_polarity_82577
s32 e1000_check_polarity_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:3891
e1000_copper_link_setup_m88
s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:1120
e1000_get_cable_length_82577
s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:4027
e1000_copper_link_setup_igp
s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:1371
e1000_write_phy_reg_igp
s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:845
e1000_phy_init_script_igp3
s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
Definition: e1000_phy.c:2918
e1000_setup_copper_link_generic
s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:1699
E1000_SFF_IDENTIFIER_SFP
#define E1000_SFF_IDENTIFIER_SFP
Definition: e1000_phy.h:317
E1000_SFF_IDENTIFIER_SFF
#define E1000_SFF_IDENTIFIER_SFF
Definition: e1000_phy.h:316
IGP01E1000_PHY_PORT_CONFIG
#define IGP01E1000_PHY_PORT_CONFIG
Definition: e1000_phy.h:133
E1000_SFF_IDENTIFIER_OFFSET
#define E1000_SFF_IDENTIFIER_OFFSET
Definition: e1000_phy.h:315
E1000_SFF_ETH_FLAGS_OFFSET
#define E1000_SFF_ETH_FLAGS_OFFSET
Definition: e1000_phy.h:319
E1000_82580_PM_D0_LPLU
#define E1000_82580_PM_D0_LPLU
Definition: e1000_phy.h:209
E1000_82580_PHY_POWER_MGMT
#define E1000_82580_PHY_POWER_MGMT
Definition: e1000_phy.h:207
IGP02E1000_PM_D0_LPLU
#define IGP02E1000_PM_D0_LPLU
Definition: e1000_phy.h:250
E1000_82580_PM_SPD
#define E1000_82580_PM_SPD
Definition: e1000_phy.h:208
IGP02E1000_PHY_POWER_MGMT
#define IGP02E1000_PHY_POWER_MGMT
Definition: e1000_phy.h:138
E1000_82580_PM_D3_LPLU
#define E1000_82580_PM_D3_LPLU
Definition: e1000_phy.h:210
IGP01E1000_PSCFR_SMART_SPEED
#define IGP01E1000_PSCFR_SMART_SPEED
Definition: e1000_phy.h:243
E1000_TCTL_EXT
#define E1000_TCTL_EXT
Definition: e1000_regs.h:105
E1000_HGPTC
#define E1000_HGPTC
Definition: e1000_regs.h:480
E1000_RXERRC
#define E1000_RXERRC
Definition: e1000_regs.h:329
E1000_GCR
#define E1000_GCR
Definition: e1000_regs.h:536
E1000_PTC1522
#define E1000_PTC1522
Definition: e1000_regs.h:379
E1000_PTC255
#define E1000_PTC255
Definition: e1000_regs.h:376
E1000_HGOTCH
#define E1000_HGOTCH
Definition: e1000_regs.h:485
E1000_ICTXQMTC
#define E1000_ICTXQMTC
Definition: e1000_regs.h:391
E1000_EEE_SU
#define E1000_EEE_SU
Definition: e1000_regs.h:710
E1000_PTC127
#define E1000_PTC127
Definition: e1000_regs.h:375
E1000_PCS_CFG0
#define E1000_PCS_CFG0
Definition: e1000_regs.h:472
E1000_PTC511
#define E1000_PTC511
Definition: e1000_regs.h:377
E1000_HGORCH
#define E1000_HGORCH
Definition: e1000_regs.h:483
E1000_PRC255
#define E1000_PRC255
Definition: e1000_regs.h:348
E1000_CCMCTL
#define E1000_CCMCTL
Definition: e1000_regs.h:532
E1000_ICRXDMTC
#define E1000_ICRXDMTC
Definition: e1000_regs.h:392
E1000_I2CPARAMS
#define E1000_I2CPARAMS
Definition: e1000_regs.h:130
E1000_VFTA
#define E1000_VFTA
Definition: e1000_regs.h:499
E1000_TXSWC
#define E1000_TXSWC
Definition: e1000_regs.h:586
E1000_PRC127
#define E1000_PRC127
Definition: e1000_regs.h:347
E1000_PRC64
#define E1000_PRC64
Definition: e1000_regs.h:346
E1000_ICRXPTC
#define E1000_ICRXPTC
Definition: e1000_regs.h:386
E1000_PCS_ANADV
#define E1000_PCS_ANADV
Definition: e1000_regs.h:489
E1000_GIOCTL
#define E1000_GIOCTL
Definition: e1000_regs.h:533
E1000_EEMNGCTL
#define E1000_EEMNGCTL
Definition: e1000_regs.h:119
E1000_ICTXATC
#define E1000_ICTXATC
Definition: e1000_regs.h:389
E1000_EMIADD
#define E1000_EMIADD
Definition: e1000_regs.h:172
E1000_TNCRS
#define E1000_TNCRS
Definition: e1000_regs.h:337
E1000_I2C_CLK_IN
#define E1000_I2C_CLK_IN
Definition: e1000_regs.h:137
E1000_PCS_LCTL
#define E1000_PCS_LCTL
Definition: e1000_regs.h:473
E1000_RCTL
#define E1000_RCTL
Definition: e1000_regs.h:89
E1000_ICTXQEC
#define E1000_ICTXQEC
Definition: e1000_regs.h:390
E1000_LENERRS
#define E1000_LENERRS
Definition: e1000_regs.h:486
E1000_VT_CTL
#define E1000_VT_CTL
Definition: e1000_regs.h:500
E1000_TCTL
#define E1000_TCTL
Definition: e1000_regs.h:104
E1000_ICRXOC
#define E1000_ICRXOC
Definition: e1000_regs.h:393
E1000_I2C_CLK_OUT
#define E1000_I2C_CLK_OUT
Definition: e1000_regs.h:132
E1000_STATUS
#define E1000_STATUS
Definition: e1000_regs.h:41
E1000_FWSM
#define E1000_FWSM
Definition: e1000_regs.h:545
E1000_I2C_DATA_OUT
#define E1000_I2C_DATA_OUT
Definition: e1000_regs.h:133
E1000_HGOTCL
#define E1000_HGOTCL
Definition: e1000_regs.h:484
E1000_ALGNERRC
#define E1000_ALGNERRC
Definition: e1000_regs.h:327
E1000_EEER
#define E1000_EEER
Definition: e1000_regs.h:709
E1000_MGTPRC
#define E1000_MGTPRC
Definition: e1000_regs.h:365
E1000_CBRMPC
#define E1000_CBRMPC
Definition: e1000_regs.h:478
E1000_ICRXATC
#define E1000_ICRXATC
Definition: e1000_regs.h:387
E1000_CBTMPC
#define E1000_CBTMPC
Definition: e1000_regs.h:475
E1000_HGORCL
#define E1000_HGORCL
Definition: e1000_regs.h:482
E1000_IPCNFG
#define E1000_IPCNFG
Definition: e1000_regs.h:707
E1000_PTC1023
#define E1000_PTC1023
Definition: e1000_regs.h:378
E1000_MGTPTC
#define E1000_MGTPTC
Definition: e1000_regs.h:367
E1000_MDICNFG
#define E1000_MDICNFG
Definition: e1000_regs.h:47
E1000_CTRL
#define E1000_CTRL
Definition: e1000_regs.h:39
E1000_PRC1522
#define E1000_PRC1522
Definition: e1000_regs.h:351
E1000_MDIC
#define E1000_MDIC
Definition: e1000_regs.h:46
E1000_IMC
#define E1000_IMC
Definition: e1000_regs.h:83
E1000_I2C_DATA_OE_N
#define E1000_I2C_DATA_OE_N
Definition: e1000_regs.h:134
E1000_SCTL
#define E1000_SCTL
Definition: e1000_regs.h:60
E1000_DTXSWC
#define E1000_DTXSWC
Definition: e1000_regs.h:576
E1000_ICTXPTC
#define E1000_ICTXPTC
Definition: e1000_regs.h:388
E1000_SCVPC
#define E1000_SCVPC
Definition: e1000_regs.h:487
E1000_I2C_CLK_OE_N
#define E1000_I2C_CLK_OE_N
Definition: e1000_regs.h:136
E1000_PRC1023
#define E1000_PRC1023
Definition: e1000_regs.h:350
E1000_PCS_LSTAT
#define E1000_PCS_LSTAT
Definition: e1000_regs.h:474
E1000_I2C_DATA_IN
#define E1000_I2C_DATA_IN
Definition: e1000_regs.h:135
E1000_I2CBB_EN
#define E1000_I2CBB_EN
Definition: e1000_regs.h:131
E1000_PRC511
#define E1000_PRC511
Definition: e1000_regs.h:349
E1000_SCCTL
#define E1000_SCCTL
Definition: e1000_regs.h:534
E1000_TSCTFC
#define E1000_TSCTFC
Definition: e1000_regs.h:383
E1000_CEXTERR
#define E1000_CEXTERR
Definition: e1000_regs.h:339
E1000_ICR
#define E1000_ICR
Definition: e1000_regs.h:79
E1000_EMIDATA
#define E1000_EMIDATA
Definition: e1000_regs.h:173
E1000_HTCBDPC
#define E1000_HTCBDPC
Definition: e1000_regs.h:481
E1000_PTC64
#define E1000_PTC64
Definition: e1000_regs.h:374
E1000_EECD
#define E1000_EECD
Definition: e1000_regs.h:42
E1000_IAC
#define E1000_IAC
Definition: e1000_regs.h:384
E1000_MGTPDC
#define E1000_MGTPDC
Definition: e1000_regs.h:366
E1000_TSCTC
#define E1000_TSCTC
Definition: e1000_regs.h:382
E1000_RPTHC
#define E1000_RPTHC
Definition: e1000_regs.h:479
E1000_CTRL_EXT
#define E1000_CTRL_EXT
Definition: e1000_regs.h:44
E1000_HTDPMC
#define E1000_HTDPMC
Definition: e1000_regs.h:476
e1000_bus_info::func
u16 func
Definition: e1000_hw.h:908
e1000_dev_spec_82575
Definition: e1000_hw.h:1004
e1000_dev_spec_82575::clear_semaphore_once
bool clear_semaphore_once
Definition: e1000_hw.h:1009
e1000_dev_spec_82575::module_plugged
bool module_plugged
Definition: e1000_hw.h:1008
e1000_dev_spec_82575::eee_disable
bool eee_disable
Definition: e1000_hw.h:1007
e1000_dev_spec_82575::sgmii_active
bool sgmii_active
Definition: e1000_hw.h:1005
e1000_dev_spec_82575::eth_flags
struct sfp_e1000_flags eth_flags
Definition: e1000_hw.h:1011
e1000_dev_spec_82575::mtu
u32 mtu
Definition: e1000_hw.h:1010
e1000_dev_spec_82575::media_changed
bool media_changed
Definition: e1000_hw.h:1013
e1000_dev_spec_82575::global_device_reset
bool global_device_reset
Definition: e1000_hw.h:1006
e1000_dev_spec_82575::media_port
u8 media_port
Definition: e1000_hw.h:1012
e1000_fc_info::requested_mode
enum e1000_fc_mode requested_mode
Definition: e1000_hw.h:920
e1000_hw
Definition: e1000_hw.h:1021
e1000_hw::dev_spec
union e1000_hw::@46 dev_spec
e1000_hw::bus
struct e1000_bus_info bus
Definition: e1000_hw.h:1032
e1000_hw::mac
struct e1000_mac_info mac
Definition: e1000_hw.h:1028
e1000_hw::_82575
struct e1000_dev_spec_82575 _82575
Definition: e1000_hw.h:1043
e1000_hw::nvm
struct e1000_nvm_info nvm
Definition: e1000_hw.h:1031
e1000_hw::mbx
struct e1000_mbx_info mbx
Definition: e1000_hw.h:1033
e1000_hw::fc
struct e1000_fc_info fc
Definition: e1000_hw.h:1029
e1000_hw::device_id
u16 device_id
Definition: e1000_hw.h:1047
e1000_hw::phy
struct e1000_phy_info phy
Definition: e1000_hw.h:1030
e1000_mac_info
Definition: e1000_hw.h:810
e1000_mac_info::has_fwsm
bool has_fwsm
Definition: e1000_hw.h:841
e1000_mac_info::autoneg
bool autoneg
Definition: e1000_hw.h:844
e1000_mac_info::type
enum e1000_mac_type type
Definition: e1000_hw.h:815
e1000_mac_info::arc_subsystem_valid
bool arc_subsystem_valid
Definition: e1000_hw.h:842
e1000_mac_info::get_link_status
bool get_link_status
Definition: e1000_hw.h:846
e1000_mac_info::asf_firmware_present
bool asf_firmware_present
Definition: e1000_hw.h:843
e1000_mac_info::mta_reg_count
u16 mta_reg_count
Definition: e1000_hw.h:830
e1000_mac_info::serdes_has_link
bool serdes_has_link
Definition: e1000_hw.h:850
e1000_mac_info::uta_reg_count
u16 uta_reg_count
Definition: e1000_hw.h:831
e1000_mac_info::rar_entry_count
u16 rar_entry_count
Definition: e1000_hw.h:836
e1000_mac_info::ops
struct e1000_mac_operations ops
Definition: e1000_hw.h:811
e1000_mac_operations::release_swfw_sync
void(* release_swfw_sync)(struct e1000_hw *, u16)
Definition: e1000_hw.h:752
e1000_mac_operations::setup_led
s32(* setup_led)(struct e1000_hw *)
Definition: e1000_hw.h:744
e1000_mac_operations::id_led_init
s32(* id_led_init)(struct e1000_hw *)
Definition: e1000_hw.h:725
e1000_mac_operations::get_link_up_info
s32(* get_link_up_info)(struct e1000_hw *, u16 *, u16 *)
Definition: e1000_hw.h:734
e1000_mac_operations::setup_physical_interface
s32(* setup_physical_interface)(struct e1000_hw *)
Definition: e1000_hw.h:743
e1000_mac_operations::validate_mdi_setting
s32(* validate_mdi_setting)(struct e1000_hw *)
Definition: e1000_hw.h:749
e1000_mac_operations::check_for_link
s32(* check_for_link)(struct e1000_hw *)
Definition: e1000_hw.h:728
e1000_mac_operations::config_collision_dist
void(* config_collision_dist)(struct e1000_hw *)
Definition: e1000_hw.h:746
e1000_mac_operations::clear_vfta
void(* clear_vfta)(struct e1000_hw *)
Definition: e1000_hw.h:731
e1000_mac_operations::blink_led
s32(* blink_led)(struct e1000_hw *)
Definition: e1000_hw.h:726
e1000_mac_operations::reset_hw
s32(* reset_hw)(struct e1000_hw *)
Definition: e1000_hw.h:738
e1000_mac_operations::led_on
s32(* led_on)(struct e1000_hw *)
Definition: e1000_hw.h:735
e1000_mac_operations::read_mac_addr
s32(* read_mac_addr)(struct e1000_hw *)
Definition: e1000_hw.h:748
e1000_mac_operations::write_vfta
void(* write_vfta)(struct e1000_hw *, u32, u32)
Definition: e1000_hw.h:745
e1000_mac_operations::init_hw
s32(* init_hw)(struct e1000_hw *)
Definition: e1000_hw.h:739
e1000_mac_operations::setup_link
s32(* setup_link)(struct e1000_hw *)
Definition: e1000_hw.h:742
e1000_mac_operations::power_up_serdes
void(* power_up_serdes)(struct e1000_hw *)
Definition: e1000_hw.h:741
e1000_mac_operations::cleanup_led
s32(* cleanup_led)(struct e1000_hw *)
Definition: e1000_hw.h:729
e1000_mac_operations::clear_hw_cntrs
void(* clear_hw_cntrs)(struct e1000_hw *)
Definition: e1000_hw.h:730
e1000_mac_operations::set_lan_id
void(* set_lan_id)(struct e1000_hw *)
Definition: e1000_hw.h:733
e1000_mac_operations::acquire_swfw_sync
s32(* acquire_swfw_sync)(struct e1000_hw *, u16)
Definition: e1000_hw.h:751
e1000_mac_operations::update_mc_addr_list
void(* update_mc_addr_list)(struct e1000_hw *, u8 *, u32)
Definition: e1000_hw.h:737
e1000_mac_operations::led_off
s32(* led_off)(struct e1000_hw *)
Definition: e1000_hw.h:736
e1000_mac_operations::get_bus_info
s32(* get_bus_info)(struct e1000_hw *)
Definition: e1000_hw.h:732
e1000_mac_operations::init_params
s32(* init_params)(struct e1000_hw *)
Definition: e1000_hw.h:724
e1000_mac_operations::shutdown_serdes
void(* shutdown_serdes)(struct e1000_hw *)
Definition: e1000_hw.h:740
e1000_mbx_info::ops
struct e1000_mbx_operations ops
Definition: e1000_hw.h:944
e1000_mbx_operations::init_params
s32(* init_params)(struct e1000_hw *hw)
Definition: e1000_hw.h:924
e1000_nvm_info
Definition: e1000_hw.h:888
e1000_nvm_info::ops
struct e1000_nvm_operations ops
Definition: e1000_hw.h:889
e1000_nvm_info::type
enum e1000_nvm_type type
Definition: e1000_hw.h:890
e1000_nvm_info::opcode_bits
u16 opcode_bits
Definition: e1000_hw.h:899
e1000_nvm_info::override
enum e1000_nvm_override override
Definition: e1000_hw.h:891
e1000_nvm_info::delay_usec
u16 delay_usec
Definition: e1000_hw.h:897
e1000_nvm_info::page_size
u16 page_size
Definition: e1000_hw.h:900
e1000_nvm_info::address_bits
u16 address_bits
Definition: e1000_hw.h:898
e1000_nvm_info::word_size
u16 word_size
Definition: e1000_hw.h:896
e1000_nvm_operations::release
void(* release)(struct e1000_hw *)
Definition: e1000_hw.h:802
e1000_nvm_operations::init_params
s32(* init_params)(struct e1000_hw *)
Definition: e1000_hw.h:799
e1000_nvm_operations::write
s32(* write)(struct e1000_hw *, u16, u16, u16 *)
Definition: e1000_hw.h:807
e1000_nvm_operations::validate
s32(* validate)(struct e1000_hw *)
Definition: e1000_hw.h:806
e1000_nvm_operations::update
s32(* update)(struct e1000_hw *)
Definition: e1000_hw.h:804
e1000_nvm_operations::read
s32(* read)(struct e1000_hw *, u16, u16, u16 *)
Definition: e1000_hw.h:801
e1000_nvm_operations::acquire
s32(* acquire)(struct e1000_hw *)
Definition: e1000_hw.h:800
e1000_nvm_operations::valid_led_default
s32(* valid_led_default)(struct e1000_hw *, u16 *)
Definition: e1000_hw.h:805
e1000_phy_info
Definition: e1000_hw.h:855
e1000_phy_info::id
u32 id
Definition: e1000_hw.h:867
e1000_phy_info::reset_delay_us
u32 reset_delay_us
Definition: e1000_hw.h:868
e1000_phy_info::media_type
enum e1000_media_type media_type
Definition: e1000_hw.h:871
e1000_phy_info::autoneg_advertised
u16 autoneg_advertised
Definition: e1000_hw.h:873
e1000_phy_info::ops
struct e1000_phy_operations ops
Definition: e1000_hw.h:856
e1000_phy_info::type
enum e1000_phy_type type
Definition: e1000_hw.h:857
e1000_phy_info::autoneg_mask
u16 autoneg_mask
Definition: e1000_hw.h:874
e1000_phy_info::smart_speed
enum e1000_smart_speed smart_speed
Definition: e1000_hw.h:864
e1000_phy_info::addr
u32 addr
Definition: e1000_hw.h:866
e1000_phy_operations::get_cfg_done
s32(* get_cfg_done)(struct e1000_hw *hw)
Definition: e1000_hw.h:777
e1000_phy_operations::power_up
void(* power_up)(struct e1000_hw *)
Definition: e1000_hw.h:791
e1000_phy_operations::reset
s32(* reset)(struct e1000_hw *)
Definition: e1000_hw.h:785
e1000_phy_operations::read_i2c_byte
s32(* read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *)
Definition: e1000_hw.h:793
e1000_phy_operations::init_params
s32(* init_params)(struct e1000_hw *)
Definition: e1000_hw.h:770
e1000_phy_operations::read_reg
s32(* read_reg)(struct e1000_hw *, u32, u16 *)
Definition: e1000_hw.h:781
e1000_phy_operations::get_info
s32(* get_info)(struct e1000_hw *)
Definition: e1000_hw.h:779
e1000_phy_operations::release
void(* release)(struct e1000_hw *)
Definition: e1000_hw.h:784
e1000_phy_operations::set_d3_lplu_state
s32(* set_d3_lplu_state)(struct e1000_hw *, bool)
Definition: e1000_hw.h:787
e1000_phy_operations::force_speed_duplex
s32(* force_speed_duplex)(struct e1000_hw *)
Definition: e1000_hw.h:776
e1000_phy_operations::write_i2c_byte
s32(* write_i2c_byte)(struct e1000_hw *, u8, u8, u8)
Definition: e1000_hw.h:794
e1000_phy_operations::get_cable_length
s32(* get_cable_length)(struct e1000_hw *)
Definition: e1000_hw.h:778
e1000_phy_operations::check_reset_block
s32(* check_reset_block)(struct e1000_hw *)
Definition: e1000_hw.h:774
e1000_phy_operations::acquire
s32(* acquire)(struct e1000_hw *)
Definition: e1000_hw.h:771
e1000_phy_operations::set_d0_lplu_state
s32(* set_d0_lplu_state)(struct e1000_hw *, bool)
Definition: e1000_hw.h:786
e1000_phy_operations::write_reg
s32(* write_reg)(struct e1000_hw *, u32, u16)
Definition: e1000_hw.h:788
e1000_phy_operations::commit
s32(* commit)(struct e1000_hw *)
Definition: e1000_hw.h:775
e1000_phy_operations::power_down
void(* power_down)(struct e1000_hw *)
Definition: e1000_hw.h:792
e1000_phy_operations::check_polarity
s32(* check_polarity)(struct e1000_hw *)
Definition: e1000_hw.h:773
sfp_e1000_flags
Definition: e1000_phy.h:321
sfp_e1000_flags::e1000_base_t
u8 e1000_base_t
Definition: e1000_phy.h:325
sfp_e1000_flags::e1000_base_sx
u8 e1000_base_sx
Definition: e1000_phy.h:322
sfp_e1000_flags::e100_base_fx
u8 e100_base_fx
Definition: e1000_phy.h:327
sfp_e1000_flags::e1000_base_lx
u8 e1000_base_lx
Definition: e1000_phy.h:323