FreeBSD kernel E1000 device code
e1000_ich8lan.c
Go to the documentation of this file.
1/******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33******************************************************************************/
34/*$FreeBSD$*/
35
36/* 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection
42 * 82566DC-2 Gigabit Network Connection
43 * 82566DC Gigabit Network Connection
44 * 82566DM-2 Gigabit Network Connection
45 * 82566DM Gigabit Network Connection
46 * 82566MC Gigabit Network Connection
47 * 82566MM Gigabit Network Connection
48 * 82567LM Gigabit Network Connection
49 * 82567LF Gigabit Network Connection
50 * 82567V Gigabit Network Connection
51 * 82567LM-2 Gigabit Network Connection
52 * 82567LF-2 Gigabit Network Connection
53 * 82567V-2 Gigabit Network Connection
54 * 82567LF-3 Gigabit Network Connection
55 * 82567LM-3 Gigabit Network Connection
56 * 82567LM-4 Gigabit Network Connection
57 * 82577LM Gigabit Network Connection
58 * 82577LC Gigabit Network Connection
59 * 82578DM Gigabit Network Connection
60 * 82578DC Gigabit Network Connection
61 * 82579LM Gigabit Network Connection
62 * 82579V Gigabit Network Connection
63 * Ethernet Connection I217-LM
64 * Ethernet Connection I217-V
65 * Ethernet Connection I218-V
66 * Ethernet Connection I218-LM
67 * Ethernet Connection (2) I218-LM
68 * Ethernet Connection (2) I218-V
69 * Ethernet Connection (3) I218-LM
70 * Ethernet Connection (3) I218-V
71 */
72
73#include "e1000_api.h"
74
75static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
76static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
77static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
78static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
79static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
80static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
81static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
82static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
83static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
84static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
85 u8 *mc_addr_list,
86 u32 mc_addr_count);
87static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
88static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
89static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
90static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 bool active);
92static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 bool active);
94static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 u16 words, u16 *data);
96static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 u16 *data);
98static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 u16 words, u16 *data);
100static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
101static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
102static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
103static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 u16 *data);
105static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
106static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
107static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
108static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
109static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
110static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
111static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
112static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 u16 *speed, u16 *duplex);
114static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
115static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
116static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
117static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
118static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
119static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
120static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
121static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
122static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
123static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
124static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
125static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 u32 offset, u8 *data);
128static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 u8 size, u16 *data);
130static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 u32 *data);
132static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 *data);
134static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 u32 offset, u32 data);
136static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 u32 offset, u32 dword);
138static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 u32 offset, u16 *data);
140static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 u32 offset, u8 byte);
142static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
143static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
144static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
145static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
146static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
147static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
148static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
149
150/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
151/* Offset 04h HSFSTS */
152union ich8_hws_flash_status {
153 struct ich8_hsfsts {
154 u16 flcdone:1; /* bit 0 Flash Cycle Done */
155 u16 flcerr:1; /* bit 1 Flash Cycle Error */
156 u16 dael:1; /* bit 2 Direct Access error Log */
157 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
158 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
159 u16 reserved1:2; /* bit 13:6 Reserved */
160 u16 reserved2:6; /* bit 13:6 Reserved */
161 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
162 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
163 } hsf_status;
164 u16 regval;
165};
166
167/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
168/* Offset 06h FLCTL */
169union ich8_hws_flash_ctrl {
170 struct ich8_hsflctl {
171 u16 flcgo:1; /* 0 Flash Cycle Go */
172 u16 flcycle:2; /* 2:1 Flash Cycle */
173 u16 reserved:5; /* 7:3 Reserved */
174 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
175 u16 flockdn:6; /* 15:10 Reserved */
176 } hsf_ctrl;
177 u16 regval;
178};
179
180/* ICH Flash Region Access Permissions */
181union ich8_hws_flash_regacc {
182 struct ich8_flracc {
183 u32 grra:8; /* 0:7 GbE region Read Access */
184 u32 grwa:8; /* 8:15 GbE region Write Access */
185 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
186 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
187 } hsf_flregacc;
188 u16 regval;
189};
190
201static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
202{
203 u16 phy_reg = 0;
204 u32 phy_id = 0;
205 s32 ret_val = 0;
206 u16 retry_count;
207 u32 mac_reg = 0;
208
209 for (retry_count = 0; retry_count < 2; retry_count++) {
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211 if (ret_val || (phy_reg == 0xFFFF))
212 continue;
213 phy_id = (u32)(phy_reg << 16);
214
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216 if (ret_val || (phy_reg == 0xFFFF)) {
217 phy_id = 0;
218 continue;
219 }
220 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
221 break;
222 }
223
224 if (hw->phy.id) {
225 if (hw->phy.id == phy_id)
226 goto out;
227 } else if (phy_id) {
228 hw->phy.id = phy_id;
229 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
230 goto out;
231 }
232
233 /* In case the PHY needs to be in mdio slow mode,
234 * set slow mode and try to get the PHY id again.
235 */
236 if (hw->mac.type < e1000_pch_lpt) {
237 hw->phy.ops.release(hw);
238 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 if (!ret_val)
240 ret_val = e1000_get_phy_id(hw);
241 hw->phy.ops.acquire(hw);
242 }
243
244 if (ret_val)
245 return false;
246out:
247 if (hw->mac.type >= e1000_pch_lpt) {
248 /* Only unforce SMBus if ME is not active */
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
250 E1000_ICH_FWSM_FW_VALID)) {
251 /* Unforce SMBus mode in PHY */
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
255
256 /* Unforce SMBus mode in MAC */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
260 }
261 }
262
263 return true;
264}
265
273static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
274{
275 u32 mac_reg;
276
277 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
278
279 /* Set Phy Config Counter to 50msec */
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
281 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
282 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
284
285 /* Toggle LANPHYPC Value bit */
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
287 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
288 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290 E1000_WRITE_FLUSH(hw);
291 msec_delay(1);
292 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294 E1000_WRITE_FLUSH(hw);
295
296 if (hw->mac.type < e1000_pch_lpt) {
297 msec_delay(50);
298 } else {
299 u16 count = 20;
300
301 do {
302 msec_delay(5);
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
304 E1000_CTRL_EXT_LPCD) && count--);
305
306 msec_delay(30);
307 }
308}
309
317static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
318{
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
320 s32 ret_val;
321
322 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
323
324 /* Gate automatic PHY configuration by hardware on managed and
325 * non-managed 82579 and newer adapters.
326 */
327 e1000_gate_hw_phy_config_ich8lan(hw, true);
328
329 /* It is not possible to be certain of the current state of ULP
330 * so forcibly disable it.
331 */
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
333 e1000_disable_ulp_lpt_lp(hw, TRUE);
334
335 ret_val = hw->phy.ops.acquire(hw);
336 if (ret_val) {
337 DEBUGOUT("Failed to initialize PHY flow\n");
338 goto out;
339 }
340
341 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
342 * inaccessible and resetting the PHY is not blocked, toggle the
343 * LANPHYPC Value bit to force the interconnect to PCIe mode.
344 */
345 switch (hw->mac.type) {
346 case e1000_pch_lpt:
347 case e1000_pch_spt:
348 case e1000_pch_cnp:
349 case e1000_pch_tgp:
350 case e1000_pch_adp:
351 case e1000_pch_mtp:
352 if (e1000_phy_is_accessible_pchlan(hw))
353 break;
354
355 /* Before toggling LANPHYPC, see if PHY is accessible by
356 * forcing MAC to SMBus mode first.
357 */
358 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
359 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
360 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
361
362 /* Wait 50 milliseconds for MAC to finish any retries
363 * that it might be trying to perform from previous
364 * attempts to acknowledge any phy read requests.
365 */
366 msec_delay(50);
367
368 /* FALLTHROUGH */
369 case e1000_pch2lan:
370 if (e1000_phy_is_accessible_pchlan(hw))
371 break;
372
373 /* FALLTHROUGH */
374 case e1000_pchlan:
375 if ((hw->mac.type == e1000_pchlan) &&
376 (fwsm & E1000_ICH_FWSM_FW_VALID))
377 break;
378
379 if (hw->phy.ops.check_reset_block(hw)) {
380 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
381 ret_val = -E1000_ERR_PHY;
382 break;
383 }
384
385 /* Toggle LANPHYPC Value bit */
386 e1000_toggle_lanphypc_pch_lpt(hw);
387 if (hw->mac.type >= e1000_pch_lpt) {
388 if (e1000_phy_is_accessible_pchlan(hw))
389 break;
390
391 /* Toggling LANPHYPC brings the PHY out of SMBus mode
392 * so ensure that the MAC is also out of SMBus mode
393 */
394 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
395 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
396 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
397
398 if (e1000_phy_is_accessible_pchlan(hw))
399 break;
400
401 ret_val = -E1000_ERR_PHY;
402 }
403 break;
404 default:
405 break;
406 }
407
408 hw->phy.ops.release(hw);
409 if (!ret_val) {
410
411 /* Check to see if able to reset PHY. Print error if not */
412 if (hw->phy.ops.check_reset_block(hw)) {
413 ERROR_REPORT("Reset blocked by ME\n");
414 goto out;
415 }
416
417 /* Reset the PHY before any access to it. Doing so, ensures
418 * that the PHY is in a known good state before we read/write
419 * PHY registers. The generic reset is sufficient here,
420 * because we haven't determined the PHY type yet.
421 */
422 ret_val = e1000_phy_hw_reset_generic(hw);
423 if (ret_val)
424 goto out;
425
426 /* On a successful reset, possibly need to wait for the PHY
427 * to quiesce to an accessible state before returning control
428 * to the calling function. If the PHY does not quiesce, then
429 * return E1000E_BLK_PHY_RESET, as this is the condition that
430 * the PHY is in.
431 */
432 ret_val = hw->phy.ops.check_reset_block(hw);
433 if (ret_val)
434 ERROR_REPORT("ME blocked access to PHY after reset\n");
435 }
436
437out:
438 /* Ungate automatic PHY configuration on non-managed 82579 */
439 if ((hw->mac.type == e1000_pch2lan) &&
440 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
441 msec_delay(10);
442 e1000_gate_hw_phy_config_ich8lan(hw, false);
443 }
444
445 return ret_val;
446}
447
454static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
455{
456 struct e1000_phy_info *phy = &hw->phy;
457 s32 ret_val;
458
459 DEBUGFUNC("e1000_init_phy_params_pchlan");
460
461 phy->addr = 1;
462 phy->reset_delay_us = 100;
463
464 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
465 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
466 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
467 phy->ops.set_page = e1000_set_page_igp;
468 phy->ops.read_reg = e1000_read_phy_reg_hv;
469 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
470 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
471 phy->ops.release = e1000_release_swflag_ich8lan;
472 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
473 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
474 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
475 phy->ops.write_reg = e1000_write_phy_reg_hv;
476 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
477 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
478 phy->ops.power_up = e1000_power_up_phy_copper;
479 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
480 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
481
482 phy->id = e1000_phy_unknown;
483
484 ret_val = e1000_init_phy_workarounds_pchlan(hw);
485 if (ret_val)
486 return ret_val;
487
488 if (phy->id == e1000_phy_unknown)
489 switch (hw->mac.type) {
490 default:
491 ret_val = e1000_get_phy_id(hw);
492 if (ret_val)
493 return ret_val;
494 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
495 break;
496 /* FALLTHROUGH */
497 case e1000_pch2lan:
498 case e1000_pch_lpt:
499 case e1000_pch_spt:
500 case e1000_pch_cnp:
501 case e1000_pch_tgp:
502 case e1000_pch_adp:
503 case e1000_pch_mtp:
504 /* In case the PHY needs to be in mdio slow mode,
505 * set slow mode and try to get the PHY id again.
506 */
507 ret_val = e1000_set_mdio_slow_mode_hv(hw);
508 if (ret_val)
509 return ret_val;
510 ret_val = e1000_get_phy_id(hw);
511 if (ret_val)
512 return ret_val;
513 break;
514 }
515 phy->type = e1000_get_phy_type_from_id(phy->id);
516
517 switch (phy->type) {
518 case e1000_phy_82577:
519 case e1000_phy_82579:
520 case e1000_phy_i217:
521 phy->ops.check_polarity = e1000_check_polarity_82577;
522 phy->ops.force_speed_duplex =
523 e1000_phy_force_speed_duplex_82577;
524 phy->ops.get_cable_length = e1000_get_cable_length_82577;
525 phy->ops.get_info = e1000_get_phy_info_82577;
526 phy->ops.commit = e1000_phy_sw_reset_generic;
527 break;
528 case e1000_phy_82578:
529 phy->ops.check_polarity = e1000_check_polarity_m88;
530 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
531 phy->ops.get_cable_length = e1000_get_cable_length_m88;
532 phy->ops.get_info = e1000_get_phy_info_m88;
533 break;
534 default:
535 ret_val = -E1000_ERR_PHY;
536 break;
537 }
538
539 return ret_val;
540}
541
548static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
549{
550 struct e1000_phy_info *phy = &hw->phy;
551 s32 ret_val;
552 u16 i = 0;
553
554 DEBUGFUNC("e1000_init_phy_params_ich8lan");
555
556 phy->addr = 1;
557 phy->reset_delay_us = 100;
558
559 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
560 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
561 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
562 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
563 phy->ops.read_reg = e1000_read_phy_reg_igp;
564 phy->ops.release = e1000_release_swflag_ich8lan;
565 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
566 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
567 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
568 phy->ops.write_reg = e1000_write_phy_reg_igp;
569 phy->ops.power_up = e1000_power_up_phy_copper;
570 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
571
572 /* We may need to do this twice - once for IGP and if that fails,
573 * we'll set BM func pointers and try again
574 */
575 ret_val = e1000_determine_phy_address(hw);
576 if (ret_val) {
577 phy->ops.write_reg = e1000_write_phy_reg_bm;
578 phy->ops.read_reg = e1000_read_phy_reg_bm;
579 ret_val = e1000_determine_phy_address(hw);
580 if (ret_val) {
581 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
582 return ret_val;
583 }
584 }
585
586 phy->id = 0;
587 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
588 (i++ < 100)) {
589 msec_delay(1);
590 ret_val = e1000_get_phy_id(hw);
591 if (ret_val)
592 return ret_val;
593 }
594
595 /* Verify phy id */
596 switch (phy->id) {
597 case IGP03E1000_E_PHY_ID:
598 phy->type = e1000_phy_igp_3;
599 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
600 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
601 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
602 phy->ops.get_info = e1000_get_phy_info_igp;
603 phy->ops.check_polarity = e1000_check_polarity_igp;
604 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
605 break;
606 case IFE_E_PHY_ID:
607 case IFE_PLUS_E_PHY_ID:
608 case IFE_C_E_PHY_ID:
609 phy->type = e1000_phy_ife;
610 phy->autoneg_mask = E1000_ALL_NOT_GIG;
611 phy->ops.get_info = e1000_get_phy_info_ife;
612 phy->ops.check_polarity = e1000_check_polarity_ife;
613 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
614 break;
615 case BME1000_E_PHY_ID:
616 phy->type = e1000_phy_bm;
617 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
618 phy->ops.read_reg = e1000_read_phy_reg_bm;
619 phy->ops.write_reg = e1000_write_phy_reg_bm;
620 phy->ops.commit = e1000_phy_sw_reset_generic;
621 phy->ops.get_info = e1000_get_phy_info_m88;
622 phy->ops.check_polarity = e1000_check_polarity_m88;
623 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
624 break;
625 default:
626 return -E1000_ERR_PHY;
627 break;
628 }
629
630 return E1000_SUCCESS;
631}
632
640static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
641{
642 struct e1000_nvm_info *nvm = &hw->nvm;
643 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
644 u32 gfpreg, sector_base_addr, sector_end_addr;
645 u16 i;
646 u32 nvm_size;
647
648 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
649
650 nvm->type = e1000_nvm_flash_sw;
651
652 if (hw->mac.type >= e1000_pch_spt) {
653 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
654 * STRAP register. This is because in SPT the GbE Flash region
655 * is no longer accessed through the flash registers. Instead,
656 * the mechanism has changed, and the Flash region access
657 * registers are now implemented in GbE memory space.
658 */
659 nvm->flash_base_addr = 0;
660 nvm_size =
661 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
662 * NVM_SIZE_MULTIPLIER;
663 nvm->flash_bank_size = nvm_size / 2;
664 /* Adjust to word count */
665 nvm->flash_bank_size /= sizeof(u16);
666 /* Set the base address for flash register access */
667 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
668 } else {
669 /* Can't read flash registers if register set isn't mapped. */
670 if (!hw->flash_address) {
671 DEBUGOUT("ERROR: Flash registers not mapped\n");
672 return -E1000_ERR_CONFIG;
673 }
674
675 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
676
677 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
678 * Add 1 to sector_end_addr since this sector is included in
679 * the overall size.
680 */
681 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
682 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
683
684 /* flash_base_addr is byte-aligned */
685 nvm->flash_base_addr = sector_base_addr
686 << FLASH_SECTOR_ADDR_SHIFT;
687
688 /* find total size of the NVM, then cut in half since the total
689 * size represents two separate NVM banks.
690 */
691 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
692 << FLASH_SECTOR_ADDR_SHIFT);
693 nvm->flash_bank_size /= 2;
694 /* Adjust to word count */
695 nvm->flash_bank_size /= sizeof(u16);
696 }
697
698 nvm->word_size = E1000_SHADOW_RAM_WORDS;
699
700 /* Clear shadow ram */
701 for (i = 0; i < nvm->word_size; i++) {
702 dev_spec->shadow_ram[i].modified = false;
703 dev_spec->shadow_ram[i].value = 0xFFFF;
704 }
705
706 /* Function Pointers */
707 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
708 nvm->ops.release = e1000_release_nvm_ich8lan;
709 if (hw->mac.type >= e1000_pch_spt) {
710 nvm->ops.read = e1000_read_nvm_spt;
711 nvm->ops.update = e1000_update_nvm_checksum_spt;
712 } else {
713 nvm->ops.read = e1000_read_nvm_ich8lan;
714 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
715 }
716 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
717 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
718 nvm->ops.write = e1000_write_nvm_ich8lan;
719
720 return E1000_SUCCESS;
721}
722
730static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
731{
732 struct e1000_mac_info *mac = &hw->mac;
733
734 DEBUGFUNC("e1000_init_mac_params_ich8lan");
735
736 /* Set media type function pointer */
737 hw->phy.media_type = e1000_media_type_copper;
738
739 /* Set mta register count */
740 mac->mta_reg_count = 32;
741 /* Set rar entry count */
742 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
743 if (mac->type == e1000_ich8lan)
744 mac->rar_entry_count--;
745 /* Set if part includes ASF firmware */
746 mac->asf_firmware_present = true;
747 /* FWSM register */
748 mac->has_fwsm = true;
749 /* ARC subsystem not supported */
750 mac->arc_subsystem_valid = false;
751 /* Adaptive IFS supported */
752 mac->adaptive_ifs = true;
753
754 /* Function pointers */
755
756 /* bus type/speed/width */
757 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
758 /* function id */
759 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
760 /* reset */
761 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
762 /* hw initialization */
763 mac->ops.init_hw = e1000_init_hw_ich8lan;
764 /* link setup */
765 mac->ops.setup_link = e1000_setup_link_ich8lan;
766 /* physical interface setup */
767 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
768 /* check for link */
769 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
770 /* link info */
771 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
772 /* multicast address update */
773 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
774 /* clear hardware counters */
775 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
776
777 /* LED and other operations */
778 switch (mac->type) {
779 case e1000_ich8lan:
780 case e1000_ich9lan:
781 case e1000_ich10lan:
782 /* check management mode */
783 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
784 /* ID LED init */
785 mac->ops.id_led_init = e1000_id_led_init_generic;
786 /* blink LED */
787 mac->ops.blink_led = e1000_blink_led_generic;
788 /* setup LED */
789 mac->ops.setup_led = e1000_setup_led_generic;
790 /* cleanup LED */
791 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
792 /* turn on/off LED */
793 mac->ops.led_on = e1000_led_on_ich8lan;
794 mac->ops.led_off = e1000_led_off_ich8lan;
795 break;
796 case e1000_pch2lan:
797 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
798 mac->ops.rar_set = e1000_rar_set_pch2lan;
799 /* FALLTHROUGH */
800 case e1000_pch_lpt:
801 case e1000_pch_spt:
802 case e1000_pch_cnp:
803 case e1000_pch_tgp:
804 case e1000_pch_adp:
805 case e1000_pch_mtp:
806 /* multicast address update for pch2 */
807 mac->ops.update_mc_addr_list =
808 e1000_update_mc_addr_list_pch2lan;
809 /* FALLTHROUGH */
810 case e1000_pchlan:
811 /* check management mode */
812 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
813 /* ID LED init */
814 mac->ops.id_led_init = e1000_id_led_init_pchlan;
815 /* setup LED */
816 mac->ops.setup_led = e1000_setup_led_pchlan;
817 /* cleanup LED */
818 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
819 /* turn on/off LED */
820 mac->ops.led_on = e1000_led_on_pchlan;
821 mac->ops.led_off = e1000_led_off_pchlan;
822 break;
823 default:
824 break;
825 }
826
827 if (mac->type >= e1000_pch_lpt) {
828 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
829 mac->ops.rar_set = e1000_rar_set_pch_lpt;
830 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
831 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
832 }
833
834 /* Enable PCS Lock-loss workaround for ICH8 */
835 if (mac->type == e1000_ich8lan)
836 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
837
838 return E1000_SUCCESS;
839}
840
850static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
851 u16 *data, bool read)
852{
853 s32 ret_val;
854
855 DEBUGFUNC("__e1000_access_emi_reg_locked");
856
857 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
858 if (ret_val)
859 return ret_val;
860
861 if (read)
862 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
863 data);
864 else
865 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
866 *data);
867
868 return ret_val;
869}
870
879s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
880{
881 DEBUGFUNC("e1000_read_emi_reg_locked");
882
883 return __e1000_access_emi_reg_locked(hw, addr, data, true);
884}
885
894s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
895{
896 DEBUGFUNC("e1000_read_emi_reg_locked");
897
898 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
899}
900
915s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
916{
917 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
918 s32 ret_val;
919 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
920
921 DEBUGFUNC("e1000_set_eee_pchlan");
922
923 switch (hw->phy.type) {
924 case e1000_phy_82579:
925 lpa = I82579_EEE_LP_ABILITY;
926 pcs_status = I82579_EEE_PCS_STATUS;
927 adv_addr = I82579_EEE_ADVERTISEMENT;
928 break;
929 case e1000_phy_i217:
930 lpa = I217_EEE_LP_ABILITY;
931 pcs_status = I217_EEE_PCS_STATUS;
932 adv_addr = I217_EEE_ADVERTISEMENT;
933 break;
934 default:
935 return E1000_SUCCESS;
936 }
937
938 ret_val = hw->phy.ops.acquire(hw);
939 if (ret_val)
940 return ret_val;
941
942 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
943 if (ret_val)
944 goto release;
945
946 /* Clear bits that enable EEE in various speeds */
947 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
948
949 /* Enable EEE if not disabled by user */
950 if (!dev_spec->eee_disable) {
951 /* Save off link partner's EEE ability */
952 ret_val = e1000_read_emi_reg_locked(hw, lpa,
953 &dev_spec->eee_lp_ability);
954 if (ret_val)
955 goto release;
956
957 /* Read EEE advertisement */
958 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
959 if (ret_val)
960 goto release;
961
962 /* Enable EEE only for speeds in which the link partner is
963 * EEE capable and for which we advertise EEE.
964 */
965 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
966 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
967
968 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
969 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
970 if (data & NWAY_LPAR_100TX_FD_CAPS)
971 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
972 else
973 /* EEE is not supported in 100Half, so ignore
974 * partner's EEE in 100 ability if full-duplex
975 * is not advertised.
976 */
977 dev_spec->eee_lp_ability &=
978 ~I82579_EEE_100_SUPPORTED;
979 }
980 }
981
982 if (hw->phy.type == e1000_phy_82579) {
983 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
984 &data);
985 if (ret_val)
986 goto release;
987
988 data &= ~I82579_LPI_100_PLL_SHUT;
989 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
990 data);
991 }
992
993 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
994 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
995 if (ret_val)
996 goto release;
997
998 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
999release:
1000 hw->phy.ops.release(hw);
1001
1002 return ret_val;
1003}
1004
1016static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1017{
1018 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1019 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1020 s32 ret_val = E1000_SUCCESS;
1021 u16 reg;
1022
1023 if (link && (status & E1000_STATUS_SPEED_1000)) {
1024 ret_val = hw->phy.ops.acquire(hw);
1025 if (ret_val)
1026 return ret_val;
1027
1028 ret_val =
1029 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1030 &reg);
1031 if (ret_val)
1032 goto release;
1033
1034 ret_val =
1035 e1000_write_kmrn_reg_locked(hw,
1036 E1000_KMRNCTRLSTA_K1_CONFIG,
1037 reg &
1038 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1039 if (ret_val)
1040 goto release;
1041
1042 usec_delay(10);
1043
1044 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1045 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1046
1047 ret_val =
1048 e1000_write_kmrn_reg_locked(hw,
1049 E1000_KMRNCTRLSTA_K1_CONFIG,
1050 reg);
1051release:
1052 hw->phy.ops.release(hw);
1053 } else {
1054 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1055 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1056
1057 if ((hw->phy.revision > 5) || !link ||
1058 ((status & E1000_STATUS_SPEED_100) &&
1059 (status & E1000_STATUS_FD)))
1060 goto update_fextnvm6;
1061
1062 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1063 if (ret_val)
1064 return ret_val;
1065
1066 /* Clear link status transmit timeout */
1067 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1068
1069 if (status & E1000_STATUS_SPEED_100) {
1070 /* Set inband Tx timeout to 5x10us for 100Half */
1071 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1072
1073 /* Do not extend the K1 entry latency for 100Half */
1074 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1075 } else {
1076 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1077 reg |= 50 <<
1078 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1079
1080 /* Extend the K1 entry latency for 10 Mbps */
1081 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1082 }
1083
1084 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1085 if (ret_val)
1086 return ret_val;
1087
1088update_fextnvm6:
1089 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1090 }
1091
1092 return ret_val;
1093}
1094
1095static u64 e1000_ltr2ns(u16 ltr)
1096{
1097 u32 value, scale;
1098
1099 /* Determine the latency in nsec based on the LTR value & scale */
1100 value = ltr & E1000_LTRV_VALUE_MASK;
1101 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1102
1103 return value * (1ULL << (scale * E1000_LTRV_SCALE_FACTOR));
1104}
1105
1125static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1126{
1127 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1128 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1129 u16 lat_enc = 0; /* latency encoded */
1130 s32 obff_hwm = 0;
1131
1132 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1133
1134 if (link) {
1135 u16 speed, duplex, scale = 0;
1136 u16 max_snoop, max_nosnoop;
1137 u16 max_ltr_enc; /* max LTR latency encoded */
1138 s64 lat_ns;
1139 s64 value;
1140 u32 rxa;
1141
1142 if (!hw->mac.max_frame_size) {
1143 DEBUGOUT("max_frame_size not set.\n");
1144 return -E1000_ERR_CONFIG;
1145 }
1146
1147 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1148 if (!speed) {
1149 DEBUGOUT("Speed not set.\n");
1150 return -E1000_ERR_CONFIG;
1151 }
1152
1153 /* Rx Packet Buffer Allocation size (KB) */
1154 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1155
1156 /* Determine the maximum latency tolerated by the device.
1157 *
1158 * Per the PCIe spec, the tolerated latencies are encoded as
1159 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1160 * a 10-bit value (0-1023) to provide a range from 1 ns to
1161 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1162 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1163 */
1164 lat_ns = ((s64)rxa * 1024 -
1165 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1166 if (lat_ns < 0)
1167 lat_ns = 0;
1168 else
1169 lat_ns /= speed;
1170 value = lat_ns;
1171
1172 while (value > E1000_LTRV_VALUE_MASK) {
1173 scale++;
1174 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1175 }
1176 if (scale > E1000_LTRV_SCALE_MAX) {
1177 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1178 return -E1000_ERR_CONFIG;
1179 }
1180 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1181
1182 /* Determine the maximum latency tolerated by the platform */
1183 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1184 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1185 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1186
1187 if (lat_enc > max_ltr_enc) {
1188 lat_enc = max_ltr_enc;
1189 lat_ns = e1000_ltr2ns(max_ltr_enc);
1190 }
1191
1192 if (lat_ns) {
1193 lat_ns *= speed * 1000;
1194 lat_ns /= 8;
1195 lat_ns /= 1000000000;
1196 obff_hwm = (s32)(rxa - lat_ns);
1197 }
1198 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1199 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1200 return -E1000_ERR_CONFIG;
1201 }
1202 }
1203
1204 /* Set Snoop and No-Snoop latencies the same */
1205 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1206 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1207
1208 /* Set OBFF high water mark */
1209 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1210 reg |= obff_hwm;
1211 E1000_WRITE_REG(hw, E1000_SVT, reg);
1212
1213 /* Enable OBFF */
1214 reg = E1000_READ_REG(hw, E1000_SVCR);
1215 reg |= E1000_SVCR_OFF_EN;
1216 /* Always unblock interrupts to the CPU even when the system is
1217 * in OBFF mode. This ensures that small round-robin traffic
1218 * (like ping) does not get dropped or experience long latency.
1219 */
1220 reg |= E1000_SVCR_OFF_MASKINT;
1221 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1222
1223 return E1000_SUCCESS;
1224}
1225
1233static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1234{
1235 u32 svcr;
1236 s32 timer;
1237
1238 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1239
1240 /* Convert ITR value into microseconds for OBFF timer */
1241 timer = itr & E1000_ITR_MASK;
1242 timer = (timer * E1000_ITR_MULT) / 1000;
1243
1244 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1245 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1246 return -E1000_ERR_CONFIG;
1247 }
1248
1249 svcr = E1000_READ_REG(hw, E1000_SVCR);
1250 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1251 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1252 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1253
1254 return E1000_SUCCESS;
1255}
1256
1267s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1268{
1269 u32 mac_reg;
1270 s32 ret_val = E1000_SUCCESS;
1271 u16 phy_reg;
1272 u16 oem_reg = 0;
1273
1274 if ((hw->mac.type < e1000_pch_lpt) ||
1275 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1276 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1277 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1278 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1279 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1280 return 0;
1281
1282 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1283 /* Request ME configure ULP mode in the PHY */
1284 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1285 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1286 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1287
1288 goto out;
1289 }
1290
1291 if (!to_sx) {
1292 int i = 0;
1293
1294 /* Poll up to 5 seconds for Cable Disconnected indication */
1295 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1296 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1297 /* Bail if link is re-acquired */
1298 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1299 return -E1000_ERR_PHY;
1300
1301 if (i++ == 100)
1302 break;
1303
1304 msec_delay(50);
1305 }
1306 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1307 (E1000_READ_REG(hw, E1000_FEXT) &
1308 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1309 i * 50);
1310 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1311 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1312 return 0;
1313
1314 }
1315
1316 ret_val = hw->phy.ops.acquire(hw);
1317 if (ret_val)
1318 goto out;
1319
1320 /* Force SMBus mode in PHY */
1321 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1322 if (ret_val)
1323 goto release;
1324 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1325 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1326
1327 /* Force SMBus mode in MAC */
1328 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1329 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1330 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1331
1332 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1333 * LPLU and disable Gig speed when entering ULP
1334 */
1335 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1336 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1337 &oem_reg);
1338 if (ret_val)
1339 goto release;
1340
1341 phy_reg = oem_reg;
1342 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1343
1344 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1345 phy_reg);
1346
1347 if (ret_val)
1348 goto release;
1349 }
1350
1351 /* Set Inband ULP Exit, Reset to SMBus mode and
1352 * Disable SMBus Release on PERST# in PHY
1353 */
1354 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1355 if (ret_val)
1356 goto release;
1357 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1358 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1359 if (to_sx) {
1360 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1361 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1362 else
1363 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1364
1365 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1366 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1367 } else {
1368 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1369 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1370 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1371 }
1372 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1373
1374 /* Set Disable SMBus Release on PERST# in MAC */
1375 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1376 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1377 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1378
1379 /* Commit ULP changes in PHY by starting auto ULP configuration */
1380 phy_reg |= I218_ULP_CONFIG1_START;
1381 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1382
1383 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1384 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1385 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1386 oem_reg);
1387 if (ret_val)
1388 goto release;
1389 }
1390
1391release:
1392 hw->phy.ops.release(hw);
1393out:
1394 if (ret_val)
1395 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1396 else
1397 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1398
1399 return ret_val;
1400}
1401
1417s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1418{
1419 s32 ret_val = E1000_SUCCESS;
1420 u8 ulp_exit_timeout = 30;
1421 u32 mac_reg;
1422 u16 phy_reg;
1423 int i = 0;
1424
1425 if ((hw->mac.type < e1000_pch_lpt) ||
1426 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1427 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1428 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1429 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1430 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1431 return 0;
1432
1433 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1434 if (force) {
1435 /* Request ME un-configure ULP mode in the PHY */
1436 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1437 mac_reg &= ~E1000_H2ME_ULP;
1438 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1439 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1440 }
1441
1442 if (hw->mac.type == e1000_pch_cnp)
1443 ulp_exit_timeout = 100;
1444
1445 while (E1000_READ_REG(hw, E1000_FWSM) &
1446 E1000_FWSM_ULP_CFG_DONE) {
1447 if (i++ == ulp_exit_timeout) {
1448 ret_val = -E1000_ERR_PHY;
1449 goto out;
1450 }
1451
1452 msec_delay(10);
1453 }
1454 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1455
1456 if (force) {
1457 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1458 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1459 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1460 } else {
1461 /* Clear H2ME.ULP after ME ULP configuration */
1462 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1463 mac_reg &= ~E1000_H2ME_ULP;
1464 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1465 }
1466
1467 goto out;
1468 }
1469
1470 ret_val = hw->phy.ops.acquire(hw);
1471 if (ret_val)
1472 goto out;
1473
1474 if (force)
1475 /* Toggle LANPHYPC Value bit */
1476 e1000_toggle_lanphypc_pch_lpt(hw);
1477
1478 /* Unforce SMBus mode in PHY */
1479 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1480 if (ret_val) {
1481 /* The MAC might be in PCIe mode, so temporarily force to
1482 * SMBus mode in order to access the PHY.
1483 */
1484 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1485 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1486 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1487
1488 msec_delay(50);
1489
1490 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1491 &phy_reg);
1492 if (ret_val)
1493 goto release;
1494 }
1495 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1496 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1497
1498 /* Unforce SMBus mode in MAC */
1499 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1500 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1501 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1502
1503 /* When ULP mode was previously entered, K1 was disabled by the
1504 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1505 */
1506 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1507 if (ret_val)
1508 goto release;
1509 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1510 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1511
1512 /* Clear ULP enabled configuration */
1513 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1514 if (ret_val)
1515 goto release;
1516 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1517 I218_ULP_CONFIG1_STICKY_ULP |
1518 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1519 I218_ULP_CONFIG1_WOL_HOST |
1520 I218_ULP_CONFIG1_INBAND_EXIT |
1521 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1522 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1523 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1524 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1525
1526 /* Commit ULP changes by starting auto ULP configuration */
1527 phy_reg |= I218_ULP_CONFIG1_START;
1528 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1529
1530 /* Clear Disable SMBus Release on PERST# in MAC */
1531 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1532 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1533 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1534
1535release:
1536 hw->phy.ops.release(hw);
1537 if (force) {
1538 hw->phy.ops.reset(hw);
1539 msec_delay(50);
1540 }
1541out:
1542 if (ret_val)
1543 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1544 else
1545 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1546
1547 return ret_val;
1548}
1549
1558static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1559{
1560 struct e1000_mac_info *mac = &hw->mac;
1561 s32 ret_val, tipg_reg = 0;
1562 u16 emi_addr, emi_val = 0;
1563 bool link;
1564 u16 phy_reg;
1565
1566 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1567
1568 /* We only want to go out to the PHY registers to see if Auto-Neg
1569 * has completed and/or if our link status has changed. The
1570 * get_link_status flag is set upon receiving a Link Status
1571 * Change or Rx Sequence Error interrupt.
1572 */
1573 if (!mac->get_link_status)
1574 return E1000_SUCCESS;
1575
1576 /* First we want to see if the MII Status Register reports
1577 * link. If so, then we want to get the current speed/duplex
1578 * of the PHY.
1579 */
1580 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1581 if (ret_val)
1582 return ret_val;
1583
1584 if (hw->mac.type == e1000_pchlan) {
1585 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1586 if (ret_val)
1587 return ret_val;
1588 }
1589
1590 /* When connected at 10Mbps half-duplex, some parts are excessively
1591 * aggressive resulting in many collisions. To avoid this, increase
1592 * the IPG and reduce Rx latency in the PHY.
1593 */
1594 if ((hw->mac.type >= e1000_pch2lan) && link) {
1595 u16 speed, duplex;
1596
1597 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1598 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1599 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1600
1601 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1602 tipg_reg |= 0xFF;
1603 /* Reduce Rx latency in analog PHY */
1604 emi_val = 0;
1605 } else if (hw->mac.type >= e1000_pch_spt &&
1606 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1607 tipg_reg |= 0xC;
1608 emi_val = 1;
1609 } else {
1610 /* Roll back the default values */
1611 tipg_reg |= 0x08;
1612 emi_val = 1;
1613 }
1614
1615 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1616
1617 ret_val = hw->phy.ops.acquire(hw);
1618 if (ret_val)
1619 return ret_val;
1620
1621 if (hw->mac.type == e1000_pch2lan)
1622 emi_addr = I82579_RX_CONFIG;
1623 else
1624 emi_addr = I217_RX_CONFIG;
1625 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1626
1627
1628 if (hw->mac.type >= e1000_pch_lpt) {
1629 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1630 &phy_reg);
1631 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1632 if (speed == SPEED_100 || speed == SPEED_10)
1633 phy_reg |= 0x3E8;
1634 else
1635 phy_reg |= 0xFA;
1636 hw->phy.ops.write_reg_locked(hw,
1637 I217_PLL_CLOCK_GATE_REG,
1638 phy_reg);
1639
1640 if (speed == SPEED_1000) {
1641 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1642 &phy_reg);
1643
1644 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1645
1646 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1647 phy_reg);
1648 }
1649 }
1650 hw->phy.ops.release(hw);
1651
1652 if (ret_val)
1653 return ret_val;
1654
1655 if (hw->mac.type >= e1000_pch_spt) {
1656 u16 data;
1657 u16 ptr_gap;
1658
1659 if (speed == SPEED_1000) {
1660 ret_val = hw->phy.ops.acquire(hw);
1661 if (ret_val)
1662 return ret_val;
1663
1664 ret_val = hw->phy.ops.read_reg_locked(hw,
1665 PHY_REG(776, 20),
1666 &data);
1667 if (ret_val) {
1668 hw->phy.ops.release(hw);
1669 return ret_val;
1670 }
1671
1672 ptr_gap = (data & (0x3FF << 2)) >> 2;
1673 if (ptr_gap < 0x18) {
1674 data &= ~(0x3FF << 2);
1675 data |= (0x18 << 2);
1676 ret_val =
1677 hw->phy.ops.write_reg_locked(hw,
1678 PHY_REG(776, 20), data);
1679 }
1680 hw->phy.ops.release(hw);
1681 if (ret_val)
1682 return ret_val;
1683 } else {
1684 ret_val = hw->phy.ops.acquire(hw);
1685 if (ret_val)
1686 return ret_val;
1687
1688 ret_val = hw->phy.ops.write_reg_locked(hw,
1689 PHY_REG(776, 20),
1690 0xC023);
1691 hw->phy.ops.release(hw);
1692 if (ret_val)
1693 return ret_val;
1694
1695 }
1696 }
1697 }
1698
1699 /* I217 Packet Loss issue:
1700 * ensure that FEXTNVM4 Beacon Duration is set correctly
1701 * on power up.
1702 * Set the Beacon Duration for I217 to 8 usec
1703 */
1704 if (hw->mac.type >= e1000_pch_lpt) {
1705 u32 mac_reg;
1706
1707 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1708 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1709 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1710 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1711 }
1712
1713 /* Work-around I218 hang issue */
1714 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1715 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1716 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1717 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1718 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1719 if (ret_val)
1720 return ret_val;
1721 }
1722 if (hw->mac.type >= e1000_pch_lpt) {
1723 /* Set platform power management values for
1724 * Latency Tolerance Reporting (LTR)
1725 * Optimized Buffer Flush/Fill (OBFF)
1726 */
1727 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1728 if (ret_val)
1729 return ret_val;
1730 }
1731 /* Clear link partner's EEE ability */
1732 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1733
1734 if (hw->mac.type >= e1000_pch_lpt) {
1735 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1736
1737 if (hw->mac.type == e1000_pch_spt) {
1738 /* FEXTNVM6 K1-off workaround - for SPT only */
1739 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1740
1741 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1742 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1743 else
1744 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1745 }
1746
1747 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1748 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1749
1750 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1751
1752 /* Configure K0s minimum time */
1753 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1754 }
1755
1756 if (!link)
1757 return E1000_SUCCESS; /* No link detected */
1758
1759 mac->get_link_status = false;
1760
1761 switch (hw->mac.type) {
1762 case e1000_pch2lan:
1763 ret_val = e1000_k1_workaround_lv(hw);
1764 if (ret_val)
1765 return ret_val;
1766 /* FALLTHROUGH */
1767 case e1000_pchlan:
1768 if (hw->phy.type == e1000_phy_82578) {
1769 ret_val = e1000_link_stall_workaround_hv(hw);
1770 if (ret_val)
1771 return ret_val;
1772 }
1773
1774 /* Workaround for PCHx parts in half-duplex:
1775 * Set the number of preambles removed from the packet
1776 * when it is passed from the PHY to the MAC to prevent
1777 * the MAC from misinterpreting the packet type.
1778 */
1779 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1780 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1781
1782 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1783 E1000_STATUS_FD)
1784 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1785
1786 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1787 break;
1788 default:
1789 break;
1790 }
1791
1792 /* Check if there was DownShift, must be checked
1793 * immediately after link-up
1794 */
1795 e1000_check_downshift_generic(hw);
1796
1797 /* Enable/Disable EEE after link up */
1798 if (hw->phy.type > e1000_phy_82579) {
1799 ret_val = e1000_set_eee_pchlan(hw);
1800 if (ret_val)
1801 return ret_val;
1802 }
1803
1804 /* If we are forcing speed/duplex, then we simply return since
1805 * we have already determined whether we have link or not.
1806 */
1807 if (!mac->autoneg)
1808 return -E1000_ERR_CONFIG;
1809
1810 /* Auto-Neg is enabled. Auto Speed Detection takes care
1811 * of MAC speed/duplex configuration. So we only need to
1812 * configure Collision Distance in the MAC.
1813 */
1814 mac->ops.config_collision_dist(hw);
1815
1816 /* Configure Flow Control now that Auto-Neg has completed.
1817 * First, we need to restore the desired flow control
1818 * settings because we may have had to re-autoneg with a
1819 * different link partner.
1820 */
1821 ret_val = e1000_config_fc_after_link_up_generic(hw);
1822 if (ret_val)
1823 DEBUGOUT("Error configuring flow control\n");
1824
1825 return ret_val;
1826}
1827
1834void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1835{
1836 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1837
1838 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1839 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1840 switch (hw->mac.type) {
1841 case e1000_ich8lan:
1842 case e1000_ich9lan:
1843 case e1000_ich10lan:
1844 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1845 break;
1846 case e1000_pchlan:
1847 case e1000_pch2lan:
1848 case e1000_pch_lpt:
1849 case e1000_pch_spt:
1850 case e1000_pch_cnp:
1851 case e1000_pch_tgp:
1852 case e1000_pch_adp:
1853 case e1000_pch_mtp:
1854 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1855 break;
1856 default:
1857 break;
1858 }
1859}
1860
1867static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1868{
1869 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1870
1871 ASSERT_CTX_LOCK_HELD(hw);
1872
1873 return E1000_SUCCESS;
1874}
1875
1882static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1883{
1884 DEBUGFUNC("e1000_release_nvm_ich8lan");
1885
1886 ASSERT_CTX_LOCK_HELD(hw);
1887}
1888
1896static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1897{
1898 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1899 s32 ret_val = E1000_SUCCESS;
1900
1901 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1902
1903 ASSERT_CTX_LOCK_HELD(hw);
1904
1905 while (timeout) {
1906 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1907 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1908 break;
1909
1910 msec_delay_irq(1);
1911 timeout--;
1912 }
1913
1914 if (!timeout) {
1915 DEBUGOUT("SW has already locked the resource.\n");
1916 ret_val = -E1000_ERR_CONFIG;
1917 goto out;
1918 }
1919
1920 timeout = SW_FLAG_TIMEOUT;
1921
1922 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1923 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1924
1925 while (timeout) {
1926 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1927 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1928 break;
1929
1930 msec_delay_irq(1);
1931 timeout--;
1932 }
1933
1934 if (!timeout) {
1935 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1936 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1937 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1938 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1939 ret_val = -E1000_ERR_CONFIG;
1940 goto out;
1941 }
1942
1943out:
1944 return ret_val;
1945}
1946
1954static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1955{
1956 u32 extcnf_ctrl;
1957
1958 DEBUGFUNC("e1000_release_swflag_ich8lan");
1959
1960 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1961
1962 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1963 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1964 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1965 } else {
1966 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1967 }
1968}
1969
1978static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1979{
1980 u32 fwsm;
1981
1982 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1983
1984 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1985
1986 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1987 ((fwsm & E1000_FWSM_MODE_MASK) ==
1988 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1989}
1990
1999static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
2000{
2001 u32 fwsm;
2002
2003 DEBUGFUNC("e1000_check_mng_mode_pchlan");
2004
2005 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2006
2007 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
2008 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
2009}
2010
2022static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2023{
2024 u32 rar_low, rar_high;
2025
2026 DEBUGFUNC("e1000_rar_set_pch2lan");
2027
2028 /* HW expects these in little endian so we reverse the byte order
2029 * from network order (big endian) to little endian
2030 */
2031 rar_low = ((u32) addr[0] |
2032 ((u32) addr[1] << 8) |
2033 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2034
2035 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2036
2037 /* If MAC address zero, no need to set the AV bit */
2038 if (rar_low || rar_high)
2039 rar_high |= E1000_RAH_AV;
2040
2041 if (index == 0) {
2042 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2043 E1000_WRITE_FLUSH(hw);
2044 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2045 E1000_WRITE_FLUSH(hw);
2046 return E1000_SUCCESS;
2047 }
2048
2049 /* RAR[1-6] are owned by manageability. Skip those and program the
2050 * next address into the SHRA register array.
2051 */
2052 if (index < (u32) (hw->mac.rar_entry_count)) {
2053 s32 ret_val;
2054
2055 ret_val = e1000_acquire_swflag_ich8lan(hw);
2056 if (ret_val)
2057 goto out;
2058
2059 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2060 E1000_WRITE_FLUSH(hw);
2061 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2062 E1000_WRITE_FLUSH(hw);
2063
2064 e1000_release_swflag_ich8lan(hw);
2065
2066 /* verify the register updates */
2067 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2068 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2069 return E1000_SUCCESS;
2070
2071 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2072 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2073 }
2074
2075out:
2076 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2077 return -E1000_ERR_CONFIG;
2078}
2079
2091static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2092{
2093 u32 rar_low, rar_high;
2094 u32 wlock_mac;
2095
2096 DEBUGFUNC("e1000_rar_set_pch_lpt");
2097
2098 /* HW expects these in little endian so we reverse the byte order
2099 * from network order (big endian) to little endian
2100 */
2101 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2102 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2103
2104 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2105
2106 /* If MAC address zero, no need to set the AV bit */
2107 if (rar_low || rar_high)
2108 rar_high |= E1000_RAH_AV;
2109
2110 if (index == 0) {
2111 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2112 E1000_WRITE_FLUSH(hw);
2113 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2114 E1000_WRITE_FLUSH(hw);
2115 return E1000_SUCCESS;
2116 }
2117
2118 /* The manageability engine (ME) can lock certain SHRAR registers that
2119 * it is using - those registers are unavailable for use.
2120 */
2121 if (index < hw->mac.rar_entry_count) {
2122 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2123 E1000_FWSM_WLOCK_MAC_MASK;
2124 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2125
2126 /* Check if all SHRAR registers are locked */
2127 if (wlock_mac == 1)
2128 goto out;
2129
2130 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2131 s32 ret_val;
2132
2133 ret_val = e1000_acquire_swflag_ich8lan(hw);
2134
2135 if (ret_val)
2136 goto out;
2137
2138 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2139 rar_low);
2140 E1000_WRITE_FLUSH(hw);
2141 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2142 rar_high);
2143 E1000_WRITE_FLUSH(hw);
2144
2145 e1000_release_swflag_ich8lan(hw);
2146
2147 /* verify the register updates */
2148 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2149 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2150 return E1000_SUCCESS;
2151 }
2152 }
2153
2154out:
2155 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2156 return -E1000_ERR_CONFIG;
2157}
2158
2168static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2169 u8 *mc_addr_list,
2170 u32 mc_addr_count)
2171{
2172 u16 phy_reg = 0;
2173 int i;
2174 s32 ret_val;
2175
2176 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2177
2178 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2179
2180 ret_val = hw->phy.ops.acquire(hw);
2181 if (ret_val)
2182 return;
2183
2184 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2185 if (ret_val)
2186 goto release;
2187
2188 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2189 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2190 (u16)(hw->mac.mta_shadow[i] &
2191 0xFFFF));
2192 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2193 (u16)((hw->mac.mta_shadow[i] >> 16) &
2194 0xFFFF));
2195 }
2196
2197 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2198
2199release:
2200 hw->phy.ops.release(hw);
2201}
2202
2211static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2212{
2213 u32 fwsm;
2214 bool blocked = false;
2215 int i = 0;
2216
2217 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2218
2219 do {
2220 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2221 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2222 blocked = true;
2223 msec_delay(10);
2224 continue;
2225 }
2226 blocked = false;
2227 } while (blocked && (i++ < 30));
2228 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2229}
2230
2238static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2239{
2240 u16 phy_data;
2241 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2242 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2243 E1000_STRAP_SMT_FREQ_SHIFT;
2244 s32 ret_val;
2245
2246 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2247
2248 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2249 if (ret_val)
2250 return ret_val;
2251
2252 phy_data &= ~HV_SMB_ADDR_MASK;
2253 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2254 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2255
2256 if (hw->phy.type == e1000_phy_i217) {
2257 /* Restore SMBus frequency */
2258 if (freq--) {
2259 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2260 phy_data |= (freq & (1 << 0)) <<
2261 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2262 phy_data |= (freq & (1 << 1)) <<
2263 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2264 } else {
2265 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2266 }
2267 }
2268
2269 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2270}
2271
2279static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2280{
2281 struct e1000_phy_info *phy = &hw->phy;
2282 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2283 s32 ret_val = E1000_SUCCESS;
2284 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2285
2286 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2287
2288 /* Initialize the PHY from the NVM on ICH platforms. This
2289 * is needed due to an issue where the NVM configuration is
2290 * not properly autoloaded after power transitions.
2291 * Therefore, after each PHY reset, we will load the
2292 * configuration data out of the NVM manually.
2293 */
2294 switch (hw->mac.type) {
2295 case e1000_ich8lan:
2296 if (phy->type != e1000_phy_igp_3)
2297 return ret_val;
2298
2299 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2300 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2301 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2302 break;
2303 }
2304 /* FALLTHROUGH */
2305 case e1000_pchlan:
2306 case e1000_pch2lan:
2307 case e1000_pch_lpt:
2308 case e1000_pch_spt:
2309 case e1000_pch_cnp:
2310 case e1000_pch_tgp:
2311 case e1000_pch_adp:
2312 case e1000_pch_mtp:
2313 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2314 break;
2315 default:
2316 return ret_val;
2317 }
2318
2319 ret_val = hw->phy.ops.acquire(hw);
2320 if (ret_val)
2321 return ret_val;
2322
2323 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2324 if (!(data & sw_cfg_mask))
2325 goto release;
2326
2327 /* Make sure HW does not configure LCD from PHY
2328 * extended configuration before SW configuration
2329 */
2330 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2331 if ((hw->mac.type < e1000_pch2lan) &&
2332 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2333 goto release;
2334
2335 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2336 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2337 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2338 if (!cnf_size)
2339 goto release;
2340
2341 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2342 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2343
2344 if (((hw->mac.type == e1000_pchlan) &&
2345 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2346 (hw->mac.type > e1000_pchlan)) {
2347 /* HW configures the SMBus address and LEDs when the
2348 * OEM and LCD Write Enable bits are set in the NVM.
2349 * When both NVM bits are cleared, SW will configure
2350 * them instead.
2351 */
2352 ret_val = e1000_write_smbus_addr(hw);
2353 if (ret_val)
2354 goto release;
2355
2356 data = E1000_READ_REG(hw, E1000_LEDCTL);
2357 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2358 (u16)data);
2359 if (ret_val)
2360 goto release;
2361 }
2362
2363 /* Configure LCD from extended configuration region. */
2364
2365 /* cnf_base_addr is in DWORD */
2366 word_addr = (u16)(cnf_base_addr << 1);
2367
2368 for (i = 0; i < cnf_size; i++) {
2369 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2370 &reg_data);
2371 if (ret_val)
2372 goto release;
2373
2374 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2375 1, &reg_addr);
2376 if (ret_val)
2377 goto release;
2378
2379 /* Save off the PHY page for future writes. */
2380 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2381 phy_page = reg_data;
2382 continue;
2383 }
2384
2385 reg_addr &= PHY_REG_MASK;
2386 reg_addr |= phy_page;
2387
2388 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2389 reg_data);
2390 if (ret_val)
2391 goto release;
2392 }
2393
2394release:
2395 hw->phy.ops.release(hw);
2396 return ret_val;
2397}
2398
2409static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2410{
2411 s32 ret_val = E1000_SUCCESS;
2412 u16 status_reg = 0;
2413 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2414
2415 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2416
2417 if (hw->mac.type != e1000_pchlan)
2418 return E1000_SUCCESS;
2419
2420 /* Wrap the whole flow with the sw flag */
2421 ret_val = hw->phy.ops.acquire(hw);
2422 if (ret_val)
2423 return ret_val;
2424
2425 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2426 if (link) {
2427 if (hw->phy.type == e1000_phy_82578) {
2428 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2429 &status_reg);
2430 if (ret_val)
2431 goto release;
2432
2433 status_reg &= (BM_CS_STATUS_LINK_UP |
2434 BM_CS_STATUS_RESOLVED |
2435 BM_CS_STATUS_SPEED_MASK);
2436
2437 if (status_reg == (BM_CS_STATUS_LINK_UP |
2438 BM_CS_STATUS_RESOLVED |
2439 BM_CS_STATUS_SPEED_1000))
2440 k1_enable = false;
2441 }
2442
2443 if (hw->phy.type == e1000_phy_82577) {
2444 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2445 &status_reg);
2446 if (ret_val)
2447 goto release;
2448
2449 status_reg &= (HV_M_STATUS_LINK_UP |
2450 HV_M_STATUS_AUTONEG_COMPLETE |
2451 HV_M_STATUS_SPEED_MASK);
2452
2453 if (status_reg == (HV_M_STATUS_LINK_UP |
2454 HV_M_STATUS_AUTONEG_COMPLETE |
2455 HV_M_STATUS_SPEED_1000))
2456 k1_enable = false;
2457 }
2458
2459 /* Link stall fix for link up */
2460 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2461 0x0100);
2462 if (ret_val)
2463 goto release;
2464
2465 } else {
2466 /* Link stall fix for link down */
2467 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2468 0x4100);
2469 if (ret_val)
2470 goto release;
2471 }
2472
2473 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2474
2475release:
2476 hw->phy.ops.release(hw);
2477
2478 return ret_val;
2479}
2480
2491s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2492{
2493 s32 ret_val;
2494 u32 ctrl_reg = 0;
2495 u32 ctrl_ext = 0;
2496 u32 reg = 0;
2497 u16 kmrn_reg = 0;
2498
2499 DEBUGFUNC("e1000_configure_k1_ich8lan");
2500
2501 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2502 &kmrn_reg);
2503 if (ret_val)
2504 return ret_val;
2505
2506 if (k1_enable)
2507 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2508 else
2509 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2510
2511 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2512 kmrn_reg);
2513 if (ret_val)
2514 return ret_val;
2515
2516 usec_delay(20);
2517 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2518 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2519
2520 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2521 reg |= E1000_CTRL_FRCSPD;
2522 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2523
2524 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2525 E1000_WRITE_FLUSH(hw);
2526 usec_delay(20);
2527 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2528 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2529 E1000_WRITE_FLUSH(hw);
2530 usec_delay(20);
2531
2532 return E1000_SUCCESS;
2533}
2534
2544static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2545{
2546 s32 ret_val = 0;
2547 u32 mac_reg;
2548 u16 oem_reg;
2549
2550 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2551
2552 if (hw->mac.type < e1000_pchlan)
2553 return ret_val;
2554
2555 ret_val = hw->phy.ops.acquire(hw);
2556 if (ret_val)
2557 return ret_val;
2558
2559 if (hw->mac.type == e1000_pchlan) {
2560 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2561 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2562 goto release;
2563 }
2564
2565 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2566 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2567 goto release;
2568
2569 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2570
2571 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2572 if (ret_val)
2573 goto release;
2574
2575 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2576
2577 if (d0_state) {
2578 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2579 oem_reg |= HV_OEM_BITS_GBE_DIS;
2580
2581 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2582 oem_reg |= HV_OEM_BITS_LPLU;
2583 } else {
2584 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2585 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2586 oem_reg |= HV_OEM_BITS_GBE_DIS;
2587
2588 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2589 E1000_PHY_CTRL_NOND0A_LPLU))
2590 oem_reg |= HV_OEM_BITS_LPLU;
2591 }
2592
2593 /* Set Restart auto-neg to activate the bits */
2594 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2595 !hw->phy.ops.check_reset_block(hw))
2596 oem_reg |= HV_OEM_BITS_RESTART_AN;
2597
2598 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2599
2600release:
2601 hw->phy.ops.release(hw);
2602
2603 return ret_val;
2604}
2605
2606
2611static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2612{
2613 s32 ret_val;
2614 u16 data;
2615
2616 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2617
2618 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2619 if (ret_val)
2620 return ret_val;
2621
2622 data |= HV_KMRN_MDIO_SLOW;
2623
2624 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2625
2626 return ret_val;
2627}
2628
2634static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2635{
2636 s32 ret_val = E1000_SUCCESS;
2637 u16 phy_data;
2638
2639 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2640
2641 if (hw->mac.type != e1000_pchlan)
2642 return E1000_SUCCESS;
2643
2644 /* Set MDIO slow mode before any other MDIO access */
2645 if (hw->phy.type == e1000_phy_82577) {
2646 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2647 if (ret_val)
2648 return ret_val;
2649 }
2650
2651 if (((hw->phy.type == e1000_phy_82577) &&
2652 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2653 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2654 /* Disable generation of early preamble */
2655 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2656 if (ret_val)
2657 return ret_val;
2658
2659 /* Preamble tuning for SSC */
2660 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2661 0xA204);
2662 if (ret_val)
2663 return ret_val;
2664 }
2665
2666 if (hw->phy.type == e1000_phy_82578) {
2667 /* Return registers to default by doing a soft reset then
2668 * writing 0x3140 to the control register.
2669 */
2670 if (hw->phy.revision < 2) {
2671 e1000_phy_sw_reset_generic(hw);
2672 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2673 0x3140);
2674 if (ret_val)
2675 return ret_val;
2676 }
2677 }
2678
2679 /* Select page 0 */
2680 ret_val = hw->phy.ops.acquire(hw);
2681 if (ret_val)
2682 return ret_val;
2683
2684 hw->phy.addr = 1;
2685 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2686 hw->phy.ops.release(hw);
2687 if (ret_val)
2688 return ret_val;
2689
2690 /* Configure the K1 Si workaround during phy reset assuming there is
2691 * link so that it disables K1 if link is in 1Gbps.
2692 */
2693 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2694 if (ret_val)
2695 return ret_val;
2696
2697 /* Workaround for link disconnects on a busy hub in half duplex */
2698 ret_val = hw->phy.ops.acquire(hw);
2699 if (ret_val)
2700 return ret_val;
2701 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2702 if (ret_val)
2703 goto release;
2704 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2705 phy_data & 0x00FF);
2706 if (ret_val)
2707 goto release;
2708
2709 /* set MSE higher to enable link to stay up when noise is high */
2710 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2711release:
2712 hw->phy.ops.release(hw);
2713
2714 return ret_val;
2715}
2716
2721void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2722{
2723 u32 mac_reg;
2724 u16 i, phy_reg = 0;
2725 s32 ret_val;
2726
2727 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2728
2729 ret_val = hw->phy.ops.acquire(hw);
2730 if (ret_val)
2731 return;
2732 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2733 if (ret_val)
2734 goto release;
2735
2736 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2737 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2738 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2739 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2740 (u16)(mac_reg & 0xFFFF));
2741 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2742 (u16)((mac_reg >> 16) & 0xFFFF));
2743
2744 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2745 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2746 (u16)(mac_reg & 0xFFFF));
2747 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2748 (u16)((mac_reg & E1000_RAH_AV)
2749 >> 16));
2750 }
2751
2752 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2753
2754release:
2755 hw->phy.ops.release(hw);
2756}
2757
2758static u32 e1000_calc_rx_da_crc(u8 mac[])
2759{
2760 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2761 u32 i, j, mask, crc;
2762
2763 DEBUGFUNC("e1000_calc_rx_da_crc");
2764
2765 crc = 0xffffffff;
2766 for (i = 0; i < 6; i++) {
2767 crc = crc ^ mac[i];
2768 for (j = 8; j > 0; j--) {
2769 mask = (crc & 1) * (-1);
2770 crc = (crc >> 1) ^ (poly & mask);
2771 }
2772 }
2773 return ~crc;
2774}
2775
2782s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2783{
2784 s32 ret_val = E1000_SUCCESS;
2785 u16 phy_reg, data;
2786 u32 mac_reg;
2787 u16 i;
2788
2789 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2790
2791 if (hw->mac.type < e1000_pch2lan)
2792 return E1000_SUCCESS;
2793
2794 /* disable Rx path while enabling/disabling workaround */
2795 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2796 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2797 phy_reg | (1 << 14));
2798 if (ret_val)
2799 return ret_val;
2800
2801 if (enable) {
2802 /* Write Rx addresses (rar_entry_count for RAL/H, and
2803 * SHRAL/H) and initial CRC values to the MAC
2804 */
2805 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2806 u8 mac_addr[ETHER_ADDR_LEN] = {0};
2807 u32 addr_high, addr_low;
2808
2809 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2810 if (!(addr_high & E1000_RAH_AV))
2811 continue;
2812 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2813 mac_addr[0] = (addr_low & 0xFF);
2814 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2815 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2816 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2817 mac_addr[4] = (addr_high & 0xFF);
2818 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2819
2820 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2821 e1000_calc_rx_da_crc(mac_addr));
2822 }
2823
2824 /* Write Rx addresses to the PHY */
2825 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2826
2827 /* Enable jumbo frame workaround in the MAC */
2828 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2829 mac_reg &= ~(1 << 14);
2830 mac_reg |= (7 << 15);
2831 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2832
2833 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2834 mac_reg |= E1000_RCTL_SECRC;
2835 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2836
2837 ret_val = e1000_read_kmrn_reg_generic(hw,
2838 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2839 &data);
2840 if (ret_val)
2841 return ret_val;
2842 ret_val = e1000_write_kmrn_reg_generic(hw,
2843 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2844 data | (1 << 0));
2845 if (ret_val)
2846 return ret_val;
2847 ret_val = e1000_read_kmrn_reg_generic(hw,
2848 E1000_KMRNCTRLSTA_HD_CTRL,
2849 &data);
2850 if (ret_val)
2851 return ret_val;
2852 data &= ~(0xF << 8);
2853 data |= (0xB << 8);
2854 ret_val = e1000_write_kmrn_reg_generic(hw,
2855 E1000_KMRNCTRLSTA_HD_CTRL,
2856 data);
2857 if (ret_val)
2858 return ret_val;
2859
2860 /* Enable jumbo frame workaround in the PHY */
2861 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2862 data &= ~(0x7F << 5);
2863 data |= (0x37 << 5);
2864 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2865 if (ret_val)
2866 return ret_val;
2867 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2868 data &= ~(1 << 13);
2869 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2870 if (ret_val)
2871 return ret_val;
2872 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2873 data &= ~(0x3FF << 2);
2874 data |= (E1000_TX_PTR_GAP << 2);
2875 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2876 if (ret_val)
2877 return ret_val;
2878 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2879 if (ret_val)
2880 return ret_val;
2881 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2882 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2883 (1 << 10));
2884 if (ret_val)
2885 return ret_val;
2886 } else {
2887 /* Write MAC register values back to h/w defaults */
2888 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2889 mac_reg &= ~(0xF << 14);
2890 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2891
2892 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2893 mac_reg &= ~E1000_RCTL_SECRC;
2894 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2895
2896 ret_val = e1000_read_kmrn_reg_generic(hw,
2897 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2898 &data);
2899 if (ret_val)
2900 return ret_val;
2901 ret_val = e1000_write_kmrn_reg_generic(hw,
2902 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2903 data & ~(1 << 0));
2904 if (ret_val)
2905 return ret_val;
2906 ret_val = e1000_read_kmrn_reg_generic(hw,
2907 E1000_KMRNCTRLSTA_HD_CTRL,
2908 &data);
2909 if (ret_val)
2910 return ret_val;
2911 data &= ~(0xF << 8);
2912 data |= (0xB << 8);
2913 ret_val = e1000_write_kmrn_reg_generic(hw,
2914 E1000_KMRNCTRLSTA_HD_CTRL,
2915 data);
2916 if (ret_val)
2917 return ret_val;
2918
2919 /* Write PHY register values back to h/w defaults */
2920 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2921 data &= ~(0x7F << 5);
2922 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2923 if (ret_val)
2924 return ret_val;
2925 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2926 data |= (1 << 13);
2927 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2928 if (ret_val)
2929 return ret_val;
2930 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2931 data &= ~(0x3FF << 2);
2932 data |= (0x8 << 2);
2933 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2934 if (ret_val)
2935 return ret_val;
2936 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2937 if (ret_val)
2938 return ret_val;
2939 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2940 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2941 ~(1 << 10));
2942 if (ret_val)
2943 return ret_val;
2944 }
2945
2946 /* re-enable Rx path after enabling/disabling workaround */
2947 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2948 ~(1 << 14));
2949}
2950
2956static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2957{
2958 s32 ret_val = E1000_SUCCESS;
2959
2960 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2961
2962 if (hw->mac.type != e1000_pch2lan)
2963 return E1000_SUCCESS;
2964
2965 /* Set MDIO slow mode before any other MDIO access */
2966 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2967 if (ret_val)
2968 return ret_val;
2969
2970 ret_val = hw->phy.ops.acquire(hw);
2971 if (ret_val)
2972 return ret_val;
2973 /* set MSE higher to enable link to stay up when noise is high */
2974 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2975 if (ret_val)
2976 goto release;
2977 /* drop link after 5 times MSE threshold was reached */
2978 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2979release:
2980 hw->phy.ops.release(hw);
2981
2982 return ret_val;
2983}
2984
2992static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2993{
2994 s32 ret_val = E1000_SUCCESS;
2995 u16 status_reg = 0;
2996
2997 DEBUGFUNC("e1000_k1_workaround_lv");
2998
2999 if (hw->mac.type != e1000_pch2lan)
3000 return E1000_SUCCESS;
3001
3002 /* Set K1 beacon duration based on 10Mbs speed */
3003 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
3004 if (ret_val)
3005 return ret_val;
3006
3007 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
3008 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
3009 if (status_reg &
3010 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
3011 u16 pm_phy_reg;
3012
3013 /* LV 1G/100 Packet drop issue wa */
3014 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3015 &pm_phy_reg);
3016 if (ret_val)
3017 return ret_val;
3018 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
3019 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3020 pm_phy_reg);
3021 if (ret_val)
3022 return ret_val;
3023 } else {
3024 u32 mac_reg;
3025 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3026 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
3027 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
3028 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3029 }
3030 }
3031
3032 return ret_val;
3033}
3034
3043static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3044{
3045 u32 extcnf_ctrl;
3046
3047 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3048
3049 if (hw->mac.type < e1000_pch2lan)
3050 return;
3051
3052 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3053
3054 if (gate)
3055 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3056 else
3057 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3058
3059 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3060}
3061
3069static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3070{
3071 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3072
3073 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3074
3075 /* Wait for basic configuration completes before proceeding */
3076 do {
3077 data = E1000_READ_REG(hw, E1000_STATUS);
3078 data &= E1000_STATUS_LAN_INIT_DONE;
3079 usec_delay(100);
3080 } while ((!data) && --loop);
3081
3082 /* If basic configuration is incomplete before the above loop
3083 * count reaches 0, loading the configuration from NVM will
3084 * leave the PHY in a bad state possibly resulting in no link.
3085 */
3086 if (loop == 0)
3087 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3088
3089 /* Clear the Init Done bit for the next init event */
3090 data = E1000_READ_REG(hw, E1000_STATUS);
3091 data &= ~E1000_STATUS_LAN_INIT_DONE;
3092 E1000_WRITE_REG(hw, E1000_STATUS, data);
3093}
3094
3099static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3100{
3101 s32 ret_val = E1000_SUCCESS;
3102 u16 reg;
3103
3104 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3105
3106 if (hw->phy.ops.check_reset_block(hw))
3107 return E1000_SUCCESS;
3108
3109 /* Allow time for h/w to get to quiescent state after reset */
3110 msec_delay(10);
3111
3112 /* Perform any necessary post-reset workarounds */
3113 switch (hw->mac.type) {
3114 case e1000_pchlan:
3115 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3116 if (ret_val)
3117 return ret_val;
3118 break;
3119 case e1000_pch2lan:
3120 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3121 if (ret_val)
3122 return ret_val;
3123 break;
3124 default:
3125 break;
3126 }
3127
3128 /* Clear the host wakeup bit after lcd reset */
3129 if (hw->mac.type >= e1000_pchlan) {
3130 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3131 reg &= ~BM_WUC_HOST_WU_BIT;
3132 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3133 }
3134
3135 /* Configure the LCD with the extended configuration region in NVM */
3136 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3137 if (ret_val)
3138 return ret_val;
3139
3140 /* Configure the LCD with the OEM bits in NVM */
3141 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3142
3143 if (hw->mac.type == e1000_pch2lan) {
3144 /* Ungate automatic PHY configuration on non-managed 82579 */
3145 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3146 E1000_ICH_FWSM_FW_VALID)) {
3147 msec_delay(10);
3148 e1000_gate_hw_phy_config_ich8lan(hw, false);
3149 }
3150
3151 /* Set EEE LPI Update Timer to 200usec */
3152 ret_val = hw->phy.ops.acquire(hw);
3153 if (ret_val)
3154 return ret_val;
3155 ret_val = e1000_write_emi_reg_locked(hw,
3156 I82579_LPI_UPDATE_TIMER,
3157 0x1387);
3158 hw->phy.ops.release(hw);
3159 }
3160
3161 return ret_val;
3162}
3163
3172static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3173{
3174 s32 ret_val = E1000_SUCCESS;
3175
3176 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3177
3178 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3179 if ((hw->mac.type == e1000_pch2lan) &&
3180 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3181 e1000_gate_hw_phy_config_ich8lan(hw, true);
3182
3183 ret_val = e1000_phy_hw_reset_generic(hw);
3184 if (ret_val)
3185 return ret_val;
3186
3187 return e1000_post_phy_reset_ich8lan(hw);
3188}
3189
3201static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3202{
3203 s32 ret_val;
3204 u16 oem_reg;
3205
3206 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3207 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3208 if (ret_val)
3209 return ret_val;
3210
3211 if (active)
3212 oem_reg |= HV_OEM_BITS_LPLU;
3213 else
3214 oem_reg &= ~HV_OEM_BITS_LPLU;
3215
3216 if (!hw->phy.ops.check_reset_block(hw))
3217 oem_reg |= HV_OEM_BITS_RESTART_AN;
3218
3219 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3220}
3221
3235static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3236{
3237 struct e1000_phy_info *phy = &hw->phy;
3238 u32 phy_ctrl;
3239 s32 ret_val = E1000_SUCCESS;
3240 u16 data;
3241
3242 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3243
3244 if (phy->type == e1000_phy_ife)
3245 return E1000_SUCCESS;
3246
3247 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3248
3249 if (active) {
3250 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3251 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3252
3253 if (phy->type != e1000_phy_igp_3)
3254 return E1000_SUCCESS;
3255
3256 /* Call gig speed drop workaround on LPLU before accessing
3257 * any PHY registers
3258 */
3259 if (hw->mac.type == e1000_ich8lan)
3260 e1000_gig_downshift_workaround_ich8lan(hw);
3261
3262 /* When LPLU is enabled, we should disable SmartSpeed */
3263 ret_val = phy->ops.read_reg(hw,
3264 IGP01E1000_PHY_PORT_CONFIG,
3265 &data);
3266 if (ret_val)
3267 return ret_val;
3268 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3269 ret_val = phy->ops.write_reg(hw,
3270 IGP01E1000_PHY_PORT_CONFIG,
3271 data);
3272 if (ret_val)
3273 return ret_val;
3274 } else {
3275 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3276 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3277
3278 if (phy->type != e1000_phy_igp_3)
3279 return E1000_SUCCESS;
3280
3281 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3282 * during Dx states where the power conservation is most
3283 * important. During driver activity we should enable
3284 * SmartSpeed, so performance is maintained.
3285 */
3286 if (phy->smart_speed == e1000_smart_speed_on) {
3287 ret_val = phy->ops.read_reg(hw,
3288 IGP01E1000_PHY_PORT_CONFIG,
3289 &data);
3290 if (ret_val)
3291 return ret_val;
3292
3293 data |= IGP01E1000_PSCFR_SMART_SPEED;
3294 ret_val = phy->ops.write_reg(hw,
3295 IGP01E1000_PHY_PORT_CONFIG,
3296 data);
3297 if (ret_val)
3298 return ret_val;
3299 } else if (phy->smart_speed == e1000_smart_speed_off) {
3300 ret_val = phy->ops.read_reg(hw,
3301 IGP01E1000_PHY_PORT_CONFIG,
3302 &data);
3303 if (ret_val)
3304 return ret_val;
3305
3306 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3307 ret_val = phy->ops.write_reg(hw,
3308 IGP01E1000_PHY_PORT_CONFIG,
3309 data);
3310 if (ret_val)
3311 return ret_val;
3312 }
3313 }
3314
3315 return E1000_SUCCESS;
3316}
3317
3331static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3332{
3333 struct e1000_phy_info *phy = &hw->phy;
3334 u32 phy_ctrl;
3335 s32 ret_val = E1000_SUCCESS;
3336 u16 data;
3337
3338 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3339
3340 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3341
3342 if (!active) {
3343 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3344 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3345
3346 if (phy->type != e1000_phy_igp_3)
3347 return E1000_SUCCESS;
3348
3349 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3350 * during Dx states where the power conservation is most
3351 * important. During driver activity we should enable
3352 * SmartSpeed, so performance is maintained.
3353 */
3354 if (phy->smart_speed == e1000_smart_speed_on) {
3355 ret_val = phy->ops.read_reg(hw,
3356 IGP01E1000_PHY_PORT_CONFIG,
3357 &data);
3358 if (ret_val)
3359 return ret_val;
3360
3361 data |= IGP01E1000_PSCFR_SMART_SPEED;
3362 ret_val = phy->ops.write_reg(hw,
3363 IGP01E1000_PHY_PORT_CONFIG,
3364 data);
3365 if (ret_val)
3366 return ret_val;
3367 } else if (phy->smart_speed == e1000_smart_speed_off) {
3368 ret_val = phy->ops.read_reg(hw,
3369 IGP01E1000_PHY_PORT_CONFIG,
3370 &data);
3371 if (ret_val)
3372 return ret_val;
3373
3374 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3375 ret_val = phy->ops.write_reg(hw,
3376 IGP01E1000_PHY_PORT_CONFIG,
3377 data);
3378 if (ret_val)
3379 return ret_val;
3380 }
3381 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3382 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3383 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3384 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3385 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3386
3387 if (phy->type != e1000_phy_igp_3)
3388 return E1000_SUCCESS;
3389
3390 /* Call gig speed drop workaround on LPLU before accessing
3391 * any PHY registers
3392 */
3393 if (hw->mac.type == e1000_ich8lan)
3394 e1000_gig_downshift_workaround_ich8lan(hw);
3395
3396 /* When LPLU is enabled, we should disable SmartSpeed */
3397 ret_val = phy->ops.read_reg(hw,
3398 IGP01E1000_PHY_PORT_CONFIG,
3399 &data);
3400 if (ret_val)
3401 return ret_val;
3402
3403 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3404 ret_val = phy->ops.write_reg(hw,
3405 IGP01E1000_PHY_PORT_CONFIG,
3406 data);
3407 }
3408
3409 return ret_val;
3410}
3411
3420static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3421{
3422 u32 eecd;
3423 struct e1000_nvm_info *nvm = &hw->nvm;
3424 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3425 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3426 u32 nvm_dword = 0;
3427 u8 sig_byte = 0;
3428 s32 ret_val;
3429
3430 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3431
3432 switch (hw->mac.type) {
3433 case e1000_pch_spt:
3434 case e1000_pch_cnp:
3435 case e1000_pch_tgp:
3436 case e1000_pch_adp:
3437 case e1000_pch_mtp:
3438 bank1_offset = nvm->flash_bank_size;
3439 act_offset = E1000_ICH_NVM_SIG_WORD;
3440
3441 /* set bank to 0 in case flash read fails */
3442 *bank = 0;
3443
3444 /* Check bank 0 */
3445 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3446 &nvm_dword);
3447 if (ret_val)
3448 return ret_val;
3449 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3450 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3451 E1000_ICH_NVM_SIG_VALUE) {
3452 *bank = 0;
3453 return E1000_SUCCESS;
3454 }
3455
3456 /* Check bank 1 */
3457 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3458 bank1_offset,
3459 &nvm_dword);
3460 if (ret_val)
3461 return ret_val;
3462 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3463 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3464 E1000_ICH_NVM_SIG_VALUE) {
3465 *bank = 1;
3466 return E1000_SUCCESS;
3467 }
3468
3469 DEBUGOUT("ERROR: No valid NVM bank present\n");
3470 return -E1000_ERR_NVM;
3471 case e1000_ich8lan:
3472 case e1000_ich9lan:
3473 eecd = E1000_READ_REG(hw, E1000_EECD);
3474 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3475 E1000_EECD_SEC1VAL_VALID_MASK) {
3476 if (eecd & E1000_EECD_SEC1VAL)
3477 *bank = 1;
3478 else
3479 *bank = 0;
3480
3481 return E1000_SUCCESS;
3482 }
3483 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3484 /* FALLTHROUGH */
3485 default:
3486 /* set bank to 0 in case flash read fails */
3487 *bank = 0;
3488
3489 /* Check bank 0 */
3490 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3491 &sig_byte);
3492 if (ret_val)
3493 return ret_val;
3494 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3495 E1000_ICH_NVM_SIG_VALUE) {
3496 *bank = 0;
3497 return E1000_SUCCESS;
3498 }
3499
3500 /* Check bank 1 */
3501 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3502 bank1_offset,
3503 &sig_byte);
3504 if (ret_val)
3505 return ret_val;
3506 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3507 E1000_ICH_NVM_SIG_VALUE) {
3508 *bank = 1;
3509 return E1000_SUCCESS;
3510 }
3511
3512 DEBUGOUT("ERROR: No valid NVM bank present\n");
3513 return -E1000_ERR_NVM;
3514 }
3515}
3516
3526static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3527 u16 *data)
3528{
3529 struct e1000_nvm_info *nvm = &hw->nvm;
3530 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3531 u32 act_offset;
3532 s32 ret_val = E1000_SUCCESS;
3533 u32 bank = 0;
3534 u32 dword = 0;
3535 u16 offset_to_read;
3536 u16 i;
3537
3538 DEBUGFUNC("e1000_read_nvm_spt");
3539
3540 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3541 (words == 0)) {
3542 DEBUGOUT("nvm parameter(s) out of bounds\n");
3543 ret_val = -E1000_ERR_NVM;
3544 goto out;
3545 }
3546
3547 nvm->ops.acquire(hw);
3548
3549 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3550 if (ret_val != E1000_SUCCESS) {
3551 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3552 bank = 0;
3553 }
3554
3555 act_offset = (bank) ? nvm->flash_bank_size : 0;
3556 act_offset += offset;
3557
3558 ret_val = E1000_SUCCESS;
3559
3560 for (i = 0; i < words; i += 2) {
3561 if (words - i == 1) {
3562 if (dev_spec->shadow_ram[offset + i].modified) {
3563 data[i] =
3564 dev_spec->shadow_ram[offset + i].value;
3565 } else {
3566 offset_to_read = act_offset + i -
3567 ((act_offset + i) % 2);
3568 ret_val =
3569 e1000_read_flash_dword_ich8lan(hw,
3570 offset_to_read,
3571 &dword);
3572 if (ret_val)
3573 break;
3574 if ((act_offset + i) % 2 == 0)
3575 data[i] = (u16)(dword & 0xFFFF);
3576 else
3577 data[i] = (u16)((dword >> 16) & 0xFFFF);
3578 }
3579 } else {
3580 offset_to_read = act_offset + i;
3581 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3582 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3583 ret_val =
3584 e1000_read_flash_dword_ich8lan(hw,
3585 offset_to_read,
3586 &dword);
3587 if (ret_val)
3588 break;
3589 }
3590 if (dev_spec->shadow_ram[offset + i].modified)
3591 data[i] =
3592 dev_spec->shadow_ram[offset + i].value;
3593 else
3594 data[i] = (u16)(dword & 0xFFFF);
3595 if (dev_spec->shadow_ram[offset + i + 1].modified)
3596 data[i + 1] =
3597 dev_spec->shadow_ram[offset + i + 1].value;
3598 else
3599 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3600 }
3601 }
3602
3603 nvm->ops.release(hw);
3604
3605out:
3606 if (ret_val)
3607 DEBUGOUT1("NVM read error: %d\n", ret_val);
3608
3609 return ret_val;
3610}
3611
3621static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3622 u16 *data)
3623{
3624 struct e1000_nvm_info *nvm = &hw->nvm;
3625 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3626 u32 act_offset;
3627 s32 ret_val = E1000_SUCCESS;
3628 u32 bank = 0;
3629 u16 i, word;
3630
3631 DEBUGFUNC("e1000_read_nvm_ich8lan");
3632
3633 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3634 (words == 0)) {
3635 DEBUGOUT("nvm parameter(s) out of bounds\n");
3636 ret_val = -E1000_ERR_NVM;
3637 goto out;
3638 }
3639
3640 nvm->ops.acquire(hw);
3641
3642 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3643 if (ret_val != E1000_SUCCESS) {
3644 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3645 bank = 0;
3646 }
3647
3648 act_offset = (bank) ? nvm->flash_bank_size : 0;
3649 act_offset += offset;
3650
3651 ret_val = E1000_SUCCESS;
3652 for (i = 0; i < words; i++) {
3653 if (dev_spec->shadow_ram[offset + i].modified) {
3654 data[i] = dev_spec->shadow_ram[offset + i].value;
3655 } else {
3656 ret_val = e1000_read_flash_word_ich8lan(hw,
3657 act_offset + i,
3658 &word);
3659 if (ret_val)
3660 break;
3661 data[i] = word;
3662 }
3663 }
3664
3665 nvm->ops.release(hw);
3666
3667out:
3668 if (ret_val)
3669 DEBUGOUT1("NVM read error: %d\n", ret_val);
3670
3671 return ret_val;
3672}
3673
3681static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3682{
3683 union ich8_hws_flash_status hsfsts;
3684 s32 ret_val = -E1000_ERR_NVM;
3685
3686 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3687
3688 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3689
3690 /* Check if the flash descriptor is valid */
3691 if (!hsfsts.hsf_status.fldesvalid) {
3692 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3693 return -E1000_ERR_NVM;
3694 }
3695
3696 /* Clear FCERR and DAEL in hw status by writing 1 */
3697 hsfsts.hsf_status.flcerr = 1;
3698 hsfsts.hsf_status.dael = 1;
3699 if (hw->mac.type >= e1000_pch_spt)
3700 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3701 hsfsts.regval & 0xFFFF);
3702 else
3703 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3704
3705 /* Either we should have a hardware SPI cycle in progress
3706 * bit to check against, in order to start a new cycle or
3707 * FDONE bit should be changed in the hardware so that it
3708 * is 1 after hardware reset, which can then be used as an
3709 * indication whether a cycle is in progress or has been
3710 * completed.
3711 */
3712
3713 if (!hsfsts.hsf_status.flcinprog) {
3714 /* There is no cycle running at present,
3715 * so we can start a cycle.
3716 * Begin by setting Flash Cycle Done.
3717 */
3718 hsfsts.hsf_status.flcdone = 1;
3719 if (hw->mac.type >= e1000_pch_spt)
3720 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3721 hsfsts.regval & 0xFFFF);
3722 else
3723 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3724 hsfsts.regval);
3725 ret_val = E1000_SUCCESS;
3726 } else {
3727 s32 i;
3728
3729 /* Otherwise poll for sometime so the current
3730 * cycle has a chance to end before giving up.
3731 */
3732 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3733 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3734 ICH_FLASH_HSFSTS);
3735 if (!hsfsts.hsf_status.flcinprog) {
3736 ret_val = E1000_SUCCESS;
3737 break;
3738 }
3739 usec_delay(1);
3740 }
3741 if (ret_val == E1000_SUCCESS) {
3742 /* Successful in waiting for previous cycle to timeout,
3743 * now set the Flash Cycle Done.
3744 */
3745 hsfsts.hsf_status.flcdone = 1;
3746 if (hw->mac.type >= e1000_pch_spt)
3747 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3748 hsfsts.regval & 0xFFFF);
3749 else
3750 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3751 hsfsts.regval);
3752 } else {
3753 DEBUGOUT("Flash controller busy, cannot get access\n");
3754 }
3755 }
3756
3757 return ret_val;
3758}
3759
3767static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3768{
3769 union ich8_hws_flash_ctrl hsflctl;
3770 union ich8_hws_flash_status hsfsts;
3771 u32 i = 0;
3772
3773 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3774
3775 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3776 if (hw->mac.type >= e1000_pch_spt)
3777 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3778 else
3779 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3780 hsflctl.hsf_ctrl.flcgo = 1;
3781
3782 if (hw->mac.type >= e1000_pch_spt)
3783 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3784 hsflctl.regval << 16);
3785 else
3786 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3787
3788 /* wait till FDONE bit is set to 1 */
3789 do {
3790 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3791 if (hsfsts.hsf_status.flcdone)
3792 break;
3793 usec_delay(1);
3794 } while (i++ < timeout);
3795
3796 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3797 return E1000_SUCCESS;
3798
3799 return -E1000_ERR_NVM;
3800}
3801
3811static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3812 u32 *data)
3813{
3814 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3815
3816 if (!data)
3817 return -E1000_ERR_NVM;
3818
3819 /* Must convert word offset into bytes. */
3820 offset <<= 1;
3821
3822 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3823}
3824
3834static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3835 u16 *data)
3836{
3837 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3838
3839 if (!data)
3840 return -E1000_ERR_NVM;
3841
3842 /* Must convert offset into bytes. */
3843 offset <<= 1;
3844
3845 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3846}
3847
3856static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3857 u8 *data)
3858{
3859 s32 ret_val;
3860 u16 word = 0;
3861
3862 /* In SPT, only 32 bits access is supported,
3863 * so this function should not be called.
3864 */
3865 if (hw->mac.type >= e1000_pch_spt)
3866 return -E1000_ERR_NVM;
3867 else
3868 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3869
3870 if (ret_val)
3871 return ret_val;
3872
3873 *data = (u8)word;
3874
3875 return E1000_SUCCESS;
3876}
3877
3887static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3888 u8 size, u16 *data)
3889{
3890 union ich8_hws_flash_status hsfsts;
3891 union ich8_hws_flash_ctrl hsflctl;
3892 u32 flash_linear_addr;
3893 u32 flash_data = 0;
3894 s32 ret_val = -E1000_ERR_NVM;
3895 u8 count = 0;
3896
3897 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3898
3899 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3900 return -E1000_ERR_NVM;
3901 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3902 hw->nvm.flash_base_addr);
3903
3904 do {
3905 usec_delay(1);
3906 /* Steps */
3907 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3908 if (ret_val != E1000_SUCCESS)
3909 break;
3910 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3911
3912 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3913 hsflctl.hsf_ctrl.fldbcount = size - 1;
3914 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3915 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3916 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3917
3918 ret_val = e1000_flash_cycle_ich8lan(hw,
3919 ICH_FLASH_READ_COMMAND_TIMEOUT);
3920
3921 /* Check if FCERR is set to 1, if set to 1, clear it
3922 * and try the whole sequence a few more times, else
3923 * read in (shift in) the Flash Data0, the order is
3924 * least significant byte first msb to lsb
3925 */
3926 if (ret_val == E1000_SUCCESS) {
3927 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3928 if (size == 1)
3929 *data = (u8)(flash_data & 0x000000FF);
3930 else if (size == 2)
3931 *data = (u16)(flash_data & 0x0000FFFF);
3932 break;
3933 } else {
3934 /* If we've gotten here, then things are probably
3935 * completely hosed, but if the error condition is
3936 * detected, it won't hurt to give it another try...
3937 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3938 */
3939 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3940 ICH_FLASH_HSFSTS);
3941 if (hsfsts.hsf_status.flcerr) {
3942 /* Repeat for some time before giving up. */
3943 continue;
3944 } else if (!hsfsts.hsf_status.flcdone) {
3945 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3946 break;
3947 }
3948 }
3949 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3950
3951 return ret_val;
3952}
3953
3962static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3963 u32 *data)
3964{
3965 union ich8_hws_flash_status hsfsts;
3966 union ich8_hws_flash_ctrl hsflctl;
3967 u32 flash_linear_addr;
3968 s32 ret_val = -E1000_ERR_NVM;
3969 u8 count = 0;
3970
3971 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3972
3973 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3974 hw->mac.type < e1000_pch_spt)
3975 return -E1000_ERR_NVM;
3976 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3977 hw->nvm.flash_base_addr);
3978
3979 do {
3980 usec_delay(1);
3981 /* Steps */
3982 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3983 if (ret_val != E1000_SUCCESS)
3984 break;
3985 /* In SPT, This register is in Lan memory space, not flash.
3986 * Therefore, only 32 bit access is supported
3987 */
3988 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3989
3990 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3991 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3992 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3993 /* In SPT, This register is in Lan memory space, not flash.
3994 * Therefore, only 32 bit access is supported
3995 */
3996 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3997 (u32)hsflctl.regval << 16);
3998 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3999
4000 ret_val = e1000_flash_cycle_ich8lan(hw,
4001 ICH_FLASH_READ_COMMAND_TIMEOUT);
4002
4003 /* Check if FCERR is set to 1, if set to 1, clear it
4004 * and try the whole sequence a few more times, else
4005 * read in (shift in) the Flash Data0, the order is
4006 * least significant byte first msb to lsb
4007 */
4008 if (ret_val == E1000_SUCCESS) {
4009 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
4010 break;
4011 } else {
4012 /* If we've gotten here, then things are probably
4013 * completely hosed, but if the error condition is
4014 * detected, it won't hurt to give it another try...
4015 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
4016 */
4017 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4018 ICH_FLASH_HSFSTS);
4019 if (hsfsts.hsf_status.flcerr) {
4020 /* Repeat for some time before giving up. */
4021 continue;
4022 } else if (!hsfsts.hsf_status.flcdone) {
4023 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4024 break;
4025 }
4026 }
4027 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4028
4029 return ret_val;
4030}
4031
4041static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4042 u16 *data)
4043{
4044 struct e1000_nvm_info *nvm = &hw->nvm;
4045 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4046 u16 i;
4047
4048 DEBUGFUNC("e1000_write_nvm_ich8lan");
4049
4050 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4051 (words == 0)) {
4052 DEBUGOUT("nvm parameter(s) out of bounds\n");
4053 return -E1000_ERR_NVM;
4054 }
4055
4056 nvm->ops.acquire(hw);
4057
4058 for (i = 0; i < words; i++) {
4059 dev_spec->shadow_ram[offset + i].modified = true;
4060 dev_spec->shadow_ram[offset + i].value = data[i];
4061 }
4062
4063 nvm->ops.release(hw);
4064
4065 return E1000_SUCCESS;
4066}
4067
4079static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4080{
4081 struct e1000_nvm_info *nvm = &hw->nvm;
4082 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4083 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4084 s32 ret_val;
4085 u32 dword = 0;
4086
4087 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4088
4089 ret_val = e1000_update_nvm_checksum_generic(hw);
4090 if (ret_val)
4091 goto out;
4092
4093 if (nvm->type != e1000_nvm_flash_sw)
4094 goto out;
4095
4096 nvm->ops.acquire(hw);
4097
4098 /* We're writing to the opposite bank so if we're on bank 1,
4099 * write to bank 0 etc. We also need to erase the segment that
4100 * is going to be written
4101 */
4102 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4103 if (ret_val != E1000_SUCCESS) {
4104 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4105 bank = 0;
4106 }
4107
4108 if (bank == 0) {
4109 new_bank_offset = nvm->flash_bank_size;
4110 old_bank_offset = 0;
4111 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4112 if (ret_val)
4113 goto release;
4114 } else {
4115 old_bank_offset = nvm->flash_bank_size;
4116 new_bank_offset = 0;
4117 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4118 if (ret_val)
4119 goto release;
4120 }
4121 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4122 /* Determine whether to write the value stored
4123 * in the other NVM bank or a modified value stored
4124 * in the shadow RAM
4125 */
4126 ret_val = e1000_read_flash_dword_ich8lan(hw,
4127 i + old_bank_offset,
4128 &dword);
4129
4130 if (dev_spec->shadow_ram[i].modified) {
4131 dword &= 0xffff0000;
4132 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4133 }
4134 if (dev_spec->shadow_ram[i + 1].modified) {
4135 dword &= 0x0000ffff;
4136 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4137 << 16);
4138 }
4139 if (ret_val)
4140 break;
4141
4142 /* If the word is 0x13, then make sure the signature bits
4143 * (15:14) are 11b until the commit has completed.
4144 * This will allow us to write 10b which indicates the
4145 * signature is valid. We want to do this after the write
4146 * has completed so that we don't mark the segment valid
4147 * while the write is still in progress
4148 */
4149 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4150 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4151
4152 /* Convert offset to bytes. */
4153 act_offset = (i + new_bank_offset) << 1;
4154
4155 usec_delay(100);
4156
4157 /* Write the data to the new bank. Offset in words*/
4158 act_offset = i + new_bank_offset;
4159 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4160 dword);
4161 if (ret_val)
4162 break;
4163 }
4164
4165 /* Don't bother writing the segment valid bits if sector
4166 * programming failed.
4167 */
4168 if (ret_val) {
4169 DEBUGOUT("Flash commit failed.\n");
4170 goto release;
4171 }
4172
4173 /* Finally validate the new segment by setting bit 15:14
4174 * to 10b in word 0x13 , this can be done without an
4175 * erase as well since these bits are 11 to start with
4176 * and we need to change bit 14 to 0b
4177 */
4178 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4179
4180 /*offset in words but we read dword*/
4181 --act_offset;
4182 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4183
4184 if (ret_val)
4185 goto release;
4186
4187 dword &= 0xBFFFFFFF;
4188 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4189
4190 if (ret_val)
4191 goto release;
4192
4193 /* offset in words but we read dword*/
4194 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4195 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4196
4197 if (ret_val)
4198 goto release;
4199
4200 dword &= 0x00FFFFFF;
4201 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4202
4203 if (ret_val)
4204 goto release;
4205
4206 /* Great! Everything worked, we can now clear the cached entries. */
4207 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4208 dev_spec->shadow_ram[i].modified = false;
4209 dev_spec->shadow_ram[i].value = 0xFFFF;
4210 }
4211
4212release:
4213 nvm->ops.release(hw);
4214
4215 /* Reload the EEPROM, or else modifications will not appear
4216 * until after the next adapter reset.
4217 */
4218 if (!ret_val) {
4219 nvm->ops.reload(hw);
4220 msec_delay(10);
4221 }
4222
4223out:
4224 if (ret_val)
4225 DEBUGOUT1("NVM update error: %d\n", ret_val);
4226
4227 return ret_val;
4228}
4229
4241static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4242{
4243 struct e1000_nvm_info *nvm = &hw->nvm;
4244 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4245 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4246 s32 ret_val;
4247 u16 data = 0;
4248
4249 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4250
4251 ret_val = e1000_update_nvm_checksum_generic(hw);
4252 if (ret_val)
4253 goto out;
4254
4255 if (nvm->type != e1000_nvm_flash_sw)
4256 goto out;
4257
4258 nvm->ops.acquire(hw);
4259
4260 /* We're writing to the opposite bank so if we're on bank 1,
4261 * write to bank 0 etc. We also need to erase the segment that
4262 * is going to be written
4263 */
4264 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4265 if (ret_val != E1000_SUCCESS) {
4266 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4267 bank = 0;
4268 }
4269
4270 if (bank == 0) {
4271 new_bank_offset = nvm->flash_bank_size;
4272 old_bank_offset = 0;
4273 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4274 if (ret_val)
4275 goto release;
4276 } else {
4277 old_bank_offset = nvm->flash_bank_size;
4278 new_bank_offset = 0;
4279 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4280 if (ret_val)
4281 goto release;
4282 }
4283 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4284 if (dev_spec->shadow_ram[i].modified) {
4285 data = dev_spec->shadow_ram[i].value;
4286 } else {
4287 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4288 old_bank_offset,
4289 &data);
4290 if (ret_val)
4291 break;
4292 }
4293 /* If the word is 0x13, then make sure the signature bits
4294 * (15:14) are 11b until the commit has completed.
4295 * This will allow us to write 10b which indicates the
4296 * signature is valid. We want to do this after the write
4297 * has completed so that we don't mark the segment valid
4298 * while the write is still in progress
4299 */
4300 if (i == E1000_ICH_NVM_SIG_WORD)
4301 data |= E1000_ICH_NVM_SIG_MASK;
4302
4303 /* Convert offset to bytes. */
4304 act_offset = (i + new_bank_offset) << 1;
4305
4306 usec_delay(100);
4307
4308 /* Write the bytes to the new bank. */
4309 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4310 act_offset,
4311 (u8)data);
4312 if (ret_val)
4313 break;
4314
4315 usec_delay(100);
4316 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4317 act_offset + 1,
4318 (u8)(data >> 8));
4319 if (ret_val)
4320 break;
4321 }
4322
4323 /* Don't bother writing the segment valid bits if sector
4324 * programming failed.
4325 */
4326 if (ret_val) {
4327 DEBUGOUT("Flash commit failed.\n");
4328 goto release;
4329 }
4330
4331 /* Finally validate the new segment by setting bit 15:14
4332 * to 10b in word 0x13 , this can be done without an
4333 * erase as well since these bits are 11 to start with
4334 * and we need to change bit 14 to 0b
4335 */
4336 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4337 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4338 if (ret_val)
4339 goto release;
4340
4341 data &= 0xBFFF;
4342 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4343 (u8)(data >> 8));
4344 if (ret_val)
4345 goto release;
4346
4347 /* And invalidate the previously valid segment by setting
4348 * its signature word (0x13) high_byte to 0b. This can be
4349 * done without an erase because flash erase sets all bits
4350 * to 1's. We can write 1's to 0's without an erase
4351 */
4352 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4353
4354 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4355
4356 if (ret_val)
4357 goto release;
4358
4359 /* Great! Everything worked, we can now clear the cached entries. */
4360 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4361 dev_spec->shadow_ram[i].modified = false;
4362 dev_spec->shadow_ram[i].value = 0xFFFF;
4363 }
4364
4365release:
4366 nvm->ops.release(hw);
4367
4368 /* Reload the EEPROM, or else modifications will not appear
4369 * until after the next adapter reset.
4370 */
4371 if (!ret_val) {
4372 nvm->ops.reload(hw);
4373 msec_delay(10);
4374 }
4375
4376out:
4377 if (ret_val)
4378 DEBUGOUT1("NVM update error: %d\n", ret_val);
4379
4380 return ret_val;
4381}
4382
4391static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4392{
4393 s32 ret_val;
4394 u16 data;
4395 u16 word;
4396 u16 valid_csum_mask;
4397
4398 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4399
4400 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4401 * the checksum needs to be fixed. This bit is an indication that
4402 * the NVM was prepared by OEM software and did not calculate
4403 * the checksum...a likely scenario.
4404 */
4405 switch (hw->mac.type) {
4406 case e1000_pch_lpt:
4407 case e1000_pch_spt:
4408 case e1000_pch_cnp:
4409 case e1000_pch_tgp:
4410 case e1000_pch_adp:
4411 case e1000_pch_mtp:
4412 word = NVM_COMPAT;
4413 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4414 break;
4415 default:
4416 word = NVM_FUTURE_INIT_WORD1;
4417 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4418 break;
4419 }
4420
4421 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4422 if (ret_val)
4423 return ret_val;
4424
4425 if (!(data & valid_csum_mask)) {
4426 data |= valid_csum_mask;
4427 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4428 if (ret_val)
4429 return ret_val;
4430 ret_val = hw->nvm.ops.update(hw);
4431 if (ret_val)
4432 return ret_val;
4433 }
4434
4435 return e1000_validate_nvm_checksum_generic(hw);
4436}
4437
4447static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4448 u8 size, u16 data)
4449{
4450 union ich8_hws_flash_status hsfsts;
4451 union ich8_hws_flash_ctrl hsflctl;
4452 u32 flash_linear_addr;
4453 u32 flash_data = 0;
4454 s32 ret_val;
4455 u8 count = 0;
4456
4457 DEBUGFUNC("e1000_write_ich8_data");
4458
4459 if (hw->mac.type >= e1000_pch_spt) {
4460 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4461 return -E1000_ERR_NVM;
4462 } else {
4463 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4464 return -E1000_ERR_NVM;
4465 }
4466
4467 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4468 hw->nvm.flash_base_addr);
4469
4470 do {
4471 usec_delay(1);
4472 /* Steps */
4473 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4474 if (ret_val != E1000_SUCCESS)
4475 break;
4476 /* In SPT, This register is in Lan memory space, not
4477 * flash. Therefore, only 32 bit access is supported
4478 */
4479 if (hw->mac.type >= e1000_pch_spt)
4480 hsflctl.regval =
4481 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4482 else
4483 hsflctl.regval =
4484 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4485
4486 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4487 hsflctl.hsf_ctrl.fldbcount = size - 1;
4488 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4489 /* In SPT, This register is in Lan memory space,
4490 * not flash. Therefore, only 32 bit access is
4491 * supported
4492 */
4493 if (hw->mac.type >= e1000_pch_spt)
4494 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4495 hsflctl.regval << 16);
4496 else
4497 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4498 hsflctl.regval);
4499
4500 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4501
4502 if (size == 1)
4503 flash_data = (u32)data & 0x00FF;
4504 else
4505 flash_data = (u32)data;
4506
4507 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4508
4509 /* check if FCERR is set to 1 , if set to 1, clear it
4510 * and try the whole sequence a few more times else done
4511 */
4512 ret_val =
4513 e1000_flash_cycle_ich8lan(hw,
4514 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4515 if (ret_val == E1000_SUCCESS)
4516 break;
4517
4518 /* If we're here, then things are most likely
4519 * completely hosed, but if the error condition
4520 * is detected, it won't hurt to give it another
4521 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4522 */
4523 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4524 if (hsfsts.hsf_status.flcerr)
4525 /* Repeat for some time before giving up. */
4526 continue;
4527 if (!hsfsts.hsf_status.flcdone) {
4528 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4529 break;
4530 }
4531 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4532
4533 return ret_val;
4534}
4535
4544static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4545 u32 data)
4546{
4547 union ich8_hws_flash_status hsfsts;
4548 union ich8_hws_flash_ctrl hsflctl;
4549 u32 flash_linear_addr;
4550 s32 ret_val;
4551 u8 count = 0;
4552
4553 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4554
4555 if (hw->mac.type >= e1000_pch_spt) {
4556 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4557 return -E1000_ERR_NVM;
4558 }
4559 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4560 hw->nvm.flash_base_addr);
4561 do {
4562 usec_delay(1);
4563 /* Steps */
4564 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4565 if (ret_val != E1000_SUCCESS)
4566 break;
4567
4568 /* In SPT, This register is in Lan memory space, not
4569 * flash. Therefore, only 32 bit access is supported
4570 */
4571 if (hw->mac.type >= e1000_pch_spt)
4572 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4573 ICH_FLASH_HSFSTS)
4574 >> 16;
4575 else
4576 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4577 ICH_FLASH_HSFCTL);
4578
4579 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4580 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4581
4582 /* In SPT, This register is in Lan memory space,
4583 * not flash. Therefore, only 32 bit access is
4584 * supported
4585 */
4586 if (hw->mac.type >= e1000_pch_spt)
4587 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4588 hsflctl.regval << 16);
4589 else
4590 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4591 hsflctl.regval);
4592
4593 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4594
4595 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4596
4597 /* check if FCERR is set to 1 , if set to 1, clear it
4598 * and try the whole sequence a few more times else done
4599 */
4600 ret_val = e1000_flash_cycle_ich8lan(hw,
4601 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4602
4603 if (ret_val == E1000_SUCCESS)
4604 break;
4605
4606 /* If we're here, then things are most likely
4607 * completely hosed, but if the error condition
4608 * is detected, it won't hurt to give it another
4609 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4610 */
4611 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4612
4613 if (hsfsts.hsf_status.flcerr)
4614 /* Repeat for some time before giving up. */
4615 continue;
4616 if (!hsfsts.hsf_status.flcdone) {
4617 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4618 break;
4619 }
4620 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4621
4622 return ret_val;
4623}
4624
4633static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4634 u8 data)
4635{
4636 u16 word = (u16)data;
4637
4638 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4639
4640 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4641}
4642
4652static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4653 u32 offset, u32 dword)
4654{
4655 s32 ret_val;
4656 u16 program_retries;
4657
4658 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4659
4660 /* Must convert word offset into bytes. */
4661 offset <<= 1;
4662
4663 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4664
4665 if (!ret_val)
4666 return ret_val;
4667 for (program_retries = 0; program_retries < 100; program_retries++) {
4668 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4669 usec_delay(100);
4670 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4671 if (ret_val == E1000_SUCCESS)
4672 break;
4673 }
4674 if (program_retries == 100)
4675 return -E1000_ERR_NVM;
4676
4677 return E1000_SUCCESS;
4678}
4679
4689static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4690 u32 offset, u8 byte)
4691{
4692 s32 ret_val;
4693 u16 program_retries;
4694
4695 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4696
4697 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4698 if (!ret_val)
4699 return ret_val;
4700
4701 for (program_retries = 0; program_retries < 100; program_retries++) {
4702 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4703 usec_delay(100);
4704 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4705 if (ret_val == E1000_SUCCESS)
4706 break;
4707 }
4708 if (program_retries == 100)
4709 return -E1000_ERR_NVM;
4710
4711 return E1000_SUCCESS;
4712}
4713
4722static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4723{
4724 struct e1000_nvm_info *nvm = &hw->nvm;
4725 union ich8_hws_flash_status hsfsts;
4726 union ich8_hws_flash_ctrl hsflctl;
4727 u32 flash_linear_addr;
4728 /* bank size is in 16bit words - adjust to bytes */
4729 u32 flash_bank_size = nvm->flash_bank_size * 2;
4730 s32 ret_val;
4731 s32 count = 0;
4732 s32 j, iteration, sector_size;
4733
4734 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4735
4736 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4737
4738 /* Determine HW Sector size: Read BERASE bits of hw flash status
4739 * register
4740 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4741 * consecutive sectors. The start index for the nth Hw sector
4742 * can be calculated as = bank * 4096 + n * 256
4743 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4744 * The start index for the nth Hw sector can be calculated
4745 * as = bank * 4096
4746 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4747 * (ich9 only, otherwise error condition)
4748 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4749 */
4750 switch (hsfsts.hsf_status.berasesz) {
4751 case 0:
4752 /* Hw sector size 256 */
4753 sector_size = ICH_FLASH_SEG_SIZE_256;
4754 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4755 break;
4756 case 1:
4757 sector_size = ICH_FLASH_SEG_SIZE_4K;
4758 iteration = 1;
4759 break;
4760 case 2:
4761 sector_size = ICH_FLASH_SEG_SIZE_8K;
4762 iteration = 1;
4763 break;
4764 case 3:
4765 sector_size = ICH_FLASH_SEG_SIZE_64K;
4766 iteration = 1;
4767 break;
4768 default:
4769 return -E1000_ERR_NVM;
4770 }
4771
4772 /* Start with the base address, then add the sector offset. */
4773 flash_linear_addr = hw->nvm.flash_base_addr;
4774 flash_linear_addr += (bank) ? flash_bank_size : 0;
4775
4776 for (j = 0; j < iteration; j++) {
4777 do {
4778 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4779
4780 /* Steps */
4781 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4782 if (ret_val)
4783 return ret_val;
4784
4785 /* Write a value 11 (block Erase) in Flash
4786 * Cycle field in hw flash control
4787 */
4788 if (hw->mac.type >= e1000_pch_spt)
4789 hsflctl.regval =
4790 E1000_READ_FLASH_REG(hw,
4791 ICH_FLASH_HSFSTS)>>16;
4792 else
4793 hsflctl.regval =
4794 E1000_READ_FLASH_REG16(hw,
4795 ICH_FLASH_HSFCTL);
4796
4797 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4798 if (hw->mac.type >= e1000_pch_spt)
4799 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4800 hsflctl.regval << 16);
4801 else
4802 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4803 hsflctl.regval);
4804
4805 /* Write the last 24 bits of an index within the
4806 * block into Flash Linear address field in Flash
4807 * Address.
4808 */
4809 flash_linear_addr += (j * sector_size);
4810 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4811 flash_linear_addr);
4812
4813 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4814 if (ret_val == E1000_SUCCESS)
4815 break;
4816
4817 /* Check if FCERR is set to 1. If 1,
4818 * clear it and try the whole sequence
4819 * a few more times else Done
4820 */
4821 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4822 ICH_FLASH_HSFSTS);
4823 if (hsfsts.hsf_status.flcerr)
4824 /* repeat for some time before giving up */
4825 continue;
4826 else if (!hsfsts.hsf_status.flcdone)
4827 return ret_val;
4828 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4829 }
4830
4831 return E1000_SUCCESS;
4832}
4833
4843static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4844{
4845 s32 ret_val;
4846
4847 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4848
4849 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4850 if (ret_val) {
4851 DEBUGOUT("NVM Read Error\n");
4852 return ret_val;
4853 }
4854
4855 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4856 *data = ID_LED_DEFAULT_ICH8LAN;
4857
4858 return E1000_SUCCESS;
4859}
4860
4874static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4875{
4876 struct e1000_mac_info *mac = &hw->mac;
4877 s32 ret_val;
4878 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4879 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4880 u16 data, i, temp, shift;
4881
4882 DEBUGFUNC("e1000_id_led_init_pchlan");
4883
4884 /* Get default ID LED modes */
4885 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4886 if (ret_val)
4887 return ret_val;
4888
4889 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4890 mac->ledctl_mode1 = mac->ledctl_default;
4891 mac->ledctl_mode2 = mac->ledctl_default;
4892
4893 for (i = 0; i < 4; i++) {
4894 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4895 shift = (i * 5);
4896 switch (temp) {
4897 case ID_LED_ON1_DEF2:
4898 case ID_LED_ON1_ON2:
4899 case ID_LED_ON1_OFF2:
4900 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4901 mac->ledctl_mode1 |= (ledctl_on << shift);
4902 break;
4903 case ID_LED_OFF1_DEF2:
4904 case ID_LED_OFF1_ON2:
4905 case ID_LED_OFF1_OFF2:
4906 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4907 mac->ledctl_mode1 |= (ledctl_off << shift);
4908 break;
4909 default:
4910 /* Do nothing */
4911 break;
4912 }
4913 switch (temp) {
4914 case ID_LED_DEF1_ON2:
4915 case ID_LED_ON1_ON2:
4916 case ID_LED_OFF1_ON2:
4917 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4918 mac->ledctl_mode2 |= (ledctl_on << shift);
4919 break;
4920 case ID_LED_DEF1_OFF2:
4921 case ID_LED_ON1_OFF2:
4922 case ID_LED_OFF1_OFF2:
4923 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4924 mac->ledctl_mode2 |= (ledctl_off << shift);
4925 break;
4926 default:
4927 /* Do nothing */
4928 break;
4929 }
4930 }
4931
4932 return E1000_SUCCESS;
4933}
4934
4942static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4943{
4944 struct e1000_bus_info *bus = &hw->bus;
4945 s32 ret_val;
4946
4947 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4948
4949 ret_val = e1000_get_bus_info_pcie_generic(hw);
4950
4951 /* ICH devices are "PCI Express"-ish. They have
4952 * a configuration space, but do not contain
4953 * PCI Express Capability registers, so bus width
4954 * must be hardcoded.
4955 */
4956 if (bus->width == e1000_bus_width_unknown)
4957 bus->width = e1000_bus_width_pcie_x1;
4958
4959 return ret_val;
4960}
4961
4969static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4970{
4971 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4972 u16 kum_cfg;
4973 u32 ctrl, reg;
4974 s32 ret_val;
4975 u16 pci_cfg;
4976
4977 DEBUGFUNC("e1000_reset_hw_ich8lan");
4978
4979 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4980 * on the last TLP read/write transaction when MAC is reset.
4981 */
4982 ret_val = e1000_disable_pcie_master_generic(hw);
4983 if (ret_val)
4984 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4985
4986 DEBUGOUT("Masking off all interrupts\n");
4987 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4988
4989 /* Disable the Transmit and Receive units. Then delay to allow
4990 * any pending transactions to complete before we hit the MAC
4991 * with the global reset.
4992 */
4993 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4994 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4995 E1000_WRITE_FLUSH(hw);
4996
4997 msec_delay(10);
4998
4999 /* Workaround for ICH8 bit corruption issue in FIFO memory */
5000 if (hw->mac.type == e1000_ich8lan) {
5001 /* Set Tx and Rx buffer allocation to 8k apiece. */
5002 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
5003 /* Set Packet Buffer Size to 16k. */
5004 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
5005 }
5006
5007 if (hw->mac.type == e1000_pchlan) {
5008 /* Save the NVM K1 bit setting*/
5009 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
5010 if (ret_val)
5011 return ret_val;
5012
5013 if (kum_cfg & E1000_NVM_K1_ENABLE)
5014 dev_spec->nvm_k1_enabled = true;
5015 else
5016 dev_spec->nvm_k1_enabled = false;
5017 }
5018
5019 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5020
5021 if (!hw->phy.ops.check_reset_block(hw)) {
5022 /* Full-chip reset requires MAC and PHY reset at the same
5023 * time to make sure the interface between MAC and the
5024 * external PHY is reset.
5025 */
5026 ctrl |= E1000_CTRL_PHY_RST;
5027
5028 /* Gate automatic PHY configuration by hardware on
5029 * non-managed 82579
5030 */
5031 if ((hw->mac.type == e1000_pch2lan) &&
5032 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5033 e1000_gate_hw_phy_config_ich8lan(hw, true);
5034 }
5035 ret_val = e1000_acquire_swflag_ich8lan(hw);
5036
5037 /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
5038 * may occur during global reset and cause system hang.
5039 * Configuration space access creates the needed delay.
5040 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
5041 * insures configuration space read is done before global reset.
5042 */
5043 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
5044 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
5045 DEBUGOUT("Issuing a global reset to ich8lan\n");
5046 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5047 /* cannot issue a flush here because it hangs the hardware */
5048 msec_delay(20);
5049
5050 /* Configuration space access improve HW level time sync mechanism.
5051 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
5052 * value to insure configuration space read is done
5053 * before any access to mac register.
5054 */
5055 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
5056 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
5057
5058 /* Set Phy Config Counter to 50msec */
5059 if (hw->mac.type == e1000_pch2lan) {
5060 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5061 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
5062 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
5063 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5064 }
5065
5066
5067 if (ctrl & E1000_CTRL_PHY_RST) {
5068 ret_val = hw->phy.ops.get_cfg_done(hw);
5069 if (ret_val)
5070 return ret_val;
5071
5072 ret_val = e1000_post_phy_reset_ich8lan(hw);
5073 if (ret_val)
5074 return ret_val;
5075 }
5076
5077 /* For PCH, this write will make sure that any noise
5078 * will be detected as a CRC error and be dropped rather than show up
5079 * as a bad packet to the DMA engine.
5080 */
5081 if (hw->mac.type == e1000_pchlan)
5082 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5083
5084 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5085 E1000_READ_REG(hw, E1000_ICR);
5086
5087 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5088 reg |= E1000_KABGTXD_BGSQLBIAS;
5089 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5090
5091 return E1000_SUCCESS;
5092}
5093
5106static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5107{
5108 struct e1000_mac_info *mac = &hw->mac;
5109 u32 ctrl_ext, txdctl, snoop;
5110 s32 ret_val;
5111 u16 i;
5112
5113 DEBUGFUNC("e1000_init_hw_ich8lan");
5114
5115 e1000_initialize_hw_bits_ich8lan(hw);
5116
5117 /* Initialize identification LED */
5118 ret_val = mac->ops.id_led_init(hw);
5119 /* An error is not fatal and we should not stop init due to this */
5120 if (ret_val)
5121 DEBUGOUT("Error initializing identification LED\n");
5122
5123 /* Setup the receive address. */
5124 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5125
5126 /* Zero out the Multicast HASH table */
5127 DEBUGOUT("Zeroing the MTA\n");
5128 for (i = 0; i < mac->mta_reg_count; i++)
5129 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5130
5131 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5132 * the ME. Disable wakeup by clearing the host wakeup bit.
5133 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5134 */
5135 if (hw->phy.type == e1000_phy_82578) {
5136 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5137 i &= ~BM_WUC_HOST_WU_BIT;
5138 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5139 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5140 if (ret_val)
5141 return ret_val;
5142 }
5143
5144 /* Setup link and flow control */
5145 ret_val = mac->ops.setup_link(hw);
5146
5147 /* Set the transmit descriptor write-back policy for both queues */
5148 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5149 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5150 E1000_TXDCTL_FULL_TX_DESC_WB);
5151 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5152 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5153 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5154 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5155 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5156 E1000_TXDCTL_FULL_TX_DESC_WB);
5157 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5158 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5159 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5160
5161 /* ICH8 has opposite polarity of no_snoop bits.
5162 * By default, we should use snoop behavior.
5163 */
5164 if (mac->type == e1000_ich8lan)
5165 snoop = PCIE_ICH8_SNOOP_ALL;
5166 else
5167 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5168 e1000_set_pcie_no_snoop_generic(hw, snoop);
5169
5170 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5171 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5172 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5173
5174 /* Clear all of the statistics registers (clear on read). It is
5175 * important that we do this after we have tried to establish link
5176 * because the symbol error count will increment wildly if there
5177 * is no link.
5178 */
5179 e1000_clear_hw_cntrs_ich8lan(hw);
5180
5181 return ret_val;
5182}
5183
5191static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5192{
5193 u32 reg;
5194
5195 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5196
5197 /* Extended Device Control */
5198 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5199 reg |= (1 << 22);
5200 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5201 if (hw->mac.type >= e1000_pchlan)
5202 reg |= E1000_CTRL_EXT_PHYPDEN;
5203 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5204
5205 /* Transmit Descriptor Control 0 */
5206 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5207 reg |= (1 << 22);
5208 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5209
5210 /* Transmit Descriptor Control 1 */
5211 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5212 reg |= (1 << 22);
5213 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5214
5215 /* Transmit Arbitration Control 0 */
5216 reg = E1000_READ_REG(hw, E1000_TARC(0));
5217 if (hw->mac.type == e1000_ich8lan)
5218 reg |= (1 << 28) | (1 << 29);
5219 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5220 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5221
5222 /* Transmit Arbitration Control 1 */
5223 reg = E1000_READ_REG(hw, E1000_TARC(1));
5224 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5225 reg &= ~(1 << 28);
5226 else
5227 reg |= (1 << 28);
5228 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5229 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5230
5231 /* Device Status */
5232 if (hw->mac.type == e1000_ich8lan) {
5233 reg = E1000_READ_REG(hw, E1000_STATUS);
5234 reg &= ~(1U << 31);
5235 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5236 }
5237
5238 /* work-around descriptor data corruption issue during nfs v2 udp
5239 * traffic, just disable the nfs filtering capability
5240 */
5241 reg = E1000_READ_REG(hw, E1000_RFCTL);
5242 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5243
5244 /* Disable IPv6 extension header parsing because some malformed
5245 * IPv6 headers can hang the Rx.
5246 */
5247 if (hw->mac.type == e1000_ich8lan)
5248 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5249 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5250
5251 /* Enable ECC on Lynxpoint */
5252 if (hw->mac.type >= e1000_pch_lpt) {
5253 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5254 reg |= E1000_PBECCSTS_ECC_ENABLE;
5255 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5256
5257 reg = E1000_READ_REG(hw, E1000_CTRL);
5258 reg |= E1000_CTRL_MEHE;
5259 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5260 }
5261
5262 return;
5263}
5264
5275static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5276{
5277 s32 ret_val;
5278
5279 DEBUGFUNC("e1000_setup_link_ich8lan");
5280
5281 /* ICH parts do not have a word in the NVM to determine
5282 * the default flow control setting, so we explicitly
5283 * set it to full.
5284 */
5285 if (hw->fc.requested_mode == e1000_fc_default)
5286 hw->fc.requested_mode = e1000_fc_full;
5287
5288 /* Save off the requested flow control mode for use later. Depending
5289 * on the link partner's capabilities, we may or may not use this mode.
5290 */
5291 hw->fc.current_mode = hw->fc.requested_mode;
5292
5293 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5294 hw->fc.current_mode);
5295
5296 if (!hw->phy.ops.check_reset_block(hw)) {
5297 /* Continue to configure the copper link. */
5298 ret_val = hw->mac.ops.setup_physical_interface(hw);
5299 if (ret_val)
5300 return ret_val;
5301 }
5302
5303 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5304 if ((hw->phy.type == e1000_phy_82578) ||
5305 (hw->phy.type == e1000_phy_82579) ||
5306 (hw->phy.type == e1000_phy_i217) ||
5307 (hw->phy.type == e1000_phy_82577)) {
5308 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5309
5310 ret_val = hw->phy.ops.write_reg(hw,
5311 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5312 hw->fc.pause_time);
5313 if (ret_val)
5314 return ret_val;
5315 }
5316
5317 return e1000_set_fc_watermarks_generic(hw);
5318}
5319
5328static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5329{
5330 u32 ctrl;
5331 s32 ret_val;
5332 u16 reg_data;
5333
5334 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5335
5336 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5337 ctrl |= E1000_CTRL_SLU;
5338 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5339 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5340
5341 /* Set the mac to wait the maximum time between each iteration
5342 * and increase the max iterations when polling the phy;
5343 * this fixes erroneous timeouts at 10Mbps.
5344 */
5345 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5346 0xFFFF);
5347 if (ret_val)
5348 return ret_val;
5349 ret_val = e1000_read_kmrn_reg_generic(hw,
5350 E1000_KMRNCTRLSTA_INBAND_PARAM,
5351 &reg_data);
5352 if (ret_val)
5353 return ret_val;
5354 reg_data |= 0x3F;
5355 ret_val = e1000_write_kmrn_reg_generic(hw,
5356 E1000_KMRNCTRLSTA_INBAND_PARAM,
5357 reg_data);
5358 if (ret_val)
5359 return ret_val;
5360
5361 switch (hw->phy.type) {
5362 case e1000_phy_igp_3:
5363 ret_val = e1000_copper_link_setup_igp(hw);
5364 if (ret_val)
5365 return ret_val;
5366 break;
5367 case e1000_phy_bm:
5368 case e1000_phy_82578:
5369 ret_val = e1000_copper_link_setup_m88(hw);
5370 if (ret_val)
5371 return ret_val;
5372 break;
5373 case e1000_phy_82577:
5374 case e1000_phy_82579:
5375 ret_val = e1000_copper_link_setup_82577(hw);
5376 if (ret_val)
5377 return ret_val;
5378 break;
5379 case e1000_phy_ife:
5380 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5381 &reg_data);
5382 if (ret_val)
5383 return ret_val;
5384
5385 reg_data &= ~IFE_PMC_AUTO_MDIX;
5386
5387 switch (hw->phy.mdix) {
5388 case 1:
5389 reg_data &= ~IFE_PMC_FORCE_MDIX;
5390 break;
5391 case 2:
5392 reg_data |= IFE_PMC_FORCE_MDIX;
5393 break;
5394 case 0:
5395 default:
5396 reg_data |= IFE_PMC_AUTO_MDIX;
5397 break;
5398 }
5399 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5400 reg_data);
5401 if (ret_val)
5402 return ret_val;
5403 break;
5404 default:
5405 break;
5406 }
5407
5408 return e1000_setup_copper_link_generic(hw);
5409}
5410
5419static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5420{
5421 u32 ctrl;
5422 s32 ret_val;
5423
5424 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5425
5426 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5427 ctrl |= E1000_CTRL_SLU;
5428 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5429 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5430
5431 ret_val = e1000_copper_link_setup_82577(hw);
5432 if (ret_val)
5433 return ret_val;
5434
5435 return e1000_setup_copper_link_generic(hw);
5436}
5437
5448static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5449 u16 *duplex)
5450{
5451 s32 ret_val;
5452
5453 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5454
5455 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5456 if (ret_val)
5457 return ret_val;
5458
5459 if ((hw->mac.type == e1000_ich8lan) &&
5460 (hw->phy.type == e1000_phy_igp_3) &&
5461 (*speed == SPEED_1000)) {
5462 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5463 }
5464
5465 return ret_val;
5466}
5467
5483static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5484{
5485 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5486 u32 phy_ctrl;
5487 s32 ret_val;
5488 u16 i, data;
5489 bool link;
5490
5491 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5492
5493 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5494 return E1000_SUCCESS;
5495
5496 /* Make sure link is up before proceeding. If not just return.
5497 * Attempting this while link is negotiating fouled up link
5498 * stability
5499 */
5500 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5501 if (!link)
5502 return E1000_SUCCESS;
5503
5504 for (i = 0; i < 10; i++) {
5505 /* read once to clear */
5506 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5507 if (ret_val)
5508 return ret_val;
5509 /* and again to get new status */
5510 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5511 if (ret_val)
5512 return ret_val;
5513
5514 /* check for PCS lock */
5515 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5516 return E1000_SUCCESS;
5517
5518 /* Issue PHY reset */
5519 hw->phy.ops.reset(hw);
5520 msec_delay_irq(5);
5521 }
5522 /* Disable GigE link negotiation */
5523 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5524 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5525 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5526 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5527
5528 /* Call gig speed drop workaround on Gig disable before accessing
5529 * any PHY registers
5530 */
5531 e1000_gig_downshift_workaround_ich8lan(hw);
5532
5533 /* unable to acquire PCS lock */
5534 return -E1000_ERR_PHY;
5535}
5536
5545void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5546 bool state)
5547{
5548 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5549
5550 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5551
5552 if (hw->mac.type != e1000_ich8lan) {
5553 DEBUGOUT("Workaround applies to ICH8 only.\n");
5554 return;
5555 }
5556
5557 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5558
5559 return;
5560}
5561
5572void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5573{
5574 u32 reg;
5575 u16 data;
5576 u8 retry = 0;
5577
5578 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5579
5580 if (hw->phy.type != e1000_phy_igp_3)
5581 return;
5582
5583 /* Try the workaround twice (if needed) */
5584 do {
5585 /* Disable link */
5586 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5587 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5588 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5589 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5590
5591 /* Call gig speed drop workaround on Gig disable before
5592 * accessing any PHY registers
5593 */
5594 if (hw->mac.type == e1000_ich8lan)
5595 e1000_gig_downshift_workaround_ich8lan(hw);
5596
5597 /* Write VR power-down enable */
5598 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5599 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5600 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5601 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5602
5603 /* Read it back and test */
5604 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5605 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5606 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5607 break;
5608
5609 /* Issue PHY reset and repeat at most one more time */
5610 reg = E1000_READ_REG(hw, E1000_CTRL);
5611 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5612 retry++;
5613 } while (retry);
5614}
5615
5626void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5627{
5628 s32 ret_val;
5629 u16 reg_data = 0;
5630
5631 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5632
5633 if ((hw->mac.type != e1000_ich8lan) ||
5634 (hw->phy.type == e1000_phy_ife))
5635 return;
5636
5637 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5638 &reg_data);
5639 if (ret_val)
5640 return;
5641 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5642 ret_val = e1000_write_kmrn_reg_generic(hw,
5643 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5644 reg_data);
5645 if (ret_val)
5646 return;
5647 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5648 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5649 reg_data);
5650}
5651
5666void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5667{
5668 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5669 u32 phy_ctrl;
5670 s32 ret_val;
5671
5672 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5673
5674 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5675 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5676
5677 if (hw->phy.type == e1000_phy_i217) {
5678 u16 phy_reg, device_id = hw->device_id;
5679
5680 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5681 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5682 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5683 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5684 (hw->mac.type >= e1000_pch_spt)) {
5685 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5686
5687 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5688 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5689 }
5690
5691 ret_val = hw->phy.ops.acquire(hw);
5692 if (ret_val)
5693 goto out;
5694
5695 if (!dev_spec->eee_disable) {
5696 u16 eee_advert;
5697
5698 ret_val =
5699 e1000_read_emi_reg_locked(hw,
5700 I217_EEE_ADVERTISEMENT,
5701 &eee_advert);
5702 if (ret_val)
5703 goto release;
5704
5705 /* Disable LPLU if both link partners support 100BaseT
5706 * EEE and 100Full is advertised on both ends of the
5707 * link, and enable Auto Enable LPI since there will
5708 * be no driver to enable LPI while in Sx.
5709 */
5710 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5711 (dev_spec->eee_lp_ability &
5712 I82579_EEE_100_SUPPORTED) &&
5713 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5714 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5715 E1000_PHY_CTRL_NOND0A_LPLU);
5716
5717 /* Set Auto Enable LPI after link up */
5718 hw->phy.ops.read_reg_locked(hw,
5719 I217_LPI_GPIO_CTRL,
5720 &phy_reg);
5721 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5722 hw->phy.ops.write_reg_locked(hw,
5723 I217_LPI_GPIO_CTRL,
5724 phy_reg);
5725 }
5726 }
5727
5728 /* For i217 Intel Rapid Start Technology support,
5729 * when the system is going into Sx and no manageability engine
5730 * is present, the driver must configure proxy to reset only on
5731 * power good. LPI (Low Power Idle) state must also reset only
5732 * on power good, as well as the MTA (Multicast table array).
5733 * The SMBus release must also be disabled on LCD reset.
5734 */
5735 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5736 E1000_ICH_FWSM_FW_VALID)) {
5737 /* Enable proxy to reset only on power good. */
5738 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5739 &phy_reg);
5740 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5741 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5742 phy_reg);
5743
5744 /* Set bit enable LPI (EEE) to reset only on
5745 * power good.
5746 */
5747 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5748 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5749 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5750
5751 /* Disable the SMB release on LCD reset. */
5752 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5753 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5754 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5755 }
5756
5757 /* Enable MTA to reset for Intel Rapid Start Technology
5758 * Support
5759 */
5760 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5761 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5762 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5763
5764release:
5765 hw->phy.ops.release(hw);
5766 }
5767out:
5768 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5769
5770 if (hw->mac.type == e1000_ich8lan)
5771 e1000_gig_downshift_workaround_ich8lan(hw);
5772
5773 if (hw->mac.type >= e1000_pchlan) {
5774 e1000_oem_bits_config_ich8lan(hw, false);
5775
5776 /* Reset PHY to activate OEM bits on 82577/8 */
5777 if (hw->mac.type == e1000_pchlan)
5778 e1000_phy_hw_reset_generic(hw);
5779
5780 ret_val = hw->phy.ops.acquire(hw);
5781 if (ret_val)
5782 return;
5783 e1000_write_smbus_addr(hw);
5784 hw->phy.ops.release(hw);
5785 }
5786
5787 return;
5788}
5789
5800u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5801{
5802 s32 ret_val;
5803
5804 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5805 if (hw->mac.type < e1000_pch2lan)
5806 return E1000_SUCCESS;
5807
5808 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5809 if (ret_val) {
5810 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5811 return ret_val;
5812 }
5813
5814 /* For i217 Intel Rapid Start Technology support when the system
5815 * is transitioning from Sx and no manageability engine is present
5816 * configure SMBus to restore on reset, disable proxy, and enable
5817 * the reset on MTA (Multicast table array).
5818 */
5819 if (hw->phy.type == e1000_phy_i217) {
5820 u16 phy_reg;
5821
5822 ret_val = hw->phy.ops.acquire(hw);
5823 if (ret_val) {
5824 DEBUGOUT("Failed to setup iRST\n");
5825 return ret_val;
5826 }
5827
5828 /* Clear Auto Enable LPI after link up */
5829 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5830 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5831 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5832
5833 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5834 E1000_ICH_FWSM_FW_VALID)) {
5835 /* Restore clear on SMB if no manageability engine
5836 * is present
5837 */
5838 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5839 &phy_reg);
5840 if (ret_val)
5841 goto release;
5842 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5843 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5844
5845 /* Disable Proxy */
5846 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5847 }
5848 /* Enable reset on MTA */
5849 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5850 &phy_reg);
5851 if (ret_val)
5852 goto release;
5853 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5854 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5855release:
5856 if (ret_val)
5857 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5858 hw->phy.ops.release(hw);
5859 return ret_val;
5860 }
5861 return E1000_SUCCESS;
5862}
5863
5870static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5871{
5872 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5873
5874 if (hw->phy.type == e1000_phy_ife)
5875 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5876 0);
5877
5878 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5879 return E1000_SUCCESS;
5880}
5881
5888static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5889{
5890 DEBUGFUNC("e1000_led_on_ich8lan");
5891
5892 if (hw->phy.type == e1000_phy_ife)
5893 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5894 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5895
5896 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5897 return E1000_SUCCESS;
5898}
5899
5906static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5907{
5908 DEBUGFUNC("e1000_led_off_ich8lan");
5909
5910 if (hw->phy.type == e1000_phy_ife)
5911 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5912 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5913
5914 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5915 return E1000_SUCCESS;
5916}
5917
5924static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5925{
5926 DEBUGFUNC("e1000_setup_led_pchlan");
5927
5928 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5929 (u16)hw->mac.ledctl_mode1);
5930}
5931
5938static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5939{
5940 DEBUGFUNC("e1000_cleanup_led_pchlan");
5941
5942 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5943 (u16)hw->mac.ledctl_default);
5944}
5945
5952static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5953{
5954 u16 data = (u16)hw->mac.ledctl_mode2;
5955 u32 i, led;
5956
5957 DEBUGFUNC("e1000_led_on_pchlan");
5958
5959 /* If no link, then turn LED on by setting the invert bit
5960 * for each LED that's mode is "link_up" in ledctl_mode2.
5961 */
5962 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5963 for (i = 0; i < 3; i++) {
5964 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5965 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5966 E1000_LEDCTL_MODE_LINK_UP)
5967 continue;
5968 if (led & E1000_PHY_LED0_IVRT)
5969 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5970 else
5971 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5972 }
5973 }
5974
5975 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5976}
5977
5984static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5985{
5986 u16 data = (u16)hw->mac.ledctl_mode1;
5987 u32 i, led;
5988
5989 DEBUGFUNC("e1000_led_off_pchlan");
5990
5991 /* If no link, then turn LED off by clearing the invert bit
5992 * for each LED that's mode is "link_up" in ledctl_mode1.
5993 */
5994 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5995 for (i = 0; i < 3; i++) {
5996 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5997 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5998 E1000_LEDCTL_MODE_LINK_UP)
5999 continue;
6000 if (led & E1000_PHY_LED0_IVRT)
6001 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
6002 else
6003 data |= (E1000_PHY_LED0_IVRT << (i * 5));
6004 }
6005 }
6006
6007 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
6008}
6009
6022static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
6023{
6024 s32 ret_val = E1000_SUCCESS;
6025 u32 bank = 0;
6026 u32 status;
6027
6028 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
6029
6030 e1000_get_cfg_done_generic(hw);
6031
6032 /* Wait for indication from h/w that it has completed basic config */
6033 if (hw->mac.type >= e1000_ich10lan) {
6034 e1000_lan_init_done_ich8lan(hw);
6035 } else {
6036 ret_val = e1000_get_auto_rd_done_generic(hw);
6037 if (ret_val) {
6038 /* When auto config read does not complete, do not
6039 * return with an error. This can happen in situations
6040 * where there is no eeprom and prevents getting link.
6041 */
6042 DEBUGOUT("Auto Read Done did not complete\n");
6043 ret_val = E1000_SUCCESS;
6044 }
6045 }
6046
6047 /* Clear PHY Reset Asserted bit */
6048 status = E1000_READ_REG(hw, E1000_STATUS);
6049 if (status & E1000_STATUS_PHYRA)
6050 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6051 else
6052 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
6053
6054 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
6055 if (hw->mac.type <= e1000_ich9lan) {
6056 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6057 (hw->phy.type == e1000_phy_igp_3)) {
6058 e1000_phy_init_script_igp3(hw);
6059 }
6060 } else {
6061 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6062 /* Maybe we should do a basic PHY config */
6063 DEBUGOUT("EEPROM not present\n");
6064 ret_val = -E1000_ERR_CONFIG;
6065 }
6066 }
6067
6068 return ret_val;
6069}
6070
6078static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6079{
6080 /* If the management interface is not enabled, then power down */
6081 if (!(hw->mac.ops.check_mng_mode(hw) ||
6082 hw->phy.ops.check_reset_block(hw)))
6083 e1000_power_down_phy_copper(hw);
6084
6085 return;
6086}
6087
6095static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6096{
6097 u16 phy_data;
6098 s32 ret_val;
6099
6100 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6101
6102 e1000_clear_hw_cntrs_base_generic(hw);
6103
6104 E1000_READ_REG(hw, E1000_ALGNERRC);
6105 E1000_READ_REG(hw, E1000_RXERRC);
6106 E1000_READ_REG(hw, E1000_TNCRS);
6107 E1000_READ_REG(hw, E1000_CEXTERR);
6108 E1000_READ_REG(hw, E1000_TSCTC);
6109 E1000_READ_REG(hw, E1000_TSCTFC);
6110
6111 E1000_READ_REG(hw, E1000_MGTPRC);
6112 E1000_READ_REG(hw, E1000_MGTPDC);
6113 E1000_READ_REG(hw, E1000_MGTPTC);
6114
6115 E1000_READ_REG(hw, E1000_IAC);
6116 E1000_READ_REG(hw, E1000_ICRXOC);
6117
6118 /* Clear PHY statistics registers */
6119 if ((hw->phy.type == e1000_phy_82578) ||
6120 (hw->phy.type == e1000_phy_82579) ||
6121 (hw->phy.type == e1000_phy_i217) ||
6122 (hw->phy.type == e1000_phy_82577)) {
6123 ret_val = hw->phy.ops.acquire(hw);
6124 if (ret_val)
6125 return;
6126 ret_val = hw->phy.ops.set_page(hw,
6127 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6128 if (ret_val)
6129 goto release;
6130 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6131 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6132 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6133 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6134 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6135 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6136 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6137 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6138 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6139 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6140 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6141 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6142 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6143 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6144release:
6145 hw->phy.ops.release(hw);
6146 }
6147}
6148
6164s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6165{
6166 s32 ret_val;
6167 u16 kmrn_reg = 0;
6168
6169 DEBUGFUNC("e1000_configure_k0s_lpt");
6170
6171 if (entry_latency > 3 || min_time > 4)
6172 return -E1000_ERR_PARAM;
6173
6174 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6175 &kmrn_reg);
6176 if (ret_val)
6177 return ret_val;
6178
6179 /* for now don't touch the latency */
6180 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6181 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6182
6183 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6184 kmrn_reg);
6185 if (ret_val)
6186 return ret_val;
6187
6188 return E1000_SUCCESS;
6189}
e1000_read_nvm
s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_api.c:1340
e1000_api.h
E1000_MAX
#define E1000_MAX(a, b)
Definition: e1000_api.h:166
E1000_DIVIDE_ROUND_UP
#define E1000_DIVIDE_ROUND_UP(a, b)
Definition: e1000_api.h:167
ID_LED_RESERVED_0000
#define ID_LED_RESERVED_0000
Definition: e1000_defines.h:1213
E1000_ITR_MASK
#define E1000_ITR_MASK
Definition: e1000_defines.h:576
ID_LED_OFF1_OFF2
#define ID_LED_OFF1_OFF2
Definition: e1000_defines.h:1227
E1000_ERR_PHY
#define E1000_ERR_PHY
Definition: e1000_defines.h:711
IFE_E_PHY_ID
#define IFE_E_PHY_ID
Definition: e1000_defines.h:1276
PHY_REVISION_MASK
#define PHY_REVISION_MASK
Definition: e1000_defines.h:1256
E1000_RFCTL_NFSW_DIS
#define E1000_RFCTL_NFSW_DIS
Definition: e1000_defines.h:441
E1000_ERR_PARAM
#define E1000_ERR_PARAM
Definition: e1000_defines.h:713
E1000_EXTCNF_CTRL_GATE_PHY_CFG
#define E1000_EXTCNF_CTRL_GATE_PHY_CFG
Definition: e1000_defines.h:485
E1000_CTRL_LANPHYPC_OVERRIDE
#define E1000_CTRL_LANPHYPC_OVERRIDE
Definition: e1000_defines.h:272
E1000_PBS_16K
#define E1000_PBS_16K
Definition: e1000_defines.h:523
E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
Definition: e1000_defines.h:488
E1000_ITR_MULT
#define E1000_ITR_MULT
Definition: e1000_defines.h:577
E1000_PHY_CTRL_NOND0A_GBE_DISABLE
#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE
Definition: e1000_defines.h:493
IFE_C_E_PHY_ID
#define IFE_C_E_PHY_ID
Definition: e1000_defines.h:1278
E1000_STATUS_PHYRA
#define E1000_STATUS_PHYRA
Definition: e1000_defines.h:336
E1000_CTRL_EXT_PHYPDEN
#define E1000_CTRL_EXT_PHYPDEN
Definition: e1000_defines.h:98
E1000_EECD_SEC1VAL_VALID_MASK
#define E1000_EECD_SEC1VAL_VALID_MASK
Definition: e1000_defines.h:1056
E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
Definition: e1000_defines.h:489
E1000_TCTL_MULR
#define E1000_TCTL_MULR
Definition: e1000_defines.h:423
SPEED_100
#define SPEED_100
Definition: e1000_defines.h:352
E1000_CTRL_FRCSPD
#define E1000_CTRL_FRCSPD
Definition: e1000_defines.h:270
PHY_CONTROL
#define PHY_CONTROL
Definition: e1000_defines.h:1018
E1000_TXDCTL_MAX_TX_DESC_PREFETCH
#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH
Definition: e1000_defines.h:681
E1000_PHY_LED0_MASK
#define E1000_PHY_LED0_MASK
Definition: e1000_defines.h:383
ID_LED_ON1_DEF2
#define ID_LED_ON1_DEF2
Definition: e1000_defines.h:1222
ERROR_REPORT
#define ERROR_REPORT(fmt)
Definition: e1000_defines.h:1524
E1000_STATUS_SPEED_1000
#define E1000_STATUS_SPEED_1000
Definition: e1000_defines.h:334
E1000_BLK_PHY_RESET
#define E1000_BLK_PHY_RESET
Definition: e1000_defines.h:719
E1000_ALL_SPEED_DUPLEX
#define E1000_ALL_SPEED_DUPLEX
Definition: e1000_defines.h:368
SPEED_1000
#define SPEED_1000
Definition: e1000_defines.h:353
E1000_TCTL_PSP
#define E1000_TCTL_PSP
Definition: e1000_defines.h:419
E1000_CTRL_MEHE
#define E1000_CTRL_MEHE
Definition: e1000_defines.h:274
ID_LED_DEF1_OFF2
#define ID_LED_DEF1_OFF2
Definition: e1000_defines.h:1221
E1000_PHY_CTRL_GBE_DISABLE
#define E1000_PHY_CTRL_GBE_DISABLE
Definition: e1000_defines.h:494
PHY_ID1
#define PHY_ID1
Definition: e1000_defines.h:1020
HALF_DUPLEX
#define HALF_DUPLEX
Definition: e1000_defines.h:355
E1000_CTRL_SLU
#define E1000_CTRL_SLU
Definition: e1000_defines.h:264
ID_LED_DEF1_ON2
#define ID_LED_DEF1_ON2
Definition: e1000_defines.h:1220
E1000_ALL_10_SPEED
#define E1000_ALL_10_SPEED
Definition: e1000_defines.h:375
E1000_STATUS_SPEED_100
#define E1000_STATUS_SPEED_100
Definition: e1000_defines.h:333
E1000_CTRL_EXT_SPD_BYPS
#define E1000_CTRL_EXT_SPD_BYPS
Definition: e1000_defines.h:82
E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
Definition: e1000_defines.h:482
E1000_CTRL_EXT_RO_DIS
#define E1000_CTRL_EXT_RO_DIS
Definition: e1000_defines.h:83
E1000_LEDCTL_MODE_LINK_UP
#define E1000_LEDCTL_MODE_LINK_UP
Definition: e1000_defines.h:390
ID_LED_OFF1_ON2
#define ID_LED_OFF1_ON2
Definition: e1000_defines.h:1226
ID_LED_RESERVED_FFFF
#define ID_LED_RESERVED_FFFF
Definition: e1000_defines.h:1214
E1000_CTRL_PHY_RST
#define E1000_CTRL_PHY_RST
Definition: e1000_defines.h:289
ID_LED_ON1_ON2
#define ID_LED_ON1_ON2
Definition: e1000_defines.h:1223
PHY_CFG_TIMEOUT
#define PHY_CFG_TIMEOUT
Definition: e1000_defines.h:737
E1000_STATUS_FD
#define E1000_STATUS_FD
Definition: e1000_defines.h:325
E1000_PHY_LED0_IVRT
#define E1000_PHY_LED0_IVRT
Definition: e1000_defines.h:382
E1000_CTRL_RST
#define E1000_CTRL_RST
Definition: e1000_defines.h:285
E1000_PHY_CTRL_D0A_LPLU
#define E1000_PHY_CTRL_D0A_LPLU
Definition: e1000_defines.h:491
E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
Definition: e1000_defines.h:487
E1000_PBECCSTS_ECC_ENABLE
#define E1000_PBECCSTS_ECC_ENABLE
Definition: e1000_defines.h:529
E1000_STATUS_LU
#define E1000_STATUS_LU
Definition: e1000_defines.h:326
E1000_PBA_RXA_MASK
#define E1000_PBA_RXA_MASK
Definition: e1000_defines.h:521
AUTONEG_ADVERTISE_SPEED_DEFAULT
#define AUTONEG_ADVERTISE_SPEED_DEFAULT
Definition: e1000_defines.h:378
PCIE_NO_SNOOP_ALL
#define PCIE_NO_SNOOP_ALL
Definition: e1000_defines.h:905
PHY_LP_ABILITY
#define PHY_LP_ABILITY
Definition: e1000_defines.h:1023
PHY_ID2
#define PHY_ID2
Definition: e1000_defines.h:1021
ID_LED_ON1_OFF2
#define ID_LED_ON1_OFF2
Definition: e1000_defines.h:1224
ADVERTISE_100_FULL
#define ADVERTISE_100_FULL
Definition: e1000_defines.h:363
E1000_ALL_NOT_GIG
#define E1000_ALL_NOT_GIG
Definition: e1000_defines.h:371
ID_LED_OFF1_DEF2
#define ID_LED_OFF1_DEF2
Definition: e1000_defines.h:1225
E1000_RFCTL_NFSR_DIS
#define E1000_RFCTL_NFSR_DIS
Definition: e1000_defines.h:442
NVM_FUTURE_INIT_WORD1_VALID_CSUM
#define NVM_FUTURE_INIT_WORD1_VALID_CSUM
Definition: e1000_defines.h:1135
SPEED_10
#define SPEED_10
Definition: e1000_defines.h:351
E1000_RCTL_SECRC
#define E1000_RCTL_SECRC
Definition: e1000_defines.h:221
E1000_TX_PTR_GAP
#define E1000_TX_PTR_GAP
Definition: e1000_defines.h:478
E1000_EECD_PRES
#define E1000_EECD_PRES
Definition: e1000_defines.h:1040
E1000_PBA_8K
#define E1000_PBA_8K
Definition: e1000_defines.h:502
E1000_CTRL_EXT_FORCE_SMBUS
#define E1000_CTRL_EXT_FORCE_SMBUS
Definition: e1000_defines.h:77
E1000_EECD_SEC1VAL
#define E1000_EECD_SEC1VAL
Definition: e1000_defines.h:1055
E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
Definition: e1000_defines.h:483
NVM_COMPAT
#define NVM_COMPAT
Definition: e1000_defines.h:1084
BME1000_E_PHY_ID
#define BME1000_E_PHY_ID
Definition: e1000_defines.h:1279
E1000_KABGTXD_BGSQLBIAS
#define E1000_KABGTXD_BGSQLBIAS
Definition: e1000_defines.h:496
E1000_PHY_CTRL_NOND0A_LPLU
#define E1000_PHY_CTRL_NOND0A_LPLU
Definition: e1000_defines.h:492
NVM_COMPAT_VALID_CSUM
#define NVM_COMPAT_VALID_CSUM
Definition: e1000_defines.h:1134
E1000_WUFC_LNKC
#define E1000_WUFC_LNKC
Definition: e1000_defines.h:52
E1000_CTRL_FRCDPX
#define E1000_CTRL_FRCDPX
Definition: e1000_defines.h:271
E1000_STATUS_LAN_INIT_DONE
#define E1000_STATUS_LAN_INIT_DONE
Definition: e1000_defines.h:335
E1000_ERR_CONFIG
#define E1000_ERR_CONFIG
Definition: e1000_defines.h:712
E1000_LEDCTL_LED0_MODE_MASK
#define E1000_LEDCTL_LED0_MODE_MASK
Definition: e1000_defines.h:385
E1000_SUCCESS
#define E1000_SUCCESS
Definition: e1000_defines.h:709
E1000_RAH_AV
#define E1000_RAH_AV
Definition: e1000_defines.h:702
NVM_FUTURE_INIT_WORD1
#define NVM_FUTURE_INIT_WORD1
Definition: e1000_defines.h:1091
E1000_RFCTL_NEW_IPV6_EXT_DIS
#define E1000_RFCTL_NEW_IPV6_EXT_DIS
Definition: e1000_defines.h:446
IFE_PLUS_E_PHY_ID
#define IFE_PLUS_E_PHY_ID
Definition: e1000_defines.h:1277
E1000_CTRL_SPD_1000
#define E1000_CTRL_SPD_1000
Definition: e1000_defines.h:269
E1000_PHY_LED0_MODE_MASK
#define E1000_PHY_LED0_MODE_MASK
Definition: e1000_defines.h:381
E1000_CTRL_EXT_LPCD
#define E1000_CTRL_EXT_LPCD
Definition: e1000_defines.h:69
E1000_CTRL_SPD_100
#define E1000_CTRL_SPD_100
Definition: e1000_defines.h:268
E1000_ERR_NVM
#define E1000_ERR_NVM
Definition: e1000_defines.h:710
FULL_DUPLEX
#define FULL_DUPLEX
Definition: e1000_defines.h:356
E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
Definition: e1000_defines.h:486
E1000_TXDCTL_FULL_TX_DESC_WB
#define E1000_TXDCTL_FULL_TX_DESC_WB
Definition: e1000_defines.h:680
NVM_ID_LED_SETTINGS
#define NVM_ID_LED_SETTINGS
Definition: e1000_defines.h:1085
NWAY_LPAR_100TX_FD_CAPS
#define NWAY_LPAR_100TX_FD_CAPS
Definition: e1000_defines.h:973
E1000_RFCTL_IPV6_EX_DIS
#define E1000_RFCTL_IPV6_EX_DIS
Definition: e1000_defines.h:445
E1000_EXTCNF_CTRL_SWFLAG
#define E1000_EXTCNF_CTRL_SWFLAG
Definition: e1000_defines.h:484
IGP03E1000_E_PHY_ID
#define IGP03E1000_E_PHY_ID
Definition: e1000_defines.h:1275
E1000_DEV_ID_PCH_LPT_I217_V
#define E1000_DEV_ID_PCH_LPT_I217_V
Definition: e1000_hw.h:134
E1000_DEV_ID_PCH_LPTLP_I218_LM
#define E1000_DEV_ID_PCH_LPTLP_I218_LM
Definition: e1000_hw.h:135
e1000_phy_i217
@ e1000_phy_i217
Definition: e1000_hw.h:320
e1000_phy_82577
@ e1000_phy_82577
Definition: e1000_hw.h:318
e1000_phy_bm
@ e1000_phy_bm
Definition: e1000_hw.h:316
e1000_phy_82579
@ e1000_phy_82579
Definition: e1000_hw.h:319
e1000_phy_ife
@ e1000_phy_ife
Definition: e1000_hw.h:315
e1000_phy_82578
@ e1000_phy_82578
Definition: e1000_hw.h:317
e1000_phy_unknown
@ e1000_phy_unknown
Definition: e1000_hw.h:308
e1000_phy_igp_3
@ e1000_phy_igp_3
Definition: e1000_hw.h:314
e1000_bus_width_pcie_x1
@ e1000_bus_width_pcie_x1
Definition: e1000_hw.h:348
e1000_bus_width_unknown
@ e1000_bus_width_unknown
Definition: e1000_hw.h:347
E1000_DEV_ID_PCH_I218_LM2
#define E1000_DEV_ID_PCH_I218_LM2
Definition: e1000_hw.h:137
E1000_DEV_ID_ICH8_IGP_C
#define E1000_DEV_ID_ICH8_IGP_C
Definition: e1000_hw.h:107
E1000_DEV_ID_ICH8_IGP_AMT
#define E1000_DEV_ID_ICH8_IGP_AMT
Definition: e1000_hw.h:106
E1000_DEV_ID_PCH_I218_V2
#define E1000_DEV_ID_PCH_I218_V2
Definition: e1000_hw.h:138
e1000_ich8lan
@ e1000_ich8lan
Definition: e1000_hw.h:258
e1000_pch_mtp
@ e1000_pch_mtp
Definition: e1000_hw.h:268
e1000_pch2lan
@ e1000_pch2lan
Definition: e1000_hw.h:262
e1000_pch_cnp
@ e1000_pch_cnp
Definition: e1000_hw.h:265
e1000_pch_spt
@ e1000_pch_spt
Definition: e1000_hw.h:264
e1000_ich9lan
@ e1000_ich9lan
Definition: e1000_hw.h:259
e1000_ich10lan
@ e1000_ich10lan
Definition: e1000_hw.h:260
e1000_pch_lpt
@ e1000_pch_lpt
Definition: e1000_hw.h:263
e1000_pch_adp
@ e1000_pch_adp
Definition: e1000_hw.h:267
e1000_pchlan
@ e1000_pchlan
Definition: e1000_hw.h:261
e1000_pch_tgp
@ e1000_pch_tgp
Definition: e1000_hw.h:266
E1000_SHADOW_RAM_WORDS
#define E1000_SHADOW_RAM_WORDS
Definition: e1000_hw.h:982
e1000_fc_default
@ e1000_fc_default
Definition: e1000_hw.h:374
e1000_fc_full
@ e1000_fc_full
Definition: e1000_hw.h:373
e1000_smart_speed_off
@ e1000_smart_speed_off
Definition: e1000_hw.h:400
e1000_smart_speed_on
@ e1000_smart_speed_on
Definition: e1000_hw.h:399
E1000_DEV_ID_PCH_I218_LM3
#define E1000_DEV_ID_PCH_I218_LM3
Definition: e1000_hw.h:139
e1000_media_type_copper
@ e1000_media_type_copper
Definition: e1000_hw.h:283
E1000_DEV_ID_PCH_LPTLP_I218_V
#define E1000_DEV_ID_PCH_LPTLP_I218_V
Definition: e1000_hw.h:136
e1000_ulp_state_unknown
@ e1000_ulp_state_unknown
Definition: e1000_hw.h:986
e1000_ulp_state_on
@ e1000_ulp_state_on
Definition: e1000_hw.h:988
e1000_ulp_state_off
@ e1000_ulp_state_off
Definition: e1000_hw.h:987
e1000_nvm_flash_sw
@ e1000_nvm_flash_sw
Definition: e1000_hw.h:296
E1000_DEV_ID_PCH_LPT_I217_LM
#define E1000_DEV_ID_PCH_LPT_I217_LM
Definition: e1000_hw.h:133
e1000_read_pci_cfg
void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
Definition: e1000_osdep.c:51
E1000_DEV_ID_PCH_I218_V3
#define E1000_DEV_ID_PCH_I218_V3
Definition: e1000_hw.h:140
e1000_read_nvm_spt
static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_ich8lan.c:3526
e1000_post_phy_reset_ich8lan
static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:3099
e1000_set_eee_pchlan
s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:915
e1000_set_mdio_slow_mode_hv
static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2611
e1000_resume_workarounds_pchlan
u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5800
e1000_suspend_workarounds_ich8lan
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5666
e1000_igp3_phy_powerdown_workaround_ich8lan
void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5572
e1000_update_nvm_checksum_ich8lan
static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:4241
e1000_phy_is_accessible_pchlan
static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:201
e1000_rar_set_pch_lpt
static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
Definition: e1000_ich8lan.c:2091
e1000_write_nvm_ich8lan
static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_ich8lan.c:4041
e1000_retry_write_flash_dword_ich8lan
static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, u32 dword)
Definition: e1000_ich8lan.c:4652
e1000_validate_nvm_checksum_ich8lan
static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:4391
e1000_oem_bits_config_ich8lan
static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
Definition: e1000_ich8lan.c:2544
e1000_init_phy_params_pchlan
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:454
__e1000_access_emi_reg_locked
static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, u16 *data, bool read)
Definition: e1000_ich8lan.c:850
e1000_erase_flash_bank_ich8lan
static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
Definition: e1000_ich8lan.c:4722
e1000_enable_ulp_lpt_lp
s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
Definition: e1000_ich8lan.c:1267
e1000_init_nvm_params_ich8lan
static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:640
e1000_setup_copper_link_ich8lan
static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5328
e1000_setup_led_pchlan
static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5924
e1000_power_down_phy_copper_ich8lan
static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:6078
e1000_check_for_copper_link_ich8lan
static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1558
e1000_configure_k0s_lpt
s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
Definition: e1000_ich8lan.c:6164
e1000_k1_gig_workaround_hv
static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
Definition: e1000_ich8lan.c:2409
e1000_configure_k1_ich8lan
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
Definition: e1000_ich8lan.c:2491
e1000_valid_led_default_ich8lan
static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
Definition: e1000_ich8lan.c:4843
e1000_init_phy_workarounds_pchlan
static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:317
e1000_set_lplu_state_pchlan
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
Definition: e1000_ich8lan.c:3201
e1000_k1_workaround_lpt_lp
static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
Definition: e1000_ich8lan.c:1016
e1000_check_mng_mode_pchlan
static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1999
e1000_update_nvm_checksum_spt
static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:4079
e1000_platform_pm_pch_lpt
static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
Definition: e1000_ich8lan.c:1125
e1000_init_hw_ich8lan
static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5106
e1000_read_flash_data_ich8lan
static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, u8 size, u16 *data)
Definition: e1000_ich8lan.c:3887
e1000_sw_lcd_config_ich8lan
static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2279
e1000_rar_set_pch2lan
static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
Definition: e1000_ich8lan.c:2022
e1000_cleanup_led_pchlan
static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5938
e1000_write_flash_byte_ich8lan
static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 data)
Definition: e1000_ich8lan.c:4633
e1000_update_mc_addr_list_pch2lan
static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count)
Definition: e1000_ich8lan.c:2168
e1000_flash_cycle_init_ich8lan
static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:3681
e1000_init_phy_params_ich8lan
static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:548
e1000_get_cfg_done_ich8lan
static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:6022
e1000_setup_copper_link_pch_lpt
static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5419
e1000_setup_link_ich8lan
static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5275
e1000_read_flash_word_ich8lan
static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_ich8lan.c:3834
e1000_cleanup_led_ich8lan
static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5870
e1000_acquire_swflag_ich8lan
static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1896
e1000_lv_jumbo_workaround_ich8lan
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
Definition: e1000_ich8lan.c:2782
e1000_gate_hw_phy_config_ich8lan
static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
Definition: e1000_ich8lan.c:3043
e1000_hv_phy_workarounds_ich8lan
static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2634
e1000_write_smbus_addr
static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2238
e1000_read_emi_reg_locked
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
Definition: e1000_ich8lan.c:879
e1000_release_swflag_ich8lan
static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1954
e1000_ltr2ns
static u64 e1000_ltr2ns(u16 ltr)
Definition: e1000_ich8lan.c:1095
e1000_calc_rx_da_crc
static u32 e1000_calc_rx_da_crc(u8 mac[])
Definition: e1000_ich8lan.c:2758
e1000_valid_nvm_bank_detect_ich8lan
static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
Definition: e1000_ich8lan.c:3420
e1000_init_mac_params_ich8lan
static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:730
e1000_check_mng_mode_ich8lan
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1978
e1000_gig_downshift_workaround_ich8lan
void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5626
e1000_get_link_up_info_ich8lan
static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
Definition: e1000_ich8lan.c:5448
e1000_led_off_pchlan
static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5984
e1000_initialize_hw_bits_ich8lan
static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5191
e1000_set_kmrn_lock_loss_workaround_ich8lan
void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, bool state)
Definition: e1000_ich8lan.c:5545
e1000_write_emi_reg_locked
s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
Definition: e1000_ich8lan.c:894
e1000_flash_cycle_ich8lan
static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
Definition: e1000_ich8lan.c:3767
e1000_toggle_lanphypc_pch_lpt
static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:273
e1000_reset_hw_ich8lan
static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:4969
e1000_led_on_ich8lan
static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5888
e1000_release_nvm_ich8lan
static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1882
e1000_read_flash_data32_ich8lan
static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, u32 *data)
Definition: e1000_ich8lan.c:3962
e1000_lv_phy_workarounds_ich8lan
static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2956
e1000_disable_ulp_lpt_lp
s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
Definition: e1000_ich8lan.c:1417
e1000_led_on_pchlan
static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5952
e1000_set_d3_lplu_state_ich8lan
static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
Definition: e1000_ich8lan.c:3331
e1000_set_d0_lplu_state_ich8lan
static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
Definition: e1000_ich8lan.c:3235
e1000_clear_hw_cntrs_ich8lan
static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:6095
e1000_set_obff_timer_pch_lpt
static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
Definition: e1000_ich8lan.c:1233
e1000_led_off_ich8lan
static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5906
e1000_read_flash_dword_ich8lan
static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, u32 *data)
Definition: e1000_ich8lan.c:3811
e1000_get_bus_info_ich8lan
static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:4942
e1000_lan_init_done_ich8lan
static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:3069
e1000_write_flash_data32_ich8lan
static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, u32 data)
Definition: e1000_ich8lan.c:4544
e1000_phy_hw_reset_ich8lan
static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:3172
e1000_k1_workaround_lv
static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2992
e1000_init_function_pointers_ich8lan
void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1834
e1000_acquire_nvm_ich8lan
static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:1867
e1000_copy_rx_addrs_to_phy_ich8lan
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2721
e1000_retry_write_flash_byte_ich8lan
static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 byte)
Definition: e1000_ich8lan.c:4689
e1000_write_flash_data_ich8lan
static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, u8 size, u16 data)
Definition: e1000_ich8lan.c:4447
e1000_id_led_init_pchlan
static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:4874
e1000_check_reset_block_ich8lan
static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:2211
e1000_read_nvm_ich8lan
static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
Definition: e1000_ich8lan.c:3621
e1000_kmrn_lock_loss_workaround_ich8lan
static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
Definition: e1000_ich8lan.c:5483
e1000_read_flash_byte_ich8lan
static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, u8 *data)
Definition: e1000_ich8lan.c:3856
SW_FLAG_TIMEOUT
#define SW_FLAG_TIMEOUT
Definition: e1000_ich8lan.h:251
HV_ECOL_LOWER
#define HV_ECOL_LOWER
Definition: e1000_ich8lan.h:175
I217_CGFREG
#define I217_CGFREG
Definition: e1000_ich8lan.h:302
E1000_STRAP
#define E1000_STRAP
Definition: e1000_ich8lan.h:222
ICH_CYCLE_READ
#define ICH_CYCLE_READ
Definition: e1000_ich8lan.h:52
I217_INBAND_CTRL
#define I217_INBAND_CTRL
Definition: e1000_ich8lan.h:254
HV_COLC_LOWER
#define HV_COLC_LOWER
Definition: e1000_ich8lan.h:181
E1000_ICH_FWSM_RSPCIPHY
#define E1000_ICH_FWSM_RSPCIPHY
Definition: e1000_ich8lan.h:64
HV_OEM_BITS_GBE_DIS
#define HV_OEM_BITS_GBE_DIS
Definition: e1000_ich8lan.h:231
E1000_ICH_NVM_VALID_SIG_MASK
#define E1000_ICH_NVM_VALID_SIG_MASK
Definition: e1000_ich8lan.h:91
HV_SMB_ADDR_VALID
#define HV_SMB_ADDR_VALID
Definition: e1000_ich8lan.h:216
HV_COLC_UPPER
#define HV_COLC_UPPER
Definition: e1000_ich8lan.h:180
HV_OEM_BITS
#define HV_OEM_BITS
Definition: e1000_ich8lan.h:229
E1000_STRAP_SMT_FREQ_SHIFT
#define E1000_STRAP_SMT_FREQ_SHIFT
Definition: e1000_ich8lan.h:226
HV_DC_LOWER
#define HV_DC_LOWER
Definition: e1000_ich8lan.h:183
E1000_ICH_MNG_IAMT_MODE
#define E1000_ICH_MNG_IAMT_MODE
Definition: e1000_ich8lan.h:70
E1000_SVT_OFF_HWM_MASK
#define E1000_SVT_OFF_HWM_MASK
Definition: e1000_ich8lan.h:329
I82579_LPI_CTRL_100_ENABLE
#define I82579_LPI_CTRL_100_ENABLE
Definition: e1000_ich8lan.h:264
I82579_MSE_THRESHOLD
#define I82579_MSE_THRESHOLD
Definition: e1000_ich8lan.h:276
BM_PORT_GEN_CFG
#define BM_PORT_GEN_CFG
Definition: e1000_ich8lan.h:147
E1000_FEXT_PHY_CABLE_DISCONNECTED
#define E1000_FEXT_PHY_CABLE_DISCONNECTED
Definition: e1000_ich8lan.h:97
E1000_LTRV
#define E1000_LTRV
Definition: e1000_ich8lan.h:311
E1000_LTRV_SCALE_MASK
#define E1000_LTRV_SCALE_MASK
Definition: e1000_ich8lan.h:316
I217_LPI_GPIO_CTRL
#define I217_LPI_GPIO_CTRL
Definition: e1000_ich8lan.h:259
HV_LATECOL_UPPER
#define HV_LATECOL_UPPER
Definition: e1000_ich8lan.h:178
HV_MCC_UPPER
#define HV_MCC_UPPER
Definition: e1000_ich8lan.h:176
I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
Definition: e1000_ich8lan.h:209
ICH_FLASH_SEG_SIZE_64K
#define ICH_FLASH_SEG_SIZE_64K
Definition: e1000_ich8lan.h:62
ICH_FLASH_SEG_SIZE_4K
#define ICH_FLASH_SEG_SIZE_4K
Definition: e1000_ich8lan.h:60
I217_MEMPWR_DISABLE_SMB_RELEASE
#define I217_MEMPWR_DISABLE_SMB_RELEASE
Definition: e1000_ich8lan.h:305
E1000_ICH8_LAN_INIT_TIMEOUT
#define E1000_ICH8_LAN_INIT_TIMEOUT
Definition: e1000_ich8lan.h:94
E1000_FEXTNVM4_BEACON_DURATION_16USEC
#define E1000_FEXTNVM4_BEACON_DURATION_16USEC
Definition: e1000_ich8lan.h:107
HV_PM_CTRL_K1_CLK_REQ
#define HV_PM_CTRL_K1_CLK_REQ
Definition: e1000_ich8lan.h:245
I218_ULP_CONFIG1_WOL_HOST
#define I218_ULP_CONFIG1_WOL_HOST
Definition: e1000_ich8lan.h:204
HV_MCC_LOWER
#define HV_MCC_LOWER
Definition: e1000_ich8lan.h:177
PCIE_ICH8_SNOOP_ALL
#define PCIE_ICH8_SNOOP_ALL
Definition: e1000_ich8lan.h:130
E1000_FEXTNVM7_DISABLE_SMB_PERST
#define E1000_FEXTNVM7_DISABLE_SMB_PERST
Definition: e1000_ich8lan.h:115
ICH_FLASH_CYCLE_REPEAT_COUNT
#define ICH_FLASH_CYCLE_REPEAT_COUNT
Definition: e1000_ich8lan.h:50
ICH_FLASH_FADDR
#define ICH_FLASH_FADDR
Definition: e1000_ich8lan.h:42
ICH_FLASH_FDATA0
#define ICH_FLASH_FDATA0
Definition: e1000_ich8lan.h:43
I217_LPI_GPIO_CTRL_AUTO_EN_LPI
#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI
Definition: e1000_ich8lan.h:260
HV_KMRN_MDIO_SLOW
#define HV_KMRN_MDIO_SLOW
Definition: e1000_ich8lan.h:236
I218_ULP_CONFIG1_RESET_TO_SMBUS
#define I218_ULP_CONFIG1_RESET_TO_SMBUS
Definition: e1000_ich8lan.h:205
E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
Definition: e1000_ich8lan.h:103
HV_TNCRS_UPPER
#define HV_TNCRS_UPPER
Definition: e1000_ich8lan.h:184
E1000_PCH2_RAR_ENTRIES
#define E1000_PCH2_RAR_ENTRIES
Definition: e1000_ich8lan.h:133
ICH_FLASH_SEG_SIZE_8K
#define ICH_FLASH_SEG_SIZE_8K
Definition: e1000_ich8lan.h:61
I217_CGFREG_ENABLE_MTA_RESET
#define I217_CGFREG_ENABLE_MTA_RESET
Definition: e1000_ich8lan.h:303
I82579_EEE_LP_ABILITY
#define I82579_EEE_LP_ABILITY
Definition: e1000_ich8lan.h:284
ICH_FLASH_HSFCTL
#define ICH_FLASH_HSFCTL
Definition: e1000_ich8lan.h:41
ICH_FLASH_LINEAR_ADDR_MASK
#define ICH_FLASH_LINEAR_ADDR_MASK
Definition: e1000_ich8lan.h:49
I217_EEE_PCS_STATUS
#define I217_EEE_PCS_STATUS
Definition: e1000_ich8lan.h:288
I217_EEE_LP_ABILITY
#define I217_EEE_LP_ABILITY
Definition: e1000_ich8lan.h:291
ICH_FLASH_SEG_SIZE_256
#define ICH_FLASH_SEG_SIZE_256
Definition: e1000_ich8lan.h:59
I82579_LPI_CTRL_1000_ENABLE
#define I82579_LPI_CTRL_1000_ENABLE
Definition: e1000_ich8lan.h:265
HV_LED_CONFIG
#define HV_LED_CONFIG
Definition: e1000_ich8lan.h:166
HV_DC_UPPER
#define HV_DC_UPPER
Definition: e1000_ich8lan.h:182
HV_SMB_ADDR_PEC_EN
#define HV_SMB_ADDR_PEC_EN
Definition: e1000_ich8lan.h:215
HV_KMRN_FIFO_CTRLSTA
#define HV_KMRN_FIFO_CTRLSTA
Definition: e1000_ich8lan.h:239
I218_ULP_CONFIG1_EN_ULP_LANPHYPC
#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC
Definition: e1000_ich8lan.h:207
E1000_STRAP_SMT_FREQ_MASK
#define E1000_STRAP_SMT_FREQ_MASK
Definition: e1000_ich8lan.h:225
E1000_FWSM_WLOCK_MAC_MASK
#define E1000_FWSM_WLOCK_MAC_MASK
Definition: e1000_ich8lan.h:72
E1000_ICH_FWSM_FW_VALID
#define E1000_ICH_FWSM_FW_VALID
Definition: e1000_ich8lan.h:66
E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION
#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION
Definition: e1000_ich8lan.h:110
IGP3_VR_CTRL
#define IGP3_VR_CTRL
Definition: e1000_ich8lan.h:140
ICH_CYCLE_WRITE
#define ICH_CYCLE_WRITE
Definition: e1000_ich8lan.h:53
I82579_RX_CONFIG
#define I82579_RX_CONFIG
Definition: e1000_ich8lan.h:279
E1000_FEXTNVM6_K1_OFF_ENABLE
#define E1000_FEXTNVM6_K1_OFF_ENABLE
Definition: e1000_ich8lan.h:111
HV_SCC_LOWER
#define HV_SCC_LOWER
Definition: e1000_ich8lan.h:173
I218_ULP_CONFIG1_DISABLE_SMB_PERST
#define I218_ULP_CONFIG1_DISABLE_SMB_PERST
Definition: e1000_ich8lan.h:210
E1000_SHRAH_PCH_LPT
#define E1000_SHRAH_PCH_LPT(_i)
Definition: e1000_ich8lan.h:78
E1000_ICH_RAR_ENTRIES
#define E1000_ICH_RAR_ENTRIES
Definition: e1000_ich8lan.h:132
ICH_FLASH_READ_COMMAND_TIMEOUT
#define ICH_FLASH_READ_COMMAND_TIMEOUT
Definition: e1000_ich8lan.h:46
E1000_H2ME_ULP
#define E1000_H2ME_ULP
Definition: e1000_ich8lan.h:81
BM_RAR_L
#define BM_RAR_L(_i)
Definition: e1000_ich8lan.h:152
E1000_ICH_NVM_SIG_WORD
#define E1000_ICH_NVM_SIG_WORD
Definition: e1000_ich8lan.h:89
I82579_EEE_ADVERTISEMENT
#define I82579_EEE_ADVERTISEMENT
Definition: e1000_ich8lan.h:283
I218_ULP_CONFIG1_INBAND_EXIT
#define I218_ULP_CONFIG1_INBAND_EXIT
Definition: e1000_ich8lan.h:203
I82579_EEE_1000_SUPPORTED
#define I82579_EEE_1000_SUPPORTED
Definition: e1000_ich8lan.h:286
HV_STATS_PAGE
#define HV_STATS_PAGE
Definition: e1000_ich8lan.h:170
E1000_FEXTNVM_SW_CONFIG
#define E1000_FEXTNVM_SW_CONFIG
Definition: e1000_ich8lan.h:99
ID_LED_DEFAULT_ICH8LAN
#define ID_LED_DEFAULT_ICH8LAN
Definition: e1000_ich8lan.h:84
PHY_REG
#define PHY_REG(page, reg)
Definition: e1000_ich8lan.h:137
I82579_LPI_UPDATE_TIMER
#define I82579_LPI_UPDATE_TIMER
Definition: e1000_ich8lan.h:275
CV_SMB_CTRL_FORCE_SMBUS
#define CV_SMB_CTRL_FORCE_SMBUS
Definition: e1000_ich8lan.h:196
E1000_LTRV_REQ_SHIFT
#define E1000_LTRV_REQ_SHIFT
Definition: e1000_ich8lan.h:317
K1_ENTRY_LATENCY
#define K1_ENTRY_LATENCY
Definition: e1000_ich8lan.h:191
HV_OEM_BITS_RESTART_AN
#define HV_OEM_BITS_RESTART_AN
Definition: e1000_ich8lan.h:232
E1000_FCRTV_PCH
#define E1000_FCRTV_PCH
Definition: e1000_ich8lan.h:187
BM_RAR_M
#define BM_RAR_M(_i)
Definition: e1000_ich8lan.h:153
E1000_ICH_NVM_SIG_MASK
#define E1000_ICH_NVM_SIG_MASK
Definition: e1000_ich8lan.h:90
I82579_EEE_100_SUPPORTED
#define I82579_EEE_100_SUPPORTED
Definition: e1000_ich8lan.h:285
E1000_STRAP_SMBUS_ADDRESS_SHIFT
#define E1000_STRAP_SMBUS_ADDRESS_SHIFT
Definition: e1000_ich8lan.h:224
E1000_PCH_LPT_RAR_ENTRIES
#define E1000_PCH_LPT_RAR_ENTRIES
Definition: e1000_ich8lan.h:134
I82577_MSE_THRESHOLD
#define I82577_MSE_THRESHOLD
Definition: e1000_ich8lan.h:277
NVM_SIZE_MULTIPLIER
#define NVM_SIZE_MULTIPLIER
Definition: e1000_ich8lan.h:125
I218_ULP_CONFIG1
#define I218_ULP_CONFIG1
Definition: e1000_ich8lan.h:199
E1000_LTRV_SCALE_MAX
#define E1000_LTRV_SCALE_MAX
Definition: e1000_ich8lan.h:313
HV_OEM_BITS_LPLU
#define HV_OEM_BITS_LPLU
Definition: e1000_ich8lan.h:230
E1000_LTRV_SCALE_FACTOR
#define E1000_LTRV_SCALE_FACTOR
Definition: e1000_ich8lan.h:314
ICH_FLASH_HSFSTS
#define ICH_FLASH_HSFSTS
Definition: e1000_ich8lan.h:40
I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
Definition: e1000_ich8lan.h:256
E1000_H2ME
#define E1000_H2ME
Definition: e1000_ich8lan.h:80
BM_RAR_H
#define BM_RAR_H(_i)
Definition: e1000_ich8lan.h:154
FLASH_SECTOR_ADDR_SHIFT
#define FLASH_SECTOR_ADDR_SHIFT
Definition: e1000_ich8lan.h:57
E1000_FEXTNVM6_REQ_PLL_CLK
#define E1000_FEXTNVM6_REQ_PLL_CLK
Definition: e1000_ich8lan.h:109
HV_PM_CTRL
#define HV_PM_CTRL
Definition: e1000_ich8lan.h:244
BM_RAR_CTRL
#define BM_RAR_CTRL(_i)
Definition: e1000_ich8lan.h:155
I82579_LPI_PLL_SHUT
#define I82579_LPI_PLL_SHUT
Definition: e1000_ich8lan.h:280
I217_PROXY_CTRL
#define I217_PROXY_CTRL
Definition: e1000_ich8lan.h:298
I217_SxCTRL_ENABLE_LPI_RESET
#define I217_SxCTRL_ENABLE_LPI_RESET
Definition: e1000_ich8lan.h:301
I218_ULP_CONFIG1_STICKY_ULP
#define I218_ULP_CONFIG1_STICKY_ULP
Definition: e1000_ich8lan.h:202
E1000_SHRAL_PCH_LPT
#define E1000_SHRAL_PCH_LPT(_i)
Definition: e1000_ich8lan.h:77
I82579_EMI_DATA
#define I82579_EMI_DATA
Definition: e1000_ich8lan.h:274
I218_ULP_CONFIG1_START
#define I218_ULP_CONFIG1_START
Definition: e1000_ich8lan.h:200
E1000_FEXTNVM_SW_CONFIG_ICH8M
#define E1000_FEXTNVM_SW_CONFIG_ICH8M
Definition: e1000_ich8lan.h:100
E1000_LTRV_SEND
#define E1000_LTRV_SEND
Definition: e1000_ich8lan.h:319
HV_ECOL_UPPER
#define HV_ECOL_UPPER
Definition: e1000_ich8lan.h:174
HV_LATECOL_LOWER
#define HV_LATECOL_LOWER
Definition: e1000_ich8lan.h:179
E1000_PCH_RAICC
#define E1000_PCH_RAICC(_n)
Definition: e1000_ich8lan.h:308
IGP3_KMRN_DIAG
#define IGP3_KMRN_DIAG
Definition: e1000_ich8lan.h:139
IGP3_VR_CTRL_MODE_SHUTDOWN
#define IGP3_VR_CTRL_MODE_SHUTDOWN
Definition: e1000_ich8lan.h:144
I82579_LPI_CTRL
#define I82579_LPI_CTRL
Definition: e1000_ich8lan.h:263
E1000_LTRV_SCALE_SHIFT
#define E1000_LTRV_SCALE_SHIFT
Definition: e1000_ich8lan.h:315
HV_SMB_ADDR
#define HV_SMB_ADDR
Definition: e1000_ich8lan.h:213
HV_SMB_ADDR_FREQ_LOW_SHIFT
#define HV_SMB_ADDR_FREQ_LOW_SHIFT
Definition: e1000_ich8lan.h:218
IGP3_KMRN_DIAG_PCS_LOCK_LOSS
#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS
Definition: e1000_ich8lan.h:142
E1000_FWSM_ULP_CFG_DONE
#define E1000_FWSM_ULP_CFG_DONE
Definition: e1000_ich8lan.h:74
I217_EEE_ADVERTISEMENT
#define I217_EEE_ADVERTISEMENT
Definition: e1000_ich8lan.h:290
E1000_FEXTNVM4_BEACON_DURATION_8USEC
#define E1000_FEXTNVM4_BEACON_DURATION_8USEC
Definition: e1000_ich8lan.h:106
IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
Definition: e1000_ich8lan.h:143
E1000_SVCR_OFF_TIMER_SHIFT
#define E1000_SVCR_OFF_TIMER_SHIFT
Definition: e1000_ich8lan.h:328
BM_MTA
#define BM_MTA(_i)
Definition: e1000_ich8lan.h:156
E1000_PCI_LTR_CAP_LPT
#define E1000_PCI_LTR_CAP_LPT
Definition: e1000_ich8lan.h:322
E1000_SVCR_OFF_EN
#define E1000_SVCR_OFF_EN
Definition: e1000_ich8lan.h:325
I82579_EEE_PCS_STATUS
#define I82579_EEE_PCS_STATUS
Definition: e1000_ich8lan.h:281
I217_RX_CONFIG
#define I217_RX_CONFIG
Definition: e1000_ich8lan.h:292
ICH_FLASH_WRITE_COMMAND_TIMEOUT
#define ICH_FLASH_WRITE_COMMAND_TIMEOUT
Definition: e1000_ich8lan.h:47
HV_KMRN_MODE_CTRL
#define HV_KMRN_MODE_CTRL
Definition: e1000_ich8lan.h:235
E1000_LTRV_NOSNOOP_SHIFT
#define E1000_LTRV_NOSNOOP_SHIFT
Definition: e1000_ich8lan.h:318
E1000_NVM_K1_ENABLE
#define E1000_NVM_K1_ENABLE
Definition: e1000_ich8lan.h:190
E1000_ICH_NVM_SIG_VALUE
#define E1000_ICH_NVM_SIG_VALUE
Definition: e1000_ich8lan.h:92
HV_SMB_ADDR_FREQ_HIGH_SHIFT
#define HV_SMB_ADDR_FREQ_HIGH_SHIFT
Definition: e1000_ich8lan.h:219
E1000_PCI_VENDOR_ID_REGISTER
#define E1000_PCI_VENDOR_ID_REGISTER
Definition: e1000_ich8lan.h:331
HV_SCC_UPPER
#define HV_SCC_UPPER
Definition: e1000_ich8lan.h:172
E1000_LTRV_VALUE_MASK
#define E1000_LTRV_VALUE_MASK
Definition: e1000_ich8lan.h:312
HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
Definition: e1000_ich8lan.h:241
FLASH_GFPREG_BASE_MASK
#define FLASH_GFPREG_BASE_MASK
Definition: e1000_ich8lan.h:56
E1000_SVCR_OFF_MASKINT
#define E1000_SVCR_OFF_MASKINT
Definition: e1000_ich8lan.h:326
CV_SMB_CTRL
#define CV_SMB_CTRL
Definition: e1000_ich8lan.h:195
ICH_FLASH_GFPREG
#define ICH_FLASH_GFPREG
Definition: e1000_ich8lan.h:39
I82579_EMI_ADDR
#define I82579_EMI_ADDR
Definition: e1000_ich8lan.h:273
I217_MEMPWR
#define I217_MEMPWR
Definition: e1000_ich8lan.h:304
E1000_NVM_K1_CONFIG
#define E1000_NVM_K1_CONFIG
Definition: e1000_ich8lan.h:189
E1000_FWSM_WLOCK_MAC_SHIFT
#define E1000_FWSM_WLOCK_MAC_SHIFT
Definition: e1000_ich8lan.h:73
I218_ULP_CONFIG1_IND
#define I218_ULP_CONFIG1_IND
Definition: e1000_ich8lan.h:201
K1_MIN_TIME
#define K1_MIN_TIME
Definition: e1000_ich8lan.h:192
I82579_MSE_LINK_DOWN
#define I82579_MSE_LINK_DOWN
Definition: e1000_ich8lan.h:278
E1000_FLASH_BASE_ADDR
#define E1000_FLASH_BASE_ADDR
Definition: e1000_ich8lan.h:126
I217_SxCTRL
#define I217_SxCTRL
Definition: e1000_ich8lan.h:300
E1000_STRAP_SMBUS_ADDRESS_MASK
#define E1000_STRAP_SMBUS_ADDRESS_MASK
Definition: e1000_ich8lan.h:223
ICH_FLASH_ERASE_COMMAND_TIMEOUT
#define ICH_FLASH_ERASE_COMMAND_TIMEOUT
Definition: e1000_ich8lan.h:48
ICH_CYCLE_ERASE
#define ICH_CYCLE_ERASE
Definition: e1000_ich8lan.h:54
I217_PLL_CLOCK_GATE_REG
#define I217_PLL_CLOCK_GATE_REG
Definition: e1000_ich8lan.h:248
I217_PROXY_CTRL_AUTO_DISABLE
#define I217_PROXY_CTRL_AUTO_DISABLE
Definition: e1000_ich8lan.h:299
E1000_H2ME_ENFORCE_SETTINGS
#define E1000_H2ME_ENFORCE_SETTINGS
Definition: e1000_ich8lan.h:82
HV_PM_CTRL_K1_ENABLE
#define HV_PM_CTRL_K1_ENABLE
Definition: e1000_ich8lan.h:246
HV_TNCRS_LOWER
#define HV_TNCRS_LOWER
Definition: e1000_ich8lan.h:185
e1000_get_bus_info_pcie_generic
s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:240
e1000_set_fc_watermarks_generic
s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1258
e1000_id_led_init_generic
s32 e1000_id_led_init_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1775
e1000_disable_pcie_master_generic
s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:2023
e1000_clear_hw_cntrs_base_generic
void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:666
e1000_update_mc_addr_list_generic
void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count)
Definition: e1000_mac.c:595
e1000_blink_led_generic
s32 e1000_blink_led_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1889
e1000_get_speed_and_duplex_copper_generic
s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, u16 *duplex)
Definition: e1000_mac.c:1667
e1000_init_rx_addrs_generic
void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
Definition: e1000_mac.c:378
e1000_set_pcie_no_snoop_generic
void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
Definition: e1000_mac.c:1995
e1000_setup_led_generic
s32 e1000_setup_led_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1843
e1000_config_fc_after_link_up_generic
s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1359
e1000_set_lan_id_single_port
void e1000_set_lan_id_single_port(struct e1000_hw *hw)
Definition: e1000_mac.c:326
e1000_get_auto_rd_done_generic
s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
Definition: e1000_mac.c:1723
E1000_FWSM_MODE_SHIFT
#define E1000_FWSM_MODE_SHIFT
Definition: e1000_manage.h:64
E1000_FWSM_MODE_MASK
#define E1000_FWSM_MODE_MASK
Definition: e1000_manage.h:63
e1000_update_nvm_checksum_generic
s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:1235
e1000_validate_nvm_checksum_generic
s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
Definition: e1000_nvm.c:1202
DEBUGOUT1
#define DEBUGOUT1(...)
Definition: e1000_osdep.h:111
DEBUGOUT2
#define DEBUGOUT2(...)
Definition: e1000_osdep.h:112
msec_delay
#define msec_delay(x)
Definition: e1000_osdep.h:103
s64
int64_t s64
Definition: e1000_osdep.h:125
u64
uint64_t u64
Definition: e1000_osdep.h:121
usec_delay
#define usec_delay(x)
Definition: e1000_osdep.h:101
E1000_WRITE_REG_ARRAY
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value)
Definition: e1000_osdep.h:206
u8
uint8_t u8
Definition: e1000_osdep.h:124
E1000_WRITE_FLASH_REG
#define E1000_WRITE_FLASH_REG(hw, reg, value)
Definition: e1000_osdep.h:245
DEBUGFUNC
#define DEBUGFUNC(F)
Definition: e1000_osdep.h:115
E1000_READ_FLASH_REG16
#define E1000_READ_FLASH_REG16(hw, reg)
Definition: e1000_osdep.h:241
E1000_WRITE_FLUSH
#define E1000_WRITE_FLUSH(a)
Definition: e1000_osdep.h:177
E1000_WRITE_REG
#define E1000_WRITE_REG(hw, reg, value)
Definition: e1000_osdep.h:196
u16
uint16_t u16
Definition: e1000_osdep.h:123
DEBUGOUT
#define DEBUGOUT(...)
Definition: e1000_osdep.h:109
msec_delay_irq
#define msec_delay_irq(x)
Definition: e1000_osdep.h:104
E1000_READ_REG
#define E1000_READ_REG(hw, reg)
Definition: e1000_osdep.h:191
s32
int32_t s32
Definition: e1000_osdep.h:126
E1000_READ_FLASH_REG
#define E1000_READ_FLASH_REG(hw, reg)
Definition: e1000_osdep.h:237
u32
uint32_t u32
Definition: e1000_osdep.h:122
E1000_WRITE_FLASH_REG16
#define E1000_WRITE_FLASH_REG16(hw, reg, value)
Definition: e1000_osdep.h:249
ASSERT_CTX_LOCK_HELD
#define ASSERT_CTX_LOCK_HELD(hw)
Definition: e1000_osdep.h:149
e1000_phy_force_speed_duplex_igp
s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:1752
e1000_get_cable_length_m88
s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:2418
e1000_write_kmrn_reg_locked
s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:1004
e1000_read_phy_reg_igp
s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:777
e1000_phy_has_link_generic
s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success)
Definition: e1000_phy.c:2360
e1000_write_phy_reg_hv
s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:3737
e1000_phy_force_speed_duplex_ife
s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
Definition: e1000_phy.c:1957
e1000_write_phy_reg_page_hv
s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:3765
e1000_get_cable_length_igp_2
s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
Definition: e1000_phy.c:2567
e1000_write_phy_reg_mdic
s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:356
e1000_read_kmrn_reg_generic
s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:919
e1000_get_phy_id
s32 e1000_get_phy_id(struct e1000_hw *hw)
Definition: e1000_phy.c:225
e1000_power_down_phy_copper
void e1000_power_down_phy_copper(struct e1000_hw *hw)
Definition: e1000_phy.c:3522
e1000_get_phy_info_82577
s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:3964
e1000_check_polarity_ife
s32 e1000_check_polarity_ife(struct e1000_hw *hw)
Definition: e1000_phy.c:2287
e1000_enable_phy_wakeup_reg_access_bm
s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
Definition: e1000_phy.c:3333
e1000_get_phy_info_m88
s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:2637
e1000_get_phy_info_igp
s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:2712
e1000_set_page_igp
s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
Definition: e1000_phy.c:715
e1000_check_polarity_igp
s32 e1000_check_polarity_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:2244
e1000_get_phy_type_from_id
enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
Definition: e1000_phy.c:3001
e1000_read_phy_reg_hv_locked
s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:3625
e1000_phy_force_speed_duplex_82577
s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:3915
e1000_power_up_phy_copper
void e1000_power_up_phy_copper(struct e1000_hw *hw)
Definition: e1000_phy.c:3504
e1000_phy_sw_reset_generic
s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:2829
e1000_write_phy_reg_igp_locked
s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:859
e1000_get_phy_info_ife
s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
Definition: e1000_phy.c:2774
e1000_get_cfg_done_generic
s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
Definition: e1000_phy.c:2903
e1000_read_phy_reg_hv
s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:3611
e1000_phy_force_speed_duplex_m88
s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:1818
e1000_write_phy_reg_hv_locked
s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:3751
e1000_disable_phy_wakeup_reg_access_bm
s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
Definition: e1000_phy.c:3391
e1000_read_phy_reg_igp_locked
s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:791
e1000_read_kmrn_reg_locked
s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:934
e1000_check_polarity_m88
s32 e1000_check_polarity_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:2217
e1000_link_stall_workaround_hv
s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
Definition: e1000_phy.c:3843
e1000_phy_hw_reset_generic
s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:2862
e1000_copper_link_setup_82577
s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:1055
e1000_check_polarity_82577
s32 e1000_check_polarity_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:3891
e1000_read_phy_reg_bm
s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:3184
e1000_copper_link_setup_m88
s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
Definition: e1000_phy.c:1120
e1000_read_phy_reg_page_hv
s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
Definition: e1000_phy.c:3639
e1000_check_downshift_generic
s32 e1000_check_downshift_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:2172
e1000_write_kmrn_reg_generic
s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:990
e1000_get_cable_length_82577
s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
Definition: e1000_phy.c:4027
e1000_copper_link_setup_igp
s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
Definition: e1000_phy.c:1371
e1000_write_phy_reg_igp
s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:845
e1000_write_phy_reg_bm
s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
Definition: e1000_phy.c:3124
e1000_determine_phy_address
s32 e1000_determine_phy_address(struct e1000_hw *hw)
Definition: e1000_phy.c:3068
e1000_phy_init_script_igp3
s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
Definition: e1000_phy.c:2918
e1000_setup_copper_link_generic
s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
Definition: e1000_phy.c:1699
HV_M_STATUS_SPEED_MASK
#define HV_M_STATUS_SPEED_MASK
Definition: e1000_phy.h:232
HV_M_STATUS_AUTONEG_COMPLETE
#define HV_M_STATUS_AUTONEG_COMPLETE
Definition: e1000_phy.h:231
BM_CS_STATUS_LINK_UP
#define BM_CS_STATUS_LINK_UP
Definition: e1000_phy.h:224
IGP01E1000_PHY_PAGE_SELECT
#define IGP01E1000_PHY_PAGE_SELECT
Definition: e1000_phy.h:139
E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK
#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK
Definition: e1000_phy.h:289
HV_M_STATUS_SPEED_100
#define HV_M_STATUS_SPEED_100
Definition: e1000_phy.h:234
IGP_PAGE_SHIFT
#define IGP_PAGE_SHIFT
Definition: e1000_phy.h:141
BM_CS_STATUS_SPEED_1000
#define BM_CS_STATUS_SPEED_1000
Definition: e1000_phy.h:227
IFE_PHY_SPECIAL_CONTROL_LED
#define IFE_PHY_SPECIAL_CONTROL_LED
Definition: e1000_phy.h:294
HV_M_STATUS_LINK_UP
#define HV_M_STATUS_LINK_UP
Definition: e1000_phy.h:235
IGP01E1000_PHY_PORT_CONFIG
#define IGP01E1000_PHY_PORT_CONFIG
Definition: e1000_phy.h:133
BM_CS_STATUS_SPEED_MASK
#define BM_CS_STATUS_SPEED_MASK
Definition: e1000_phy.h:226
IFE_PSCL_PROBE_LEDS_ON
#define IFE_PSCL_PROBE_LEDS_ON
Definition: e1000_phy.h:307
E1000_KMRNCTRLSTA_DIAG_NELPBK
#define E1000_KMRNCTRLSTA_DIAG_NELPBK
Definition: e1000_phy.h:280
E1000_KMRNCTRLSTA_DIAG_OFFSET
#define E1000_KMRNCTRLSTA_DIAG_OFFSET
Definition: e1000_phy.h:276
PHY_REG_MASK
#define PHY_REG_MASK
Definition: e1000_phy.h:142
E1000_KMRNCTRLSTA_TIMEOUTS
#define E1000_KMRNCTRLSTA_TIMEOUTS
Definition: e1000_phy.h:277
HV_M_STATUS_SPEED_1000
#define HV_M_STATUS_SPEED_1000
Definition: e1000_phy.h:233
HV_M_STATUS
#define HV_M_STATUS
Definition: e1000_phy.h:230
E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT
#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT
Definition: e1000_phy.h:286
E1000_KMRNCTRLSTA_K1_CONFIG
#define E1000_KMRNCTRLSTA_K1_CONFIG
Definition: e1000_phy.h:281
IFE_PMC_FORCE_MDIX
#define IFE_PMC_FORCE_MDIX
Definition: e1000_phy.h:311
BM_CS_STATUS_RESOLVED
#define BM_CS_STATUS_RESOLVED
Definition: e1000_phy.h:225
E1000_KMRNCTRLSTA_INBAND_PARAM
#define E1000_KMRNCTRLSTA_INBAND_PARAM
Definition: e1000_phy.h:278
IFE_PSCL_PROBE_MODE
#define IFE_PSCL_PROBE_MODE
Definition: e1000_phy.h:305
BM_CS_STATUS
#define BM_CS_STATUS
Definition: e1000_phy.h:223
E1000_KMRNCTRLSTA_K1_ENABLE
#define E1000_KMRNCTRLSTA_K1_ENABLE
Definition: e1000_phy.h:282
E1000_KMRNCTRLSTA_HD_CTRL
#define E1000_KMRNCTRLSTA_HD_CTRL
Definition: e1000_phy.h:283
E1000_KMRNCTRLSTA_K0S_CTRL
#define E1000_KMRNCTRLSTA_K0S_CTRL
Definition: e1000_phy.h:284
IFE_PSCL_PROBE_LEDS_OFF
#define IFE_PSCL_PROBE_LEDS_OFF
Definition: e1000_phy.h:306
IFE_PMC_AUTO_MDIX
#define IFE_PMC_AUTO_MDIX
Definition: e1000_phy.h:312
IFE_PHY_MDIX_CONTROL
#define IFE_PHY_MDIX_CONTROL
Definition: e1000_phy.h:295
E1000_KMRNCTRLSTA_CTRL_OFFSET
#define E1000_KMRNCTRLSTA_CTRL_OFFSET
Definition: e1000_phy.h:275
BM_PORT_CTRL_PAGE
#define BM_PORT_CTRL_PAGE
Definition: e1000_phy.h:155
IGP01E1000_PSCFR_SMART_SPEED
#define IGP01E1000_PSCFR_SMART_SPEED
Definition: e1000_phy.h:243
E1000_RXERRC
#define E1000_RXERRC
Definition: e1000_regs.h:329
E1000_KABGTXD
#define E1000_KABGTXD
Definition: e1000_regs.h:288
E1000_FEXT
#define E1000_FEXT
Definition: e1000_regs.h:63
E1000_FCTTV
#define E1000_FCTTV
Definition: e1000_regs.h:90
E1000_SHRAL
#define E1000_SHRAL(_i)
Definition: e1000_regs.h:294
E1000_SHRAH
#define E1000_SHRAH(_i)
Definition: e1000_regs.h:295
E1000_PHY_CTRL
#define E1000_PHY_CTRL
Definition: e1000_regs.h:113
E1000_FEXTNVM6
#define E1000_FEXTNVM6
Definition: e1000_regs.h:68
E1000_PCIEANACFG
#define E1000_PCIEANACFG
Definition: e1000_regs.h:74
E1000_FEXTNVM
#define E1000_FEXTNVM
Definition: e1000_regs.h:64
E1000_RAH
#define E1000_RAH(_i)
Definition: e1000_regs.h:292
E1000_TNCRS
#define E1000_TNCRS
Definition: e1000_regs.h:337
E1000_FEXTNVM4
#define E1000_FEXTNVM4
Definition: e1000_regs.h:66
E1000_RCTL
#define E1000_RCTL
Definition: e1000_regs.h:89
E1000_FEXTNVM7
#define E1000_FEXTNVM7
Definition: e1000_regs.h:69
E1000_WUFC
#define E1000_WUFC
Definition: e1000_regs.h:506
E1000_TCTL
#define E1000_TCTL
Definition: e1000_regs.h:104
E1000_ICRXOC
#define E1000_ICRXOC
Definition: e1000_regs.h:393
E1000_STATUS
#define E1000_STATUS
Definition: e1000_regs.h:41
E1000_FWSM
#define E1000_FWSM
Definition: e1000_regs.h:545
E1000_ALGNERRC
#define E1000_ALGNERRC
Definition: e1000_regs.h:327
E1000_TXDCTL
#define E1000_TXDCTL(_n)
Definition: e1000_regs.h:278
E1000_MGTPRC
#define E1000_MGTPRC
Definition: e1000_regs.h:365
E1000_PBS
#define E1000_PBS
Definition: e1000_regs.h:116
E1000_MGTPTC
#define E1000_MGTPTC
Definition: e1000_regs.h:367
E1000_CTRL
#define E1000_CTRL
Definition: e1000_regs.h:39
E1000_PBECCSTS
#define E1000_PBECCSTS
Definition: e1000_regs.h:117
E1000_TIPG
#define E1000_TIPG
Definition: e1000_regs.h:106
E1000_IMC
#define E1000_IMC
Definition: e1000_regs.h:83
E1000_SVCR
#define E1000_SVCR
Definition: e1000_regs.h:86
E1000_EXTCNF_CTRL
#define E1000_EXTCNF_CTRL
Definition: e1000_regs.h:111
E1000_TARC
#define E1000_TARC(_n)
Definition: e1000_regs.h:284
E1000_LEDCTL
#define E1000_LEDCTL
Definition: e1000_regs.h:109
E1000_TSCTFC
#define E1000_TSCTFC
Definition: e1000_regs.h:383
E1000_CEXTERR
#define E1000_CEXTERR
Definition: e1000_regs.h:339
E1000_MTA
#define E1000_MTA
Definition: e1000_regs.h:496
E1000_ICR
#define E1000_ICR
Definition: e1000_regs.h:79
E1000_FEXTNVM3
#define E1000_FEXTNVM3
Definition: e1000_regs.h:65
E1000_CRC_OFFSET
#define E1000_CRC_OFFSET
Definition: e1000_regs.h:394
E1000_EXTCNF_SIZE
#define E1000_EXTCNF_SIZE
Definition: e1000_regs.h:112
E1000_EECD
#define E1000_EECD
Definition: e1000_regs.h:42
E1000_IAC
#define E1000_IAC
Definition: e1000_regs.h:384
E1000_PBA
#define E1000_PBA
Definition: e1000_regs.h:115
E1000_MGTPDC
#define E1000_MGTPDC
Definition: e1000_regs.h:366
E1000_RAL
#define E1000_RAL(_i)
Definition: e1000_regs.h:290
E1000_TSCTC
#define E1000_TSCTC
Definition: e1000_regs.h:382
E1000_SVT
#define E1000_SVT
Definition: e1000_regs.h:87
E1000_CTRL_EXT
#define E1000_CTRL_EXT
Definition: e1000_regs.h:44
E1000_RFCTL
#define E1000_RFCTL
Definition: e1000_regs.h:495
E1000_FFLT_DBG
#define E1000_FFLT_DBG
Definition: e1000_regs.h:551
e1000_bus_info
Definition: e1000_hw.h:903
e1000_bus_info::width
enum e1000_bus_width width
Definition: e1000_hw.h:906
e1000_dev_spec_ich8lan
Definition: e1000_hw.h:991
e1000_dev_spec_ich8lan::eee_disable
bool eee_disable
Definition: e1000_hw.h:996
e1000_dev_spec_ich8lan::ulp_state
enum e1000_ulp_state ulp_state
Definition: e1000_hw.h:998
e1000_dev_spec_ich8lan::eee_lp_ability
u16 eee_lp_ability
Definition: e1000_hw.h:997
e1000_dev_spec_ich8lan::kmrn_lock_loss_workaround_enabled
bool kmrn_lock_loss_workaround_enabled
Definition: e1000_hw.h:992
e1000_dev_spec_ich8lan::disable_k1_off
bool disable_k1_off
Definition: e1000_hw.h:995
e1000_dev_spec_ich8lan::shadow_ram
struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]
Definition: e1000_hw.h:993
e1000_dev_spec_ich8lan::nvm_k1_enabled
bool nvm_k1_enabled
Definition: e1000_hw.h:994
e1000_fc_info::current_mode
enum e1000_fc_mode current_mode
Definition: e1000_hw.h:919
e1000_fc_info::pause_time
u16 pause_time
Definition: e1000_hw.h:915
e1000_fc_info::refresh_time
u16 refresh_time
Definition: e1000_hw.h:916
e1000_fc_info::requested_mode
enum e1000_fc_mode requested_mode
Definition: e1000_hw.h:920
e1000_hw
Definition: e1000_hw.h:1021
e1000_hw::dev_spec
union e1000_hw::@46 dev_spec
e1000_hw::bus
struct e1000_bus_info bus
Definition: e1000_hw.h:1032
e1000_hw::mac
struct e1000_mac_info mac
Definition: e1000_hw.h:1028
e1000_hw::flash_address
u8 * flash_address
Definition: e1000_hw.h:1025
e1000_hw::nvm
struct e1000_nvm_info nvm
Definition: e1000_hw.h:1031
e1000_hw::hw_addr
u8 * hw_addr
Definition: e1000_hw.h:1024
e1000_hw::ich8lan
struct e1000_dev_spec_ich8lan ich8lan
Definition: e1000_hw.h:1042
e1000_hw::fc
struct e1000_fc_info fc
Definition: e1000_hw.h:1029
e1000_hw::device_id
u16 device_id
Definition: e1000_hw.h:1047
e1000_hw::phy
struct e1000_phy_info phy
Definition: e1000_hw.h:1030
e1000_mac_info
Definition: e1000_hw.h:810
e1000_mac_info::has_fwsm
bool has_fwsm
Definition: e1000_hw.h:841
e1000_mac_info::autoneg
bool autoneg
Definition: e1000_hw.h:844
e1000_mac_info::type
enum e1000_mac_type type
Definition: e1000_hw.h:815
e1000_mac_info::addr
u8 addr[ETHER_ADDR_LEN]
Definition: e1000_hw.h:812
e1000_mac_info::ledctl_default
u32 ledctl_default
Definition: e1000_hw.h:818
e1000_mac_info::adaptive_ifs
bool adaptive_ifs
Definition: e1000_hw.h:840
e1000_mac_info::arc_subsystem_valid
bool arc_subsystem_valid
Definition: e1000_hw.h:842
e1000_mac_info::get_link_status
bool get_link_status
Definition: e1000_hw.h:846
e1000_mac_info::ledctl_mode1
u32 ledctl_mode1
Definition: e1000_hw.h:819
e1000_mac_info::asf_firmware_present
bool asf_firmware_present
Definition: e1000_hw.h:843
e1000_mac_info::mta_reg_count
u16 mta_reg_count
Definition: e1000_hw.h:830
e1000_mac_info::ledctl_mode2
u32 ledctl_mode2
Definition: e1000_hw.h:820
e1000_mac_info::max_frame_size
u32 max_frame_size
Definition: e1000_hw.h:852
e1000_mac_info::rar_entry_count
u16 rar_entry_count
Definition: e1000_hw.h:836
e1000_mac_info::ops
struct e1000_mac_operations ops
Definition: e1000_hw.h:811
e1000_mac_info::mta_shadow
u32 mta_shadow[MAX_MTA_REG]
Definition: e1000_hw.h:835
e1000_mac_operations::setup_led
s32(* setup_led)(struct e1000_hw *)
Definition: e1000_hw.h:744
e1000_mac_operations::id_led_init
s32(* id_led_init)(struct e1000_hw *)
Definition: e1000_hw.h:725
e1000_mac_operations::get_link_up_info
s32(* get_link_up_info)(struct e1000_hw *, u16 *, u16 *)
Definition: e1000_hw.h:734
e1000_mac_operations::setup_physical_interface
s32(* setup_physical_interface)(struct e1000_hw *)
Definition: e1000_hw.h:743
e1000_mac_operations::check_for_link
s32(* check_for_link)(struct e1000_hw *)
Definition: e1000_hw.h:728
e1000_mac_operations::config_collision_dist
void(* config_collision_dist)(struct e1000_hw *)
Definition: e1000_hw.h:746
e1000_mac_operations::blink_led
s32(* blink_led)(struct e1000_hw *)
Definition: e1000_hw.h:726
e1000_mac_operations::reset_hw
s32(* reset_hw)(struct e1000_hw *)
Definition: e1000_hw.h:738
e1000_mac_operations::set_obff_timer
s32(* set_obff_timer)(struct e1000_hw *, u32)
Definition: e1000_hw.h:750
e1000_mac_operations::led_on
s32(* led_on)(struct e1000_hw *)
Definition: e1000_hw.h:735
e1000_mac_operations::rar_set
int(* rar_set)(struct e1000_hw *, u8 *, u32)
Definition: e1000_hw.h:747
e1000_mac_operations::init_hw
s32(* init_hw)(struct e1000_hw *)
Definition: e1000_hw.h:739
e1000_mac_operations::setup_link
s32(* setup_link)(struct e1000_hw *)
Definition: e1000_hw.h:742
e1000_mac_operations::cleanup_led
s32(* cleanup_led)(struct e1000_hw *)
Definition: e1000_hw.h:729
e1000_mac_operations::clear_hw_cntrs
void(* clear_hw_cntrs)(struct e1000_hw *)
Definition: e1000_hw.h:730
e1000_mac_operations::set_lan_id
void(* set_lan_id)(struct e1000_hw *)
Definition: e1000_hw.h:733
e1000_mac_operations::update_mc_addr_list
void(* update_mc_addr_list)(struct e1000_hw *, u8 *, u32)
Definition: e1000_hw.h:737
e1000_mac_operations::led_off
s32(* led_off)(struct e1000_hw *)
Definition: e1000_hw.h:736
e1000_mac_operations::check_mng_mode
bool(* check_mng_mode)(struct e1000_hw *)
Definition: e1000_hw.h:727
e1000_mac_operations::get_bus_info
s32(* get_bus_info)(struct e1000_hw *)
Definition: e1000_hw.h:732
e1000_mac_operations::init_params
s32(* init_params)(struct e1000_hw *)
Definition: e1000_hw.h:724
e1000_nvm_info
Definition: e1000_hw.h:888
e1000_nvm_info::ops
struct e1000_nvm_operations ops
Definition: e1000_hw.h:889
e1000_nvm_info::type
enum e1000_nvm_type type
Definition: e1000_hw.h:890
e1000_nvm_info::flash_base_addr
u32 flash_base_addr
Definition: e1000_hw.h:894
e1000_nvm_info::flash_bank_size
u32 flash_bank_size
Definition: e1000_hw.h:893
e1000_nvm_info::word_size
u16 word_size
Definition: e1000_hw.h:896
e1000_nvm_operations::release
void(* release)(struct e1000_hw *)
Definition: e1000_hw.h:802
e1000_nvm_operations::init_params
s32(* init_params)(struct e1000_hw *)
Definition: e1000_hw.h:799
e1000_nvm_operations::write
s32(* write)(struct e1000_hw *, u16, u16, u16 *)
Definition: e1000_hw.h:807
e1000_nvm_operations::reload
void(* reload)(struct e1000_hw *)
Definition: e1000_hw.h:803
e1000_nvm_operations::validate
s32(* validate)(struct e1000_hw *)
Definition: e1000_hw.h:806
e1000_nvm_operations::update
s32(* update)(struct e1000_hw *)
Definition: e1000_hw.h:804
e1000_nvm_operations::read
s32(* read)(struct e1000_hw *, u16, u16, u16 *)
Definition: e1000_hw.h:801
e1000_nvm_operations::acquire
s32(* acquire)(struct e1000_hw *)
Definition: e1000_hw.h:800
e1000_nvm_operations::valid_led_default
s32(* valid_led_default)(struct e1000_hw *, u16 *)
Definition: e1000_hw.h:805
e1000_phy_info
Definition: e1000_hw.h:855
e1000_phy_info::id
u32 id
Definition: e1000_hw.h:867
e1000_phy_info::reset_delay_us
u32 reset_delay_us
Definition: e1000_hw.h:868
e1000_phy_info::media_type
enum e1000_media_type media_type
Definition: e1000_hw.h:871
e1000_phy_info::revision
u32 revision
Definition: e1000_hw.h:869
e1000_phy_info::autoneg_advertised
u16 autoneg_advertised
Definition: e1000_hw.h:873
e1000_phy_info::ops
struct e1000_phy_operations ops
Definition: e1000_hw.h:856
e1000_phy_info::type
enum e1000_phy_type type
Definition: e1000_hw.h:857
e1000_phy_info::autoneg_mask
u16 autoneg_mask
Definition: e1000_hw.h:874
e1000_phy_info::smart_speed
enum e1000_smart_speed smart_speed
Definition: e1000_hw.h:864
e1000_phy_info::mdix
u8 mdix
Definition: e1000_hw.h:879
e1000_phy_info::addr
u32 addr
Definition: e1000_hw.h:866
e1000_phy_operations::set_page
s32(* set_page)(struct e1000_hw *, u16)
Definition: e1000_hw.h:780
e1000_phy_operations::read_reg_locked
s32(* read_reg_locked)(struct e1000_hw *, u32, u16 *)
Definition: e1000_hw.h:782
e1000_phy_operations::get_cfg_done
s32(* get_cfg_done)(struct e1000_hw *hw)
Definition: e1000_hw.h:777
e1000_phy_operations::power_up
void(* power_up)(struct e1000_hw *)
Definition: e1000_hw.h:791
e1000_phy_operations::reset
s32(* reset)(struct e1000_hw *)
Definition: e1000_hw.h:785
e1000_phy_operations::init_params
s32(* init_params)(struct e1000_hw *)
Definition: e1000_hw.h:770
e1000_phy_operations::read_reg
s32(* read_reg)(struct e1000_hw *, u32, u16 *)
Definition: e1000_hw.h:781
e1000_phy_operations::get_info
s32(* get_info)(struct e1000_hw *)
Definition: e1000_hw.h:779
e1000_phy_operations::release
void(* release)(struct e1000_hw *)
Definition: e1000_hw.h:784
e1000_phy_operations::set_d3_lplu_state
s32(* set_d3_lplu_state)(struct e1000_hw *, bool)
Definition: e1000_hw.h:787
e1000_phy_operations::force_speed_duplex
s32(* force_speed_duplex)(struct e1000_hw *)
Definition: e1000_hw.h:776
e1000_phy_operations::get_cable_length
s32(* get_cable_length)(struct e1000_hw *)
Definition: e1000_hw.h:778
e1000_phy_operations::check_reset_block
s32(* check_reset_block)(struct e1000_hw *)
Definition: e1000_hw.h:774
e1000_phy_operations::acquire
s32(* acquire)(struct e1000_hw *)
Definition: e1000_hw.h:771
e1000_phy_operations::write_reg_locked
s32(* write_reg_locked)(struct e1000_hw *, u32, u16)
Definition: e1000_hw.h:789
e1000_phy_operations::set_d0_lplu_state
s32(* set_d0_lplu_state)(struct e1000_hw *, bool)
Definition: e1000_hw.h:786
e1000_phy_operations::write_reg
s32(* write_reg)(struct e1000_hw *, u32, u16)
Definition: e1000_hw.h:788
e1000_phy_operations::commit
s32(* commit)(struct e1000_hw *)
Definition: e1000_hw.h:775
e1000_phy_operations::power_down
void(* power_down)(struct e1000_hw *)
Definition: e1000_hw.h:792
e1000_phy_operations::check_polarity
s32(* check_polarity)(struct e1000_hw *)
Definition: e1000_hw.h:773
e1000_phy_operations::write_reg_page
s32(* write_reg_page)(struct e1000_hw *, u32, u16)
Definition: e1000_hw.h:790
e1000_phy_operations::read_reg_page
s32(* read_reg_page)(struct e1000_hw *, u32, u16 *)
Definition: e1000_hw.h:783
e1000_shadow_ram::value
u16 value
Definition: e1000_hw.h:978
e1000_shadow_ram::modified
bool modified
Definition: e1000_hw.h:979
ich8_hws_flash_ctrl::ich8_hsflctl
Definition: e1000_ich8lan.c:170
ich8_hws_flash_ctrl::ich8_hsflctl::flcycle
u16 flcycle
Definition: e1000_ich8lan.c:172
ich8_hws_flash_ctrl::ich8_hsflctl::fldbcount
u16 fldbcount
Definition: e1000_ich8lan.c:174
ich8_hws_flash_ctrl::ich8_hsflctl::flcgo
u16 flcgo
Definition: e1000_ich8lan.c:171
ich8_hws_flash_ctrl::ich8_hsflctl::reserved
u16 reserved
Definition: e1000_ich8lan.c:173
ich8_hws_flash_ctrl::ich8_hsflctl::flockdn
u16 flockdn
Definition: e1000_ich8lan.c:175
ich8_hws_flash_regacc::ich8_flracc
Definition: e1000_ich8lan.c:182
ich8_hws_flash_regacc::ich8_flracc::grra
u32 grra
Definition: e1000_ich8lan.c:183
ich8_hws_flash_regacc::ich8_flracc::gmwag
u32 gmwag
Definition: e1000_ich8lan.c:186
ich8_hws_flash_regacc::ich8_flracc::grwa
u32 grwa
Definition: e1000_ich8lan.c:184
ich8_hws_flash_regacc::ich8_flracc::gmrag
u32 gmrag
Definition: e1000_ich8lan.c:185
ich8_hws_flash_status::ich8_hsfsts
Definition: e1000_ich8lan.c:153
ich8_hws_flash_status::ich8_hsfsts::flockdn
u16 flockdn
Definition: e1000_ich8lan.c:162
ich8_hws_flash_status::ich8_hsfsts::flcinprog
u16 flcinprog
Definition: e1000_ich8lan.c:158
ich8_hws_flash_status::ich8_hsfsts::fldesvalid
u16 fldesvalid
Definition: e1000_ich8lan.c:161
ich8_hws_flash_status::ich8_hsfsts::flcerr
u16 flcerr
Definition: e1000_ich8lan.c:155
ich8_hws_flash_status::ich8_hsfsts::flcdone
u16 flcdone
Definition: e1000_ich8lan.c:154
ich8_hws_flash_status::ich8_hsfsts::reserved2
u16 reserved2
Definition: e1000_ich8lan.c:160
ich8_hws_flash_status::ich8_hsfsts::berasesz
u16 berasesz
Definition: e1000_ich8lan.c:157
ich8_hws_flash_status::ich8_hsfsts::dael
u16 dael
Definition: e1000_ich8lan.c:156
ich8_hws_flash_status::ich8_hsfsts::reserved1
u16 reserved1
Definition: e1000_ich8lan.c:159
ich8_hws_flash_ctrl
Definition: e1000_ich8lan.c:169
ich8_hws_flash_ctrl::hsf_ctrl
struct ich8_hws_flash_ctrl::ich8_hsflctl hsf_ctrl
ich8_hws_flash_ctrl::regval
u16 regval
Definition: e1000_ich8lan.c:177
ich8_hws_flash_regacc
Definition: e1000_ich8lan.c:181
ich8_hws_flash_regacc::hsf_flregacc
struct ich8_hws_flash_regacc::ich8_flracc hsf_flregacc
ich8_hws_flash_regacc::regval
u16 regval
Definition: e1000_ich8lan.c:188
ich8_hws_flash_status
Definition: e1000_ich8lan.c:152
ich8_hws_flash_status::regval
u16 regval
Definition: e1000_ich8lan.c:164
ich8_hws_flash_status::hsf_status
struct ich8_hws_flash_status::ich8_hsfsts hsf_status