32#define BXE_DRIVER_VERSION "1.78.91"
48#define CTLTYPE_U64 CTLTYPE_QUAD
49#define sysctl_handle_64 sysctl_handle_quad
58#define CSUM_TCP_IPV6 0
59#define CSUM_UDP_IPV6 0
62#define BXE_DEF_SB_ATT_IDX 0x0001
63#define BXE_DEF_SB_IDX 0x0002
69#define FLR_WAIT_USEC 10000
70#define FLR_WAIT_INTERVAL 50
71#define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)
89#define BXE_DEVDESC_MAX 64
95 "QLogic NetXtreme II BCM57710 10GbE"
101 "QLogic NetXtreme II BCM57711 10GbE"
107 "QLogic NetXtreme II BCM57711E 10GbE"
113 "QLogic NetXtreme II BCM57712 10GbE"
119 "QLogic NetXtreme II BCM57712 MF 10GbE"
125 "QLogic NetXtreme II BCM57800 10GbE"
131 "QLogic NetXtreme II BCM57800 MF 10GbE"
137 "QLogic NetXtreme II BCM57810 10GbE"
143 "QLogic NetXtreme II BCM57810 MF 10GbE"
149 "QLogic NetXtreme II BCM57811 10GbE"
155 "QLogic NetXtreme II BCM57811 MF 10GbE"
161 "QLogic NetXtreme II BCM57840 4x10GbE"
167 "QLogic NetXtreme II BCM57840 4x10GbE"
173 "QLogic NetXtreme II BCM57840 2x20GbE"
179 "QLogic NetXtreme II BCM57840 MF 10GbE"
208 DEVMETHOD(bus_print_child, bus_generic_print_child),
209 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
236#define BXE_PREV_WAIT_NEEDED 1
249static int load_count[2][3] = { {0} };
254 "bxe driver parameters");
293SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN,
299 &
bxe_mrrs, 0,
"PCIe maximum read request size");
312#define STAT_NAME_LEN 32
314#define STATS_OFFSET32(stat_name) \
315 (offsetof(struct bxe_eth_stats, stat_name) / 4)
317#define Q_STATS_OFFSET32(stat_name) \
318 (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
324#define STATS_FLAGS_PORT 1
325#define STATS_FLAGS_FUNC 2
326#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
527 8,
"rx_ucast_packets" },
529 8,
"rx_mcast_packets" },
531 8,
"rx_bcast_packets" },
537 8,
"tx_ucast_packets" },
539 8,
"tx_mcast_packets" },
541 8,
"tx_bcast_packets" },
543 8,
"tpa_aggregations" },
545 8,
"tpa_aggregated_frames"},
555 4,
"rx_erroneous_jumbo_sge_pkts"},
557 4,
"rx_bxe_service_rxsgl"},
559 4,
"rx_jumbo_sge_pkts"},
561 4,
"rx_soft_errors"},
563 4,
"rx_hw_csum_errors"},
565 4,
"rx_ofld_frames_csum_ip"},
567 4,
"rx_ofld_frames_csum_tcp_udp"},
569 4,
"rx_budget_reached"},
573 4,
"tx_soft_errors"},
575 4,
"tx_ofld_frames_csum_ip"},
577 4,
"tx_ofld_frames_csum_tcp"},
579 4,
"tx_ofld_frames_csum_udp"},
581 4,
"tx_ofld_frames_lso"},
583 4,
"tx_ofld_frames_lso_hdr_splits"},
585 4,
"tx_encap_failures"},
587 4,
"tx_hw_queue_full"},
589 4,
"tx_hw_max_queue_depth"},
591 4,
"tx_dma_mapping_failure"},
593 4,
"tx_max_drbr_queue_depth"},
595 4,
"tx_window_violation_std"},
597 4,
"tx_window_violation_tso"},
599 4,
"tx_chain_lost_mbuf"},
601 4,
"tx_frames_deferred"},
605 4,
"mbuf_defrag_attempts"},
607 4,
"mbuf_defrag_failures"},
609 4,
"mbuf_rx_bd_alloc_failed"},
611 4,
"mbuf_rx_bd_mapping_failed"},
613 4,
"mbuf_rx_tpa_alloc_failed"},
615 4,
"mbuf_rx_tpa_mapping_failed"},
617 4,
"mbuf_rx_sge_alloc_failed"},
619 4,
"mbuf_rx_sge_mapping_failed"},
625 4,
"mbuf_alloc_sge"},
627 4,
"mbuf_alloc_tpa"},
629 4,
"tx_queue_full_return"},
631 4,
"bxe_tx_mq_sc_state_failures"},
633 4,
"tx_request_link_down_failures"},
635 4,
"bd_avail_too_less_failures"},
637 4,
"tx_mq_not_empty"},
639 4,
"nsegs_path1_errors"},
641 4,
"nsegs_path2_errors"}
646#define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr)
647#define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
673 uint16_t rx_sge_prod);
708 uint32_t unload_mode,
723 uint32_t crc32_length,
732 uint8_t current_byte = 0;
733 uint32_t crc32_result = crc32_seed;
734 const uint32_t CRC32_POLY = 0x1edc6f41;
736 if ((crc32_packet == NULL) ||
737 (crc32_length == 0) ||
738 ((crc32_length % 8) != 0))
740 return (crc32_result);
743 for (
byte = 0;
byte < crc32_length;
byte =
byte + 1)
745 current_byte = crc32_packet[byte];
746 for (bit = 0; bit < 8; bit = bit + 1)
749 msb = (uint8_t)(crc32_result >> 31);
751 crc32_result = crc32_result << 1;
754 if (msb != (0x1 & (current_byte >> bit)))
756 crc32_result = crc32_result ^ CRC32_POLY;
771 shft =
sizeof(crc32_result) * 8 - 1;
773 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
776 temp |= crc32_result & 1;
786 uint32_t t0, t1, t2, t3;
787 t0 = (0x000000ff & (temp >> 24));
788 t1 = (0x0000ff00 & (temp >> 8));
789 t2 = (0x00ff0000 & (temp << 8));
790 t3 = (0xff000000 & (temp << 24));
791 crc32_result = t0 | t1 | t2 | t3;
797 crc32_result = ~crc32_result;
800 return (crc32_result);
805 volatile unsigned long *
addr)
807 return ((atomic_load_acq_long(
addr) & (1 << nr)) != 0);
812 volatile unsigned long *
addr)
814 atomic_set_acq_long(
addr, (1 << nr));
819 volatile unsigned long *
addr)
821 atomic_clear_acq_long(
addr, (1 << nr));
826 volatile unsigned long *
addr)
832 }
while (atomic_cmpset_acq_long(
addr, x, x | nr) == 0);
839 volatile unsigned long *
addr)
845 }
while (atomic_cmpset_acq_long(
addr, x, x & ~nr) == 0);
858 }
while (atomic_cmpset_acq_int(
addr, old,
new) == 0);
882 BLOGE(dma->
sc,
"Failed DMA alloc '%s' (%d)!\n", dma->
msg, error);
884 dma->
paddr = segs->ds_addr;
906 BLOGE(
sc,
"dma block '%s' already has size %lu\n",
msg,
907 (
unsigned long)dma->
size);
911 memset(dma, 0,
sizeof(*dma));
914 snprintf(dma->
msg,
sizeof(dma->
msg),
"%s",
msg);
931 BLOGE(
sc,
"Failed to create dma tag for '%s' (%d)\n",
msg, rc);
932 memset(dma, 0,
sizeof(*dma));
936 rc = bus_dmamem_alloc(dma->
tag,
937 (
void **)&dma->
vaddr,
938 (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
941 BLOGE(
sc,
"Failed to alloc dma mem for '%s' (%d)\n",
msg, rc);
942 bus_dma_tag_destroy(dma->
tag);
943 memset(dma, 0,
sizeof(*dma));
947 rc = bus_dmamap_load(dma->
tag,
955 BLOGE(
sc,
"Failed to load dma map for '%s' (%d)\n",
msg, rc);
957 bus_dma_tag_destroy(dma->
tag);
958 memset(dma, 0,
sizeof(*dma));
972 bus_dmamap_sync(dma->
tag, dma->
map,
973 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
974 bus_dmamap_unload(dma->
tag, dma->
map);
976 bus_dma_tag_destroy(dma->
tag);
979 memset(dma, 0,
sizeof(*dma));
1014 uint32_t lock_status;
1015 uint32_t resource_bit = (1 << resource);
1017 uint32_t hw_lock_control_reg;
1022 BLOGE(
sc,
"(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1023 " resource_bit 0x%x\n", resource, resource_bit);
1030 hw_lock_control_reg =
1035 lock_status =
REG_RD(
sc, hw_lock_control_reg);
1036 if (lock_status & resource_bit) {
1037 BLOGE(
sc,
"resource (0x%x) in use (status 0x%x bit 0x%x)\n",
1038 resource, lock_status, resource_bit);
1043 for (cnt = 0; cnt < 1000; cnt++) {
1044 REG_WR(
sc, (hw_lock_control_reg + 4), resource_bit);
1045 lock_status =
REG_RD(
sc, hw_lock_control_reg);
1046 if (lock_status & resource_bit) {
1052 BLOGE(
sc,
"Resource 0x%x resource_bit 0x%x lock timeout!\n",
1053 resource, resource_bit);
1061 uint32_t lock_status;
1062 uint32_t resource_bit = (1 << resource);
1064 uint32_t hw_lock_control_reg;
1068 BLOGE(
sc,
"(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1069 " resource_bit 0x%x\n", resource, resource_bit);
1076 hw_lock_control_reg =
1081 lock_status =
REG_RD(
sc, hw_lock_control_reg);
1082 if (!(lock_status & resource_bit)) {
1083 BLOGE(
sc,
"resource (0x%x) not in use (status 0x%x bit 0x%x)\n",
1084 resource, lock_status, resource_bit);
1088 REG_WR(
sc, hw_lock_control_reg, resource_bit);
1136 for (i = 0; i < count*10; i++) {
1146 BLOGE(
sc,
"Cannot get access to nvram interface "
1147 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1172 for (i = 0; i < count*10; i++) {
1182 BLOGE(
sc,
"Cannot free access to nvram interface "
1183 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1250 for (i = 0; i < count; i++) {
1260 *ret_val = htobe32(val);
1267 BLOGE(
sc,
"nvram read timeout expired "
1268 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1285 if ((
offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1286 BLOGE(
sc,
"Invalid parameter, offset 0x%x buf_size 0x%x\n",
1292 BLOGE(
sc,
"Invalid parameter, "
1293 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1309 while ((buf_size >
sizeof(uint32_t)) && (rc == 0)) {
1311 memcpy(ret_buf, &val, 4);
1314 offset +=
sizeof(uint32_t);
1315 ret_buf +=
sizeof(uint32_t);
1316 buf_size -=
sizeof(uint32_t);
1323 memcpy(ret_buf, &val, 4);
1365 for (i = 0; i < count; i++) {
1375 BLOGE(
sc,
"nvram write timeout expired "
1376 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1383#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1392 uint32_t align_offset;
1397 BLOGE(
sc,
"Invalid parameter, "
1398 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1413 align_offset = (
offset & ~0x03);
1443 uint32_t written_so_far;
1446 if (buf_size == 1) {
1450 if ((
offset & 0x03) || (buf_size & 0x03) ) {
1451 BLOGE(
sc,
"Invalid parameter, offset 0x%x buf_size 0x%x\n",
1456 if (buf_size == 0) {
1461 BLOGE(
sc,
"Invalid parameter, "
1462 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1478 while ((written_so_far < buf_size) && (rc == 0)) {
1479 if (written_so_far == (buf_size -
sizeof(uint32_t))) {
1487 memcpy(&val, data_buf, 4);
1492 offset +=
sizeof(uint32_t);
1493 data_buf +=
sizeof(uint32_t);
1494 written_so_far +=
sizeof(uint32_t);
1511 uint32_t cmd_offset;
1515 for (i = 0; i < ((
sizeof(
struct dmae_cmd) / 4)); i++) {
1516 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1576 memset(dmae, 0,
sizeof(
struct dmae_cmd));
1593 uint32_t *wb_comp =
BXE_SP(sc, wb_comp);
1611 BLOGE(sc,
"DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n",
1622 BLOGE(sc,
"DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n",
1641 DBASSERT(sc, (len32 <= 4), (
"DMAE read length is %d", len32));
1644 data =
BXE_SP(sc, wb_data[0]);
1646 for (i = 0; i < len32; i++) {
1649 REG_RD(sc, (src_addr + (i * 4)));
1667 bxe_panic(sc, (
"DMAE failed (%d)\n", rc));
1673 bus_addr_t dma_addr,
1681 DBASSERT(sc, (len32 <= 4), (
"DMAE not ready and length is %d", len32));
1704 bxe_panic(sc, (
"DMAE failed (%d)\n", rc));
1710 bus_addr_t phys_addr,
1717 while (len > dmae_wr_max) {
1722 offset += (dmae_wr_max * 4);
1761 "port %d fw_sb_id %d sb_index %d ticks %d\n",
1762 port, fw_sb_id, sb_index, ticks);
1772 uint32_t enable_flag =
1773 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1781 flags &= ~HC_INDEX_DATA_HC_ENABLED;
1782 flags |= enable_flag;
1786 "port %d fw_sb_id %d sb_index %d disable %d\n",
1787 port, fw_sb_id, sb_index, disable);
1798 uint8_t ticks = (usec / 4);
1802 disable = (disable) ? 1 : ((usec) ? 0 : 1);
1870 BLOGE(sc,
"Invalid SPIO 0x%x mode 0x%x\n", spio, mode);
1888 BLOGD(sc,
DBG_LOAD,
"Set SPIO 0x%x -> output high\n", spio);
1918 int gpio_shift = (gpio_num +
1920 uint32_t gpio_mask = (1 << gpio_shift);
1924 BLOGE(sc,
"Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d"
1925 " gpio_mask 0x%x\n", gpio_num, port, gpio_port, gpio_shift,
1934 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
1946 int gpio_shift = (gpio_num +
1948 uint32_t gpio_mask = (1 << gpio_shift);
1952 BLOGE(sc,
"Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
1953 " gpio_shift %d gpio_mask 0x%x\n",
1954 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
1966 "Set GPIO %d (shift %d) -> output low\n",
1967 gpio_num, gpio_shift);
1975 "Set GPIO %d (shift %d) -> output high\n",
1976 gpio_num, gpio_shift);
1984 "Set GPIO %d (shift %d) -> input\n",
1985 gpio_num, gpio_shift);
2019 BLOGD(sc,
DBG_PHY,
"Set GPIO 0x%x -> output low\n", pins);
2025 BLOGD(sc,
DBG_PHY,
"Set GPIO 0x%x -> output high\n", pins);
2037 BLOGE(sc,
"Invalid GPIO mode assignment pins 0x%x mode 0x%x"
2038 " gpio_reg 0x%x\n", pins, mode, gpio_reg);
2058 int gpio_shift = (gpio_num +
2060 uint32_t gpio_mask = (1 << gpio_shift);
2064 BLOGE(sc,
"Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
2065 " gpio_shift %d gpio_mask 0x%x\n",
2066 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
2078 "Clear GPIO INT %d (shift %d) -> output low\n",
2079 gpio_num, gpio_shift);
2087 "Set GPIO INT %d (shift %d) -> output high\n",
2088 gpio_num, gpio_shift);
2142 (
SC_FUNC(sc) *
sizeof(uint32_t))), 1);
2160 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2161 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2164 "wrote command 0x%08x to FW MB param 0x%08x\n",
2165 (command | seq), param);
2169 DELAY(delay * 1000);
2170 rc =
SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2174 "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2175 cnt*delay, rc, seq);
2182 BLOGE(sc,
"FW failed to respond!\n");
2358 BUS_SPACE_BARRIER_WRITE);
2416 BLOGE(sc,
"EQ ring is full!\n");
2422 BLOGE(sc,
"SPQ ring is full!\n");
2440 spe->
hdr.
type = htole16(type);
2460 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2501 uint16_t did, sdid, svid, vid;
2507 vid = pci_get_vendor(dev);
2508 did = pci_get_device(dev);
2509 svid = pci_get_subvendor(dev);
2510 sdid = pci_get_subdevice(dev);
2518 if (descbuf == NULL)
2524 (((pci_read_config(dev, PCIR_REVID, 4) &
2526 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2529 device_set_desc_copy(dev, descbuf);
2530 free(descbuf, M_TEMP);
2531 return (BUS_PROBE_DEFAULT);
2542#ifdef BXE_CORE_LOCK_SX
2544 "bxe%d_core_lock", sc->
unit);
2547 snprintf(sc->core_mtx_name,
sizeof(sc->core_mtx_name),
2548 "bxe%d_core_lock", sc->
unit);
2549 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2553 "bxe%d_sp_lock", sc->
unit);
2557 "bxe%d_dmae_lock", sc->
unit);
2561 "bxe%d_phy_lock", sc->
unit);
2565 "bxe%d_fwmb_lock", sc->
unit);
2569 "bxe%d_print_lock", sc->
unit);
2573 "bxe%d_stats_lock", sc->
unit);
2577 "bxe%d_mcast_lock", sc->
unit);
2584#ifdef BXE_CORE_LOCK_SX
2587 if (mtx_initialized(&sc->core_mtx)) {
2588 mtx_destroy(&sc->core_mtx);
2592 if (mtx_initialized(&sc->
sp_mtx)) {
2593 mtx_destroy(&sc->
sp_mtx);
2596 if (mtx_initialized(&sc->
dmae_mtx)) {
2604 if (mtx_initialized(&sc->
fwmb_mtx)) {
2628 if_setdrvflags(ifp, 0);
2639static inline uint16_t
2665static inline uint8_t
2675 uint16_t rx_cq_cons_sb;
2694 BLOGD(sc,
DBG_SP,
"fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2699 BLOGD(sc,
DBG_SP,
"got UPDATE ramrod. CID %d\n", cid);
2704 BLOGD(sc,
DBG_SP,
"got MULTI[%d] setup ramrod\n", cid);
2709 BLOGD(sc,
DBG_SP,
"got MULTI[%d] tx-only setup ramrod\n", cid);
2714 BLOGD(sc,
DBG_SP,
"got MULTI[%d] halt ramrod\n", cid);
2719 BLOGD(sc,
DBG_SP,
"got MULTI[%d] teminate ramrod\n", cid);
2724 BLOGD(sc,
DBG_SP,
"got MULTI[%d] empty ramrod\n", cid);
2729 BLOGD(sc,
DBG_SP,
"ERROR: unexpected MC reply (%d) on fp[%d]\n",
2730 command, fp->
index);
2770 int max_agg_queues __diagused;
2775 "cons=%d prod=%d\n",
2776 fp->
index, queue, cons, prod);
2780 KASSERT((queue < max_agg_queues),
2781 (
"fp[%02d] invalid aggr queue (%d >= %d)!",
2782 fp->
index, queue, max_agg_queues));
2785 (
"fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2789 tmp_bd = tpa_info->
bd;
2791 if (tmp_bd.
m == NULL) {
2794 tmp = (uint32_t *)cqe;
2796 BLOGE(sc,
"fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n",
2797 fp->
index, queue, cons, prod);
2798 BLOGE(sc,
"cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2799 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2826 if (cons != index) {
2829 if (rx_buf->
m_map != NULL) {
2831 BUS_DMASYNC_POSTREAD);
2867 struct mbuf *m_frag;
2868 uint32_t frag_len, frag_size, i;
2876 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
2882 uint32_t *tmp = (uint32_t *)cqe;
2884 BLOGE(sc,
"fp[%02d].sge[0x%04x] has too many pages (%d)! "
2885 "pkt_len=%d len_on_bd=%d frag_size=%d\n",
2889 BLOGE(sc,
"cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2890 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2892 bxe_panic(sc, (
"sge page count error\n"));
2907 frag_len = min(frag_size, (uint32_t)(
SGE_PAGES));
2909 BLOGD(sc,
DBG_LRO,
"fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
2910 "sge_idx=%d frag_size=%d frag_len=%d\n",
2911 fp->
index, queue, i, j, sge_idx, frag_size, frag_len);
2923 m_frag->m_len = frag_len;
2930 m->m_pkthdr.len += frag_len;
2931 frag_size -= frag_len;
2935 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
2936 fp->
index, queue, frag_size);
2949 for (j = 0; j < 2; j++) {
2976 if (
SUB_S16(idx, last_max) > 0) {
2987 uint16_t last_max, last_elem, first_elem;
2996 for (i = 0; i < sge_len; i++) {
3002 "fp[%02d] fp_cqe->sgl[%d] = %d\n",
3003 fp->
index, sge_len - 1,
3004 le16toh(cqe->
sgl[sge_len - 1]));
3008 le16toh(cqe->
sgl[sge_len - 1]));
3015 if (last_elem + 1 != first_elem) {
3021 if (__predict_true(fp->
sge_mask[i])) {
3036 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3059 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3070 goto bxe_tpa_stop_exit;
3075 m->m_pkthdr.len = m->m_len = tpa_info->
len_on_bd;
3080 m->m_pkthdr.csum_data = 0xffff;
3081 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3094 m->m_pkthdr.ether_vtag = tpa_info->
vlan_tag;
3095 m->m_flags |= M_VLANTAG;
3099 if_setrcvif(m, ifp);
3102 m->m_pkthdr.flowid = fp->
index;
3105 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3129 struct mbuf *m_frag;
3130 uint16_t frags, frag_len;
3131 uint16_t sge_idx = 0;
3139 frag_size = len - lenonbd;
3147 m_frag->m_len = frag_len;
3160 frag_size -= frag_len;
3173 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3174 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3188 bd_prod_fw = bd_prod;
3199 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3200 fp->
index, hw_cq_cons, sw_cq_cons);
3202 while (sw_cq_cons != hw_cq_cons) {
3206 uint8_t cqe_fp_flags;
3208 uint16_t len, lenonbd, pad;
3209 struct mbuf *m = NULL;
3211 comp_ring_cons =
RCQ(sw_cq_cons);
3212 bd_prod =
RX_BD(bd_prod);
3213 bd_cons =
RX_BD(bd_cons);
3221 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3222 "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3223 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n",
3247 uint16_t frag_size, pages;
3252 bd_cons, bd_prod, cqe_fp);
3258 (
"CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3281 if (__predict_false(cqe_fp_flags &
3283 BLOGE(sc,
"flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3294 if (__predict_false(m == NULL)) {
3295 BLOGE(sc,
"No mbuf in rx chain descriptor %d for fp[%02d]\n",
3296 bd_cons, fp->
index);
3315 BLOGE(sc,
"mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3334 m->m_pkthdr.len = m->m_len = len;
3336 if ((len > 60) && (len > lenonbd)) {
3342 }
else if (lenonbd < len) {
3347 if_setrcvif(m, ifp);
3350 m->m_pkthdr.csum_flags = 0;
3353 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
3357 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3358 if (__predict_false(cqe_fp_flags &
3363 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3370 if (__predict_false(cqe_fp_flags &
3375 m->m_pkthdr.csum_data = 0xFFFF;
3376 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3385 m->m_flags |= M_VLANTAG;
3389 m->m_pkthdr.flowid = fp->
index;
3399 if (__predict_true(m != NULL)) {
3400 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3433 return (sw_cq_cons != hw_cq_cons);
3451 nbd = le16toh(tx_start_bd->
nbd) - 1;
3456 if (__predict_true(tx_buf->
m != NULL)) {
3481 BLOGE(sc,
"TX watchdog timeout on fp[%02d], resetting!\n", fp->
index);
3485 taskqueue_enqueue_timeout(taskqueue_thread,
3497 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3498 uint16_t tx_bd_avail;
3506 while (sw_cons != hw_cons) {
3507 pkt_cons =
TX_BD(sw_cons);
3510 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3511 fp->
index, hw_cons, sw_cons, pkt_cons);
3522 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3530 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
3532 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3565 BLOGE(
sc,
"Timeout waiting for fp[%d] "
3566 "transmits to complete!\n", i);
3584 uint8_t wait_for_comp)
3586 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3590 if (wait_for_comp) {
3597 rc = mac_obj->
delete_all(
sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3599 BLOGE(
sc,
"Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n",
3600 rc, mac_type, wait_for_comp);
3609 unsigned long *rx_accept_flags,
3610 unsigned long *tx_accept_flags)
3613 *rx_accept_flags = 0;
3614 *tx_accept_flags = 0;
3672 BLOGE(
sc,
"Unknown rx_mode (0x%x)\n", rx_mode);
3688 unsigned long rx_mode_flags,
3689 unsigned long rx_accept_flags,
3690 unsigned long tx_accept_flags,
3691 unsigned long ramrod_flags)
3696 memset(&ramrod_param, 0,
sizeof(ramrod_param));
3699 ramrod_param.
cid = 0;
3720 BLOGE(sc,
"Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x "
3721 "rx_accept_flags 0x%x tx_accept_flags 0x%x "
3722 "ramrod_flags 0x%x rc %d failed\n", sc->
rx_mode,
cl_id,
3760 BLOGI(sc,
"NO MCP - load counts[%d] %d, %d, %d\n",
3761 path, load_count[path][0], load_count[path][1],
3762 load_count[path][2]);
3763 load_count[path][0]++;
3764 load_count[path][1 + port]++;
3765 BLOGI(sc,
"NO MCP - new load counts[%d] %d, %d, %d\n",
3766 path, load_count[path][0], load_count[path][1],
3767 load_count[path][2]);
3768 if (load_count[path][0] == 1) {
3770 }
else if (load_count[path][1 + port] == 1) {
3784 BLOGI(sc,
"NO MCP - load counts[%d] %d, %d, %d\n",
3785 path, load_count[path][0], load_count[path][1],
3786 load_count[path][2]);
3787 load_count[path][0]--;
3788 load_count[path][1 + port]--;
3789 BLOGI(sc,
"NO MCP - new load counts[%d] %d, %d, %d\n",
3790 path, load_count[path][0], load_count[path][1],
3791 load_count[path][2]);
3792 if (load_count[path][0] == 0) {
3794 }
else if (load_count[path][1 + port] == 0) {
3806 uint32_t reset_code = 0;
3822 return (reset_code);
3830 uint32_t reset_param =
3879 BLOGE(sc,
"Unexpected function state! "
3880 "Forcing STARTED-->TX_STOPPED-->STARTED\n");
3937static inline uint8_t
3946 if (!(atomic_load_acq_long(&sc->
sp_state) & mask)) {
3955 tmp = atomic_load_acq_long(&sc->
sp_state);
3957 BLOGE(sc,
"Filtering completion timed out: "
3958 "sp_state 0x%lx, mask 0x%lx\n",
3985 BLOGE(sc,
"FUNC_STOP ramrod failed. "
3986 "Running a dry transaction (%d)\n", rc);
4029 uint32_t unload_mode,
4034 uint32_t reset_code;
4045 BLOGE(sc,
"Failed to delete all ETH MACs (%d)\n", rc);
4051 BLOGE(sc,
"Failed to delete UC MACs list (%d)\n", rc);
4077 BLOGE(sc,
"Failed to send DEL MCAST command (%d)\n", rc);
4097 BLOGE(sc,
"bxe_func_wait_started failed (%d)\n", rc);
4115 BLOGE(sc,
"Common slow path ramrods got stuck!(%d)\n", rc);
4122 BLOGE(sc,
"Function stop failed!(%d)\n", rc);
4134 BLOGE(sc,
"Hardware reset failed(%d)\n", rc);
4148 "Disabling 'close the gates'\n");
4188 BLOGE(sc,
"Failed to clean ETH MACs (%d)\n", rc);
4194 rc = mac_obj->
delete_all(sc, mac_obj, &vlan_mac_flags,
4197 BLOGE(sc,
"Failed to clean UC list MACs (%d)\n", rc);
4208 BLOGE(sc,
"Failed to send DEL MCAST command (%d)\n", rc);
4216 BLOGE(sc,
"Failed to clean MCAST object (%d)\n", rc);
4225static __noinline
int
4227 uint32_t unload_mode,
4230 uint8_t global = FALSE;
4236 if_setdrvflagbits(sc->
ifp, 0, IFF_DRV_RUNNING);
4274 BLOGE(
sc,
"Can't unload in closed or error state recover_state 0x%x"
4404 struct ifmedia *ifm;
4409 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4413 switch (IFM_SUBTYPE(ifm->ifm_media)) {
4419 case IFM_10G_TWINAX:
4423 IFM_SUBTYPE(ifm->ifm_media));
4444 ifmr->ifm_status = IFM_AVALID;
4447 ifmr->ifm_active = IFM_ETHER;
4450 if ((
ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4451 ifmr->ifm_active |= IFM_NONE;
4452 BLOGD(sc,
DBG_PHY,
"in %s : nic still not loaded fully\n", __func__);
4460 ifmr->ifm_status |= IFM_ACTIVE;
4461 ifmr->ifm_active |= IFM_FDX;
4463 ifmr->ifm_active |= IFM_NONE;
4469 ifmr->ifm_active |= sc->
media;
4484 if (if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING) {
4512 struct ifreq *ifr = (
struct ifreq *)data;
4526 if (sc->
mtu == ifr->ifr_mtu) {
4531 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4532 BLOGE(sc,
"Unsupported MTU size %d (range is %d-%d)\n",
4533 ifr->ifr_mtu, mtu_min, mtu_max);
4538 atomic_store_rel_int((
volatile unsigned int *)&sc->
mtu,
4539 (
unsigned long)ifr->ifr_mtu);
4545 if_setmtu(ifp, ifr->ifr_mtu);
4555 if (if_getflags(ifp) & IFF_UP) {
4556 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4563 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4575 BLOGD(sc,
DBG_IOCTL,
"Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4578 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4589 mask = (ifr->ifr_reqcap ^ if_getcapenable(ifp));
4591 BLOGD(sc,
DBG_IOCTL,
"Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4595 if (mask & IFCAP_LRO) {
4596 if_togglecapenable(ifp, IFCAP_LRO);
4598 (if_getcapenable(ifp) & IFCAP_LRO) ?
"ON" :
"OFF");
4603 if (mask & IFCAP_TXCSUM) {
4604 if_togglecapenable(ifp, IFCAP_TXCSUM);
4606 (if_getcapenable(ifp) & IFCAP_TXCSUM) ?
"ON" :
"OFF");
4607 if (if_getcapenable(ifp) & IFCAP_TXCSUM) {
4608 if_sethwassistbits(ifp, (CSUM_IP |
4615 if_clearhwassist(ifp);
4620 if (mask & IFCAP_RXCSUM) {
4621 if_togglecapenable(ifp, IFCAP_RXCSUM);
4623 (if_getcapenable(ifp) & IFCAP_RXCSUM) ?
"ON" :
"OFF");
4624 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
4625 if_sethwassistbits(ifp, (CSUM_IP |
4632 if_clearhwassist(ifp);
4637 if (mask & IFCAP_TSO4) {
4638 if_togglecapenable(ifp, IFCAP_TSO4);
4640 (if_getcapenable(ifp) & IFCAP_TSO4) ?
"ON" :
"OFF");
4644 if (mask & IFCAP_TSO6) {
4645 if_togglecapenable(ifp, IFCAP_TSO6);
4647 (if_getcapenable(ifp) & IFCAP_TSO6) ?
"ON" :
"OFF");
4651 if (mask & IFCAP_VLAN_HWTSO) {
4653 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
4655 (if_getcapenable(ifp) & IFCAP_VLAN_HWTSO) ?
"ON" :
"OFF");
4659 if (mask & IFCAP_VLAN_HWCSUM) {
4661 BLOGE(sc,
"Changing VLAN_HWCSUM is not supported!\n");
4666 if (mask & IFCAP_VLAN_MTU) {
4668 BLOGE(sc,
"Changing VLAN_MTU is not supported!\n");
4673 if (mask & IFCAP_VLAN_HWTAGGING) {
4675 BLOGE(sc,
"Changing VLAN_HWTAGGING is not supported!\n");
4680 if (mask & IFCAP_VLAN_HWFILTER) {
4682 BLOGE(sc,
"Changing VLAN_HWFILTER is not supported!\n");
4696 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4698 error = ifmedia_ioctl(ifp, ifr, &sc->
ifmedia, command);
4704 error = ether_ioctl(ifp, command, data);
4708 if (reinit && (if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING)) {
4710 "Re-initializing hardware from IOCTL change\n");
4721static __noinline
void
4741 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4742 i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data);
4744 if (m->m_flags & M_PKTHDR) {
4746 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4747 i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS,
4748 (
int)m->m_pkthdr.csum_flags, CSUM_BITS);
4751 if (m->m_flags & M_EXT) {
4752 switch (m->m_ext.ext_type) {
4753 case EXT_CLUSTER: type =
"EXT_CLUSTER";
break;
4754 case EXT_SFBUF: type =
"EXT_SFBUF";
break;
4755 case EXT_JUMBOP: type =
"EXT_JUMBOP";
break;
4756 case EXT_JUMBO9: type =
"EXT_JUMBO9";
break;
4757 case EXT_JUMBO16: type =
"EXT_JUMBO16";
break;
4758 case EXT_PACKET: type =
"EXT_PACKET";
break;
4759 case EXT_MBUF: type =
"EXT_MBUF";
break;
4760 case EXT_NET_DRV: type =
"EXT_NET_DRV";
break;
4761 case EXT_MOD_TYPE: type =
"EXT_MOD_TYPE";
break;
4762 case EXT_DISPOSABLE: type =
"EXT_DISPOSABLE";
break;
4763 case EXT_EXTREF: type =
"EXT_EXTREF";
break;
4764 default: type =
"UNKNOWN";
break;
4768 "%02d: - m_ext: %p ext_size=%d type=%s\n",
4769 i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
4791 bus_dma_segment_t *segs,
4794 uint32_t num_wnds, wnd_size, wnd_sum;
4795 int32_t frag_idx, wnd_idx;
4796 unsigned short lso_mss;
4800 num_wnds = nsegs - wnd_size;
4801 lso_mss = htole16(m->m_pkthdr.tso_segsz);
4808 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
4809 wnd_sum += htole16(segs[frag_idx].ds_len);
4813 if (wnd_sum < lso_mss) {
4818 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
4820 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
4822 wnd_sum += htole16(segs[frag_idx].ds_len);
4823 if (wnd_sum < lso_mss) {
4834 uint32_t *parsing_data)
4836 struct ether_vlan_header *eh = NULL;
4837 struct ip *ip4 = NULL;
4838 struct ip6_hdr *ip6 = NULL;
4840 struct tcphdr *th = NULL;
4841 int e_hlen, ip_hlen, l4_off;
4844 if (m->m_pkthdr.csum_flags == CSUM_IP) {
4850 eh = mtod(m,
struct ether_vlan_header *);
4853 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4854 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4855 proto = ntohs(eh->evl_proto);
4857 e_hlen = ETHER_HDR_LEN;
4858 proto = ntohs(eh->evl_encap_proto);
4864 ip4 = (m->m_len <
sizeof(
struct ip)) ?
4865 (struct ip *)m->m_next->m_data :
4866 (
struct ip *)(m->m_data + e_hlen);
4868 ip_hlen = (ip4->ip_hl << 2);
4871 case ETHERTYPE_IPV6:
4873 ip6 = (m->m_len <
sizeof(
struct ip6_hdr)) ?
4874 (struct ip6_hdr *)m->m_next->m_data :
4875 (
struct ip6_hdr *)(m->m_data + e_hlen);
4877 ip_hlen =
sizeof(
struct ip6_hdr);
4887 l4_off = (e_hlen + ip_hlen);
4893 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4897 th = (
struct tcphdr *)(ip + ip_hlen);
4899 *parsing_data |= ((th->th_off <<
4902 return (l4_off + (th->th_off << 2));
4903 }
else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4906 return (l4_off +
sizeof(
struct udphdr));
4918 struct ether_vlan_header *eh = NULL;
4919 struct ip *ip4 = NULL;
4920 struct ip6_hdr *ip6 = NULL;
4922 struct tcphdr *th = NULL;
4923 struct udphdr *uh = NULL;
4924 int e_hlen, ip_hlen;
4931 eh = mtod(m,
struct ether_vlan_header *);
4934 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4935 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4936 proto = ntohs(eh->evl_proto);
4938 e_hlen = ETHER_HDR_LEN;
4939 proto = ntohs(eh->evl_encap_proto);
4945 ip4 = (m->m_len <
sizeof(
struct ip)) ?
4946 (struct ip *)m->m_next->m_data :
4947 (
struct ip *)(m->m_data + e_hlen);
4949 ip_hlen = (ip4->ip_hl << 1);
4952 case ETHERTYPE_IPV6:
4954 ip6 = (m->m_len <
sizeof(
struct ip6_hdr)) ?
4955 (struct ip6_hdr *)m->m_next->m_data :
4956 (
struct ip6_hdr *)(m->m_data + e_hlen);
4958 ip_hlen = (
sizeof(
struct ip6_hdr) >> 1);
4967 hlen = (e_hlen >> 1);
4970 if (m->m_flags & M_VLANTAG) {
4983 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4986 th = (
struct tcphdr *)(ip + (ip_hlen << 1));
4988 hlen += (uint16_t)(th->th_off << 1);
4989 }
else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4991 uh = (
struct udphdr *)(ip + (ip_hlen << 1));
4992 hlen += (
sizeof(
struct udphdr) / 2);
5000 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5005 }
else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5026 tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5029 tmp_csum = in_pseudo(*tmp_uh,
5031 *(uint16_t *)(tmp_uh + 2));
5041 uint32_t *parsing_data)
5043 *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5054 struct ether_vlan_header *eh = NULL;
5055 struct ip *ip = NULL;
5056 struct tcphdr *th = NULL;
5060 eh = mtod(m,
struct ether_vlan_header *);
5063 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5064 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5068 ip = (
struct ip *)(m->m_data + e_hlen);
5069 th = (
struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5071 pbd->
lso_mss = htole16(m->m_pkthdr.tso_segsz);
5073 pbd->
tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5077 pbd->
ip_id = ntohs(ip->ip_id);
5079 ntohs(in_pseudo(ip->ip_src.s_addr,
5081 htons(IPPROTO_TCP)));
5085 ntohs(in_pseudo(&ip6->ip6_src,
5087 htons(IPPROTO_TCP)));
5109 bus_dma_segment_t segs[32];
5118 uint16_t bd_prod, pkt_prod, total_pkt_size;
5120 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5122 uint16_t tx_bd_avail;
5123 struct ether_vlan_header *eh;
5124 uint32_t pbd_e2_parsing_data = 0;
5131 M_ASSERTPKTHDR(*m_head);
5134 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5137 tx_total_pkt_size_bd = NULL;
5149 segs, &nsegs, BUS_DMA_NOWAIT);
5152 if(__predict_false(error != 0)) {
5154 if (error == ENOMEM) {
5157 }
else if (error == EFBIG) {
5160 m0 = m_defrag(*m_head, M_NOWAIT);
5169 segs, &nsegs, BUS_DMA_NOWAIT);
5177 BLOGE(sc,
"Unknown TX mapping error rc=%d\n", error);
5182 goto bxe_tx_encap_continue;
5188 if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5193 goto bxe_tx_encap_continue;
5208 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5210 goto bxe_tx_encap_continue;
5222 m0 = m_defrag(*m_head, M_NOWAIT);
5232 segs, &nsegs, BUS_DMA_NOWAIT);
5239 if(m0->m_pkthdr.csum_flags & CSUM_TSO) {
5260bxe_tx_encap_continue:
5277 if (m0->m_flags & M_BCAST) {
5279 }
else if (m0->m_flags & M_MCAST) {
5292 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5293 pkt_prod, tx_buf, fp->
tx_pkt_prod, bd_prod, tx_start_bd);
5297 tx_start_bd->
nbytes = htole16(segs[0].ds_len);
5298 total_pkt_size += tx_start_bd->
nbytes;
5305 tx_start_bd->
nbd = htole16(nbds);
5307 if (m0->m_flags & M_VLANTAG) {
5315 eh = mtod(m0,
struct ether_vlan_header *);
5329 if (m0->m_pkthdr.csum_flags) {
5330 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5342 }
else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5343 (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5345 }
else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5355 if (m0->m_pkthdr.csum_flags) {
5362 uint16_t global_data = 0;
5367 if (m0->m_pkthdr.csum_flags) {
5377 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5381 if (__predict_false(tx_start_bd->
nbytes > hlen)) {
5386 tx_start_bd->
nbd = htole16(nbds);
5387 tx_start_bd->
nbytes = htole16(hlen);
5393 tx_data_bd->
addr_hi = htole32(
U64_HI(segs[0].ds_addr + hlen));
5394 tx_data_bd->
addr_lo = htole32(
U64_LO(segs[0].ds_addr + hlen));
5395 tx_data_bd->
nbytes = htole16(segs[0].ds_len - hlen);
5396 if (tx_total_pkt_size_bd == NULL) {
5397 tx_total_pkt_size_bd = tx_data_bd;
5401 "TSO split header size is %d (%x:%x) nbds %d\n",
5402 le16toh(tx_start_bd->
nbytes),
5403 le32toh(tx_start_bd->
addr_hi),
5404 le32toh(tx_start_bd->
addr_lo),
5415 if (pbd_e2_parsing_data) {
5420 for (i = 1; i < nsegs ; i++) {
5425 tx_data_bd->
nbytes = htole16(segs[i].ds_len);
5426 if (tx_total_pkt_size_bd == NULL) {
5427 tx_total_pkt_size_bd = tx_data_bd;
5429 total_pkt_size += tx_data_bd->
nbytes;
5434 if (tx_total_pkt_size_bd != NULL) {
5440 for (i = 0; i < nbds; i++)
5444 "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5445 "bd_flags=0x%x hdr_nbds=%d\n",
5448 le16toh(tx_start_bd->
nbd),
5452 }
else if (i == 1) {
5455 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5456 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5457 "tcp_seq=%u total_hlen_w=%u\n",
5470 "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5471 "src=%02x:%02x:%02x parsing_data=0x%x\n",
5487 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5490 le16toh(tx_data_bd->
nbytes),
5492 le32toh(tx_data_bd->
addr_lo));
5499 BLOGD(sc,
DBG_TX,
"doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5527 0, 0, BUS_SPACE_BARRIER_READ);
5531 0, 0, BUS_SPACE_BARRIER_READ);
5541 struct mbuf *m = NULL;
5543 uint16_t tx_bd_avail;
5548 while (!if_sendq_empty(ifp)) {
5554 m = if_dequeue(ifp);
5555 if (__predict_false(m == NULL)) {
5571 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5572 if_sendq_prepend(ifp, m);
5585 if_etherbpfmtap(ifp, m);
5593 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
5613 sc = if_getsoftc(ifp);
5615 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
5616 BLOGW(
sc,
"Interface not running, ignoring transmit request\n");
5621 BLOGW(
sc,
"Interface link is down, ignoring transmit request\n");
5627 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
5643 struct buf_ring *tx_br = fp->
tx_br;
5645 int depth, rc, tx_count;
5646 uint16_t tx_bd_avail;
5658 BLOGE(sc,
"Multiqueue TX and no buf_ring!\n");
5663 rc = drbr_enqueue(ifp, tx_br, m);
5666 goto bxe_tx_mq_start_locked_exit;
5672 goto bxe_tx_mq_start_locked_exit;
5676 depth = drbr_inuse(ifp, tx_br);
5682 while ((next = drbr_peek(ifp, tx_br)) != NULL) {
5692 drbr_advance(ifp, tx_br);
5707 if (__predict_false(rc != 0)) {
5711 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5712 drbr_putback(ifp, tx_br, next);
5716 drbr_advance(ifp, tx_br);
5726 if_etherbpfmtap(ifp, next);
5728 drbr_advance(ifp, tx_br);
5737bxe_tx_mq_start_locked_exit:
5739 if (!drbr_empty(ifp, tx_br)) {
5776 fp = &
sc->
fp[fp_index];
5787 rc = drbr_enqueue(ifp, fp->
tx_br, m);
5788 taskqueue_enqueue(fp->
tq, &fp->
tx_task);
5806 BLOGD(sc,
DBG_LOAD,
"Not clearing fp[%02d] buf_ring (state=%d)\n",
5811 if (fp->
tx_br != NULL) {
5814 while ((m = buf_ring_dequeue_sc(fp->
tx_br)) != NULL) {
5848 ilt_client->
start = line;
5855 ilt_client->
end = (line - 1);
5858 "ilt client[CDU]: start %d, end %d, "
5859 "psz 0x%x, flags 0x%x, hw psz %d\n",
5860 ilt_client->
start, ilt_client->
end,
5870 ilt_client->
flags = 0;
5871 ilt_client->
start = line;
5877 ilt_client->
end = (line - 1);
5880 "ilt client[QM]: start %d, end %d, "
5881 "psz 0x%x, flags 0x%x, hw psz %d\n",
5882 ilt_client->
start, ilt_client->
end,
5892 ilt_client->
flags = 0;
5893 ilt_client->
start = line;
5895 ilt_client->
end = (line - 1);
5898 "ilt client[SRC]: start %d, end %d, "
5899 "psz 0x%x, flags 0x%x, hw psz %d\n",
5900 ilt_client->
start, ilt_client->
end,
5908 ilt_client->
flags = 0;
5909 ilt_client->
start = line;
5911 ilt_client->
end = (line - 1);
5914 "ilt client[TM]: start %d, end %d, "
5915 "psz 0x%x, flags 0x%x, hw psz %d\n",
5916 ilt_client->
start, ilt_client->
end,
5921 KASSERT((line <=
ILT_MAX_LINES), (
"Invalid number of ILT lines!"));
5928 uint32_t rx_buf_size;
5933 if(rx_buf_size <= MCLBYTES){
5936 }
else if (rx_buf_size <= MJUMPAGESIZE){
5939 }
else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){
5942 }
else if (rx_buf_size <= (2 * MJUMPAGESIZE)){
5960 (M_NOWAIT | M_ZERO))) == NULL) {
5975 (M_NOWAIT | M_ZERO))) == NULL) {
5985 if (sc->
ilt != NULL) {
5986 free(sc->
ilt, M_BXE_ILT);
6040 for (i = 0, allocated = 0; allocated < context_size; i++) {
6042 (context_size - allocated));
6046 "cdu context") != 0) {
6062 for (i = 0; i < 4; i++) {
6064 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6074 BLOGE(sc,
"ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6096 BUS_DMASYNC_POSTREAD);
6113 int i, max_agg_queues;
6124 for (i = 0; i < max_agg_queues; i++) {
6128 BUS_DMASYNC_POSTREAD);
6155 BUS_DMASYNC_POSTREAD);
6177 if (fp->
tx_br != NULL) {
6179 if (mtx_initialized(&fp->
tx_mtx)) {
6183 while ((m = buf_ring_dequeue_sc(fp->
tx_br)) != NULL)
6195 BLOGE(sc,
"failed to claim all rx mbufs (%d left)\n",
6200 BLOGE(sc,
"failed to claim all sge mbufs (%d left)\n",
6205 BLOGE(sc,
"failed to claim all sge mbufs (%d left)\n",
6210 BLOGE(sc,
"failed to release tx mbufs (%d left)\n",
6220 uint16_t prev_index,
6225 bus_dma_segment_t segs[1];
6234 if (__predict_false(m == NULL)) {
6247 m, segs, &nsegs, BUS_DMA_NOWAIT);
6248 if (__predict_false(rc != 0)) {
6256 KASSERT((nsegs == 1), (
"Too many segments, %d returned!", nsegs));
6260 if (prev_index != index) {
6263 if (rx_buf->
m_map != NULL) {
6265 BUS_DMASYNC_POSTREAD);
6280 if (rx_buf->
m_map != NULL) {
6282 BUS_DMASYNC_POSTREAD);
6287 map = (prev_index != index) ?
6292 BUS_DMASYNC_PREREAD);
6307 bus_dma_segment_t segs[1];
6315 if (__predict_false(m == NULL)) {
6328 m, segs, &nsegs, BUS_DMA_NOWAIT);
6329 if (__predict_false(rc != 0)) {
6337 KASSERT((nsegs == 1), (
"Too many segments, %d returned!", nsegs));
6340 if (tpa_info->
bd.
m_map != NULL) {
6342 BUS_DMASYNC_POSTREAD);
6351 BUS_DMASYNC_PREREAD);
6353 tpa_info->
seg = segs[0];
6369 bus_dma_segment_t segs[1];
6377 if (__predict_false(m == NULL)) {
6390 m, segs, &nsegs, BUS_DMA_NOWAIT);
6391 if (__predict_false(rc != 0)) {
6399 KASSERT((nsegs == 1), (
"Too many segments, %d returned!", nsegs));
6404 if (sge_buf->
m_map != NULL) {
6406 BUS_DMASYNC_POSTREAD);
6411 map = sge_buf->
m_map;
6415 BUS_DMASYNC_PREREAD);
6425static __noinline
int
6430 int ring_prod, cqe_ring_prod;
6436 ring_prod = cqe_ring_prod = 0;
6444 BLOGE(
sc,
"mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6446 goto bxe_alloc_fp_buffers_error;
6450 cqe_ring_prod =
RCQ_NEXT(cqe_ring_prod);
6462 for (j = 0; j < max_agg_queues; j++) {
6465 BLOGE(
sc,
"mbuf alloc fail for fp[%02d] TPA queue %d\n",
6468 goto bxe_alloc_fp_buffers_error;
6480 BLOGE(
sc,
"mbuf alloc fail for fp[%02d] SGE %d\n",
6484 goto bxe_alloc_fp_buffers_error;
6496bxe_alloc_fp_buffers_error:
6525 uint8_t num_queue_stats;
6587 BLOGD(sc,
DBG_LOAD,
"statistics request base address set to %#jx\n",
6590 BLOGD(sc,
DBG_LOAD,
"statistics data base address set to %#jx\n",
6609#define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
6610#define BXE_PATH0_LOAD_CNT_MASK 0x000000ff
6611#define BXE_PATH0_LOAD_CNT_SHIFT 0
6612#define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00
6613#define BXE_PATH1_LOAD_CNT_SHIFT 8
6614#define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6615#define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
6616#define BXE_GLOBAL_RESET_BIT 0x00040000
6695 return (val & bit) ? FALSE : TRUE;
6709 BLOGD(sc,
DBG_LOAD,
"Old value for GLOB_REG=0x%08x\n", val);
6711 val = ((val & mask) >> shift);
6713 BLOGD(sc,
DBG_LOAD,
"Load mask engine %d = 0x%08x\n", engine, val);
6733 BLOGD(sc,
DBG_LOAD,
"Old value for GLOB_REG=0x%08x\n", val);
6736 val1 = ((val & mask) >> shift);
6745 val |= ((val1 << shift) & mask);
6768 val1 = (val & mask) >> shift;
6777 val |= ((val1 << shift) & mask);
6787 uint32_t *load_code)
6809 if (!(*load_code)) {
6810 BLOGE(sc,
"MCP response failure!\n");
6816 BLOGE(sc,
"MCP refused load request\n");
6832 uint32_t my_fw, loaded_fw;
6849 if (my_fw != loaded_fw) {
6850 BLOGE(sc,
"FW 0x%08x already loaded (mine is 0x%08x)",
6864 uint32_t ncsi_oem_data_addr;
6884 ncsi_oem_data_addr =
SHMEM2_RD(sc, ncsi_oem_data_addr);
6885 if (ncsi_oem_data_addr) {
6887 (ncsi_oem_data_addr +
6919 MFCFG_RD(sc, func_mf_config[abs_func].config);
6928 sc->
flags &= ~BXE_MF_FUNC_DIS;
6937 for (j = 0; j < 1000; j++) {
6941 if (val & (1L << 31))
6947 if (!(val & (1L << 31))) {
6948 BLOGE(sc,
"Cannot acquire MCP access lock register\n");
6965 uint32_t ext_phy_config;
6969 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
6971 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
6973 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
6977 BLOGW(sc,
"Fan Failure has caused the driver to shutdown "
6978 "the card to prevent permanent damage. "
6979 "Please contact OEM Support for assistance\n");
6983 bxe_panic(sc, (
"Schedule task to handle fan failure\n"));
6990 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
6991 schedule_delayed_work(&sc->sp_rtnl_task, 0);
6999 uint32_t pause_enabled = 0;
7037 taskqueue_enqueue(fp->
tq, &fp->
tx_task);
7072 uint32_t nig_mask = 0;
7078 BLOGE(
sc,
"IGU ERROR attn=0x%08x\n", asserted);
7086 aeu_mask, asserted);
7088 aeu_mask &= ~(asserted & 0x3ff);
7105 nig_mask =
REG_RD(
sc, nig_int_mask_addr);
7188 BLOGE(
sc,
"Failed to verify IGU ack on time\n");
7194 REG_WR(
sc, nig_int_mask_addr, nig_mask);
7205 BLOGI(
sc,
"%s%s", idx ?
", " :
"", blk);
7214 uint32_t cur_bit = 0;
7217 for (i = 0; sig; i++) {
7218 cur_bit = ((uint32_t)0x1 << i);
7219 if (sig & cur_bit) {
7267 uint32_t cur_bit = 0;
7268 for (i = 0; sig; i++) {
7269 cur_bit = ((uint32_t)0x1 << i);
7270 if (sig & cur_bit) {
7353 uint32_t cur_bit = 0;
7356 for (i = 0; sig; i++) {
7357 cur_bit = ((uint32_t)0x1 << i);
7358 if (sig & cur_bit) {
7409 uint32_t cur_bit = 0;
7412 for (i = 0; sig; i++) {
7413 cur_bit = ((uint32_t)0x1 << i);
7414 if (sig & cur_bit) {
7455 uint32_t cur_bit = 0;
7458 for (i = 0; sig; i++) {
7459 cur_bit = ((uint32_t)0x1 << i);
7460 if (sig & cur_bit) {
7493 BLOGE(
sc,
"Parity error: HW block parity attention:\n"
7494 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7502 BLOGI(
sc,
"Parity errors detected in blocks: ");
7511 par_num, global, print);
7519 par_num, global, print);
7528 if( *global == TRUE ) {
7575 boolean_t err_flg = FALSE;
7579 BLOGE(sc,
"PGLUE hw attention 0x%08x\n", val);
7582 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7584 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7586 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7588 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7590 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7592 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7594 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7596 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7598 BLOGE(sc,
"PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7603 BLOGE(sc,
"ATC hw attention 0x%08x\n", val);
7606 BLOGE(sc,
"ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7608 BLOGE(sc,
"ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7610 BLOGE(sc,
"ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7612 BLOGE(sc,
"ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7614 BLOGE(sc,
"ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7616 BLOGE(sc,
"ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7621 BLOGE(sc,
"FATAL parity attention set4 0x%08x\n",
7628 taskqueue_enqueue_timeout(taskqueue_thread,
7685#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
7705 if (if_getcapenable(sc->
ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) {
7721 uint32_t drv_info_ctl =
SHMEM2_RD(sc, drv_info_control);
7776 sc->
flags &= ~BXE_MF_FUNC_DIS;
7779 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
7784 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
7815 val = (0xff0f | (1 << (
SC_VN(sc) + 4)));
7832 uint32_t row0, row1, row2, row3;
7837 BLOGE(sc,
"XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7848 BLOGE(sc,
"XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7849 i, row3, row2, row1, row0);
7859 BLOGE(sc,
"TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7871 BLOGE(sc,
"TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7872 i, row3, row2, row1, row0);
7882 BLOGE(sc,
"CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7894 BLOGE(sc,
"CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7895 i, row3, row2, row1, row0);
7905 BLOGE(sc,
"USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7917 BLOGE(sc,
"USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7918 i, row3, row2, row1, row0);
7965 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
7980 BLOGE(sc,
"MC assert!\n");
7988 taskqueue_enqueue_timeout(taskqueue_thread,
7993 BLOGE(sc,
"MCP assert!\n");
7996 taskqueue_enqueue_timeout(taskqueue_thread,
8002 BLOGE(sc,
"Unknown HW assert! (attn 0x%08x)\n", attn);
8007 BLOGE(sc,
"LATCHED attention 0x%08x (masked)\n", attn);
8010 BLOGE(sc,
"GRC time-out 0x%08x\n", val);
8014 BLOGE(sc,
"GRC reserved 0x%08x\n", val);
8026 uint32_t val0, mask0, val1, mask1;
8028 boolean_t err_flg = FALSE;
8032 BLOGE(sc,
"CFC hw attention 0x%08x\n", val);
8035 BLOGE(sc,
"FATAL error from CFC\n");
8042 BLOGE(sc,
"PXP hw attention-0 0x%08x\n", val);
8044 if (val & 0x18000) {
8045 BLOGE(sc,
"FATAL error from PXP\n");
8051 BLOGE(sc,
"PXP hw attention-1 0x%08x\n", val);
8056#define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8057#define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8081 BLOGE(sc,
"PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8088 BLOGE(sc,
"PXP2_WR_PGLUE_EOP_ERROR\n");
8096 ((val1 & mask1) == 0))
8097 attn &= ~AEU_PXP2_HW_INT_BIT;
8106 val =
REG_RD(sc, reg_offset);
8108 REG_WR(sc, reg_offset, val);
8110 BLOGE(sc,
"FATAL HW block attention set2 0x%x\n",
8113 bxe_panic(sc, (
"HW block attention set2\n"));
8117 taskqueue_enqueue_timeout(taskqueue_thread,
8130 boolean_t err_flg = FALSE;
8134 BLOGE(sc,
"DB hw attention 0x%08x\n", val);
8137 BLOGE(sc,
"FATAL error from DORQ\n");
8146 val =
REG_RD(sc, reg_offset);
8148 REG_WR(sc, reg_offset, val);
8150 BLOGE(sc,
"FATAL HW block attention set1 0x%08x\n",
8153 bxe_panic(sc, (
"HW block attention set1\n"));
8157 taskqueue_enqueue_timeout(taskqueue_thread,
8175 val =
REG_RD(sc, reg_offset);
8176 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8177 REG_WR(sc, reg_offset, val);
8179 BLOGW(sc,
"SPIO5 hw attention\n");
8193 val =
REG_RD(sc, reg_offset);
8195 REG_WR(sc, reg_offset, val);
8199 taskqueue_enqueue_timeout(taskqueue_thread,
8202 bxe_panic(sc, (
"FATAL HW block attention set0 0x%lx\n",
8209 uint32_t deasserted)
8218 uint8_t global = FALSE;
8235 taskqueue_enqueue_timeout(taskqueue_thread,
8251 BLOGD(sc,
DBG_INTR,
"attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8255 if (deasserted & (1 << index)) {
8259 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8260 group_mask->
sig[0], group_mask->
sig[1],
8261 group_mask->
sig[2], group_mask->
sig[3],
8262 group_mask->
sig[4]);
8283 "about to mask 0x%08x at %s addr 0x%08x\n", val,
8288 BLOGE(sc,
"IGU error\n");
8298 BLOGD(sc,
DBG_INTR,
"aeu_mask 0x%08x newly deasserted 0x%08x\n",
8299 aeu_mask, deasserted);
8300 aeu_mask |= (deasserted & 0x3ff);
8320 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
8321 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
8324 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8325 attn_bits, attn_ack, asserted, deasserted);
8327 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8328 BLOGE(sc,
"BAD attention state\n");
8368 BLOGD(sc,
DBG_SP,
"retrieving fp from cid %d\n", cid);
8378 memset(&rparam, 0,
sizeof(rparam));
8392 "ERROR: Failed to send pending mcast commands (%d)\n", rc);
8418 BLOGD(sc,
DBG_SP,
"Got SETUP_MCAST completions\n");
8427 BLOGE(sc,
"Unsupported classification command: %d\n",
8432 rc = vlan_mac_obj->
complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8435 BLOGE(sc,
"Failed to schedule new commands (%d)\n", rc);
8436 }
else if (rc > 0) {
8437 BLOGD(sc,
DBG_SP,
"Scheduled next pending commands...\n");
8465 uint16_t hw_cons, sw_cons, sw_prod;
8494 BLOGD(sc,
DBG_SP,
"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8495 hw_cons, sw_cons, atomic_load_acq_long(&sc->
eq_spq_left));
8511 BLOGD(sc,
DBG_SP,
"got statistics completion event %d\n",
8545 BLOGD(sc,
DBG_SP,
"got FUNC_SWITCH_UPDATE ramrod\n");
8553 "AFEX: ramrod completed FUNCTION_UPDATE\n");
8580 switch (opcode | sc->
state) {
8614 BLOGE(sc,
"Unknown EQ event %d, sc->state 0x%x\n",
8653 status &= ~BXE_DEF_SB_ATT_IDX;
8663 status &= ~BXE_DEF_SB_IDX;
8667 if (__predict_false(status)) {
8668 BLOGE(sc,
"Got an unknown SP interrupt! (0x%04x)\n", status);
8691 uint8_t more_tx = FALSE;
8692 uint8_t more_rx = FALSE;
8703 if (!(if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING)) {
8737 uint8_t more_tx = FALSE;
8738 uint8_t more_rx = FALSE;
8786 uint16_t status, mask;
8803 if (__predict_false(status == 0)) {
8813 if (status & mask) {
8821 if (__predict_false(status & 0x1)) {
8831 if (__predict_false(status)) {
8832 BLOGW(
sc,
"Unexpected fastpath status (0x%08x)!\n", status);
8861 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
8880 bus_release_resource(sc->
dev,
8890 bus_release_resource(sc->
dev,
8896 pci_release_msi(sc->
dev);
8902 bus_release_resource(sc->
dev,
8908 pci_release_msi(sc->
dev);
8938 int num_requested = 0;
8939 int num_allocated = 0;
8946 msix_count = pci_msix_count(sc->
dev);
8950 msi_count = pci_msi_count(sc->
dev);
8953 BLOGD(sc,
DBG_LOAD,
"%d MSI and %d MSI-X vectors available\n",
8954 msi_count, msix_count);
8969 num_requested = min((sc->
num_queues + 1), msix_count);
8971 BLOGD(sc,
DBG_LOAD,
"Requesting %d MSI-X vectors\n", num_requested);
8973 num_allocated = num_requested;
8974 if ((rc = pci_alloc_msix(sc->
dev, &num_allocated)) != 0) {
8975 BLOGE(sc,
"MSI-X alloc failed! (%d)\n", rc);
8980 if (num_allocated < 2) {
8981 BLOGE(sc,
"MSI-X allocation less than 2!\n");
8983 pci_release_msi(sc->
dev);
8987 BLOGI(sc,
"MSI-X vectors Requested %d and Allocated %d\n",
8988 num_requested, num_allocated);
8997 for (i = 0; i < num_allocated; i++) {
9001 bus_alloc_resource_any(sc->
dev,
9004 RF_ACTIVE)) == NULL) {
9005 BLOGE(sc,
"Failed to map MSI-X[%d] (rid=%d)!\n",
9008 for (j = (i - 1); j >= 0; j--) {
9009 bus_release_resource(sc->
dev,
9018 pci_release_msi(sc->
dev);
9022 BLOGD(sc,
DBG_LOAD,
"Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9040 BLOGD(sc,
DBG_LOAD,
"Requesting %d MSI vectors\n", num_requested);
9042 num_allocated = num_requested;
9043 if ((rc = pci_alloc_msi(sc->
dev, &num_allocated)) != 0) {
9044 BLOGE(sc,
"MSI alloc failed (%d)!\n", rc);
9049 if (num_allocated != 1) {
9050 BLOGE(sc,
"MSI allocation is not 1!\n");
9052 pci_release_msi(sc->
dev);
9056 BLOGI(sc,
"MSI vectors Requested %d and Allocated %d\n",
9057 num_requested, num_allocated);
9068 bus_alloc_resource_any(sc->
dev,
9071 RF_ACTIVE)) == NULL) {
9072 BLOGE(sc,
"Failed to map MSI[0] (rid=%d)!\n", rid);
9076 pci_release_msi(sc->
dev);
9099 bus_alloc_resource_any(sc->
dev,
9102 (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9103 BLOGE(sc,
"Failed to map INTx (rid=%d)!\n", rid);
9114 BLOGE(sc,
"Interrupt Allocation: FAILED!!!\n");
9118 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9152 if (fp->
tq != NULL) {
9153 taskqueue_free(fp->
tq);
9183 "bxe%d_sp_tq",
sc->
unit);
9186 taskqueue_thread_enqueue,
9188 taskqueue_start_threads(&
sc->
sp_tq, 1, PWAIT,
9195 "bxe%d_fp%d_tq",
sc->
unit, i);
9198 fp->
tq = taskqueue_create(fp->
tq_name, M_NOWAIT,
9199 taskqueue_thread_enqueue,
9203 taskqueue_start_threads(&fp->
tq, 1, PI_NET,
9216 (INTR_TYPE_NET | INTR_MPSAFE),
9219 BLOGE(
sc,
"Failed to allocate MSI-X[0] vector (%d)\n", rc);
9220 goto bxe_interrupt_attach_exit;
9239 (INTR_TYPE_NET | INTR_MPSAFE),
9242 BLOGE(
sc,
"Failed to allocate MSI-X[%d] vector (%d)\n",
9244 goto bxe_interrupt_attach_exit;
9266 (INTR_TYPE_NET | INTR_MPSAFE),
9269 BLOGE(
sc,
"Failed to allocate MSI[0] vector (%d)\n", rc);
9270 goto bxe_interrupt_attach_exit;
9282 (INTR_TYPE_NET | INTR_MPSAFE),
9285 BLOGE(
sc,
"Failed to allocate INTx interrupt (%d)\n", rc);
9286 goto bxe_interrupt_attach_exit;
9290bxe_interrupt_attach_exit:
9371 if (!(len % 4) && !(
addr % 4)) {
9372 for (i = 0; i < len; i += 4) {
9376 for (i = 0; i < len; i++) {
9386 uint32_t *sb_data_p,
9391 for (index = 0; index < data_size; index++) {
9395 (
sizeof(uint32_t) * index)),
9396 *(sb_data_p + index));
9406 uint32_t *sb_data_p;
9407 uint32_t data_size = 0;
9413 sb_data_p = (uint32_t *)&sb_data_e2;
9420 sb_data_p = (uint32_t *)&sb_data_e1x;
9445 (i *
sizeof(uint32_t))),
9446 *((uint32_t *)sp_sb_data + i));
9458 sp_sb_data.
p_func.vf_valid = FALSE;
9477 hc_sm->igu_sb_id = igu_sb_id;
9478 hc_sm->igu_seg_id = igu_seg_id;
9479 hc_sm->timer_value = 0xFF;
9501 (
SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9505 (
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9507 (
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9509 (
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9511 (
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9525 uint32_t *sb_data_p;
9544 sb_data_e2.
common.same_igu_sb_1b = TRUE;
9548 sb_data_p = (uint32_t *)&sb_data_e2;
9559 sb_data_e1x.
common.same_igu_sb_1b = TRUE;
9563 sb_data_p = (uint32_t *)&sb_data_e1x;
9578static inline uint8_t
9588static inline uint32_t
9609 unsigned long q_type = 0;
9642 for (cos = 0; cos <
sc->
max_cos; cos++) {
9699 rx_prods.bd_prod = rx_bd_prod;
9700 rx_prods.cqe_prod = rx_cq_prod;
9701 rx_prods.sge_prod = rx_sge_prod;
9713 for (i = 0; i < (
sizeof(rx_prods) / 4); i++) {
9716 ((uint32_t *)&rx_prods)[i]);
9722 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
9723 fp->
index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
9793 int igu_sp_sb_index;
9797 int reg_offset, reg_offset_en5;
9813 section = ((uint64_t)mapping +
9818 reg_offset = (port) ?
9821 reg_offset_en5 = (port) ?
9827 for (sindex = 0; sindex < 4; sindex++) {
9829 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
9839 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
9846 reg_offset = (port) ?
9856 section = ((uint64_t)mapping +
9865 sp_sb_data.igu_sb_id = igu_sp_sb_index;
9866 sp_sb_data.igu_seg_id = igu_seg_id;
9867 sp_sb_data.
p_func.pf_id = func;
9869 sp_sb_data.
p_func.vf_id = 0xff;
9937 switch (load_code) {
9952 BLOGE(sc,
"Unknown load_code (0x%x) from MCP\n", load_code);
10009 uint32_t vn_min_rate;
10021 }
else if (!vn_min_rate) {
10035 }
else if (all_zero) {
10038 "Fariness disabled (all MIN values are zeroes)\n");
10044static inline uint16_t
10052 BLOGD(sc,
DBG_LOAD,
"Max BW configured to 0 - using 100 instead\n");
10064 uint16_t vn_max_rate;
10078 vn_max_rate = (max_cfg * 100);
10082 BLOGD(sc,
DBG_LOAD,
"vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10123 BLOGD(sc,
DBG_LOAD,
"rate shaping and fairness have been disabled\n");
10232 eq_data.producer = sc->
eq_prod;
10258 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10274 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10282 BLOGD(sc,
DBG_INTR,
"write %x to HC %d (addr 0x%x) mode %s\n",
10283 val, port,
addr, ((msix) ?
"MSI-X" : ((msi) ?
"MSI" :
"INTx")));
10293 val = (0xee0f | (1 << (
SC_VN(sc) + 4)));
10330 val &= ~IGU_PF_CONF_INT_LINE_EN;
10335 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10342 if ((!msix) || single_msix) {
10350 val, ((msix) ?
"MSI-X" : ((msi) ?
"MSI" :
"INTx")));
10358 val = (0xee0f | (1 << (
SC_VN(sc) + 4)));
10420 BLOGE(sc,
"proper val not read from HC IGU!\n");
10440 BLOGE(sc,
"proper val not read from IGU!\n");
10519 BXE_SP(sc, mcast_rdata),
10591 BLOGW(sc,
"No power capability\n");
10595 pmcsr = pci_read_config(sc->
dev,
10601 pci_write_config(sc->
dev,
10603 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
10605 if (pmcsr & PCIM_PSTAT_DMASK) {
10620 pmcsr &= ~PCIM_PSTAT_DMASK;
10621 pmcsr |= PCIM_PSTAT_D3;
10624 pmcsr |= PCIM_PSTAT_PMEENABLE;
10627 pci_write_config(sc->
dev,
10638 BLOGE(sc,
"Can't support PCI power state = 0x%x pmcsr 0x%x\n",
10652 uint32_t lock_status;
10653 uint32_t resource_bit = (1 << resource);
10655 uint32_t hw_lock_control_reg;
10657 BLOGD(sc,
DBG_LOAD,
"Trying to take a resource lock 0x%x\n", resource);
10662 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
10674 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
10675 lock_status =
REG_RD(sc, hw_lock_control_reg);
10676 if (lock_status & resource_bit) {
10680 BLOGE(sc,
"Failed to get a resource lock 0x%x func %d "
10681 "lock_status 0x%x resource_bit 0x%x\n", resource, func,
10682 lock_status, resource_bit);
10752 close ?
"closing" :
"opening");
10761 uint32_t cnt = 1000;
10762 uint32_t pend_bits = 0;
10767 if (pend_bits == 0) {
10772 }
while (--cnt > 0);
10775 BLOGE(sc,
"Still pending IGU requests bits=0x%08x!\n", pend_bits);
10782#define SHARED_MF_CLP_MAGIC 0x80000000
10786 uint32_t *magic_val)
10789 uint32_t val =
MFCFG_RD(sc, shared_mf_config.clp_mb);
10797 uint32_t magic_val)
10800 uint32_t val =
MFCFG_RD(sc, shared_mf_config.clp_mb);
10801 MFCFG_WR(sc, shared_mf_config.clp_mb,
10808 uint32_t *magic_val)
10811 uint32_t validity_offset;
10825 REG_WR(sc, shmem + validity_offset, 0);
10829#define MCP_TIMEOUT 5000
10830#define MCP_ONE_TIMEOUT 100
10865 BLOGE(sc,
"BAD MCP validity signature\n");
10872 uint32_t magic_val)
10907 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
10908 uint32_t global_bits2, stay_reset2;
10956 reset_mask1 = 0xffffffff;
10959 reset_mask2 = 0xffff;
10961 reset_mask2 = 0x1ffff;
10963 reset_mask2 = 0xfffff;
10965 reset_mask2 = 0x3ffffff;
10969 reset_mask2 &= ~global_bits2;
10986 reset_mask2 & (~not_reset_mask2));
10989 reset_mask1 & (~not_reset_mask1));
10995 reset_mask2 & (~stay_reset2));
11010 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
11011 uint32_t tags_63_32 = 0;
11024 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11025 ((port_is_idle_0 & 0x1) == 0x1) &&
11026 ((port_is_idle_1 & 0x1) == 0x1) &&
11027 (pgl_exp_rom2 == 0xffffffff) &&
11028 (!
CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11031 }
while (cnt-- > 0);
11034 BLOGE(sc,
"ERROR: Tetris buffer didn't get empty or there "
11035 "are still outstanding read requests after 1s! "
11036 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11037 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11038 sr_cnt, blk_cnt, port_is_idle_0,
11039 port_is_idle_1, pgl_exp_rom2);
11110 uint32_t load_code;
11120 BLOGE(sc,
"MCP response failure, aborting\n");
11122 goto exit_leader_reset;
11127 BLOGE(sc,
"MCP unexpected response, aborting\n");
11129 goto exit_leader_reset2;
11134 BLOGE(sc,
"MCP response failure, aborting\n");
11136 goto exit_leader_reset2;
11142 BLOGE(sc,
"Something bad occurred on engine %d!\n",
SC_PATH(sc));
11144 goto exit_leader_reset2;
11184 int cxt_index, cxt_offset;
11208 BLOGD(sc,
DBG_LOAD,
"fp %d setting queue params max cos to %d\n",
11222static unsigned long
11225 uint8_t zero_stats)
11227 unsigned long flags = 0;
11256static unsigned long
11261 unsigned long flags = 0;
11267 if (if_getcapenable(sc->
ifp) & IFCAP_LRO) {
11291 gen_init->
mtu = sc->
mtu;
11292 gen_init->
cos = cos;
11301 uint8_t max_sge = 0;
11302 uint16_t sge_sz = 0;
11303 uint16_t tpa_agg_size = 0;
11312 BLOGW(sc,
"sge ring threshold limit\n");
11316 tpa_agg_size = (2 * sc->
mtu);
11317 if (tpa_agg_size < sc->max_aggregation_size) {
11324 sge_sz = (uint16_t)min(
SGE_PAGES, 0xffff);
11338 BLOGW(sc,
"rx bd ring threshold limit\n");
11344 BLOGW(sc,
"rcq ring threshold limit\n");
11449 BLOGE(sc,
"Queue(%d) INIT failed rc = %d\n", fp->
index, rc);
11456 memset(setup_params, 0,
sizeof(*setup_params));
11479 BLOGE(sc,
"Queue(%d) SETUP failed (rc = %d)\n", fp->
index, rc);
11495 uint8_t config_hash)
11530 for (i = 0; i <
sizeof(params.
rss_key) / 4; i++) {
11531 params.
rss_key[i] = arc4random();
11542 uint8_t config_hash)
11559 (sc->
fp->
cl_id + (i % num_eth_queues));
11587 memset(&ramrod_param, 0,
sizeof(ramrod_param));
11607 BLOGD(sc,
DBG_SP,
"Failed to schedule ADD operations (EEXIST)\n");
11610 }
else if (rc < 0) {
11611 BLOGE(sc,
"%s MAC failed (%d)\n", (set ?
"Set" :
"Delete"), rc);
11636 uint32_t sel_phy_idx = 0;
11663 return (sel_phy_idx);
11739 line_speed = (line_speed * maxCfg) / 100;
11741 uint16_t vn_max_rate = maxCfg * 100;
11743 if (vn_max_rate < line_speed) {
11744 line_speed = vn_max_rate;
11749 return (line_speed);
11758 memset(data, 0,
sizeof(*data));
11807 ELINK_DEBUG_P2(sc,
"Change in link status : cur_data = %x, last_reported_link = %x\n",
11817 if_link_state_change(sc->
ifp, LINK_STATE_DOWN);
11819 const char *duplex;
11841 flow =
"ON - receive & transmit";
11846 flow =
"ON - receive";
11851 flow =
"ON - transmit";
11859 if_link_state_change(sc->
ifp, LINK_STATE_UP);
11860 BLOGI(sc,
"NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
11958 }
else if (bond & 0x4) {
11964 }
else if (bond & 0x8) {
12024 mc_mac->
mac = (uint8_t *)LLADDR(sdl);
12033 if_t ifp = sc->
ifp;
12041 mc_count = if_llmaddr_count(ifp);
12047 mc_mac = malloc(
sizeof(*mc_mac) * mc_count, M_DEVBUF,
12048 (M_NOWAIT | M_ZERO));
12050 BLOGE(sc,
"Failed to allocate temp mcast list\n");
12053 bzero(mc_mac, (
sizeof(*mc_mac) * mc_count));
12056 for (
int i = 0; i < mc_count; i ++) {
12059 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X and mc_count %d\n",
12060 mc_mac[i].
mac[0], mc_mac[i].
mac[1], mc_mac[i].
mac[2],
12061 mc_mac[i].
mac[3], mc_mac[i].
mac[4], mc_mac[i].
mac[5],
12080 free(mc_mac, M_DEVBUF);
12096 BLOGE(sc,
"Failed to clear multicast configuration: %d\n", rc);
12105 BLOGE(sc,
"Failed to create mcast MACs list (%d)\n", rc);
12113 BLOGE(sc,
"Failed to set new mcast config (%d)\n", rc);
12144 BLOGD(ctx->
sc,
DBG_SP,
"Failed to schedule ADD operations (EEXIST)\n");
12146 BLOGE(ctx->
sc,
"Failed to schedule ADD operations (%d)\n", rc);
12156 if_t ifp = sc->
ifp;
12164 BLOGE(
sc,
"Failed to schedule delete of all ETH MACs (%d)\n",
rc);
12181 if_t ifp =
sc->
ifp;
12191 if (if_getflags(ifp) & IFF_PROMISC) {
12193 }
else if ((if_getflags(ifp) & IFF_ALLMULTI) ||
12230 uint32_t drv_flags;
12272 BLOGW(sc,
"periodic callout exit (state=0x%x)\n", sc->
state);
12302 uint32_t drv_pulse;
12303 uint32_t mcp_pulse;
12311 mcp_pulse = (
SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12318 if ((drv_pulse != mcp_pulse) &&
12321 BLOGE(sc,
"drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12322 drv_pulse, mcp_pulse);
12356 uint8_t global = FALSE;
12357 uint32_t error_recovered, error_unrecovered;
12363 BLOGE(sc,
"RECOVERY failed, "
12364 "stack notified driver is NOT running! "
12365 "Please reboot/power cycle the system.\n");
12371 "%s sc=%p state=0x%x rec_state=0x%x error_status=%x\n",
12384 if (if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING) {
12390 BLOGE(sc,
" No Recovery tried for error 0x%x"
12391 " stack notified driver is NOT running!"
12392 " Please reboot/power cycle the system.\n",
12416 if (if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING) {
12435 int other_engine =
SC_PATH(sc) ? 0 : 1;
12436 bool other_load_status =
12451 (global && other_load_status)) {
12456 taskqueue_enqueue_timeout(taskqueue_thread,
12467 BLOGE(sc,
"RECOVERY failed, "
12468 "stack notified driver is NOT running!\n");
12502 taskqueue_enqueue_timeout(taskqueue_thread,
12512 taskqueue_enqueue_timeout(taskqueue_thread,
12519 error_unrecovered =
12525 error_unrecovered++;
12528 BLOGE(sc,
"Recovery is NOT successfull, "
12529 " state=0x%x recovery_state=0x%x error=%x\n",
12536 BLOGI(sc,
"Recovery is successfull from errors %x,"
12569 if_link_state_change(sc->
ifp, LINK_STATE_DOWN);
12572 BLOGI(sc,
"bxe%d: Recovery started errors 0x%x recovery state 0x%x\n",
12585 "%s state = 0x%x rec state=0x%x error_status=%x\n",
12607static __noinline
int
12631 BLOGE(sc,
"Failed to allocate fastpath memory\n");
12634 goto bxe_nic_load_error0;
12640 goto bxe_nic_load_error0;
12646 goto bxe_nic_load_error0;
12659 goto bxe_nic_load_error1;
12667 goto bxe_nic_load_error2;
12670 BLOGI(sc,
"Device has no MCP!\n");
12682 BLOGE(sc,
"HW init failed\n");
12686 goto bxe_nic_load_error2;
12699 goto bxe_nic_load_error2;
12716 BLOGE(sc,
"Function start failed! rc = %d\n", rc);
12719 goto bxe_nic_load_error3;
12726 BLOGE(sc,
"MCP response failure, aborting\n");
12729 goto bxe_nic_load_error3;
12735 BLOGE(sc,
"Setup leading failed! rc = %d\n", rc);
12737 goto bxe_nic_load_error3;
12743 BLOGE(sc,
"Queue(%d) setup failed rc = %d\n", i, rc);
12745 goto bxe_nic_load_error3;
12751 BLOGE(sc,
"PF RSS init failed\n");
12753 goto bxe_nic_load_error3;
12766 BLOGE(sc,
"Setting Ethernet MAC failed rc = %d\n", rc);
12768 goto bxe_nic_load_error3;
12775 goto bxe_nic_load_error3;
12780 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
12822 BLOGE(sc,
"Timeout waiting for all SPs to complete!\n");
12829 if_setdrvflags(sc->
ifp, IFF_DRV_RUNNING);
12835bxe_nic_load_error3:
12846bxe_nic_load_error2:
12855bxe_nic_load_error1:
12862bxe_nic_load_error0:
12874 int other_engine =
SC_PATH(sc) ? 0 : 1;
12875 uint8_t other_load_status, load_status;
12876 uint8_t global = FALSE;
12882 if (if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING) {
12883 BLOGD(sc,
DBG_LOAD,
"Init called while driver is running!\n");
12889 BLOGE(sc,
"Initialization not done, "
12890 "as previous recovery failed."
12891 "Reboot/Power-cycle the system\n" );
12925 if ((!load_status && (!global || !other_load_status)) &&
12927 BLOGI(sc,
"Recovered during init\n");
12935 BLOGE(sc,
"Recovery flow hasn't properly "
12936 "completed yet, try again later. "
12937 "If you still see this message after a "
12938 "few retries then power cycle is required.\n");
12941 goto bxe_init_locked_done;
12950bxe_init_locked_done:
12954 BLOGE(sc,
"Initialization failed, "
12955 "stack notified driver is NOT running!\n");
12956 if_setdrvflagbits(sc->
ifp, 0, IFF_DRV_RUNNING);
12993 ifmedia_init(&sc->
ifmedia, IFM_IMASK,
12998 ifmedia_add(&sc->
ifmedia, (IFM_ETHER | IFM_FDX | sc->
media), 0, NULL);
12999 ifmedia_add(&sc->
ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
13000 ifmedia_set(&sc->
ifmedia, (IFM_ETHER | IFM_AUTO));
13003 BLOGI(sc,
"IFMEDIA flags : %x\n", sc->
ifmedia.ifm_media);
13006 if ((
ifp = if_gethandle(IFT_ETHER)) == NULL) {
13007 BLOGE(sc,
"Interface allocation failed!\n");
13011 if_setsoftc(
ifp, sc);
13012 if_initname(
ifp, device_get_name(sc->
dev), device_get_unit(sc->
dev));
13013 if_setflags(
ifp, (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST));
13020 if_setmtu(
ifp, sc->
mtu);
13021 if_sethwassist(
ifp, (CSUM_IP |
13030 IFCAP_VLAN_HWTAGGING |
13032 IFCAP_VLAN_HWFILTER |
13033 IFCAP_VLAN_HWCSUM |
13040 if_setcapabilitiesbit(
ifp, capabilities, 0);
13041 if_setcapenable(
ifp, if_getcapabilities(
ifp));
13042 if_setbaudrate(
ifp, IF_Gbps(10));
13045 if_setsendqready(
ifp);
13054 DEBUGNET_SET(
ifp, bxe);
13066 bus_release_resource(sc->
dev,
13082 memset(sc->
bar, 0,
sizeof(sc->
bar));
13088 if ((i != 0) && (i != 2) && (i != 4)) {
13092 sc->
bar[i].
rid = PCIR_BAR(i);
13096 flags |= RF_SHAREABLE;
13100 bus_alloc_resource_any(sc->
dev,
13111 BLOGI(sc,
"PCI BAR%d [%02x] memory allocated: %#jx-%#jx (%jd) -> %#jx\n",
13116 (uintmax_t)sc->
bar[i].
kva);
13148 "Relative function %d, Absolute function %d, Path %d\n",
13155 uint32_t shmem2_size;
13157 uint32_t mf_cfg_offset_value;
13166 if (shmem2_size > offsetof(
struct shmem2_region, mf_cfg_addr)) {
13167 mf_cfg_offset_value =
SHMEM2_RD(sc, mf_cfg_addr);
13169 offset = mf_cfg_offset_value;
13185 if (pci_find_cap(sc->
dev, PCIY_EXPRESS, &pcie_reg) == 0) {
13186 if (pcie_reg != 0) {
13187 BLOGD(sc,
DBG_LOAD,
"PCIe capability at 0x%04x\n", pcie_reg);
13188 return (pci_read_config(sc->
dev, (pcie_reg + reg), width));
13192 BLOGE(sc,
"PCIe capability NOT FOUND!!!\n");
13201 PCIEM_STA_TRANSACTION_PND);
13212 uint16_t link_status;
13216 if (pci_find_cap(sc->
dev, PCIY_PMG, ®) == 0) {
13218 BLOGD(sc,
DBG_LOAD,
"Found PM capability at 0x%04x\n", reg);
13231 (
REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
13235 ((link_status & PCIEM_LINK_STA_WIDTH) >> 4);
13238 ((link_status & PCIEM_LINK_STA_WIDTH) >> 4) >> 1;
13242 (link_status & PCIEM_LINK_STA_SPEED);
13244 ((link_status & PCIEM_LINK_STA_WIDTH) >> 4);
13254 if (pci_find_cap(sc->
dev, PCIY_MSI, ®) == 0) {
13256 BLOGD(sc,
DBG_LOAD,
"Found MSI capability at 0x%04x\n", reg);
13264 if (pci_find_cap(sc->
dev, PCIY_MSIX, ®) == 0) {
13266 BLOGD(sc,
DBG_LOAD,
"Found MSI-X capability at 0x%04x\n", reg);
13283 mf_info->
ext_id = (uint16_t)val;
13288 BLOGE(sc,
"Invalid VLAN (%d)\n", mf_info->
ext_id);
13312 uint32_t retval = 0;
13359 uint32_t e1hov_tag;
13360 uint32_t func_config;
13361 uint32_t niv_config;
13411 BLOGD(sc,
DBG_LOAD,
"MF config parameters for function %d\n",
13433 BLOGE(sc,
"Enumerated function %d is marked as hidden\n",
13439 BLOGE(sc,
"vnics_per_port=%d multi_vnics_mode=%d\n",
13447 BLOGE(sc,
"mf_mode=SD vnic_id=%d ovlan=%d\n",
13453 BLOGE(sc,
"mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13464 mf_cfg1 =
MFCFG_RD(sc, func_mf_config[i].config);
13465 ovlan1 =
MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13469 BLOGE(sc,
"mf_mode=SD function %d MF config "
13470 "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13478 mf_cfg1 =
MFCFG_RD(sc, func_mf_config[i].config);
13479 ovlan1 =
MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13482 mf_cfg2 =
MFCFG_RD(sc, func_mf_config[j].config);
13483 ovlan2 =
MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13488 (ovlan1 == ovlan2)) {
13489 BLOGE(sc,
"mf_mode=SD functions %d and %d "
13490 "have the same ovlan (%d)\n",
13505 uint32_t val, mac_upper;
13519 BLOGE(sc,
"Invalid mf_cfg_base!\n");
13525 val =
SHMEM_RD(sc, dev_info.shared_feature_config.config);
13537 BLOGE(sc,
"Invalid config for Switch Independent mode\n");
13552 BLOGE(sc,
"Invalid config for Switch Dependent mode\n");
13570 if ((
SHMEM2_HAS(sc, afex_driver_support)) &&
13574 BLOGE(sc,
"Invalid config for AFEX mode\n");
13581 BLOGE(sc,
"Unknown MF mode (0x%08x)\n",
13597 uint8_t other_port = !(
PORT_ID(sc) & 1);
13598 uint8_t abs_func_other_port = (
SC_PATH(sc) + (2 * other_port));
13600 val =
MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13608 if (
SC_VN(sc) >= 1) {
13609 BLOGE(sc,
"VNIC ID >= 1 in SF mode\n");
13639 BLOGE(sc,
"Get MF config failed (mf_mode=0x%08x)\n",
13649 val =
MFCFG_RD(sc, func_mf_config[i].config);
13664 uint32_t mac_hi, mac_lo, val;
13667 mac_hi = mac_lo = 0;
13674 SHMEM_RD(sc, dev_info.shared_hw_config.config);
13676 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13684 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
13688 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13690 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13694 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13697 val =
SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13701 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13704 val =
SHMEM_RD(sc, dev_info.shared_feature_config.config);
13710 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13715 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
13719 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
13729 mac_hi =
SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
13730 mac_lo =
SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
13733 if ((mac_lo == 0) && (mac_hi == 0)) {
13735 BLOGE(sc,
"No Ethernet address programmed!\n");
13744 "%02x:%02x:%02x:%02x:%02x:%02x",
13795 BLOGW(sc,
"invalid max_aggregation_size (%d)\n",
13840 "interrupt_mode=%d "
13845 "max_aggregation_size=%d "
13870 BLOGI(sc,
"Found 10Gb Fiber media.\n");
13871 sc->
media = IFM_10G_SR;
13875 BLOGI(sc,
"Found 1Gb Fiber media.\n");
13876 sc->
media = IFM_1000_SX;
13881 BLOGI(sc,
"Found 10GBase-CX4 media.\n");
13882 sc->
media = IFM_10G_CX4;
13886 BLOGI(sc,
"Found 10Gb Twinax media.\n");
13887 sc->
media = IFM_10G_TWINAX;
13893 BLOGI(sc,
"Found 10GBase-T media.\n");
13894 sc->
media = IFM_10G_T;
13897 BLOGI(sc,
"Found 1000Base-T media.\n");
13898 sc->
media = IFM_1000_T;
13903 BLOGI(sc,
"Media not present.\n");
13909 BLOGI(sc,
"Unknown media!\n");
13917#define GET_FIELD(value, fname) \
13918 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
13919#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
13920#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
13928 uint8_t fid, igu_sb_cnt = 0;
13933 int vn =
SC_VN(sc);
13943 for (igu_sb_id = 0;
13975 if (igu_sb_cnt == 0) {
13976 BLOGE(sc,
"CAM configuration error\n");
14020 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
14027 val = (
REG_RD(sc, 0x2874) & 0x55);
14048 val = ((val >> 1) & 1);
14056 BLOGD(sc,
DBG_LOAD,
"Port mode = %s\n", (val) ?
"4" :
"2");
14070 BLOGD(sc,
DBG_LOAD,
"shmem_base=0x%08x, shmem2_base=0x%08x\n",
14075 BLOGI(sc,
"MCP not active\n");
14084 BLOGE(sc,
"Invalid SHMEM validity signature: 0x%08x\n", val);
14087 BLOGD(sc,
DBG_LOAD,
"Valid SHMEM validity signature: 0x%08x\n", val);
14142 val = pci_read_config(sc->
dev,
14146 sc->
igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
14181 BLOGD(sc,
DBG_LOAD,
"FORCING IGU Normal Mode failed!!!\n");
14220 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
14231 uint32_t switch_cfg)
14233 uint32_t cfg_size = 0;
14268 BLOGE(sc,
"Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14270 dev_info.port_hw_config[port].external_phy_config),
14272 dev_info.port_hw_config[port].external_phy_config2));
14279 switch (switch_cfg) {
14289 BLOGE(sc,
"Invalid switch config in link_config=0x%08x\n",
14298 for (idx = 0; idx < cfg_size; idx++) {
14321 sc->
port.
supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14326 sc->
port.
supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14331 sc->
port.
supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14336 sc->
port.
supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14349 uint32_t link_config;
14351 uint32_t cfg_size = 0;
14366 for (idx = 0; idx < cfg_size; idx++) {
14395 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14396 "speed_cap_mask=0x%08x\n",
14408 ELINK_DEBUG_P1(sc,
"driver requesting DUPLEX_HALF req_duplex = %x!\n",
14411 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14412 "speed_cap_mask=0x%08x\n",
14424 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14425 "speed_cap_mask=0x%08x\n",
14438 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14439 "speed_cap_mask=0x%08x\n",
14451 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14452 "speed_cap_mask=0x%08x\n",
14464 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14465 "speed_cap_mask=0x%08x\n",
14477 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14478 "speed_cap_mask=0x%08x\n",
14489 BLOGE(sc,
"Invalid NVRAM config link_config=0x%08x "
14490 "speed_cap_mask=0x%08x\n",
14509 "req_flow_ctrl=0x%x advertising=0x%x\n",
14515 "advertising=0x%x\n",
14532 "link_config0=0x%08x\n",
14546 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14554 (((
SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14587 uint32_t
flags = 0;
14631#if defined(__LITTLE_ENDIAN)
14644 bus_addr_t busaddr;
14645 int max_agg_queues;
14647 bus_size_t max_size;
14648 bus_size_t max_seg_size;
14656 rc = bus_dma_tag_create(bus_get_dma_tag(
sc->
dev),
14663 BUS_SPACE_MAXSIZE_32BIT,
14664 BUS_SPACE_UNRESTRICTED,
14665 BUS_SPACE_MAXSIZE_32BIT,
14671 BLOGE(
sc,
"Failed to alloc parent DMA tag (%d)!\n", rc);
14693 &sc->
eq_dma,
"event queue") != 0) {
14708 &sc->
sp_dma,
"slow path") != 0) {
14725 &sc->
spq_dma,
"slow path queue") != 0) {
14744 "fw decompression buffer") != 0) {
14761 malloc(
sizeof(*sc->
gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
14791 snprintf(buf,
sizeof(buf),
"fp %d status block", i);
14793 &fp->
sb_dma, buf) != 0) {
14795 BLOGE(sc,
"Failed to alloc %s\n", buf);
14811 snprintf(buf,
sizeof(buf),
"fp %d tx bd chain", i);
14813 &fp->
tx_dma, buf) != 0) {
14815 BLOGE(sc,
"Failed to alloc %s\n", buf);
14837 snprintf(buf,
sizeof(buf),
"fp %d rx bd chain", i);
14839 &fp->
rx_dma, buf) != 0) {
14841 BLOGE(sc,
"Failed to alloc %s\n", buf);
14863 snprintf(buf,
sizeof(buf),
"fp %d rcq chain", i);
14867 BLOGE(sc,
"Failed to alloc %s\n", buf);
14890 snprintf(buf,
sizeof(buf),
"fp %d sge chain", i);
14894 BLOGE(sc,
"Failed to alloc %s\n", buf);
14917 if (if_getcapenable(sc->
ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) {
14924 max_seg_size = MCLBYTES;
14944 BLOGE(sc,
"Failed to create dma tag for "
14945 "'fp %d tx mbufs' (%d)\n", i, rc);
14955 BLOGE(sc,
"Failed to create dma map for "
14956 "'fp %d tx mbuf %d' (%d)\n", i, j, rc);
14982 BLOGE(sc,
"Failed to create dma tag for "
14983 "'fp %d rx mbufs' (%d)\n", i, rc);
14993 BLOGE(sc,
"Failed to create dma map for "
14994 "'fp %d rx mbuf %d' (%d)\n", i, j, rc);
15004 BLOGE(sc,
"Failed to create dma map for "
15005 "'fp %d spare rx mbuf' (%d)\n", i, rc);
15030 BLOGE(sc,
"Failed to create dma tag for "
15031 "'fp %d rx sge mbufs' (%d)\n", i, rc);
15041 BLOGE(sc,
"Failed to create dma map for "
15042 "'fp %d rx sge mbuf %d' (%d)\n", i, j, rc);
15052 BLOGE(sc,
"Failed to create dma map for "
15053 "'fp %d spare rx sge mbuf' (%d)\n", i, rc);
15064 for (j = 0; j < max_agg_queues; j++) {
15069 BLOGE(sc,
"Failed to create dma map for "
15070 "'fp %d rx tpa mbuf %d' (%d)\n", i, j, rc);
15080 BLOGE(sc,
"Failed to create dma map for "
15081 "'fp %d spare rx tpa mbuf' (%d)\n", i, rc);
15095 int max_agg_queues;
15183 for (j = 0; j < max_agg_queues; j++) {
15286 "Clearing 'was-error' bit that was set in pglueb");
15298 BLOGE(
sc,
"MCP response failure, aborting\n");
15310 LIST_FOREACH(tmp, &bxe_prev_list, node) {
15313 (
SC_PATH(sc) == tmp->path)) {
15333 "Path %d/%d/%d was marked by AER\n",
15338 "Path %d/%d/%d was already cleaned from previous drivers\n",
15350 uint8_t after_undi)
15361 "Re-marking AER in path %d/%d/%d\n",
15365 "Removing AER indication from path %d/%d/%d\n",
15378 (M_NOWAIT | M_ZERO));
15380 BLOGE(sc,
"Failed to allocate 'bxe_prev_list_node'\n");
15388 tmp->undi = after_undi ? (1 <<
SC_PORT(sc)) : 0;
15393 "Marked path %d/%d/%d - finished previous unload\n",
15395 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15415 BLOGD(sc,
DBG_LOAD,
"FLR not supported by BC_VER: 0x%08x\n",
15421 for (i = 0; i < 4; i++) {
15423 DELAY(((1 << (i - 1)) * 100) * 1000);
15431 BLOGE(sc,
"PCIE transaction is not cleared, "
15432 "proceeding with reset anyway\n");
15457 uint32_t val, base_addr,
offset, mask, reset_reg;
15458 uint8_t mac_stopped = FALSE;
15460 uint32_t wb_data[2];
15473 if ((mask & reset_reg) && val) {
15491 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15500 mac_stopped = TRUE;
15511 mac_stopped = TRUE;
15515 if (mask & reset_reg) {
15521 mac_stopped = TRUE;
15530#define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15531#define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff)
15532#define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
15533#define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15550 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15557 uint32_t reset_reg, tmp_reg = 0, rc;
15558 uint8_t prev_undi = FALSE;
15560 uint32_t timer_count = 1000;
15570 memset(&mac_vals, 0,
sizeof(mac_vals));
15592 if (tmp_reg == 0x7) {
15604 while (timer_count) {
15605 prev_brb = tmp_reg;
15615 if (prev_brb > tmp_reg) {
15616 timer_count = 1000;
15629 if (!timer_count) {
15630 BLOGE(sc,
"Failed to empty BRB\n");
15682 BLOGD(sc,
DBG_LOAD,
"FW version matches our own, attempting FLR\n");
15706 int time_counter = 10;
15707 uint32_t fw, hw_lock_reg, hw_lock_val;
15722 hw_lock_val = (
REG_RD(sc, hw_lock_reg));
15725 BLOGD(sc,
DBG_LOAD,
"Releasing previously held NVRAM lock\n");
15729 BLOGD(sc,
DBG_LOAD,
"Releasing previously held HW lock\n");
15730 REG_WR(sc, hw_lock_reg, 0xffffffff);
15732 BLOGD(sc,
DBG_LOAD,
"No need to release HW/NVRAM locks\n");
15744 BLOGE(sc,
"MCP response failure, aborting\n");
15761 }
while (--time_counter);
15763 if (!time_counter || rc) {
15764 BLOGE(sc,
"Failed to unload previous driver!"
15765 " time_counter %d rc %d\n", time_counter, rc);
15775 uint32_t dcbx_enabled)
15785 "DCB state [%s:%s]\n",
15786 dcb_on ?
"ON" :
"OFF",
15790 "on-chip with negotiation" :
"invalid");
15815 uint32_t pri_map = 0;
15818 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
15819 if (cos < sc->max_cos) {
15822 BLOGW(sc,
"Invalid COS %d for priority %d "
15823 "(max COS is %d), setting to 0\n",
15824 cos, pri, (sc->
max_cos - 1));
15837 error = sysctl_handle_int(oidp, &result, 0, req);
15839 if (error || !req->newptr) {
15847 BLOGI(sc,
"... dumping driver state ...\n");
15848 temp =
SHMEM2_RD(sc, temperature_in_half_celsius);
15849 BLOGI(sc,
"\t Device Temperature = %d Celsius\n", (temp/2));
15861 uint64_t value = 0;
15862 int index = (
int)arg2;
15865 BLOGE(sc,
"bxe_eth_stats index out of range (%d)\n", index);
15873 value = (uint64_t)*
offset;
15879 BLOGE(sc,
"Invalid bxe_eth_stats size (index=%d size=%d)\n",
15893 uint64_t value = 0;
15894 uint32_t q_stat = (uint32_t)arg2;
15895 uint32_t fp_index = ((q_stat >> 16) & 0xffff);
15896 uint32_t index = (q_stat & 0xffff);
15901 BLOGE(sc,
"bxe_eth_q_stats index out of range (%d)\n", index);
15909 value = (uint64_t)*
offset;
15915 BLOGE(sc,
"Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
15943 if (error || !req->newptr) {
15970 if(result & 0x400) {
15988 if (if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING) {
16006 struct sysctl_ctx_list *ctx;
16007 struct sysctl_oid_list *children;
16008 struct sysctl_oid *queue_top, *queue;
16009 struct sysctl_oid_list *queue_top_children, *queue_children;
16010 char queue_num_buf[32];
16014 ctx = device_get_sysctl_ctx(sc->
dev);
16015 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->
dev));
16017 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
"version",
16033 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
"mf_vnics",
16035 "multifunction vnics per port");
16046 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
"bc_version",
16048 "bootcode version");
16049 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
"fw_version",
16051 "firmware version");
16052 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
"mf_mode",
16054 "multifunction mode");
16055 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
"mac_addr",
16058 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
"pci_link",
16060 "pci link status");
16061 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
"debug",
16062 CTLFLAG_RW, &sc->
debug,
16063 "debug logging mode");
16066 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
"trigger_grcdump",
16068 "trigger grcdump should be invoked"
16069 " before collecting grcdump");
16073 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
"grcdump_done",
16075 "set by driver when grcdump is done");
16078 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
"rx_budget",
16080 "rx processing budget");
16082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
"pause_param",
16083 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
16085 "need pause frames- DEF:0/TX:1/RX:2/BOTH:3/AUTO:4/AUTOTX:5/AUTORX:6/AUTORXTX:7/NONE:8");
16088 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
"state",
16089 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
16093 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
16095 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
16100 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO,
"queue",
16101 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
"queue");
16102 queue_top_children = SYSCTL_CHILDREN(queue_top);
16106 snprintf(queue_num_buf,
sizeof(queue_num_buf),
"%d", i);
16107 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
16108 queue_num_buf, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
"single queue");
16109 queue_children = SYSCTL_CHILDREN(queue);
16112 q_stat = ((i << 16) | j);
16113 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
16115 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, q_stat,
16133 if (fp->
tx_br == NULL)
16151 buf_ring_free(fp->
tx_br, M_DEVBUF);
16168 "bxe%d_fp%d_tx_lock",
sc->
unit, i);
16172 "bxe%d_fp%d_rx_lock",
sc->
unit, i);
16187 if (mtx_initialized(&fp->
tx_mtx)) {
16188 mtx_destroy(&fp->
tx_mtx);
16191 if (mtx_initialized(&fp->
rx_mtx)) {
16192 mtx_destroy(&fp->
rx_mtx);
16213 sc = device_get_softc(
dev);
16220 sc->
unit = device_get_unit(
dev);
16229 pci_enable_busmaster(
dev);
16245 "bxe%d_chip_tq", sc->
unit);
16248 taskqueue_thread_enqueue,
16250 taskqueue_start_threads(&sc->
chip_tq, 1, PWAIT,
16253 TIMEOUT_TASK_INIT(taskqueue_thread,
16259 BLOGE(sc,
"getting device info\n");
16261 pci_disable_busmaster(
dev);
16269 sc->
mtu = ETHERMTU;
16285 pci_disable_busmaster(
dev);
16290 if (sc->
ifp != NULL) {
16291 ether_ifdetach(sc->
ifp);
16293 ifmedia_removeall(&sc->
ifmedia);
16296 pci_disable_busmaster(
dev);
16303 if (sc->
ifp != NULL) {
16304 ether_ifdetach(sc->
ifp);
16306 ifmedia_removeall(&sc->
ifmedia);
16309 pci_disable_busmaster(
dev);
16319 if (sc->
ifp != NULL) {
16320 ether_ifdetach(sc->
ifp);
16322 ifmedia_removeall(&sc->
ifmedia);
16325 pci_disable_busmaster(
dev);
16334 if (sc->
ifp != NULL) {
16335 ether_ifdetach(sc->
ifp);
16337 ifmedia_removeall(&sc->
ifmedia);
16340 pci_disable_busmaster(
dev);
16350 if (sc->
ifp != NULL) {
16351 ether_ifdetach(sc->
ifp);
16353 ifmedia_removeall(&sc->
ifmedia);
16356 pci_disable_busmaster(
dev);
16374 if (
SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16375 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16376 SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16377 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16411 sc = device_get_softc(
dev);
16416 if (
ifp != NULL && if_vlantrunkinuse(
ifp)) {
16417 BLOGE(sc,
"Cannot detach while VLANs are in use.\n");
16432 taskqueue_drain_timeout(taskqueue_thread,
16446 ether_ifdetach(
ifp);
16448 ifmedia_removeall(&sc->
ifmedia);
16472 if (sc->
ifp != NULL) {
16476 pci_disable_busmaster(
dev);
16494 sc = device_get_softc(
dev);
16529 uint32_t data, ctl, cnt = 100;
16533 uint32_t sb_bit = 1 << (idu_sb_id%32);
16551 BLOGD(sc,
DBG_LOAD,
"write 0x%08x to IGU(via GRC) addr 0x%x\n",
16552 data, igu_addr_data);
16553 REG_WR(sc, igu_addr_data, data);
16556 BUS_SPACE_BARRIER_WRITE);
16559 BLOGD(sc,
DBG_LOAD,
"write 0x%08x to IGU(via GRC) addr 0x%x\n",
16560 ctl, igu_addr_ctl);
16561 REG_WR(sc, igu_addr_ctl, ctl);
16564 BUS_SPACE_BARRIER_WRITE);
16568 while (!(
REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16572 if (!(
REG_RD(sc, igu_addr_ack) & sb_bit)) {
16574 "Unable to finish IGU cleanup: "
16575 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16576 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16600 uint32_t val = 0x1400;
16616 uint32_t shmem_base[2];
16617 uint32_t shmem2_base[2];
16622 lfa_host_addr[
SC_PORT(sc)])) {
16630 shmem_base[1] =
SHMEM2_RD(sc, other_shmem_base_addr);
16631 shmem2_base[1] =
SHMEM2_RD(sc, other_shmem2_base_addr);
16645 val &= ~IGU_PF_CONF_FUNC_EN;
16656 int r_order, w_order;
16662 w_order = ((devctl & PCIEM_CTL_MAX_PAYLOAD) >> 5);
16664 if (sc->
mrrs == -1) {
16665 r_order = ((devctl & PCIEM_CTL_MAX_READ_REQUEST) >> 12);
16668 r_order = sc->
mrrs;
16690 uint16_t pretend_func_val)
16692 uint32_t pretend_reg;
16700 REG_WR(sc, pretend_reg, pretend_func_val);
16701 REG_RD(sc, pretend_reg);
16721 uint32_t wb_write[3];
16724 wb_write[0] = 0x55555555;
16725 wb_write[1] = 0x55555555;
16726 wb_write[2] = 0x20;
16730 wb_write[0] = 0x09000000;
16731 wb_write[1] = 0x55555555;
16732 wb_write[2] = 0x10;
16769 count = 1000 * factor;
16772 val = *
BXE_SP(sc, wb_data[0]);
16782 BLOGE(sc,
"NIG timeout val=0x%x\n", val);
16787 count = (1000 * factor);
16799 BLOGE(sc,
"PRS timeout val=0x%x\n", val);
16821 for (i = 0; i < 10; i++) {
16826 count = (1000 * factor);
16829 val = *
BXE_SP(sc, wb_data[0]);
16839 BLOGE(sc,
"NIG timeout val=0x%x\n", val);
16846 BLOGE(sc,
"PRS timeout val=0x%x\n", val);
16853 DELAY(10000 * factor);
16858 BLOGE(sc,
"PRS timeout val=0x%x\n", val);
16862 for (i = 0; i < 11; i++) {
16868 BLOGE(sc,
"clear of NIG failed val=0x%x\n", val);
16901 val = (
SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
16921 BLOGD(sc,
DBG_LOAD,
"fan detection setting: %d\n", is_required);
16923 if (is_required == 0) {
17013 uint8_t abs_func_id;
17049 for (abs_func_id =
SC_PATH(sc);
17051 abs_func_id += 2) {
17109 BLOGE(sc,
"PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n",
17115 BLOGE(sc,
"PXP2 RD_INIT failed val = 0x%x\n", val);
17194 memset(&ilt, 0,
sizeof(
struct ecore_ilt));
17237 }
while (factor-- && (val != 1));
17240 BLOGE(sc,
"ATC_INIT failed val = 0x%x\n", val);
17386 BLOGE(sc,
"please adjust the size of cdu_context(%ld)\n",
17391 val = (4 << 24) + (0 << 12) + 1024;
17412 REG_WR(sc, 0x2814, 0xffffffff);
17413 REG_WR(sc, 0x3820, 0xffffffff);
17449 BLOGE(sc,
"CFC LL_INIT failed val=0x%x\n", val);
17454 BLOGE(sc,
"CFC AC_INIT failed val=0x%x\n", val);
17459 BLOGE(sc,
"CFC CAM_INIT failed val=0x%x\n", val);
17467 val = *
BXE_SP(sc, wb_data[0]);
17471 BLOGE(sc,
"internal mem self test failed val=0x%x\n", val);
17507 BLOGE(sc,
"bxe_init_hw_common failed rc=%d\n", rc);
17524 uint32_t low, high;
17527 BLOGD(sc,
DBG_LOAD,
"starting port init for port %d\n", port);
17571 }
else if (sc->
mtu > 4096) {
17577 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17668 val =
IS_MF(sc) ? 0xF7 : 0x7;
17742 uint32_t poll_count)
17744 uint32_t cur_cnt = poll_count;
17747 while ((val =
REG_RD(sc, reg)) != expected && cur_cnt--) {
17763 BLOGE(sc,
"%s usage count=%d\n", msg, val);
17793 "CFC PF usage counter timed out",
17801 "DQ PF usage counter timed out",
17809 "QM PF usage counter timed out",
17817 "Timers VNIC usage counter timed out",
17824 "Timers NUM_SCANS usage counter timed out",
17832 "DMAE dommand register timed out",
17840#define OP_GEN_PARAM(param) \
17841 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17842#define OP_GEN_TYPE(type) \
17843 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17844#define OP_GEN_AGG_VECT(index) \
17845 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17849 uint8_t clnup_func,
17852 uint32_t op_gen_command = 0;
17857 if (
REG_RD(sc, comp_addr)) {
17858 BLOGE(sc,
"Cleanup complete was not 0 before sending\n");
17871 BLOGE(sc,
"FW final cleanup did not succeed\n");
17872 BLOGD(sc,
DBG_LOAD,
"At timeout completion address contained %x\n",
17873 (
REG_RD(sc, comp_addr)));
17874 bxe_panic(sc, (
"FLR cleanup failed\n"));
17879 REG_WR(sc, comp_addr, 0);
17887 uint32_t poll_count)
17889 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
17890 uint32_t cur_cnt = poll_count;
17893 crd = crd_start =
REG_RD(sc, regs->
crd);
17898 BLOGD(sc,
DBG_LOAD,
"CREDIT_FREED[%d]: s:%x\n", regs->
pN, crd_freed);
17900 while ((crd != init_crd) &&
17901 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
17902 (init_crd - crd_start))) {
17910 BLOGD(sc,
DBG_LOAD,
"CREDIT_FREED[%d]: c:%x\n", regs->
pN, crd_freed);
17915 BLOGD(sc,
DBG_LOAD,
"Waited %d*%d usec for PBF tx buffer[%d]\n",
17922 uint32_t poll_count)
17924 uint32_t occup, to_free, freed, freed_start;
17925 uint32_t cur_cnt = poll_count;
17934 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
17947 BLOGD(sc,
DBG_LOAD,
"Waited %d*%d usec for PBF cmd queue[%d]\n",
18008 for (i = 0; i <
ARRAY_SIZE(cmd_regs); i++) {
18013 for (i = 0; i <
ARRAY_SIZE(buf_regs); i++) {
18024 BLOGD(sc,
DBG_LOAD,
"CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
18030 BLOGD(sc,
DBG_LOAD,
"IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
18033 BLOGD(sc,
DBG_LOAD,
"IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
18036 BLOGD(sc,
DBG_LOAD,
"IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
18039 BLOGD(sc,
DBG_LOAD,
"PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
18042 BLOGD(sc,
DBG_LOAD,
"PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
18045 BLOGD(sc,
DBG_LOAD,
"PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
18081 BLOGE(sc,
"PCIE Transactions still pending\n");
18103 uint16_t cdu_ilt_start;
18104 uint32_t
addr, val;
18105 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
18106 int i, main_mem_width, rc;
18108 BLOGD(sc,
DBG_LOAD,
"starting func init for func %d\n", func);
18114 BLOGE(sc,
"FLR cleanup failed!\n");
18249 int num_segs, sb_idx, prod_offset;
18285 for (sb_idx = 0; sb_idx < sc->
igu_sb_cnt; sb_idx++) {
18289 for (i = 0; i < num_segs; i++) {
18291 (prod_offset + i) * 4;
18307 dsb_idx =
SC_VN(sc);
18317 for (i = 0; i < (num_segs *
E1HVN_MAX);
18320 (prod_offset + i)*4;
18355 REG_WR(sc, 0x2114, 0xffffffff);
18356 REG_WR(sc, 0x2120, 0xffffffff);
18361 SC_PORT(sc) * (main_mem_size * 4);
18363 main_mem_width = 8;
18365 val =
REG_RD(sc, main_mem_prty_clr);
18368 "Parity errors in HC block during function init (0x%x)!\n",
18373 for (i = main_mem_base;
18374 i < main_mem_base + main_mem_size * 4;
18375 i += main_mem_width) {
18378 i, main_mem_width / 4);
18381 REG_RD(sc, main_mem_prty_clr);
18410 BLOGW(sc,
"Bootcode is missing - cannot reset link\n");
18442 "BRB1 is not empty, %d blocks are occupied\n", val);
18454 uint32_t wb_write[2];
18524 for (i = 0; i < 200; i++) {
18582 BLOGE(sc,
"Unsupported chip revision\n");
18598 const uint8_t *zbuf,
18616 bus_addr_t phys_addr,
18630 for (i = 0; i <
size/4; i++) {
18643#include <sys/conf.h>
18645static int bxe_eioctl(
struct cdev *dev, u_long cmd, caddr_t data,
int fflag,
18646 struct thread *td);
18649 .d_version = D_VERSION,
18651 .d_name =
"bxecnic",
18654#define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1))
18657#define DUMP_ALL_PRESETS 0x1FFF
18658#define DUMP_MAX_PRESETS 13
18659#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
18660#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
18661#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
18662#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
18663#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
18665#define IS_REG_IN_PRESET(presets, idx) \
18666 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
18689 uint32_t preset_idx;
18690 int regdump_len32 = 0;
18698 return regdump_len32;
18701static const uint32_t *
18723static const uint32_t *
18815 uint32_t i, j, k, n;
18831 for (i = 0; i < num_pages; i++) {
18832 for (j = 0; j < write_num; j++) {
18833 REG_WR(sc, write_addr[j], page_addr[i]);
18835 for (k = 0; k < read_num; k++) {
18838 for (n = 0; n <
size; n++) {
18853 uint32_t i, j,
addr;
18854 const struct wreg_addr *wreg_addr_p = NULL;
18890 for (i = 0; i < wreg_addr_p->
size; i++) {
18916 uint32_t preset_idx;
18923 uint32_t cmd_offset;
18934 BLOGI(sc,
"Started collecting grcdump\n");
18939 sc->
grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT);
18942 BLOGW(sc,
"Unable to allocate memory for grcdump collection\n");
18992 if ((preset_idx == 2) || (preset_idx == 5) || (preset_idx == 8) ||
18993 (preset_idx == 11))
19021 BLOGI(sc,
"fw stats start_paddr %#jx end_paddr %#jx vaddr %p size 0x%x\n",
19026 if(sc->
def_sb != NULL) {
19027 BLOGI(sc,
"def_status_block paddr %p vaddr %p size 0x%zx\n",
19032 BLOGI(sc,
"event_queue paddr %#jx vaddr %p size 0x%x\n",
19036 BLOGI(sc,
"slow path paddr %#jx vaddr %p size 0x%zx\n",
19041 BLOGI(sc,
"slow path queue paddr %#jx vaddr %p size 0x%x\n",
19045 BLOGI(sc,
"fw_buf paddr %#jx vaddr %p size 0x%x\n",
19055 BLOGI(sc,
"FP status block fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
19058 BLOGI(sc,
"TX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
19061 BLOGI(sc,
"RX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
19064 BLOGI(sc,
"RX RCQ CHAIN fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
19067 BLOGI(sc,
"RX SGE CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
19074 if(ilt->
lines != NULL) {
19075 for (i = ilt_cli->
start; i <= ilt_cli->end; i++) {
19076 BLOGI(sc,
"ECORE_ILT paddr %#jx vaddr %p size 0x%x\n",
19077 (uintmax_t)(((
struct bxe_dma *)((&ilt->
lines[i])->page))->paddr),
19085 for (i = 0; i < 224; i++) {
19088 BLOGI(sc,
"DMAE_REG_CMD_MEM i=%d reg_addr 0x%x reg_val 0x%08x\n",i,
19093 BLOGI(sc,
"Collection of grcdump done\n");
19103 if (sc->
eeprom == NULL) {
19104 BLOGW(sc,
"Unable to alloc for eeprom size buffer\n");
19117 free(sc->
eeprom, M_DEVBUF);
19133 if (sc->
eeprom != NULL) {
19134 free(sc->
eeprom, M_DEVBUF);
19145 if ((if_getdrvflags(sc->
ifp) & IFF_DRV_RUNNING) == 0)
19158 BLOGW(sc,
"Cannot access eeprom when interface is down\n");
19173 BLOGW(sc,
"Cannot access eeprom when interface is down\n");
19219 BLOGW(sc,
"ioctl cmd %d failed rval %d\n", eeprom->
eeprom_cmd, rval);
19228 uint32_t ext_phy_config;
19256 dev_info.port_hw_config[port].external_phy_config);
19407 BLOGW(sc,
"BXE_RDW_PCICFG ioctl wrong cmd passed\n");
19431bxe_debugnet_init(
struct ifnet *ifp,
int *nrxr,
int *ncl,
int *clsize)
19435 sc = if_getsoftc(
ifp);
19438 *ncl = DEBUGNET_MAX_IN_FLIGHT;
19444bxe_debugnet_event(
struct ifnet *
ifp __unused,
enum debugnet_ev event __unused)
19449bxe_debugnet_transmit(
struct ifnet *
ifp,
struct mbuf *m)
19454 sc = if_getsoftc(
ifp);
19455 if ((if_getdrvflags(
ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
19460 if (error != 0 && m != NULL)
19466bxe_debugnet_poll(
struct ifnet *
ifp,
int count)
19471 sc = if_getsoftc(
ifp);
19472 if ((if_getdrvflags(
ifp) & IFF_DRV_RUNNING) == 0 ||
void ecore_init_e1_firmware(struct bxe_softc *sc)
static const struct iro e1_iro_arr[385]
void ecore_init_e1h_firmware(struct bxe_softc *sc)
static const struct iro e1h_iro_arr[385]
void ecore_init_e2_firmware(struct bxe_softc *sc)
static const struct iro e2_iro_arr[385]
static void bxe_task_fp(struct bxe_fastpath *fp)
static int bxe_init_hw_port(struct bxe_softc *sc)
static int bxe_gpio_write(struct bxe_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
static int bxe_nic_load_request(struct bxe_softc *sc, uint32_t *load_code)
static void bxe_set_requested_fc(struct bxe_softc *sc)
static void bxe_update_sge_prod(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t sge_len, union eth_sgl_or_raw_data *cqe)
static void bxe_init_pxp(struct bxe_softc *sc)
static void bxe_set_reset_in_progress(struct bxe_softc *sc)
static void bxe_drv_info_ether_stat(struct bxe_softc *sc)
#define IS_E3A0_REG(chips)
static void bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc, struct pbf_pN_cmd_regs *regs, uint32_t poll_count)
static int bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p)
static int bxe_set_eth_mac(struct bxe_softc *sc, uint8_t set)
void elink_cb_reg_wb_read(struct bxe_softc *sc, uint32_t offset, uint32_t *wb_write, uint16_t len)
static u_int bxe_push_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
static uint8_t bxe_set_pbd_csum(struct bxe_fastpath *fp, struct mbuf *m, struct eth_tx_parse_bd_e1x *pbd)
#define BXE_NUM_ETH_Q_STATS
static void bxe_init_func_obj(struct bxe_softc *sc)
static int bxe_init_mcast_macs_list(struct bxe_softc *sc, struct ecore_mcast_ramrod_params *p)
static uint32_t bxe_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param)
static void bxe_prev_interrupted_dmae(struct bxe_softc *sc)
static int bxe_set_storm_rx_mode(struct bxe_softc *sc)
static void bxe_link_settings_requested(struct bxe_softc *sc)
static void bxe_hc_int_enable(struct bxe_softc *sc)
static void bxe_get_phy_info(struct bxe_softc *sc)
static void bxe_pf_rx_q_prep(struct bxe_softc *sc, struct bxe_fastpath *fp, struct rxq_pause_params *pause, struct ecore_rxq_setup_params *rxq_init)
static int bxe_gpio_int_write(struct bxe_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
static devclass_t bxe_devclass
uint32_t calc_crc32(uint8_t *crc32_packet, uint32_t crc32_length, uint32_t crc32_seed, uint8_t complement)
static int bxe_init_rss_pf(struct bxe_softc *sc)
#define BXE_PREV_UNDI_PROD(rcq, bd)
static int bxe_fill_accept_flags(struct bxe_softc *sc, uint32_t rx_mode, unsigned long *rx_accept_flags, unsigned long *tx_accept_flags)
static void ecore_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, uint32_t addr, uint32_t len)
static void bxe_acquire_phy_lock(struct bxe_softc *sc)
static int bxe_init_hw_common(struct bxe_softc *sc)
static const uint32_t * __bxe_get_page_addr_ar(struct bxe_softc *sc)
static struct ecore_queue_sp_obj * bxe_cid_to_q_obj(struct bxe_softc *sc, uint32_t cid)
static int bxe_stop_queue(struct bxe_softc *sc, int index)
static u_int bxe_set_addr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
static void bxe_calc_fc_adv(struct bxe_softc *sc)
uint32_t elink_cb_gpio_read(struct bxe_softc *sc, uint16_t gpio_num, uint8_t port)
MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer")
static void bxe_prev_unload_close_mac(struct bxe_softc *sc, struct bxe_mac_vals *vals)
static void bxe_release_mutexes(struct bxe_softc *sc)
uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
#define BXE_PREV_UNDI_PROD_ADDR(p)
static int bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
static int bxe_fill_frag_mbuf(struct bxe_softc *sc, struct bxe_fastpath *fp, struct bxe_sw_tpa_info *tpa_info, uint16_t queue, uint16_t pages, struct mbuf *m, struct eth_end_agg_rx_cqe *cqe, uint16_t cqe_idx)
static int bxe_prev_unload_common(struct bxe_softc *sc)
void elink_cb_reg_wb_write(struct bxe_softc *sc, uint32_t offset, uint32_t *wb_write, uint16_t len)
static void bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
static void bxe_init_sp_ring(struct bxe_softc *sc)
#define Q_STATS_OFFSET32(stat_name)
static uint8_t bxe_trylock_hw_lock(struct bxe_softc *sc, uint32_t resource)
static void bxe_storm_memset_hc_timeout(struct bxe_softc *sc, uint8_t port, uint8_t fw_sb_id, uint8_t sb_index, uint8_t ticks)
static int bxe_alloc_buf_rings(struct bxe_softc *sc)
static void bxe_handle_rx_mode_eqe(struct bxe_softc *sc, union event_ring_elem *elem)
static int bxe_prev_unload_uncommon(struct bxe_softc *sc)
static void bxe_cmng_fns_init(struct bxe_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
static int bxe_poll_hw_usage_counters(struct bxe_softc *sc, uint32_t poll_cnt)
static void bxe_int_disable_sync(struct bxe_softc *sc, int disable_hw)
static int bxe_detach(device_t)
static uint8_t bxe_has_tx_work(struct bxe_fastpath *fp)
static void bxe_calc_vn_max(struct bxe_softc *sc, int vn, struct cmng_init_input *input)
static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
static uint16_t bxe_extract_max_cfg(struct bxe_softc *sc, uint32_t mf_cfg)
static int bxe_nvram_write(struct bxe_softc *sc, uint32_t offset, uint8_t *data_buf, int buf_size)
static struct ecore_func_sp_drv_ops bxe_func_sp_drv
static void bxe_nic_init(struct bxe_softc *sc, int load_code)
static uint16_t bxe_tx_avail(struct bxe_softc *sc, struct bxe_fastpath *fp)
static int bxe_tx_mq_start_locked(struct bxe_softc *sc, if_t ifp, struct bxe_fastpath *fp, struct mbuf *m)
#define IS_E3B0_REG(chips)
static int bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
static void bxe_wr_fp_sb_data(struct bxe_softc *sc, int fw_sb_id, uint32_t *sb_data_p, uint32_t data_size)
int bxe_grc_dump(struct bxe_softc *sc)
static uint8_t bxe_parity_attn(struct bxe_softc *sc, uint8_t *global, uint8_t print, uint32_t *sig)
static void bxe_reset_mcp_prep(struct bxe_softc *sc, uint32_t *magic_val)
static uint8_t bxe_fp_qzone_id(struct bxe_fastpath *fp)
static int bxe_send_final_clnup(struct bxe_softc *sc, uint8_t clnup_func, uint32_t poll_cnt)
static void bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
static int bxe_release_leader_lock(struct bxe_softc *sc)
static void bxe_pf_disable(struct bxe_softc *sc)
static void bxe_zero_sp_sb(struct bxe_softc *sc)
static void bxe_chip_cleanup(struct bxe_softc *sc, uint32_t unload_mode, uint8_t keep_link)
static void bxe_update_eq_prod(struct bxe_softc *sc, uint16_t prod)
static int bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
#define SHARED_MF_CLP_MAGIC
static void bxe_init_internal(struct bxe_softc *sc, uint32_t load_code)
static void bxe_tx_start(if_t ifp)
static void bxe_get_params(struct bxe_softc *sc)
static int bxe_set_spio(struct bxe_softc *sc, int spio, uint32_t mode)
static void bxe_handle_drv_info_req(struct bxe_softc *sc)
static int bxe_get_mf_cfg_info(struct bxe_softc *sc)
static void bxe_clear_func_ilt(struct bxe_softc *sc, uint32_t func)
static int bxe_check_blocks_with_parity3(struct bxe_softc *sc, uint32_t sig, int par_num, uint8_t *global, uint8_t print)
static struct bxe_prev_list_node * bxe_prev_path_get_entry(struct bxe_softc *sc)
#define BXE_PATH0_LOAD_CNT_MASK
static int bxe_media_detect(struct bxe_softc *sc)
static void bxe_ilt_wr(struct bxe_softc *sc, uint32_t index, bus_addr_t addr)
static int bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc, uint32_t reg, char *msg, uint32_t poll_cnt)
static void bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id, int igu_seg_id)
static void bxe_init_internal_common(struct bxe_softc *sc)
int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, struct bxe_dma *dma, const char *msg)
static __noinline void bxe_dump_mbuf(struct bxe_softc *sc, struct mbuf *m, uint8_t contents)
static int bxe_has_rx_work(struct bxe_fastpath *fp)
static uint32_t bxe_flr_clnup_poll_count(struct bxe_softc *sc)
static void bxe_update_drv_flags(struct bxe_softc *sc, uint32_t flags, uint32_t set)
static uint32_t bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
static int bxe_attach(device_t)
static int bxe_func_stop(struct bxe_softc *sc)
static uint8_t bxe_clear_pf_load(struct bxe_softc *sc)
#define BXE_PATH1_RST_IN_PROG_BIT
uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr)
static void bxe_clp_reset_prep(struct bxe_softc *sc, uint32_t *magic_val)
static int bxe_get_link_cfg_idx(struct bxe_softc *sc)
static void __storm_memset_dma_mapping(struct bxe_softc *sc, uint32_t addr, bus_addr_t mapping)
static int bxe_sysctl_pauseparam(SYSCTL_HANDLER_ARGS)
static void bxe_handle_eee_event(struct bxe_softc *sc)
static void bxe_drv_pulse(struct bxe_softc *sc)
static void bxe_pxp_prep(struct bxe_softc *sc)
static void bxe_intr_fp(void *xfp)
#define BXE_PREV_UNDI_BD(val)
static int bxe_nvram_read(struct bxe_softc *sc, uint32_t offset, uint8_t *ret_buf, int buf_size)
static void bxe_attn_int_deasserted2(struct bxe_softc *sc, uint32_t attn)
#define AEU_PXP2_HW_INT_BIT
DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0)
static void bxe_del_cdev(struct bxe_softc *sc)
static void bxe_config_mf_bw(struct bxe_softc *sc)
static void bxe_calc_vn_min(struct bxe_softc *sc, struct cmng_init_input *input)
static void bxe_init_def_sb(struct bxe_softc *sc)
static struct bxe_device_type bxe_devs[]
static uint16_t bxe_cid_ilt_lines(struct bxe_softc *sc)
static void bxe_clear_reset_global(struct bxe_softc *sc)
static void bxe_tx_start_locked(struct bxe_softc *sc, if_t ifp, struct bxe_fastpath *fp)
uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr)
static int bxe_get_leader_lock_resource(struct bxe_softc *sc)
static int bxe_init_locked(struct bxe_softc *sc)
static void bxe_common_init_phy(struct bxe_softc *sc)
static unsigned long bxe_get_common_flags(struct bxe_softc *sc, struct bxe_fastpath *fp, uint8_t zero_stats)
static void bxe_wr_sp_sb_data(struct bxe_softc *sc, struct hc_sp_status_block_data *sp_sb_data)
static void bxe_map_sb_state_machines(struct hc_index_data *index_data)
static int bxe_is_contextless_ramrod(int cmd, int cmd_type)
static void bxe_gunzip_end(struct bxe_softc *sc)
static void bxe_setup_fan_failure_detection(struct bxe_softc *sc)
static void bxe_init_tx_ring_one(struct bxe_fastpath *fp)
static void storm_memset_cmng(struct bxe_softc *sc, struct cmng_init *cmng, uint8_t port)
static int bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom)
static int bxe_func_wait_started(struct bxe_softc *sc)
uint8_t elink_cb_gpio_mult_write(struct bxe_softc *sc, uint8_t pins, uint8_t mode)
static int bxe_mc_assert(struct bxe_softc *sc)
#define OP_GEN_TYPE(type)
static int bxe_init_hw_common_chip(struct bxe_softc *sc)
static void bxe_release_phy_lock(struct bxe_softc *sc)
static void bxe_force_link_reset(struct bxe_softc *sc)
static int bxe_get_cur_phy_idx(struct bxe_softc *sc)
static void bxe_init_mutexes(struct bxe_softc *sc)
static void bxe_attn_int_deasserted3(struct bxe_softc *sc, uint32_t attn)
static void bxe_free_sge_chain(struct bxe_fastpath *fp)
static int bxe_reset_mcp_comp(struct bxe_softc *sc, uint32_t magic_val)
static int bxe_del_all_macs(struct bxe_softc *sc, struct ecore_vlan_mac_obj *mac_obj, int mac_type, uint8_t wait_for_comp)
static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, uint16_t prev_index, uint16_t index)
static void bxe_fan_failure(struct bxe_softc *sc)
static void ecore_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val)
#define IS_E1H_REG(chips)
static void bxe_link_report(struct bxe_softc *sc)
static void bxe_handle_classification_eqe(struct bxe_softc *sc, union event_ring_elem *elem)
static int bxe_check_blocks_with_parity4(struct bxe_softc *sc, uint32_t sig, int par_num, uint8_t print)
static void bxe_free_fw_stats_mem(struct bxe_softc *sc)
static int bxe_check_blocks_with_parity1(struct bxe_softc *sc, uint32_t sig, int par_num, uint8_t *global, uint8_t print)
static void bxe_set_234_gates(struct bxe_softc *sc, uint8_t close)
void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, uint32_t cid)
static uint32_t bxe_send_unload_req(struct bxe_softc *sc, int unload_mode)
static void bxe_free_ilt_lines_mem(struct bxe_softc *sc)
MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF)
static void bxe_pmf_update(struct bxe_softc *sc)
void elink_cb_notify_link_changed(struct bxe_softc *sc)
static int bxe_alloc_ilt_mem(struct bxe_softc *sc)
static void bxe_send_unload_done(struct bxe_softc *sc, uint8_t keep_link)
void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32)
static void bxe_prev_unload_undi_inc(struct bxe_softc *sc, uint8_t port, uint8_t inc)
static int bxe_check_blocks_with_parity0(struct bxe_softc *sc, uint32_t sig, int par_num, uint8_t print)
static void bxe_pf_q_prep_init(struct bxe_softc *sc, struct bxe_fastpath *fp, struct ecore_queue_init_params *init_params)
static void bxe_tpa_stop(struct bxe_softc *sc, struct bxe_fastpath *fp, struct bxe_sw_tpa_info *tpa_info, uint16_t queue, uint16_t pages, struct eth_end_agg_rx_cqe *cqe, uint16_t cqe_idx)
static int bxe_alloc_hsi_mem(struct bxe_softc *sc)
static void bxe_intr_sp(void *xsc)
static int bxe_acquire_nvram_lock(struct bxe_softc *sc)
static uint8_t bxe_rxeof(struct bxe_softc *sc, struct bxe_fastpath *fp)
static int bxe_prev_mark_path(struct bxe_softc *sc, uint8_t after_undi)
#define BXE_RECOVERY_GLOB_REG
static __noinline int bxe_alloc_fp_buffers(struct bxe_softc *sc)
static int bxe_acquire_alr(struct bxe_softc *sc)
void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val)
static void bxe_update_rx_prod(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t rx_bd_prod, uint16_t rx_cq_prod, uint16_t rx_sge_prod)
static void bxe_free_hsi_mem(struct bxe_softc *sc)
#define OP_GEN_PARAM(param)
static void bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p)
static void bxe_link_settings_supported(struct bxe_softc *sc, uint32_t switch_cfg)
static void bxe_sp_event(struct bxe_softc *sc, struct bxe_fastpath *fp, union eth_rx_cqe *rr_cqe)
static uint16_t bxe_update_dsb_idx(struct bxe_softc *sc)
static int bxe_initial_phy_init(struct bxe_softc *sc, int load_mode)
static void bxe_lb_pckt(struct bxe_softc *sc)
static uint32_t bxe_pcie_capability_read(struct bxe_softc *sc, int reg, int width)
#define PXP2_EOP_ERROR_BIT
static void bxe_attn_int(struct bxe_softc *sc)
int bxe_test_bit(int nr, volatile unsigned long *addr)
static void storm_memset_spq_addr(struct bxe_softc *sc, bus_addr_t mapping, uint16_t abs_fid)
static int bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, uint32_t addr, uint32_t len)
static int bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
static void bxe_disable_close_the_gate(struct bxe_softc *sc)
static void storm_memset_eq_data(struct bxe_softc *sc, struct event_ring_data *eq_data, uint16_t pfid)
static void bxe_link_reset(struct bxe_softc *sc)
static const uint32_t * __bxe_get_page_write_ar(struct bxe_softc *sc)
static uint32_t bxe_get_pretend_reg(struct bxe_softc *sc)
static int bxe_watchdog(struct bxe_softc *sc, struct bxe_fastpath *fp)
#define STATS_OFFSET32(stat_name)
static void bxe_sp_err_timeout_task(void *arg, int pending)
uint8_t elink_cb_gpio_write(struct bxe_softc *sc, uint16_t gpio_num, uint8_t mode, uint8_t port)
static uint8_t bxe_is_pcie_pending(struct bxe_softc *sc)
static int bxe_gpio_mult_write(struct bxe_softc *sc, uint8_t pins, uint32_t mode)
static int bxe_max_rx_bufs
static void bxe_fill(struct bxe_softc *sc, uint32_t addr, int fill, uint32_t len)
static void bxe_free_fp_buffers(struct bxe_softc *sc)
static void bxe_attn_int_deasserted0(struct bxe_softc *sc, uint32_t attn)
static int bxe_hc_tx_ticks
static void bxe_disable_nvram_access(struct bxe_softc *sc)
#define OP_GEN_AGG_VECT(index)
static void bxe_set_reset_global(struct bxe_softc *sc)
static uint16_t bxe_get_mf_speed(struct bxe_softc *sc)
static int bxe_interrupt_alloc(struct bxe_softc *sc)
int bxe_cmpxchg(volatile int *addr, int old, int new)
static void bxe_reset_common(struct bxe_softc *sc)
#define BXE_GLOBAL_RESET_BIT
static void bxe_func_init(struct bxe_softc *sc, struct bxe_func_init_params *p)
static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, uint16_t index)
static int bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
static int bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
static uint32_t __bxe_get_page_read_num(struct bxe_softc *sc)
uint8_t elink_cb_gpio_int_write(struct bxe_softc *sc, uint16_t gpio_num, uint8_t mode, uint8_t port)
static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, int queue)
SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN, &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode")
static void bxe_int_enable(struct bxe_softc *sc)
static void bxe_init_multi_cos(struct bxe_softc *sc)
static void bxe_init_fp_mutexs(struct bxe_softc *sc)
static void bxe_pf_q_prep_general(struct bxe_softc *sc, struct bxe_fastpath *fp, struct ecore_general_setup_params *gen_init, uint8_t cos)
static int bxe_set_mc_list(struct bxe_softc *sc)
void bxe_set_bit(unsigned int nr, volatile unsigned long *addr)
static unsigned long bxe_get_q_flags(struct bxe_softc *sc, struct bxe_fastpath *fp, uint8_t leading)
#define BXE_PATH1_LOAD_CNT_MASK
static void bxe_mq_flush(struct ifnet *ifp)
uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, uint8_t dst_type, uint8_t with_comp, uint8_t comp_type)
static void bxe_igu_int_enable(struct bxe_softc *sc)
static void bxe_enable_nvram_access(struct bxe_softc *sc)
static int bxe_tx_queue_has_work(struct bxe_fastpath *fp)
static void bxe_free_tpa_pool(struct bxe_fastpath *fp)
static bool bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info)
static int bxe_nic_load_analyze_req(struct bxe_softc *sc, uint32_t load_code)
static int bxe_issue_dmae_with_comp(struct bxe_softc *sc, struct dmae_cmd *dmae)
static int bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc, uint8_t *global, uint8_t print)
static int bxe_nvram_write_dword(struct bxe_softc *sc, uint32_t offset, uint32_t val, uint32_t cmd_flags)
static void bxe_e1h_disable(struct bxe_softc *sc)
#define BXE_PATH0_LOAD_CNT_SHIFT
#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
static void bxe_reset_port(struct bxe_softc *sc)
static int bxe_init_hw(struct bxe_softc *sc, uint32_t load_code)
static void storm_memset_eq_prod(struct bxe_softc *sc, uint16_t eq_prod, uint16_t pfid)
static void bxe_fill_report_data(struct bxe_softc *sc, struct bxe_link_report_data *data)
static void bxe_storm_memset_hc_disable(struct bxe_softc *sc, uint8_t port, uint16_t fw_sb_id, uint8_t sb_index, uint8_t disable)
static int bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset)
static void bxe_clp_reset_done(struct bxe_softc *sc, uint32_t magic_val)
static driver_t bxe_driver
#define BXE_DRIVER_VERSION
static void bxe_free_ilt_mem(struct bxe_softc *sc)
static void bxe_link_attn(struct bxe_softc *sc)
static void bxe_iov_init_dq(struct bxe_softc *sc)
void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx)
static void bxe_set_pbd_lso_e2(struct mbuf *m, uint32_t *parsing_data)
static void bxe_prep_dmae_with_comp(struct bxe_softc *sc, struct dmae_cmd *dmae, uint8_t src_type, uint8_t dst_type)
static void bxe_link_status_update(struct bxe_softc *sc)
static int bxe_init_shmem(struct bxe_softc *sc)
static uint8_t bxe_set_pbd_csum_e2(struct bxe_fastpath *fp, struct mbuf *m, uint32_t *parsing_data)
static const struct @1 bxe_eth_q_stats_arr[]
void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma)
static int bxe_gunzip_init(struct bxe_softc *sc)
int bxe_sp_post(struct bxe_softc *sc, int command, int cid, uint32_t data_hi, uint32_t data_lo, int cmd_type)
static void bxe_dcc_event(struct bxe_softc *sc, uint32_t dcc_event)
static int bxe_ioctl(if_t ifp, u_long command, caddr_t data)
static int bxe_set_q_rx_mode(struct bxe_softc *sc, uint8_t cl_id, unsigned long rx_mode_flags, unsigned long rx_accept_flags, unsigned long tx_accept_flags, unsigned long ramrod_flags)
static __noinline int bxe_nic_load(struct bxe_softc *sc, int load_mode)
static int bxe_do_flr(struct bxe_softc *sc)
static int bxe_shutdown(device_t)
static int bxe_chktso_window(struct bxe_softc *sc, int nsegs, bus_dma_segment_t *segs, struct mbuf *m)
static int bxe_pretend_func(struct bxe_softc *sc, uint16_t pretend_func_val)
static uint8_t bxe_wait_sp_comp(struct bxe_softc *sc, unsigned long mask)
static int bxe_nic_load_no_mcp(struct bxe_softc *sc)
#define BYTE_OFFSET(offset)
static void bxe_tx_mq_start_deferred(void *arg, int pending)
static int bxe_probe(device_t)
static void storm_memset_func_cfg(struct bxe_softc *sc, struct tstorm_eth_function_common_config *tcfg, uint16_t abs_fid)
static void bxe_handle_sp_tq(void *context, int pending)
static int bxe_init_firmware(struct bxe_softc *sc)
static void bxe_init_tx_rings(struct bxe_softc *sc)
static void bxe_init_rx_rings(struct bxe_softc *sc)
static uint8_t bxe_reset_is_done(struct bxe_softc *sc, int engine)
static int bxe_nvram_read_dword(struct bxe_softc *sc, uint32_t offset, uint32_t *ret_val, uint32_t cmd_flags)
static void bxe_hc_int_disable(struct bxe_softc *sc)
static void bxe_interrupt_free(struct bxe_softc *sc)
static void bxe_igu_clear_sb_gen(struct bxe_softc *sc, uint8_t func, uint8_t idu_sb_id, uint8_t is_pf)
static int bxe_er_poll_igu_vq(struct bxe_softc *sc)
static void bxe_attn_int_deasserted4(struct bxe_softc *sc, uint32_t attn)
static LIST_HEAD(bxe_prev_list_node)
static void bxe_enable_blocks_attention(struct bxe_softc *sc)
void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, uint32_t dst_addr, uint32_t len32)
static void bxe_init_eq_ring(struct bxe_softc *sc)
static const struct @0 bxe_eth_stats_arr[]
static void bxe_get_function_num(struct bxe_softc *sc)
static void bxe_init_objs(struct bxe_softc *sc)
static void bxe_set_mf_bw(struct bxe_softc *sc)
static void bxe_reset_func(struct bxe_softc *sc)
static void bxe_pf_init(struct bxe_softc *sc)
static void bxe_sp_prod_update(struct bxe_softc *sc)
static int bxe_gpio_read(struct bxe_softc *sc, int gpio_num, uint8_t port)
static void bxe_print_next_block(struct bxe_softc *sc, int idx, const char *blk)
static int bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, size_t size, uint32_t *data)
static void bxe_nic_load_pmf(struct bxe_softc *sc, uint32_t load_code)
static int bxe_get_igu_cam_info(struct bxe_softc *sc)
static void bxe_attn_int_deasserted1(struct bxe_softc *sc, uint32_t attn)
static const struct reg_addr * __bxe_get_page_read_ar(struct bxe_softc *sc)
static void bxe_iov_init_dmae(struct bxe_softc *sc)
static uint32_t __bxe_get_page_reg_num(struct bxe_softc *sc)
static void bxe_periodic_callout_func(void *xsc)
static void bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
static void bxe_get_tunable_params(struct bxe_softc *sc)
static int bxe_nvram_write1(struct bxe_softc *sc, uint32_t offset, uint8_t *data_buf, int buf_size)
void elink_cb_event_log(struct bxe_softc *sc, const elink_log_id_t elink_log_id,...)
static bool bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)
static void bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
static void bxe_ilt_set_info(struct bxe_softc *sc)
static int bxe_leader_reset(struct bxe_softc *sc)
static int bxe_set_qm_cid_count(struct bxe_softc *sc)
static uint32_t __bxe_get_page_write_num(struct bxe_softc *sc)
static void bxe_hw_enable_status(struct bxe_softc *sc)
static void bxe_periodic_start(struct bxe_softc *sc)
static void bxe_tpa_start(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t queue, uint16_t cons, uint16_t prod, struct eth_fast_path_rx_cqe *cqe)
static void bxe_free_mem(struct bxe_softc *sc)
static int bxe_setup_queue(struct bxe_softc *sc, struct bxe_fastpath *fp, uint8_t leading)
static void bxe_init_sb(struct bxe_softc *sc, bus_addr_t busaddr, int vfid, uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
static int bxe_config_rss_eth(struct bxe_softc *sc, uint8_t config_hash)
static int bxe_reset_hw(struct bxe_softc *sc, uint32_t load_code)
static void bxe_link_report_locked(struct bxe_softc *sc)
static uint8_t bxe_get_load_status(struct bxe_softc *sc, int engine)
#define BXE_DEF_SB_ATT_IDX
static int bxe_alloc_mem(struct bxe_softc *sc)
static int bxe_max_aggregation_size
static int bxe_setup_leading(struct bxe_softc *sc)
static uint32_t bxe_rx_ustorm_prods_offset(struct bxe_softc *sc, struct bxe_fastpath *fp)
static void bxe_add_sysctls(struct bxe_softc *sc)
MODULE_DEPEND(bxe, pci, 1, 1, 1)
static void bxe_attn_int_asserted(struct bxe_softc *sc, uint32_t asserted)
static int bxe_release_nvram_lock(struct bxe_softc *sc)
#define IS_REG_IN_PRESET(presets, idx)
#define BXE_PATH1_LOAD_CNT_SHIFT
static void bxe_int_disable(struct bxe_softc *sc)
static int bxe_func_start(struct bxe_softc *sc)
static int bxe_get_device_info(struct bxe_softc *sc)
static int bxe_check_valid_mf_cfg(struct bxe_softc *sc)
static int bxe_get_shmem_info(struct bxe_softc *sc)
static int bxe_init_ifnet(struct bxe_softc *sc)
static void bxe_igu_int_disable(struct bxe_softc *sc)
#define BXE_PREV_WAIT_NEEDED
static int bxe_add_cdev(struct bxe_softc *sc)
static void bxe_free_buf_rings(struct bxe_softc *sc)
static int bxe_init_hw_func(struct bxe_softc *sc)
#define BXE_PREV_UNDI_RCQ(val)
static void bxe_deallocate_bars(struct bxe_softc *sc)
static int bxe_set_power_state(struct bxe_softc *sc, uint8_t state)
static int bxe_prev_mcp_done(struct bxe_softc *sc)
static int bxe_process_kill(struct bxe_softc *sc, uint8_t global)
static void bxe_handle_mcast_eqe(struct bxe_softc *sc)
int bxe_test_and_set_bit(int nr, volatile unsigned long *addr)
SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD|CTLFLAG_MPSAFE, 0, "bxe driver parameters")
#define BXE_NUM_ETH_STATS
static void storm_memset_func_en(struct bxe_softc *sc, uint16_t abs_fid, uint8_t enable)
SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, CTLFLAG_RDTUN, &bxe_debug, 0, "Debug logging mode")
static void bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
static int bxe_allocate_bars(struct bxe_softc *sc)
uint8_t elink_cb_path_id(struct bxe_softc *sc)
static int bxe_pf_flr_clnup(struct bxe_softc *sc)
static __noinline int bxe_nic_unload(struct bxe_softc *sc, uint32_t unload_mode, uint8_t keep_link)
static void storm_memset_vf_to_pf(struct bxe_softc *sc, uint16_t abs_fid, uint16_t pf_id)
static struct eth_spe * bxe_sp_get_next(struct bxe_softc *sc)
static void bxe_update_last_max_sge(struct bxe_fastpath *fp, uint16_t idx)
static void bxe_set_modes_bitmap(struct bxe_softc *sc)
static void bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
static int bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
static void bxe_zero_fp_sb(struct bxe_softc *sc, int fw_sb_id)
uint32_t elink_cb_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param)
static device_method_t bxe_methods[]
static uint8_t bxe_reset_is_global(struct bxe_softc *sc)
void bxe_parity_recover(struct bxe_softc *sc)
static void bxe_e1h_enable(struct bxe_softc *sc)
static uint8_t bxe_txeof(struct bxe_softc *sc, struct bxe_fastpath *fp)
uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
static void bxe_set_pf_load(struct bxe_softc *sc)
static void bxe_init_eth_fp(struct bxe_softc *sc, int idx)
#define BXE_PATH0_RST_IN_PROG_BIT
static uint8_t bxe_trylock_leader_lock(struct bxe_softc *sc)
#define FLR_WAIT_INTERVAL
static void bxe_set_pbd_lso(struct mbuf *m, struct eth_tx_parse_bd_e1x *pbd)
static int bxe_hc_rx_ticks
void bxe_dcbx_set_state(struct bxe_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
static void bxe_release_alr(struct bxe_softc *sc)
static uint32_t bxe_flr_clnup_reg_poll(struct bxe_softc *sc, uint32_t reg, uint32_t expected, uint32_t poll_count)
static void bxe_drain_tx_queues(struct bxe_softc *sc)
static int bxe_interrupt_mode
static void bxe_release_firmware(struct bxe_softc *sc)
static void bxe_attn_int_deasserted(struct bxe_softc *sc, uint32_t deasserted)
static struct cdevsw bxe_cdevsw
static void bxe_periodic_stop(struct bxe_softc *sc)
void bxe_clear_bit(int nr, volatile unsigned long *addr)
static void bxe_read_mf_cfg(struct bxe_softc *sc)
static int bxe_get_cmng_fns_mode(struct bxe_softc *sc)
static void bxe_probe_pci_caps(struct bxe_softc *sc)
static void bxe_pbf_pN_buf_flushed(struct bxe_softc *sc, struct pbf_pN_buf_regs *regs, uint32_t poll_count)
static int ecore_gunzip(struct bxe_softc *sc, const uint8_t *zbuf, int len)
static int bxe_acquire_hw_lock(struct bxe_softc *sc, uint32_t resource)
static void bxe_tx_disable(struct bxe_softc *sc)
void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, uint8_t sb_index, uint8_t disable, uint16_t usec)
void bxe_handle_error(struct bxe_softc *sc)
static void bxe_process_kill_chip_reset(struct bxe_softc *sc, uint8_t global)
static void bxe_handle_fp_tq(void *context, int pending)
MALLOC_DECLARE(M_BXE_ILT)
static void bxe_squeeze_objects(struct bxe_softc *sc)
static void bxe_mcp_wait_one(struct bxe_softc *sc)
static int bxe_ifmedia_update(struct ifnet *ifp)
static void bxe_destroy_fp_mutexs(struct bxe_softc *sc)
static int bxe_tx_mq_start(struct ifnet *ifp, struct mbuf *m)
static uint8_t bxe_service_rxsgl(struct bxe_fastpath *fp, uint16_t len, uint16_t lenonbd, struct mbuf *m, struct eth_fast_path_rx_cqe *cqe_fp)
static void bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
static int bxe_set_uc_list(struct bxe_softc *sc)
static int bxe_config_rss_pf(struct bxe_softc *sc, struct ecore_rss_config_obj *rss_obj, uint8_t config_hash)
void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t segment, uint16_t index, uint8_t op, uint8_t update)
static int bxe_nic_unload_no_mcp(struct bxe_softc *sc)
static int bxe_int_mem_test(struct bxe_softc *sc)
static int bxe_set_mac_one(struct bxe_softc *sc, uint8_t *mac, struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type, unsigned long *ramrod_flags)
static int bxe_check_blocks_with_parity2(struct bxe_softc *sc, uint32_t sig, int par_num, uint8_t print)
static int bxe_release_hw_lock(struct bxe_softc *sc, uint32_t resource)
static int bxe_stop_locked(struct bxe_softc *sc)
void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val)
static uint16_t bxe_free_tx_pkt(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t idx)
static void bxe_igu_clear_sb(struct bxe_softc *sc, uint8_t idu_sb_id)
static int bxe_get_total_regs_len32(struct bxe_softc *sc)
static void bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
static int bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
static uint32_t bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
static int bxe_interrupt_attach(struct bxe_softc *sc)
static void bxe_handle_chip_tq(void *context, int pending)
static int bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, struct thread *td)
static bool bxe_is_nvram_accessible(struct bxe_softc *sc)
static uint8_t bxe_prev_is_path_marked(struct bxe_softc *sc)
static void bxe_eq_int(struct bxe_softc *sc)
static void bxe_set_rx_mode(struct bxe_softc *sc)
static int bxe_prev_unload(struct bxe_softc *sc)
int bxe_test_and_clear_bit(int nr, volatile unsigned long *addr)
static void bxe_intr_legacy(void *xsc)
static void bxe_init(void *xsc)
static int bxe_queue_count
void elink_cb_udelay(struct bxe_softc *sc, uint32_t usecs)
static void bxe_set_reset_done(struct bxe_softc *sc)
static void bxe_interrupt_detach(struct bxe_softc *sc)
static void bxe_pf_tx_q_prep(struct bxe_softc *sc, struct bxe_fastpath *fp, struct ecore_txq_setup_params *txq_init, uint8_t cos)
static int bxe_autogreeen
#define BXE_ONE_PORT_FLAG
#define ATTN_GENERAL_ATTN_6
#define BXE_RX_MODE_PROMISC
#define BXE_MAX_NUM_OF_VFS
#define CQE_TYPE_START(cqe_type)
#define BXE_SP_MAPPING(sc, var)
#define CHIP_IS_57810(sc)
#define ATTN_GENERAL_ATTN_3
#define MAX_IGU_ATTN_ACK_TO
#define BXE_NUM_ETH_QUEUES(sc)
#define CHIP_NUM_57840_MF
#define SHMEM2_RD(sc, field)
#define DMAE_PCI_ERR_FLAG
#define CHIP_PORT_MODE_NONE
#define ADVERTISED_1000baseT_Full
#define HC_INDEX_ETH_TX_CQ_CONS_COS2
#define BXE_SP_OBJ(sc, fp)
#define BXE_CORE_UNLOCK(sc)
#define VALID_OVLAN(ovlan)
#define BXE_TSO_MAX_SEGMENTS
#define RCQ_TOTAL_PER_PAGE
#define DOORBELL(sc, cid, val)
#define ATTN_NIG_FOR_FUNC
#define BXE_TX_CLEANUP_THRESHOLD
#define CHIP_NUM_57712_MF
#define BXE_MCAST_UNLOCK(sc)
#define BXE_ERR_TXQ_STUCK
#define CHIP_REV_IS_EMUL(sc)
#define ILT_NUM_PAGE_ENTRIES
#define BXE_RECOVERY_NIC_LOADING
#define FOR_EACH_ETH_QUEUE(sc, var)
#define ADVERTISED_10000baseT_Full
#define DMAE_LEN32_WR_MAX(sc)
#define BXE_FWMB_UNLOCK(sc)
#define RX_SGE_TOTAL_PER_PAGE
#define ATTN_GENERAL_ATTN_5
#define BXE_DMAE_UNLOCK(sc)
static void bxe_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update)
#define BXE_SET_ERROR_BIT(sc, error)
#define CHIP_INT_MODE_IS_BC(sc)
#define BXE_FP(sc, nr, var)
#define CID_TO_FP(cid, sc)
#define MFCFG_RD(sc, field)
#define BXE_PM_CAPABLE_FLAG
#define BXE_MCAST_LOCK(sc)
#define CHIP_IS_MF_CAP(sc)
#define BXE_STATE_CLOSING_WAITING_HALT
#define RCQ_USABLE_PER_PAGE
#define BXE_PXP_DRAM_ALIGN
#define BXE_MSIX_CAPABLE_FLAG
#define CHIP_PORT_MODE(sc)
#define RX_SGE_NEXT_MASK_ELEM(el)
#define BLOGW(sc, format, args...)
#define BXE_STATE_DISABLED
#define BXE_RX_MODE_ALLMULTI
#define MAX_DYNAMIC_ATTN_GRPS
static void bxe_igu_ack_sb_gen(struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t segment, uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
#define FOR_EACH_QUEUE(sc, var)
#define BXE_SP_UNLOCK(sc)
#define SHMEM2_WR(sc, field, val)
#define BXE_TSO_MAX_SEG_SIZE
#define INIT_MODE_FLAGS(sc)
#define BXE_FP_TX_LOCK(fp)
#define BXE_CORE_LOCK(sc)
#define BXE_MSI_CAPABLE_FLAG
#define BXE_FP_TX_UNLOCK(fp)
#define CHIP_IS_MODE_4_PORT(sc)
void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, struct mbuf *m, uint8_t contents)
#define BXE_FP_TX_LOCK_ASSERT(fp)
#define ATTN_HARD_WIRED_MASK
#define ATTN_GENERAL_ATTN_1
static uint8_t bxe_stats_id(struct bxe_fastpath *fp)
#define SGE_PAGE_ALIGN(addr)
#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var)
#define BLOGI(sc, format, args...)
#define BXE_STATE_OPENING_WAITING_LOAD
#define NVRAM_TIMEOUT_COUNT
#define ADVERTISED_100baseT_Half
#define FUNC_ILT_BASE(func)
static const uint32_t dmae_reg_go_c[]
#define BXE_FWMB_LOCK(sc)
static void bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
#define BXE_TPA_STATE_STOP
#define ADVERTISED_100baseT_Full
#define STORM_ASSERT_ARRAY_SIZE
#define BXE_PMF_LINK_ASSERT(sc)
#define SHMEM_WR(sc, field, val)
#define BXE_L2_MAX_CID(sc)
#define HC_INDEX_ETH_TX_CQ_CONS_COS0
#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
#define CHIP_NUM_57811_MF
#define BXE_MAX_MULTICAST
#define AUTO_GREEN_FORCE_OFF
#define BXE_DCBX_ENABLED_ON_NEG_OFF
#define SET_FLAG(value, mask, flag)
#define HC_SP_INDEX_ETH_DEF_CONS
#define VNICS_PER_PORT(sc)
#define BXE_DCBX_ENABLED_OFF
#define BXE_RECOVERY_FAILED
#define ATTN_GENERAL_ATTN_4
#define PAGES_PER_SGE_SHIFT
#define BXE_DCBX_ENABLED_ON_NEG_ON
#define FOREACH_ABS_FUNC_IN_PORT(sc, i)
#define REG_RD8(sc, offset)
#define BXE_VF_ID_INVALID
#define HC_INDEX_OOO_TX_CQ_CONS
#define SHMEM2_HAS(sc, field)
#define ADVERTISED_10baseT_Full
#define SC_MAX_VN_NUM(sc)
#define BXE_RX_ALIGN_SHIFT
#define BXE_RX_MODE_NORMAL
#define BXE_CORE_LOCK_ASSERT(sc)
#define BXE_ERR_MC_ASSERT
#define BXE_FP_RX_LOCK(fp)
#define BXE_FP_TX_TRYLOCK(fp)
#define BXE_RECOVERY_INIT
#define CHIP_REV_IS_FPGA(sc)
#define BXE_IGU_STAS_MSG_PF_CNT
#define DBASSERT(sc, exp, msg)
#define HC_SEG_ACCESS_NORM
#define INT_BLOCK_MODE_BW_COMP
#define BXE_PCIE_CAPABLE_FLAG
#define FIRST_TX_COS_INDEX
static uint16_t bxe_ack_int(struct bxe_softc *sc)
#define MF_PROTO_SUPPORT_FCOE
#define MF_PROTO_SUPPORT_ISCSI
#define TX_BD_TOTAL_PER_PAGE
#define ATTN_GENERAL_ATTN_2
#define HC_INDEX_ETH_RX_CQ_CONS
#define CHIP_REV_IS_SLOW(sc)
#define BXE_ERR_MCP_ASSERT
#define AUTO_GREEN_FORCE_ON
#define REG_WR16(sc, offset, val)
#define RX_BD_TOTAL_PER_PAGE
#define DMAE_CMD_ENDIANITY_B_DW_SWAP
#define VNICS_PER_PATH(sc)
#define ADVERTISED_10baseT_Half
#define BXE_DCBX_ENABLED_INVALID
#define DMAE_CMD_ENDIANITY_DW_SWAP
#define HC_INDEX_ETH_TX_CQ_CONS_COS1
#define BXE_MC_ASSERT_BITS
#define BXE_RECOVERY_WAIT
#define bxe_panic(sc, msg)
static int func_by_vn(struct bxe_softc *sc, int vn)
#define MFCFG_WR(sc, field, val)
#define BXE_CORE_TRYLOCK(sc)
#define ADVERTISED_2500baseX_Full
static uint32_t reg_poll(struct bxe_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
#define REG_RD(sc, offset)
#define HC_INDEX_ETH_FIRST_TX_CQ_CONS
#define BLOGE(sc, format, args...)
#define BLOGD(sc, codepath, format, args...)
#define CQE_TYPE_STOP(cqe_type)
@ BXE_LINK_REPORT_FULL_DUPLEX
@ BXE_LINK_REPORT_LINK_DOWN
@ BXE_LINK_REPORT_TX_FC_ON
@ BXE_LINK_REPORT_RX_FC_ON
#define CQE_TYPE(cqe_fp_flags)
#define BXE_DMAE_LOCK(sc)
#define HC_SEG_ACCESS_DEF
#define MF_PROTO_SUPPORT_ETHERNET
#define BXE_VALID_FLOWID(m)
#define CHIP_NUM_57840_4_10
#define DIV_ROUND_UP(n, d)
#define BXE_RECOVERY_DONE
#define BXE_PHY_UNLOCK(sc)
#define REG_WR(sc, offset, val)
#define CHIP_IS_57810_MF(sc)
#define LOAD_LOOPBACK_EXT
#define REG_WR8(sc, offset, val)
#define ATTN_SW_TIMER_4_FUNC
#define BXE_TPA_STATE_START
#define HC_SP_INDEX_EQ_CONS
#define ADVERTISED_Asym_Pause
#define bxe_fwd_sp_obj(sc, var)
#define SHMEM_RD(sc, field)
#define CHIP_NUM_57800_MF
#define CQE_TYPE_SLOW(cqe_type)
#define CQE_TYPE_FAST(cqe_type)
#define BXE_SET_FLOWID(m)
#define BXE_L2_CID_COUNT(sc)
#define BXE_FP_RX_UNLOCK(fp)
#define RX_SGE_USABLE_PER_PAGE
#define ETH_MIN_PACKET_SIZE
#define REG_WR_DMAE(sc, offset, valp, len32)
#define REG_RD_DMAE(sc, offset, valp, len32)
#define CHIP_NUM_57840_2_20
#define BXE_STATE_OPENING_WAITING_PORT
#define CHIP_NUM_57810_MF
#define BXE_IGU_STAS_MSG_VF_CNT
void bxe_dcbx_init_params(struct bxe_softc *sc)
#define BXE_IS_ETS_ENABLED(sc)
#define SET_FLAGS(flags, bits)
#define RESET_FLAGS(flags, bits)
static const uint32_t page_vals_e3[]
static const struct wreg_addr wreg_addr_e3
static const struct wreg_addr wreg_addr_e3b0
static const struct reg_addr page_read_regs_e3[]
static const struct reg_addr page_read_regs_e2[]
static const uint32_t page_vals_e2[]
#define PAGE_MODE_VALUES_E2
static const struct reg_addr reg_addrs[]
static const struct wreg_addr wreg_addr_e1
#define PAGE_MODE_VALUES_E3
static const uint32_t page_write_regs_e2[]
#define PAGE_WRITE_REGS_E3
static const unsigned int dump_num_registers[NUM_CHIPS][NUM_PRESETS]
static const struct wreg_addr wreg_addr_e2
#define BNX2X_DUMP_VERSION
static const uint32_t page_write_regs_e3[]
#define PAGE_WRITE_REGS_E2
static const struct wreg_addr wreg_addr_e1h
static const struct reg_addr idle_reg_addrs[]
#define PAGE_READ_REGS_E3
#define PAGE_READ_REGS_E2
elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
void elink_set_rx_filter(struct elink_params *params, uint8_t en)
void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars, uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base, uint8_t port)
elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
void elink_hw_reset_phy(struct elink_params *params)
void elink_handle_module_detect_int(struct elink_params *params)
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars)
elink_status_t elink_phy_probe(struct elink_params *params)
void elink_period_func(struct elink_params *params, struct elink_vars *vars)
uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, uint32_t shmem_base, uint32_t shmem2_base, uint8_t port)
elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[], uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled)
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, uint8_t reset_ext_phy)
void elink_link_status_update(struct elink_params *params, struct elink_vars *vars)
uint32_t elink_phy_selection(struct elink_params *params)
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC
#define ELINK_DEBUG_P2(sc, fmt, arg1, arg2)
#define ELINK_ETH_PHY_DA_TWINAX
#define ELINK_EEE_MODE_ENABLE_LPI
#define ELINK_SUPPORTED_FIBRE
enum elink_log_id elink_log_id_t
#define ELINK_SWITCH_CFG_10G
#define ELINK_DEBUG_P1(sc, fmt, arg1)
#define ELINK_SPEED_20000
#define ELINK_SUPPORTED_2500baseX_Full
#define ELINK_SPEED_10000
#define ELINK_SWITCH_CFG_1G
#define ELINK_SUPPORTED_100baseT_Half
#define ELINK_ETH_PHY_BASE_T
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC
#define ELINK_EEE_MODE_ADV_LPI
#define ELINK_LINK_CONFIG_IDX(_phy_idx)
#define ELINK_PERIODIC_FLAGS_LINK_EVENT
#define ELINK_ETH_PHY_CX4
#define ELINK_ETH_PHY_XFP_FIBER
#define ELINK_FLOW_CTRL_TX
#define ELINK_FLOW_CTRL_AUTO
#define ELINK_SUPPORTED_100baseT_Full
#define ELINK_SUPPORTED_1000baseT_Full
#define ELINK_LOOPBACK_XGXS
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC
#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC
#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
#define ELINK_ETH_PHY_NOT_PRESENT
#define ELINK_EEE_MODE_OUTPUT_TIME
#define ELINK_SUPPORTED_TP
#define ELINK_MAC_TYPE_BMAC
#define ELINK_DEBUG_P0(sc, fmt)
#define ELINK_SUPPORTED_10baseT_Full
#define ELINK_FLOW_CTRL_BOTH
#define ELINK_FLOW_CTRL_NONE
#define ELINK_SUPPORTED_10000baseT_Full
#define ELINK_MAC_TYPE_EMAC
#define ELINK_SUPPORTED_Asym_Pause
#define ELINK_SUPPORTED_Pause
#define ELINK_ETH_PHY_SFP_1G_FIBER
#define ELINK_LOOPBACK_EXT
#define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3)
#define ELINK_SUPPORTED_Autoneg
#define ELINK_SUPPORTED_10baseT_Half
#define ELINK_FLOW_CTRL_RX
#define ELINK_ETH_PHY_SFPP_10G_FIBER
#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config)
#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED
#define ELINK_SPEED_AUTO_NEG
#define ELINK_ETH_PHY_UNSPECIFIED
#define BXE_DRV_NAME_LENGTH
#define BXE_MFW_VERSION_LENGTH
#define BXE_BUS_INFO_LENGTH
#define BXE_GRC_DUMP_SIZE
#define BXE_WRITE_REG_CMD
#define BXE_REG_ACCESS_DIRECT
#define BXE_EEPROM_CMD_GET_EEPROM
#define BXE_STORMFW_VERSION_LENGTH
#define BXE_DRV_VERSION_LENGTH
#define BXE_EEPROM_CMD_SET_EEPROM
#define BXE_EEPROM_MAX_DATA_LEN
void bxe_save_statistics(struct bxe_softc *sc)
uint64_t bxe_get_counter(if_t ifp, ift_counter cnt)
void bxe_stats_init(struct bxe_softc *sc)
void bxe_stats_handle(struct bxe_softc *sc, enum bxe_stats_event event)
#define TSTORM_ASSERT_LIST_INDEX_OFFSET
#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId)
#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId)
#define CSTORM_SYNC_BLOCK_SIZE
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry)
#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId)
#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId)
#define ETH_MAX_RX_CLIENTS_E1H
#define CSTORM_STATUS_BLOCK_SIZE
#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
#define USTORM_VF_TO_PF_OFFSET(funcId)
#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId)
#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId)
#define USTORM_AGG_DATA_OFFSET
#define TSTORM_VF_TO_PF_OFFSET(funcId)
#define TSTORM_FUNC_EN_OFFSET(funcId)
#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId)
#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId)
#define XSTORM_FUNC_EN_OFFSET(funcId)
#define CSTORM_SP_SYNC_BLOCK_SIZE
#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId)
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex)
#define XSTORM_SPQ_DATA_SIZE
#define STATS_QUERY_CMD_COUNT
#define CSTORM_STATUS_BLOCK_OFFSET(sbId)
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex)
#define COMMON_ASM_INVALID_ASSERT_OPCODE
#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId)
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry)
#define USTORM_RX_PRODS_E2_OFFSET(qzoneId)
#define IP_HEADER_ALIGNMENT_PADDING
#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId)
#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId)
#define USTORM_FUNC_EN_OFFSET(funcId)
#define USTORM_ASSERT_LIST_INDEX_OFFSET
#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId)
#define CSTORM_SYNC_BLOCK_OFFSET(sbId)
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId)
#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId)
#define CSTORM_FUNC_EN_OFFSET(funcId)
#define CSTORM_VF_TO_PF_OFFSET(funcId)
#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId)
#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId)
#define XSTORM_ASSERT_LIST_INDEX_OFFSET
#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId)
#define CSTORM_SP_STATUS_BLOCK_SIZE
#define XSTORM_VF_TO_PF_OFFSET(funcId)
#define XSTORM_SPQ_PROD_OFFSET(funcId)
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry)
#define CSTORM_IGU_MODE_OFFSET
#define USTORM_AGG_DATA_SIZE
#define XSTORM_SPQ_DATA_OFFSET(funcId)
#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId)
#define CSTORM_ASSERT_LIST_INDEX_OFFSET
#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry)
#define ETH_TX_BD_FLAGS_L4_CSUM
#define DRV_STATUS_EEE_NEGOTIATION_RESULTS
#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
#define DRV_STATUS_DRV_INFO_REQ
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT
#define BCM_5710_FW_REVISION_VERSION
#define DRV_MSG_CODE_DRV_INFO_ACK
#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG
#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK
#define DRV_MSG_CODE_EEE_RESULTS_ACK
#define FUNC_MF_CFG_FUNC_DISABLED
#define IGU_CTRL_REG_ADDRESS_SHIFT
#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT
#define SPE_HDR_T_CONN_TYPE
#define FUNC_MF_CFG_AFEX_VLAN_MASK
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
#define BCM_5710_FW_MINOR_VERSION
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
#define DRV_STATUS_SET_MF_BW
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
#define MCP_PULSE_SEQ_MASK
#define SHR_MEM_VALIDITY_MB
#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
#define PORT_FEATURE_LINK_SPEED_10M_FULL
#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
#define FUNC_MF_CFG_UPPERMAC_DEFAULT
#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
#define DRV_FLAGS_CAPABILITIES_LOADED_L2
#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT
@ RAMROD_CMD_ID_ETH_CLIENT_SETUP
@ RAMROD_CMD_ID_ETH_FILTER_RULES
@ RAMROD_CMD_ID_ETH_CLIENT_UPDATE
@ RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
@ RAMROD_CMD_ID_ETH_MULTICAST_RULES
@ RAMROD_CMD_ID_ETH_EMPTY
@ RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
@ RAMROD_CMD_ID_ETH_FORWARD_SETUP
@ RAMROD_CMD_ID_ETH_SET_MAC
@ RAMROD_CMD_ID_ETH_TERMINATE
@ RAMROD_CMD_ID_ETH_RSS_UPDATE
#define DRV_MSG_CODE_LOAD_REQ
#define DMAE_CMD_DST_RESET
#define PORT_FEATURE_FLOW_CONTROL_SHIFT
#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT
#define FUNC_MF_CFG_FUNC_HIDE
#define DMAE_CMD_C_TYPE_ENABLE
#define ETH_TX_BD_FLAGS_IPV6
#define PORT_FEATURE_LINK_SPEED_10M_HALF
#define ETH_TX_BD_FLAGS_START_BD
#define IGU_CTRL_REG_FID_SHIFT
#define PORT_FEATURE_LINK_SPEED_100M_HALF
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK
#define PORT_FEATURE_LINK_SPEED_1G
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
#define DOORBELL_HDR_T_DB_TYPE
#define REQ_BC_VER_4_INITIATE_FLR
#define DRV_INFO_CONTROL_VER_MASK
#define FUNC_MF_CFG_PROTOCOL_MASK
#define IGU_REGULAR_BCLEANUP
#define FW_MSG_CODE_DRV_LOAD_PORT
#define SPE_HDR_T_CONN_TYPE_SHIFT
#define SHARED_HW_CFG_FAN_FAILURE_ENABLED
#define DRV_MSG_CODE_DCC_FAILURE
#define FW_MSG_CODE_DRV_LOAD_COMMON
#define DRV_INFO_CONTROL_OP_CODE_SHIFT
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W
#define LINK_STATUS_SERDES_LINK
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
#define IGU_REGULAR_CLEANUP_TYPE_SHIFT
#define ETH_TX_BD_FLAGS_IP_CSUM
#define PORT_FEAT_CFG_AUTOGREEEN_ENABLED
#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
#define DMAE_CMD_SRC_RESET
#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
#define DRV_FLAGS_PORT_MASK
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE
#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
#define PORT_FEATURE_LINK_SPEED_20G
#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK
#define SHARED_HW_CFG_LED_MODE_SHIFT
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT
#define SHARED_HW_CFG_LED_MODE_MASK
#define PORT_FEATURE_LINK_SPEED_MASK
#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA
#define DRV_STATUS_DCC_EVENT_MASK
#define ETH_FAST_PATH_RX_CQE_TYPE
#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
#define PORT_FEATURE_LINK_SPEED_2_5G
@ EVENT_RING_OPCODE_START_TRAFFIC
@ EVENT_RING_OPCODE_FUNCTION_START
@ EVENT_RING_OPCODE_CFC_DEL
@ EVENT_RING_OPCODE_SET_MAC
@ EVENT_RING_OPCODE_FILTERS_RULES
@ EVENT_RING_OPCODE_FUNCTION_STOP
@ EVENT_RING_OPCODE_MULTICAST_RULES
@ EVENT_RING_OPCODE_RSS_UPDATE_RULES
@ EVENT_RING_OPCODE_FUNCTION_UPDATE
@ EVENT_RING_OPCODE_STAT_QUERY
@ EVENT_RING_OPCODE_CLASSIFICATION_RULES
@ EVENT_RING_OPCODE_FORWARD_SETUP
@ EVENT_RING_OPCODE_STOP_TRAFFIC
#define DRV_MSG_CODE_LOAD_DONE
#define DRV_PULSE_SEQ_MASK
#define DMAE_CMD_DST_SHIFT
#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT
#define FW_MSG_SEQ_NUMBER_MASK
#define SPE_HDR_T_FUNCTION_ID
#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
#define PORT_FEATURE_LINK_SPEED_100M_FULL
#define SPE_HDR_T_CMD_ID_SHIFT
#define DRV_PULSE_ALWAYS_ALIVE
#define FUNC_MF_CFG_E1HOV_TAG_MASK
#define LINK_STATUS_LINK_UP
#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT
#define FW_MSG_CODE_DRV_UNLOAD_COMMON
#define ETH_TX_START_BD_HDR_NBDS_SHIFT
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE
#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN
#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
#define DRV_MSG_CODE_INITIATE_FLR
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
#define SHR_MEM_VALIDITY_DEV_INFO
#define PARSING_FLAGS_INNER_VLAN_EXIST
#define SHARED_HW_CFG_FAN_FAILURE_MASK
#define ETH_TX_PARSE_BD_E2_LSO_MSS
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN
#define FUNC_MF_CFG_MAX_BW_MASK
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
#define DMAE_CMD_E1HVN_SHIFT
#define IGU_CTRL_REG_TYPE_SHIFT
#define FUNC_MF_CFG_AFEX_VLAN_SHIFT
#define MACP_FUNC_CFG_FLAGS_MASK
#define FUNC_MF_CFG_MIN_BW_MASK
#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT
#define BCM_5710_FW_ENGINEERING_VERSION
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT
#define IGU_REGULAR_CLEANUP_SET
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK
#define DRV_MSG_CODE_SET_MF_BW_ACK
#define FW_MSG_CODE_DRV_LOAD_REFUSED
#define DRV_STATUS_DCC_DISABLE_ENABLE_PF
#define PORT_HW_CFG_PHY_SWAPPED_ENABLED
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
#define FUNC_MF_CFG_PROTOCOL_ISCSI
#define DMAE_CMD_ERR_POLICY_SHIFT
#define DRV_MSG_SEQ_NUMBER_MASK
#define MACP_FUNC_CFG_FLAGS_ENABLED
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW
#define PORT_FEATURE_LINK_SPEED_AUTO
#define BCM_5710_FW_MAJOR_VERSION
#define MACP_FUNC_CFG_FLAGS_ETHERNET
#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
#define DRV_INFO_CONTROL_OP_CODE_MASK
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
#define SHMEM_MF_CFG_ADDR_NONE
#define DMAE_CMD_SRC_SHIFT
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
#define ETH_TX_START_BD_HDR_NBDS
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG
#define FW_MSG_CODE_DRV_UNLOAD_PORT
#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION
#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
#define FW_MSG_CODE_DRV_LOAD_FUNCTION
#define FUNC_MF_CFG_MIN_BW_SHIFT
#define DMAE_CMD_C_DST_SHIFT
#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG
#define FUNC_MF_CFG_MAX_BW_SHIFT
#define ETH_TX_BD_FLAGS_SW_LSO
#define PORT_FEATURE_LINK_SPEED_10G_CX4
#define FUNC_MF_CFG_E1HOV_TAG_SHIFT
#define PORT_FEATURE_FLOW_CONTROL_MASK
#define PORT_FEATURE_CONNECTED_SWITCH_MASK
#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF
#define DRV_MSG_CODE_DCC_OK
#define FUNC_MF_CFG_PROTOCOL_FCOE
#define DRV_MSG_CODE_UNLOAD_DONE
#define SPE_HDR_T_FUNCTION_ID_SHIFT
#define DRV_MSG_CODE_DRV_INFO_NACK
#define DMAE_CMD_DST_VN_SHIFT
#define ETH_TX_BD_FLAGS_IS_UDP
#define MISC_AEU_ENABLE_MCP_PRTY_BITS
#define ILT_CLIENT_SKIP_MEM
static void ecore_clear_blocks_parity(struct bxe_softc *sc)
static void ecore_enable_blocks_parity(struct bxe_softc *sc)
static void ecore_init_cmng(const struct cmng_init_input *input_data, struct cmng_init *ram_data)
static void ecore_disable_blocks_parity(struct bxe_softc *sc)
static void ecore_init_str_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data, uint32_t len)
static void ecore_ilt_client_init_op_ilt(struct bxe_softc *sc, struct ecore_ilt *ilt, struct ilt_client_info *ilt_cli, uint8_t initop)
static void ecore_ilt_init_op(struct bxe_softc *sc, uint8_t initop)
static void ecore_init_fill(struct bxe_softc *sc, uint32_t addr, int fill, uint32_t len, uint8_t wb)
static void ecore_qm_init_ptr_table(struct bxe_softc *sc, int qm_cid_count, uint8_t initop)
#define QM_QUEUES_PER_FUNC
static void ecore_init_ind_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data, uint32_t len)
static void ecore_ilt_boundry_init_op(struct bxe_softc *sc, struct ilt_client_info *ilt_cli, uint32_t ilt_start, uint8_t initop)
static int ecore_ilt_mem_op(struct bxe_softc *sc, uint8_t memop)
static void ecore_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
static void ecore_init_pxp_arb(struct bxe_softc *sc, int r_order, int w_order)
static void ecore_ilt_init_page_size(struct bxe_softc *sc, uint8_t initop)
static void ecore_qm_init_cid_count(struct bxe_softc *sc, int qm_cid_count, uint8_t initop)
#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK
#define ETH_STAT_INFO_VERSION_LEN
#define FEATURE_ETH_LSO_MASK
#define PXP2_REG_RQ_ONCHIP_AT
#define CCM_REG_CCM_INT_MASK
#define PRS_REG_MUST_HAVE_HDRS_PORT_1
#define PRS_REG_HDRS_AFTER_BASIC_PORT_0
#define CFC_REG_AC_INIT_DONE
#define CDU_REG_CDU_GLOBAL_PARAMS
#define PXP2_REG_PXP2_INT_STS_CLR_0
#define PXP2_REG_RD_SR_CNT
#define PBF_REG_P1_TQ_LINES_FREED_CNT
#define PCICFG_GRC_ADDRESS
#define BRB1_REG_BRB1_INT_MASK
#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0
#define MISC_REG_GPIO_INT
#define NIG_REG_DEBUG_PACKET_LB
#define TSEM_REG_VFPF_ERR_NUM
#define IGU_CMD_ATTN_BIT_SET_UPPER
#define NIG_REG_NIG_INT_STS_CLR_0
#define NIG_REG_LLFC_OUT_EN_0
#define MISC_REGISTERS_GPIO_INPUT_HI_Z
#define MISC_REG_UNPREPARED
#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR
#define HW_PRTY_ASSERT_SET_3
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0
#define NIG_REG_LLH0_BRB1_DRV_MASK
#define TM_REG_LIN0_SCAN_TIME
#define ATC_REG_ATC_INT_STS_CLR
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
#define MISC_REGISTERS_RESET_REG_1_SET
#define TM_REG_LIN0_NUM_SCANS
#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
#define DMAE_REG_DMAE_INT_MASK
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
#define IGU_REG_LEADING_EDGE_LATCH
#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
#define TCM_REG_TCM_INT_MASK
#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
#define HW_LOCK_RESOURCE_RESET
#define DORQ_REG_NORM_CID_OFST
#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
#define PBF_REG_P4_INIT_CRD
#define MISC_REGISTERS_RESET_REG_2_UMAC1
#define PXP2_REG_PGL_ADDR_90_F1
#define MISC_REGISTERS_GPIO_FLOAT_POS
#define MISC_REG_CHIP_REV
#define BRB1_REG_NUM_OF_FULL_BLOCKS
#define PGLUE_B_REG_PGLUE_B_INT_STS
#define IGU_REG_ATTN_MSG_ADDR_L
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1
#define PBF_REG_P4_CREDIT
#define HW_LOCK_MAX_RESOURCE_VALUE
#define PXP2_REG_PGL_PRETEND_FUNC_F0
#define MISC_SPIO_SET_POS
#define MISC_REG_AEU_GENERAL_ATTN_6
#define PXP2_REG_RD_PORT_IS_IDLE_1
#define PRS_REG_A_PRSU_20
#define PXP2_REG_RQ_CFG_DONE
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0
#define SRC_REG_KEYSEARCH_1
#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
#define NIG_REG_LLH1_BRB1_NOT_MCP
#define CDU_REGION_NUMBER_UCM_AG
#define HC_REG_LEADING_EDGE_0
#define MISC_REG_WC0_CTRL_PHY_ADDR
#define HW_LOCK_RESOURCE_PORT0_ATT_MASK
#define NIG_REG_LLH0_CLS_TYPE
#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
#define MCPR_NVM_COMMAND_DONE
#define MISC_REG_SPIO_INT
#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
#define MISC_REG_CHIP_TYPE_57811_MASK
#define HW_LOCK_RESOURCE_RECOVERY_REG
#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
#define TM_REG_LIN0_SCAN_ON
#define PXP2_REG_RD_START_INIT
#define IGU_REG_MAPPING_MEMORY
#define NIG_REG_LLH0_FUNC_VLAN_ID
#define PRS_REG_MUST_HAVE_HDRS
#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
#define NIG_REG_BMAC0_REGS_OUT_EN
#define CFC_REG_NUM_LCIDS_INSIDE_PF
#define MISC_REGISTERS_GPIO_INT_CLR_POS
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
#define HW_PRTY_ASSERT_SET_1
#define NIG_REG_EGRESS_DRAIN0_MODE
#define PRS_REG_TAG_ETHERTYPE_0
#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
#define HW_LOCK_RESOURCE_SPIO
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
#define MISC_REGISTERS_RESET_REG_1_RST_BRB1
#define MISC_REGISTERS_RESET_REG_1_RST_PXP
#define BIGMAC_REGISTER_BMAC_CONTROL
#define PXP2_REG_RD_SRC_SWAP_MODE
#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
#define SRC_REG_KEYSEARCH_7
#define MCPR_NVM_CFG4_FLASH_SIZE
#define BRB1_REG_PAUSE_LOW_THRESHOLD_0
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1
#define MCPR_NVM_SW_ARB_ARB_ARB1
#define PXP2_REG_RD_QM_SWAP_MODE
#define UMAC_REG_COMMAND_CONFIG
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
#define COMMAND_REG_ATTN_BITS_CLR
#define NIG_REG_LLH1_CLS_TYPE
#define BAR_TSTRORM_INTMEM
#define MISC_REG_GRC_TIMEOUT_ATTN
#define USDM_REG_USDM_INT_MASK_1
#define CSEM_REG_VFPF_ERR_NUM
#define CFC_REG_WEAK_ENABLE_PF
#define NIG_REG_P1_HDRS_AFTER_BASIC
#define MISC_REGISTERS_GPIO_OUTPUT_LOW
#define PXP2_REG_RQ_TM_ENDIAN_M
#define DORQ_REG_DORQ_INT_MASK
#define QM_REG_QM_INT_MASK
#define PXPCS_TL_CONTROL_5
#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q
#define XSEM_REG_PASSIVE_BUFFER
#define PXP2_REG_RQ_DRAM_ALIGN
#define IGU_NORM_NDSB_NUM_SEGS
#define PBF_REG_P1_INIT_CRD
#define PBF_REG_P4_TQ_LINES_FREED_CNT
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
#define MISC_SPIO_CLR_POS
#define BIGMAC2_REGISTER_BMAC_CONTROL
#define MCP_REG_MCPR_NVM_ADDR
#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
#define IGU_FID_PF_NUM_MASK
#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
#define HW_LOCK_RESOURCE_MDIO
#define MISC_REG_AEU_GENERAL_ATTN_11
#define MISC_REG_GENERIC_CR_0
#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
#define MCPR_NVM_SW_ARB_ARB_REQ_SET1
#define MCP_REG_MCPR_NVM_COMMAND
#define PRS_REG_TAG_LEN_0
#define HW_INTERRUT_ASSERT_SET_0
#define TM_REG_LIN0_VNIC_UC
#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
#define IGU_REG_SB_INT_BEFORE_MASK_MSB
#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
#define IGU_REG_SB_MASK_LSB
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
#define IGU_REG_ATTENTION_ACK_BITS
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
#define PRS_REG_MUST_HAVE_HDRS_PORT_0
#define HC_CONFIG_0_REG_BLOCK_DISABLE_0
#define MISC_REGISTERS_RESET_REG_2_RST_ATC
#define PXP2_REG_PGL_ADDR_88_F1
#define MCP_REG_MCPR_ACCESS_LOCK
#define IGU_REG_PCI_PF_MSI_EN
#define USEM_REG_PASSIVE_BUFFER
#define MISC_REGISTERS_RESET_REG_2_CLEAR
#define MISC_REGISTERS_RESET_REG_2_XMAC
#define SRC_REG_KEYSEARCH_8
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
#define MCP_REG_MCPR_NVM_ACCESS_ENABLE
#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
#define NIG_REG_NIG_EMAC0_EN
#define IGU_BC_DSB_NUM_SEGS
#define MISC_REG_AEU_MASK_ATTN_FUNC_1
#define MISC_REG_AEU_GENERAL_ATTN_7
#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT
#define HW_LOCK_RESOURCE_NVRAM
#define NIG_REG_XGXS_SERDES0_MODE_SEL
#define MCPR_NVM_COMMAND_WR
#define PBF_REG_P4_TQ_OCCUPANCY
#define MISC_REG_AEU_GENERAL_MASK
#define PRS_REG_HDRS_AFTER_TAG_0
#define IGU_REG_PROD_CONS_MEMORY
#define IGU_REG_MAPPING_MEMORY_SIZE
#define PXP2_REG_PGL_ADDR_88_F0
#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
#define PBF_REG_P0_PAUSE_ENABLE
#define PB_REG_PB_INT_MASK
#define HC_REG_TRAILING_EDGE_0
#define MISC_REG_AEU_CLR_LATCH_SIGNAL
#define HC_CONFIG_0_REG_INT_LINE_EN_0
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
#define PBF_REG_TQ_OCCUPANCY_Q1
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
#define HC_CONFIG_1_REG_BLOCK_DISABLE_1
#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
#define BAR_CSTRORM_INTMEM
#define IGU_BC_NDSB_NUM_SEGS
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
#define PXP2_REG_RQ_SRC_ENDIAN_M
#define IGU_PF_CONF_INT_LINE_EN
#define MISC_REG_DRIVER_CONTROL_7
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1
#define MISC_REG_GRC_RSV_ATTN
#define PXP2_REG_PXP2_INT_MASK_1
#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
#define MISC_SPIO_INT_OLD_SET_POS
#define PXP2_REG_PGL_ADDR_8C_F1
#define PXP2_REG_RQ_HC_ENDIAN_M
#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT
#define MISC_REGISTERS_GPIO_3
#define MISC_REGISTERS_GPIO_CLR_POS
#define MCPR_NVM_ACCESS_ENABLE_EN
#define PGLUE_B_REG_LATCHED_ERRORS_CLR
#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
#define HW_PRTY_ASSERT_SET_4
#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET
#define CSEM_REG_PASSIVE_BUFFER
#define DORQ_REG_DORQ_INT_STS_CLR
#define MISC_REGISTERS_RESET_REG_2_SET
#define PXP2_REG_PXP2_INT_STS_1
#define TM_REG_LIN0_MAX_ACTIVE_CID
#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
#define IGU_REG_PBA_STATUS_MSB
#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
#define IGU_REG_PBA_STATUS_LSB
#define VFC_REG_MEMORIES_RST
#define PXP2_REG_RD_INIT_DONE
#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
#define PBF_REG_PBF_INT_MASK
#define BAR_XSTRORM_INTMEM
#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT
#define TSDM_REG_ENABLE_IN1
#define MCP_REG_MCPR_NVM_READ
#define PXP2_REG_PGL_ADDR_8C_F0
#define BRB1_REG_MAC_GUARANTIED_0
#define ME_REG_ABS_PF_NUM
#define PBF_REG_P0_TQ_OCCUPANCY
#define MISC_REG_AEU_GENERAL_ATTN_1
#define PBF_REG_TQ_OCCUPANCY_LB_Q
#define PBF_REG_INIT_CRD_LB_Q
#define USEM_REG_VFPF_ERR_NUM
#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
#define IGU_PF_CONF_ATTN_BIT_EN
#define CFC_REG_LL_INIT_DONE
#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
#define NIG_REG_MASK_INTERRUPT_PORT0
#define MISC_REGISTERS_GPIO_OUTPUT_HIGH
#define MISC_REGISTERS_RESET_REG_1_RST_HC
#define MISC_SPIO_OUTPUT_HIGH
#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
#define XSEM_REG_FAST_MEMORY
#define NIG_REG_MASK_INTERRUPT_PORT1
#define NIG_REG_STAT2_BRB_OCTET
#define MISC_REGISTERS_RESET_REG_1_RST_PXPV
#define CFC_REG_CFC_INT_MASK
#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
#define TSDM_REG_TSDM_INT_MASK_1
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0
#define NIG_REG_INGRESS_BMAC0_MEM
#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)
#define EVEREST_GEN_ATTN_IN_USE_MASK
#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
#define SRC_REG_KEYSEARCH_4
#define IGU_REG_COMMAND_REG_32LSB_DATA
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
#define PBF_REG_INIT_CRD_Q0
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0
#define IGU_PF_CONF_FUNC_EN
#define NIG_REG_PORT_SWAP
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
#define PXP_REG_HST_DISCARD_INTERNAL_WRITES
#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
#define NIG_REG_PAUSE_ENABLE_0
#define TM_REG_EN_LINEAR0_TIMER
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1
#define PRS_REG_HDRS_AFTER_BASIC
#define PXP_REG_HST_DISCARD_DOORBELLS
#define TSEM_REG_PASSIVE_BUFFER
#define TSEM_REG_FAST_MEMORY
#define PXP2_REG_RQ_QM_ENDIAN_M
#define IGU_REG_MAPPING_MEMORY_VALID
#define SRC_REG_KEYSEARCH_5
#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
#define PXP2_REG_RD_CDURD_SWAP_MODE
#define PXP_REG_PXP_INT_STS_CLR_0
#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
#define HC_REG_ATTN_MSG1_ADDR_L
#define XSDM_REG_OPERATION_GEN
#define PXP2_REG_PXP2_INT_STS_0
#define CSDM_REG_CSDM_INT_MASK_1
#define HW_INTERRUT_ASSERT_SET_1
#define CDU_REGION_NUMBER_XCM_AG
#define IGU_NORM_DSB_NUM_SEGS
#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
#define NIG_REG_XGXS0_CTRL_PHY_ADDR
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
#define PGLUE_B_REG_TAGS_63_32
#define IGU_PF_CONF_SINGLE_ISR_EN
#define MISC_REG_AEU_GENERAL_ATTN_9
#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
#define PXPCS_TL_FUNC678_STAT
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
#define SRC_REG_KEYSEARCH_6
#define PBF_REG_P1_TQ_OCCUPANCY
#define PXP2_REG_RD_DISABLE_INPUTS
#define SRC_REG_KEYSEARCH_3
#define MISC_REG_PORT4MODE_EN
#define PXP2_REG_PGL_EXP_ROM2
#define PBF_REG_TQ_LINES_FREED_CNT_Q0
#define PXP2_REG_RQ_DBG_ENDIAN_M
#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
#define HW_PRTY_ASSERT_SET_2
#define NIG_REG_LLH0_BRB1_DRV_MASK_MF
#define IGU_CMD_INT_ACK_BASE
#define PXP2_REG_RQ_DRAM_ALIGN_SEL
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
#define MISC_REG_AEU_GENERAL_ATTN_4
#define TM_REG_TM_INT_MASK
#define PXP2_REG_PGL_ADDR_94_F1
#define IGU_FID_ENCODE_IS_PF
#define MISC_REGISTERS_RESET_REG_2_MSTAT1
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
#define MISC_REGISTERS_RESET_REG_1_RST_DORQ
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
#define HW_PRTY_ASSERT_SET_0
#define VFC_MEMORIES_RST_REG_CAM_RST
#define HC_REG_MAIN_MEMORY_SIZE
#define IGU_REG_RESET_MEMORIES
#define QM_REG_SOFT_RESET
#define BRB1_REG_MAC_GUARANTIED_1
#define XSEM_REG_VFPF_ERR_NUM
#define IGU_NORM_BASE_DSB_PROD
#define PBF_REG_MUST_HAVE_HDRS
#define BAR_USTRORM_INTMEM
#define PXP2_REG_RQ_DRAM_ALIGN_RD
#define PXP_REG_PXP_INT_MASK_0
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
#define PXP_REG_PXP_INT_STS_CLR_1
#define PBF_REG_P0_ARB_THRSH
#define MISC_REG_AEU_GENERAL_ATTN_3
#define MCPR_NVM_COMMAND_FIRST
#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
#define MCP_REG_MCPR_NVM_WRITE
#define ME_REG_PF_NUM_SHIFT
#define IGU_REG_PCI_PF_MSIX_EN
#define IGU_REG_ATTN_MSG_ADDR_H
#define MISC_SPIO_FLOAT_POS
#define PBF_REG_TQ_OCCUPANCY_Q0
#define IGU_BC_BASE_DSB_PROD
#define ME_REG_ABS_PF_NUM_SHIFT
#define NIG_REG_LLH1_MF_MODE
#define SRC_REG_KEYSEARCH_2
#define AEU_INPUTS_ATTN_BITS_SPIO5
#define USDM_REG_USDM_INT_MASK_0
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
#define PXP2_REG_RQ_CDU_ENDIAN_M
#define CFC_REG_CAM_INIT_DONE
#define NIG_REG_P0_HDRS_AFTER_BASIC
#define MISC_REGISTERS_GPIO_INT_SET_POS
#define MCPR_ACCESS_LOCK_LOCK
#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
#define SRC_REG_KEYSEARCH_0
#define MISC_REG_AEU_MASK_ATTN_FUNC_0
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
#define IGU_PF_CONF_MSI_MSIX_EN
#define XMAC_REG_PFC_CTRL_HI
#define COMMAND_REG_ATTN_BITS_SET
#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT
#define PBF_REG_P0_TQ_LINES_FREED_CNT
#define PXP2_REG_RQ_DISABLE_INPUTS
#define PXP2_REG_RD_BLK_CNT
#define MISC_REG_RESET_REG_2
#define PXP2_REG_PGL_ADDR_90_F0
#define IGU_REG_PENDING_BITS_STATUS
#define MISC_REG_RESET_REG_1
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0
#define PXP2_REG_PXP2_INT_MASK_0
#define IGU_REG_SB_MASK_MSB
#define CDU_REG_CDU_INT_MASK
#define PXP2_REG_RQ_ONCHIP_AT_B0
#define PXP2_REG_PGL_PRETEND_FUNC_F1
#define DORQ_REG_DPM_CID_OFST
#define NIG_REG_STRAP_OVERRIDE
#define PBF_REG_TAG_LEN_0
#define PBF_REG_DISABLE_PF
#define NIG_REG_PRS_REQ_IN_EN
#define PXP2_REG_RD_TM_SWAP_MODE
#define XSDM_REG_XSDM_INT_MASK_0
#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
#define MISC_REG_GENERIC_CR_1
#define VFC_MEMORIES_RST_REG_RAM_RST
#define IGU_REG_COMMAND_REG_CTRL
#define MISC_REG_SHARED_MEM_ADDR
#define PBF_REG_INIT_CRD_Q1
#define PBF_REG_HDRS_AFTER_TAG_0
#define MISC_REGISTERS_RESET_REG_2_RST_GRC
#define NIG_REG_LLH0_FUNC_EN
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
#define MISC_REG_AEU_GENERAL_ATTN_12
#define MISC_REG_AEU_GENERAL_ATTN_5
#define HW_INTERRUT_ASSERT_SET_2
#define IGU_REG_SB_INT_BEFORE_MASK_LSB
#define MISC_REGISTERS_GPIO_FLOAT
#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
#define MCPR_NVM_ACCESS_ENABLE_WR_EN
#define MISC_SPIO_INPUT_HI_Z
#define TSEM_REG_TSEM_INT_MASK_1
#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
#define SRC_REG_KEYSEARCH_9
#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
#define NIG_REG_SERDES0_CTRL_PHY_ADDR
#define QM_REG_PF_USG_CNT_0
#define MCP_REG_MCPR_NVM_CFG4
#define PBF_REG_TAG_ETHERTYPE_0
#define MCPR_NVM_COMMAND_DOIT
#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
#define NIG_REG_LLH0_BRB1_NOT_MCP
#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
#define NIG_REG_LLH_MF_MODE
#define MISC_REGISTERS_GPIO_SET_POS
#define HC_REG_ATTN_MSG0_ADDR_L
#define XCM_REG_XCM_INT_MASK
#define PXP_REG_PXP_INT_MASK_1
#define PXP2_REG_RQ_RBC_DONE
#define MISC_REG_CHIP_NUM
#define PBF_REG_CREDIT_LB_Q
#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
#define MISC_REGISTERS_GPIO_PORT_SHIFT
#define PXP2_REG_PGL_TAGS_LIMIT
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE
#define PRS_REG_NUM_OF_PACKETS
#define PRS_REG_E1HOV_MODE
#define CFC_REG_CFC_INT_STS_CLR
#define MISC_SPIO_OUTPUT_LOW
#define MISC_REGISTERS_RESET_REG_2_RST_RBCN
#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT
#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
#define UCM_REG_UCM_INT_MASK
#define MISC_REGISTERS_RESET_REG_2_PGLC
#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
#define PRS_REG_HDRS_AFTER_BASIC_PORT_1
#define HW_LOCK_RESOURCE_GPIO
#define IGU_CMD_ATTN_BIT_CLR_UPPER
#define IGU_REG_BLOCK_CONFIGURATION
#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
#define PXPCS_TL_FUNC345_STAT
#define MISC_REGISTERS_RESET_REG_1_CLEAR
#define TSDM_REG_TSDM_INT_MASK_0
#define PXP2_REG_PGL_ADDR_94_F0
#define IGU_REG_PF_CONFIGURATION
#define IGU_REG_PCI_PF_MSIX_FUNC_MASK
#define MISC_REGISTERS_RESET_REG_2_UMAC0
#define IGU_FID_ENCODE_IS_PF_SHIFT
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0
#define PBF_REG_P1_CREDIT
#define IGU_CMD_E2_PROD_UPD_BASE
#define PBF_REG_P0_CREDIT
#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
#define NIG_REG_LLFC_ENABLE_0
#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
#define MISC_REG_SPIO_EVENT_EN
#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0
#define MISC_REG_PORT4MODE_EN_OVWR
#define MISC_REG_CHIP_TYPE
#define IGU_REG_TRAILING_EDGE_LATCH
#define NIG_REG_INGRESS_EOP_LB_FIFO
#define MISC_REGISTERS_RESET_REG_2_MSTAT0
#define PBF_REG_P0_INIT_CRD
#define NIG_REG_LLH_E1HOV_MODE
#define XSDM_REG_XSDM_INT_MASK_1
#define PBF_REG_HDRS_AFTER_BASIC
#define MCP_REG_MCPR_NVM_SW_ARB
#define MISC_REG_DRIVER_CONTROL_1
#define MISC_REG_AEU_GENERAL_ATTN_10
#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
#define DORQ_REG_PF_USAGE_CNT
#define EVEREST_LATCHED_ATTN_IN_USE_MASK
#define HC_REG_MAIN_MEMORY
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
#define MISC_REG_AEU_GENERAL_ATTN_8
#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
#define NIG_REG_INGRESS_BMAC1_MEM
#define HW_LOCK_RESOURCE_DRV_FLAGS
#define PBF_REG_TQ_LINES_FREED_CNT_Q1
#define MCPR_NVM_COMMAND_LAST
#define PXP2_REG_RD_PORT_IS_IDLE_0
#define PBF_REG_CREDIT_Q0
#define MISC_REG_AEU_GENERAL_ATTN_2
#define CSDM_REG_CSDM_INT_MASK_0
#define ATC_REG_ATC_INIT_DONE
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0
#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
#define HC_REG_HC_PRTY_STS_CLR
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
#define NIG_REG_INGRESS_EOP_LB_EMPTY
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
#define PBF_REG_CREDIT_Q1
#define HC_REG_COMMAND_REG
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
int ecore_config_rx_mode(struct bxe_softc *sc, struct ecore_rx_mode_ramrod_params *p)
void ecore_init_queue_obj(struct bxe_softc *sc, struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, uint8_t cid_cnt, uint8_t func_id, void *rdata, ecore_dma_addr_t rdata_mapping, unsigned long type)
void ecore_init_rss_config_obj(struct bxe_softc *sc, struct ecore_rss_config_obj *rss_obj, uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, int state, unsigned long *pstate, ecore_obj_type type)
int ecore_config_vlan_mac(struct bxe_softc *sc, struct ecore_vlan_mac_ramrod_params *p)
void ecore_init_mac_obj(struct bxe_softc *sc, struct ecore_vlan_mac_obj *mac_obj, uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, ecore_dma_addr_t rdata_mapping, int state, unsigned long *pstate, ecore_obj_type type, struct ecore_credit_pool_obj *macs_pool)
int ecore_func_state_change(struct bxe_softc *sc, struct ecore_func_state_params *params)
void ecore_init_vlan_credit_pool(struct bxe_softc *sc, struct ecore_credit_pool_obj *p, uint8_t func_id, uint8_t func_num)
void ecore_init_mac_credit_pool(struct bxe_softc *sc, struct ecore_credit_pool_obj *p, uint8_t func_id, uint8_t func_num)
void ecore_init_rx_mode_obj(struct bxe_softc *sc, struct ecore_rx_mode_obj *o)
int ecore_queue_state_change(struct bxe_softc *sc, struct ecore_queue_state_params *params)
void ecore_init_mcast_obj(struct bxe_softc *sc, struct ecore_mcast_obj *mcast_obj, uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, int state, unsigned long *pstate, ecore_obj_type type)
enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc, struct ecore_func_sp_obj *o)
void ecore_init_func_obj(struct bxe_softc *sc, struct ecore_func_sp_obj *obj, void *rdata, ecore_dma_addr_t rdata_mapping, void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, struct ecore_func_sp_drv_ops *drv_iface)
int ecore_config_rss(struct bxe_softc *sc, struct ecore_config_rss_params *p)
int ecore_config_mcast(struct bxe_softc *sc, struct ecore_mcast_ramrod_params *p, enum ecore_mcast_cmd cmd)
#define BIT_VEC64_CLEAR_BIT(vec64, idx)
#define ECORE_LIST_INIT(_list)
#define BIT_VEC64_ELEM_ONE_MASK
@ ECORE_Q_CMD_SETUP_TX_ONLY
@ ECORE_Q_FLG_PCSUM_ON_PKT
@ ECORE_Q_FLG_LEADING_RSS
@ ECORE_ACCEPT_ALL_MULTICAST
@ ECORE_ACCEPT_ALL_UNICAST
@ ECORE_F_CMD_SWITCH_UPDATE
#define ECORE_LIST_PUSH_TAIL(_elem, _list)
@ ECORE_FILTER_RSS_CONF_PENDING
@ ECORE_FILTER_MCAST_PENDING
@ ECORE_FILTER_RX_MODE_PENDING
@ ECORE_FILTER_RX_MODE_SCHED
@ ECORE_FILTER_MAC_PENDING
#define BIT_VEC64_ELEM_SZ
#define BIT_VEC64_ELEM_SHIFT
#define ECORE_MULTI_TX_COS
#define ECORE_LIST_FIRST_ENTRY(_list, cast, _link)
struct resource * resource
bus_space_handle_t handle
uint16_t pcie_msix_cap_reg
uint16_t pcie_pcie_cap_reg
uint16_t pcie_msi_cap_reg
struct bxe_mf_info mf_info
char drv_version[BXE_DRV_VERSION_LENGTH]
char mfw_version[BXE_MFW_VERSION_LENGTH]
char drv_name[BXE_DRV_NAME_LENGTH]
char stormfw_version[BXE_STORMFW_VERSION_LENGTH]
char bus_info[BXE_BUS_INFO_LENGTH]
uint32_t rx_ofld_frames_csum_tcp_udp
uint32_t tx_request_link_down_failures
uint32_t tx_max_drbr_queue_depth
uint32_t bd_avail_too_less_failures
uint32_t tx_frames_deferred
uint32_t tx_hw_queue_full
uint32_t tx_window_violation_std
uint32_t nsegs_path1_errors
uint32_t rx_hw_csum_errors
uint32_t tx_ofld_frames_lso_hdr_splits
uint32_t mbuf_rx_tpa_mapping_failed
uint32_t tx_encap_failures
uint32_t mbuf_rx_sge_mapping_failed
uint32_t tx_ofld_frames_csum_udp
uint32_t mbuf_rx_bd_alloc_failed
uint32_t mbuf_rx_sge_alloc_failed
uint32_t nsegs_path2_errors
uint32_t rx_ofld_frames_csum_ip
uint32_t rx_budget_reached
uint32_t tx_queue_full_return
uint32_t tx_ofld_frames_csum_ip
uint32_t tx_ofld_frames_lso
uint32_t rx_jumbo_sge_pkts
uint32_t mbuf_defrag_failures
uint32_t rx_erroneous_jumbo_sge_pkts
uint32_t tx_hw_max_queue_depth
uint32_t mbuf_defrag_attempts
uint32_t tx_window_violation_tso
uint32_t bxe_tx_mq_sc_state_failures
uint32_t mbuf_rx_bd_mapping_failed
uint32_t tx_chain_lost_mbuf
uint32_t tx_dma_mapping_failure
uint32_t tx_ofld_frames_csum_tcp
uint32_t mbuf_rx_tpa_alloc_failed
uint32_t rx_bxe_service_rxsgl
uint32_t recoverable_error
uint32_t unrecoverable_error
uint32_t ustorm_rx_prods_offset
bus_dmamap_t rx_sge_mbuf_spare_map
union eth_rx_cqe * rcq_chain
union bxe_host_hc_status_block status_block
struct bxe_dma rx_sge_dma
bus_dma_tag_t tx_mbuf_tag
struct bxe_eth_q_stats eth_q_stats
struct eth_rx_sge * rx_sge_chain
bus_dmamap_t rx_mbuf_spare_map
bus_dmamap_t rx_tpa_info_mbuf_spare_map
uint64_t sge_mask[RX_SGE_MASK_LEN]
union eth_tx_bd_types * tx_chain
uint16_t * sb_running_index
struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]
struct eth_rx_bd * rx_chain
struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]
bus_dma_tag_t rx_mbuf_tag
uint16_t * sb_index_values
struct timeout_task tx_timeout_task
struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]
uint64_t rx_tpa_queue_used
struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]
bus_dma_tag_t rx_sge_mbuf_tag
struct resource * resource
unsigned long link_report_flags
uint32_t mf_config[E1HVN_MAX]
uint8_t max_bw[MAX_VNIC_NUM]
uint32_t multi_vnics_mode
uint32_t mf_protos_supported
uint8_t min_bw[MAX_VNIC_NUM]
uint8_t niv_allowed_priorities
enum mf_cfg_afex_vlan_mode afex_vlan_mode
uint32_t advertising[ELINK_LINK_CONFIG_SIZE]
uint32_t supported[ELINK_LINK_CONFIG_SIZE]
uint32_t link_config[ELINK_LINK_CONFIG_SIZE]
unsigned long ramrod_flags
union drv_info_to_mcp drv_info_to_mcp
struct eth_spe * spq_last_bd
struct bxe_fw_stats_data * fw_stats_data
const struct iro * iro_array
union event_ring_elem * eq
struct bxe_bar bar[MAX_BARS]
struct bxe_fw_stats_req * fw_stats_req
uint16_t fw_drv_pulse_wr_seq
struct taskqueue * chip_tq
unsigned int trigger_grcdump
struct ecore_credit_pool_obj vlans_pool
struct bxe_dma def_sb_dma
unsigned int grcdump_started
struct eth_spe * spq_prod_bd
struct bxe_fastpath fp[MAX_RSS_CHAINS]
bus_dma_tag_t parent_dma_tag
uint8_t prio_to_cos[BXE_MAX_PRIORITY]
volatile unsigned long chip_tq_flags
struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]
struct ecore_credit_pool_obj macs_pool
struct elink_vars link_vars
int last_reported_link_state
struct hw_context context[ILT_MAX_L2_LINES]
struct ecore_rx_mode_obj rx_mode_obj
struct bxe_eth_stats eth_stats
struct elink_params link_params
volatile unsigned long cq_spq_left
struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]
bus_addr_t fw_stats_req_mapping
struct bxe_devinfo devinfo
struct ecore_func_sp_obj func_obj
struct ecore_mcast_obj mcast_obj
volatile unsigned long periodic_flags
struct bxe_link_report_data last_reported_link
struct timeout_task sp_err_timeout_task
struct callout periodic_callout
struct bxe_dma fw_stats_dma
unsigned int grcdump_done
struct ecore_rss_config_obj rss_conf_obj
bus_addr_t fw_stats_data_mapping
volatile unsigned long eq_spq_left
struct bxe_dma gz_buf_dma
struct bxe_intr intr[MAX_RSS_CHAINS+1]
struct host_sp_status_block * def_sb
struct ecore_queue_sp_obj q_obj
struct ecore_vlan_mac_obj mac_obj
struct cmng_struct_per_port port
struct rate_shaping_vars_per_vn vnic_max_rate[4]
struct fairness_vars_per_vn vnic_min_rate[4]
uint32_t conn_and_cmd_data
int(* init_hw_cmn_chip)(struct bxe_softc *sc)
int(* complete_cmd)(struct bxe_softc *sc, struct ecore_func_sp_obj *o, enum ecore_func_cmd cmd)
struct ecore_func_hw_init_params hw_init
unsigned long ramrod_flags
struct ecore_func_start_params start
union ecore_func_state_params::@45 params
struct ecore_func_sp_obj * f_obj
struct ilt_client_info clients[4]
bool(* check_pending)(struct ecore_mcast_obj *o)
unsigned long ramrod_flags
struct ecore_mcast_obj * mcast_obj
struct ecore_queue_init_params::@43 rx
struct eth_context * cxts[ECORE_MULTI_TX_COS]
struct ecore_queue_init_params::@42 tx
struct ecore_txq_setup_params txq_params
struct ecore_general_setup_params gen_params
struct rxq_pause_params pause_params
struct ecore_rxq_setup_params rxq_params
int(* complete_cmd)(struct bxe_softc *sc, struct ecore_queue_sp_obj *o, enum ecore_queue_cmd)
struct ecore_queue_cfc_del_params cfc_del
struct ecore_queue_terminate_params terminate
struct ecore_queue_sp_obj * q_obj
unsigned long ramrod_flags
struct ecore_queue_init_params init
struct ecore_queue_setup_params setup
union ecore_queue_state_params::@44 params
void(* clear_pending)(struct ecore_raw_obj *o)
unsigned long ramrod_flags
ecore_dma_addr_t rdata_mapping
struct ecore_rx_mode_obj * rx_mode_obj
unsigned long tx_accept_flags
unsigned long rx_mode_flags
unsigned long rx_accept_flags
uint16_t silent_removal_value
uint16_t silent_removal_mask
ecore_dma_addr_t dscr_map
ecore_dma_addr_t rcq_np_map
ecore_dma_addr_t dscr_map
uint8_t tss_leading_cl_id
union ecore_classification_ramrod_data u
unsigned long vlan_mac_flags
enum ecore_vlan_mac_cmd cmd
int(* complete)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, union event_ring_elem *cqe, unsigned long *ramrod_flags)
int(* get_n_elements)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, int n, uint8_t *base, uint8_t stride, uint8_t size)
int(* delete_all)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, unsigned long *vlan_mac_flags, unsigned long *ramrod_flags)
unsigned long ramrod_flags
struct ecore_vlan_mac_obj * vlan_mac_obj
struct ecore_vlan_mac_data user_req
uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]
uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]
uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE]
uint32_t multi_phy_config
uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE]
uint32_t feature_config_flags
struct elink_phy phy[ELINK_MAX_PHYS]
struct xstorm_eth_ag_context xstorm_ag_context
struct ustorm_eth_ag_context ustorm_ag_context
union eth_sgl_or_raw_data sgl_or_raw_data
uint16_t pkt_len_or_gro_seg_len
union eth_sgl_or_raw_data sgl_or_raw_data
struct parsing_flags pars_flags
union eth_specific_data data
uint8_t version[ETH_STAT_INFO_VERSION_LEN]
uint32_t promiscuous_mode
union eth_mac_addr_or_tunnel_data data
uint16_t vlan_or_ethertype
struct eth_tx_bd_flags bd_flags
struct regpair_native_t base_addr
struct regpair_native_t host_sb_addr
struct hc_status_block_sm state_machine[HC_SB_MAX_SM]
struct regpair_native_t host_sb_addr
uint16_t index_values[HC_SP_SB_MAX_INDICES]
struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]
struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]
uint16_t running_index[HC_SB_MAX_SM]
uint16_t index_values[HC_SB_MAX_INDICES_E1X]
uint16_t index_values[HC_SB_MAX_INDICES_E2]
uint16_t running_index[HC_SB_MAX_SM]
struct hc_status_block_e1x sb
struct hc_status_block_e2 sb
struct mac_stx mac_stx[MAC_STX_IDX_MAX]
struct hc_sp_status_block sp_sb
struct atten_sp_status_block atten_status_block
ecore_dma_addr_t page_mapping
uint32_t conn_and_cmd_data
const uint32_t * read_regs
struct doorbell_set_prod data
struct host_hc_status_block_e2 * e2_sb
struct host_hc_status_block_e1x * e1x_sb
struct eth_stats_info ether_stat
struct ecore_mac_ramrod_data mac
struct eth_mac_addresses mac_addr
struct eth_end_agg_rx_cqe end_agg_cqe
struct common_ramrod_eth_rx_cqe ramrod_cqe
struct eth_fast_path_rx_cqe fast_path_cqe
struct regpair_t update_data_addr
struct eth_tx_next_bd next_bd
struct eth_tx_start_bd start_bd
struct eth_tx_parse_bd_e1x parse_bd_e1x
struct eth_tx_parse_bd_e2 parse_bd_e2
struct function_update_event_data function_update_event
struct cfc_del_event_data cfc_del_event
struct eth_event_data eth_event
struct event_ring_msg message
struct event_ring_next next_page