35#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
41#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
42#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
43#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
44#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
49#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
50#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
51#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
52#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
63#define PIN_CFG_NA 0x00000000
64#define PIN_CFG_GPIO0_P0 0x00000001
65#define PIN_CFG_GPIO1_P0 0x00000002
66#define PIN_CFG_GPIO2_P0 0x00000003
67#define PIN_CFG_GPIO3_P0 0x00000004
68#define PIN_CFG_GPIO0_P1 0x00000005
69#define PIN_CFG_GPIO1_P1 0x00000006
70#define PIN_CFG_GPIO2_P1 0x00000007
71#define PIN_CFG_GPIO3_P1 0x00000008
72#define PIN_CFG_EPIO0 0x00000009
73#define PIN_CFG_EPIO1 0x0000000a
74#define PIN_CFG_EPIO2 0x0000000b
75#define PIN_CFG_EPIO3 0x0000000c
76#define PIN_CFG_EPIO4 0x0000000d
77#define PIN_CFG_EPIO5 0x0000000e
78#define PIN_CFG_EPIO6 0x0000000f
79#define PIN_CFG_EPIO7 0x00000010
80#define PIN_CFG_EPIO8 0x00000011
81#define PIN_CFG_EPIO9 0x00000012
82#define PIN_CFG_EPIO10 0x00000013
83#define PIN_CFG_EPIO11 0x00000014
84#define PIN_CFG_EPIO12 0x00000015
85#define PIN_CFG_EPIO13 0x00000016
86#define PIN_CFG_EPIO14 0x00000017
87#define PIN_CFG_EPIO15 0x00000018
88#define PIN_CFG_EPIO16 0x00000019
89#define PIN_CFG_EPIO17 0x0000001a
90#define PIN_CFG_EPIO18 0x0000001b
91#define PIN_CFG_EPIO19 0x0000001c
92#define PIN_CFG_EPIO20 0x0000001d
93#define PIN_CFG_EPIO21 0x0000001e
94#define PIN_CFG_EPIO22 0x0000001f
95#define PIN_CFG_EPIO23 0x00000020
96#define PIN_CFG_EPIO24 0x00000021
97#define PIN_CFG_EPIO25 0x00000022
98#define PIN_CFG_EPIO26 0x00000023
99#define PIN_CFG_EPIO27 0x00000024
100#define PIN_CFG_EPIO28 0x00000025
101#define PIN_CFG_EPIO29 0x00000026
102#define PIN_CFG_EPIO30 0x00000027
103#define PIN_CFG_EPIO31 0x00000028
106#define EPIO_CFG_NA 0x00000000
107#define EPIO_CFG_EPIO0 0x00000001
108#define EPIO_CFG_EPIO1 0x00000002
109#define EPIO_CFG_EPIO2 0x00000003
110#define EPIO_CFG_EPIO3 0x00000004
111#define EPIO_CFG_EPIO4 0x00000005
112#define EPIO_CFG_EPIO5 0x00000006
113#define EPIO_CFG_EPIO6 0x00000007
114#define EPIO_CFG_EPIO7 0x00000008
115#define EPIO_CFG_EPIO8 0x00000009
116#define EPIO_CFG_EPIO9 0x0000000a
117#define EPIO_CFG_EPIO10 0x0000000b
118#define EPIO_CFG_EPIO11 0x0000000c
119#define EPIO_CFG_EPIO12 0x0000000d
120#define EPIO_CFG_EPIO13 0x0000000e
121#define EPIO_CFG_EPIO14 0x0000000f
122#define EPIO_CFG_EPIO15 0x00000010
123#define EPIO_CFG_EPIO16 0x00000011
124#define EPIO_CFG_EPIO17 0x00000012
125#define EPIO_CFG_EPIO18 0x00000013
126#define EPIO_CFG_EPIO19 0x00000014
127#define EPIO_CFG_EPIO20 0x00000015
128#define EPIO_CFG_EPIO21 0x00000016
129#define EPIO_CFG_EPIO22 0x00000017
130#define EPIO_CFG_EPIO23 0x00000018
131#define EPIO_CFG_EPIO24 0x00000019
132#define EPIO_CFG_EPIO25 0x0000001a
133#define EPIO_CFG_EPIO26 0x0000001b
134#define EPIO_CFG_EPIO27 0x0000001c
135#define EPIO_CFG_EPIO28 0x0000001d
136#define EPIO_CFG_EPIO29 0x0000001e
137#define EPIO_CFG_EPIO30 0x0000001f
138#define EPIO_CFG_EPIO31 0x00000020
151 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
152 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
153 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
154 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
156 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
158 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
160 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
161 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
163 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
164 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
167 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
168 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
169 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
170 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
173 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
176 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
179 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
185 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000
186 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12
188 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000
189 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
190 #define SHARED_HW_CFG_LED_MAC1 0x00000000
191 #define SHARED_HW_CFG_LED_PHY1 0x00010000
192 #define SHARED_HW_CFG_LED_PHY2 0x00020000
193 #define SHARED_HW_CFG_LED_PHY3 0x00030000
194 #define SHARED_HW_CFG_LED_MAC2 0x00040000
195 #define SHARED_HW_CFG_LED_PHY4 0x00050000
196 #define SHARED_HW_CFG_LED_PHY5 0x00060000
197 #define SHARED_HW_CFG_LED_PHY6 0x00070000
198 #define SHARED_HW_CFG_LED_MAC3 0x00080000
199 #define SHARED_HW_CFG_LED_PHY7 0x00090000
200 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
201 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
202 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
203 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
204 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
205 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
207 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
208 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
209 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
211 #define SHARED_HW_CFG_ATC_MASK 0x80000000
212 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
213 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
217 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100
218 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8
219 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
220 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
222 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
223 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
224 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
226 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
230 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
231 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
232 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
234 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
235 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
236 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
237 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
238 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
239 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
248 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
249 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
250 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
251 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
252 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
255 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
256 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
257 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
258 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
259 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
260 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
264 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
265 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
266 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
284 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
285 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
289 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
290 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
294 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
295 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
296 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
297 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
302 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
303 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
304 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
305 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
315 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
316 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
318 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
319 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
322 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
324 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
325 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
336 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
337 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
338 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
339 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
342 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
343 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
344 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
345 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
347 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
348 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
349 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
350 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
358 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
359 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
360 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
361 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
371 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF
372 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0
374 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000
375 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16
378 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF
379 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0
381 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000
382 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16
385 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF
386 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
387 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00
388 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
389 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000
390 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
391 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000
392 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
395 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF
396 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
397 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00
398 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
399 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000
400 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
401 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000
402 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
406 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF
407 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
417 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
418 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
420 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
421 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
438 #define PORT_HW_CFG_TX_LASER_SHIFT 0
439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
512 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
513 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
520 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
521 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
527 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
528 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
530 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
531 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
534 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
535 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
538 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
539 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
546 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
547 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
549 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
550 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
552 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
553 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
566 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
567 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
578 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001
579 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0
580 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000
581 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001
585 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF
586 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0
595 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF
596 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0
601 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
602 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
605 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
606 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
607 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
608 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
609 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
610 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
612 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
613 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
614 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
615 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
616 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
617 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
619 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
620 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
621 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
622 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
623 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
624 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
626 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
627 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
628 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
629 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
630 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
631 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
639 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
640 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
641 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
642 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
643 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
644 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
645 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
646 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
647 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
648 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
649 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
650 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
652 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
653 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
654 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
655 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
656 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
657 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
658 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
659 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
660 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
661 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
662 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
665 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
666 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
667 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
668 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
671 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
672 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
673 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
674 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
677 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
678 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
679 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
680 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
681 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
682 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
683 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
684 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
687 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000
688 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28
689 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000
690 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000
691 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000
692 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000
693 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000
694 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000
697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
703 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
704 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
705 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
706 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
708 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
709 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
710 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
711 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000
712 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000
713 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
714 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
715 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000
716 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
717 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
725 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
726 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
727 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
728 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
729 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
730 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
731 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
735 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
736 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
737 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
738 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
743 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
744 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
755 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
756 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
757 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
758 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
759 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
760 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
761 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
762 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
763 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
764 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
765 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
766 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
767 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
768 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
769 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
778 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
779 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
781 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
783 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
785 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
787 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
788 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
789 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
790 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
791 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
792 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000
793 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
796 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
797 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
798 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
802 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF
803 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00
806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
813 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
814 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
815 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
816 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
817 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
818 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
819 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
820 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
821 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
822 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
823 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
824 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
825 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
826 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
827 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
828 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
830 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000
831 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
833 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000
834 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
835 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
836 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
837 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
838 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
841 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF
842 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
843 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
844 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
845 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
846 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
847 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
848 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
849 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
850 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
851 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
853 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000
854 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
855 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
856 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
857 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
858 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
859 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
860 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
861 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
862 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
863 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
878 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
881 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
883 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
885 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
888 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
889 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
890 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
892 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
893 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
897 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
898 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
899 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
900 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
901 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
902 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
903 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
904 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
905 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
906 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
909 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
912 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000
915 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000
916 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14
917 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000
918 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000
922 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000
923 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
926 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000
927 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
938 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F
939 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0
940 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000
941 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001
942 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002
943 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003
944 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004
945 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005
946 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006
947 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007
948 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008
949 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009
950 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a
951 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b
952 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c
953 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d
954 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e
955 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f
956 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0
957 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4
958 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000
959 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010
960 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020
961 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030
962 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040
963 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050
964 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060
965 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070
966 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080
967 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090
968 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0
969 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0
970 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0
971 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0
972 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0
973 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0
975 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
976 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
977 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
979 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200
980 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9
981 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000
982 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200
984 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
985 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10
986 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000
987 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
988 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
989 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
991 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
992 #define PORT_FEATURE_EN_SIZE_SHIFT 24
993 #define PORT_FEATURE_WOL_ENABLED 0x01000000
994 #define PORT_FEATURE_MBA_ENABLED 0x02000000
995 #define PORT_FEATURE_MFW_ENABLED 0x04000000
998 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
999 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
1000 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
1004 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
1005 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
1006 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
1008 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
1010 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
1011 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
1015 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
1018 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
1019 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
1020 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
1021 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
1022 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
1023 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
1024 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
1025 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
1027 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
1028 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
1030 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
1031 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
1032 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
1033 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
1035 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000
1036 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
1037 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
1038 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
1039 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
1040 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
1041 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
1042 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
1043 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
1044 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
1045 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
1046 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1047 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1048 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1049 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1050 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1051 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1052 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1053 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000
1054 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
1055 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1056 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
1057 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1058 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1059 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1060 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1061 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000
1062 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
1063 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1064 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000
1065 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000
1066 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000
1067 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000
1068 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000
1069 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000
1070 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
1071 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
1076 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
1077 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1078 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1079 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
1080 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
1081 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
1085 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1086 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1089 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F
1090 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1091 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1092 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1093 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1094 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1095 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1096 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1097 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1098 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1099 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1100 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1101 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1102 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1103 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1104 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1105 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1106 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1110 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1111 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1112 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1113 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1114 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1115 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1116 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1117 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500
1118 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600
1119 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700
1121 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
1122 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1123 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1124 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
1125 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
1126 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1127 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1128 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1129 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1130 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1131 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1133 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1134 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1136 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1138 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1139 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1140 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1158 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1159 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1160 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1161 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1162 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1163 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F
1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0
1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00
1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8
1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000
1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16
1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000
1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000
1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000
1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000
1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000
1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000
1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000
1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000
1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000
1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000
1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000
1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000
1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000
1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000
1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000
1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000
1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000
1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000
1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000
1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000
1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000
1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000
1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000
1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000
1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000
1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000
1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000
1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000
1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000
1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000
1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000
1231 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000
1232 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000
1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000
1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24
1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000
1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000
1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000
1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000
1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000
1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000
1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000
1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000
1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000
1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000
1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000
1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000
1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000
1250 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000
1251 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000
1252 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000
1253 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000
1254 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000
1255 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000
1256 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000
1257 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000
1258 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000
1259 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000
1260 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000
1261 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000
1262 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000
1263 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000
1264 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000
1265 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000
1266 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000
1267 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000
1268 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000
1269 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000
1274 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
1275 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
1278 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
1279 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16
1280 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000
1281 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
1284 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
1285 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18
1289 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF
1290 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0
1291 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000
1292 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001
1295 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100
1296 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8
1297 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
1298 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
1301 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
1302 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9
1303 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
1304 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
1307 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
1308 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10
1309 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
1310 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
1315 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
1316 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
1317 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000
1318 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000
1321 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF
1322 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0
1326 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F
1327 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0
1328 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000
1329 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008
1330 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009
1331 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a
1332 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b
1333 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c
1334 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d
1335 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e
1336 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f
1339 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100
1340 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8
1341 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000
1342 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100
1345 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200
1346 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9
1347 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
1348 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
1352 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
1353 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10
1354 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
1355 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
1358 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
1359 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11
1360 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
1361 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
1363 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
1364 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12
1365 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
1366 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
1367 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
1368 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
1371 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
1372 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0
1375 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00
1376 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8
1380 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF
1381 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0
1383 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00
1384 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8
1387 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000
1388 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16
1391 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000
1392 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24
1396 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF
1397 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0
1398 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001
1399 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002
1400 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004
1401 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008
1402 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010
1403 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020
1404 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040
1405 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080
1406 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100
1407 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200
1408 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400
1409 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800
1410 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000
1411 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000
1412 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000
1413 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000
1414 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000
1415 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000
1416 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
1417 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
1422 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
1423 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20
1424 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
1425 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
1429 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
1430 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0
1434 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001
1435 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0
1436 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000
1437 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001
1440 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E
1441 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1
1444 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010
1445 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4
1446 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000
1447 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010
1450 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020
1451 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5
1452 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000
1453 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020
1456 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000
1457 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15
1458 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000
1459 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000
1463 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E
1464 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1
1467 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010
1468 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4
1469 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000
1470 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010
1473 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020
1474 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5
1475 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000
1476 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020
1483 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF
1484 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0
1485 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00
1486 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8
1487 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000
1488 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16
1492 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF
1493 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
1494 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00
1495 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8
1496 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
1497 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16
1501 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF
1502 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
1503 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00
1504 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8
1505 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
1506 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16
1512 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF
1513 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0
1514 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00
1515 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8
1516 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000
1517 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
1518 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
1519 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
1528 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
1529 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18
1530 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
1531 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
1535 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
1536 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
1537 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
1538 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
1548#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1549 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1560#define E1_FUNC_MAX 2
1561#define E1H_FUNC_MAX 8
1562#define E2_FUNC_MAX 4
1575#define DRV_PULSE_PERIOD_MS 250
1582#define FW_ACK_TIME_OUT_MS 5000
1584#define FW_ACK_POLL_TIME_MS 1
1586#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1588#define MFW_TRACE_SIGNATURE 0x54524342
1598 #define LINK_STATUS_NONE (0<<0)
1599 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1600 #define LINK_STATUS_LINK_UP 0x00000001
1601 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1602 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1603 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1604 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1605 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1606 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1607 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1608 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1609 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1610 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1611 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1612 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1613 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1614 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1615 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1616 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1617 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1619 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1620 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1622 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1623 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1624 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1626 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1627 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1628 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1629 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1630 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1631 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1632 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1634 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1635 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1637 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1638 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1640 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1641 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1642 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1643 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1644 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1646 #define LINK_STATUS_SERDES_LINK 0x00100000
1648 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1649 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1650 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1651 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1653 #define LINK_STATUS_PFC_ENABLED 0x20000000
1655 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1656 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1671 #define DRV_MSG_CODE_MASK 0xffff0000
1672 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1673 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1674 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1675 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1676 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1677 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1678 #define DRV_MSG_CODE_DCC_OK 0x30000000
1679 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1680 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1681 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1682 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1683 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1684 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1685 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1686 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1687 #define DRV_MSG_CODE_OEM_OK 0x00010000
1688 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
1689 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
1690 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
1697 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1698 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1699 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1700 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1701 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1702 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1703 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1704 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1705 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1706 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1708 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1709 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1710 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1712 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1714 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1715 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1716 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1717 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1718 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1720 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1721 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1723 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1725 #define DRV_MSG_CODE_RMMOD 0xdb000000
1726 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1728 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1729 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1730 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1732 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1734 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1735 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1737 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1738 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1739 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1740 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1742 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
1743 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
1745 #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
1747 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1749 #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
1752 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1753 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1755 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001
1756 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1758 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1759 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1761 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
1762 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
1763 #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
1765 #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
1766 #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
1767 #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
1768 #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
1769 #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
1772 #define FW_MSG_CODE_MASK 0xffff0000
1773 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1774 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1775 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1777 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1778 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1780 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1781 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1782 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1783 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1784 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1785 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1786 #define FW_MSG_CODE_DCC_DONE 0x30100000
1787 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1788 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1789 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1790 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1791 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1792 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1793 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1794 #define FW_MSG_CODE_NO_KEY 0x80f00000
1795 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1796 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1797 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1798 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1799 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1800 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1801 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1802 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1803 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1804 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1805 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1807 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1808 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1809 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1810 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1811 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1813 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1814 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1816 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1818 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1820 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1821 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1823 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1825 #define FW_MSG_CODE_FLR_ACK 0x02000000
1826 #define FW_MSG_CODE_FLR_NACK 0x02100000
1828 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1829 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1830 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1831 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1833 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
1834 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
1836 #define FW_MSG_CODE_OEM_ACK 0x00010000
1837 #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
1839 #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
1841 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1845 #define FW_PARAM_INVALID_IMG 0xffffffff
1848 #define DRV_PULSE_SEQ_MASK 0x00007fff
1849 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1854 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1862 #define MCP_PULSE_SEQ_MASK 0x00007fff
1863 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1866 #define MCP_EVENT_MASK 0xffff0000
1867 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1873 #define DRV_STATUS_PMF 0x00000001
1874 #define DRV_STATUS_VF_DISABLED 0x00000002
1875 #define DRV_STATUS_SET_MF_BW 0x00000004
1876 #define DRV_STATUS_LINK_EVENT 0x00000008
1878 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
1879 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
1880 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
1881 #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
1883 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
1885 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1886 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1887 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1888 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1889 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1890 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1891 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1893 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1894 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1895 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1896 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1897 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1898 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1899 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1901 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1903 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1906 #define VIRT_MAC_SIGN_MASK 0xffff0000
1907 #define VIRT_MAC_SIGNATURE 0x564d0000
1917#define MGMTFW_STATE_WORD_SIZE 110
1930 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1932 #define SHARED_MF_CLP_EXIT 0x00000001
1934 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1941 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1942 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1943 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1954 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1956 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1957 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1958 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1959 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1960 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1961 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1962 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1964 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1965 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1967 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060
1968 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000
1969 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020
1970 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040
1974 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1975 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1976 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1980 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1981 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1982 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1983 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1984 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1985 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1988 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1989 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1990 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1992 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1995 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1996 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1997 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
2000 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
2001 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
2004 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
2005 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
2006 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
2007 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
2008 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
2009 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
2010 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
2014 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF
2015 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0
2027 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
2028 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
2029 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
2030 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
2031 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
2032 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
2033 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
2048 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
2049 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
2050 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
2051 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
2052 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
2053 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
2076 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
2077 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
2079 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
2080 #define SHR_MEM_VALIDITY_MB 0x00200000
2081 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
2082 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
2084 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
2085 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
2086 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
2087 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
2089 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
2090 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
2091 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
2092 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
2093 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
2094 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
2160#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
2161#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
2187#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
2188 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
2189 (((i)%((fb)/(eb))) * (eb)))
2191#define SHMEM_ARRAY_GET(a, i, eb, fb) \
2192 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
2193 SHMEM_ARRAY_MASK(eb))
2195#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
2197 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
2198 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
2199 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
2200 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
2205#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
2206#define DCBX_PRI_PG_BITWIDTH 4
2207#define DCBX_PRI_PG_FBITS 8
2208#define DCBX_PRI_PG_GET(a, i) \
2209 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
2210#define DCBX_PRI_PG_SET(a, i, val) \
2211 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
2212#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
2213#define DCBX_BW_PG_BITWIDTH 8
2214#define DCBX_PG_BW_GET(a, i) \
2215 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
2216#define DCBX_PG_BW_SET(a, i, val) \
2217 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
2218#define DCBX_STRICT_PRI_PG 15
2219#define DCBX_MAX_APP_PROTOCOL 16
2220#define DCBX_MAX_APP_LOCAL 32
2221#define FCOE_APP_IDX 0
2222#define ISCSI_APP_IDX 1
2223#define PREDEFINED_APP_IDX_MAX 2
2240 uint8_t pri_en_bitmap;
2241 #define DCBX_PFC_PRI_0 0x01
2242 #define DCBX_PFC_PRI_1 0x02
2243 #define DCBX_PFC_PRI_2 0x04
2244 #define DCBX_PFC_PRI_3 0x08
2245 #define DCBX_PFC_PRI_4 0x10
2246 #define DCBX_PFC_PRI_5 0x20
2247 #define DCBX_PFC_PRI_6 0x40
2248 #define DCBX_PFC_PRI_7 0x80
2252#elif defined(__LITTLE_ENDIAN)
2256 uint8_t pri_en_bitmap;
2257 #define DCBX_PFC_PRI_0 0x01
2258 #define DCBX_PFC_PRI_1 0x02
2259 #define DCBX_PFC_PRI_2 0x04
2260 #define DCBX_PFC_PRI_3 0x08
2261 #define DCBX_PFC_PRI_4 0x10
2262 #define DCBX_PFC_PRI_5 0x20
2263 #define DCBX_PFC_PRI_6 0x40
2264 #define DCBX_PFC_PRI_7 0x80
2272 uint8_t appBitfield;
2273 #define DCBX_APP_ENTRY_VALID 0x01
2274 #define DCBX_APP_ENTRY_SF_MASK 0x30
2275 #define DCBX_APP_ENTRY_SF_SHIFT 4
2276 #define DCBX_APP_SF_ETH_TYPE 0x10
2277 #define DCBX_APP_SF_PORT 0x20
2278 #define DCBX_APP_PRI_0 0x01
2279 #define DCBX_APP_PRI_1 0x02
2280 #define DCBX_APP_PRI_2 0x04
2281 #define DCBX_APP_PRI_3 0x08
2282 #define DCBX_APP_PRI_4 0x10
2283 #define DCBX_APP_PRI_5 0x20
2284 #define DCBX_APP_PRI_6 0x40
2285 #define DCBX_APP_PRI_7 0x80
2286#elif defined(__LITTLE_ENDIAN)
2287 uint8_t appBitfield;
2288 #define DCBX_APP_ENTRY_VALID 0x01
2289 #define DCBX_APP_ENTRY_SF_MASK 0x30
2290 #define DCBX_APP_ENTRY_SF_SHIFT 4
2291 #define DCBX_APP_SF_ETH_TYPE 0x10
2292 #define DCBX_APP_SF_PORT 0x20
2303 uint8_t default_pri;
2304 uint8_t tc_supported;
2306#elif defined(__LITTLE_ENDIAN)
2308 uint8_t tc_supported;
2309 uint8_t default_pri;
2329 uint8_t msg_fast_tx_interval;
2330 uint8_t msg_tx_hold;
2331 uint8_t msg_tx_interval;
2332 uint8_t admin_status;
2333 #define LLDP_TX_ONLY 0x01
2334 #define LLDP_RX_ONLY 0x02
2335 #define LLDP_TX_RX 0x03
2336 #define LLDP_DISABLED 0x04
2341#elif defined(__LITTLE_ENDIAN)
2342 uint8_t admin_status;
2343 #define LLDP_TX_ONLY 0x01
2344 #define LLDP_RX_ONLY 0x02
2345 #define LLDP_TX_RX 0x03
2346 #define LLDP_DISABLED 0x04
2347 uint8_t msg_tx_interval;
2348 uint8_t msg_tx_hold;
2349 uint8_t msg_fast_tx_interval;
2355 #define REM_CHASSIS_ID_STAT_LEN 4
2356 #define REM_PORT_ID_STAT_LEN 4
2364 #define LOCAL_CHASSIS_ID_STAT_LEN 2
2365 #define LOCAL_PORT_ID_STAT_LEN 2
2379 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
2380 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
2381 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
2382 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
2383 #define DCBX_ETS_RECO_VALID 0x00000010
2384 #define DCBX_ETS_WILLING 0x00000020
2385 #define DCBX_PFC_WILLING 0x00000040
2386 #define DCBX_APP_WILLING 0x00000080
2387 #define DCBX_VERSION_CEE 0x00000100
2388 #define DCBX_VERSION_IEEE 0x00000200
2389 #define DCBX_DCBX_ENABLED 0x00000400
2390 #define DCBX_CEE_VERSION_MASK 0x0000f000
2391 #define DCBX_CEE_VERSION_SHIFT 12
2392 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
2393 #define DCBX_CEE_MAX_VERSION_SHIFT 16
2401 #define DCBX_ETS_TLV_RX 0x00000001
2402 #define DCBX_PFC_TLV_RX 0x00000002
2403 #define DCBX_APP_TLV_RX 0x00000004
2404 #define DCBX_ETS_RX_ERROR 0x00000010
2405 #define DCBX_PFC_RX_ERROR 0x00000020
2406 #define DCBX_APP_RX_ERROR 0x00000040
2407 #define DCBX_ETS_REM_WILLING 0x00000100
2408 #define DCBX_PFC_REM_WILLING 0x00000200
2409 #define DCBX_APP_REM_WILLING 0x00000400
2410 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
2411 #define DCBX_REMOTE_MIB_VALID 0x00002000
2421 #define DCBX_LOCAL_ETS_ERROR 0x00000001
2422 #define DCBX_LOCAL_PFC_ERROR 0x00000002
2423 #define DCBX_LOCAL_APP_ERROR 0x00000004
2424 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
2425 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
2426 #define DCBX_REMOTE_MIB_ERROR 0x00000040
2427 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
2428 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
2429 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
2445#define SHMEM_LINK_CONFIG_SIZE 2
2448 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
2449 #define REQ_DUPLEX_PHY0_SHIFT 0
2450 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
2451 #define REQ_DUPLEX_PHY1_SHIFT 16
2453 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
2454 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
2455 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
2456 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
2458 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
2459 #define REQ_LINE_SPD_PHY0_SHIFT 0
2460 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
2461 #define REQ_LINE_SPD_PHY1_SHIFT 16
2464 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2465 #define REQ_FC_AUTO_ADV0_SHIFT 0
2466 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2468 #define LFA_LINK_FLAP_REASON_OFFSET 0
2469 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2470 #define LFA_LINK_DOWN 0x1
2471 #define LFA_LOOPBACK_ENABLED 0x2
2472 #define LFA_DUPLEX_MISMATCH 0x3
2473 #define LFA_MFW_IS_TOO_OLD 0x4
2474 #define LFA_LINK_SPEED_MISMATCH 0x5
2475 #define LFA_FLOW_CTRL_MISMATCH 0x6
2476 #define LFA_SPEED_CAP_MISMATCH 0x7
2477 #define LFA_DCC_LFA_DISABLED 0x8
2478 #define LFA_EEE_MISMATCH 0x9
2480 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
2481 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2483 #define LINK_FLAP_COUNT_OFFSET 16
2484 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2486 #define LFA_FLAGS_MASK 0xff000000
2487 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
2497 #define DRV_VER_NOT_LOADED 0
2499 #define DRV_PERS_ETHERNET 0
2500 #define DRV_PERS_ISCSI 1
2501 #define DRV_PERS_FCOE 2
2503 #define MAX_DRV_PERS 3
2507#define OEM_I2C_UUID_STR_ADDR 0x9f
2508#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
2509#define OEM_I2C_CARD_FN_STR_ADDR 0x48
2510#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
2512#define OEM_I2C_UUID_STR_LEN 16
2513#define OEM_I2C_CARD_SKU_STR_LEN 12
2514#define OEM_I2C_CARD_FN_STR_LEN 12
2515#define OEM_I2C_CARD_NAME_STR_LEN 128
2516#define OEM_I2C_CARD_VERSION_STR_LEN 36
2537#define FC_NPIV_WWPN_SIZE 8
2538#define FC_NPIV_WWNN_SIZE 8
2550#define MAX_NUMBER_NPIV 64
2562 #define FIRST_DUMP_VALID (1 << 0)
2563 #define SECOND_DUMP_VALID (1 << 1)
2566 #define ENABLE_ALL_TRIGGERS (0x7fffffff)
2567 #define TRIGGER_MDUMP_ONCE (1 << 31)
2575 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2576 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2577 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2578 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2579 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2580 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2589 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2593 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2595 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2597 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2619 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2631 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2632 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2633 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2639 #define SHMEM_AFEX_VERSION_MASK 0x100f
2640 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2641 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2665 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2666 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2667 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2669 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2670 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2671 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2673 #define DRV_FLAGS_P0_OFFSET 0
2674 #define DRV_FLAGS_P1_OFFSET 16
2675 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \
2676 DRV_FLAGS_P0_OFFSET : \
2677 DRV_FLAGS_P1_OFFSET)
2679 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \
2680 DRV_FLAGS_GET_PORT_OFFSET(_port))
2682 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \
2683 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
2696 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2699 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2700 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2701 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2702 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2703 #define DRV_FLAGS_MTU_MASK 0xffff0000
2704 #define DRV_FLAGS_MTU_SHIFT 16
2719 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2720 #define DRV_INFO_CONTROL_VER_SHIFT 0
2721 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2722 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2727 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff
2728 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
2745 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2746 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2747 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2748 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2749 #define SHMEM_EEE_100M_ADV (1<<0)
2750 #define SHMEM_EEE_1G_ADV (1<<1)
2751 #define SHMEM_EEE_10G_ADV (1<<2)
2752 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2753 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2754 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2755 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2756 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2757 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2758 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2767 #define EXTPHY1_TEMP_MASK 0x0000ffff
2768 #define EXTPHY1_TEMP_SHIFT 0
2769 #define ON_BOARD_TEMP_MASK 0xffff0000
2770 #define ON_BOARD_TEMP_SHIFT 16
2776 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2777 #define LINK_ATTR_84858 0x00000002
2778 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2779 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
2780 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
2781 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
2782 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
2787 #define LINK_CHANGE_COUNT_MASK 0xff
2795 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_)
2799 #define STORAGE_BOOT_PROG_MASK 0x000000FF
2800 #define STORAGE_BOOT_PROG_NONE 0x00000000
2801 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
2802 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
2803 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
2804 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
2805 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
2806 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
2807 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
2808 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
2809 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
2847 #define SRIOV_SWITCH_MODE_NONE 0x0
2848 #define SRIOV_SWITCH_MODE_VEB 0x1
2849 #define SRIOV_SWITCH_MODE_VEPA 0x2
2858 #define OS_DRIVER_STATE_NOT_LOADED 0
2859 #define OS_DRIVER_STATE_LOADING 1
2860 #define OS_DRIVER_STATE_DISABLED 2
2861 #define OS_DRIVER_STATE_ACTIVE 3
3398#define MAC_STX_IDX_MAX 2
3454#define VICSTATST_UIF_INDEX 2
3543#define BCM_5710_FW_MAJOR_VERSION 7
3544#define BCM_5710_FW_MINOR_VERSION 13
3545#define BCM_5710_FW_REVISION_VERSION 1
3546#define BCM_5710_FW_ENGINEERING_VERSION 0
3547#define BCM_5710_FW_COMPILE_FLAGS 1
3579 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0)
3580 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
3581 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8)
3582 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8
3583 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9)
3584 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9
3585 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10)
3586 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10
3587 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11)
3588 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11
3589 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12)
3590 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12
3591 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13)
3592 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13
3593 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14)
3594 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14
3595 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16)
3596 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16
3597 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18)
3598 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18
3599 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19)
3600 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19
3601 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20)
3602 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20
3603 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21)
3604 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21
3605 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22)
3606 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22
3607 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23)
3608 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23
3609 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26)
3610 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26
3611 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28)
3612 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28
3613 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30)
3614 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30
3615#if defined(__BIG_ENDIAN)
3617 uint8_t __aux1_val ;
3618 uint16_t __agg_vars2 ;
3619#elif defined(__LITTLE_ENDIAN)
3620 uint16_t __agg_vars2 ;
3621 uint8_t __aux1_val ;
3626#if defined(__BIG_ENDIAN)
3629#elif defined(__LITTLE_ENDIAN)
3633#if defined(__BIG_ENDIAN)
3634 uint8_t __reserved62 ;
3635 uint8_t __reserved61 ;
3636 uint8_t __reserved60 ;
3637 uint8_t __reserved59 ;
3638#elif defined(__LITTLE_ENDIAN)
3639 uint8_t __reserved59 ;
3640 uint8_t __reserved60 ;
3641 uint8_t __reserved61 ;
3642 uint8_t __reserved62 ;
3644#if defined(__BIG_ENDIAN)
3645 uint16_t __reserved64 ;
3646 uint16_t cq_u_prod ;
3647#elif defined(__LITTLE_ENDIAN)
3648 uint16_t cq_u_prod ;
3649 uint16_t __reserved64 ;
3652#if defined(__BIG_ENDIAN)
3653 uint16_t __agg_vars3 ;
3654 uint16_t cq_u_pend ;
3655#elif defined(__LITTLE_ENDIAN)
3656 uint16_t cq_u_pend ;
3657 uint16_t __agg_vars3 ;
3659#if defined(__BIG_ENDIAN)
3660 uint16_t __aux2_th ;
3662#elif defined(__LITTLE_ENDIAN)
3664 uint16_t __aux2_th ;
3675#if defined(__BIG_ENDIAN)
3677 uint8_t __aux1_val ;
3678 uint16_t __agg_vars2 ;
3679#elif defined(__LITTLE_ENDIAN)
3680 uint16_t __agg_vars2 ;
3681 uint8_t __aux1_val ;
3686#if defined(__BIG_ENDIAN)
3687 uint16_t __reserved58 ;
3689#elif defined(__LITTLE_ENDIAN)
3691 uint16_t __reserved58 ;
3693#if defined(__BIG_ENDIAN)
3694 uint8_t __reserved62 ;
3695 uint8_t __reserved61 ;
3696 uint8_t __reserved60 ;
3697 uint8_t __completion_opcode ;
3698#elif defined(__LITTLE_ENDIAN)
3699 uint8_t __completion_opcode ;
3700 uint8_t __reserved60 ;
3701 uint8_t __reserved61 ;
3702 uint8_t __reserved62 ;
3704#if defined(__BIG_ENDIAN)
3705 uint16_t __reserved64 ;
3706 uint16_t __reserved63 ;
3707#elif defined(__LITTLE_ENDIAN)
3708 uint16_t __reserved63 ;
3709 uint16_t __reserved64 ;
3712#if defined(__BIG_ENDIAN)
3713 uint16_t __agg_vars3 ;
3714 uint16_t __reserved67 ;
3715#elif defined(__LITTLE_ENDIAN)
3716 uint16_t __reserved67 ;
3717 uint16_t __agg_vars3 ;
3719#if defined(__BIG_ENDIAN)
3720 uint16_t __aux2_th ;
3721 uint16_t __aux2_val ;
3722#elif defined(__LITTLE_ENDIAN)
3723 uint16_t __aux2_val ;
3724 uint16_t __aux2_th ;
3735 #define DMAE_CMD_SRC (0x1<<0)
3736 #define DMAE_CMD_SRC_SHIFT 0
3737 #define DMAE_CMD_DST (0x3<<1)
3738 #define DMAE_CMD_DST_SHIFT 1
3739 #define DMAE_CMD_C_DST (0x1<<3)
3740 #define DMAE_CMD_C_DST_SHIFT 3
3741 #define DMAE_CMD_C_TYPE_ENABLE (0x1<<4)
3742 #define DMAE_CMD_C_TYPE_ENABLE_SHIFT 4
3743 #define DMAE_CMD_C_TYPE_CRC_ENABLE (0x1<<5)
3744 #define DMAE_CMD_C_TYPE_CRC_ENABLE_SHIFT 5
3745 #define DMAE_CMD_C_TYPE_CRC_OFFSET (0x7<<6)
3746 #define DMAE_CMD_C_TYPE_CRC_OFFSET_SHIFT 6
3747 #define DMAE_CMD_ENDIANITY (0x3<<9)
3748 #define DMAE_CMD_ENDIANITY_SHIFT 9
3749 #define DMAE_CMD_PORT (0x1<<11)
3750 #define DMAE_CMD_PORT_SHIFT 11
3751 #define DMAE_CMD_CRC_RESET (0x1<<12)
3752 #define DMAE_CMD_CRC_RESET_SHIFT 12
3753 #define DMAE_CMD_SRC_RESET (0x1<<13)
3754 #define DMAE_CMD_SRC_RESET_SHIFT 13
3755 #define DMAE_CMD_DST_RESET (0x1<<14)
3756 #define DMAE_CMD_DST_RESET_SHIFT 14
3757 #define DMAE_CMD_E1HVN (0x3<<15)
3758 #define DMAE_CMD_E1HVN_SHIFT 15
3759 #define DMAE_CMD_DST_VN (0x3<<17)
3760 #define DMAE_CMD_DST_VN_SHIFT 17
3761 #define DMAE_CMD_C_FUNC (0x1<<19)
3762 #define DMAE_CMD_C_FUNC_SHIFT 19
3763 #define DMAE_CMD_ERR_POLICY (0x3<<20)
3764 #define DMAE_CMD_ERR_POLICY_SHIFT 20
3765 #define DMAE_CMD_RESERVED0 (0x3FF<<22)
3766 #define DMAE_CMD_RESERVED0_SHIFT 22
3771#if defined(__BIG_ENDIAN)
3772 uint16_t opcode_iov;
3773 #define DMAE_CMD_SRC_VFID (0x3F<<0)
3774 #define DMAE_CMD_SRC_VFID_SHIFT 0
3775 #define DMAE_CMD_SRC_VFPF (0x1<<6)
3776 #define DMAE_CMD_SRC_VFPF_SHIFT 6
3777 #define DMAE_CMD_RESERVED1 (0x1<<7)
3778 #define DMAE_CMD_RESERVED1_SHIFT 7
3779 #define DMAE_CMD_DST_VFID (0x3F<<8)
3780 #define DMAE_CMD_DST_VFID_SHIFT 8
3781 #define DMAE_CMD_DST_VFPF (0x1<<14)
3782 #define DMAE_CMD_DST_VFPF_SHIFT 14
3783 #define DMAE_CMD_RESERVED2 (0x1<<15)
3784 #define DMAE_CMD_RESERVED2_SHIFT 15
3786#elif defined(__LITTLE_ENDIAN)
3788 uint16_t opcode_iov;
3789 #define DMAE_CMD_SRC_VFID (0x3F<<0)
3790 #define DMAE_CMD_SRC_VFID_SHIFT 0
3791 #define DMAE_CMD_SRC_VFPF (0x1<<6)
3792 #define DMAE_CMD_SRC_VFPF_SHIFT 6
3793 #define DMAE_CMD_RESERVED1 (0x1<<7)
3794 #define DMAE_CMD_RESERVED1_SHIFT 7
3795 #define DMAE_CMD_DST_VFID (0x3F<<8)
3796 #define DMAE_CMD_DST_VFID_SHIFT 8
3797 #define DMAE_CMD_DST_VFPF (0x1<<14)
3798 #define DMAE_CMD_DST_VFPF_SHIFT 14
3799 #define DMAE_CMD_RESERVED2 (0x1<<15)
3800 #define DMAE_CMD_RESERVED2_SHIFT 15
3807#if defined(__BIG_ENDIAN)
3810#elif defined(__LITTLE_ENDIAN)
3814#if defined(__BIG_ENDIAN)
3817#elif defined(__LITTLE_ENDIAN)
3821#if defined(__BIG_ENDIAN)
3824#elif defined(__LITTLE_ENDIAN)
3837 #define DOORBELL_HDR_T_RX (0x1<<0)
3838 #define DOORBELL_HDR_T_RX_SHIFT 0
3839 #define DOORBELL_HDR_T_DB_TYPE (0x1<<1)
3840 #define DOORBELL_HDR_T_DB_TYPE_SHIFT 1
3841 #define DOORBELL_HDR_T_DPM_SIZE (0x3<<2)
3842 #define DOORBELL_HDR_T_DPM_SIZE_SHIFT 2
3843 #define DOORBELL_HDR_T_CONN_TYPE (0xF<<4)
3844 #define DOORBELL_HDR_T_CONN_TYPE_SHIFT 4
3852#if defined(__BIG_ENDIAN)
3855 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3856 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3857 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3858 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3859 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3860 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3862#elif defined(__LITTLE_ENDIAN)
3865 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3866 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3867 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3868 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3869 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3870 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3940#if defined(__BIG_ENDIAN)
3941 uint16_t sb_id_and_flags;
3942 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3943 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3944 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3945 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3946 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3947 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3948 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3949 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3950 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3951 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3952 uint16_t status_block_index ;
3953#elif defined(__LITTLE_ENDIAN)
3954 uint16_t status_block_index ;
3955 uint16_t sb_id_and_flags;
3956 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3957 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3958 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3959 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3960 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3961 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3962 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3963 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3964 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3965 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3976 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3977 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3978 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3979 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3980 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3981 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3982 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3983 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3984 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3985 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3986 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3987 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3998 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3999 #define IGU_REGULAR_SB_INDEX_SHIFT 0
4000 #define IGU_REGULAR_RESERVED0 (0x1<<20)
4001 #define IGU_REGULAR_RESERVED0_SHIFT 20
4002 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
4003 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
4004 #define IGU_REGULAR_BUPDATE (0x1<<24)
4005 #define IGU_REGULAR_BUPDATE_SHIFT 24
4006 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
4007 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
4008 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
4009 #define IGU_REGULAR_RESERVED_1_SHIFT 27
4010 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
4011 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
4012 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
4013 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
4014 #define IGU_REGULAR_BCLEANUP (0x1<<31)
4015 #define IGU_REGULAR_BCLEANUP_SHIFT 31
4045 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
4046 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
4047 #define IGU_CTRL_REG_FID (0x7F<<12)
4048 #define IGU_CTRL_REG_FID_SHIFT 12
4049 #define IGU_CTRL_REG_RESERVED (0x1<<19)
4050 #define IGU_CTRL_REG_RESERVED_SHIFT 19
4051 #define IGU_CTRL_REG_TYPE (0x1<<20)
4052 #define IGU_CTRL_REG_TYPE_SHIFT 20
4053 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
4054 #define IGU_CTRL_REG_UNUSED_SHIFT 21
4086#if defined(__BIG_ENDIAN)
4089 #define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0)
4090 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
4091 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
4092 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
4093 #define ISCSI_TX_DOORBELL_SPARE (0x1<<7)
4094 #define ISCSI_TX_DOORBELL_SPARE_SHIFT 7
4096#elif defined(__LITTLE_ENDIAN)
4099 #define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0)
4100 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
4101 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
4102 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
4103 #define ISCSI_TX_DOORBELL_SPARE (0x1<<7)
4104 #define ISCSI_TX_DOORBELL_SPARE_SHIFT 7
4116 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
4117 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
4118 #define PARSING_FLAGS_INNER_VLAN_EXIST (0x1<<1)
4119 #define PARSING_FLAGS_INNER_VLAN_EXIST_SHIFT 1
4120 #define PARSING_FLAGS_OUTER_VLAN_EXIST (0x1<<2)
4121 #define PARSING_FLAGS_OUTER_VLAN_EXIST_SHIFT 2
4122 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
4123 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
4124 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
4125 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
4126 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
4127 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
4128 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
4129 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
4130 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
4131 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
4132 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
4133 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
4134 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
4135 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
4136 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
4137 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
4138 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
4139 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
4140 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
4141 #define PARSING_FLAGS_RESERVED0_SHIFT 14
4194 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
4195 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
4196 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
4197 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
4198 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
4199 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
4200 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
4201 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
4202 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
4203 #define SDM_OP_GEN_RESERVED_SHIFT 17
4216 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
4217 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
4218 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
4219 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
4220 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
4221 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
4230#if defined(__BIG_ENDIAN)
4231 uint16_t wnd_sz_lsb ;
4232 uint8_t wnd_sz_msb ;
4234#elif defined(__LITTLE_ENDIAN)
4236 uint8_t wnd_sz_msb ;
4237 uint16_t wnd_sz_lsb ;
4247#if defined(__BIG_ENDIAN)
4250 #define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0)
4251 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
4252 #define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5)
4253 #define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5
4255#elif defined(__LITTLE_ENDIAN)
4258 #define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0)
4259 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
4260 #define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5)
4261 #define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5
4272#if defined(__BIG_ENDIAN)
4275 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0)
4276 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
4277 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5)
4278 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5
4280#elif defined(__LITTLE_ENDIAN)
4283 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0)
4284 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
4285 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5)
4286 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5
4297#if defined(__BIG_ENDIAN)
4298 uint16_t nbytes_lsb ;
4300 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0)
4301 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
4302 #define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5)
4303 #define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5
4305#elif defined(__LITTLE_ENDIAN)
4308 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0)
4309 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
4310 #define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5)
4311 #define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5
4312 uint16_t nbytes_lsb ;
4322#if defined(__BIG_ENDIAN)
4323 uint16_t nbytes_lsb ;
4325 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0)
4326 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
4327 #define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5)
4328 #define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5
4330#elif defined(__LITTLE_ENDIAN)
4333 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0)
4334 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
4335 #define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5)
4336 #define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5
4337 uint16_t nbytes_lsb ;
4347#if defined(__BIG_ENDIAN)
4350 #define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0)
4351 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
4352 #define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6)
4353 #define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6
4354 #define TOE_TX_DOORBELL_FLUSH (0x1<<7)
4355 #define TOE_TX_DOORBELL_FLUSH_SHIFT 7
4357#elif defined(__LITTLE_ENDIAN)
4360 #define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0)
4361 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
4362 #define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6)
4363 #define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6
4364 #define TOE_TX_DOORBELL_FLUSH (0x1<<7)
4365 #define TOE_TX_DOORBELL_FLUSH_SHIFT 7
4386#if defined(__BIG_ENDIAN)
4387 uint8_t __tcp_agg_vars2 ;
4388 uint8_t __agg_val3 ;
4389 uint16_t __agg_val2 ;
4390#elif defined(__LITTLE_ENDIAN)
4391 uint16_t __agg_val2 ;
4392 uint8_t __agg_val3 ;
4393 uint8_t __tcp_agg_vars2 ;
4395#if defined(__BIG_ENDIAN)
4396 uint16_t __agg_val5;
4398 uint8_t __tcp_agg_vars3 ;
4399#elif defined(__LITTLE_ENDIAN)
4400 uint8_t __tcp_agg_vars3 ;
4402 uint16_t __agg_val5;
4410 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
4411 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4412 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
4413 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4414 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
4415 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
4416 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
4417 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4418 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
4419 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
4420 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
4421 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4422 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
4423 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4424 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
4425 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
4426 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
4427 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
4428 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
4429 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
4430 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
4431 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
4432 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
4433 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
4434 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
4435 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
4436 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
4437 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
4438 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
4439 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4440 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
4441 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4442 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
4443 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4444 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
4445 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4446 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
4447 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4448 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
4449 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4450 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
4451 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4462#if defined(__BIG_ENDIAN)
4463 uint16_t ulp_credit;
4465 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
4466 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4467 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
4468 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4469 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
4470 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4471 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
4472 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4473 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
4474 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
4475 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
4476 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4477 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
4478 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4480#elif defined(__LITTLE_ENDIAN)
4483 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
4484 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4485 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
4486 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4487 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
4488 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4489 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
4490 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4491 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
4492 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
4493 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
4494 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4495 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
4496 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4497 uint16_t ulp_credit;
4499#if defined(__BIG_ENDIAN)
4500 uint16_t __agg_val4;
4502 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
4503 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4504 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
4505 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4506 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
4507 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4508 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
4509 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4510 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
4511 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4512 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
4513 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4514 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
4515 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4516 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
4517 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
4518 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
4519 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
4520 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
4521 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
4522 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
4523 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4524 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
4525 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4526#elif defined(__LITTLE_ENDIAN)
4528 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
4529 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4530 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
4531 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4532 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
4533 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4534 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
4535 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4536 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
4537 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4538 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
4539 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4540 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
4541 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4542 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
4543 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
4544 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
4545 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
4546 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
4547 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
4548 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
4549 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4550 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
4551 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4552 uint16_t __agg_val4;
4564#if defined(__BIG_ENDIAN)
4565 uint8_t __tcp_agg_vars2 ;
4566 uint8_t __agg_val3 ;
4567 uint16_t __agg_val2 ;
4568#elif defined(__LITTLE_ENDIAN)
4569 uint16_t __agg_val2 ;
4570 uint8_t __agg_val3 ;
4571 uint8_t __tcp_agg_vars2 ;
4573#if defined(__BIG_ENDIAN)
4574 uint16_t __agg_val5;
4576 uint8_t __tcp_agg_vars3 ;
4577#elif defined(__LITTLE_ENDIAN)
4578 uint8_t __tcp_agg_vars3 ;
4580 uint16_t __agg_val5;
4588 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
4589 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4590 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
4591 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4592 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
4593 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
4594 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
4595 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4596 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
4597 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
4598 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
4599 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4600 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
4601 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4602 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
4603 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
4604 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
4605 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
4606 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
4607 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
4608 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
4609 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
4610 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
4611 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
4612 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
4613 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
4614 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
4615 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
4616 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
4617 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4618 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
4619 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4620 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
4621 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4622 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
4623 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4624 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
4625 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4626 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
4627 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4628 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
4629 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4640#if defined(__BIG_ENDIAN)
4641 uint16_t ulp_credit;
4643 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
4644 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4645 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
4646 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4647 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
4648 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4649 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
4650 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4651 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
4652 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4653 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
4654 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4655 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
4656 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
4658#elif defined(__LITTLE_ENDIAN)
4661 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
4662 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4663 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
4664 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4665 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
4666 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4667 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
4668 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4669 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
4670 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4671 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
4672 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4673 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
4674 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
4675 uint16_t ulp_credit;
4677#if defined(__BIG_ENDIAN)
4678 uint16_t __agg_val4;
4680 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
4681 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
4682 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
4683 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
4684 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
4685 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
4686 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
4687 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
4688 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
4689 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
4690 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
4691 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
4692 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
4693 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4694 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
4695 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4696 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
4697 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
4698 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
4699 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
4700 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
4701 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4702 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
4703 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4704#elif defined(__LITTLE_ENDIAN)
4706 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
4707 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
4708 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
4709 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
4710 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
4711 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
4712 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
4713 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
4714 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
4715 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
4716 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
4717 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
4718 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
4719 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4720 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
4721 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4722 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
4723 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
4724 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
4725 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
4726 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
4727 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4728 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
4729 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4730 uint16_t __agg_val4;
4742#if defined(__BIG_ENDIAN)
4743 uint8_t __tcp_agg_vars2 ;
4744 uint8_t __agg_val3 ;
4745 uint16_t __agg_val2 ;
4746#elif defined(__LITTLE_ENDIAN)
4747 uint16_t __agg_val2 ;
4748 uint8_t __agg_val3 ;
4749 uint8_t __tcp_agg_vars2 ;
4751#if defined(__BIG_ENDIAN)
4752 uint16_t __agg_val5;
4754 uint8_t __tcp_agg_vars3 ;
4755#elif defined(__LITTLE_ENDIAN)
4756 uint8_t __tcp_agg_vars3 ;
4758 uint16_t __agg_val5;
4766 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
4767 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4768 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
4769 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4770 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
4771 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
4772 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
4773 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4774 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
4775 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
4776 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
4777 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4778 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
4779 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4780 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
4781 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
4782 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
4783 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
4784 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
4785 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
4786 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
4787 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
4788 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
4789 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
4790 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
4791 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
4792 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
4793 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
4794 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
4795 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4796 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
4797 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4798 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
4799 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4800 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
4801 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4802 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
4803 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4804 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
4805 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4806 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
4807 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4820#if defined(__BIG_ENDIAN)
4821 uint8_t __tcp_agg_vars2 ;
4822 uint8_t __agg_val3 ;
4823 uint16_t __agg_val2 ;
4824#elif defined(__LITTLE_ENDIAN)
4825 uint16_t __agg_val2 ;
4826 uint8_t __agg_val3 ;
4827 uint8_t __tcp_agg_vars2 ;
4829#if defined(__BIG_ENDIAN)
4830 uint16_t __agg_val5;
4832 uint8_t __tcp_agg_vars3 ;
4833#elif defined(__LITTLE_ENDIAN)
4834 uint8_t __tcp_agg_vars3 ;
4836 uint16_t __agg_val5;
4844 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
4845 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4846 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
4847 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4848 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52 (0x3<<2)
4849 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52_SHIFT 2
4850 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
4851 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4852 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN (0x1<<6)
4853 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN_SHIFT 6
4854 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
4855 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4856 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
4857 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4858 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
4859 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
4860 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE (0x1<<10)
4861 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE_SHIFT 10
4862 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55 (0x1<<11)
4863 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55_SHIFT 11
4864 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN (0x1<<12)
4865 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN_SHIFT 12
4866 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN (0x1<<13)
4867 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN_SHIFT 13
4868 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56 (0x3<<14)
4869 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56_SHIFT 14
4870 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57 (0x3<<16)
4871 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57_SHIFT 16
4872 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
4873 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4874 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
4875 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4876 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
4877 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4878 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
4879 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4880 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
4881 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4882 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
4883 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4884 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
4885 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4896#if defined(__BIG_ENDIAN)
4897 uint16_t reserved54;
4899 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
4900 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4901 #define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1)
4902 #define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1
4903 #define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2)
4904 #define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2
4905 #define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3)
4906 #define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3
4907 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
4908 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4909 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
4910 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4911 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
4912 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4914#elif defined(__LITTLE_ENDIAN)
4917 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
4918 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4919 #define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1)
4920 #define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1
4921 #define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2)
4922 #define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2
4923 #define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3)
4924 #define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3
4925 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
4926 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4927 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
4928 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4929 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
4930 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4931 uint16_t reserved54;
4933#if defined(__BIG_ENDIAN)
4934 uint16_t __agg_val4;
4936 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
4937 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4938 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
4939 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4940 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2)
4941 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4942 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4)
4943 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4944 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6)
4945 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4946 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8)
4947 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4948 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
4949 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4950 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
4951 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4952 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12)
4953 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12
4954 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13)
4955 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13
4956 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14)
4957 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14
4958 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15)
4959 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15
4960#elif defined(__LITTLE_ENDIAN)
4962 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
4963 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4964 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
4965 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4966 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2)
4967 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4968 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4)
4969 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4970 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6)
4971 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4972 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8)
4973 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4974 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
4975 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4976 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
4977 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4978 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12)
4979 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12
4980 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13)
4981 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13
4982 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14)
4983 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14
4984 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15)
4985 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15
4986 uint16_t __agg_val4;
4998#if defined(__BIG_ENDIAN)
5000 uint8_t __reserved2;
5001 uint16_t __reserved1;
5002#elif defined(__LITTLE_ENDIAN)
5003 uint16_t __reserved1;
5004 uint8_t __reserved2;
5016#if defined(__BIG_ENDIAN)
5017 uint8_t __aux_counter_flags ;
5019 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
5020 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
5021 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
5022 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
5023 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
5024 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5025 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
5026 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5028 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5029 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5030 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5031 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5032 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
5033 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5034 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
5035 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5036 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
5037 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
5038 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
5039 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5041#elif defined(__LITTLE_ENDIAN)
5044 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5045 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5046 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5047 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5048 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
5049 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5050 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
5051 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5052 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
5053 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
5054 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
5055 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5057 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
5058 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
5059 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
5060 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
5061 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
5062 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5063 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
5064 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5065 uint8_t __aux_counter_flags ;
5067#if defined(__BIG_ENDIAN)
5070 uint16_t pbf_tx_seq_ack ;
5071#elif defined(__LITTLE_ENDIAN)
5072 uint16_t pbf_tx_seq_ack ;
5077#if defined(__BIG_ENDIAN)
5078 uint8_t agg_val3_th;
5081#elif defined(__LITTLE_ENDIAN)
5084 uint8_t agg_val3_th;
5088#if defined(__BIG_ENDIAN)
5091#elif defined(__LITTLE_ENDIAN)
5095#if defined(__BIG_ENDIAN)
5096 uint16_t __reserved2;
5097 uint8_t decision_rules;
5098 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
5099 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
5100 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
5101 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5102 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
5103 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
5104 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
5105 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
5106 uint8_t decision_rule_enable_bits;
5107 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
5108 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
5109 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
5110 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5111 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
5112 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
5113 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
5114 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5115 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
5116 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
5117 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
5118 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
5119 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
5120 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5121 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
5122 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5123#elif defined(__LITTLE_ENDIAN)
5124 uint8_t decision_rule_enable_bits;
5125 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
5126 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
5127 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
5128 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5129 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
5130 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
5131 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
5132 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5133 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
5134 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
5135 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
5136 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
5137 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
5138 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5139 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
5140 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5141 uint8_t decision_rules;
5142 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
5143 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
5144 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
5145 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5146 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
5147 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
5148 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
5149 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
5150 uint16_t __reserved2;
5160#if defined(__BIG_ENDIAN)
5161 uint8_t __aux_counter_flags ;
5163 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
5164 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
5165 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
5166 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
5167 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
5168 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5169 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
5170 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5172 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5173 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5174 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5175 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5176 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
5177 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5178 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
5179 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5180 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
5181 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
5182 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
5183 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5185#elif defined(__LITTLE_ENDIAN)
5188 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5189 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5190 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5191 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5192 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
5193 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5194 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
5195 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5196 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
5197 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
5198 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
5199 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5201 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
5202 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
5203 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
5204 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
5205 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
5206 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5207 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
5208 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5209 uint8_t __aux_counter_flags ;
5211#if defined(__BIG_ENDIAN)
5214 uint16_t __cq_local_comp_itt_val ;
5215#elif defined(__LITTLE_ENDIAN)
5216 uint16_t __cq_local_comp_itt_val ;
5221#if defined(__BIG_ENDIAN)
5222 uint8_t agg_val3_th;
5225#elif defined(__LITTLE_ENDIAN)
5228 uint8_t agg_val3_th;
5232#if defined(__BIG_ENDIAN)
5233 uint16_t agg_val2_th;
5235#elif defined(__LITTLE_ENDIAN)
5237 uint16_t agg_val2_th;
5239#if defined(__BIG_ENDIAN)
5240 uint16_t __reserved2;
5241 uint8_t decision_rules;
5242 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
5243 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5244 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
5245 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5246 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
5247 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5248 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
5249 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
5250 uint8_t decision_rule_enable_bits;
5251 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
5252 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
5253 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
5254 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5255 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
5256 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
5257 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
5258 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5259 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
5260 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
5261 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
5262 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
5263 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
5264 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5265 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
5266 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5267#elif defined(__LITTLE_ENDIAN)
5268 uint8_t decision_rule_enable_bits;
5269 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
5270 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
5271 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
5272 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5273 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
5274 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
5275 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
5276 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5277 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
5278 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
5279 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
5280 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
5281 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
5282 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5283 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
5284 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5285 uint8_t decision_rules;
5286 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
5287 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5288 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
5289 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5290 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
5291 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5292 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
5293 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
5294 uint16_t __reserved2;
5304#if defined(__BIG_ENDIAN)
5305 uint8_t __aux_counter_flags ;
5306 uint8_t __agg_vars2 ;
5307 uint8_t __agg_vars1 ;
5309#elif defined(__LITTLE_ENDIAN)
5311 uint8_t __agg_vars1 ;
5312 uint8_t __agg_vars2 ;
5313 uint8_t __aux_counter_flags ;
5315#if defined(__BIG_ENDIAN)
5317 uint8_t __agg_misc2;
5318 uint16_t __agg_misc1;
5319#elif defined(__LITTLE_ENDIAN)
5320 uint16_t __agg_misc1;
5321 uint8_t __agg_misc2;
5325#if defined(__BIG_ENDIAN)
5326 uint8_t __agg_val3_th;
5328 uint16_t __agg_misc3;
5329#elif defined(__LITTLE_ENDIAN)
5330 uint16_t __agg_misc3;
5332 uint8_t __agg_val3_th;
5336#if defined(__BIG_ENDIAN)
5337 uint16_t __agg_val2_th;
5339#elif defined(__LITTLE_ENDIAN)
5341 uint16_t __agg_val2_th;
5343#if defined(__BIG_ENDIAN)
5344 uint16_t __reserved2;
5345 uint8_t decision_rules;
5346 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
5347 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5348 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
5349 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5350 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
5351 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5352 #define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7)
5353 #define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7
5354 uint8_t __decision_rule_enable_bits ;
5355#elif defined(__LITTLE_ENDIAN)
5356 uint8_t __decision_rule_enable_bits ;
5357 uint8_t decision_rules;
5358 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
5359 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5360 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
5361 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5362 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
5363 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5364 #define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7)
5365 #define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7
5366 uint16_t __reserved2;
5377#if defined(__BIG_ENDIAN)
5378 uint8_t cdu_reserved ;
5381#elif defined(__LITTLE_ENDIAN)
5384 uint8_t cdu_reserved ;
5395#if defined(__BIG_ENDIAN)
5396 uint8_t tcp_agg_vars1;
5397 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
5398 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
5399 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
5400 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5401 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
5402 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
5404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
5405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
5406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
5407 uint8_t __reserved_da_cnt ;
5409#elif defined(__LITTLE_ENDIAN)
5411 uint8_t __reserved_da_cnt ;
5412 uint8_t tcp_agg_vars1;
5413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
5414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
5415 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
5416 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5417 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
5418 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
5420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
5421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
5422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
5428#if defined(__BIG_ENDIAN)
5429 uint8_t __agg_val8_th ;
5431 uint16_t tcp_agg_vars2;
5432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
5433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
5434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
5435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
5436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
5437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
5438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
5439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
5441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5442 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
5443 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
5444 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
5445 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
5446 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
5447 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
5449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
5450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
5451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
5453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5454 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
5455 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5456 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
5457 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5458#elif defined(__LITTLE_ENDIAN)
5459 uint16_t tcp_agg_vars2;
5460 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
5461 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
5462 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
5463 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
5464 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
5465 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
5466 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
5467 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5468 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
5469 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5470 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
5471 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
5472 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
5473 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
5474 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
5475 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5476 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
5477 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
5478 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
5479 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5480 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
5481 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5482 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
5483 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5484 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
5485 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5487 uint8_t __agg_val8_th ;
5493#if defined(__BIG_ENDIAN)
5494 uint16_t __xfrq_cons ;
5495 uint16_t __xfrq_prod ;
5496#elif defined(__LITTLE_ENDIAN)
5497 uint16_t __xfrq_prod ;
5498 uint16_t __xfrq_cons ;
5500#if defined(__BIG_ENDIAN)
5501 uint8_t __tcp_agg_vars5 ;
5502 uint8_t __tcp_agg_vars4 ;
5503 uint8_t __tcp_agg_vars3 ;
5504 uint8_t __reserved_force_pure_ack_cnt ;
5505#elif defined(__LITTLE_ENDIAN)
5506 uint8_t __reserved_force_pure_ack_cnt ;
5507 uint8_t __tcp_agg_vars3 ;
5508 uint8_t __tcp_agg_vars4 ;
5509 uint8_t __tcp_agg_vars5 ;
5512#if defined(__BIG_ENDIAN)
5513 uint16_t __xfrqe_mng ;
5514 uint16_t __tcp_agg_vars7 ;
5515#elif defined(__LITTLE_ENDIAN)
5516 uint16_t __tcp_agg_vars7 ;
5517 uint16_t __xfrqe_mng ;
5521#if defined(__BIG_ENDIAN)
5522 uint16_t __reserved3;
5523 uint8_t __reserved2;
5524 uint8_t __da_only_cnt ;
5525#elif defined(__LITTLE_ENDIAN)
5526 uint8_t __da_only_cnt ;
5527 uint8_t __reserved2;
5528 uint16_t __reserved3;
5537#if defined(__BIG_ENDIAN)
5540 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5541 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5542 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5543 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5544 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
5545 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
5546 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
5547 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
5548 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
5549 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5550 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
5551 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
5552 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
5553 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5554 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
5555 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
5557#elif defined(__LITTLE_ENDIAN)
5560 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5561 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5562 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5563 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5564 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
5565 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
5566 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
5567 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
5568 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
5569 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5570 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
5571 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
5572 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
5573 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5574 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
5575 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
5578#if defined(__BIG_ENDIAN)
5579 uint8_t cdu_reserved ;
5580 uint8_t __agg_vars4 ;
5582 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
5583 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
5584 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
5585 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
5587 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
5588 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
5589 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
5590 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
5591 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
5592 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
5593 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
5594 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
5595 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
5596 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
5597 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
5598 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5599#elif defined(__LITTLE_ENDIAN)
5601 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
5602 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
5603 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
5604 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
5605 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
5606 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
5607 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
5608 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
5609 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
5610 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
5611 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
5612 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5614 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
5615 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
5616 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
5617 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
5618 uint8_t __agg_vars4 ;
5619 uint8_t cdu_reserved ;
5622#if defined(__BIG_ENDIAN)
5624 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
5625 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
5626 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
5627 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
5628 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
5629 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
5630 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
5631 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
5633#elif defined(__LITTLE_ENDIAN)
5636 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
5637 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
5638 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
5639 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
5640 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
5641 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
5642 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
5643 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
5646#if defined(__BIG_ENDIAN)
5648 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
5649 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
5650 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
5651 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
5652 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
5653 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
5654 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
5655 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
5656 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
5657 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
5658 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
5659 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
5660 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
5661 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
5662 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
5663 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
5664 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
5665 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
5666 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
5667 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
5668 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
5669 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
5670 uint8_t agg_val3_th ;
5672 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
5673 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
5674 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
5675 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
5676 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
5677 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
5678#elif defined(__LITTLE_ENDIAN)
5680 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
5681 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
5682 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
5683 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
5684 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
5685 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
5686 uint8_t agg_val3_th ;
5688 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
5689 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
5690 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
5691 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
5692 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
5693 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
5694 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
5695 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
5696 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
5697 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
5698 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
5699 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
5700 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
5701 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
5702 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
5703 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
5704 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
5705 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
5706 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
5707 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
5708 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
5709 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
5711#if defined(__BIG_ENDIAN)
5712 uint16_t __agg_val11_th ;
5713 uint16_t __agg_val11 ;
5714#elif defined(__LITTLE_ENDIAN)
5715 uint16_t __agg_val11 ;
5716 uint16_t __agg_val11_th ;
5718#if defined(__BIG_ENDIAN)
5719 uint8_t __reserved1;
5720 uint8_t __agg_val6_th ;
5721 uint16_t __agg_val9 ;
5722#elif defined(__LITTLE_ENDIAN)
5723 uint16_t __agg_val9 ;
5724 uint8_t __agg_val6_th ;
5725 uint8_t __reserved1;
5727#if defined(__BIG_ENDIAN)
5728 uint16_t confq_cons ;
5729 uint16_t confq_prod ;
5730#elif defined(__LITTLE_ENDIAN)
5731 uint16_t confq_prod ;
5732 uint16_t confq_cons ;
5735 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
5736 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
5737 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
5738 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
5739#if defined(__BIG_ENDIAN)
5740 uint16_t __cache_wqe_db ;
5742#elif defined(__LITTLE_ENDIAN)
5744 uint16_t __cache_wqe_db ;
5746#if defined(__BIG_ENDIAN)
5749 uint8_t agg_val5_th ;
5751#elif defined(__LITTLE_ENDIAN)
5753 uint8_t agg_val5_th ;
5757#if defined(__BIG_ENDIAN)
5758 uint16_t __agg_misc1 ;
5759 uint16_t agg_limit1 ;
5760#elif defined(__LITTLE_ENDIAN)
5761 uint16_t agg_limit1 ;
5762 uint16_t __agg_misc1 ;
5775#if defined(__BIG_ENDIAN)
5776 uint8_t tcp_agg_vars1;
5777 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
5778 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
5779 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
5780 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5781 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
5782 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5783 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
5784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
5785 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
5786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
5789#elif defined(__LITTLE_ENDIAN)
5792 uint8_t tcp_agg_vars1;
5793 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
5794 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
5795 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
5796 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5797 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
5798 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
5800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
5801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
5802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
5808#if defined(__BIG_ENDIAN)
5809 uint8_t __agg_val8_th ;
5811 uint16_t tcp_agg_vars2;
5812 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
5813 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
5814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
5815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
5816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
5817 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
5818 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
5819 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5820 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
5821 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5822 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
5823 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
5824 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
5825 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
5826 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
5827 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
5829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
5830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
5831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
5833 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5834 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
5835 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5836 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
5837 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5838#elif defined(__LITTLE_ENDIAN)
5839 uint16_t tcp_agg_vars2;
5840 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
5841 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
5842 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
5843 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
5844 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
5845 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
5846 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
5847 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5848 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
5849 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5850 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
5851 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
5852 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
5853 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
5854 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
5855 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5856 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
5857 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
5858 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
5859 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5860 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
5861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
5863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
5865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5867 uint8_t __agg_val8_th ;
5873#if defined(__BIG_ENDIAN)
5874 uint16_t __agg_val7_th ;
5875 uint16_t __agg_val7 ;
5876#elif defined(__LITTLE_ENDIAN)
5877 uint16_t __agg_val7 ;
5878 uint16_t __agg_val7_th ;
5880#if defined(__BIG_ENDIAN)
5881 uint8_t __tcp_agg_vars5 ;
5882 uint8_t __tcp_agg_vars4 ;
5883 uint8_t __tcp_agg_vars3 ;
5884 uint8_t __force_pure_ack_cnt ;
5885#elif defined(__LITTLE_ENDIAN)
5886 uint8_t __force_pure_ack_cnt ;
5887 uint8_t __tcp_agg_vars3 ;
5888 uint8_t __tcp_agg_vars4 ;
5889 uint8_t __tcp_agg_vars5 ;
5892 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
5893 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
5894 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
5895 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
5896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
5897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
5898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
5899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
5900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
5901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
5902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
5903 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
5904 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
5905 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
5906 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
5907 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
5908 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
5909 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
5910 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
5911 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
5912 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
5913 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
5914 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
5915 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
5916 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
5917 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
5918 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
5919 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
5920 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
5921 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
5922 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
5923 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
5924 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
5925 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
5926 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
5927 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
5928 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
5929 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
5930 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
5931 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
5932 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
5933 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
5934 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
5935 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
5936#if defined(__BIG_ENDIAN)
5937 uint16_t __agg_misc6 ;
5938 uint16_t __tcp_agg_vars7 ;
5939#elif defined(__LITTLE_ENDIAN)
5940 uint16_t __tcp_agg_vars7 ;
5941 uint16_t __agg_misc6 ;
5945#if defined(__BIG_ENDIAN)
5946 uint16_t __reserved3;
5947 uint8_t __reserved2;
5948 uint8_t __da_only_cnt ;
5949#elif defined(__LITTLE_ENDIAN)
5950 uint8_t __da_only_cnt ;
5951 uint8_t __reserved2;
5952 uint16_t __reserved3;
5961#if defined(__BIG_ENDIAN)
5964 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5965 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5966 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5967 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5968 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
5969 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5970 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
5971 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5972 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
5973 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5974 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
5975 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
5976 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
5977 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5978 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
5979 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
5981#elif defined(__LITTLE_ENDIAN)
5984 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
5985 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5986 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
5987 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5988 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
5989 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5990 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
5991 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5992 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
5993 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5994 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
5995 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
5996 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
5997 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5998 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
5999 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
6002#if defined(__BIG_ENDIAN)
6003 uint8_t cdu_reserved ;
6004 uint8_t __agg_vars4 ;
6006 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
6007 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6008 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
6009 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
6011 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
6012 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
6013 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
6014 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
6015 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
6016 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6017 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
6018 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6019 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
6020 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
6021 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
6022 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6023#elif defined(__LITTLE_ENDIAN)
6025 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
6026 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
6027 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
6028 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
6029 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
6030 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6031 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
6032 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6033 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
6034 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
6035 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
6036 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6038 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
6039 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6040 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
6041 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
6042 uint8_t __agg_vars4 ;
6043 uint8_t cdu_reserved ;
6046#if defined(__BIG_ENDIAN)
6048 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
6049 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
6050 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
6051 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6052 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
6053 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6054 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
6055 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
6057#elif defined(__LITTLE_ENDIAN)
6060 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
6061 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
6062 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
6063 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6064 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
6065 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6066 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
6067 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
6070#if defined(__BIG_ENDIAN)
6072 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
6073 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
6074 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
6075 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
6076 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
6077 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
6078 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
6079 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
6080 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
6081 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
6082 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
6083 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
6084 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
6085 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
6086 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
6087 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
6088 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
6089 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
6090 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
6091 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
6092 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
6093 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
6094 uint8_t agg_val3_th ;
6096 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
6097 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
6098 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
6099 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
6100 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
6101 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
6102#elif defined(__LITTLE_ENDIAN)
6104 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
6105 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
6106 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
6107 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
6108 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
6109 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
6110 uint8_t agg_val3_th ;
6112 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
6113 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
6114 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
6115 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
6116 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
6117 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
6118 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
6119 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
6120 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
6121 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
6122 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
6123 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
6124 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
6125 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
6126 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
6127 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
6128 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
6129 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
6130 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
6131 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
6132 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
6133 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
6135#if defined(__BIG_ENDIAN)
6136 uint16_t __agg_val11_th ;
6137 uint16_t __gen_data ;
6138#elif defined(__LITTLE_ENDIAN)
6139 uint16_t __gen_data ;
6140 uint16_t __agg_val11_th ;
6142#if defined(__BIG_ENDIAN)
6143 uint8_t __reserved1;
6144 uint8_t __agg_val6_th ;
6145 uint16_t __agg_val9 ;
6146#elif defined(__LITTLE_ENDIAN)
6147 uint16_t __agg_val9 ;
6148 uint8_t __agg_val6_th ;
6149 uint8_t __reserved1;
6151#if defined(__BIG_ENDIAN)
6154#elif defined(__LITTLE_ENDIAN)
6159 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
6160 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
6161 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
6162 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24
6163#if defined(__BIG_ENDIAN)
6164 uint16_t r2tq_prod ;
6166#elif defined(__LITTLE_ENDIAN)
6168 uint16_t r2tq_prod ;
6170#if defined(__BIG_ENDIAN)
6173 uint8_t agg_val5_th ;
6175#elif defined(__LITTLE_ENDIAN)
6177 uint8_t agg_val5_th ;
6181#if defined(__BIG_ENDIAN)
6182 uint16_t __agg_misc1 ;
6183 uint16_t agg_limit1 ;
6184#elif defined(__LITTLE_ENDIAN)
6185 uint16_t agg_limit1 ;
6186 uint16_t __agg_misc1 ;
6199#if defined(__BIG_ENDIAN)
6200 uint8_t tcp_agg_vars1;
6201 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
6202 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
6203 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
6204 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
6205 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
6206 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
6207 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
6208 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
6209 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
6210 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
6213#elif defined(__LITTLE_ENDIAN)
6216 uint8_t tcp_agg_vars1;
6217 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
6218 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
6219 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
6220 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
6221 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
6222 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
6223 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
6224 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
6225 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
6226 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
6232#if defined(__BIG_ENDIAN)
6233 uint8_t __agg_val8_th ;
6235 uint16_t tcp_agg_vars2;
6236 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
6237 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
6238 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
6239 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
6240 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
6241 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
6242 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
6243 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
6244 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
6245 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
6246 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
6247 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
6248 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
6249 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
6250 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
6251 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
6252 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
6253 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
6254 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
6255 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
6256 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
6257 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
6258 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
6259 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
6260 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
6261 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
6262#elif defined(__LITTLE_ENDIAN)
6263 uint16_t tcp_agg_vars2;
6264 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
6265 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
6266 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
6267 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
6268 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
6269 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
6270 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
6271 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
6272 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
6273 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
6274 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
6275 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
6276 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
6277 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
6278 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
6279 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
6280 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
6281 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
6282 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
6283 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
6284 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
6285 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
6286 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
6287 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
6288 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
6289 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
6291 uint8_t __agg_val8_th ;
6297#if defined(__BIG_ENDIAN)
6298 uint16_t __agg_val7_th ;
6299 uint16_t __agg_val7 ;
6300#elif defined(__LITTLE_ENDIAN)
6301 uint16_t __agg_val7 ;
6302 uint16_t __agg_val7_th ;
6304#if defined(__BIG_ENDIAN)
6305 uint8_t __tcp_agg_vars5 ;
6306 uint8_t __tcp_agg_vars4 ;
6307 uint8_t __tcp_agg_vars3 ;
6308 uint8_t __force_pure_ack_cnt ;
6309#elif defined(__LITTLE_ENDIAN)
6310 uint8_t __force_pure_ack_cnt ;
6311 uint8_t __tcp_agg_vars3 ;
6312 uint8_t __tcp_agg_vars4 ;
6313 uint8_t __tcp_agg_vars5 ;
6316 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
6317 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
6318 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
6319 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
6320 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
6321 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
6322 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
6323 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
6324 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
6325 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
6326 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
6327 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
6328 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
6329 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
6330 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
6331 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
6332 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
6333 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
6334 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
6335 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
6336 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
6337 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
6338 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
6339 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
6340 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
6341 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
6342 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
6343 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
6344 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
6345 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
6346 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
6347 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
6348 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
6349 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
6350 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
6351 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
6352 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
6353 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
6354 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
6355 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
6356 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
6357 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
6358 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
6359 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
6360#if defined(__BIG_ENDIAN)
6361 uint16_t __agg_misc6 ;
6362 uint16_t __tcp_agg_vars7 ;
6363#elif defined(__LITTLE_ENDIAN)
6364 uint16_t __tcp_agg_vars7 ;
6365 uint16_t __agg_misc6 ;
6369#if defined(__BIG_ENDIAN)
6370 uint16_t __reserved3;
6371 uint8_t __reserved2;
6372 uint8_t __da_only_cnt ;
6373#elif defined(__LITTLE_ENDIAN)
6374 uint8_t __da_only_cnt ;
6375 uint8_t __reserved2;
6376 uint16_t __reserved3;
6385#if defined(__BIG_ENDIAN)
6388 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
6389 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
6390 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1)
6391 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1
6392 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2)
6393 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2
6394 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3)
6395 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3
6396 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
6397 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
6398 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
6399 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
6400 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6)
6401 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6
6402 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
6403 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
6405#elif defined(__LITTLE_ENDIAN)
6408 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
6409 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
6410 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1)
6411 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1
6412 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2)
6413 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2
6414 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3)
6415 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3
6416 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
6417 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
6418 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
6419 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
6420 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6)
6421 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6
6422 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
6423 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
6426#if defined(__BIG_ENDIAN)
6427 uint8_t cdu_reserved ;
6428 uint8_t __agg_vars4 ;
6430 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
6431 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6432 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6)
6433 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6
6435 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0)
6436 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
6437 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2)
6438 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2
6439 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
6440 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6441 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
6442 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6443 #define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5)
6444 #define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5
6445 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
6446 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6447#elif defined(__LITTLE_ENDIAN)
6449 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0)
6450 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
6451 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2)
6452 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2
6453 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
6454 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6455 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
6456 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6457 #define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5)
6458 #define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5
6459 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
6460 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6462 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
6463 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6464 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6)
6465 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6
6466 uint8_t __agg_vars4 ;
6467 uint8_t cdu_reserved ;
6470#if defined(__BIG_ENDIAN)
6472 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0)
6473 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
6474 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
6475 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6476 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
6477 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6478 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14)
6479 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14
6480 uint16_t __agg_val4_th ;
6481#elif defined(__LITTLE_ENDIAN)
6482 uint16_t __agg_val4_th ;
6484 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0)
6485 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
6486 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
6487 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6488 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
6489 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6490 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14)
6491 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14
6494#if defined(__BIG_ENDIAN)
6495 uint16_t __agg_vars7 ;
6496 uint8_t __agg_val3_th ;
6497 uint8_t __agg_vars6 ;
6498#elif defined(__LITTLE_ENDIAN)
6499 uint8_t __agg_vars6 ;
6500 uint8_t __agg_val3_th ;
6501 uint16_t __agg_vars7 ;
6503#if defined(__BIG_ENDIAN)
6504 uint16_t __agg_val11_th ;
6505 uint16_t __agg_val11 ;
6506#elif defined(__LITTLE_ENDIAN)
6507 uint16_t __agg_val11 ;
6508 uint16_t __agg_val11_th ;
6510#if defined(__BIG_ENDIAN)
6511 uint8_t __reserved1;
6512 uint8_t __agg_val6_th ;
6513 uint16_t __agg_val9 ;
6514#elif defined(__LITTLE_ENDIAN)
6515 uint16_t __agg_val9 ;
6516 uint8_t __agg_val6_th ;
6517 uint8_t __reserved1;
6519#if defined(__BIG_ENDIAN)
6520 uint16_t __agg_val2_th ;
6521 uint16_t cmp_bd_cons ;
6522#elif defined(__LITTLE_ENDIAN)
6523 uint16_t cmp_bd_cons ;
6524 uint16_t __agg_val2_th ;
6527#if defined(__BIG_ENDIAN)
6528 uint16_t __agg_misc0 ;
6529 uint16_t __agg_val4 ;
6530#elif defined(__LITTLE_ENDIAN)
6531 uint16_t __agg_val4 ;
6532 uint16_t __agg_misc0 ;
6534#if defined(__BIG_ENDIAN)
6535 uint8_t __agg_val3 ;
6536 uint8_t __agg_val6 ;
6537 uint8_t __agg_val5_th ;
6538 uint8_t __agg_val5 ;
6539#elif defined(__LITTLE_ENDIAN)
6540 uint8_t __agg_val5 ;
6541 uint8_t __agg_val5_th ;
6542 uint8_t __agg_val6 ;
6543 uint8_t __agg_val3 ;
6545#if defined(__BIG_ENDIAN)
6546 uint16_t __agg_misc1 ;
6547 uint16_t __bd_ind_max_val ;
6548#elif defined(__LITTLE_ENDIAN)
6549 uint16_t __bd_ind_max_val ;
6550 uint16_t __agg_misc1 ;
6563#if defined(__BIG_ENDIAN)
6564 uint16_t zero_fill2 ;
6565 uint8_t zero_fill1 ;
6567#elif defined(__LITTLE_ENDIAN)
6569 uint8_t zero_fill1 ;
6570 uint16_t zero_fill2 ;
6580#if defined(__BIG_ENDIAN)
6582 uint8_t zero_fill1 ;
6584#elif defined(__LITTLE_ENDIAN)
6586 uint8_t zero_fill1 ;
6621enum classify_rule_action_type
6655 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
6656 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
6657 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
6658 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
6659 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
6660 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
6661 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
6662 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
6691 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
6692 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
6693 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
6694 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
6695 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
6696 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
6697 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
6698 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
6699 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
6700 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
6701 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
6702 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
6703 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
6704 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
6705 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
6706 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
6735 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
6736 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
6737 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
6738 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
6739 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
6740 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
6741 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
6742 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
6743 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
6744 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
6842 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
6843 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
6844 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
6845 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
6846 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
6847 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
6848 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
6849 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
6850 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
6851 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
7013 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
7014 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
7015 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
7016 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
7017 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
7018 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
7039 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
7040 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
7041 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
7042 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
7043 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
7044 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
7045 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
7046 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
7047 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
7048 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
7049 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
7050 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
7051 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
7052 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
7054 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
7055 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
7056 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
7057 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
7058 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
7059 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
7060 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
7061 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
7062 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
7063 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
7064 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
7065 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
7089 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
7090 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
7091 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
7092 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
7093 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
7094 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
7099 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
7100 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
7101 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
7102 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
7103 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
7104 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
7105 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
7106 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
7107 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
7108 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
7109 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
7110 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
7111 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
7112 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
7113 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
7114 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
7166#if defined(__BIG_ENDIAN)
7169#elif defined(__LITTLE_ENDIAN)
7173#if defined(__BIG_ENDIAN)
7176#elif defined(__LITTLE_ENDIAN)
7180#if defined(__BIG_ENDIAN)
7183#elif defined(__LITTLE_ENDIAN)
7202 #define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
7203 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
7204 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
7205 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
7224 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
7225 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
7226 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
7227 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
7228 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
7229 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
7230 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
7231 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
7306 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
7307 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
7308 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
7309 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
7310 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
7311 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
7312 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
7313 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
7314 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
7315 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
7316 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
7317 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
7318 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
7319 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
7320 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
7321 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
7322 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
7323 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
7324 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
7325 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
7326 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
7327 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
7362 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
7363 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
7364 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
7365 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
7366 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
7367 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
7371 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
7372 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
7373 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
7374 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
7440 #define SPE_HDR_T_CID (0xFFFFFF<<0)
7441 #define SPE_HDR_T_CID_SHIFT 0
7442 #define SPE_HDR_T_CMD_ID (0xFFUL<<24)
7443 #define SPE_HDR_T_CMD_ID_SHIFT 24
7445 #define SPE_HDR_T_CONN_TYPE (0xFF<<0)
7446 #define SPE_HDR_T_CONN_TYPE_SHIFT 0
7447 #define SPE_HDR_T_FUNCTION_ID (0xFF<<8)
7448 #define SPE_HDR_T_FUNCTION_ID_SHIFT 8
7566 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
7567 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
7568 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
7569 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
7570 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
7571 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
7572 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
7573 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
7574 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
7575 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
7576 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
7577 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
7578 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
7579 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
7594 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
7595 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
7596 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
7597 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
7598 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
7599 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
7600 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
7601 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
7602 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
7603 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
7612 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
7613 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
7614 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
7615 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
7616 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
7617 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
7618 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
7619 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
7620 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
7621 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
7622 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
7623 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
7625 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
7626 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
7627 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
7628 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
7629 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
7630 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
7631 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
7632 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
7633 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
7634 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
7635 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
7636 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
7637 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
7638 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
7639 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
7640 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
7656 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
7657 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
7658 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
7659 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
7660 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
7661 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
7662 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
7663 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
7664 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
7665 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
7674 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
7675 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
7676 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
7677 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
7678 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
7679 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
7680 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
7681 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
7682 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
7683 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
7684 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
7685 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
7686 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
7687 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
7689 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
7690 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
7691 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
7692 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
7695 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
7696 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
7697 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
7698 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
7699 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
7700 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
7701 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
7702 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
7703 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
7704 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
7705 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
7706 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
7707 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
7708 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
7709 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
7710 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
7796 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
7797 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
7798 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
7799 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
7800 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
7801 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
7802 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
7803 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
7804 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
7805 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
7806 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
7807 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
7879 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
7880 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
7881 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
7882 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
7883 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
7884 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
7885 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
7886 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
7887 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
7888 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
7889 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
7890 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
7891 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
7892 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
7929#if defined(__BIG_ENDIAN)
7932#elif defined(__LITTLE_ENDIAN)
7936#if defined(__BIG_ENDIAN)
7939#elif defined(__LITTLE_ENDIAN)
8011 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
8012 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
8013 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
8014 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
8015 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
8016 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
8017 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
8018 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
8019 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
8020 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
8021 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
8022 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
8199 #define FCOE_KCQE_RESERVED0 (0x7<<0)
8200 #define FCOE_KCQE_RESERVED0_SHIFT 0
8201 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
8202 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
8203 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
8204 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
8205 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
8206 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
8217 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
8218 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
8219 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
8220 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
8221 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
8222 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
8243 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
8244 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
8245 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
8246 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
8247 #define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED (0x1<<7)
8248 #define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED_SHIFT 7
8321 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
8322 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
8323 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
8324 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
8325 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
8326 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
8332 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
8333 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
8334 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
8335 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
8336 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
8337 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
8338 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
8339 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
8340 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
8341 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
8342 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
8343 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
8344 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
8345 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
8346 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
8347 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
8389 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
8390 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
8391 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
8392 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
8393 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
8394 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
8487 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
8488 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
8489 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
8490 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
8491 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
8492 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
8493 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
8494 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
8495 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
8496 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
8497 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
8498 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
8499 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
8500 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
8569 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
8570 #define FCOE_SQE_TASK_ID_SHIFT 0
8571 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
8572 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
8627 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
8628 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
8629 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
8630 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
8631 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
8632 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
8633 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
8634 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
8635 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
8636 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
8638 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
8639 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
8640 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
8641 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
8642 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
8643 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
8644 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
8645 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
8646 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7)
8647 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7
8668 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
8669 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
8670 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
8671 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
8680 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
8681 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
8682 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
8683 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
8684 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
8685 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
8686 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
8687 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
8688 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
8689 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
8690 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
8691 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
8692 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
8693 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
8694 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
8695 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
8736 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
8737 #define FCOE_XFRQE_TASK_ID_SHIFT 0
8738 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
8739 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
8785#if defined(__BIG_ENDIAN)
8786 uint8_t mid_seq_proc_flag ;
8787 uint8_t tce_in_cam_flag ;
8788 uint8_t tce_on_ior_flag ;
8789 uint8_t en_cached_tce_flag ;
8790#elif defined(__LITTLE_ENDIAN)
8791 uint8_t en_cached_tce_flag ;
8792 uint8_t tce_on_ior_flag ;
8793 uint8_t tce_in_cam_flag ;
8794 uint8_t mid_seq_proc_flag ;
8796#if defined(__BIG_ENDIAN)
8797 uint8_t tce_cam_addr ;
8798 uint8_t cached_conn_flag ;
8800#elif defined(__LITTLE_ENDIAN)
8802 uint8_t cached_conn_flag ;
8803 uint8_t tce_cam_addr ;
8805#if defined(__BIG_ENDIAN)
8806 uint16_t dma_tce_ram_addr ;
8807 uint16_t tce_ram_addr ;
8808#elif defined(__LITTLE_ENDIAN)
8809 uint16_t tce_ram_addr ;
8810 uint16_t dma_tce_ram_addr ;
8812#if defined(__BIG_ENDIAN)
8814 uint16_t wr_done_seq ;
8815#elif defined(__LITTLE_ENDIAN)
8816 uint16_t wr_done_seq ;
8827#if defined(__BIG_ENDIAN)
8828 uint16_t fcoe_conn_id ;
8830 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
8831 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
8832 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
8833 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
8834 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
8835 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
8836 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
8837 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
8838 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
8839 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
8840 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
8841 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
8842 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
8843 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
8844 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7)
8845 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7
8846 #define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8)
8847 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8
8848#elif defined(__LITTLE_ENDIAN)
8850 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
8851 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
8852 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
8853 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
8854 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
8855 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
8856 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
8857 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
8858 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
8859 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
8860 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
8861 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
8862 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
8863 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
8864 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7)
8865 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7
8866 #define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8)
8867 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8
8868 uint16_t fcoe_conn_id ;
8870#if defined(__BIG_ENDIAN)
8871 uint8_t hc_csdm_byte_en ;
8875#elif defined(__LITTLE_ENDIAN)
8879 uint8_t hc_csdm_byte_en ;
8881#if defined(__BIG_ENDIAN)
8882 uint16_t rx_total_conc_seqs ;
8883 uint16_t rx_max_fc_pay_len ;
8884#elif defined(__LITTLE_ENDIAN)
8885 uint16_t rx_max_fc_pay_len ;
8886 uint16_t rx_total_conc_seqs ;
8888#if defined(__BIG_ENDIAN)
8889 uint8_t task_pbe_idx_off ;
8890 uint8_t task_in_page_log_size ;
8891 uint16_t rx_max_conc_seqs ;
8892#elif defined(__LITTLE_ENDIAN)
8893 uint16_t rx_max_conc_seqs ;
8894 uint8_t task_in_page_log_size ;
8895 uint8_t task_pbe_idx_off ;
8905 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
8906 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0
8907 #define FCOE_IDX16_FIELDS_MSB (0x1<<15)
8908 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15
8925#if defined(__BIG_ENDIAN)
8929#elif defined(__LITTLE_ENDIAN)
8993#if defined(__BIG_ENDIAN)
8996#elif defined(__LITTLE_ENDIAN)
9000#if defined(__BIG_ENDIAN)
9001 uint16_t xfrq_prod ;
9003#elif defined(__LITTLE_ENDIAN)
9005 uint16_t xfrq_prod ;
9007#if defined(__BIG_ENDIAN)
9009 uint16_t hc_cram_address ;
9010#elif defined(__LITTLE_ENDIAN)
9011 uint16_t hc_cram_address ;
9014#if defined(__BIG_ENDIAN)
9015 uint16_t sq_xfrq_lcq_confq_size ;
9016 uint16_t confq_prod ;
9017#elif defined(__LITTLE_ENDIAN)
9018 uint16_t confq_prod ;
9019 uint16_t sq_xfrq_lcq_confq_size ;
9021#if defined(__BIG_ENDIAN)
9022 uint8_t hc_csdm_agg_int ;
9024 uint8_t available_rqes ;
9025 uint8_t sp_q_flush_cnt ;
9026#elif defined(__LITTLE_ENDIAN)
9027 uint8_t sp_q_flush_cnt ;
9028 uint8_t available_rqes ;
9030 uint8_t hc_csdm_agg_int ;
9032#if defined(__BIG_ENDIAN)
9033 uint16_t num_pend_tasks ;
9034 uint16_t pbf_ack_ram_addr ;
9035#elif defined(__LITTLE_ENDIAN)
9036 uint16_t pbf_ack_ram_addr ;
9037 uint16_t num_pend_tasks ;
9056#if defined(__BIG_ENDIAN)
9057 uint8_t remote_addr_4 ;
9058 uint8_t remote_addr_5 ;
9059 uint8_t local_addr_0 ;
9060 uint8_t local_addr_1 ;
9061#elif defined(__LITTLE_ENDIAN)
9062 uint8_t local_addr_1 ;
9063 uint8_t local_addr_0 ;
9064 uint8_t remote_addr_5 ;
9065 uint8_t remote_addr_4 ;
9067#if defined(__BIG_ENDIAN)
9068 uint8_t remote_addr_0 ;
9069 uint8_t remote_addr_1 ;
9070 uint8_t remote_addr_2 ;
9071 uint8_t remote_addr_3 ;
9072#elif defined(__LITTLE_ENDIAN)
9073 uint8_t remote_addr_3 ;
9074 uint8_t remote_addr_2 ;
9075 uint8_t remote_addr_1 ;
9076 uint8_t remote_addr_0 ;
9078#if defined(__BIG_ENDIAN)
9079 uint16_t reserved_vlan_type ;
9081 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
9082 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
9083 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
9084 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
9085 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
9086 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
9087#elif defined(__LITTLE_ENDIAN)
9089 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
9090 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
9091 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
9092 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
9093 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
9094 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
9095 uint16_t reserved_vlan_type ;
9097#if defined(__BIG_ENDIAN)
9098 uint8_t local_addr_2 ;
9099 uint8_t local_addr_3 ;
9100 uint8_t local_addr_4 ;
9101 uint8_t local_addr_5 ;
9102#elif defined(__LITTLE_ENDIAN)
9103 uint8_t local_addr_5 ;
9104 uint8_t local_addr_4 ;
9105 uint8_t local_addr_3 ;
9106 uint8_t local_addr_2 ;
9116 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
9117 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
9118 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
9119 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
9120 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3)
9121 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3
9122 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
9123 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
9124 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
9125 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
9126 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
9127 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
9128 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7)
9129 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7
9144#if defined(__BIG_ENDIAN)
9145 uint16_t cached_sge_off;
9146 uint8_t cached_num_sges ;
9147 uint8_t cached_sge_idx ;
9148#elif defined(__LITTLE_ENDIAN)
9149 uint8_t cached_sge_idx ;
9150 uint8_t cached_num_sges ;
9151 uint16_t cached_sge_off;
9155#if defined(__BIG_ENDIAN)
9156 uint16_t num_of_pending_tasks ;
9157 uint16_t buf_len_0 ;
9158#elif defined(__LITTLE_ENDIAN)
9159 uint16_t buf_len_0 ;
9160 uint16_t num_of_pending_tasks ;
9164#if defined(__BIG_ENDIAN)
9165 uint16_t task_pbe_idx_off ;
9166 uint16_t buf_len_1 ;
9167#elif defined(__LITTLE_ENDIAN)
9168 uint16_t buf_len_1 ;
9169 uint16_t task_pbe_idx_off ;
9173#if defined(__BIG_ENDIAN)
9175 uint16_t buf_len_2 ;
9176#elif defined(__LITTLE_ENDIAN)
9177 uint16_t buf_len_2 ;
9188 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE (0x1<<0)
9189 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE_SHIFT 0
9190 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG (0x1<<1)
9191 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG_SHIFT 1
9192 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED (0x3F<<2)
9193 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED_SHIFT 2
9202 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY (0x7<<0)
9203 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY_SHIFT 0
9204 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3)
9205 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3
9206 #define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY (0x7<<4)
9207 #define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY_SHIFT 4
9208 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0x1<<7)
9209 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 7
9218 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
9219 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
9220 #define FCOE_VLAN_FIELDS_CLI (0x1<<12)
9221 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
9222 #define FCOE_VLAN_FIELDS_PRI (0x7<<13)
9223 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
9249#if defined(__BIG_ENDIAN)
9252#elif defined(__LITTLE_ENDIAN)
9256#if defined(__BIG_ENDIAN)
9259#elif defined(__LITTLE_ENDIAN)
9263#if defined(__BIG_ENDIAN)
9264 uint16_t sq_xfrq_lcq_confq_size ;
9265 uint16_t tx_max_fc_pay_len ;
9266#elif defined(__LITTLE_ENDIAN)
9267 uint16_t tx_max_fc_pay_len ;
9268 uint16_t sq_xfrq_lcq_confq_size ;
9271#if defined(__BIG_ENDIAN)
9276#elif defined(__LITTLE_ENDIAN)
9282#if defined(__BIG_ENDIAN)
9286#elif defined(__LITTLE_ENDIAN)
9296#if defined(__BIG_ENDIAN)
9297 uint8_t tx_max_conc_seqs_c3 ;
9300 uint8_t data_pb_cmd_size ;
9301#elif defined(__LITTLE_ENDIAN)
9302 uint8_t data_pb_cmd_size ;
9305 uint8_t tx_max_conc_seqs_c3 ;
9307#if defined(__BIG_ENDIAN)
9308 uint16_t fcoe_tx_stat_params_ram_addr ;
9309 uint16_t fcoe_tx_fc_seq_ram_addr ;
9310#elif defined(__LITTLE_ENDIAN)
9311 uint16_t fcoe_tx_fc_seq_ram_addr ;
9312 uint16_t fcoe_tx_stat_params_ram_addr ;
9314#if defined(__BIG_ENDIAN)
9315 uint8_t fcp_cmd_line_credit;
9316 uint8_t eth_hdr_size ;
9318#elif defined(__LITTLE_ENDIAN)
9320 uint8_t eth_hdr_size ;
9321 uint8_t fcp_cmd_line_credit;
9323#if defined(__BIG_ENDIAN)
9325 uint8_t page_log_size ;
9327#elif defined(__LITTLE_ENDIAN)
9329 uint8_t page_log_size ;
9332#if defined(__BIG_ENDIAN)
9333 uint16_t fcp_cmd_frame_size ;
9334 uint16_t pbf_addr_ff ;
9335#elif defined(__LITTLE_ENDIAN)
9336 uint16_t pbf_addr_ff ;
9337 uint16_t fcp_cmd_frame_size ;
9339#if defined(__BIG_ENDIAN)
9342 uint8_t cache_xfrq_cons ;
9343 uint8_t cache_sq_cons ;
9344#elif defined(__LITTLE_ENDIAN)
9345 uint8_t cache_sq_cons ;
9346 uint8_t cache_xfrq_cons ;
9410#if defined(__BIG_ENDIAN)
9413#elif defined(__LITTLE_ENDIAN)
9472#if defined(__BIG_ENDIAN)
9474 #define ISCSI_KCQE_RESERVED0 (0x7<<0)
9475 #define ISCSI_KCQE_RESERVED0_SHIFT 0
9476 #define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3)
9477 #define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3
9478 #define ISCSI_KCQE_LAYER_CODE (0x7<<4)
9479 #define ISCSI_KCQE_LAYER_CODE_SHIFT 4
9480 #define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7)
9481 #define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7
9483 uint16_t qe_self_seq ;
9484#elif defined(__LITTLE_ENDIAN)
9485 uint16_t qe_self_seq ;
9488 #define ISCSI_KCQE_RESERVED0 (0x7<<0)
9489 #define ISCSI_KCQE_RESERVED0_SHIFT 0
9490 #define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3)
9491 #define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3
9492 #define ISCSI_KCQE_LAYER_CODE (0x7<<4)
9493 #define ISCSI_KCQE_LAYER_CODE_SHIFT 4
9494 #define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7)
9495 #define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7
9505#if defined(__BIG_ENDIAN)
9507 #define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0)
9508 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
9509 #define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4)
9510 #define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4
9511 #define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7)
9512 #define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7
9514#elif defined(__LITTLE_ENDIAN)
9517 #define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0)
9518 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
9519 #define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4)
9520 #define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4
9521 #define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7)
9522 #define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7
9531#if defined(__BIG_ENDIAN)
9533 uint8_t hsi_version ;
9535#elif defined(__LITTLE_ENDIAN)
9537 uint8_t hsi_version ;
9542#if defined(__BIG_ENDIAN)
9543 uint16_t num_ccells_per_conn ;
9544 uint16_t num_tasks_per_conn ;
9545#elif defined(__LITTLE_ENDIAN)
9546 uint16_t num_tasks_per_conn ;
9547 uint16_t num_ccells_per_conn ;
9549#if defined(__BIG_ENDIAN)
9550 uint16_t sq_wqes_per_page ;
9551 uint16_t sq_num_wqes ;
9552#elif defined(__LITTLE_ENDIAN)
9553 uint16_t sq_num_wqes ;
9554 uint16_t sq_wqes_per_page ;
9556#if defined(__BIG_ENDIAN)
9557 uint8_t cq_log_wqes_per_page ;
9559 #define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0)
9560 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
9561 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4)
9562 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4
9563 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5)
9564 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5
9565 #define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6)
9566 #define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6
9567 uint16_t cq_num_wqes ;
9568#elif defined(__LITTLE_ENDIAN)
9569 uint16_t cq_num_wqes ;
9571 #define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0)
9572 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
9573 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4)
9574 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4
9575 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5)
9576 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5
9577 #define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6)
9578 #define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6
9579 uint8_t cq_log_wqes_per_page ;
9581#if defined(__BIG_ENDIAN)
9582 uint16_t cq_num_pages ;
9583 uint16_t sq_num_pages ;
9584#elif defined(__LITTLE_ENDIAN)
9585 uint16_t sq_num_pages ;
9586 uint16_t cq_num_pages ;
9588#if defined(__BIG_ENDIAN)
9589 uint16_t rq_buffer_size ;
9590 uint16_t rq_num_wqes ;
9591#elif defined(__LITTLE_ENDIAN)
9592 uint16_t rq_num_wqes ;
9593 uint16_t rq_buffer_size ;
9602#if defined(__BIG_ENDIAN)
9604 uint16_t max_cq_sqn ;
9605#elif defined(__LITTLE_ENDIAN)
9606 uint16_t max_cq_sqn ;
9619#if defined(__BIG_ENDIAN)
9621 uint16_t iscsi_conn_id ;
9622#elif defined(__LITTLE_ENDIAN)
9623 uint16_t iscsi_conn_id ;
9647#if defined(__BIG_ENDIAN)
9650#elif defined(__LITTLE_ENDIAN)
9666#if defined(__BIG_ENDIAN)
9669#elif defined(__LITTLE_ENDIAN)
9682#if defined(__BIG_ENDIAN)
9685#elif defined(__LITTLE_ENDIAN)
9689#if defined(__BIG_ENDIAN)
9690 uint8_t session_error_recovery_level ;
9691 uint8_t max_outstanding_r2ts ;
9694 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0)
9695 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
9696 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1)
9697 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1
9698 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2)
9699 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
9700 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3)
9701 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
9702 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4)
9703 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
9704 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6)
9705 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
9706#elif defined(__LITTLE_ENDIAN)
9708 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0)
9709 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
9710 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1)
9711 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1
9712 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2)
9713 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
9714 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3)
9715 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
9716 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4)
9717 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
9718 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6)
9719 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
9721 uint8_t max_outstanding_r2ts ;
9722 uint8_t session_error_recovery_level ;
9737#if defined(__BIG_ENDIAN)
9739 uint16_t iscsi_conn_id ;
9740#elif defined(__LITTLE_ENDIAN)
9741 uint16_t iscsi_conn_id ;
9765#if defined(__BIG_ENDIAN)
9768#elif defined(__LITTLE_ENDIAN)
9778#if defined(__BIG_ENDIAN)
9779 uint16_t reserved0 ;
9781#elif defined(__LITTLE_ENDIAN)
9783 uint16_t reserved0 ;
9795 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0)
9796 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
9797 #define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN (0x1<<12)
9798 #define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN_SHIFT 12
9799 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13)
9800 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13
9801 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14)
9802 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14
9818#if defined(__BIG_ENDIAN)
9819 uint16_t hq_bd_itt ;
9820 uint16_t iscsi_conn_id;
9821#elif defined(__LITTLE_ENDIAN)
9822 uint16_t iscsi_conn_id;
9823 uint16_t hq_bd_itt ;
9827#if defined(__BIG_ENDIAN)
9829 uint8_t cq_proc_en_bit_map ;
9830 uint8_t cq_pend_comp_itt_valid_bit_map ;
9831 uint8_t hq_bd_opcode ;
9832#elif defined(__LITTLE_ENDIAN)
9833 uint8_t hq_bd_opcode ;
9834 uint8_t cq_pend_comp_itt_valid_bit_map ;
9835 uint8_t cq_proc_en_bit_map ;
9839#if defined(__BIG_ENDIAN)
9841 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
9842 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
9843 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
9844 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
9845 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
9846 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
9847 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
9848 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
9849 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
9850 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
9851 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
9852 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
9854#elif defined(__LITTLE_ENDIAN)
9857 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
9858 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
9859 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
9860 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
9861 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
9862 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
9863 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
9864 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
9865 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
9866 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
9867 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
9868 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
9879#if defined(__BIG_ENDIAN)
9882 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
9883 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
9884 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
9885 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
9886 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
9887 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
9888 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
9889 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
9890 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
9891 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
9893#elif defined(__LITTLE_ENDIAN)
9896 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
9897 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
9898 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
9899 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
9900 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
9901 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
9902 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
9903 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
9904 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
9905 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
9909 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
9910 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
9911 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
9912 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
9954#if defined(__BIG_ENDIAN)
9957#elif defined(__LITTLE_ENDIAN)
9972#if defined(__BIG_ENDIAN)
9974 uint16_t r2tq_prod ;
9975#elif defined(__LITTLE_ENDIAN)
9976 uint16_t r2tq_prod ;
9991#if defined(__BIG_ENDIAN)
9992 uint16_t curr_sge_offset ;
9993 uint16_t local_sge_0_size ;
9994#elif defined(__LITTLE_ENDIAN)
9995 uint16_t local_sge_0_size ;
9996 uint16_t curr_sge_offset ;
10000#if defined(__BIG_ENDIAN)
10001 uint8_t exp_padding_2b ;
10002 uint8_t nal_len_3b ;
10003 uint16_t local_sge_1_size ;
10004#elif defined(__LITTLE_ENDIAN)
10005 uint16_t local_sge_1_size ;
10006 uint8_t nal_len_3b ;
10007 uint8_t exp_padding_2b ;
10009#if defined(__BIG_ENDIAN)
10011 uint8_t local_sge_index_2b ;
10012 uint16_t reserved7;
10013#elif defined(__LITTLE_ENDIAN)
10014 uint16_t reserved7;
10015 uint8_t local_sge_index_2b ;
10020 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0)
10021 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
10022 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24)
10023 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24
10025 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0)
10026 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
10027 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24)
10028 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24
10030 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0)
10031 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
10032 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24)
10033 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24
10049#if defined(__BIG_ENDIAN)
10051 uint16_t iscsi_conn_id;
10052#elif defined(__LITTLE_ENDIAN)
10053 uint16_t iscsi_conn_id;
10057#if defined(__BIG_ENDIAN)
10058 uint8_t hdr_second_byte_union ;
10059 uint8_t bitfield_0;
10060 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
10061 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
10062 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
10063 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
10064 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
10065 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
10066 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
10067 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
10068 uint8_t task_pdu_cache_index;
10069 uint8_t task_pbe_cache_index;
10070#elif defined(__LITTLE_ENDIAN)
10071 uint8_t task_pbe_cache_index;
10072 uint8_t task_pdu_cache_index;
10073 uint8_t bitfield_0;
10074 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
10075 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
10076 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
10077 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
10078 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
10079 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
10080 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
10081 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
10082 uint8_t hdr_second_byte_union ;
10084#if defined(__BIG_ENDIAN)
10085 uint16_t reserved3 ;
10086 uint8_t reserved2 ;
10087 uint8_t acDecrement ;
10088#elif defined(__LITTLE_ENDIAN)
10089 uint8_t acDecrement ;
10090 uint8_t reserved2 ;
10091 uint16_t reserved3 ;
10094#if defined(__BIG_ENDIAN)
10095 uint8_t hdr_opcode ;
10097 uint16_t reserved5 ;
10098#elif defined(__LITTLE_ENDIAN)
10099 uint16_t reserved5 ;
10101 uint8_t hdr_opcode ;
10104 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0)
10105 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
10106 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24)
10107 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24
10109 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0)
10110 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
10111 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24)
10112 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24
10113 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25)
10114 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25
10115 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26)
10116 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26
10117 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27)
10118 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27
10119 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28)
10120 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28
10121 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29)
10122 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29
10123 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31)
10124 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31
10133 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0)
10134 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
10135 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24)
10136 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24
10137 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25)
10138 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25
10139 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26)
10140 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26
10141 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27)
10142 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27
10143 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28)
10144 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28
10145 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29)
10146 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29
10147 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30)
10148 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30
10149 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31)
10150 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31
10152 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0)
10153 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
10154 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24)
10155 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24
10156 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25)
10157 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25
10158 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26)
10159 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26
10160 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27)
10161 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27
10162 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28)
10163 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28
10164 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29)
10165 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29
10166 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30)
10167 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30
10168 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31)
10169 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31
10170#if defined(__BIG_ENDIAN)
10172 uint8_t tcp_sm_state ;
10174#elif defined(__LITTLE_ENDIAN)
10176 uint8_t tcp_sm_state ;
10188#if defined(__BIG_ENDIAN)
10189 uint8_t retransmit_count ;
10190 uint8_t ka_max_probe_count ;
10191 uint8_t persist_probe_count ;
10192 uint8_t ka_probe_count ;
10193#elif defined(__LITTLE_ENDIAN)
10194 uint8_t ka_probe_count ;
10195 uint8_t persist_probe_count ;
10196 uint8_t ka_max_probe_count ;
10197 uint8_t retransmit_count ;
10199#if defined(__BIG_ENDIAN)
10200 uint8_t statistics_counter_id ;
10201 uint8_t ooo_support_mode;
10202 uint8_t snd_wnd_scale ;
10203 uint8_t dup_ack_count ;
10204#elif defined(__LITTLE_ENDIAN)
10205 uint8_t dup_ack_count ;
10206 uint8_t snd_wnd_scale ;
10207 uint8_t ooo_support_mode;
10208 uint8_t statistics_counter_id ;
10215#if defined(__BIG_ENDIAN)
10216 uint16_t second_isle_address ;
10217 uint16_t recent_seg_wnd ;
10218#elif defined(__LITTLE_ENDIAN)
10219 uint16_t recent_seg_wnd ;
10220 uint16_t second_isle_address ;
10222#if defined(__BIG_ENDIAN)
10223 uint8_t max_isles_ever_happened ;
10224 uint8_t isles_number ;
10225 uint16_t last_isle_address ;
10226#elif defined(__LITTLE_ENDIAN)
10227 uint16_t last_isle_address ;
10228 uint8_t isles_number ;
10229 uint8_t max_isles_ever_happened ;
10232#if defined(__BIG_ENDIAN)
10233 uint16_t lsb_mac_address ;
10235#elif defined(__LITTLE_ENDIAN)
10237 uint16_t lsb_mac_address ;
10239#if defined(__BIG_ENDIAN)
10240 uint16_t msb_mac_address ;
10241 uint16_t mid_mac_address ;
10242#elif defined(__LITTLE_ENDIAN)
10243 uint16_t mid_mac_address ;
10244 uint16_t msb_mac_address ;
10255 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0)
10256 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
10257 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
10258 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
10259 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
10260 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
10261 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6)
10262 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6
10263 #define ISCSI_TERM_VARS_RSRV (0x1<<7)
10264 #define ISCSI_TERM_VARS_RSRV_SHIFT 7
10274#if defined(__BIG_ENDIAN)
10277 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
10278 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
10279 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
10280 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
10281 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
10282 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
10283 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
10284 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
10285 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
10286 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
10287 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
10288 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
10289 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
10290 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
10291 uint8_t hdr_bytes_2_fetch ;
10292#elif defined(__LITTLE_ENDIAN)
10293 uint8_t hdr_bytes_2_fetch ;
10295 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
10296 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
10297 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
10298 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
10299 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
10300 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
10301 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
10302 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
10303 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
10304 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
10305 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
10306 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
10307 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
10308 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
10312#if defined(__BIG_ENDIAN)
10315 uint16_t iscsi_conn_id;
10316#elif defined(__LITTLE_ENDIAN)
10317 uint16_t iscsi_conn_id;
10338#if defined(__BIG_ENDIAN)
10339 uint8_t remote_addr_4 ;
10340 uint8_t remote_addr_5 ;
10341 uint8_t local_addr_0 ;
10342 uint8_t local_addr_1 ;
10343#elif defined(__LITTLE_ENDIAN)
10344 uint8_t local_addr_1 ;
10345 uint8_t local_addr_0 ;
10346 uint8_t remote_addr_5 ;
10347 uint8_t remote_addr_4 ;
10349#if defined(__BIG_ENDIAN)
10350 uint8_t remote_addr_0 ;
10351 uint8_t remote_addr_1 ;
10352 uint8_t remote_addr_2 ;
10353 uint8_t remote_addr_3 ;
10354#elif defined(__LITTLE_ENDIAN)
10355 uint8_t remote_addr_3 ;
10356 uint8_t remote_addr_2 ;
10357 uint8_t remote_addr_1 ;
10358 uint8_t remote_addr_0 ;
10360#if defined(__BIG_ENDIAN)
10361 uint16_t reserved_vlan_type ;
10362 uint16_t vlan_params;
10363 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
10364 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
10365 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
10366 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
10367 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
10368 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
10369#elif defined(__LITTLE_ENDIAN)
10370 uint16_t vlan_params;
10371 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
10372 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
10373 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
10374 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
10375 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
10376 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
10377 uint16_t reserved_vlan_type ;
10379#if defined(__BIG_ENDIAN)
10380 uint8_t local_addr_2 ;
10381 uint8_t local_addr_3 ;
10382 uint8_t local_addr_4 ;
10383 uint8_t local_addr_5 ;
10384#elif defined(__LITTLE_ENDIAN)
10385 uint8_t local_addr_5 ;
10386 uint8_t local_addr_4 ;
10387 uint8_t local_addr_3 ;
10388 uint8_t local_addr_2 ;
10397#if defined(__BIG_ENDIAN)
10398 uint16_t __pbf_hdr_cmd_rsvd_id;
10399 uint16_t __pbf_hdr_cmd_rsvd_flags_offset;
10400#elif defined(__LITTLE_ENDIAN)
10401 uint16_t __pbf_hdr_cmd_rsvd_flags_offset;
10402 uint16_t __pbf_hdr_cmd_rsvd_id;
10404#if defined(__BIG_ENDIAN)
10405 uint8_t __pbf_hdr_cmd_rsvd_ver_ihl;
10407 uint16_t __pbf_hdr_cmd_rsvd_length;
10408#elif defined(__LITTLE_ENDIAN)
10409 uint16_t __pbf_hdr_cmd_rsvd_length;
10411 uint8_t __pbf_hdr_cmd_rsvd_ver_ihl;
10414#if defined(__BIG_ENDIAN)
10416 uint8_t __pbf_hdr_cmd_rsvd_protocol;
10417 uint16_t __pbf_hdr_cmd_rsvd_csum;
10418#elif defined(__LITTLE_ENDIAN)
10419 uint16_t __pbf_hdr_cmd_rsvd_csum;
10420 uint8_t __pbf_hdr_cmd_rsvd_protocol;
10441#if defined(__BIG_ENDIAN)
10442 uint16_t pbf_hdr_cmd_rsvd_payload_len;
10443 uint8_t pbf_hdr_cmd_rsvd_nxt_hdr;
10444 uint8_t hop_limit ;
10445#elif defined(__LITTLE_ENDIAN)
10446 uint8_t hop_limit ;
10447 uint8_t pbf_hdr_cmd_rsvd_nxt_hdr;
10448 uint16_t pbf_hdr_cmd_rsvd_payload_len;
10451 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0)
10452 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
10453 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20)
10454 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20
10455 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28)
10456 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28
10479#if defined(__BIG_ENDIAN)
10480 uint16_t remote_port ;
10481 uint16_t local_port ;
10482#elif defined(__LITTLE_ENDIAN)
10483 uint16_t local_port ;
10484 uint16_t remote_port ;
10486#if defined(__BIG_ENDIAN)
10487 uint8_t original_nagle_1b;
10488 uint8_t ts_enabled ;
10489 uint16_t tcp_params;
10490 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
10491 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
10492 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
10493 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
10494 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
10495 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
10496 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
10497 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
10498 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
10499 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
10500 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
10501 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
10502 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
10503 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
10504 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
10505 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
10506#elif defined(__LITTLE_ENDIAN)
10507 uint16_t tcp_params;
10508 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
10509 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
10510 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
10511 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
10512 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
10513 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
10514 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
10515 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
10516 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
10517 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
10518 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
10519 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
10520 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
10521 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
10522 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
10523 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
10524 uint8_t ts_enabled ;
10525 uint8_t original_nagle_1b;
10527#if defined(__BIG_ENDIAN)
10528 uint16_t pseudo_csum ;
10529 uint16_t window_scaling_factor ;
10530#elif defined(__LITTLE_ENDIAN)
10531 uint16_t window_scaling_factor ;
10532 uint16_t pseudo_csum ;
10534#if defined(__BIG_ENDIAN)
10535 uint16_t reserved2 ;
10536 uint8_t statistics_counter_id ;
10537 uint8_t statistics_params;
10538 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
10539 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
10540 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
10541 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
10542 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
10543 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
10544#elif defined(__LITTLE_ENDIAN)
10545 uint8_t statistics_params;
10546 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
10547 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
10548 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
10549 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
10550 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
10551 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
10552 uint8_t statistics_counter_id ;
10553 uint16_t reserved2 ;
10567#if defined(__BIG_ENDIAN)
10570 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
10571 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
10572 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
10573 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
10574 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
10575 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
10576 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
10577 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
10578 uint8_t outer_tag_flags;
10579 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0)
10580 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
10581 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3)
10582 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3
10583 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6)
10584 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6
10585 uint8_t ip_version_1b;
10586#elif defined(__LITTLE_ENDIAN)
10587 uint8_t ip_version_1b;
10588 uint8_t outer_tag_flags;
10589 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0)
10590 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
10591 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3)
10592 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3
10593 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6)
10594 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6
10596 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
10597 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
10598 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
10599 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
10600 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
10601 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
10602 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
10603 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
10614 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0)
10615 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
10616 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1)
10617 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1
10618 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2)
10619 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2
10620 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3)
10621 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3
10622 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4)
10623 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4
10624 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5)
10625 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5
10626 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6)
10627 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6
10628 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7)
10629 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7
10648#if defined(__BIG_ENDIAN)
10651 uint16_t sge_offset;
10652#elif defined(__LITTLE_ENDIAN)
10653 uint16_t sge_offset;
10673#if defined(__BIG_ENDIAN)
10674 uint16_t data_out_count;
10676 uint8_t task_pbl_cache_idx ;
10677#elif defined(__LITTLE_ENDIAN)
10678 uint8_t task_pbl_cache_idx ;
10680 uint16_t data_out_count;
10691#if defined(__BIG_ENDIAN)
10692 uint16_t rxmit_sge_offset;
10693 uint16_t hq_rxmit_cons;
10694#elif defined(__LITTLE_ENDIAN)
10695 uint16_t hq_rxmit_cons;
10696 uint16_t rxmit_sge_offset;
10698#if defined(__BIG_ENDIAN)
10699 uint16_t r2tq_cons;
10700 uint8_t rxmit_flags;
10701 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
10702 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
10703 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
10704 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
10705 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
10706 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
10707 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
10708 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
10709 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
10710 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
10711 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
10712 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
10713 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
10714 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
10715 uint8_t rxmit_sge_idx;
10716#elif defined(__LITTLE_ENDIAN)
10717 uint8_t rxmit_sge_idx;
10718 uint8_t rxmit_flags;
10719 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
10720 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
10721 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
10722 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
10723 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
10724 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
10725 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
10726 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
10727 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
10728 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
10729 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
10730 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
10731 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
10732 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
10733 uint16_t r2tq_cons;
10771#if defined(__BIG_ENDIAN)
10774 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
10775 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10776 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
10777 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
10779#elif defined(__LITTLE_ENDIAN)
10782 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
10783 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10784 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
10785 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
10789 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
10790 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10791 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
10792 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10810#if defined(__BIG_ENDIAN)
10813 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
10814 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
10815 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
10816 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
10817 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
10818 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
10819 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
10820 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10821 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
10822 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
10823 uint8_t version_max;
10824 uint8_t version_min;
10825#elif defined(__LITTLE_ENDIAN)
10826 uint8_t version_min;
10827 uint8_t version_max;
10829 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
10830 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
10831 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
10832 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
10833 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
10834 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
10835 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
10836 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10837 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
10838 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
10842 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
10843 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10844 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
10845 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10847#if defined(__BIG_ENDIAN)
10850#elif defined(__LITTLE_ENDIAN)
10855#if defined(__BIG_ENDIAN)
10858#elif defined(__LITTLE_ENDIAN)
10872#if defined(__BIG_ENDIAN)
10875 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
10876 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
10877 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
10878 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10880#elif defined(__LITTLE_ENDIAN)
10883 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
10884 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
10885 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
10886 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10890 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
10891 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10892 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
10893 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10896#if defined(__BIG_ENDIAN)
10899#elif defined(__LITTLE_ENDIAN)
10913#if defined(__BIG_ENDIAN)
10916 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
10917 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
10918 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
10919 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10921#elif defined(__LITTLE_ENDIAN)
10924 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
10925 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
10926 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
10927 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10931 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
10932 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10933 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
10934 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10950#if defined(__BIG_ENDIAN)
10953 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
10954 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10955 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
10956 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10957 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
10958 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
10960#elif defined(__LITTLE_ENDIAN)
10963 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
10964 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10965 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
10966 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10967 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
10968 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
10972 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
10973 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10974 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
10975 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10989#if defined(__BIG_ENDIAN)
10992 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
10993 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10994 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
10995 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
10997#elif defined(__LITTLE_ENDIAN)
11000 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
11001 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
11002 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
11003 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
11007 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
11008 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
11009 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
11010 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
11037#if defined(__BIG_ENDIAN)
11038 uint16_t reserved1;
11039 uint16_t lcl_cmp_flg;
11040#elif defined(__LITTLE_ENDIAN)
11041 uint16_t lcl_cmp_flg;
11042 uint16_t reserved1;
11046#if defined(__BIG_ENDIAN)
11049 uint16_t sge_offset;
11050#elif defined(__LITTLE_ENDIAN)
11051 uint16_t sge_offset;
11087#if defined(__BIG_ENDIAN)
11088 uint16_t data_in_count ;
11091#elif defined(__LITTLE_ENDIAN)
11094 uint16_t data_in_count ;
11119#if defined(__BIG_ENDIAN)
11120 uint16_t data_out_count;
11122#elif defined(__LITTLE_ENDIAN)
11124 uint16_t data_out_count;
11179 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
11180 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
11181 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
11182 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
11183 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
11184 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
11185 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
11186 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
11187 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
11188 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
11218#if defined(__BIG_ENDIAN)
11219 uint16_t __reserved1;
11220 uint8_t __reserved0;
11221 uint8_t safc_timeout_usec ;
11222#elif defined(__LITTLE_ENDIAN)
11223 uint8_t safc_timeout_usec ;
11224 uint8_t __reserved0;
11225 uint16_t __reserved1;
11248#if defined(__BIG_ENDIAN)
11249 uint16_t __reserved0;
11251#elif defined(__LITTLE_ENDIAN)
11253 uint16_t __reserved0;
11403#if defined(__BIG_ENDIAN)
11404 uint16_t reserved1;
11407#elif defined(__LITTLE_ENDIAN)
11410 uint16_t reserved1;
11449#if defined(__BIG_ENDIAN)
11451 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
11452 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
11453 #define E2_INTEG_DATA_LB_TX (0x1<<1)
11454 #define E2_INTEG_DATA_LB_TX_SHIFT 1
11455 #define E2_INTEG_DATA_COS_TX (0x1<<2)
11456 #define E2_INTEG_DATA_COS_TX_SHIFT 2
11457 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
11458 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
11459 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
11460 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
11461 #define E2_INTEG_DATA_RESERVED (0x7<<5)
11462 #define E2_INTEG_DATA_RESERVED_SHIFT 5
11465 uint8_t pbf_queue ;
11466#elif defined(__LITTLE_ENDIAN)
11467 uint8_t pbf_queue ;
11471 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
11472 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
11473 #define E2_INTEG_DATA_LB_TX (0x1<<1)
11474 #define E2_INTEG_DATA_LB_TX_SHIFT 1
11475 #define E2_INTEG_DATA_COS_TX (0x1<<2)
11476 #define E2_INTEG_DATA_COS_TX_SHIFT 2
11477 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
11478 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
11479 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
11480 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
11481 #define E2_INTEG_DATA_RESERVED (0x7<<5)
11482 #define E2_INTEG_DATA_RESERVED_SHIFT 5
11484#if defined(__BIG_ENDIAN)
11485 uint16_t reserved3;
11488#elif defined(__LITTLE_ENDIAN)
11491 uint16_t reserved3;
11588#if defined(__BIG_ENDIAN)
11591 uint16_t producer ;
11592#elif defined(__LITTLE_ENDIAN)
11593 uint16_t producer ;
11770#if defined(__BIG_ENDIAN)
11771 uint8_t engineering ;
11775#elif defined(__LITTLE_ENDIAN)
11779 uint8_t engineering ;
11782 #define FW_VERSION_OPTIMIZED (0x1<<0)
11783 #define FW_VERSION_OPTIMIZED_SHIFT 0
11784 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
11785 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
11786 #define FW_VERSION_CHIP_VERSION (0x3<<2)
11787 #define FW_VERSION_CHIP_VERSION_SHIFT 2
11788 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
11789 #define __FW_VERSION_RESERVED_SHIFT 4
11807#if defined(__BIG_ENDIAN)
11809 #define HC_INDEX_DATA_SM_ID (0x1<<0)
11810 #define HC_INDEX_DATA_SM_ID_SHIFT 0
11811 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
11812 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
11813 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
11814 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
11815 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
11816 #define HC_INDEX_DATA_RESERVE_SHIFT 3
11818#elif defined(__LITTLE_ENDIAN)
11821 #define HC_INDEX_DATA_SM_ID (0x1<<0)
11822 #define HC_INDEX_DATA_SM_ID_SHIFT 0
11823 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
11824 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
11825 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
11826 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
11827 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
11828 #define HC_INDEX_DATA_RESERVE_SHIFT 3
11838#if defined(__BIG_ENDIAN)
11839 uint8_t igu_seg_id;
11840 uint8_t igu_sb_id ;
11841 uint8_t timer_value ;
11843#elif defined(__LITTLE_ENDIAN)
11845 uint8_t timer_value ;
11846 uint8_t igu_sb_id ;
11847 uint8_t igu_seg_id;
11857#if defined(__BIG_ENDIAN)
11862#elif defined(__LITTLE_ENDIAN)
11878#if defined(__BIG_ENDIAN)
11881 uint8_t dhc_qzone_id ;
11882 uint8_t same_igu_sb_1b ;
11883#elif defined(__LITTLE_ENDIAN)
11884 uint8_t same_igu_sb_1b ;
11885 uint8_t dhc_qzone_id ;
11909#if defined(__BIG_ENDIAN)
11912 uint8_t igu_seg_id ;
11913 uint8_t igu_sb_id ;
11914#elif defined(__LITTLE_ENDIAN)
11915 uint8_t igu_sb_id ;
11916 uint8_t igu_seg_id ;
12120 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
12121 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
12122 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
12123 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
12124 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
12125 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
12126 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
12127 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
12128 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
12129 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
12336#if defined(__BIG_ENDIAN)
12340 uint8_t read_size ;
12341#elif defined(__LITTLE_ENDIAN)
12342 uint8_t read_size ;
12347#if defined(__BIG_ENDIAN)
12348 uint16_t num_meas ;
12350 uint8_t period_10us ;
12351#elif defined(__LITTLE_ENDIAN)
12352 uint8_t period_10us ;
12354 uint16_t num_meas ;
12364#if defined(__BIG_ENDIAN)
12365 uint16_t max_time_ns ;
12366 uint16_t min_time_ns ;
12367#elif defined(__LITTLE_ENDIAN)
12368 uint16_t min_time_ns ;
12369 uint16_t max_time_ns ;
12371#if defined(__BIG_ENDIAN)
12373 uint16_t num_reads ;
12374#elif defined(__LITTLE_ENDIAN)
12375 uint16_t num_reads ;
12406#if defined(__BIG_ENDIAN)
12407 uint16_t reserved0;
12410#elif defined(__LITTLE_ENDIAN)
12413 uint16_t reserved0;
12503#if defined(__BIG_ENDIAN)
12504 uint16_t __rss_params_ram_line ;
12506#elif defined(__LITTLE_ENDIAN)
12508 uint16_t __rss_params_ram_line ;
12531#if defined(__BIG_ENDIAN)
12532 uint8_t __reserved1 ;
12533 uint8_t __isle_num ;
12534 uint16_t __buf_un_used ;
12535#elif defined(__LITTLE_ENDIAN)
12536 uint16_t __buf_un_used ;
12537 uint8_t __isle_num ;
12538 uint8_t __reserved1 ;
12549#if defined(__BIG_ENDIAN)
12550 uint8_t __rq_local_cons ;
12551 uint8_t __rq_local_prod ;
12553#elif defined(__LITTLE_ENDIAN)
12555 uint8_t __rq_local_prod ;
12556 uint8_t __rq_local_cons ;
12567#if defined(__BIG_ENDIAN)
12569 #define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0)
12570 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
12571 #define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1)
12572 #define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1
12573 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2)
12574 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2
12575 #define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3)
12576 #define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3
12577 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4)
12578 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4
12579 uint16_t __buf_un_used ;
12580#elif defined(__LITTLE_ENDIAN)
12581 uint16_t __buf_un_used ;
12583 #define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0)
12584 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
12585 #define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1)
12586 #define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1
12587 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2)
12588 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2
12589 #define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3)
12590 #define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3
12591 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4)
12592 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4
12603#if defined(__BIG_ENDIAN)
12605 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0)
12606 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
12607 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1)
12608 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1
12609 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2)
12610 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2
12611 #define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3)
12612 #define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3
12613 uint8_t __indirection_shift ;
12614 uint16_t indirection_ram_offset ;
12615#elif defined(__LITTLE_ENDIAN)
12616 uint16_t indirection_ram_offset ;
12617 uint8_t __indirection_shift ;
12619 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0)
12620 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
12621 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1)
12622 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1
12623 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2)
12624 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2
12625 #define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3)
12626 #define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3
12629#if defined(__BIG_ENDIAN)
12630 uint8_t isles_counter ;
12631 uint8_t __push_timer_state ;
12632 uint16_t rcv_indication_size ;
12633#elif defined(__LITTLE_ENDIAN)
12634 uint16_t rcv_indication_size ;
12635 uint8_t __push_timer_state ;
12636 uint8_t isles_counter ;
12700#if defined(__BIG_ENDIAN)
12701 uint16_t tx_bd_offset ;
12702 uint16_t tx_bd_cons ;
12703#elif defined(__LITTLE_ENDIAN)
12704 uint16_t tx_bd_cons ;
12705 uint16_t tx_bd_offset ;
12707#if defined(__BIG_ENDIAN)
12709 uint16_t seqMismatchCnt;
12710#elif defined(__LITTLE_ENDIAN)
12711 uint16_t seqMismatchCnt;
12758 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED (0x1<<0)
12759 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED_SHIFT 0
12760 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE (0x1<<1)
12761 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE_SHIFT 1
12762 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0 (0x3FFFFFFF<<2)
12763 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 2
12773#if defined(__BIG_ENDIAN)
12774 uint16_t reserved1;
12777#elif defined(__LITTLE_ENDIAN)
12780 uint16_t reserved1;
12824#if defined(__BIG_ENDIAN)
12825 uint16_t reserved0;
12826 uint16_t toe_rss_bitmap ;
12827#elif defined(__LITTLE_ENDIAN)
12828 uint16_t toe_rss_bitmap ;
12829 uint16_t reserved0;
12842#if defined(__BIG_ENDIAN)
12844 #define TOE_RX_BD_START (0x1<<0)
12845 #define TOE_RX_BD_START_SHIFT 0
12846 #define TOE_RX_BD_END (0x1<<1)
12847 #define TOE_RX_BD_END_SHIFT 1
12848 #define TOE_RX_BD_NO_PUSH (0x1<<2)
12849 #define TOE_RX_BD_NO_PUSH_SHIFT 2
12850 #define TOE_RX_BD_SPLIT (0x1<<3)
12851 #define TOE_RX_BD_SPLIT_SHIFT 3
12852 #define TOE_RX_BD_RESERVED1 (0xFFF<<4)
12853 #define TOE_RX_BD_RESERVED1_SHIFT 4
12855#elif defined(__LITTLE_ENDIAN)
12858 #define TOE_RX_BD_START (0x1<<0)
12859 #define TOE_RX_BD_START_SHIFT 0
12860 #define TOE_RX_BD_END (0x1<<1)
12861 #define TOE_RX_BD_END_SHIFT 1
12862 #define TOE_RX_BD_NO_PUSH (0x1<<2)
12863 #define TOE_RX_BD_NO_PUSH_SHIFT 2
12864 #define TOE_RX_BD_SPLIT (0x1<<3)
12865 #define TOE_RX_BD_SPLIT_SHIFT 3
12866 #define TOE_RX_BD_RESERVED1 (0xFFF<<4)
12867 #define TOE_RX_BD_RESERVED1_SHIFT 4
12878#if defined(__BIG_ENDIAN)
12879 uint16_t reserved0;
12880 uint16_t hash_value ;
12881#elif defined(__LITTLE_ENDIAN)
12882 uint16_t hash_value ;
12883 uint16_t reserved0;
12895 #define TOE_RX_CQE_OOO_PARAMS_NBYTES (0xFFFFFF<<0)
12896 #define TOE_RX_CQE_OOO_PARAMS_NBYTES_SHIFT 0
12897 #define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM (0xFF<<24)
12898 #define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM_SHIFT 24
12907 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES (0xFFFFFFFF<<0)
12908 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES_SHIFT 0
12927 #define TOE_RX_CQE_CID (0xFFFFFF<<0)
12928 #define TOE_RX_CQE_CID_SHIFT 0
12929 #define TOE_RX_CQE_COMPLETION_OPCODE (0xFF<<24)
12930 #define TOE_RX_CQE_COMPLETION_OPCODE_SHIFT 24
12942#if defined(__BIG_ENDIAN)
12943 uint8_t reserved1 ;
12945 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0)
12946 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
12947 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1)
12948 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1
12949 #define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2)
12950 #define TOE_RX_DB_DATA_RESERVED0_SHIFT 2
12951 uint16_t bds_prod ;
12952#elif defined(__LITTLE_ENDIAN)
12953 uint16_t bds_prod ;
12955 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0)
12956 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
12957 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1)
12958 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1
12959 #define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2)
12960 #define TOE_RX_DB_DATA_RESERVED0_SHIFT 2
12961 uint8_t reserved1 ;
13105#if defined(__BIG_ENDIAN)
13107 #define TOE_TX_BD_PUSH (0x1<<0)
13108 #define TOE_TX_BD_PUSH_SHIFT 0
13109 #define TOE_TX_BD_NOTIFY (0x1<<1)
13110 #define TOE_TX_BD_NOTIFY_SHIFT 1
13111 #define TOE_TX_BD_FIN (0x1<<2)
13112 #define TOE_TX_BD_FIN_SHIFT 2
13113 #define TOE_TX_BD_LARGE_IO (0x1<<3)
13114 #define TOE_TX_BD_LARGE_IO_SHIFT 3
13115 #define TOE_TX_BD_RESERVED1 (0xFFF<<4)
13116 #define TOE_TX_BD_RESERVED1_SHIFT 4
13118#elif defined(__LITTLE_ENDIAN)
13121 #define TOE_TX_BD_PUSH (0x1<<0)
13122 #define TOE_TX_BD_PUSH_SHIFT 0
13123 #define TOE_TX_BD_NOTIFY (0x1<<1)
13124 #define TOE_TX_BD_NOTIFY_SHIFT 1
13125 #define TOE_TX_BD_FIN (0x1<<2)
13126 #define TOE_TX_BD_FIN_SHIFT 2
13127 #define TOE_TX_BD_LARGE_IO (0x1<<3)
13128 #define TOE_TX_BD_LARGE_IO_SHIFT 3
13129 #define TOE_TX_BD_RESERVED1 (0xFFF<<4)
13130 #define TOE_TX_BD_RESERVED1_SHIFT 4
13142 #define TOE_TX_CQE_CID (0xFFFFFF<<0)
13143 #define TOE_TX_CQE_CID_SHIFT 0
13144 #define TOE_TX_CQE_COMPLETION_OPCODE (0xFF<<24)
13145 #define TOE_TX_CQE_COMPLETION_OPCODE_SHIFT 24
13156#if defined(__BIG_ENDIAN)
13158 #define TOE_TX_DB_DATA_FIN (0x1<<0)
13159 #define TOE_TX_DB_DATA_FIN_SHIFT 0
13160 #define TOE_TX_DB_DATA_FLUSH (0x1<<1)
13161 #define TOE_TX_DB_DATA_FLUSH_SHIFT 1
13162 #define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2)
13163 #define TOE_TX_DB_DATA_RESERVE_SHIFT 2
13164 uint16_t bds_prod ;
13165#elif defined(__LITTLE_ENDIAN)
13166 uint16_t bds_prod ;
13168 #define TOE_TX_DB_DATA_FIN (0x1<<0)
13169 #define TOE_TX_DB_DATA_FIN_SHIFT 0
13170 #define TOE_TX_DB_DATA_FLUSH (0x1<<1)
13171 #define TOE_TX_DB_DATA_FLUSH_SHIFT 1
13172 #define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2)
13173 #define TOE_TX_DB_DATA_RESERVE_SHIFT 2
13184 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED (0x1<<0)
13185 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED_SHIFT 0
13186 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED (0x1<<1)
13187 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED_SHIFT 1
13188 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED (0x1<<2)
13189 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 2
13190 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED (0x1<<3)
13191 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED_SHIFT 3
13192 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED (0x1<<4)
13193 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED_SHIFT 4
13194 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED (0x1<<5)
13195 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 5
13196 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED (0x1<<6)
13197 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED_SHIFT 6
13198 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED (0x1<<7)
13199 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED_SHIFT 7
13200 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED (0x1<<8)
13201 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED_SHIFT 8
13202 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED (0x1<<9)
13203 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED_SHIFT 9
13204 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED (0x1<<10)
13205 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED_SHIFT 10
13206 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED (0x1<<11)
13207 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED_SHIFT 11
13208 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED (0x1<<12)
13209 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED_SHIFT 12
13210 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED (0x1<<13)
13211 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED_SHIFT 13
13212 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED (0x1<<14)
13213 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED_SHIFT 14
13214 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED (0x1<<15)
13215 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 15
13244#if defined(__BIG_ENDIAN)
13245 uint16_t grq_thr_low ;
13246 uint16_t cq_thr_low ;
13247#elif defined(__LITTLE_ENDIAN)
13248 uint16_t cq_thr_low ;
13249 uint16_t grq_thr_low ;
13251#if defined(__BIG_ENDIAN)
13252 uint16_t grq_thr_high ;
13253 uint16_t cq_thr_high ;
13254#elif defined(__LITTLE_ENDIAN)
13255 uint16_t cq_thr_high ;
13256 uint16_t grq_thr_high ;
#define HC_SB_MAX_DYNAMIC_INDICES
#define MULTICAST_RULES_COUNT
#define CLASSIFY_RULES_COUNT
#define T_ETH_INDIRECTION_TABLE_SIZE
#define STATS_QUERY_CMD_COUNT
#define HC_SB_MAX_INDICES_E1X
#define MAX_TRAFFIC_TYPES
#define FILTER_RULES_COUNT
#define MAX_VLAN_PRIORITIES
#define HC_SB_MAX_INDICES_E2
#define HC_SP_SB_MAX_INDICES
@ MAX_TOE_RSS_UPDATE_OPCODE
#define REM_PORT_ID_STAT_LEN
@ TPA_UPDATE_ENABLE_COMMAND
@ TPA_UPDATE_DISABLE_COMMAND
@ TPA_UPDATE_NONE_COMMAND
@ MAX_ETH_TPA_UPDATE_COMMAND
@ RAMROD_CMD_ID_COMMON_STAT_QUERY
@ RAMROD_CMD_ID_COMMON_UNUSED
@ RAMROD_CMD_ID_COMMON_STOP_TRAFFIC
@ RAMROD_CMD_ID_COMMON_FUNCTION_STOP
@ RAMROD_CMD_ID_COMMON_CFC_DEL_WB
@ RAMROD_CMD_ID_COMMON_SET_TIMESYNC
@ RAMROD_CMD_ID_COMMON_CFC_DEL
@ RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE
@ RAMROD_CMD_ID_COMMON_FUNCTION_START
@ RAMROD_CMD_ID_COMMON_START_TRAFFIC
@ RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS
#define SHMEM_LINK_CONFIG_SIZE
@ VIF_LIST_RULE_CLEAR_FUNC
@ VIF_LIST_RULE_CLEAR_ALL
@ MAX_VF_PF_CHANNEL_STATE
@ VF_PF_CHANNEL_STATE_WAITING_FOR_ACK
@ VF_PF_CHANNEL_STATE_READY
@ RAMROD_CMD_ID_ETH_CLIENT_SETUP
@ RAMROD_CMD_ID_ETH_FILTER_RULES
@ RAMROD_CMD_ID_ETH_UNUSED
@ RAMROD_CMD_ID_ETH_CLIENT_UPDATE
@ RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
@ RAMROD_CMD_ID_ETH_MULTICAST_RULES
@ RAMROD_CMD_ID_ETH_EMPTY
@ RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
@ RAMROD_CMD_ID_ETH_FORWARD_SETUP
@ RAMROD_CMD_ID_ETH_SET_MAC
@ RAMROD_CMD_ID_ETH_TERMINATE
@ RAMROD_CMD_ID_ETH_TPA_UPDATE
@ RAMROD_CMD_ID_ETH_RSS_UPDATE
#define FC_NPIV_WWNN_SIZE
@ PRS_FLAG_OVERIP_UNKNOWN
@ CURR_CFG_MET_VENDOR_SPEC
@ T_ETH_MAC_COMMAND_INVALIDATE
@ MAX_SET_MAC_ACTION_TYPE
@ MAX_TS_DRIFT_ADJUST_CMD
@ MAX_ETH_VLAN_FILTER_MODE
@ ETH_VLAN_FILTER_SPECIFIC_VLAN
@ ETH_VLAN_FILTER_CLASSIFY
@ ETH_VLAN_FILTER_ANY_VLAN
#define OEM_I2C_UUID_STR_LEN
#define DCBX_MAX_APP_PROTOCOL
@ PRS_FLAG_OVERETH_UNKNOWN
@ PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN
@ EVENT_RING_OPCODE_START_TRAFFIC
@ EVENT_RING_OPCODE_FUNCTION_START
@ EVENT_RING_OPCODE_VF_PF_CHANNEL
@ EVENT_RING_OPCODE_CFC_DEL
@ EVENT_RING_OPCODE_SET_MAC
@ EVENT_RING_OPCODE_FILTERS_RULES
@ EVENT_RING_OPCODE_FUNCTION_STOP
@ EVENT_RING_OPCODE_CFC_DEL_WB
@ EVENT_RING_OPCODE_MULTICAST_RULES
@ EVENT_RING_OPCODE_RSS_UPDATE_RULES
@ EVENT_RING_OPCODE_FUNCTION_UPDATE
@ EVENT_RING_OPCODE_STAT_QUERY
@ EVENT_RING_OPCODE_MALICIOUS_VF
@ EVENT_RING_OPCODE_CLASSIFICATION_RULES
@ EVENT_RING_OPCODE_FORWARD_SETUP
@ EVENT_RING_OPCODE_AFEX_VIF_LISTS
@ EVENT_RING_OPCODE_SET_TIMESYNC
@ EVENT_RING_OPCODE_STOP_TRAFFIC
@ EVENT_RING_OPCODE_VF_FLR
@ LLFC_TRAFFIC_TYPE_ISCSI
@ MAX_MALICIOUS_VF_ERROR_ID
@ ETH_TUNNEL_NOT_SUPPORTED
@ ETH_ILLEGAL_LSO_HDR_LEN
@ VF_PF_CHANNEL_NOT_READY
@ MAX_ETH_2ND_PARSE_BD_TYPE
@ ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL
@ RAMROD_OPCODE_TOE_QUERY
@ RAMROD_OPCODE_TOE_EMPTY_RAMROD
@ RAMROD_OPCODE_TOE_TERMINATE_RING
@ RAMROD_OPCODE_TOE_INVALIDATE
@ RAMROD_OPCODE_TOE_TERMINATE
@ RAMROD_OPCODE_TOE_RSS_UPDATE
@ RAMROD_OPCODE_TOE_RESET_SEND
@ RAMROD_OPCODE_TOE_INITIATE_OFFLOAD
@ RAMROD_OPCODE_TOE_SEARCHER_DELETE
@ RAMROD_OPCODE_TOE_UPDATE
@ PRS_FLAG_ETHTYPE_UNICAST
@ PRS_FLAG_ETHTYPE_NON_UNICAST
@ MAX_PRS_FLAGS_ETH_ADDR_TYPE
#define OEM_I2C_CARD_SKU_STR_LEN
#define OEM_I2C_CARD_VERSION_STR_LEN
@ FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
@ FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE
@ FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE
@ RX_ETH_CQE_TYPE_ETH_FASTPATH
@ RX_ETH_CQE_TYPE_ETH_START_AGG
@ RX_ETH_CQE_TYPE_ETH_STOP_AGG
@ RX_ETH_CQE_TYPE_ETH_RAMROD
@ CLASSIFY_RULE_OPCODE_PAIR
@ CLASSIFY_RULE_OPCODE_VLAN
@ CLASSIFY_RULE_OPCODE_MAC
@ CLASSIFY_RULE_OPCODE_IMAC_VNI
#define REM_CHASSIS_ID_STAT_LEN
eth_tunnel_non_lso_csum_location
@ MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
@ RESERVED_CONNECTION_TYPE_1
@ RESERVED_CONNECTION_TYPE_2
@ RESERVED_CONNECTION_TYPE_0
#define OEM_I2C_CARD_NAME_STR_LEN
@ MAX_ETH_TUNNEL_LSO_INC_IP_ID
#define MGMTFW_STATE_WORD_SIZE
#define FC_NPIV_WWPN_SIZE
@ TCP_TSTORM_OOO_SUPPORTED
@ TCP_TSTORM_OOO_SEND_PURE_ACK
@ TCP_TSTORM_OOO_DROP_AND_PROC_ACK
@ MAX_CLASSIFY_RULE_ACTION_TYPE
#define LOCAL_CHASSIS_ID_STAT_LEN
#define LOCAL_PORT_ID_STAT_LEN
#define OEM_I2C_CARD_FN_STR_LEN
@ TCP_EVENT_ADD_ISLE_LEFT
@ TCP_EVENT_ADD_ISLE_RIGHT
uint32_t tx_multicast_bytes_lo
uint32_t rx_frames_discarded_lo
uint32_t tx_unicast_bytes_lo
uint32_t rx_multicast_bytes_hi
uint32_t rx_multicast_frames_hi
uint32_t rx_broadcast_frames_lo
uint32_t tx_unicast_bytes_hi
uint32_t tx_multicast_frames_hi
uint32_t rx_unicast_bytes_lo
uint32_t tx_frames_dropped_lo
uint32_t tx_multicast_frames_lo
uint32_t rx_broadcast_frames_hi
uint32_t rx_unicast_frames_hi
uint32_t rx_multicast_frames_lo
uint32_t tx_frames_dropped_hi
uint32_t rx_broadcast_bytes_lo
uint32_t rx_multicast_bytes_lo
uint32_t rx_frames_dropped_hi
uint32_t rx_frames_discarded_hi
uint32_t tx_broadcast_bytes_hi
uint32_t tx_frames_discarded_hi
uint32_t tx_broadcast_frames_lo
uint32_t rx_broadcast_bytes_hi
uint32_t tx_unicast_frames_hi
uint32_t tx_unicast_frames_lo
uint32_t rx_frames_dropped_lo
uint32_t rx_unicast_bytes_hi
uint32_t tx_broadcast_bytes_lo
uint32_t tx_frames_discarded_lo
uint32_t rx_unicast_frames_lo
uint32_t tx_broadcast_frames_hi
uint32_t tx_multicast_bytes_hi
uint8_t afex_vif_list_command
struct bdn_npiv_settings settings[MAX_NUMBER_NPIV]
struct bdn_fc_npiv_cfg fc_npiv_cfg
uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE]
uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE]
uint32_t tx_stat_gtxpf_lo
uint32_t tx_stat_gt1518_lo
uint32_t tx_stat_gt4095_hi
uint32_t tx_stat_gtpkt_lo
uint32_t rx_stat_gr255_lo
uint32_t rx_stat_grmeg_lo
uint32_t rx_stat_grund_lo
uint32_t rx_stat_grbca_hi
uint32_t tx_stat_gtbyt_hi
uint32_t rx_stat_gr511_lo
uint32_t tx_stat_gt511_lo
uint32_t tx_stat_gt1023_lo
uint32_t rx_stat_grflr_hi
uint32_t tx_stat_gtovr_lo
uint32_t rx_stat_gr511_hi
uint32_t tx_stat_gterr_hi
uint32_t rx_stat_grpkt_hi
uint32_t tx_stat_gtmca_hi
uint32_t rx_stat_grerb_hi
uint32_t rx_stat_grjbr_hi
uint32_t rx_stat_grmeb_lo
uint32_t tx_stat_gtxpf_hi
uint32_t rx_stat_grxuo_lo
uint32_t tx_stat_gt1518_hi
uint32_t tx_stat_gtpkt_hi
uint32_t tx_stat_gt9216_hi
uint32_t tx_stat_gt2047_lo
uint32_t rx_stat_grjbr_lo
uint32_t rx_stat_grfre_hi
uint32_t tx_stat_gtufl_lo
uint32_t rx_stat_gr1023_hi
uint32_t tx_stat_gtovr_hi
uint32_t tx_stat_gt127_hi
uint32_t rx_stat_grmeb_hi
uint32_t rx_stat_grxpf_hi
uint32_t rx_stat_gr9216_hi
uint32_t tx_stat_gtbca_hi
uint32_t rx_stat_gr1518_hi
uint32_t tx_stat_gtufl_hi
uint32_t rx_stat_gr127_hi
uint32_t rx_stat_gr2047_hi
uint32_t tx_stat_gt16383_hi
uint32_t tx_stat_gt16383_lo
uint32_t rx_stat_grfrg_hi
uint32_t rx_stat_grfrg_lo
uint32_t rx_stat_grxcf_lo
uint32_t tx_stat_gt255_lo
uint32_t tx_stat_gt255_hi
uint32_t tx_stat_gtfrg_hi
uint32_t rx_stat_grbyt_hi
uint32_t rx_stat_grovr_hi
uint32_t rx_stat_grxpf_lo
uint32_t tx_stat_gtfcs_lo
uint32_t rx_stat_grxuo_hi
uint32_t tx_stat_gtbca_lo
uint32_t tx_stat_gtmca_lo
uint32_t rx_stat_gr255_hi
uint32_t tx_stat_gtfcs_hi
uint32_t rx_stat_gr1518_lo
uint32_t rx_stat_gr2047_lo
uint32_t rx_stat_grmca_lo
uint32_t tx_stat_gtfrg_lo
uint32_t rx_stat_grfcs_lo
uint32_t rx_stat_grbyt_lo
uint32_t rx_stat_grerb_lo
uint32_t rx_stat_grovr_lo
uint32_t tx_stat_gt2047_hi
uint32_t tx_stat_gtmax_lo
uint32_t tx_stat_gterr_lo
uint32_t rx_stat_gr127_lo
uint32_t rx_stat_grfcs_hi
uint32_t rx_stat_gripj_hi
uint32_t rx_stat_grpkt_lo
uint32_t rx_stat_grmca_hi
uint32_t tx_stat_gt127_lo
uint32_t rx_stat_gr4095_hi
uint32_t rx_stat_grbca_lo
uint32_t rx_stat_grund_hi
uint32_t rx_stat_grxcf_hi
uint32_t tx_stat_gtbyt_lo
uint32_t rx_stat_grmax_hi
uint32_t tx_stat_gt4095_lo
uint32_t rx_stat_grfre_lo
uint32_t rx_stat_grflr_lo
uint32_t rx_stat_gr16383_hi
uint32_t tx_stat_gtmax_hi
uint32_t rx_stat_gripj_lo
uint32_t rx_stat_grmax_lo
uint32_t rx_stat_gr1023_lo
uint32_t rx_stat_gr16383_lo
uint32_t tx_stat_gt1023_hi
uint32_t tx_stat_gt511_hi
uint32_t tx_stat_gt9216_lo
uint32_t rx_stat_grmeg_hi
uint32_t rx_stat_gr9216_lo
uint32_t rx_stat_gr4095_lo
uint32_t rx_stat_grxpf_hi
uint32_t tx_stat_gt16383_hi
uint32_t tx_stat_gtufl_hi
uint32_t tx_stat_gt127_lo
uint32_t rx_stat_grfcs_hi
uint32_t rx_stat_grerb_hi
uint32_t rx_stat_grfcs_lo
uint32_t rx_stat_grmeg_hi
uint32_t rx_stat_grmca_hi
uint32_t tx_stat_gt9216_hi
uint32_t rx_stat_gripj_hi
uint32_t tx_stat_gt2047_lo
uint32_t tx_stat_gt511_lo
uint32_t rx_stat_gruca_lo
uint32_t rx_stat_gr9216_hi
uint32_t rx_stat_grmeg_lo
uint32_t rx_stat_gr255_lo
uint32_t rx_stat_grpkt_hi
uint32_t tx_stat_gtxpf_hi
uint32_t rx_stat_gr16383_hi
uint32_t tx_stat_gtxpf_lo
uint32_t rx_stat_gruca_hi
uint32_t tx_stat_gt9216_lo
uint32_t rx_stat_grbyt_hi
uint32_t rx_stat_grpok_lo
uint32_t rx_stat_grflr_lo
uint32_t rx_stat_gr9216_lo
uint32_t tx_stat_gtbca_lo
uint32_t rx_stat_grovr_lo
uint32_t rx_stat_gr511_lo
uint32_t rx_stat_grjbr_hi
uint32_t tx_stat_gtfcs_lo
uint32_t rx_stat_grxcf_lo
uint32_t tx_stat_gtmca_hi
uint32_t tx_stat_gt255_lo
uint32_t rx_stat_grpkt_lo
uint32_t tx_stat_gt127_hi
uint32_t rx_stat_gr4095_hi
uint32_t tx_stat_gtuca_lo
uint32_t tx_stat_gtfrg_lo
uint32_t tx_stat_gtbca_hi
uint32_t rx_stat_grxuo_hi
uint32_t rx_stat_grxuo_lo
uint32_t rx_stat_grbca_lo
uint32_t rx_stat_grfrg_hi
uint32_t rx_stat_grfre_hi
uint32_t rx_stat_grmca_lo
uint32_t rx_stat_grxcf_hi
uint32_t rx_stat_gr2047_hi
uint32_t rx_stat_gr2047_lo
uint32_t tx_stat_gt255_hi
uint32_t rx_stat_grfre_lo
uint32_t tx_stat_gt511_hi
uint32_t rx_stat_grerb_lo
uint32_t tx_stat_gtufl_lo
uint32_t rx_stat_gr1023_hi
uint32_t rx_stat_grxpf_lo
uint32_t tx_stat_gterr_lo
uint32_t tx_stat_gt2047_hi
uint32_t rx_stat_grovr_hi
uint32_t rx_stat_gr1518_hi
uint32_t tx_stat_gt4095_lo
uint32_t rx_stat_grbca_hi
uint32_t rx_stat_grmeb_hi
uint32_t rx_stat_gr127_lo
uint32_t tx_stat_gtbyt_lo
uint32_t tx_stat_gtovr_lo
uint32_t tx_stat_gtbyt_hi
uint32_t tx_stat_gtfcs_hi
uint32_t rx_stat_gr4095_lo
uint32_t tx_stat_gt1023_lo
uint32_t rx_stat_grmax_lo
uint32_t rx_stat_gr255_hi
uint32_t tx_stat_gtpkt1_hi
uint32_t tx_stat_gtmax_hi
uint32_t rx_stat_gripj_lo
uint32_t tx_stat_gt4095_hi
uint32_t rx_stat_grmeb_lo
uint32_t rx_stat_gr1023_lo
uint32_t rx_stat_gr127_hi
uint32_t rx_stat_grmax_hi
uint32_t tx_stat_gt1023_hi
uint32_t tx_stat_gt1518_hi
uint32_t tx_stat_gtfrg_hi
uint32_t rx_stat_grflr_hi
uint32_t rx_stat_grund_lo
uint32_t tx_stat_gtuca_hi
uint32_t rx_stat_grfrg_lo
uint32_t tx_stat_gtmca_lo
uint32_t rx_stat_grpok_hi
uint32_t tx_stat_gterr_hi
uint32_t tx_stat_gtovr_hi
uint32_t rx_stat_grbyt_lo
uint32_t tx_stat_gtpkt1_lo
uint32_t rx_stat_grund_hi
uint32_t tx_stat_gt16383_lo
uint32_t tx_stat_gtmax_lo
uint32_t tx_stat_gt1518_lo
uint32_t rx_stat_gr16383_lo
uint32_t rx_stat_gr1518_lo
uint32_t rx_stat_grjbr_lo
uint32_t rx_stat_gr511_hi
uint8_t val[MAX_VLAN_PRIORITIES]
uint8_t statistics_counter_id
uint8_t statistics_zero_flg
uint8_t statistics_en_flg
struct client_init_general_data general
struct client_init_tx_data tx
struct client_init_rx_data rx
uint16_t sge_pause_thr_high
uint16_t silent_vlan_value
uint16_t sge_pause_thr_low
uint8_t dont_verify_rings_pause_thr_flg
uint8_t vmqueue_mode_en_flg
uint8_t drop_udp_cs_err_flg
uint8_t rx_sb_index_number
uint8_t inner_vlan_removal_enable_flg
struct regpair_t sge_page_base
uint16_t bd_pause_thr_low
uint8_t drop_tcp_cs_err_flg
uint8_t outer_vlan_removal_enable_flg
uint8_t handle_ptp_pkts_flg
uint8_t silent_vlan_removal_flg
uint8_t drop_ip_cs_err_flg
uint16_t cqe_pause_thr_low
uint16_t cqe_pause_thr_high
uint16_t silent_vlan_mask
uint16_t bd_pause_thr_high
uint8_t enable_dynamic_hc
uint8_t approx_mcast_engine_id
uint8_t max_sges_for_packet
struct regpair_t bd_page_base
uint8_t extra_data_over_sgl_en_flg
uint8_t cache_line_alignment_log_size
struct regpair_t cqe_page_base
uint8_t tunnel_non_lso_pcsum_location
uint8_t anti_spoofing_flg
uint8_t refuse_outband_vlan_flg
uint8_t enforce_security_flg
struct regpair_t tx_bd_page_base
uint8_t tss_leading_client_id
uint8_t tunnel_lso_inc_ip_id
uint8_t force_default_pri_flg
uint8_t tx_status_block_id
uint8_t tunnel_non_lso_outer_ip_csum_location
uint8_t tx_sb_index_number
uint8_t outer_vlan_removal_enable_flg
uint8_t tx_switching_change_flg
uint8_t inner_vlan_removal_change_flg
uint8_t handle_ptp_pkts_change_flg
uint8_t default_vlan_enable_flg
uint8_t outer_vlan_removal_change_flg
uint16_t silent_vlan_mask
uint8_t default_vlan_change_flg
uint8_t refuse_outband_vlan_flg
uint8_t activate_change_flg
uint8_t anti_spoofing_change_flg
uint8_t inner_vlan_removal_enable_flg
uint8_t anti_spoofing_enable_flg
uint8_t refuse_outband_vlan_change_flg
uint8_t handle_ptp_pkts_flg
uint8_t silent_vlan_change_flg
uint8_t silent_vlan_removal_flg
uint16_t silent_vlan_value
struct cmng_struct_per_port port
struct rate_shaping_vars_per_port rs_vars
struct safc_struct_per_port safc_vars
struct cmng_flags_per_port flags
struct fairness_vars_per_port fair_vars
struct rate_shaping_vars_per_vn vnic_max_rate[4]
struct fairness_vars_per_vn vnic_min_rate[4]
struct fcoe_bd_ctx sge[3]
struct ramrod_data protocol_data
uint32_t conn_and_cmd_data
struct regpair_t cq_db_base
uint32_t hq_bd_buffer_offset
uint32_t hq_bd_data_segment_len
struct regpair_t hq_pbl_base
struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr
struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr
struct regpair_t hq_curr_pbe
struct regpair_t task_pbl_base
struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr
struct regpair_t reserved[2]
struct hc_dynamic_drv_counter hc_dyn_drv_cnt
uint32_t __rel_seq_threshold
struct cstorm_toe_st_context context
uint32_t __last_rel_to_notify
uint32_t bds_ring_page_base_addr_hi
uint32_t bds_ring_page_base_addr_lo
struct trigger_vf_zone trigger
struct non_trigger_vf_zone non_trigger
struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]
struct dcbx_ets_feature ets
struct dcbx_app_priority_feature app
struct dcbx_pfc_feature pfc
uint32_t iscsi_boot_signature
uint32_t iscsi_boot_block_offset
uint32_t ext_phy_fw_version
struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]
uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]
uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]
uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]
uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]
uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]
uint32_t tx_stat_dot3statsinternalmactransmiterrors
uint32_t rx_stat_etherstatspktsover1522octets
uint32_t tx_stat_dot3statsdeferredtransmissions
uint32_t rx_stat_etherstatspkts256octetsto511octets
uint32_t tx_stat_outxonsent
uint32_t rx_stat_xoffpauseframesreceived
uint32_t rx_stat_etherstatspkts128octetsto255octets
uint32_t rx_stat_dot3statsalignmenterrors
uint32_t rx_stat_etherstatsundersizepkts
uint32_t rx_stat_maccontrolframesreceived
uint32_t rx_stat_etherstatspkts512octetsto1023octets
uint32_t rx_stat_ifhcinbroadcastpkts
uint32_t rx_stat_xonpauseframesreceived
uint32_t tx_stat_ifhcoutbroadcastpkts
uint32_t tx_stat_dot3statslatecollisions
uint32_t tx_stat_outxoffsent
uint32_t rx_stat_dot3statsfcserrors
uint32_t tx_stat_ifhcoutoctets
uint32_t tx_stat_flowcontroldone
uint32_t tx_stat_dot3statsmultiplecollisionframes
uint32_t tx_stat_ifhcoutucastpkts
uint32_t rx_stat_dot3statsframestoolong
uint32_t rx_stat_etherstatspkts64octets
uint32_t tx_stat_etherstatspkts256octetsto511octets
uint32_t rx_stat_etherstatsjabbers
uint32_t rx_stat_ifhcinoctets
uint32_t tx_stat_etherstatspkts65octetsto127octets
uint32_t rx_stat_dot3statscarriersenseerrors
uint32_t tx_stat_ifhcoutmulticastpkts
uint32_t rx_stat_falsecarriererrors
uint32_t tx_stat_etherstatspkts512octetsto1023octets
uint32_t rx_stat_xoffstateentered
uint32_t tx_stat_etherstatscollisions
uint32_t tx_stat_etherstatspktsover1522octets
uint32_t tx_stat_etherstatspkts128octetsto255octets
uint32_t rx_stat_ifhcinmulticastpkts
uint32_t rx_stat_etherstatsfragments
uint32_t rx_stat_etherstatspkts65octetsto127octets
uint32_t rx_stat_ifhcinbadoctets
uint32_t tx_stat_etherstatspkts1024octetsto1522octets
uint32_t rx_stat_etherstatspkts1024octetsto1522octets
uint32_t rx_stat_ifhcinucastpkts
uint32_t tx_stat_etherstatspkts64octets
uint32_t tx_stat_ifhcoutbadoctets
uint32_t tx_stat_dot3statssinglecollisionframes
uint32_t tx_stat_dot3statsexcessivecollisions
struct eth_classify_cmd_header header
struct eth_classify_cmd_header header
struct eth_classify_cmd_header header
struct eth_classify_header header
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]
struct eth_classify_cmd_header header
struct xstorm_eth_st_context xstorm_st_context
struct timers_block_context timers_context
struct xstorm_eth_ag_context xstorm_ag_context
struct ustorm_eth_st_context ustorm_st_context
struct cstorm_eth_ag_context cstorm_ag_context
struct ustorm_eth_ag_context ustorm_ag_context
struct cstorm_eth_st_context cstorm_st_context
struct tstorm_eth_ag_context tstorm_ag_context
struct tstorm_eth_st_context tstorm_st_context
uint16_t num_of_coalesced_segs
union eth_sgl_or_raw_data sgl_or_raw_data
uint16_t pkt_len_or_gro_seg_len
union eth_sgl_or_raw_data sgl_or_raw_data
uint8_t tunn_inner_hdrs_offset
struct parsing_flags pars_flags
struct regpair_t reserved4
struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]
struct eth_classify_header header
struct eth_classify_header header
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]
struct regpair_t reserved3
struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]
struct eth_classify_header header
union eth_specific_data data
uint8_t ip_hdr_start_inner_w
union eth_tx_bd_types bds[13]
uint8_t fw_ip_hdr_to_payload_w
uint8_t tunnel_udp_hdr_start_w
uint16_t fw_ip_csum_wo_len_flags_frag
union eth_mac_addr_or_tunnel_data data
uint16_t vlan_or_ethertype
struct eth_tx_bd_flags bd_flags
struct regpair_native_t base_addr
uint32_t mac_threshold_val
uint32_t phy_threshold_val
uint32_t current_iffe_mask
uint32_t temperature_report
uint32_t temperature_monitor2
uint32_t dbg_rx_sigdet_threshold
uint32_t temperature_monitor1
uint32_t manufacture_data
uint32_t fairness_timeout
uint32_t cos_credit_delta[MAX_COS_NUMBER]
uint32_t abts_rsp_payload[7]
struct regpair_t second_buf_addr
struct regpair_t cur_buf_addr
uint32_t rolled_tx_data_offset
uint16_t rolled_tx_seq_cnt
struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe
struct fcoe_kwqe_conn_offload4 offload_kwqe4
struct fcoe_kwqe_conn_offload3 offload_kwqe3
struct fcoe_kwqe_conn_offload2 offload_kwqe2
struct fcoe_kwqe_conn_offload1 offload_kwqe1
struct xstorm_fcoe_st_context xstorm_st_context
struct tstorm_fcoe_st_context tstorm_st_context
struct timers_block_context timers_context
struct ustorm_fcoe_ag_context ustorm_ag_context
struct xstorm_fcoe_ag_context xstorm_ag_context
struct ustorm_fcoe_st_context ustorm_st_context
struct tstorm_fcoe_ag_context tstorm_ag_context
struct fcoe_abts_info ctx
struct fcoe_cleanup_info ctx
struct fcoe_fw_tx_seq_ctx ctx
struct fcoe_mul_sges_ctx mul_sgl
struct fcoe_fc_hdr fc_hdr
struct regpair_t reserved0
struct fcoe_fcp_rsp_flags fcp_flags
uint16_t retry_delay_timer
struct fcoe_fcp_rsp_payload payload
struct regpair_t reserved0
struct fcoe_kwqe_init3 init_kwqe3
struct regpair_t eq_pbl_base
struct fcoe_kwqe_init2 init_kwqe2
struct fcoe_kwqe_init1 init_kwqe1
union fcoe_kcqe_params params
uint32_t completion_status
uint32_t fcoe_conn_context_id
struct fcoe_kwqe_header hdr
uint8_t dst_mac_addr_hi[2]
uint8_t dst_mac_addr_mid[2]
uint8_t src_mac_addr_hi[2]
uint8_t src_mac_addr_mid[2]
uint8_t dst_mac_addr_lo[2]
struct fcoe_kwqe_header hdr
uint8_t src_mac_addr_lo[2]
uint32_t rq_first_pbe_addr_lo
struct fcoe_kwqe_header hdr
uint32_t rq_first_pbe_addr_hi
struct fcoe_kwqe_header hdr
uint16_t tx_max_fc_pay_len
struct fcoe_kwqe_header hdr
uint8_t tx_max_conc_seqs_c3
uint16_t tx_total_conc_seqs
uint16_t rx_max_fc_pay_len
uint16_t rx_total_conc_seqs
uint8_t rx_max_conc_seqs_c3
uint8_t rx_open_seqs_exch_c3
uint32_t confq_first_pbe_addr_hi
uint32_t confq_first_pbe_addr_lo
struct fcoe_kwqe_header hdr
uint8_t dst_mac_addr_lo[2]
uint32_t confq_pbl_base_addr_lo
uint8_t src_mac_addr_hi[2]
uint8_t e_d_tov_timer_val
uint8_t dst_mac_addr_mid[2]
uint8_t dst_mac_addr_hi[2]
uint8_t src_mac_addr_mid[2]
uint32_t confq_pbl_base_addr_hi
uint8_t src_mac_addr_lo[2]
struct fcoe_kwqe_header hdr
uint32_t dummy_buffer_addr_hi
uint32_t dummy_buffer_addr_lo
uint32_t task_list_pbl_addr_lo
uint32_t task_list_pbl_addr_hi
uint16_t rq_buffer_log_size
struct fcoe_kwqe_header hdr
uint32_t t2_hash_tbl_addr_lo
uint32_t t2_hash_tbl_addr_hi
uint32_t hash_tbl_pbl_addr_lo
uint8_t hsi_major_version
uint32_t t2_ptr_hash_tbl_addr_hi
struct fcoe_kwqe_header hdr
uint32_t hash_tbl_pbl_addr_hi
uint8_t hsi_minor_version
uint32_t t2_ptr_hash_tbl_addr_lo
struct fcoe_kwqe_header hdr
uint32_t error_bit_map_hi
uint32_t error_bit_map_lo
uint32_t stat_params_addr_hi
struct fcoe_kwqe_header hdr
uint32_t stat_params_addr_lo
struct fcoe_fc_hdr fc_hdr
struct regpair_t cur_sge_addr
union fcoe_sgl_union_ctx sgl_ctx
struct fcoe_s_stat_ctx s_stat
uint32_t fcoe_rx_byte_cnt
uint32_t fcoe_rx_drop_pkt_cnt
uint32_t fcoe_rx_drop_pkt_cnt
struct fcoe_kwqe_stat stat_kwqe
struct fcoe_rx_stat_params_section0 rx_stat0
struct fcoe_rx_stat_params_section1 rx_stat1
struct fcoe_rx_stat_params_section2 rx_stat2
struct fcoe_tx_stat_params tx_stat
struct fcoe_tce_rx_wr_tx_rd rxwr_txrd
struct fcoe_tce_tx_wr_rx_rd txwr_rxrd
struct fcoe_tce_tx_only txwr_only
struct fcoe_tce_rx_only rxwr_only
union fcoe_rx_wr_union_ctx union_ctx
struct fcoe_rx_seq_ctx rx_seq_ctx
struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy
struct fcoe_tce_rx_wr_tx_rd_const const_ctx
struct fcoe_tce_rx_wr_tx_rd_var var_ctx
union fcoe_sgl_union_ctx sgl_ctx
struct fcoe_tce_tx_wr_rx_rd_const const_ctx
union fcoe_tx_wr_rx_rd_union_ctx union_ctx
uint32_t fcoe_tx_byte_cnt
struct fcoe_tce_tx_wr_rx_rd_const const_ctx
union fcoe_u_tce_tx_wr_rx_rd_union union_ctx
struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]
uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES]
uint32_t iscsi_mac_addr_upper
uint32_t fcoe_mac_addr_lower
uint32_t iscsi_mac_addr_lower
uint32_t fcoe_wwn_port_name_lower
uint32_t fcoe_mac_addr_upper
uint32_t fcoe_wwn_node_name_lower
uint32_t fcoe_wwn_port_name_upper
uint32_t fcoe_wwn_node_name_upper
uint8_t sd_accept_mf_clss_fail
uint8_t inner_clss_l2geneve
uint8_t sd_accept_mf_clss_fail_match_ethtype
uint8_t sd_vlan_force_pri_val
uint8_t allow_npar_tx_switching
struct c2s_pri_trans_table_entry c2s_pri_trans_table
uint16_t sd_vlan_eth_type
uint8_t sd_vlan_force_pri_flg
uint16_t sd_accept_mf_clss_fail_ethtype
uint8_t sd_vlan_force_pri_change_flg
uint8_t allowed_priorities
uint16_t afex_default_vlan
uint8_t sd_vlan_force_pri_val
uint8_t afex_default_vlan_change_flg
uint8_t lb_mode_en_change_flg
uint8_t inner_clss_l2geneve
uint8_t tx_switch_suspend
uint8_t sd_vlan_eth_type_change_flg
uint8_t update_tunn_cfg_flg
uint8_t tx_switch_suspend_change_flg
uint8_t sd_vlan_tag_change_flg
uint8_t allowed_priorities_change_flg
uint16_t sd_vlan_eth_type
uint8_t vif_id_change_flg
uint8_t network_cos_mode_change_flg
uint8_t sd_vlan_force_pri_flg
uint32_t val[HC_SB_MAX_DYNAMIC_INDICES]
uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]
struct regpair_native_t rsrv1[2]
struct regpair_native_t host_sb_addr
struct hc_status_block_sm state_machine[HC_SB_MAX_SM]
struct regpair_native_t host_sb_addr
uint16_t index_values[HC_SP_SB_MAX_INDICES]
struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]
struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]
uint16_t running_index[HC_SB_MAX_SM]
uint16_t index_values[HC_SB_MAX_INDICES_E1X]
uint16_t index_values[HC_SB_MAX_INDICES_E2]
uint16_t running_index[HC_SB_MAX_SM]
uint32_t total_unicast_packets_transmitted_lo
uint32_t total_bytes_transmitted_hi
uint32_t valid_bytes_received_hi
uint32_t total_broadcast_packets_transmitted_hi
uint32_t host_func_stats_start
uint32_t total_broadcast_packets_received_hi
uint32_t total_multicast_packets_transmitted_hi
uint32_t total_unicast_packets_received_lo
uint32_t total_broadcast_packets_received_lo
uint32_t total_unicast_packets_received_hi
uint32_t total_bytes_transmitted_lo
uint32_t total_multicast_packets_received_lo
uint32_t total_multicast_packets_received_hi
uint32_t total_unicast_packets_transmitted_hi
uint32_t total_broadcast_packets_transmitted_lo
uint32_t total_bytes_received_hi
uint32_t host_func_stats_end
uint32_t total_multicast_packets_transmitted_lo
uint32_t valid_bytes_received_lo
uint32_t total_bytes_received_lo
struct hc_status_block_e1x sb
struct hc_status_block_e2 sb
uint32_t host_port_stats_counter
uint32_t pfc_frames_tx_hi
uint32_t pfc_frames_rx_lo
uint32_t pfc_frames_tx_lo
uint32_t eee_lpi_count_hi
uint32_t pfc_frames_rx_hi
uint32_t eee_lpi_count_lo
struct hc_sp_status_block sp_sb
struct atten_sp_status_block atten_status_block
uint32_t scsi_command_block[4]
uint32_t expected_data_transfer_length
struct regpair_t reserved[8]
struct ustorm_iscsi_st_context ustorm_st_context
struct regpair_t xpb_context
struct tstorm_iscsi_st_context tstorm_st_context
struct xstorm_iscsi_st_context xstorm_st_context
struct cstorm_iscsi_st_context cstorm_st_context
struct ustorm_iscsi_ag_context ustorm_ag_context
struct xstorm_iscsi_ag_context xstorm_ag_context
struct cstorm_iscsi_ag_context cstorm_ag_context
struct timers_block_context timers_context
struct regpair_t upb_context
struct tstorm_iscsi_ag_context tstorm_ag_context
struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8]
struct iscsi_cq_db_pnd_comp_itt_arr cq_c_pend_comp_itt_arr
struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_u_prod_pend_comp_ctr_arr
struct iscsi_cq_db_sqn_2_notify_arr cq_drv_sqn_2_notify_arr
union iscsi_pdu_headers_little_endian pdu_header
uint32_t completion_status
union iscsi_kcqe_params params
uint32_t iscsi_conn_context_id
uint32_t sq_page_table_addr_lo
uint32_t cq_page_table_addr_hi
uint32_t cq_page_table_addr_lo
uint32_t sq_page_table_addr_hi
uint32_t rq_page_table_addr_lo
uint32_t num_additional_wqes
struct iscsi_pte sq_first_pte
uint32_t rq_page_table_addr_hi
struct iscsi_pte cq_first_pte
struct iscsi_pte qp_first_pte[3]
uint32_t max_send_pdu_length
uint32_t max_recv_pdu_length
uint32_t max_burst_length
uint32_t first_burst_length
uint32_t dummy_buffer_addr_lo
uint32_t dummy_buffer_addr_hi
uint32_t error_bit_map[2]
uint32_t exp_r2t_buff_offset
uint32_t data_out_buffer_offset
uint32_t total_data_acked
struct iscsi_task_context_r2t_table_entry r2t_table[4]
uint32_t exp_data_transfer_len
struct iscsi_task_context_entry_xuc_xu_write_both write_xu
uint32_t exp_data_transfer_len
struct iscsi_task_context_entry_xuc_x_write_only write_x
struct iscsi_task_context_entry_xuc_u_write_only write_u
struct iscsi_task_context_entry_xuc_c_write_only write_c
struct iscsi_task_context_entry_u tce_u
struct iscsi_task_context_entry_x tce_x
struct iscsi_task_context_entry_xuc tce_xuc
uint32_t desired_data_len
uint32_t referenced_task_tag
struct dcbx_features features
uint32_t num_tx_dcbx_pkts
uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]
uint32_t num_rx_dcbx_pkts
uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]
struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]
struct dcbx_features features
uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]
uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]
struct dcbx_features features
struct mac_configuration_hdr hdr
struct mac_configuration_entry config_table[64]
uint32_t clients_bit_vector
uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi
uint32_t tx_stat_outxonsent_hi
uint32_t tx_stat_mac_2047_hi
uint32_t rx_stat_ifhcinbadoctets_hi
uint32_t tx_stat_etherstatspkts65octetsto127octets_lo
uint32_t tx_stat_mac_16383_hi
uint32_t rx_stat_mac_xcf_hi
uint32_t tx_stat_mac_16383_lo
uint32_t rx_stat_etherstatsundersizepkts_lo
uint32_t rx_stat_dot3statsfcserrors_lo
uint32_t tx_stat_etherstatspktsover1522octets_hi
uint32_t rx_stat_ifhcinbadoctets_lo
uint32_t tx_stat_etherstatspktsover1522octets_lo
uint32_t tx_stat_ifhcoutbadoctets_hi
uint32_t rx_stat_dot3statsalignmenterrors_lo
uint32_t rx_stat_xoffpauseframesreceived_hi
uint32_t rx_stat_xoffpauseframesreceived_lo
uint32_t rx_stat_maccontrolframesreceived_lo
uint32_t tx_stat_dot3statsmultiplecollisionframes_hi
uint32_t tx_stat_etherstatspkts64octets_lo
uint32_t tx_stat_dot3statsmultiplecollisionframes_lo
uint32_t rx_stat_xonpauseframesreceived_hi
uint32_t tx_stat_dot3statsexcessivecollisions_hi
uint32_t rx_stat_xoffstateentered_lo
uint32_t rx_stat_dot3statscarriersenseerrors_lo
uint32_t rx_stat_maccontrolframesreceived_hi
uint32_t rx_stat_etherstatsundersizepkts_hi
uint32_t tx_stat_mac_ufl_lo
uint32_t tx_stat_flowcontroldone_hi
uint32_t tx_stat_dot3statsdeferredtransmissions_hi
uint32_t rx_stat_etherstatsjabbers_hi
uint32_t tx_stat_dot3statsdeferredtransmissions_lo
uint32_t rx_stat_mac_xcf_lo
uint32_t rx_stat_dot3statsalignmenterrors_hi
uint32_t tx_stat_mac_2047_lo
uint32_t rx_stat_dot3statsframestoolong_lo
uint32_t rx_stat_dot3statsfcserrors_hi
uint32_t tx_stat_outxoffsent_lo
uint32_t tx_stat_mac_4095_hi
uint32_t rx_stat_mac_xpf_lo
uint32_t tx_stat_dot3statssinglecollisionframes_hi
uint32_t tx_stat_outxoffsent_hi
uint32_t tx_stat_flowcontroldone_lo
uint32_t tx_stat_dot3statslatecollisions_hi
uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo
uint32_t tx_stat_mac_9216_lo
uint32_t rx_stat_dot3statscarriersenseerrors_hi
uint32_t tx_stat_etherstatspkts65octetsto127octets_hi
uint32_t rx_stat_falsecarriererrors_hi
uint32_t rx_stat_etherstatsfragments_hi
uint32_t tx_stat_etherstatspkts64octets_hi
uint32_t tx_stat_etherstatspkts128octetsto255octets_hi
uint32_t rx_stat_dot3statsframestoolong_hi
uint32_t rx_stat_mac_xpf_hi
uint32_t tx_stat_mac_ufl_hi
uint32_t rx_stat_falsecarriererrors_lo
uint32_t tx_stat_etherstatscollisions_lo
uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi
uint32_t rx_stat_etherstatsfragments_lo
uint32_t tx_stat_etherstatscollisions_hi
uint32_t tx_stat_outxonsent_lo
uint32_t tx_stat_etherstatspkts256octetsto511octets_lo
uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo
uint32_t tx_stat_dot3statsexcessivecollisions_lo
uint32_t rx_stat_xoffstateentered_hi
uint32_t tx_stat_ifhcoutbadoctets_lo
uint32_t tx_stat_dot3statssinglecollisionframes_lo
uint32_t rx_stat_xonpauseframesreceived_lo
uint32_t tx_stat_mac_4095_lo
uint32_t tx_stat_etherstatspkts256octetsto511octets_hi
uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo
uint32_t rx_stat_etherstatsjabbers_lo
uint32_t tx_stat_mac_9216_hi
uint32_t tx_stat_etherstatspkts128octetsto255octets_lo
uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi
uint32_t tx_stat_dot3statslatecollisions_lo
struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]
struct shared_mf_cfg shared_mf_config
struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]
struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]
uint32_t opaque[MGMTFW_STATE_WORD_SIZE]
uint32_t tx_latecollisions_lo
struct mstat_stats::@17 stats_rx
uint32_t tx_excessivecollisions_hi
uint32_t rx_falsecarrier_hi
struct mstat_stats::@16 stats_tx
uint32_t tx_excessivecollisions_lo
uint32_t tx_singlecollision_hi
uint32_t tx_singlecollision_lo
uint32_t rx_alignmenterrors_hi
uint32_t tx_latecollisions_hi
uint32_t tx_collisions_lo
uint32_t tx_multiplecollisions_lo
uint32_t rx_alignmenterrors_lo
uint32_t rx_falsecarrier_lo
uint32_t tx_collisions_hi
uint32_t rx_llfcmsgcnt_lo
uint32_t tx_multiplecollisions_hi
uint32_t rx_llfcmsgcnt_hi
struct vf_pf_channel_zone_data vf_pf_channel
uint8_t uuid[OEM_I2C_UUID_STR_LEN]
uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN]
uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN]
uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN]
uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN]
uint32_t versions[MAX_DRV_PERS]
struct tstorm_per_pf_stats tstorm_pf_statistics
struct tstorm_per_port_stats tstorm_port_statistics
struct xstorm_per_queue_stats xstorm_queue_statistics
struct ustorm_per_queue_stats ustorm_queue_statistics
struct tstorm_per_queue_stats tstorm_queue_statistics
uint32_t mfw_wol_link_cfg2
uint32_t mfw_wol_link_cfg
uint32_t generic_features
uint32_t multi_phy_config
uint32_t fcoe_wwn_port_name_upper
uint32_t backup_mac_lower
uint32_t fcoe_fip_mac_upper
uint16_t xgxs_config_tx[4]
uint32_t wwpn_for_npiv_config
uint32_t power_dissipated
uint32_t speed_capability_mask2
uint32_t fcoe_wwn_node_name_upper
uint32_t fcoe_fip_mac_lower
uint32_t fcoe_wwn_node_name_lower
uint16_t xgxs_config_rx[4]
uint16_t xgxs_config2_tx[4]
uint32_t wwpn_for_npiv_valid_addresses
uint32_t fcoe_wwn_port_name_lower
struct mac_addr wwpn_for_niv_macs[16]
uint32_t external_phy_config2
uint32_t external_phy_config
uint32_t backup_mac_upper
uint16_t xgxs_config2_rx[4]
uint32_t speed_capability_mask
uint32_t tx_pfc_frames_lo
uint32_t rx_pfc_frames_hi
uint32_t tx_pfc_frames_hi
uint32_t rx_pfc_frames_lo
union protocol_common_specific_data data
uint32_t rs_periodic_timeout
struct rate_shaping_counter vn_counter
struct ustorm_iscsi_cq_db cq[8]
struct regpair_t cq_pbl_base
struct ustorm_iscsi_rq_db rq
struct ustorm_iscsi_r2tq_db r2tq
uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS]
uint8_t cos_to_traffic_types[MAX_COS_NUMBER]
struct regpair_t offset_delta
uint8_t drift_adjust_value
uint8_t add_sub_drift_adjust_value
uint32_t drift_adjust_period
uint32_t ump_nc_si_config
struct port_hw_cfg port_hw_config[PORT_MAX]
struct shared_feat_cfg shared_feature_config
struct shared_hw_cfg shared_hw_config
struct port_feat_cfg port_feature_config[PORT_MAX]
uint32_t oem_i2c_data_addr
uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]
uint32_t dcbx_en[PORT_MAX]
uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX/32]
uint32_t afex_driver_support
uint32_t dcbx_neg_res_ext_offset
uint32_t temperature_in_half_celsius
uint32_t lfa_host_addr[PORT_MAX]
uint32_t buffer_block_addr
uint32_t drv_func_info_addr
uint32_t drv_func_info_size
uint32_t ibft_host_addr_hi
uint32_t afex_param2_to_driver[E2_FUNC_MAX]
uint32_t pf_allocation[E2_FUNC_MAX]
uint32_t other_shmem2_base_addr
uint32_t drv_info_host_addr_lo
uint32_t img_inv_table_addr
uint32_t extended_dev_info_shared_cfg_size
uint32_t drv_info_host_addr_hi
uint32_t nvm_retain_bitmap_addr
uint8_t storage_boot_prog[E2_FUNC_MAX]
uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]
uint32_t afex_profiles_enabled[2]
struct mdump_driver_info drv_info
uint32_t c2s_pcp_map_default[E2_FUNC_MAX]
uint32_t afex_param1_to_driver[E2_FUNC_MAX]
uint32_t dcbx_lldp_dcbx_stat_offset
uint8_t rsrv2[E2_FUNC_MAX]
uint32_t extphy_temps_in_celsius
uint32_t ocdata_info_addr
uint32_t sriov_switch_mode
uint32_t drv_capabilities_flag[E2_FUNC_MAX]
uint32_t edebug_driver_if[2]
uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]
uint32_t dcbx_lldp_params_offset
uint32_t drv_info_control
uint32_t link_attr_sync[PORT_MAX]
uint32_t dcbx_remote_mib_offset
uint32_t eee_status[PORT_MAX]
union shmem2_region::@15 u
uint32_t mfw_drv_indication
enum curr_cfg_method_e curr_cfg
uint32_t sensor_data_req_update_interval
uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]
uint32_t mcp_vf_disabled[E2_VF_MAX/32]
uint32_t glob_struct_in_host
uint32_t ext_phy_fw_version2[PORT_MAX]
uint32_t mtu_size[E2_FUNC_MAX]
uint32_t sizeof_port_stats
uint32_t ncsi_oem_data_addr
uint32_t dcbx_neg_res_offset
uint32_t multi_thread_data_offset
uint32_t other_shmem_base_addr
uint32_t os_driver_state[E2_FUNC_MAX]
uint32_t extended_dev_info_shared_addr
struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]
uint32_t sensor_data_addr
uint32_t link_change_count[PORT_MAX]
uint32_t additional_config
uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]
struct drv_port_mb port_mb[PORT_MAX]
license_key_t drv_lic_key[PORT_MAX]
struct shm_dev_info dev_info
struct drv_func_mb func_mb[]
uint32_t validity_map[PORT_MAX]
uint32_t fw_info_fio_offset
struct regpair_t protocol_data
uint32_t conn_and_cmd_data
struct stats_query_entry query[STATS_QUERY_CMD_COUNT]
struct regpair_t read_addr
struct regpair_t sum_time_ns
struct timers_block_context timers_context
struct tstorm_toe_ag_context tstorm_ag_context
struct xstorm_toe_ag_context xstorm_ag_context
struct cstorm_toe_ag_context cstorm_ag_context
struct ustorm_toe_st_aligned_context ustorm_st_context
struct cstorm_toe_st_aligned_context cstorm_st_context
struct tstorm_toe_st_aligned_context tstorm_st_context
struct xstorm_toe_st_aligned_context xstorm_st_context
struct ustorm_toe_ag_context ustorm_ag_context
union toe_rx_cqe_data_union data
uint32_t consumed_grq_bytes
uint32_t rcv_win_right_edge
union toe_spe_data toe_data
struct xstorm_toe_stats xstorm_toe
struct cstorm_toe_stats cstorm_toe
struct tstorm_toe_stats tstorm_toe
uint8_t ka_max_probe_count
uint16_t rcv_indication_size
uint8_t retransmit_restart
uint8_t complete_on_both_clients
uint16_t sge_pause_thr_low
uint16_t sge_pause_thr_high
uint8_t max_sges_for_packet
uint32_t sge_page_base_hi
uint8_t dont_verify_rings_pause_thr_flg
uint32_t sge_page_base_lo
uint32_t mcast_add_hash_bit_array[8]
uint32_t unmatched_unicast
uint32_t ucast_accept_all
uint32_t bcast_accept_all
uint32_t mcast_accept_all
struct tstorm_fcoe_extra_ag_context_section __extra_section
struct regpair_t reserved1
struct regpair_t reserved0
struct tstorm_iscsi_tcp_ag_context_section tcp
struct regpair_t rq_db_phy_addr
struct tstorm_tcp_st_context_section tcp
struct tstorm_iscsi_st_context_section iscsi
uint32_t wnd_right_edge_local
struct regpair_t rcv_error_bytes
uint32_t brb_truncate_discard
uint32_t mac_filter_discard
struct regpair_t rcv_mcast_bytes
struct regpair_t rcv_ucast_bytes
uint32_t checksum_discard
struct regpair_t rcv_bcast_bytes
uint32_t pkts_too_big_discard
struct regpair_t reserved[4]
uint32_t retransmit_start_time
uint32_t expected_rel_seq
uint32_t timestamp_recent
uint32_t rightmost_received_seq
uint32_t timestamp_recent_time
struct tstorm_toe_tcp_ag_context_section tcp
struct tstorm_toe_st_context context
struct tstorm_toe_st_context_section toe
struct tstorm_tcp_st_context_section tcp
uint32_t ip_in_truncated_packets
uint32_t ip_in_header_errors
struct regpair_t ip_in_octets
struct tstorm_toe_stats_section statistics[2]
struct regpair_t reserved
struct client_init_tx_data tx
struct client_init_general_data general
struct ustorm_fcoe_data_place data_place
struct ustorm_fcoe_tce tce
struct fcoe_bd_ctx cached_sge[2]
struct ustorm_fcoe_data_place_mng cached_mng
struct regpair_t task_addr
struct regpair_t lcq_base_addr
struct regpair_t confq_pbl_base_addr
struct regpair_t conn_db_base
struct regpair_t cq_base_addr
struct ustorm_fcoe_mng_ctx mng_ctx
struct ustorm_fcoe_cache_ctx cache_ctx
struct regpair_t rq_pbl_base
struct ustorm_fcoe_params fcoe_params
struct regpair_t xfrq_base_addr
struct regpair_t rq_cur_page_addr
struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd
struct fcoe_tce_rx_wr_tx_rd rxwr_txrd
struct fcoe_tce_rx_only rxwr
struct regpair_t curr_pbe
uint32_t local_sge_1_address_hi
uint32_t place_db_bitfield_1
uint32_t local_sge_0_address_hi
uint32_t local_sge_1_address_lo
uint32_t local_sge_0_address_lo
uint32_t place_db_bitfield_2
struct regpair_t curr_pbe
struct regpair_t pbl_base
struct regpair_t pbl_base
struct regpair_t curr_pbe
struct regpair_t task_pbl_base
struct regpair_t tce_phy_addr
struct ustorm_iscsi_placement_db place_db
uint32_t negotiated_rx_and_flags
uint32_t bcast_no_buff_pkts
struct regpair_t bcast_no_buff_bytes
struct regpair_t ucast_no_buff_bytes
struct regpair_t mcast_no_buff_bytes
struct regpair_t coalesced_bytes
uint32_t mcast_no_buff_pkts
uint32_t coalesced_events
uint32_t ucast_no_buff_pkts
uint32_t coalesced_aborts
struct regpair_t reserved[3]
struct ustorm_eth_rx_producers eth_rx_producers
uint32_t driver_doorbell_info_ptr_lo
uint32_t driver_doorbell_info_ptr_hi
struct ustorm_toe_st_context context
struct ustorm_toe_prefetched_bd __pen_bd_2
struct ustorm_toe_prefetched_bd __pen_bd_5
struct ustorm_toe_prefetched_bd __pen_bd_1
struct ustorm_toe_prefetched_isle_bd __isle_bd
struct ustorm_toe_prefetched_bd __pen_bd_6
struct ustorm_toe_prefetched_bd __pen_bd_8
uint32_t __rq_available_bytes
uint32_t __min_expiration_time
struct ustorm_toe_prefetched_bd __pen_bd_3
struct ustorm_toe_prefetched_bd __pen_bd_9
uint32_t __prev_consumed_grq_bytes
struct ustorm_toe_prefetched_bd __pen_bd_4
uint32_t prev_rcv_win_right_edge
struct ustorm_toe_prefetched_bd __pen_bd_0
struct ustorm_toe_prefetched_bd __pen_bd_7
uint32_t pen_grq_placed_bytes
struct ustorm_toe_ring_params pen_ring_params
struct regpair_t reserved
struct xstorm_tcp_context_section tcp
struct xstorm_eth_context_section ethernet
union xstorm_ip_context_section_types ip_union
uint32_t confq_pbl_base_lo
struct xstorm_fcoe_extra_ag_context_section __extra_section
uint32_t confq_pbl_base_hi
struct fcoe_cached_wqe cached_wqe[8]
struct regpair_t lcq_base_addr
struct xstorm_fcoe_tce tce
struct regpair_t confq_curr_page_addr
struct xstorm_fcoe_fcp_data fcp_data
struct xstorm_fcoe_context_section fcoe
struct xstorm_fcoe_eth_context_section eth
struct fcoe_tce_tx_only txwr
struct fcoe_tce_tx_wr_rx_rd txwr_rxrd
uint32_t __pbf_hdr_cmd_rsvd_1
uint32_t ip_local_addr_hi_lo
uint32_t ip_remote_addr_lo_lo
uint32_t ip_local_addr_hi_hi
uint32_t ip_remote_addr_lo_hi
uint32_t ip_remote_addr_hi_lo
uint32_t priority_flow_label
uint32_t ip_local_addr_lo_lo
uint32_t ip_local_addr_lo_hi
uint32_t ip_remote_addr_hi_hi
struct xstorm_tcp_tcp_ag_context_section tcp
uint32_t max_send_pdu_length
uint32_t rxmit_bytes_2_dr
uint32_t first_burst_length
uint32_t hq_rxmit_tcp_seq
struct regpair_t hq_curr_pbe_base
struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr
uint32_t exp_data_transfer_len_ttt
struct iscsi_task_context_entry_x temp_tce_x
struct regpair_t r2tq_pbl_base
struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr
struct regpair_t hq_pbl_base
struct regpair_t task_pbl_base
struct regpair_t sq_pbl_base
struct regpair_t sq_curr_pbe
struct regpair_t r2tq_curr_pbe_base
uint32_t pdu_data_2_rxmit
struct xstorm_common_context_section common
struct xstorm_iscsi_context_section iscsi
struct xstorm_ip_v4_context_section ip_v4
struct regpair_t ucast_bytes_sent
struct regpair_t bcast_bytes_sent
struct regpair_t mcast_bytes_sent
struct regpair_t reserved[4]
uint32_t __next_timer_expir
uint32_t cmp_bd_page_32_to_63
struct xstorm_toe_tcp_ag_context_section tcp
uint32_t cmp_bd_page_0_to_31
uint32_t cmp_bd_start_seq
uint32_t driver_doorbell_info_ptr_lo
uint32_t driver_doorbell_info_ptr_hi
uint32_t tx_bd_page_base_lo
uint32_t tx_bd_page_base_hi
struct xstorm_toe_st_context context
struct xstorm_common_context_section common
struct xstorm_toe_context_section toe
uint32_t tcp_out_segments
struct regpair_t ip_out_octets
uint32_t tcp_retransmitted_segments
struct xstorm_toe_stats_section statistics[2]
struct regpair_t reserved
struct eth_classify_mac_cmd mac
struct eth_classify_imac_vni_cmd imac_vni
struct eth_classify_vlan_cmd vlan
struct eth_classify_pair_cmd pair
struct eth_tunnel_data tunnel_data
struct ramrod_data general
struct eth_end_agg_rx_cqe end_agg_cqe
struct common_ramrod_eth_rx_cqe ramrod_cqe
struct eth_fast_path_rx_cqe fast_path_cqe
struct eth_rx_cqe_next_page next_page_cqe
struct regpair_t filter_cfg_addr
struct eth_halt_ramrod_data halt_ramrod_data
struct eth_common_ramrod_data common_ramrod_data
struct regpair_t update_data_addr
struct regpair_t mcast_cfg_addr
struct regpair_t client_init_ramrod_init_data
struct regpair_t classify_cfg_addr
struct eth_tx_next_bd next_bd
struct eth_tx_parse_2nd_bd parse_2nd_bd
struct eth_tx_start_bd start_bd
struct eth_tx_parse_bd_e1x parse_bd_e1x
struct eth_tx_parse_bd_e2 parse_bd_e2
struct vif_list_event_data vif_list_event
struct vf_flr_event_data vf_flr_event
struct function_update_event_data function_update_event
struct vf_pf_event_data vf_pf_event
struct malicious_vf_event_data malicious_vf_event
struct cfc_del_event_data cfc_del_event
struct eth_event_data eth_event
struct event_ring_msg message
struct event_ring_next next_page
struct fcoe_fcp_rsp_union fcp_rsp
struct fcoe_mp_rsp_union mp_rsp
struct fcoe_abts_rsp_union abts_rsp
struct fcoe_idx16_fields fields
struct fcoe_kwqe_init2 init2
struct fcoe_kwqe_conn_offload3 conn_offload3
struct fcoe_kwqe_init3 init3
struct fcoe_kwqe_init1 init1
struct fcoe_kwqe_conn_offload1 conn_offload1
struct fcoe_kwqe_stat statistics
struct fcoe_kwqe_destroy destroy
struct fcoe_kwqe_conn_destroy conn_destroy
struct fcoe_kwqe_conn_offload2 conn_offload2
struct fcoe_kwqe_conn_offload4 conn_offload4
struct fcoe_kwqe_conn_enable_disable conn_enable_disable
struct fcoe_read_flow_info read_info
union fcoe_comp_flow_info comp_info
struct fcoe_cached_sge_ctx cached_sge
struct fcoe_ext_mul_sges_ctx sgl
struct fcoe_ext_cleanup_info cleanup
struct fcoe_fcp_cmd_payload fcp_cmd
struct fcoe_fc_frame tx_frame
struct fcoe_ext_abts_info abts
struct fcoe_ext_fw_tx_seq_ctx tx_seq
struct fcoe_abts_info abts
struct fcoe_cleanup_info cleanup
struct fcoe_fw_tx_seq_ctx tx_seq_ctx
struct fcoe_vlan_fields fields
union fcoe_vlan_field_union vlan
struct igu_regular regular
struct igu_backward_compatible backward_compatible
struct iscsi_kwqe_conn_offload2 conn_offload2
struct iscsi_kwqe_conn_offload1 conn_offload1
struct iscsi_kwqe_conn_offload3 conn_offload3
struct iscsi_kwqe_init1 init1
struct iscsi_kwqe_conn_destroy conn_destroy
struct iscsi_kwqe_init2 init2
struct iscsi_kwqe_conn_update conn_update
struct regpair_t phy_address
struct regpair_t mac_config_addr
struct afex_vif_list_ramrod_data afex_vif_list_data
struct toe_initiate_offload_ramrod_data initiate_offload
struct ramrod_data general
struct toe_rx_cqe_in_order_params in_order_params
struct toe_rx_cqe_ooo_params ooo_params
struct regpair_t phys_addr
struct toe_rx_completion_ramrod_data rx_completion
struct toe_init_ramrod_data toe_init
struct xstorm_padded_ip_v4_context_section padded_ip_v4
struct xstorm_ip_v6_context_section ip_v6