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#define | ECORE_HSI_H |
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#define | FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e |
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#define | LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF |
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#define | LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 |
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#define | LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 |
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#define | LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 |
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#define | LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF |
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#define | LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 |
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#define | LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 |
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#define | LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 |
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#define | PIN_CFG_NA 0x00000000 |
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#define | PIN_CFG_GPIO0_P0 0x00000001 |
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#define | PIN_CFG_GPIO1_P0 0x00000002 |
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#define | PIN_CFG_GPIO2_P0 0x00000003 |
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#define | PIN_CFG_GPIO3_P0 0x00000004 |
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#define | PIN_CFG_GPIO0_P1 0x00000005 |
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#define | PIN_CFG_GPIO1_P1 0x00000006 |
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#define | PIN_CFG_GPIO2_P1 0x00000007 |
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#define | PIN_CFG_GPIO3_P1 0x00000008 |
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#define | PIN_CFG_EPIO0 0x00000009 |
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#define | PIN_CFG_EPIO1 0x0000000a |
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#define | PIN_CFG_EPIO2 0x0000000b |
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#define | PIN_CFG_EPIO3 0x0000000c |
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#define | PIN_CFG_EPIO4 0x0000000d |
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#define | PIN_CFG_EPIO5 0x0000000e |
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#define | PIN_CFG_EPIO6 0x0000000f |
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#define | PIN_CFG_EPIO7 0x00000010 |
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#define | PIN_CFG_EPIO8 0x00000011 |
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#define | PIN_CFG_EPIO9 0x00000012 |
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#define | PIN_CFG_EPIO10 0x00000013 |
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#define | PIN_CFG_EPIO11 0x00000014 |
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#define | PIN_CFG_EPIO12 0x00000015 |
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#define | PIN_CFG_EPIO13 0x00000016 |
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#define | PIN_CFG_EPIO14 0x00000017 |
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#define | PIN_CFG_EPIO15 0x00000018 |
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#define | PIN_CFG_EPIO16 0x00000019 |
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#define | PIN_CFG_EPIO17 0x0000001a |
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#define | PIN_CFG_EPIO18 0x0000001b |
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#define | PIN_CFG_EPIO19 0x0000001c |
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#define | PIN_CFG_EPIO20 0x0000001d |
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#define | PIN_CFG_EPIO21 0x0000001e |
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#define | PIN_CFG_EPIO22 0x0000001f |
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#define | PIN_CFG_EPIO23 0x00000020 |
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#define | PIN_CFG_EPIO24 0x00000021 |
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#define | PIN_CFG_EPIO25 0x00000022 |
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#define | PIN_CFG_EPIO26 0x00000023 |
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#define | PIN_CFG_EPIO27 0x00000024 |
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#define | PIN_CFG_EPIO28 0x00000025 |
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#define | PIN_CFG_EPIO29 0x00000026 |
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#define | PIN_CFG_EPIO30 0x00000027 |
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#define | PIN_CFG_EPIO31 0x00000028 |
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#define | EPIO_CFG_NA 0x00000000 |
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#define | EPIO_CFG_EPIO0 0x00000001 |
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#define | EPIO_CFG_EPIO1 0x00000002 |
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#define | EPIO_CFG_EPIO2 0x00000003 |
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#define | EPIO_CFG_EPIO3 0x00000004 |
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#define | EPIO_CFG_EPIO4 0x00000005 |
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#define | EPIO_CFG_EPIO5 0x00000006 |
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#define | EPIO_CFG_EPIO6 0x00000007 |
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#define | EPIO_CFG_EPIO7 0x00000008 |
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#define | EPIO_CFG_EPIO8 0x00000009 |
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#define | EPIO_CFG_EPIO9 0x0000000a |
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#define | EPIO_CFG_EPIO10 0x0000000b |
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#define | EPIO_CFG_EPIO11 0x0000000c |
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#define | EPIO_CFG_EPIO12 0x0000000d |
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#define | EPIO_CFG_EPIO13 0x0000000e |
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#define | EPIO_CFG_EPIO14 0x0000000f |
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#define | EPIO_CFG_EPIO15 0x00000010 |
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#define | EPIO_CFG_EPIO16 0x00000011 |
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#define | EPIO_CFG_EPIO17 0x00000012 |
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#define | EPIO_CFG_EPIO18 0x00000013 |
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#define | EPIO_CFG_EPIO19 0x00000014 |
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#define | EPIO_CFG_EPIO20 0x00000015 |
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#define | EPIO_CFG_EPIO21 0x00000016 |
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#define | EPIO_CFG_EPIO22 0x00000017 |
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#define | EPIO_CFG_EPIO23 0x00000018 |
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#define | EPIO_CFG_EPIO24 0x00000019 |
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#define | EPIO_CFG_EPIO25 0x0000001a |
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#define | EPIO_CFG_EPIO26 0x0000001b |
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#define | EPIO_CFG_EPIO27 0x0000001c |
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#define | EPIO_CFG_EPIO28 0x0000001d |
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#define | EPIO_CFG_EPIO29 0x0000001e |
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#define | EPIO_CFG_EPIO30 0x0000001f |
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#define | EPIO_CFG_EPIO31 0x00000020 |
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#define | SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 |
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#define | SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 |
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#define | SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 |
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#define | SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 |
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#define | SHARED_HW_CFG_PORT_SWAP 0x00000004 |
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#define | SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 |
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#define | SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 |
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#define | SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 |
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#define | SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 |
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#define | SHARED_HW_CFG_MFW_SELECT_SHIFT 8 |
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#define | SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 |
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#define | SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 |
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#define | SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 |
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#define | SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 |
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#define | SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 |
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#define | SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 |
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#define | SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 |
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#define | SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 |
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#define | SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 |
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#define | SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 |
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#define | SHARED_HW_CFG_LED_MODE_SHIFT 16 |
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#define | SHARED_HW_CFG_LED_MAC1 0x00000000 |
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#define | SHARED_HW_CFG_LED_PHY1 0x00010000 |
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#define | SHARED_HW_CFG_LED_PHY2 0x00020000 |
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#define | SHARED_HW_CFG_LED_PHY3 0x00030000 |
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#define | SHARED_HW_CFG_LED_MAC2 0x00040000 |
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#define | SHARED_HW_CFG_LED_PHY4 0x00050000 |
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#define | SHARED_HW_CFG_LED_PHY5 0x00060000 |
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#define | SHARED_HW_CFG_LED_PHY6 0x00070000 |
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#define | SHARED_HW_CFG_LED_MAC3 0x00080000 |
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#define | SHARED_HW_CFG_LED_PHY7 0x00090000 |
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#define | SHARED_HW_CFG_LED_PHY9 0x000a0000 |
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#define | SHARED_HW_CFG_LED_PHY11 0x000b0000 |
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#define | SHARED_HW_CFG_LED_MAC4 0x000c0000 |
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#define | SHARED_HW_CFG_LED_PHY8 0x000d0000 |
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#define | SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 |
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#define | SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 |
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#define | SHARED_HW_CFG_SRIOV_MASK 0x40000000 |
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#define | SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 |
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#define | SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 |
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#define | SHARED_HW_CFG_ATC_MASK 0x80000000 |
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#define | SHARED_HW_CFG_ATC_DISABLED 0x00000000 |
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#define | SHARED_HW_CFG_ATC_ENABLED 0x80000000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 |
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#define | SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 |
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#define | SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 |
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#define | SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 |
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#define | SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 |
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#define | SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 |
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#define | SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
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#define | SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 |
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#define | SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 |
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#define | SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 |
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#define | SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 |
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#define | SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 |
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#define | SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 |
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#define | SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 |
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#define | SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 |
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#define | SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 |
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#define | SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 |
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#define | SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 |
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#define | SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 |
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#define | SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 |
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#define | SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 |
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#define | SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 |
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#define | SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 |
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#define | SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 |
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#define | SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 |
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#define | SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 |
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#define | SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 |
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#define | SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F |
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#define | SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 |
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#define | SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 |
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#define | SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 |
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#define | SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 |
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#define | SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 |
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#define | SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 |
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#define | SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 |
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#define | SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 |
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#define | SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 |
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#define | SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 |
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#define | SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 |
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#define | SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F |
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#define | SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 |
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#define | SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 |
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#define | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 |
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#define | SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 |
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#define | SHARED_HW_CFG_BOARD_REV_SHIFT 16 |
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#define | SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 |
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#define | SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 |
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#define | SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 |
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#define | SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 |
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#define | SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 |
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#define | SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 |
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#define | SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 |
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#define | SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 |
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#define | SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 |
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#define | SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 |
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#define | SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 |
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#define | SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 |
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#define | SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 |
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#define | SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000 |
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#define | PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 |
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#define | PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 |
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#define | PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 |
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#define | PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 |
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#define | PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 |
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#define | PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 |
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#define | PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF |
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#define | PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 |
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#define | PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 |
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#define | PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 |
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#define | PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 |
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#define | PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 |
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#define | PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 |
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#define | PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF |
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#define | PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 |
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#define | PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 |
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#define | PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 |
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#define | PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 |
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#define | PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 |
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#define | PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 |
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#define | PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_UPPERMAC_SHIFT 0 |
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#define | PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 |
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#define | PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 |
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#define | PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 |
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#define | PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 |
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#define | PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 |
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#define | PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 |
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#define | PORT_HW_CFG_TX_LASER_MASK 0x000000FF |
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#define | PORT_HW_CFG_TX_LASER_SHIFT 0 |
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#define | PORT_HW_CFG_TX_LASER_MDIO 0x00000000 |
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#define | PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 |
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#define | PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 |
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#define | PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 |
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#define | PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 |
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#define | PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 |
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#define | PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF |
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#define | PORT_HW_CFG_E3_TX_LASER_SHIFT 0 |
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#define | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 |
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#define | PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 |
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#define | PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 |
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#define | PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 |
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#define | PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 |
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#define | PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF |
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#define | PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 |
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#define | PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 |
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#define | PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 |
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#define | PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 |
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#define | PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 |
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#define | PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 |
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#define | PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF |
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#define | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 |
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#define | PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 |
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#define | PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 |
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#define | PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 |
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#define | PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 |
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#define | PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 |
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#define | PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 |
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#define | PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 |
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#define | PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000 |
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#define | PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20 |
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#define | PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000 |
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#define | PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24 |
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#define | PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000 |
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#define | PORT_HW_CFG_TX_DRV_POST2_SHIFT 28 |
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#define | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF |
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#define | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 |
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#define | PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 |
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#define | PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 |
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#define | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 |
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#define | PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff |
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#define | PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 |
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#define | PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 |
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#define | PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 |
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#define | PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 |
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#define | PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 |
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#define | PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 |
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#define | PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF |
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#define | PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 |
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#define | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF |
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#define | PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 |
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#define | PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 |
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#define | PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 |
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#define | PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 |
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#define | PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 |
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#define | PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 |
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#define | PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 |
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#define | PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C |
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#define | PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 |
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#define | PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 |
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#define | PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 |
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#define | PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 |
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#define | PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c |
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#define | PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 |
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#define | PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 |
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#define | PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 |
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#define | PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 |
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#define | PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 |
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#define | PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 |
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#define | PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 |
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#define | PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 |
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#define | PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 |
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#define | PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 |
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#define | PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 |
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#define | PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 |
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#define | PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 |
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#define | PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 |
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#define | PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 |
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#define | PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 |
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#define | PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 |
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#define | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 |
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#define | PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 |
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#define | PORT_HW_CFG_ENABLE_CMS_SHIFT 21 |
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#define | PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 |
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#define | PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 |
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#define | PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 |
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#define | PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_SHIFT 28 |
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#define | PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 |
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#define | PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 |
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#define | PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 |
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#define | PORT_HW_CFG_PHY_SELECTION_SHIFT 0 |
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#define | PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 |
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#define | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 |
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#define | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 |
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#define | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 |
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#define | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 |
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#define | PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 |
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#define | PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 |
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#define | PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 |
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#define | PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 |
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#define | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 |
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#define | PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 |
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#define | PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 |
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#define | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 |
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#define | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 |
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#define | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 |
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#define | PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 |
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#define | SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 |
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#define | SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK 0x00000002 |
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#define | SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000 |
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#define | SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002 |
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#define | SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 |
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#define | SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 |
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#define | SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 |
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#define | SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 |
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#define | SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 |
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#define | SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 |
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#define | SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 |
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#define | SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 |
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#define | SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 |
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#define | SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 |
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#define | SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 |
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#define | SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 |
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#define | SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 |
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#define | SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 |
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#define | SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 |
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#define | SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F |
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#define | PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 |
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#define | PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a |
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#define | PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b |
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#define | PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c |
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#define | PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d |
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#define | PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e |
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#define | PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f |
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#define | PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 |
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#define | PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 |
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#define | PORT_FEAT_CFG_DCBX_MASK 0x00000100 |
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#define | PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 |
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#define | PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 |
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#define | PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 |
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#define | PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 |
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#define | PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 |
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#define | PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 |
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#define | PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 |
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#define | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 |
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#define | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 |
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#define | PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 |
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#define | PORT_FEATURE_EN_SIZE_MASK 0x0f000000 |
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#define | PORT_FEATURE_EN_SIZE_SHIFT 24 |
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#define | PORT_FEATURE_WOL_ENABLED 0x01000000 |
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#define | PORT_FEATURE_MBA_ENABLED 0x02000000 |
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#define | PORT_FEATURE_MFW_ENABLED 0x04000000 |
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#define | PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 |
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#define | PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 |
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#define | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 |
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#define | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 |
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#define | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000 |
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#define | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000 |
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#define | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 |
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#define | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 |
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#define | PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 |
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#define | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 |
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#define | PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 |
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#define | PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 |
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#define | PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 |
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#define | PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 |
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#define | PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 |
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#define | PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 |
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#define | PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 |
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#define | PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 |
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#define | PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 |
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#define | PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 |
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#define | PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 |
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#define | PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 |
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#define | PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 |
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#define | PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 |
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#define | PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 |
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#define | PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 |
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#define | PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF |
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#define | PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 |
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#define | PORT_FEATURE_MBA_VLAN_EN 0x00010000 |
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#define | PORT_FEATUTE_BOFM_CFGD_EN 0x00020000 |
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#define | PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000 |
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#define | PORT_FEATURE_BOFM_CFGD_VEN 0x00080000 |
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#define | PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe |
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#define | PORT_FEATURE_SMBUS_ADDR_SHIFT 1 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e |
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#define | PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f |
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#define | PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 |
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#define | PORT_FEATURE_FLOW_CONTROL_SHIFT 8 |
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#define | PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 |
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#define | PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 |
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#define | PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 |
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#define | PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 |
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#define | PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 |
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#define | PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 |
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#define | PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 |
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#define | PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 |
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#define | PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 |
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#define | PORT_FEATURE_LINK_SPEED_SHIFT 16 |
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#define | PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 |
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#define | PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000 |
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#define | PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000 |
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#define | PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 |
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#define | PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 |
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#define | PORT_FEATURE_LINK_SPEED_1G 0x00050000 |
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#define | PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 |
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#define | PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 |
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#define | PORT_FEATURE_LINK_SPEED_20G 0x00080000 |
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#define | PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 |
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#define | PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 |
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#define | PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 |
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#define | PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 |
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#define | PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 |
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#define | PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 |
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#define | PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF |
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#define | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 |
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#define | PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 |
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#define | PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 |
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#define | PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 |
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#define | PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000 |
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#define | EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001 |
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#define | FUNC_0 0 |
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#define | FUNC_1 1 |
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#define | FUNC_2 2 |
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#define | FUNC_3 3 |
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#define | FUNC_4 4 |
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#define | FUNC_5 5 |
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#define | FUNC_6 6 |
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#define | FUNC_7 7 |
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#define | E1_FUNC_MAX 2 |
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#define | E1H_FUNC_MAX 8 |
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#define | E2_FUNC_MAX 4 /* per path */ |
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#define | VN_0 0 |
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#define | VN_1 1 |
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#define | VN_2 2 |
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#define | VN_3 3 |
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#define | E1VN_MAX 1 |
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#define | E1HVN_MAX 4 |
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#define | E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ |
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#define | DRV_PULSE_PERIOD_MS 250 |
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#define | FW_ACK_TIME_OUT_MS 5000 |
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#define | FW_ACK_POLL_TIME_MS 1 |
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#define | FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) |
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#define | MFW_TRACE_SIGNATURE 0x54524342 |
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#define | LINK_STATUS_NONE (0<<0) |
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#define | LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
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#define | LINK_STATUS_LINK_UP 0x00000001 |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) |
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#define | LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) |
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#define | LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 |
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#define | LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 |
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#define | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 |
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#define | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 |
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#define | LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 |
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#define | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 |
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#define | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 |
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#define | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 |
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#define | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 |
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#define | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 |
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#define | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 |
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#define | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 |
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#define | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 |
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#define | LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 |
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#define | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 |
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#define | LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 |
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#define | LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 |
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#define | LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) |
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#define | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) |
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#define | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) |
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#define | LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) |
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#define | LINK_STATUS_SERDES_LINK 0x00100000 |
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#define | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 |
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#define | LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 |
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#define | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 |
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#define | LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 |
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#define | LINK_STATUS_PFC_ENABLED 0x20000000 |
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#define | LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 |
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#define | LINK_STATUS_SFP_TX_FAULT 0x80000000 |
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#define | DRV_MSG_CODE_MASK 0xffff0000 |
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#define | DRV_MSG_CODE_LOAD_REQ 0x10000000 |
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#define | DRV_MSG_CODE_LOAD_DONE 0x11000000 |
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#define | DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 |
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#define | DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 |
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#define | DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 |
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#define | DRV_MSG_CODE_UNLOAD_DONE 0x21000000 |
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#define | DRV_MSG_CODE_DCC_OK 0x30000000 |
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#define | DRV_MSG_CODE_DCC_FAILURE 0x31000000 |
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#define | DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 |
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#define | DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 |
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#define | DRV_MSG_CODE_VALIDATE_KEY 0x70000000 |
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#define | DRV_MSG_CODE_GET_CURR_KEY 0x80000000 |
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#define | DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 |
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#define | DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 |
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#define | DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 |
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#define | DRV_MSG_CODE_OEM_OK 0x00010000 |
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#define | DRV_MSG_CODE_OEM_FAILURE 0x00020000 |
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#define | DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000 |
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#define | DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000 |
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#define | DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 |
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#define | REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 |
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#define | DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 |
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#define | REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 |
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#define | DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 |
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#define | REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 |
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#define | REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 |
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#define | REQ_BC_VER_4_MT_SUPPORTED 0x00070201 |
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#define | REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 |
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#define | REQ_BC_VER_4_FCOE_FEATURES 0x00070209 |
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#define | DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 |
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#define | DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 |
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#define | REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 |
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#define | DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 |
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#define | DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 |
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#define | DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 |
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#define | DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 |
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#define | DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 |
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#define | DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 |
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#define | DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 |
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#define | DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 |
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#define | DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 |
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#define | DRV_MSG_CODE_RMMOD 0xdb000000 |
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#define | REQ_BC_VER_4_RMMOD_CMD 0x0007080f |
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#define | DRV_MSG_CODE_SET_MF_BW 0xe0000000 |
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#define | REQ_BC_VER_4_SET_MF_BW 0x00060202 |
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#define | DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 |
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#define | DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 |
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#define | DRV_MSG_CODE_INITIATE_FLR 0x02000000 |
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#define | REQ_BC_VER_4_INITIATE_FLR 0x00070213 |
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#define | BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 |
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#define | BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 |
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#define | BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 |
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#define | BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 |
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#define | DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 |
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#define | DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 |
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#define | DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000 |
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#define | DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff |
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#define | DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000 |
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#define | DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 |
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#define | DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 |
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#define | DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 |
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#define | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 |
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#define | DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a |
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#define | DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 |
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#define | DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 |
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#define | DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 |
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#define | DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003 |
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#define | DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001 |
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#define | DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002 |
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#define | DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003 |
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#define | DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004 |
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#define | DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005 |
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#define | FW_MSG_CODE_MASK 0xffff0000 |
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#define | FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 |
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#define | FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 |
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#define | FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 |
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#define | REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 |
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#define | FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 |
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#define | FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 |
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#define | FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 |
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#define | FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 |
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#define | FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 |
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#define | FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 |
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#define | FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 |
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#define | FW_MSG_CODE_DCC_DONE 0x30100000 |
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#define | FW_MSG_CODE_LLDP_DONE 0x40100000 |
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#define | FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 |
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#define | FW_MSG_CODE_DIAG_REFUSE 0x50200000 |
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#define | FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 |
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#define | FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 |
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#define | FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 |
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#define | FW_MSG_CODE_GET_KEY_DONE 0x80100000 |
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#define | FW_MSG_CODE_NO_KEY 0x80f00000 |
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#define | FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 |
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#define | FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 |
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#define | FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 |
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#define | FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 |
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#define | FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 |
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#define | FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 |
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#define | FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 |
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#define | FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 |
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#define | FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 |
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#define | FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 |
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#define | FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 |
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#define | FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 |
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#define | FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 |
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#define | FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 |
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#define | FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 |
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#define | FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 |
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#define | FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 |
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#define | FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 |
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#define | FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 |
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#define | FW_MSG_CODE_RMMOD_ACK 0xdb100000 |
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#define | FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 |
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#define | FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 |
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#define | FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 |
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#define | FW_MSG_CODE_FLR_ACK 0x02000000 |
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#define | FW_MSG_CODE_FLR_NACK 0x02100000 |
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#define | FW_MSG_CODE_LIC_CHALLENGE 0xff010000 |
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#define | FW_MSG_CODE_LIC_RESPONSE 0xff020000 |
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#define | FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 |
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#define | FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 |
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#define | FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 |
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#define | FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 |
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#define | FW_MSG_CODE_OEM_ACK 0x00010000 |
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#define | DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000 |
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#define | FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000 |
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#define | FW_MSG_SEQ_NUMBER_MASK 0x0000ffff |
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#define | FW_PARAM_INVALID_IMG 0xffffffff |
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#define | DRV_PULSE_SEQ_MASK 0x00007fff |
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#define | DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 |
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#define | DRV_PULSE_ALWAYS_ALIVE 0x00008000 |
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#define | MCP_PULSE_SEQ_MASK 0x00007fff |
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#define | MCP_PULSE_ALWAYS_ALIVE 0x00008000 |
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#define | MCP_EVENT_MASK 0xffff0000 |
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#define | MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 |
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#define | DRV_STATUS_PMF 0x00000001 |
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#define | DRV_STATUS_VF_DISABLED 0x00000002 |
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#define | DRV_STATUS_SET_MF_BW 0x00000004 |
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#define | DRV_STATUS_LINK_EVENT 0x00000008 |
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#define | DRV_STATUS_OEM_EVENT_MASK 0x00000070 |
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#define | DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010 |
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#define | DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020 |
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#define | DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040 |
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#define | DRV_STATUS_OEM_UPDATE_SVID 0x00000080 |
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#define | DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 |
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#define | DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 |
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#define | DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 |
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#define | DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 |
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#define | DRV_STATUS_DCC_RESERVED1 0x00000800 |
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#define | DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 |
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#define | DRV_STATUS_DCC_SET_PRIORITY 0x00002000 |
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#define | DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 |
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#define | DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 |
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#define | DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 |
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#define | DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 |
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#define | DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 |
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#define | DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 |
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#define | DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 |
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#define | DRV_STATUS_DRV_INFO_REQ 0x04000000 |
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#define | DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 |
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#define | VIRT_MAC_SIGN_MASK 0xffff0000 |
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#define | VIRT_MAC_SIGNATURE 0x564d0000 |
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#define | MGMTFW_STATE_WORD_SIZE 110 |
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#define | SHARED_MF_CLP_SET_DEFAULT 0x00000000 |
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#define | SHARED_MF_CLP_EXIT 0x00000001 |
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#define | SHARED_MF_CLP_EXIT_DONE 0x00010000 |
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#define | PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
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#define | PORT_MF_CFG_E1HOV_TAG_SHIFT 0 |
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#define | PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK |
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#define | FUNC_MF_CFG_FUNC_HIDE 0x00000001 |
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#define | FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 |
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#define | FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 |
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#define | FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 |
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#define | FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 |
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#define | FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 |
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#define | FUNC_MF_CFG_PROTOCOL_DEFAULT FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA |
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#define | FUNC_MF_CFG_FUNC_DISABLED 0x00000008 |
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#define | FUNC_MF_CFG_FUNC_DELETED 0x00000010 |
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#define | FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 |
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#define | FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 |
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#define | FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 |
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#define | FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 |
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#define | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 |
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#define | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 |
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#define | FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 |
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#define | FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 |
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#define | FUNC_MF_CFG_MIN_BW_SHIFT 16 |
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#define | FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 |
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#define | FUNC_MF_CFG_MAX_BW_MASK 0xff000000 |
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#define | FUNC_MF_CFG_MAX_BW_SHIFT 24 |
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#define | FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 |
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#define | FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff |
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#define | FUNC_MF_CFG_UPPERMAC_SHIFT 0 |
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#define | FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK |
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#define | FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff |
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#define | FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
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#define | FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 |
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#define | FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK |
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#define | FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 |
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#define | FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 |
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#define | FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff |
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#define | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 |
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#define | FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 |
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#define | FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 |
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#define | FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 |
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#define | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 |
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#define | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 |
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#define | FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF |
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#define | FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 |
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#define | MACP_FUNC_CFG_FLAGS_MASK 0x0000007F |
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#define | MACP_FUNC_CFG_FLAGS_SHIFT 0 |
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#define | MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 |
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#define | MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 |
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#define | MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 |
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#define | MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 |
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#define | MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 |
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#define | MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) |
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#define | MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) |
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#define | MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) |
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#define | MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) |
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#define | MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) |
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#define | MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) |
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#define | SHR_MEM_FORMAT_REV_MASK 0xff000000 |
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#define | SHR_MEM_FORMAT_REV_ID ('A'<<24) |
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#define | SHR_MEM_VALIDITY_PCI_CFG 0x00100000 |
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#define | SHR_MEM_VALIDITY_MB 0x00200000 |
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#define | SHR_MEM_VALIDITY_DEV_INFO 0x00400000 |
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#define | SHR_MEM_VALIDITY_RESERVED 0x00000007 |
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#define | SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 |
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#define | SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 |
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#define | SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 |
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#define | SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 |
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#define | SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 |
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#define | SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 |
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#define | SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 |
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#define | SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 |
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#define | SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 |
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#define | SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 |
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#define | SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) |
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#define | SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) |
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#define | SHMEM_ARRAY_BITPOS(i, eb, fb) |
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#define | SHMEM_ARRAY_GET(a, i, eb, fb) |
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#define | SHMEM_ARRAY_SET(a, i, eb, fb, val) |
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#define | DCBX_MAX_NUM_PRI_PG_ENTRIES 8 |
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#define | DCBX_PRI_PG_BITWIDTH 4 |
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#define | DCBX_PRI_PG_FBITS 8 |
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#define | DCBX_PRI_PG_GET(a, i) SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) |
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#define | DCBX_PRI_PG_SET(a, i, val) SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) |
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#define | DCBX_MAX_NUM_PG_BW_ENTRIES 8 |
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#define | DCBX_BW_PG_BITWIDTH 8 |
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#define | DCBX_PG_BW_GET(a, i) SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) |
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#define | DCBX_PG_BW_SET(a, i, val) SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) |
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#define | DCBX_STRICT_PRI_PG 15 |
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#define | DCBX_MAX_APP_PROTOCOL 16 |
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#define | DCBX_MAX_APP_LOCAL 32 |
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#define | FCOE_APP_IDX 0 |
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#define | ISCSI_APP_IDX 1 |
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#define | PREDEFINED_APP_IDX_MAX 2 |
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#define | REM_CHASSIS_ID_STAT_LEN 4 |
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#define | REM_PORT_ID_STAT_LEN 4 |
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#define | LOCAL_CHASSIS_ID_STAT_LEN 2 |
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#define | LOCAL_PORT_ID_STAT_LEN 2 |
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#define | DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 |
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#define | DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 |
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#define | DCBX_APP_CONFIG_TX_ENABLED 0x00000004 |
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#define | DCBX_ETS_RECO_TX_ENABLED 0x00000008 |
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#define | DCBX_ETS_RECO_VALID 0x00000010 |
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#define | DCBX_ETS_WILLING 0x00000020 |
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#define | DCBX_PFC_WILLING 0x00000040 |
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#define | DCBX_APP_WILLING 0x00000080 |
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#define | DCBX_VERSION_CEE 0x00000100 |
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#define | DCBX_VERSION_IEEE 0x00000200 |
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#define | DCBX_DCBX_ENABLED 0x00000400 |
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#define | DCBX_CEE_VERSION_MASK 0x0000f000 |
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#define | DCBX_CEE_VERSION_SHIFT 12 |
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#define | DCBX_CEE_MAX_VERSION_MASK 0x000f0000 |
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#define | DCBX_CEE_MAX_VERSION_SHIFT 16 |
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#define | DCBX_ETS_TLV_RX 0x00000001 |
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#define | DCBX_PFC_TLV_RX 0x00000002 |
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#define | DCBX_APP_TLV_RX 0x00000004 |
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#define | DCBX_ETS_RX_ERROR 0x00000010 |
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#define | DCBX_PFC_RX_ERROR 0x00000020 |
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#define | DCBX_APP_RX_ERROR 0x00000040 |
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#define | DCBX_ETS_REM_WILLING 0x00000100 |
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#define | DCBX_PFC_REM_WILLING 0x00000200 |
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#define | DCBX_APP_REM_WILLING 0x00000400 |
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#define | DCBX_REMOTE_ETS_RECO_VALID 0x00001000 |
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#define | DCBX_REMOTE_MIB_VALID 0x00002000 |
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#define | DCBX_LOCAL_ETS_ERROR 0x00000001 |
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#define | DCBX_LOCAL_PFC_ERROR 0x00000002 |
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#define | DCBX_LOCAL_APP_ERROR 0x00000004 |
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#define | DCBX_LOCAL_PFC_MISMATCH 0x00000010 |
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#define | DCBX_LOCAL_APP_MISMATCH 0x00000020 |
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#define | DCBX_REMOTE_MIB_ERROR 0x00000040 |
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#define | DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 |
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#define | DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 |
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#define | DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 |
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#define | SHMEM_LINK_CONFIG_SIZE 2 |
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#define | REQ_DUPLEX_PHY0_MASK 0x0000ffff |
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#define | REQ_DUPLEX_PHY0_SHIFT 0 |
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#define | REQ_DUPLEX_PHY1_MASK 0xffff0000 |
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#define | REQ_DUPLEX_PHY1_SHIFT 16 |
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#define | REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff |
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#define | REQ_FLOW_CTRL_PHY0_SHIFT 0 |
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#define | REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 |
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#define | REQ_FLOW_CTRL_PHY1_SHIFT 16 |
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#define | REQ_LINE_SPD_PHY0_MASK 0x0000ffff |
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#define | REQ_LINE_SPD_PHY0_SHIFT 0 |
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#define | REQ_LINE_SPD_PHY1_MASK 0xffff0000 |
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#define | REQ_LINE_SPD_PHY1_SHIFT 16 |
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#define | REQ_FC_AUTO_ADV_MASK 0x0000ffff |
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#define | REQ_FC_AUTO_ADV0_SHIFT 0 |
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#define | NO_LFA_DUE_TO_DCC_MASK 0x00010000 |
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#define | LFA_LINK_FLAP_REASON_OFFSET 0 |
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#define | LFA_LINK_FLAP_REASON_MASK 0x000000ff |
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#define | LFA_LINK_DOWN 0x1 |
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#define | LFA_LOOPBACK_ENABLED 0x2 |
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#define | LFA_DUPLEX_MISMATCH 0x3 |
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#define | LFA_MFW_IS_TOO_OLD 0x4 |
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#define | LFA_LINK_SPEED_MISMATCH 0x5 |
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#define | LFA_FLOW_CTRL_MISMATCH 0x6 |
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#define | LFA_SPEED_CAP_MISMATCH 0x7 |
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#define | LFA_DCC_LFA_DISABLED 0x8 |
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#define | LFA_EEE_MISMATCH 0x9 |
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#define | LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 |
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#define | LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 |
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#define | LINK_FLAP_COUNT_OFFSET 16 |
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#define | LINK_FLAP_COUNT_MASK 0x00ff0000 |
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#define | LFA_FLAGS_MASK 0xff000000 |
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#define | SHMEM_LFA_DONT_CLEAR_STAT (1<<24) |
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#define | DRV_VER_NOT_LOADED 0 |
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#define | DRV_PERS_ETHERNET 0 |
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#define | DRV_PERS_ISCSI 1 |
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#define | DRV_PERS_FCOE 2 |
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#define | MAX_DRV_PERS 3 |
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#define | OEM_I2C_UUID_STR_ADDR 0x9f |
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#define | OEM_I2C_CARD_SKU_STR_ADDR 0x3c |
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#define | OEM_I2C_CARD_FN_STR_ADDR 0x48 |
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#define | OEM_I2C_CARD_NAME_STR_ADDR 0x10e |
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#define | OEM_I2C_UUID_STR_LEN 16 |
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#define | OEM_I2C_CARD_SKU_STR_LEN 12 |
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#define | OEM_I2C_CARD_FN_STR_LEN 12 |
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#define | OEM_I2C_CARD_NAME_STR_LEN 128 |
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#define | OEM_I2C_CARD_VERSION_STR_LEN 36 |
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#define | FC_NPIV_WWPN_SIZE 8 |
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#define | FC_NPIV_WWNN_SIZE 8 |
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#define | MAX_NUMBER_NPIV 64 |
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#define | FIRST_DUMP_VALID (1 << 0) |
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#define | SECOND_DUMP_VALID (1 << 1) |
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#define | ENABLE_ALL_TRIGGERS (0x7fffffff) |
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#define | TRIGGER_MDUMP_ONCE (1 << 31) |
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#define | SHMEM_DCC_SUPPORT_NONE 0x00000000 |
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#define | SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 |
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#define | SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 |
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#define | SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 |
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#define | SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 |
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#define | SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 |
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#define | SHMEM_MF_CFG_ADDR_NONE 0x00000000 |
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#define | SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 |
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#define | SHMEM_DCBX_NEG_RES_NONE 0x00000000 |
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#define | SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 |
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#define | SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 |
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#define | EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 |
|
#define | EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 |
|
#define | EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 |
|
#define | SHMEM_AFEX_VERSION_MASK 0x100f |
|
#define | SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 |
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#define | SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 |
|
#define | DRV_FLAGS_DCB_CONFIGURED 0x0 |
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#define | DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 |
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#define | DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 |
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#define | DRV_FLAGS_PORT_MASK |
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#define | DRV_FLAGS_P0_OFFSET 0 |
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#define | DRV_FLAGS_P1_OFFSET 16 |
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#define | DRV_FLAGS_GET_PORT_OFFSET(_port) |
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#define | DRV_FLAGS_GET_PORT_MASK(_port) |
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#define | DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) |
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#define | SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 |
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#define | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 |
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#define | DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 |
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#define | DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 |
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#define | DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 |
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#define | DRV_FLAGS_MTU_MASK 0xffff0000 |
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#define | DRV_FLAGS_MTU_SHIFT 16 |
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#define | DRV_INFO_CONTROL_VER_MASK 0x000000ff |
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#define | DRV_INFO_CONTROL_VER_SHIFT 0 |
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#define | DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 |
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#define | DRV_INFO_CONTROL_OP_CODE_SHIFT 8 |
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#define | PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ |
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#define | PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 |
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#define | SHMEM_EEE_TIMER_MASK 0x0000ffff |
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#define | SHMEM_EEE_SUPPORTED_MASK 0x000f0000 |
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#define | SHMEM_EEE_SUPPORTED_SHIFT 16 |
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#define | SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 |
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#define | SHMEM_EEE_100M_ADV (1<<0) |
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#define | SHMEM_EEE_1G_ADV (1<<1) |
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#define | SHMEM_EEE_10G_ADV (1<<2) |
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#define | SHMEM_EEE_ADV_STATUS_SHIFT 20 |
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#define | SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 |
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#define | SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 |
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#define | SHMEM_EEE_REQUESTED_BIT 0x10000000 |
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#define | SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 |
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#define | SHMEM_EEE_ACTIVE_BIT 0x40000000 |
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#define | SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 |
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#define | EXTPHY1_TEMP_MASK 0x0000ffff |
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#define | EXTPHY1_TEMP_SHIFT 0 |
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#define | ON_BOARD_TEMP_MASK 0xffff0000 |
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#define | ON_BOARD_TEMP_SHIFT 16 |
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#define | LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 |
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#define | LINK_ATTR_84858 0x00000002 |
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#define | LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 |
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#define | LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 |
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#define | LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 |
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#define | LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 |
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#define | LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 |
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#define | LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */ |
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#define | MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_) |
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#define | STORAGE_BOOT_PROG_MASK 0x000000FF |
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#define | STORAGE_BOOT_PROG_NONE 0x00000000 |
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#define | STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002 |
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#define | STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002 |
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#define | STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004 |
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#define | STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008 |
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#define | STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008 |
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#define | STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010 |
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#define | STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020 |
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#define | STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040 |
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#define | STORAGE_BOOT_PROG_COMPLETED 0x00000080 |
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#define | SRIOV_SWITCH_MODE_NONE 0x0 |
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#define | SRIOV_SWITCH_MODE_VEB 0x1 |
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#define | SRIOV_SWITCH_MODE_VEPA 0x2 |
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#define | OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */ |
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#define | OS_DRIVER_STATE_LOADING 1 /* transition state */ |
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#define | OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */ |
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#define | OS_DRIVER_STATE_ACTIVE 3 /* installed and active */ |
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#define | MAC_STX_IDX_MAX 2 |
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#define | VICSTATST_UIF_INDEX 2 |
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#define | BCM_5710_FW_MAJOR_VERSION 7 |
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#define | BCM_5710_FW_MINOR_VERSION 13 |
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#define | BCM_5710_FW_REVISION_VERSION 1 |
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#define | BCM_5710_FW_ENGINEERING_VERSION 0 |
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#define | BCM_5710_FW_COMPILE_FLAGS 1 |
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#define | CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) /* BitField agg_vars1Various aggregative variables The state of the connection */ |
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#define | CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) /* BitField agg_vars1Various aggregative variables ULP Rx SE counter flag enable */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) /* BitField agg_vars1Various aggregative variables ULP Rx invalidate counter flag enable */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) /* BitField agg_vars1Various aggregative variables Aux 4 counter flag */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) /* BitField agg_vars1Various aggregative variables The connection QOS */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) /* BitField agg_vars1Various aggregative variables Enable decision rule for fin_received_cf */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 1 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 2 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 3 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 4 */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ, 3-GT, 4-GE, 5-LS, 6-LE */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23 |
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#define | CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ |
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#define | CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28 |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */ |
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#define | __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30 |
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#define | DMAE_CMD_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ |
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#define | DMAE_CMD_SRC_SHIFT 0 |
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#define | DMAE_CMD_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ |
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#define | DMAE_CMD_DST_SHIFT 1 |
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#define | DMAE_CMD_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ |
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#define | DMAE_CMD_C_DST_SHIFT 3 |
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#define | DMAE_CMD_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ |
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#define | DMAE_CMD_C_TYPE_ENABLE_SHIFT 4 |
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#define | DMAE_CMD_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ |
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#define | DMAE_CMD_C_TYPE_CRC_ENABLE_SHIFT 5 |
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#define | DMAE_CMD_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ |
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#define | DMAE_CMD_C_TYPE_CRC_OFFSET_SHIFT 6 |
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#define | DMAE_CMD_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ |
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#define | DMAE_CMD_ENDIANITY_SHIFT 9 |
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#define | DMAE_CMD_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ |
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#define | DMAE_CMD_PORT_SHIFT 11 |
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#define | DMAE_CMD_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ |
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#define | DMAE_CMD_CRC_RESET_SHIFT 12 |
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#define | DMAE_CMD_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ |
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#define | DMAE_CMD_SRC_RESET_SHIFT 13 |
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#define | DMAE_CMD_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ |
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#define | DMAE_CMD_DST_RESET_SHIFT 14 |
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#define | DMAE_CMD_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ |
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#define | DMAE_CMD_E1HVN_SHIFT 15 |
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#define | DMAE_CMD_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ |
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#define | DMAE_CMD_DST_VN_SHIFT 17 |
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#define | DMAE_CMD_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ |
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#define | DMAE_CMD_C_FUNC_SHIFT 19 |
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#define | DMAE_CMD_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ |
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#define | DMAE_CMD_ERR_POLICY_SHIFT 20 |
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#define | DMAE_CMD_RESERVED0 (0x3FF<<22) /* BitField opcode */ |
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#define | DMAE_CMD_RESERVED0_SHIFT 22 |
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#define | DOORBELL_HDR_T_RX (0x1<<0) /* BitField data 1 for rx doorbell, 0 for tx doorbell */ |
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#define | DOORBELL_HDR_T_RX_SHIFT 0 |
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#define | DOORBELL_HDR_T_DB_TYPE (0x1<<1) /* BitField data 0 for normal doorbell, 1 for advertise wnd doorbell */ |
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#define | DOORBELL_HDR_T_DB_TYPE_SHIFT 1 |
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#define | DOORBELL_HDR_T_DPM_SIZE (0x3<<2) /* BitField data rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ |
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#define | DOORBELL_HDR_T_DPM_SIZE_SHIFT 2 |
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#define | DOORBELL_HDR_T_CONN_TYPE (0xF<<4) /* BitField data connection type */ |
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#define | DOORBELL_HDR_T_CONN_TYPE_SHIFT 4 |
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#define | IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ |
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#define | IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 |
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#define | IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ |
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#define | IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 |
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#define | IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ |
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#define | IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 |
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#define | IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ |
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#define | IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 |
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#define | IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ |
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#define | IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 |
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#define | IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ |
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#define | IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 |
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#define | IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_SB_INDEX_SHIFT 0 |
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#define | IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_RESERVED0_SHIFT 20 |
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#define | IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ |
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#define | IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 |
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#define | IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_BUPDATE_SHIFT 24 |
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#define | IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ |
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#define | IGU_REGULAR_ENABLE_INT_SHIFT 25 |
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#define | IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_RESERVED_1_SHIFT 27 |
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#define | IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 |
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#define | IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_CLEANUP_SET_SHIFT 30 |
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#define | IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ |
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#define | IGU_REGULAR_BCLEANUP_SHIFT 31 |
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#define | IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ |
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#define | IGU_CTRL_REG_ADDRESS_SHIFT 0 |
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#define | IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ |
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#define | IGU_CTRL_REG_FID_SHIFT 12 |
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#define | IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ |
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#define | IGU_CTRL_REG_RESERVED_SHIFT 19 |
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#define | IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ |
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#define | IGU_CTRL_REG_TYPE_SHIFT 20 |
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#define | IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ |
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#define | IGU_CTRL_REG_UNUSED_SHIFT 21 |
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#define | PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ |
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#define | PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 |
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#define | PARSING_FLAGS_INNER_VLAN_EXIST (0x1<<1) /* BitField flagscontext flags 0 or 1 */ |
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#define | PARSING_FLAGS_INNER_VLAN_EXIST_SHIFT 1 |
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#define | PARSING_FLAGS_OUTER_VLAN_EXIST (0x1<<2) /* BitField flagscontext flags 0 or 1 */ |
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#define | PARSING_FLAGS_OUTER_VLAN_EXIST_SHIFT 2 |
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#define | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ |
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#define | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 |
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#define | PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ |
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#define | PARSING_FLAGS_IP_OPTIONS_SHIFT 5 |
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#define | PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ |
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#define | PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 |
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#define | PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ |
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#define | PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 |
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#define | PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ |
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#define | PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 |
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#define | PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ |
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#define | PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 |
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#define | PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ |
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#define | PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 |
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#define | PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ |
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#define | PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 |
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#define | PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ |
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#define | PARSING_FLAGS_LLC_SNAP_SHIFT 13 |
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#define | PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ |
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#define | PARSING_FLAGS_RESERVED0_SHIFT 14 |
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#define | SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ |
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#define | SDM_OP_GEN_COMP_PARAM_SHIFT 0 |
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#define | SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ |
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#define | SDM_OP_GEN_COMP_TYPE_SHIFT 5 |
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#define | SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ |
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#define | SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 |
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#define | SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ |
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#define | SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 |
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#define | SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ |
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#define | SDM_OP_GEN_RESERVED_SHIFT 17 |
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#define | __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ |
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#define | __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 |
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#define | TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ |
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#define | TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 |
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#define | __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ |
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#define | __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ |
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#define | TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ |
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#define | TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ |
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#define | TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52 (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52_SHIFT 2 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN_SHIFT 6 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE_SHIFT 10 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55 (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55_SHIFT 11 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN_SHIFT 12 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN_SHIFT 13 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56 (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56_SHIFT 14 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57 (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57_SHIFT 16 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */ |
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#define | __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */ |
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#define | TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 |
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#define | XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 2 */ |
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#define | XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0 |
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#define | XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 3 */ |
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#define | XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux7_cf */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux8_cf */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux9_cf */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux10_cf */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 6 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 7 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 5 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 9 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 10 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 11 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 12 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 13 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 14 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 15 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 16 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 17 */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 |
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#define | XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ |
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#define | XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* BitField tcp_agg_vars6Various aggregative variables This flag is set if the Force ACK count is set by the TSTORM. On QM output it is cleared. */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* BitField tcp_agg_vars6Various aggregative variables Indicates that the connection is in autostop mode */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* BitField tcp_agg_vars6Various aggregative variables This bit uses like a one shot that the TSTORM fires and the XSTORM arms. Used to allow a single TS update for each transmission */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* BitField tcp_agg_vars6Various aggregative variables This bit is set by the TSTORM when need to cancel precious fast retransmit */ |
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#define | __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 |
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#define | XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 2 */ |
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#define | XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0 |
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#define | XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 3 */ |
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#define | XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux7_cf */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux8_cf */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux9_cf */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux10_cf */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 6 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 7 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 5 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 9 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 10 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 11 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 12 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 13 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 14 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 15 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 16 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 17 */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 |
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#define | XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ |
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#define | XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* BitField tcp_agg_vars6Various aggregative variables This flag is set if the Force ACK count is set by the TSTORM. On QM output it is cleared. */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* BitField tcp_agg_vars6Various aggregative variables Indicates that the connection is in autostop mode */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* BitField tcp_agg_vars6Various aggregative variables This bit uses like a one shot that the TSTORM fires and the XSTORM arms. Used to allow a single TS update for each transmission */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* BitField tcp_agg_vars6Various aggregative variables This bit is set by the TSTORM when need to cancel precious fast retransmit */ |
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#define | __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 |
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#define | CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ |
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#define | CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 |
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#define | CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ |
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#define | CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 |
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#define | CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ |
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#define | CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 |
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#define | CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ |
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#define | CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 |
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#define | CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ |
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#define | CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 |
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#define | CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ |
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#define | CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 |
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#define | CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ |
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#define | CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 |
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#define | CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ |
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#define | CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 |
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#define | CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ |
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#define | CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 |
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#define | CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ |
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#define | CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 |
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#define | CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ |
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#define | CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 |
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#define | CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ |
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#define | CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 |
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#define | CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ |
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#define | CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 |
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#define | CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ |
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#define | CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 |
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#define | CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ |
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#define | CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 |
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#define | CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ |
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#define | CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 |
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#define | CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ |
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#define | CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 |
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#define | ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ |
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#define | ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 |
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#define | ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ |
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#define | ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 |
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#define | ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR/IMAC_VNI (use enum classify_rule) */ |
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#define | ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 |
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#define | ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ |
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#define | ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 |
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#define | ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ |
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#define | ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 |
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#define | ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ |
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#define | ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 |
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#define | ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ |
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#define | ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 |
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#define | ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ |
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#define | ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 |
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#define | ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ |
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#define | ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 |
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#define | ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ |
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#define | ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 |
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#define | ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ |
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#define | ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 |
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#define | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ |
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#define | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 |
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#define | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ |
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#define | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 |
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#define | ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6) /* BitField type_error_flags Is a PTP Timesync Packet */ |
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#define | ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6 |
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#define | ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7) /* BitField type_error_flags */ |
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#define | ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7 |
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#define | ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ |
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#define | ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 |
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#define | ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ |
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#define | ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 |
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#define | ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ |
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#define | ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 |
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#define | ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ |
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#define | ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 |
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#define | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ |
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#define | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 |
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#define | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ |
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#define | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 |
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#define | ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ |
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#define | ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 |
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#define | ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ |
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#define | ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 |
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#define | ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ |
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#define | ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 |
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#define | ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ |
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#define | ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 |
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#define | ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ |
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#define | ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 |
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#define | ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ |
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#define | ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 |
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#define | ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ |
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#define | ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 |
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#define | ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ |
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#define | ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 |
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#define | ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ |
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#define | ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 |
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#define | ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ |
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#define | ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 |
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#define | ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ |
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#define | ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 |
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#define | ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ |
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#define | ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0 |
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#define | ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ |
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#define | ETH_TUNNEL_DATA_RESERVED_SHIFT 1 |
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#define | ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ |
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#define | ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 |
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#define | ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ |
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#define | ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 |
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#define | ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ |
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#define | ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 |
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#define | ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ |
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#define | ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tuple capability */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for TCP */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for UDP */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for VXLAN Tunnels */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tuple capability */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for TCP */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for UDP */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for VXLAN Tunnels */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8) /* BitField capabilitiesFunction RSS capabilities configuration of Tunnel Inner Headers capability. */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9 |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10) /* BitField capabilitiesFunction RSS capabilities */ |
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#define | ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10 |
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#define | COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ |
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#define | COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 |
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#define | COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ |
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#define | COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 |
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#define | COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ |
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#define | COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 |
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#define | COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ |
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#define | COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 |
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#define | COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ |
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#define | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 |
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#define | SPE_HDR_T_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ |
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#define | SPE_HDR_T_CID_SHIFT 0 |
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#define | SPE_HDR_T_CMD_ID (0xFFUL<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ |
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#define | SPE_HDR_T_CMD_ID_SHIFT 24 |
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#define | SPE_HDR_T_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ |
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#define | SPE_HDR_T_CONN_TYPE_SHIFT 0 |
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#define | SPE_HDR_T_FUNCTION_ID (0xFF<<8) /* BitField type */ |
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#define | SPE_HDR_T_FUNCTION_ID_SHIFT 8 |
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#define | ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ |
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#define | ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 |
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#define | ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ |
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#define | ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 |
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#define | ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ |
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#define | ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 |
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#define | ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ |
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#define | ETH_TX_BD_FLAGS_START_BD_SHIFT 4 |
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#define | ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ |
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#define | ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 |
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#define | ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ |
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#define | ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 |
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#define | ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ |
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#define | ETH_TX_BD_FLAGS_IPV6_SHIFT 7 |
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#define | ETH_TX_START_BD_HDR_NBDS (0x7<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ |
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#define | ETH_TX_START_BD_HDR_NBDS_SHIFT 0 |
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#define | ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3) /* BitField general_data If set, do not add any additional tags to the packet including MF Tags, Default VLAN or VLAN for the sake of DCB */ |
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#define | ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3 |
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#define | ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ |
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#define | ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 |
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#define | ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ |
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#define | ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 |
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#define | ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ |
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#define | ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 |
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#define | ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ |
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#define | ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 |
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#define | ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ |
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#define | ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 |
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#define | ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ |
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#define | ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 |
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#define | ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ |
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#define | ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 |
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#define | ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ |
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#define | ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 |
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#define | ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ |
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#define | ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 |
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#define | ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ |
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#define | ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 |
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#define | ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ |
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#define | ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 |
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#define | ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ |
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#define | ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 |
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#define | ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ |
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#define | ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 |
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#define | ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ |
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#define | ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 |
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#define | ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ |
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#define | ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 |
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#define | ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ |
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#define | ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 |
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#define | ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ |
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#define | ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 |
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#define | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ |
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#define | ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 |
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#define | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ |
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#define | ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 |
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#define | ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ |
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#define | ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 |
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#define | ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ |
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#define | ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 |
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#define | ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ |
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#define | ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 |
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#define | ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ |
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#define | ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 |
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#define | ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ |
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#define | ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 |
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#define | ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ |
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#define | ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 |
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#define | ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ |
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#define | ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 |
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#define | ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ |
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#define | ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 |
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#define | ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ |
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#define | ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 |
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#define | ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ |
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#define | ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 |
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#define | ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0) /* BitField bd_type Type of bd (use enum eth_2nd_parse_bd_type) */ |
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#define | ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0 |
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#define | ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4) /* BitField bd_type */ |
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#define | ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4 |
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#define | ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ |
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#define | ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 |
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#define | ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ |
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#define | ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 |
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#define | ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ |
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#define | ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 |
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#define | ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ |
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#define | ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 |
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#define | ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ |
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#define | ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 |
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#define | ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ |
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#define | ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 |
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#define | ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ |
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#define | ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 |
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#define | ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ |
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#define | ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 |
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#define | MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ |
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#define | MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 |
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#define | MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ |
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#define | MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 |
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#define | MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ |
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#define | MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 |
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#define | MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ |
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#define | MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 |
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#define | MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ |
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#define | MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 |
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#define | MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ |
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#define | MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ |
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#define | TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 |
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#define | __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ |
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#define | __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 |
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#define | FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) /* BitField flags */ |
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#define | FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 |
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#define | FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) /* BitField flags */ |
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#define | FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 |
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#define | FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) /* BitField flags */ |
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#define | FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 |
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#define | FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) /* BitField flags */ |
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#define | FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 |
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#define | FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) /* BitField flags */ |
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#define | FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 |
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#define | FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) /* BitField flags */ |
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#define | FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 |
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#define | FCOE_KCQE_RESERVED0 (0x7<<0) /* BitField flags */ |
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#define | FCOE_KCQE_RESERVED0_SHIFT 0 |
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#define | FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */ |
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#define | FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 |
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#define | FCOE_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI,FCoE) */ |
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#define | FCOE_KCQE_LAYER_CODE_SHIFT 4 |
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#define | FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */ |
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#define | FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 |
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#define | FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */ |
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#define | FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 |
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#define | FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5) */ |
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#define | FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 |
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#define | FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */ |
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#define | FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 |
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#define | FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) /* BitField flags log of page size value */ |
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#define | FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 |
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#define | FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) /* BitField flags */ |
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#define | FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 |
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#define | FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED (0x1<<7) /* BitField flags Special MF mode where classification failure indication from HW is allowed */ |
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#define | FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED_SHIFT 7 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) /* BitField vlan_tag Vlan id */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) /* BitField vlan_tag Canonical format indicator */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) /* BitField vlan_tag Vlan priority */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) /* BitField flags Class 2 valid, received during PLOGI */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) /* BitField flags ACK_0 capability supporting by target, received furing PLOGI */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) /* BitField flags Is inner vlan exist */ |
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#define | FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 |
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#define | FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) /* BitField vlan_tagVlan tag Vlan id */ |
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#define | FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 |
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#define | FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) /* BitField vlan_tagVlan tag Canonical format indicator */ |
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#define | FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 |
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#define | FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) /* BitField vlan_tagVlan tag Vlan priority */ |
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#define | FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 |
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#define | FCOE_S_STAT_CTX_ACTIVE (0x1<<0) /* BitField flags Active Sequence indication (0 - not avtive; 1 - active) */ |
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#define | FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 |
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#define | FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) /* BitField flags Abort Sequence requested indication */ |
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#define | FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 |
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#define | FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) /* BitField flags ABTS (on Sequence) protocol complete indication (0 - not completed; 1 -completed by Recipient) */ |
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#define | FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 |
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#define | FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) /* BitField flags E_D_TOV timeout indication */ |
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#define | FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 |
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#define | FCOE_S_STAT_CTX_P_RJT (0x1<<4) /* BitField flags P_RJT transmitted indication */ |
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#define | FCOE_S_STAT_CTX_P_RJT_SHIFT 4 |
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#define | FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) /* BitField flags ACK (EOFt) transmitted indication (0 - not tranmitted; 1 - transmitted) */ |
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#define | FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 |
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#define | FCOE_S_STAT_CTX_RSRV1 (0x3<<6) /* BitField flags */ |
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#define | FCOE_S_STAT_CTX_RSRV1_SHIFT 6 |
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#define | FCOE_SQE_TASK_ID (0x7FFF<<0) /* BitField wqe The task ID (OX_ID) to be processed */ |
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#define | FCOE_SQE_TASK_ID_SHIFT 0 |
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#define | FCOE_SQE_TOGGLE_BIT (0x1<<15) /* BitField wqe Toggle bit updated by the driver */ |
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#define | FCOE_SQE_TOGGLE_BIT_SHIFT 15 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) /* BitField init_flags Task type - Write / Read / Middle / Unsolicited / ABTS / Cleanup */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) /* BitField init_flags Tape/Disk device indication */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) /* BitField init_flags Class 3/2 indication */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) /* BitField init_flags Num of cached sge (0 - not cached sge) */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) /* BitField init_flags Support REC_TOV flag, for FW use only */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write Indication of TX valid task */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write The TX state of the task */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write TX Sequence initiative indication */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6 |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write Compelted full tranmission of this task */ |
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#define | FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7 |
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#define | FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) /* BitField init_flags The CID of the connection (used by the CHIP) */ |
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#define | FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0 |
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#define | FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) /* BitField init_flags */ |
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#define | FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) /* BitField rx_flags */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) /* BitField rx_flags The number of RQ WQEs that were consumed (for sense data only) */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) /* BitField rx_flags Confirmation request indication */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) /* BitField rx_flags The RX state of the task */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) /* BitField rx_flags Indication on expecting to receive the first frame from target */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) /* BitField rx_flags RX Sequence initiative indication */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) /* BitField rx_flags */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14 |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) /* BitField rx_flags Indication of RX valid task */ |
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#define | FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15 |
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#define | FCOE_XFRQE_TASK_ID (0x7FFF<<0) /* BitField wqe The task ID (OX_ID) to be processed */ |
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#define | FCOE_XFRQE_TASK_ID_SHIFT 0 |
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#define | FCOE_XFRQE_TOGGLE_BIT (0x1<<15) /* BitField wqe Toggle bit updated by the driver */ |
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#define | FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 |
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#define | FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) /* BitField fields */ |
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#define | FCOE_IDX16_FIELDS_IDX_SHIFT 0 |
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#define | FCOE_IDX16_FIELDS_MSB (0x1<<15) /* BitField fields */ |
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#define | FCOE_IDX16_FIELDS_MSB_SHIFT 15 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) /* BitField flags The current queue in process */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) /* BitField flags Middle of Sequence indication */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3) /* BitField flags Indicates whether the SQ is blocked since we are in the middle of ABTS/Cleanup procedure */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) /* BitField flags REC support */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) /* BitField flags SQ toggle bit */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) /* BitField flags XFRQ toggle bit */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7) /* BitField flags Are we using VNTag inner vlan - in this case we have to read it on every VNTag version change */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE (0x1<<0) /* BitField flags CONFQ toggle bit */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE_SHIFT 0 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG (0x1<<1) /* BitField flags Is any inner vlan exist */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG_SHIFT 1 |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED (0x3F<<2) /* BitField flags */ |
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#define | XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED_SHIFT 2 |
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#define | XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY (0x7<<0) /* BitField vlan_conf Original inner vlan priority */ |
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#define | XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY_SHIFT 0 |
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#define | XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3) /* BitField vlan_conf Original inner vlan flag */ |
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#define | XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3 |
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#define | XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY (0x7<<4) /* BitField vlan_conf Original outer vlan priority */ |
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#define | XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY_SHIFT 4 |
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#define | XSTORM_FCOE_VLAN_CONF_RESERVED (0x1<<7) /* BitField vlan_conf */ |
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#define | XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 7 |
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#define | FCOE_VLAN_FIELDS_VID (0xFFF<<0) /* BitField fields */ |
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#define | FCOE_VLAN_FIELDS_VID_SHIFT 0 |
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#define | FCOE_VLAN_FIELDS_CLI (0x1<<12) /* BitField fields */ |
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#define | FCOE_VLAN_FIELDS_CLI_SHIFT 12 |
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#define | FCOE_VLAN_FIELDS_PRI (0x7<<13) /* BitField fields */ |
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#define | FCOE_VLAN_FIELDS_PRI_SHIFT 13 |
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#define | TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) /* BitField flags */ |
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#define | TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0 |
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#define | TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN (0x1<<12) /* BitField flags */ |
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#define | TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN_SHIFT 12 |
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#define | TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) /* BitField flags */ |
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#define | TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13 |
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#define | TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) /* BitField flags */ |
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#define | TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14 |
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#define | ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) /* BitField place_db_bitfield_1place_db_bitfield_1 Number of bytes remaining in PDU payload */ |
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#define | USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 |
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#define | USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) /* BitField place_db_bitfield_1place_db_bitfield_1 Temp task context - determines the CQ index for CQE placement */ |
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#define | USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 |
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#define | USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) /* BitField place_db_bitfield_2place_db_bitfield_2 Bytes to truncate from the payload. */ |
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#define | USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 |
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#define | USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) /* BitField place_db_bitfield_2place_db_bitfield_2 Sge index on host */ |
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#define | USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 |
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#define | USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) /* BitField nalNon aligned db Number of bytes remaining in local SGEs */ |
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#define | USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 |
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#define | USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24) /* BitField nalNon aligned db Number of digest bytes not yet processed */ |
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#define | USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24 |
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#define | USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) /* BitField negotiated_rx */ |
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#define | USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 |
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#define | USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) /* BitField negotiated_rx */ |
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#define | USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 |
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#define | USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) /* BitField negotiated_rx_and_flags Negotiated maximum length of sequence */ |
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#define | USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 |
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#define | USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) /* BitField negotiated_rx_and_flags Marks that unvalid CQE was already posted or PDU header was cachaed in RAM */ |
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#define | USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 |
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#define | USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) /* BitField negotiated_rx_and_flags Header digest support enable */ |
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#define | USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 |
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#define | USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) /* BitField negotiated_rx_and_flags Data digest support enable */ |
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#define | USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 |
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#define | USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) /* BitField negotiated_rx_and_flags */ |
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#define | USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 |
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#define | USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) /* BitField negotiated_rx_and_flags temp task context */ |
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#define | USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 |
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#define | USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) /* BitField negotiated_rx_and_flags Task type: 0 = slow-path (non-RW) 1 = read 2 = write */ |
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#define | USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 |
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#define | USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) /* BitField negotiated_rx_and_flags Set if all data is acked */ |
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#define | USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0) /* BitField flags1various state flags 20b only, Smoothed Rount Trip Time */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) /* BitField flags1various state flags PAWS asserted as invalid in KA flow */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) /* BitField flags1various state flags Timestamps supported on this connection */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) /* BitField flags1various state flags */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) /* BitField flags1various state flags stop receiving rx payload */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) /* BitField flags1various state flags Keep Alive enabled */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) /* BitField flags1various state flags First Retransmition Timout Estimation */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) /* BitField flags1various state flags per connection flag, signals whether to check if rt count exceeds max_seg_retransmit */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) /* BitField flags1various state flags last isle ends with FIN. FIN is counted as 1 byte for isle end sequence */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0) /* BitField flags2various state flags 20b only, Round Trip Time variation */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) /* BitField flags2various state flags */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) /* BitField flags2various state flags per GOS flags, but duplicated for each context */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) /* BitField flags2various state flags keep alive packet was sent */ |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) /* BitField flags2various state flags persist packet was sent */ |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) /* BitField flags2various state flags determines wheather or not to update l2 statistics */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) /* BitField flags2various state flags determines wheather or not to update l4 statistics */ |
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#define | TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) /* BitField flags2various state flags possible blind-in-window RST attack detected */ |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30 |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) /* BitField flags2various state flags possible blind-in-window SYN attack detected */ |
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#define | __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31 |
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#define | ISCSI_TERM_VARS_TCP_STATE (0xF<<0) /* BitField BitMap tcp state for the termination process */ |
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#define | ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 |
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#define | ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) /* BitField BitMap fin received sticky bit */ |
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#define | ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 |
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#define | ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) /* BitField BitMap ack on fin received stick bit */ |
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#define | ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 |
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#define | ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) /* BitField BitMap termination on chip ( option2 ) */ |
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#define | ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 |
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#define | ISCSI_TERM_VARS_RSRV (0x1<<7) /* BitField BitMap */ |
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#define | ISCSI_TERM_VARS_RSRV_SHIFT 7 |
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#define | XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) /* BitField priority_flow_label used in PBF Header Builder Command */ |
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#define | XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0 |
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#define | XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) /* BitField priority_flow_label used in PBF Header Builder Command */ |
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#define | XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20 |
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#define | XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) /* BitField priority_flow_label */ |
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#define | XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6 |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) /* BitField flags */ |
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#define | XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7 |
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#define | ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */ |
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#define | ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 |
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#define | ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */ |
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#define | ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 |
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#define | CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ |
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#define | CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 |
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#define | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ |
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#define | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 |
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#define | CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ |
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#define | CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 |
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#define | CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ |
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#define | CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 |
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#define | __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ |
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#define | __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 |
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#define | FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ |
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#define | FW_VERSION_OPTIMIZED_SHIFT 0 |
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#define | FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ |
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#define | FW_VERSION_BIG_ENDIEN_SHIFT 1 |
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#define | FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */ |
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#define | FW_VERSION_CHIP_VERSION_SHIFT 2 |
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#define | __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ |
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#define | __FW_VERSION_RESERVED_SHIFT 4 |
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#define | PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ |
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#define | PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 |
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#define | PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ |
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#define | PRAM_FW_VERSION_STORM_ID_SHIFT 1 |
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#define | PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ |
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#define | PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 |
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#define | PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */ |
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#define | PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 |
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#define | __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ |
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#define | __PRAM_FW_VERSION_RESERVED0_SHIFT 6 |
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#define | TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED (0x1<<0) /* BitField flags error in searcher configuration */ |
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#define | TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED_SHIFT 0 |
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#define | TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE (0x1<<1) /* BitField flags license errors */ |
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#define | TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE_SHIFT 1 |
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#define | TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0 (0x3FFFFFFF<<2) /* BitField flags */ |
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#define | TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 2 |
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#define | TOE_RX_CQE_OOO_PARAMS_NBYTES (0xFFFFFF<<0) /* BitField ooo_paramsdata params for OOO cqe connection nbytes */ |
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#define | TOE_RX_CQE_OOO_PARAMS_NBYTES_SHIFT 0 |
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#define | TOE_RX_CQE_OOO_PARAMS_ISLE_NUM (0xFF<<24) /* BitField ooo_paramsdata params for OOO cqe isle number for OOO completions */ |
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#define | TOE_RX_CQE_OOO_PARAMS_ISLE_NUM_SHIFT 24 |
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#define | TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES (0xFFFFFFFF<<0) /* BitField in_order_paramsdata params for in order cqe connection nbytes */ |
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#define | TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES_SHIFT 0 |
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#define | TOE_RX_CQE_CID (0xFFFFFF<<0) /* BitField params1completion cid and opcode connection id */ |
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#define | TOE_RX_CQE_CID_SHIFT 0 |
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#define | TOE_RX_CQE_COMPLETION_OPCODE (0xFF<<24) /* BitField params1completion cid and opcode completion opcode - use enum toe_rx_cqe_type or toe_rss_update_opcode */ |
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#define | TOE_RX_CQE_COMPLETION_OPCODE_SHIFT 24 |
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#define | TOE_TX_CQE_CID (0xFFFFFF<<0) /* BitField paramscompletion cid and opcode connection id */ |
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#define | TOE_TX_CQE_CID_SHIFT 0 |
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#define | TOE_TX_CQE_COMPLETION_OPCODE (0xFF<<24) /* BitField paramscompletion cid and opcode completion opcode (use enum toe_tx_cqe_type) */ |
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#define | TOE_TX_CQE_COMPLETION_OPCODE_SHIFT 24 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED (0x1<<0) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED_SHIFT 0 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED (0x1<<1) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED_SHIFT 1 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED (0x1<<2) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 2 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED (0x1<<3) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED_SHIFT 3 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED (0x1<<4) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED_SHIFT 4 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED (0x1<<5) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 5 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED (0x1<<6) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED_SHIFT 6 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED (0x1<<7) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED_SHIFT 7 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED (0x1<<8) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED_SHIFT 8 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED (0x1<<9) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED_SHIFT 9 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED (0x1<<10) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED_SHIFT 10 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED (0x1<<11) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED_SHIFT 11 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED (0x1<<12) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED_SHIFT 12 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED (0x1<<13) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED_SHIFT 13 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED (0x1<<14) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED_SHIFT 14 |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED (0x1<<15) /* BitField changed_fieldsbitmap for indicating changed fields */ |
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#define | TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 15 |
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