63#define BLOCK_OPS_IDX(block, stage, end) \
64 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
219#define ECORE_PORT2_MODE_NUM_VNICS 4
225#define ECORE_TOE_ACK_Q 6
226#define ECORE_ISCSI_Q 9
227#define ECORE_ISCSI_ACK_Q 11
228#define ECORE_FCOE_Q 10
231#define ECORE_PORT4_MODE_NUM_VNICS 2
234#define ECORE_E3B0_PORT1_COS_OFFSET 3
237#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\
238 (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
239#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\
240 (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
241#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\
242 (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
245#define ECORE_PF_Q_NUM(q_num, port, vnic)\
246 ((((port) << 1) | (vnic)) * 16 + (q_num))
256 if (curr_cos != new_cos) {
258 uint32_t
reg_addr, reg_bit_map, vnic;
270 for (vnic = 0; vnic < num_vnics; vnic++) {
273 uint32_t q_bit_map = 1 << (pf_q_num & 0x1f);
293 q_bit_map = 1 << (2 * (pf_q_num & 0xf));
294 reg_bit_map = new_cos ?
295 (reg_bit_map | q_bit_map) :
296 (reg_bit_map & (~q_bit_map));
342#define BITS_TO_BYTES(x) ((x)/8)
347#define DEF_MIN_RATE 100
350#define RS_PERIODIC_TIMEOUT_USEC 400
356#define QM_ARB_BYTES 160000
365#define MIN_ABOVE_THRESH 32768
371#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
375#define SAFC_TIMEOUT_USEC 52
381 uint32_t r_param,
struct cmng_init *ram_data)
435 uint32_t r_param,
struct cmng_init *ram_data)
437 uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
470 if (vnicWeightSum > 0) {
493 uint32_t r_param,
struct cmng_init *ram_data)
496 uint32_t cosWeightSum = 0;
503 if (cosWeightSum > 0) {
562#define BLOCK_OPS_IDX(block, stage, end) \
563 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
567#define INITOP_CLEAR 1
585#define ILT_CLIENT_SKIP_INIT 0x1
586#define ILT_CLIENT_SKIP_MEM 0x2
593#define ILT_CLIENT_CDU 0
594#define ILT_CLIENT_QM 1
595#define ILT_CLIENT_SRC 2
596#define ILT_CLIENT_TM 3
610#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
612 block##_REG_##block##_PRTY_MASK, \
613 block##_REG_##block##_PRTY_STS_CLR, \
614 en_mask, {m1, m1h, m2, m3}, #block \
617#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
619 block##_REG_##block##_PRTY_MASK_0, \
620 block##_REG_##block##_PRTY_STS_CLR_0, \
621 en_mask, {m1, m1h, m2, m3}, #block"_0" \
624#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
626 block##_REG_##block##_PRTY_MASK_1, \
627 block##_REG_##block##_PRTY_STS_CLR_1, \
628 en_mask, {m1, m1h, m2, m3}, #block"_1" \
674 {0xf, 0xf, 0xf, 0xf},
"UPB"},
677 {0xf, 0xf, 0xf, 0xf},
"XPB"},
715#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
716 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
717 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
718 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
720#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
721 (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
722 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
757 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
786 "for %s to\t\t0x%x\n",
801 uint32_t reg_val, mcp_aeu_bits =
821 "Parity errors in %s: 0x%x\n",
829 if (reg_val & mcp_aeu_bits)
830 ECORE_MSG(sc,
"Parity error in MCP: 0x%x\n",
831 reg_val & mcp_aeu_bits);
#define INIT_MODE_FLAGS(sc)
#define REG_RD(sc, offset)
#define REG_WR(sc, offset, val)
@ LLFC_TRAFFIC_TYPE_ISCSI
#define MISC_AEU_ENABLE_MCP_PRTY_BITS
static const struct @23 ecore_blocks_parity_data[]
#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3)
#define ECORE_PF_Q_NUM(q_num, port, vnic)
#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS
#define SAFC_TIMEOUT_USEC
#define RS_PERIODIC_TIMEOUT_USEC
#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)
#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3)
#define ECORE_E3B0_PORT1_COS_OFFSET
#define ECORE_PORT4_MODE_NUM_VNICS
#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)
static void ecore_init_max(const struct cmng_init_input *input_data, uint32_t r_param, struct cmng_init *ram_data)
static void ecore_init_safc(const struct cmng_init_input *input_data, struct cmng_init *ram_data)
static void ecore_clear_blocks_parity(struct bxe_softc *sc)
#define ECORE_PORT2_MODE_NUM_VNICS
static const struct @24 mcp_attn_ctl_regs[]
#define ECORE_ISCSI_ACK_Q
static void ecore_enable_blocks_parity(struct bxe_softc *sc)
static uint32_t ecore_parity_reg_mask(struct bxe_softc *sc, int idx)
static void ecore_init_fw_wrr(const struct cmng_init_input *input_data, uint32_t r_param, struct cmng_init *ram_data)
#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)
static void ecore_init_max_per_vn(uint16_t vnic_max_rate, struct rate_shaping_vars_per_vn *ram_data)
static void ecore_init_cmng(const struct cmng_init_input *input_data, struct cmng_init *ram_data)
static void ecore_map_q_cos(struct bxe_softc *sc, uint32_t q_num, uint32_t new_cos)
static void ecore_init_min(const struct cmng_init_input *input_data, uint32_t r_param, struct cmng_init *ram_data)
static void ecore_disable_blocks_parity(struct bxe_softc *sc)
#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3)
static void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable)
static void ecore_dcb_config_qm(struct bxe_softc *sc, enum cos_mode mode, struct priority_cos *traffic_cos)
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
#define MISC_REG_AEU_ENABLE4_NIG_1
#define MISC_REG_AEU_AFTER_INVERT_4_MCP
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
#define MISC_REG_AEU_CLR_LATCH_SIGNAL
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
#define USEM_REG_FAST_MEMORY
#define XSEM_REG_FAST_MEMORY
#define TSEM_REG_FAST_MEMORY
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
#define MISC_REG_AEU_ENABLE4_NIG_0
#define PB_REG_PB_PRTY_MASK
#define MISC_REG_AEU_ENABLE4_PXP_0
#define SEM_FAST_REG_PARITY_RST
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0
#define MISC_REG_AEU_ENABLE4_PXP_1
#define CSEM_REG_FAST_MEMORY
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
#define PB_REG_PB_PRTY_STS_CLR
bus_addr_t ecore_dma_addr_t
#define ECORE_MSG(sc, m,...)
#define ECORE_MEMSET(_a, _c, _s)
struct cmng_struct_per_port port
struct rate_shaping_vars_per_port rs_vars
struct safc_struct_per_port safc_vars
struct cmng_flags_per_port flags
struct fairness_vars_per_port fair_vars
struct rate_shaping_vars_per_vn vnic_max_rate[4]
struct fairness_vars_per_vn vnic_min_rate[4]
struct ilt_client_info clients[4]
uint32_t fairness_timeout
uint32_t cos_credit_delta[MAX_COS_NUMBER]
ecore_dma_addr_t page_mapping
uint32_t rs_periodic_timeout
struct rate_shaping_counter vn_counter
struct op_if_phase if_phase
struct op_if_mode if_mode
struct op_arr_write arr_wr