36#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/endian.h>
44#include <sys/malloc.h>
48#include <sys/socket.h>
49#include <sys/sockio.h>
50#include <sys/sysctl.h>
52#include <sys/bitstring.h>
53#include <sys/limits.h>
55#include <sys/taskqueue.h>
56#include <contrib/zlib/zlib.h>
58#include <net/debugnet.h>
60#include <net/if_types.h>
61#include <net/if_arp.h>
62#include <net/ethernet.h>
64#include <net/if_var.h>
65#include <net/if_media.h>
66#include <net/if_vlan_var.h>
69#include <netinet/in.h>
70#include <netinet/ip.h>
71#include <netinet/ip6.h>
72#include <netinet/tcp.h>
73#include <netinet/udp.h>
75#include <dev/pci/pcireg.h>
76#include <dev/pci/pcivar.h>
78#include <machine/atomic.h>
79#include <machine/resource.h>
80#include <machine/endian.h>
81#include <machine/bus.h>
82#include <machine/in_cksum.h>
88#if _BYTE_ORDER == _LITTLE_ENDIAN
92#ifndef __LITTLE_ENDIAN
93#define __LITTLE_ENDIAN
105#undef __LITTLE_ENDIAN
117#define VF_MAC_CREDIT_CNT 0
118#define VF_VLAN_CREDIT_CNT (0)
121#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
124#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
127#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
130#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
137 while (x >>= 1) log++;
140#define ilog2(x) bxe_ilog2(x)
145#define BRCM_VENDORID 0x14e4
146#define QLOGIC_VENDORID 0x1077
147#define PCI_ANY_ID (uint16_t)(~0U)
158#define BCM_PAGE_SHIFT 12
159#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
160#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
161#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
163#if BCM_PAGE_SIZE != 4096
164#error Page sizes other than 4KB are unsupported!
167#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
168#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
169#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
171#define U64_LO(addr) ((uint32_t)(addr))
172#define U64_HI(addr) (0)
174#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
176#define SET_FLAG(value, mask, flag) \
178 (value) &= ~(mask); \
179 (value) |= ((flag) << (mask##_SHIFT)); \
182#define GET_FLAG(value, mask) \
183 (((value) & (mask)) >> (mask##_SHIFT))
185#define GET_FIELD(value, fname) \
186 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
188#define BXE_MAX_SEGMENTS 12
189#define BXE_TSO_MAX_SEGMENTS 32
190#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
191#define BXE_TSO_MAX_SEG_SIZE 4096
194#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
195#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \
196 ETH_MAX_AGGREGATION_QUEUES_E1 : \
197 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
198#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
199#define FW_PREFETCH_CNT 16
200#define DROPLESS_FC_HEADROOM 100
206#define RX_SGE_NUM_PAGES 2
207#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
208#define RX_SGE_NEXT_PAGE_DESC_CNT 2
209#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT)
210#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1)
211#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES)
212#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)
213#define RX_SGE_MAX (RX_SGE_TOTAL - 1)
214#define RX_SGE(x) ((x) & RX_SGE_MAX)
216#define RX_SGE_NEXT(x) \
217 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \
218 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1)
220#define RX_SGE_MASK_ELEM_SZ 64
221#define RX_SGE_MASK_ELEM_SHIFT 6
222#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
228#define RX_SGE_ONES_MASK(idx) \
229 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
230#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
233#define RX_SGE_MASK_LEN \
234 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
235#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
236#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
247#define NUM_SGE_REQ(sc) \
248 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2)
249#define NUM_SGE_PG_REQ(sc) \
250 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE)
251#define SGE_TH_LO(sc) \
252 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT)
253#define SGE_TH_HI(sc) \
254 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM)
256#define PAGES_PER_SGE_SHIFT 0
257#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
258#define SGE_PAGE_SIZE BCM_PAGE_SIZE
259#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT
260#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr)
261#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
262#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff)
268#define TX_BD_NUM_PAGES 16
269#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
270#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1)
271#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES)
272#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES)
273#define TX_BD_MAX (TX_BD_TOTAL - 1)
275#define TX_BD_NEXT(x) \
276 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \
277 ((x) + 2) : ((x) + 1))
278#define TX_BD(x) ((x) & TX_BD_MAX)
279#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8)
280#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE)
286#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8)
287#define BXE_TX_TIMEOUT 5
293#define RX_BD_NUM_PAGES 8
294#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
295#define RX_BD_NEXT_PAGE_DESC_CNT 2
296#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT)
297#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1)
298#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES)
299#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
300#define RX_BD_MAX (RX_BD_TOTAL - 1)
302#define RX_BD_NEXT(x) \
303 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
304 ((x) + 3) : ((x) + 1))
305#define RX_BD(x) ((x) & RX_BD_MAX)
306#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
307#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
315#define NUM_BD_REQ(sc) \
317#define NUM_BD_PG_REQ(sc) \
318 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE)
319#define BD_TH_LO(sc) \
321 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
323#define BD_TH_HI(sc) \
324 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
325#define MIN_RX_AVAIL(sc) \
326 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
327#define MIN_RX_SIZE_TPA_HW(sc) \
328 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \
329 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
330#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
331#define MIN_RX_SIZE_TPA(sc) \
332 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc)))
333#define MIN_RX_SIZE_NONTPA(sc) \
334 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc)))
344#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \
345 sizeof(struct eth_rx_bd))
346#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL)
347#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
348#define RCQ_NEXT_PAGE_DESC_CNT 1
349#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT)
350#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES)
351#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES)
352#define RCQ_MAX (RCQ_TOTAL - 1)
355 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \
356 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1))
357#define RCQ(x) ((x) & RCQ_MAX)
358#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
359#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
367#define NUM_RCQ_REQ(sc) \
369#define NUM_RCQ_PG_REQ(sc) \
370 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE)
371#define RCQ_TH_LO(sc) \
373 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
375#define RCQ_TH_HI(sc) \
376 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
379#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
381#define __SGE_MASK_SET_BIT(el, bit) \
383 (el) = ((el) | ((uint64_t)0x1 << (bit))); \
386#define __SGE_MASK_CLEAR_BIT(el, bit) \
388 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \
391#define SGE_MASK_SET_BIT(fp, idx) \
392 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
393 ((idx) & RX_SGE_MASK_ELEM_MASK))
395#define SGE_MASK_CLEAR_BIT(fp, idx) \
396 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
397 ((idx) & RX_SGE_MASK_ELEM_MASK))
403#define LOAD_LOOPBACK_EXT 3
404#define UNLOAD_NORMAL 0
405#define UNLOAD_CLOSE 1
406#define UNLOAD_RECOVERY 2
413#define MAX_VNIC_NUM 4
414#define MAX_FUNC_NUM 8
416#define MAX_RSS_CHAINS 16
417#define MAX_MSI_VECTOR 8
419#define ILT_NUM_PAGE_ENTRIES 3072
425#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
426#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
433#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
434#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
438#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
439#define ETH_MIN_PACKET_SIZE 60
440#define ETH_MAX_PACKET_SIZE ETHERMTU
441#define ETH_MAX_JUMBO_PACKET_SIZE 9600
443#define ETH_MAX_TPA_HEADER_SIZE 72
447#define BXE_RX_ALIGN_SHIFT 8
449#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT)
450#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT)
452#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5)
453#define BXE_SET_ERROR_BIT(sc, error) \
455 (sc)->error_status |= (error); \
486#define MAX_DYNAMIC_ATTN_GRPS 8
518#define BXE_TSO_SPLIT_BD (1 << 0)
530#define BXE_TPA_STATE_START 1
531#define BXE_TPA_STATE_STOP 2
551#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx)
552#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx)
553#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED)
554#define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx)
556#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx)
557#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx)
558#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED)
611#define BXE_FP_STATE_CLOSED 0x01
612#define BXE_FP_STATE_IRQ 0x02
613#define BXE_FP_STATE_OPENING 0x04
614#define BXE_FP_STATE_OPEN 0x08
615#define BXE_FP_STATE_HALTING 0x10
616#define BXE_FP_STATE_HALTED 0x20
620#define FP_IDX(fp) (fp->index)
624 struct taskqueue *
tq;
632#define FP_CL_ID(fp) (fp->cl_id)
683#define BXE_BR_SIZE 4096
688#define BXE_MAX_NUM_OF_VFS 64
689#define BXE_VF_CID_WND 0
690#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND)
691#define BXE_CLIENTS_PER_VF 1
692#define BXE_FIRST_VF_CID 256
693#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF)
694#define BXE_VF_ID_INVALID 0xFF
695#define IS_SRIOV(sc) 0
697#define GET_NUM_VFS_PER_PATH(sc) 0
698#define GET_NUM_VFS_PER_PF(sc) 0
701#define FP_SB_MAX_E1x 16
702#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
710#define CDU_ILT_PAGE_SZ_HW 2
711#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW)
712#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
714#define CNIC_ISCSI_CID_MAX 256
715#define CNIC_FCOE_CID_MAX 2048
716#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
717#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
719#define QM_ILT_PAGE_SZ_HW 0
720#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW)
721#define QM_CID_ROUND 1024
724#define TM_ILT_PAGE_SZ_HW 0
725#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW)
727#define TM_CONN_NUM 1024
728#define TM_ILT_SZ (8 * TM_CONN_NUM)
729#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
732#define SRC_ILT_PAGE_SZ_HW 0
733#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW)
734#define SRC_HASH_BITS 10
735#define SRC_CONN_NUM (1 << SRC_HASH_BITS)
736#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
737#define SRC_T2_SZ SRC_ILT_SZ
738#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
751#define FIRST_TX_ONLY_COS_INDEX 1
752#define FIRST_TX_COS_INDEX 0
754#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc))
756#define HC_INDEX_ETH_RX_CQ_CONS 1
757#define HC_INDEX_OOO_TX_CQ_CONS 4
758#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
759#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
760#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
761#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
764#define CMNG_FNS_NONE 0
765#define CMNG_FNS_MINMAX 1
769#define DEF_MIN_RATE 100
771#define RS_PERIODIC_TIMEOUT_USEC 400
774#define QM_ARB_BYTES 160000
778#define MIN_ABOVE_THRESH 32768
781#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
785#define HC_SEG_ACCESS_DEF 0
786#define HC_SEG_ACCESS_ATTN 4
787#define HC_SEG_ACCESS_NORM 0
812#define BXE_NUM_QUEUES(sc) ((sc)->num_queues)
813#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc)
814#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc)
815#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc)
817#define FOR_EACH_QUEUE(sc, var) \
818 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++)
820#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
821 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++)
823#define FOR_EACH_ETH_QUEUE(sc, var) \
824 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
826#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
827 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
829#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
830 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
832#define FOR_EACH_CNIC_QUEUE(sc, var) \
833 for ((var) = BXE_NUM_ETH_QUEUES(sc); \
834 (var) < BXE_NUM_QUEUES(sc); \
843#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
844#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
845#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var)
846#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
847#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var)
848#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
850#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
851#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
852#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var)
853#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
854#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var)
856#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
857#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
858#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var)
859#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
860#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var)
861#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
863#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc))
864#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
865#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
866#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
867#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
868#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
869#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
893#define BXE_IGU_STAS_MSG_VF_CNT 64
894#define BXE_IGU_STAS_MSG_PF_CNT 4
910#define BXE_CORE_LOCK_SX
1001#define ADVERTISED_10baseT_Half (1 << 1)
1002#define ADVERTISED_10baseT_Full (1 << 2)
1003#define ADVERTISED_100baseT_Half (1 << 3)
1004#define ADVERTISED_100baseT_Full (1 << 4)
1005#define ADVERTISED_1000baseT_Half (1 << 5)
1006#define ADVERTISED_1000baseT_Full (1 << 6)
1007#define ADVERTISED_TP (1 << 7)
1008#define ADVERTISED_FIBRE (1 << 8)
1009#define ADVERTISED_Autoneg (1 << 9)
1010#define ADVERTISED_Asym_Pause (1 << 10)
1011#define ADVERTISED_Pause (1 << 11)
1012#define ADVERTISED_2500baseX_Full (1 << 15)
1013#define ADVERTISED_10000baseT_Full (1 << 16)
1021#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx)
1022#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx)
1023#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED)
1043#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
1044#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
1045#define VNICS_PER_PATH(sc) \
1046 ((sc)->devinfo.mf_info.vnics_per_port * \
1047 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
1053#define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
1054#define INVALID_VIF_ID 0xFFFF
1055#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
1056#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
1059#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
1062#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
1065#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
1070#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
1075#define MF_INFO_VALID_MAC 0x0001
1079 (IS_MULTI_VNIC(sc) && \
1080 ((sc)->devinfo.mf_info.mf_mode != 0))
1081#define IS_MF_SD(sc) \
1082 (IS_MULTI_VNIC(sc) && \
1083 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
1084#define IS_MF_SI(sc) \
1085 (IS_MULTI_VNIC(sc) && \
1086 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
1087#define IS_MF_AFEX(sc) \
1088 (IS_MULTI_VNIC(sc) && \
1089 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
1090#define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
1091#define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
1092#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
1095 #define MF_PROTO_SUPPORT_ETHERNET 0x1
1096 #define MF_PROTO_SUPPORT_ISCSI 0x2
1097 #define MF_PROTO_SUPPORT_FCOE 0x4
1116#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
1117#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
1119#define CHIP_NUM_57710 0x164e
1120#define CHIP_NUM_57711 0x164f
1121#define CHIP_NUM_57711E 0x1650
1122#define CHIP_NUM_57712 0x1662
1123#define CHIP_NUM_57712_MF 0x1663
1124#define CHIP_NUM_57712_VF 0x166f
1125#define CHIP_NUM_57800 0x168a
1126#define CHIP_NUM_57800_MF 0x16a5
1127#define CHIP_NUM_57800_VF 0x16a9
1128#define CHIP_NUM_57810 0x168e
1129#define CHIP_NUM_57810_MF 0x16ae
1130#define CHIP_NUM_57810_VF 0x16af
1131#define CHIP_NUM_57811 0x163d
1132#define CHIP_NUM_57811_MF 0x163e
1133#define CHIP_NUM_57811_VF 0x163f
1134#define CHIP_NUM_57840_OBS 0x168d
1135#define CHIP_NUM_57840_OBS_MF 0x16ab
1136#define CHIP_NUM_57840_4_10 0x16a1
1137#define CHIP_NUM_57840_2_20 0x16a2
1138#define CHIP_NUM_57840_MF 0x16a4
1139#define CHIP_NUM_57840_VF 0x16ad
1141#define CHIP_REV_SHIFT 12
1142#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1143#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
1145#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1146#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1147#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
1149#define CHIP_REV_IS_SLOW(sc) \
1150 (CHIP_REV(sc) > 0x00005000)
1151#define CHIP_REV_IS_FPGA(sc) \
1152 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
1153#define CHIP_REV_IS_EMUL(sc) \
1154 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
1155#define CHIP_REV_IS_ASIC(sc) \
1156 (!CHIP_REV_IS_SLOW(sc))
1158#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
1159#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
1161#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1162#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1163#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
1164#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
1165#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
1166 (CHIP_IS_57711E(sc)))
1167#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \
1170#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
1171#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
1172#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
1173#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
1174 CHIP_IS_57712_MF(sc))
1176#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
1177#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
1178#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
1179#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
1180#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
1181#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
1182#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
1183#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
1184#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
1185#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
1186 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
1187 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
1188#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
1189 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
1190#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
1192#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
1193 CHIP_IS_57800_MF(sc) || \
1194 CHIP_IS_57800_VF(sc) || \
1195 CHIP_IS_57810(sc) || \
1196 CHIP_IS_57810_MF(sc) || \
1197 CHIP_IS_57810_VF(sc) || \
1198 CHIP_IS_57811(sc) || \
1199 CHIP_IS_57811_MF(sc) || \
1200 CHIP_IS_57811_VF(sc) || \
1201 CHIP_IS_57840(sc) || \
1202 CHIP_IS_57840_MF(sc) || \
1203 CHIP_IS_57840_VF(sc))
1204#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
1205 (CHIP_REV(sc) == CHIP_REV_Ax))
1206#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
1207 (CHIP_REV(sc) == CHIP_REV_Bx))
1209#define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
1210#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
1213#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
1214 CHIP_IS_57712_MF(sc) || \
1217#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \
1218 CHIP_IS_57800_VF(sc) || \
1219 CHIP_IS_57810_VF(sc) || \
1220 CHIP_IS_57840_VF(sc))
1221#define IS_PF(sc) (!IS_VF(sc))
1235#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
1238#define CHIP_4_PORT_MODE 0x0
1239#define CHIP_2_PORT_MODE 0x1
1240#define CHIP_PORT_MODE_NONE 0x2
1241#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
1242#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
1245#define INT_BLOCK_HC 0
1246#define INT_BLOCK_IGU 1
1247#define INT_BLOCK_MODE_NORMAL 0
1248#define INT_BLOCK_MODE_BW_COMP 2
1249#define CHIP_INT_MODE_IS_NBC(sc) \
1250 (!CHIP_IS_E1x(sc) && \
1251 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
1252#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
1262#define NVRAM_1MB_SIZE 0x20000
1263#define NVRAM_TIMEOUT_COUNT 30000
1264#define NVRAM_PAGE_SIZE 256
1268#define BXE_PM_CAPABLE_FLAG 0x00000001
1269#define BXE_PCIE_CAPABLE_FLAG 0x00000002
1270#define BXE_MSI_CAPABLE_FLAG 0x00000004
1271#define BXE_MSIX_CAPABLE_FLAG 0x00000008
1317#define BXE_STATE_CLOSED 0x0000
1318#define BXE_STATE_OPENING_WAITING_LOAD 0x1000
1319#define BXE_STATE_OPENING_WAITING_PORT 0x2000
1320#define BXE_STATE_OPEN 0x3000
1321#define BXE_STATE_CLOSING_WAITING_HALT 0x4000
1322#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000
1323#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000
1324#define BXE_STATE_DISABLED 0xD000
1325#define BXE_STATE_DIAG 0xE000
1326#define BXE_STATE_ERROR 0xF000
1329#define BXE_ONE_PORT_FLAG 0x00000001
1330#define BXE_NO_ISCSI 0x00000002
1331#define BXE_NO_FCOE 0x00000004
1332#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG)
1338#define BXE_NO_MCP_FLAG 0x00000200
1339#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG)
1341#define BXE_MF_FUNC_DIS 0x00000800
1342#define BXE_TX_SWITCHING 0x00001000
1343#define BXE_NO_PULSE 0x00002000
1353#define PERIODIC_STOP 0
1354#define PERIODIC_GO 1
1359#define CHIP_TQ_NONE 0
1360#define CHIP_TQ_START 1
1361#define CHIP_TQ_STOP 2
1362#define CHIP_TQ_REINIT 3
1388#define SC_PATH(sc) (sc->path_id)
1389#define SC_PORT(sc) (sc->pfunc_rel & 1)
1390#define SC_FUNC(sc) (sc->pfunc_rel)
1391#define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1392#define SC_VN(sc) (sc->pfunc_rel >> 1)
1393#define SC_L_ID(sc) (SC_VN(sc) << 2)
1394#define PORT_ID(sc) SC_PORT(sc)
1395#define PATH_ID(sc) SC_PATH(sc)
1396#define VNIC_ID(sc) SC_VN(sc)
1397#define FUNC_ID(sc) SC_FUNC(sc)
1398#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1399#define SC_FW_MB_IDX_VN(sc, vn) \
1400 (SC_PORT(sc) + (vn) * \
1401 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1402#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1413#ifdef BXE_CORE_LOCK_SX
1417 struct mtx core_mtx;
1418 char core_mtx_name[32];
1433#ifdef BXE_CORE_LOCK_SX
1434#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx)
1435#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx)
1436#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx)
1437#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED)
1439#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx)
1440#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx)
1441#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx)
1442#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED)
1445#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx)
1446#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx)
1447#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED)
1449#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx)
1450#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx)
1451#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED)
1453#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx)
1454#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx)
1455#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED)
1457#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx)
1458#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx)
1459#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED)
1461#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx)
1462#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx)
1463#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED)
1465#define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx);
1466#define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx);
1467#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED)
1470#define DMAE_READY(sc) (sc->dmae_ready)
1497#define BXE_RECOVERY_DONE 1
1498#define BXE_RECOVERY_INIT 2
1499#define BXE_RECOVERY_WAIT 3
1500#define BXE_RECOVERY_FAILED 4
1501#define BXE_RECOVERY_NIC_LOADING 5
1503#define BXE_ERR_TXQ_STUCK 0x1
1504#define BXE_ERR_MISC 0x2
1505#define BXE_ERR_PARITY 0x4
1506#define BXE_ERR_STATS_TO 0x8
1507#define BXE_ERR_MC_ASSERT 0x10
1508#define BXE_ERR_PANIC 0x20
1509#define BXE_ERR_MCP_ASSERT 0x40
1510#define BXE_ERR_GLOBAL 0x80
1514#define BXE_RX_MODE_NONE 0
1515#define BXE_RX_MODE_NORMAL 1
1516#define BXE_RX_MODE_ALLMULTI 2
1517#define BXE_RX_MODE_PROMISC 3
1518#define BXE_MAX_MULTICAST 64
1533#define AUTO_GREEN_HW_DEFAULT 0
1534#define AUTO_GREEN_FORCE_ON 1
1535#define AUTO_GREEN_FORCE_OFF 2
1537#define INTR_MODE_INTX 0
1538#define INTR_MODE_MSI 1
1539#define INTR_MODE_MSIX 2
1552#define DEF_SB_IGU_ID 16
1553#define DEF_SB_ID HC_SP_SB_ID
1567#define HC_SP_INDEX_ETH_DEF_CONS 3
1569#define HC_SP_INDEX_EQ_CONS 7
1571#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1572#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1574#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1575#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1583#define NUM_EQ_PAGES 1
1584#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1585#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1586#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1587#define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1588#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1590#define NEXT_EQ_IDX(x) \
1591 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1592 ((x) + 2) : ((x) + 1))
1594#define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1604#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1605#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1606#define MAX_SPQ_PENDING 8
1623#define GUNZIP_BUF(sc) (sc->gz_buf)
1624#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1625#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr)
1626#define FW_BUF_SIZE 0x40000
1632#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1642#define INIT_OPS(sc) (sc->init_ops)
1643#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1644#define INIT_DATA(sc) (sc->init_data)
1645#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1646#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1647#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1648#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1649#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1650#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1651#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1652#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1658#define ILT_MAX_L2_LINES 8
1661#define ILT_MAX_LINES 256
1664#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1667#define BXE_L2_MAX_CID(sc) \
1668 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1670#define BXE_L2_MAX_CID(sc) \
1671 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1674#define BXE_L2_CID_COUNT(sc) \
1675 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1677#define BXE_L2_CID_COUNT(sc) \
1678 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1680#define L2_ILT_LINES(sc) \
1681 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1732#define BXE_DCB_STATE_OFF 0
1733#define BXE_DCB_STATE_ON 1
1736#define BXE_DCBX_ENABLED_OFF 0
1737#define BXE_DCBX_ENABLED_ON_NEG_OFF 1
1738#define BXE_DCBX_ENABLED_ON_NEG_ON 2
1739#define BXE_DCBX_ENABLED_INVALID -1
1748#define CNIC_SUPPORT(sc) 0
1749#define CNIC_ENABLED(sc) 0
1750#define CNIC_LOADED(sc) 0
1754#define BXE_MAX_PRIORITY 8
1771#define BXE_IOC_RD_NVRAM 1
1772#define BXE_IOC_WR_NVRAM 2
1773#define BXE_IOC_STATS_SHOW_NUM 3
1774#define BXE_IOC_STATS_SHOW_STR 4
1775#define BXE_IOC_STATS_SHOW_CNT 5
1800#define FUNC_FLG_RSS 0x0001
1801#define FUNC_FLG_STATS 0x0002
1803#define FUNC_FLG_TPA 0x0008
1804#define FUNC_FLG_SPQ 0x0010
1805#define FUNC_FLG_LEADING 0x0020
1822#ifdef BXE_REG_NO_INLINE
1828void bxe_reg_write8(
struct bxe_softc *sc, bus_size_t
offset, uint8_t val);
1829void bxe_reg_write16(
struct bxe_softc *sc, bus_size_t
offset, uint16_t val);
1830void bxe_reg_write32(
struct bxe_softc *sc, bus_size_t
offset, uint32_t val);
1832#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset)
1833#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset)
1834#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset)
1836#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val)
1837#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val)
1838#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val)
1842#define REG_WR8(sc, offset, val) \
1843 bus_space_write_1(sc->bar[BAR0].tag, \
1844 sc->bar[BAR0].handle, \
1847#define REG_WR16(sc, offset, val) \
1848 bus_space_write_2(sc->bar[BAR0].tag, \
1849 sc->bar[BAR0].handle, \
1852#define REG_WR32(sc, offset, val) \
1853 bus_space_write_4(sc->bar[BAR0].tag, \
1854 sc->bar[BAR0].handle, \
1857#define REG_RD8(sc, offset) \
1858 bus_space_read_1(sc->bar[BAR0].tag, \
1859 sc->bar[BAR0].handle, \
1862#define REG_RD16(sc, offset) \
1863 bus_space_read_2(sc->bar[BAR0].tag, \
1864 sc->bar[BAR0].handle, \
1867#define REG_RD32(sc, offset) \
1868 bus_space_read_4(sc->bar[BAR0].tag, \
1869 sc->bar[BAR0].handle, \
1874#define REG_RD(sc, offset) REG_RD32(sc, offset)
1875#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1877#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset)
1878#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val)
1880#define BXE_SP(sc, var) (&(sc)->sp->var)
1881#define BXE_SP_MAPPING(sc, var) \
1882 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var))
1884#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1885#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1887#define REG_RD_DMAE(sc, offset, valp, len32) \
1889 bxe_read_dmae(sc, offset, len32); \
1890 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \
1893#define REG_WR_DMAE(sc, offset, valp, len32) \
1895 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \
1896 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \
1899#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1900 REG_WR_DMAE(sc, offset, valp, len32)
1902#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1903 REG_RD_DMAE(sc, offset, valp, len32)
1905#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1910 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1911 ecore_write_big_buf_wb(sc, addr, len32); \
1914#define BXE_DB_MIN_SHIFT 3
1915#define BXE_DB_SHIFT 7
1916#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT)
1917#error "Minimum DB doorbell stride is 8"
1919#define DPM_TRIGGER_TYPE 0x40
1920#define DOORBELL(sc, cid, val) \
1922 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \
1923 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \
1927#define SHMEM_ADDR(sc, field) \
1928 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1929#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1930#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1931#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1933#define SHMEM2_ADDR(sc, field) \
1934 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1935#define SHMEM2_HAS(sc, field) \
1936 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1937 offsetof(struct shmem2_region, field)))
1938#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1939#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1941#define MFCFG_ADDR(sc, field) \
1942 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1943#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1944#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1945#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1949#define DMAE_TIMEOUT -1
1950#define DMAE_PCI_ERROR -2
1951#define DMAE_NOT_RDY -3
1952#define DMAE_PCI_ERR_FLAG 0x80000000
1954#define DMAE_SRC_PCI 0
1955#define DMAE_SRC_GRC 1
1957#define DMAE_DST_NONE 0
1958#define DMAE_DST_PCI 1
1959#define DMAE_DST_GRC 2
1961#define DMAE_COMP_PCI 0
1962#define DMAE_COMP_GRC 1
1964#define DMAE_COMP_REGULAR 0
1965#define DMAE_COM_SET_ERR 1
1967#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT)
1968#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT)
1969#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT)
1970#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT)
1972#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT)
1973#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT)
1975#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT)
1976#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT)
1977#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT)
1978#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT)
1980#define DMAE_CMD_PORT_0 0
1981#define DMAE_CMD_PORT_1 DMAE_CMD_PORT
1983#define DMAE_SRC_PF 0
1984#define DMAE_SRC_VF 1
1986#define DMAE_DST_PF 0
1987#define DMAE_DST_VF 1
1992#define DMAE_LEN32_RD_MAX 0x80
1993#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
1995#define DMAE_COMP_VAL 0x60d0d0ae
1997#define MAX_DMAE_C_PER_PORT 8
1998#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1999#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
2008#define ATTN_NIG_FOR_FUNC (1L << 8)
2009#define ATTN_SW_TIMER_4_FUNC (1L << 9)
2010#define GPIO_2_FUNC (1L << 10)
2011#define GPIO_3_FUNC (1L << 11)
2012#define GPIO_4_FUNC (1L << 12)
2013#define ATTN_GENERAL_ATTN_1 (1L << 13)
2014#define ATTN_GENERAL_ATTN_2 (1L << 14)
2015#define ATTN_GENERAL_ATTN_3 (1L << 15)
2016#define ATTN_GENERAL_ATTN_4 (1L << 13)
2017#define ATTN_GENERAL_ATTN_5 (1L << 14)
2018#define ATTN_GENERAL_ATTN_6 (1L << 15)
2019#define ATTN_HARD_WIRED_MASK 0xff00
2020#define ATTENTION_ID 4
2022#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
2023 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
2025#define MAX_IGU_ATTN_ACK_TO 100
2027#define STORM_ASSERT_ARRAY_SIZE 50
2029#define BXE_PMF_LINK_ASSERT(sc) \
2030 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
2032#define BXE_MC_ASSERT_BITS \
2033 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2034 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2035 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2036 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2038#define BXE_MCP_ASSERT \
2039 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2041#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2042#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2043 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2044 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2045 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2046 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2047 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2049#define MULTI_MASK 0x7f
2051#define PFS_PER_PORT(sc) \
2052 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
2053#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
2055#define FIRST_ABS_FUNC_IN_PORT(sc) \
2056 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
2057 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
2059#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
2060 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
2061 (i) < MAX_FUNC_NUM; \
2062 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
2064#define BXE_SWCID_SHIFT 17
2065#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1)
2067#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK)
2068#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
2070#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
2071#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
2072#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
2073#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
2074#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
2077#define HW_CID(sc, x) \
2078 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
2081#define SPEED_100 100
2082#define SPEED_1000 1000
2083#define SPEED_2500 2500
2084#define SPEED_10000 10000
2087#define PCI_PM_D3hot 2
2089#ifndef DUPLEX_UNKNOWN
2090#define DUPLEX_UNKNOWN (0xff)
2093#ifndef SPEED_UNKNOWN
2094#define SPEED_UNKNOWN (-1)
2098#define AUTONEG_DISABLE 0x00
2099#define AUTONEG_ENABLE 0x01
2103#define PORT_AUI 0x01
2104#define PORT_MII 0x02
2105#define PORT_FIBRE 0x03
2106#define PORT_BNC 0x04
2108#define PORT_NONE 0xef
2109#define PORT_OTHER 0xff
2124 struct bxe_dma *dma,
const char *msg);
2130 uint8_t dst_type, uint8_t with_comp,
2135 uint32_t dst_addr, uint32_t len32);
2137 uint32_t
addr, uint32_t len);
2142 uint8_t sb_index, uint8_t disable,
2146 uint32_t data_hi, uint32_t data_lo,
int cmd_type);
2149 uint8_t segment, uint16_t index, uint8_t op,
2157 size_t size, uint32_t *data);
2164#define DBG_LOAD 0x00000001
2165#define DBG_INTR 0x00000002
2166#define DBG_SP 0x00000004
2167#define DBG_STATS 0x00000008
2168#define DBG_TX 0x00000010
2169#define DBG_RX 0x00000020
2170#define DBG_PHY 0x00000040
2171#define DBG_IOCTL 0x00000080
2172#define DBG_MBUF 0x00000100
2173#define DBG_REGS 0x00000200
2174#define DBG_LRO 0x00000400
2175#define DBG_ASSERT 0x80000000
2176#define DBG_ALL 0xFFFFFFFF
2178#define DBASSERT(sc, exp, msg) \
2180 if (__predict_false(sc->debug & DBG_ASSERT)) { \
2181 if (__predict_false(!(exp))) { \
2188#define BLOGD(sc, codepath, format, args...) \
2190 if (__predict_false(sc->debug & (codepath))) { \
2191 device_printf((sc)->dev, \
2192 "%s(%s:%d) " format, \
2201#define BLOGI(sc, format, args...) \
2203 if (__predict_false(sc->debug)) { \
2204 device_printf((sc)->dev, \
2205 "%s(%s:%d) " format, \
2211 device_printf((sc)->dev, \
2218#define BLOGW(sc, format, args...) \
2220 if (__predict_false(sc->debug)) { \
2221 device_printf((sc)->dev, \
2222 "%s(%s:%d) WARNING: " format, \
2228 device_printf((sc)->dev, \
2229 "WARNING: " format, \
2235#define BLOGE(sc, format, args...) \
2237 if (__predict_false(sc->debug)) { \
2238 device_printf((sc)->dev, \
2239 "%s(%s:%d) ERROR: " format, \
2245 device_printf((sc)->dev, \
2251#ifdef ECORE_STOP_ON_ERROR
2253#define bxe_panic(sc, msg) \
2260#define bxe_panic(sc, msg) \
2261 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
2265#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2266#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
2269 uint8_t *mem, uint32_t len);
2271 struct mbuf *m, uint8_t contents);
2273#define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE)
2274#define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2280static inline uint32_t
2291 if (val == expected) {
2331 BUS_SPACE_BARRIER_WRITE);
2347 igu_ack.status_block_index = index;
2348 igu_ack.sb_id_and_flags =
2349 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2350 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2351 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2352 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2354 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
2358 BUS_SPACE_BARRIER_WRITE);
2387static inline uint16_t
2392 uint32_t result =
REG_RD(sc, hc_addr);
2398static inline uint16_t
2402 uint32_t result =
REG_RD(sc, igu_addr);
2411static inline uint16_t
2426 return (2 * vn +
SC_PORT(sc));
2433static inline uint8_t
uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
static void bxe_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update)
#define CHIP_INT_MODE_IS_BC(sc)
static uint16_t bxe_igu_ack_int(struct bxe_softc *sc)
int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, struct bxe_dma *dma, const char *msg)
void ecore_init_e1h_firmware(struct bxe_softc *sc)
static uint16_t bxe_hc_ack_int(struct bxe_softc *sc)
uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr)
#define MAX_DYNAMIC_ATTN_GRPS
static void bxe_igu_ack_sb_gen(struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t segment, uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
void ecore_init_e1_firmware(struct bxe_softc *sc)
void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, struct mbuf *m, uint8_t contents)
void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, uint32_t cid)
static uint8_t bxe_stats_id(struct bxe_fastpath *fp)
void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32)
void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val)
int bxe_test_bit(int nr, volatile unsigned long *addr)
static const uint32_t dmae_reg_go_c[]
void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, uint32_t addr, uint32_t len)
static void bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
int bxe_cmpxchg(volatile int *addr, int old, int new)
void bxe_dump_mem(struct bxe_softc *sc, char *tag, uint8_t *mem, uint32_t len)
void bxe_set_bit(unsigned int nr, volatile unsigned long *addr)
uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, uint8_t dst_type, uint8_t with_comp, uint8_t comp_type)
void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx)
void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma)
int bxe_sp_post(struct bxe_softc *sc, int command, int cid, uint32_t data_hi, uint32_t data_lo, int cmd_type)
void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, uint32_t dst_addr, uint32_t len32)
static uint16_t bxe_ack_int(struct bxe_softc *sc)
void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, size_t size, uint32_t *data)
static void bxe_hc_ack_sb(struct bxe_softc *sc, uint8_t sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update)
@ BXE_FIRST_QUEUE_QUERY_IDX
int bxe_test_and_set_bit(int nr, volatile unsigned long *addr)
static int func_by_vn(struct bxe_softc *sc, int vn)
static int bxe_ilog2(int x)
static uint32_t reg_poll(struct bxe_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
#define REG_RD(sc, offset)
void ecore_init_e2_firmware(struct bxe_softc *sc)
uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
#define BLOGD(sc, codepath, format, args...)
@ BXE_LINK_REPORT_FULL_DUPLEX
@ BXE_LINK_REPORT_LINK_DOWN
@ BXE_LINK_REPORT_TX_FC_ON
@ BXE_LINK_REPORT_RX_FC_ON
void bxe_clear_bit(int nr, volatile unsigned long *addr)
void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, uint8_t sb_index, uint8_t disable, uint16_t usec)
#define REG_WR(sc, offset, val)
void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t segment, uint16_t index, uint8_t op, uint8_t update)
int bxe_test_and_clear_bit(int nr, volatile unsigned long *addr)
#define ELINK_LINK_CONFIG_SIZE
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2
#define IGU_REGULAR_SB_INDEX_SHIFT
#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT
#define IGU_REGULAR_BUPDATE_SHIFT
#define IGU_REGULAR_ENABLE_INT_SHIFT
#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER
#define COMMAND_REG_SIMD_MASK
#define COMMAND_REG_INT_ACK
#define HC_REG_COMMAND_REG
struct resource * resource
bus_space_handle_t handle
uint16_t pcie_msix_cap_reg
uint16_t pcie_pcie_cap_reg
uint16_t pcie_msi_cap_reg
struct bxe_mf_info mf_info
uint32_t ustorm_rx_prods_offset
struct tstorm_per_queue_stats old_tclient
bus_dmamap_t rx_sge_mbuf_spare_map
union eth_rx_cqe * rcq_chain
union bxe_host_hc_status_block status_block
struct bxe_dma rx_sge_dma
bus_dma_tag_t tx_mbuf_tag
struct bxe_eth_q_stats eth_q_stats
struct eth_rx_sge * rx_sge_chain
bus_dmamap_t rx_mbuf_spare_map
bus_dmamap_t rx_tpa_info_mbuf_spare_map
uint64_t sge_mask[RX_SGE_MASK_LEN]
union eth_tx_bd_types * tx_chain
uint16_t * sb_running_index
struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]
struct eth_rx_bd * rx_chain
struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]
bus_dma_tag_t rx_mbuf_tag
struct ustorm_per_queue_stats old_uclient
uint16_t * sb_index_values
struct timeout_task tx_timeout_task
struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]
uint64_t rx_tpa_queue_used
struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]
bus_dma_tag_t rx_sge_mbuf_tag
struct xstorm_per_queue_stats old_xclient
struct bxe_eth_q_stats_old eth_q_stats_old
struct per_port_stats port
struct stats_counter storm_counters
struct per_queue_stats queue_stats[1]
struct stats_query_entry query[FP_SB_MAX_E1x+BXE_FIRST_QUEUE_QUERY_IDX]
struct stats_query_header hdr
struct resource * resource
unsigned long link_report_flags
uint32_t mf_config[E1HVN_MAX]
uint8_t max_bw[MAX_VNIC_NUM]
uint32_t multi_vnics_mode
uint32_t mf_protos_supported
uint8_t min_bw[MAX_VNIC_NUM]
uint8_t niv_allowed_priorities
enum mf_cfg_afex_vlan_mode afex_vlan_mode
uint32_t advertising[ELINK_LINK_CONFIG_SIZE]
uint32_t supported[ELINK_LINK_CONFIG_SIZE]
uint32_t link_config[ELINK_LINK_CONFIG_SIZE]
struct nig_stats old_nig_stats
struct flow_control_configuration pfc_config
union bxe_slowpath::@6 rx_mode_rdata
struct host_func_stats func_stats
struct eth_classify_rules_ramrod_data e2
struct host_port_stats port_stats
struct afex_vif_list_ramrod_data func_afex_rdata
union bxe_slowpath::@8 func_rdata
union bxe_slowpath::@5 mac_rdata
union bxe_slowpath::@9 q_rdata
struct client_update_ramrod_data update_data
struct eth_rss_update_ramrod_data rss_rdata
struct mac_configuration_cmd e1x
union bxe_slowpath::@7 mcast_rdata
struct client_init_ramrod_data init_data
struct dmae_cmd dmae[MAX_DMAE_C]
struct function_start_data func_start
struct mac_configuration_cmd e1
struct bxe_eth_stats_old eth_stats_old
struct bxe_net_stats_old net_stats_old
struct eth_spe * spq_last_bd
struct host_func_stats func_stats
const struct raw_op * init_ops
struct bxe_fw_stats_data * fw_stats_data
const struct iro * iro_array
union event_ring_elem * eq
struct bxe_bar bar[MAX_BARS]
struct dmae_cmd stats_dmae
struct bxe_fw_stats_req * fw_stats_req
uint16_t fw_drv_pulse_wr_seq
const uint32_t * init_data
struct taskqueue * chip_tq
unsigned int trigger_grcdump
const uint8_t * csem_pram_data
const uint8_t * xsem_int_table_data
struct ecore_credit_pool_obj vlans_pool
const uint8_t * csem_int_table_data
struct bxe_dma def_sb_dma
const uint8_t * tsem_pram_data
unsigned int grcdump_started
struct eth_spe * spq_prod_bd
const uint8_t * xsem_pram_data
struct bxe_fastpath fp[MAX_RSS_CHAINS]
bus_dma_tag_t parent_dma_tag
uint8_t prio_to_cos[BXE_MAX_PRIORITY]
volatile unsigned long chip_tq_flags
struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]
struct ecore_credit_pool_obj macs_pool
struct elink_vars link_vars
int last_reported_link_state
const uint8_t * tsem_int_table_data
struct bxe_config_dcbx_params dcbx_config_params
struct hw_context context[ILT_MAX_L2_LINES]
const uint8_t * usem_pram_data
const uint8_t * usem_int_table_data
struct ecore_rx_mode_obj rx_mode_obj
const uint16_t * init_ops_offsets
struct bxe_config_lldp_params lldp_config_params
struct bxe_eth_stats eth_stats
struct elink_params link_params
volatile unsigned long cq_spq_left
struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]
bus_addr_t fw_stats_req_mapping
struct bxe_devinfo devinfo
struct ecore_func_sp_obj func_obj
struct ecore_mcast_obj mcast_obj
volatile unsigned long periodic_flags
struct bxe_link_report_data last_reported_link
struct timeout_task sp_err_timeout_task
struct callout periodic_callout
struct bxe_dma fw_stats_dma
struct bxe_fw_port_stats_old fw_stats_old
unsigned int grcdump_done
struct ecore_rss_config_obj rss_conf_obj
bus_addr_t fw_stats_data_mapping
volatile unsigned long eq_spq_left
struct bxe_dma gz_buf_dma
struct bxe_dcbx_port_params dcbx_port_params
struct bxe_intr intr[MAX_RSS_CHAINS+1]
struct host_sp_status_block * def_sb
struct ecore_queue_sp_obj q_obj
struct ecore_vlan_mac_obj mac_obj
struct doorbell_set_prod data
struct host_hc_status_block_e2 * e2_sb
struct host_hc_status_block_e1x * e1x_sb
struct bxe_stats_show_data::@10 desc