FreeBSD kernel BXE device code
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#include <sys/cdefs.h>
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/sx.h>
#include <sys/module.h>
#include <sys/endian.h>
#include <sys/types.h>
#include <sys/malloc.h>
#include <sys/kobj.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <sys/sysctl.h>
#include <sys/smp.h>
#include <sys/bitstring.h>
#include <sys/limits.h>
#include <sys/queue.h>
#include <sys/taskqueue.h>
#include <contrib/zlib/zlib.h>
#include <net/debugnet.h>
#include <net/if.h>
#include <net/if_types.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_var.h>
#include <net/if_media.h>
#include <net/if_vlan_var.h>
#include <net/bpf.h>
#include <netinet/in.h>
#include <netinet/ip.h>
#include <netinet/ip6.h>
#include <netinet/tcp.h>
#include <netinet/udp.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <machine/atomic.h>
#include <machine/resource.h>
#include <machine/endian.h>
#include <machine/bus.h>
#include <machine/in_cksum.h>
#include "device_if.h"
#include "bus_if.h"
#include "pci_if.h"
#include "ecore_mfw_req.h"
#include "ecore_fw_defs.h"
#include "ecore_hsi.h"
#include "ecore_reg.h"
#include "bxe_dcb.h"
#include "bxe_stats.h"
#include "bxe_elink.h"
#include "ecore_sp.h"
Go to the source code of this file.
Data Structures | |
struct | bxe_device_type |
struct | bxe_bar |
struct | bxe_intr |
struct | bxe_dma |
struct | attn_route |
struct | iro |
union | bxe_host_hc_status_block |
union | bxe_db_prod |
struct | bxe_sw_tx_bd |
struct | bxe_sw_rx_bd |
struct | bxe_sw_tpa_info |
struct | bxe_fastpath |
union | cdu_context |
struct | hw_context |
struct | bxe_fw_stats_req |
struct | bxe_fw_stats_data |
struct | bxe_slowpath |
struct | bxe_port |
struct | bxe_mf_info |
struct | bxe_devinfo |
struct | bxe_sp_objs |
struct | bxe_link_report_data |
struct | bxe_softc |
struct | bxe_nvram_data |
union | bxe_stats_show_data |
struct | bxe_func_init_params |
Macros | |
#define | LITTLE_ENDIAN |
#define | __LITTLE_ENDIAN |
#define | VF_MAC_CREDIT_CNT 0 |
#define | VF_VLAN_CREDIT_CNT (0) |
#define | ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) |
#define | DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) |
#define | roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) |
#define | ilog2(x) bxe_ilog2(x) |
#define | BRCM_VENDORID 0x14e4 |
#define | QLOGIC_VENDORID 0x1077 |
#define | PCI_ANY_ID (uint16_t)(~0U) |
#define | BCM_PAGE_SHIFT 12 |
#define | BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) |
#define | BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) |
#define | BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
#define | U64_LO(addr) ((uint32_t)(addr)) |
#define | U64_HI(addr) (0) |
#define | HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) |
#define | SET_FLAG(value, mask, flag) |
#define | GET_FLAG(value, mask) (((value) & (mask)) >> (mask##_SHIFT)) |
#define | GET_FIELD(value, fname) (((value) & (fname##_MASK)) >> (fname##_SHIFT)) |
#define | BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ |
#define | BXE_TSO_MAX_SEGMENTS 32 |
#define | BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) |
#define | BXE_TSO_MAX_SEG_SIZE 4096 |
#define | BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) |
#define | MAX_AGG_QS(sc) |
#define | FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) |
#define | FW_PREFETCH_CNT 16 |
#define | DROPLESS_FC_HEADROOM 100 |
#define | RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ |
#define | RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
#define | RX_SGE_NEXT_PAGE_DESC_CNT 2 |
#define | RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) |
#define | RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) |
#define | RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) |
#define | RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) |
#define | RX_SGE_MAX (RX_SGE_TOTAL - 1) |
#define | RX_SGE(x) ((x) & RX_SGE_MAX) |
#define | RX_SGE_NEXT(x) |
#define | RX_SGE_MASK_ELEM_SZ 64 |
#define | RX_SGE_MASK_ELEM_SHIFT 6 |
#define | RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) |
#define | RX_SGE_ONES_MASK(idx) (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) |
#define | RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) |
#define | RX_SGE_MASK_LEN ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) |
#define | RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
#define | RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) |
#define | NUM_SGE_REQ(sc) (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) |
#define | NUM_SGE_PG_REQ(sc) ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) |
#define | SGE_TH_LO(sc) (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) |
#define | SGE_TH_HI(sc) (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) |
#define | PAGES_PER_SGE_SHIFT 0 |
#define | PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) |
#define | SGE_PAGE_SIZE BCM_PAGE_SIZE |
#define | SGE_PAGE_SHIFT BCM_PAGE_SHIFT |
#define | SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) |
#define | SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) |
#define | TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) |
#define | TX_BD_NUM_PAGES 16 /* must be a power of 2 */ |
#define | TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
#define | TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) |
#define | TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) |
#define | TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) |
#define | TX_BD_MAX (TX_BD_TOTAL - 1) |
#define | TX_BD_NEXT(x) |
#define | TX_BD(x) ((x) & TX_BD_MAX) |
#define | TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) |
#define | TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) |
#define | BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) |
#define | BXE_TX_TIMEOUT 5 |
#define | RX_BD_NUM_PAGES 8 /* power of 2 */ |
#define | RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
#define | RX_BD_NEXT_PAGE_DESC_CNT 2 |
#define | RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) |
#define | RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) |
#define | RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) |
#define | RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) |
#define | RX_BD_MAX (RX_BD_TOTAL - 1) |
#define | RX_BD_NEXT(x) |
#define | RX_BD(x) ((x) & RX_BD_MAX) |
#define | RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) |
#define | RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) |
#define | NUM_BD_REQ(sc) BRB_SIZE(sc) |
#define | NUM_BD_PG_REQ(sc) ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) |
#define | BD_TH_LO(sc) |
#define | BD_TH_HI(sc) (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) |
#define | MIN_RX_AVAIL(sc) ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) |
#define | MIN_RX_SIZE_TPA_HW(sc) |
#define | MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA |
#define | MIN_RX_SIZE_TPA(sc) (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) |
#define | MIN_RX_SIZE_NONTPA(sc) (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) |
#define | CQE_BD_REL |
#define | RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ |
#define | RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
#define | RCQ_NEXT_PAGE_DESC_CNT 1 |
#define | RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) |
#define | RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) |
#define | RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) |
#define | RCQ_MAX (RCQ_TOTAL - 1) |
#define | RCQ_NEXT(x) |
#define | RCQ(x) ((x) & RCQ_MAX) |
#define | RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) |
#define | RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) |
#define | NUM_RCQ_REQ(sc) BRB_SIZE(sc) |
#define | NUM_RCQ_PG_REQ(sc) ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) |
#define | RCQ_TH_LO(sc) |
#define | RCQ_TH_HI(sc) (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) |
#define | SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) |
#define | __SGE_MASK_SET_BIT(el, bit) |
#define | __SGE_MASK_CLEAR_BIT(el, bit) |
#define | SGE_MASK_SET_BIT(fp, idx) |
#define | SGE_MASK_CLEAR_BIT(fp, idx) |
#define | LOAD_NORMAL 0 |
#define | LOAD_OPEN 1 |
#define | LOAD_DIAG 2 |
#define | LOAD_LOOPBACK_EXT 3 |
#define | UNLOAD_NORMAL 0 |
#define | UNLOAD_CLOSE 1 |
#define | UNLOAD_RECOVERY 2 |
#define | MAX_VNIC_NUM 4 |
#define | MAX_FUNC_NUM 8 /* common to all chips */ |
#define | MAX_RSS_CHAINS 16 /* a constant for HW limit */ |
#define | MAX_MSI_VECTOR 8 /* a constant for HW limit */ |
#define | ILT_NUM_PAGE_ENTRIES 3072 |
#define | ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) |
#define | FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) |
#define | ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) |
#define | ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) |
#define | ETH_HLEN 14 |
#define | ETH_OVERHEAD (ETH_HLEN + 8 + 8) |
#define | ETH_MIN_PACKET_SIZE 60 |
#define | ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ |
#define | ETH_MAX_JUMBO_PACKET_SIZE 9600 |
#define | ETH_MAX_TPA_HEADER_SIZE 72 |
#define | BXE_RX_ALIGN_SHIFT 8 |
#define | BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) |
#define | BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) |
#define | BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ |
#define | BXE_SET_ERROR_BIT(sc, error) |
#define | MAX_DYNAMIC_ATTN_GRPS 8 |
#define | BXE_TSO_SPLIT_BD (1 << 0) |
#define | BXE_TPA_STATE_START 1 |
#define | BXE_TPA_STATE_STOP 2 |
#define | BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) |
#define | BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) |
#define | BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) |
#define | BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) |
#define | BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) |
#define | BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) |
#define | BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) |
#define | BXE_FP_STATE_CLOSED 0x01 |
#define | BXE_FP_STATE_IRQ 0x02 |
#define | BXE_FP_STATE_OPENING 0x04 |
#define | BXE_FP_STATE_OPEN 0x08 |
#define | BXE_FP_STATE_HALTING 0x10 |
#define | BXE_FP_STATE_HALTED 0x20 |
#define | FP_IDX(fp) (fp->index) |
#define | FP_CL_ID(fp) (fp->cl_id) |
#define | BXE_BR_SIZE 4096 |
#define | BXE_MAX_NUM_OF_VFS 64 |
#define | BXE_VF_CID_WND 0 |
#define | BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) |
#define | BXE_CLIENTS_PER_VF 1 |
#define | BXE_FIRST_VF_CID 256 |
#define | BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) |
#define | BXE_VF_ID_INVALID 0xFF |
#define | IS_SRIOV(sc) 0 |
#define | GET_NUM_VFS_PER_PATH(sc) 0 |
#define | GET_NUM_VFS_PER_PF(sc) 0 |
#define | FP_SB_MAX_E1x 16 |
#define | FP_SB_MAX_E2 HC_SB_MAX_SB_E2 |
#define | CDU_ILT_PAGE_SZ_HW 2 |
#define | CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ |
#define | ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
#define | CNIC_ISCSI_CID_MAX 256 |
#define | CNIC_FCOE_CID_MAX 2048 |
#define | CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) |
#define | CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
#define | QM_ILT_PAGE_SZ_HW 0 |
#define | QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ |
#define | QM_CID_ROUND 1024 |
#define | TM_ILT_PAGE_SZ_HW 0 |
#define | TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ |
#define | TM_CONN_NUM 1024 |
#define | TM_ILT_SZ (8 * TM_CONN_NUM) |
#define | TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) |
#define | SRC_ILT_PAGE_SZ_HW 0 |
#define | SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ |
#define | SRC_HASH_BITS 10 |
#define | SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ |
#define | SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) |
#define | SRC_T2_SZ SRC_ILT_SZ |
#define | SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) |
#define | SM_RX_ID 0 |
#define | SM_TX_ID 1 |
#define | FIRST_TX_ONLY_COS_INDEX 1 |
#define | FIRST_TX_COS_INDEX 0 |
#define | CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) |
#define | HC_INDEX_ETH_RX_CQ_CONS 1 |
#define | HC_INDEX_OOO_TX_CQ_CONS 4 |
#define | HC_INDEX_ETH_TX_CQ_CONS_COS0 5 |
#define | HC_INDEX_ETH_TX_CQ_CONS_COS1 6 |
#define | HC_INDEX_ETH_TX_CQ_CONS_COS2 7 |
#define | HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 |
#define | CMNG_FNS_NONE 0 |
#define | CMNG_FNS_MINMAX 1 |
#define | DEF_MIN_RATE 100 |
#define | RS_PERIODIC_TIMEOUT_USEC 400 |
#define | QM_ARB_BYTES 160000 |
#define | MIN_RES 100 |
#define | MIN_ABOVE_THRESH 32768 |
#define | T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) |
#define | FAIR_MEM 2 |
#define | HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ |
#define | HC_SEG_ACCESS_ATTN 4 |
#define | HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ |
#define | BXE_NUM_QUEUES(sc) ((sc)->num_queues) |
#define | BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) |
#define | BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) |
#define | BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) |
#define | FOR_EACH_QUEUE(sc, var) for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) |
#define | FOR_EACH_NONDEFAULT_QUEUE(sc, var) for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) |
#define | FOR_EACH_ETH_QUEUE(sc, var) for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) |
#define | FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) |
#define | FOR_EACH_COS_IN_TX_QUEUE(sc, var) for ((var) = 0; (var) < (sc)->max_cos; (var)++) |
#define | FOR_EACH_CNIC_QUEUE(sc, var) |
#define | FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) |
#define | bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) |
#define | bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) |
#define | bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) |
#define | bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) |
#define | bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) |
#define | OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) |
#define | bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) |
#define | bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) |
#define | bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) |
#define | bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) |
#define | FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) |
#define | bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) |
#define | bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) |
#define | bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) |
#define | bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) |
#define | bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) |
#define | IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) |
#define | IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) |
#define | IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) |
#define | IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) |
#define | IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) |
#define | IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) |
#define | IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) |
#define | BXE_IGU_STAS_MSG_VF_CNT 64 |
#define | BXE_IGU_STAS_MSG_PF_CNT 4 |
#define | MAX_DMAE_C 8 |
#define | BXE_CORE_LOCK_SX |
#define | ADVERTISED_10baseT_Half (1 << 1) |
#define | ADVERTISED_10baseT_Full (1 << 2) |
#define | ADVERTISED_100baseT_Half (1 << 3) |
#define | ADVERTISED_100baseT_Full (1 << 4) |
#define | ADVERTISED_1000baseT_Half (1 << 5) |
#define | ADVERTISED_1000baseT_Full (1 << 6) |
#define | ADVERTISED_TP (1 << 7) |
#define | ADVERTISED_FIBRE (1 << 8) |
#define | ADVERTISED_Autoneg (1 << 9) |
#define | ADVERTISED_Asym_Pause (1 << 10) |
#define | ADVERTISED_Pause (1 << 11) |
#define | ADVERTISED_2500baseX_Full (1 << 15) |
#define | ADVERTISED_10000baseT_Full (1 << 16) |
#define | BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) |
#define | BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) |
#define | BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) |
#define | IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) |
#define | VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) |
#define | VNICS_PER_PATH(sc) |
#define | VALID_OVLAN(ovlan) ((ovlan) <= 4096) |
#define | INVALID_VIF_ID 0xFFFF |
#define | OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) |
#define | VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) |
#define | NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) |
#define | NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) |
#define | NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) |
#define | AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) |
#define | MF_INFO_VALID_MAC 0x0001 |
#define | IS_MF(sc) |
#define | IS_MF_SD(sc) |
#define | IS_MF_SI(sc) |
#define | IS_MF_AFEX(sc) |
#define | IS_MF_SD_MODE(sc) IS_MF_SD(sc) |
#define | IS_MF_SI_MODE(sc) IS_MF_SI(sc) |
#define | IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) |
#define | MF_PROTO_SUPPORT_ETHERNET 0x1 |
#define | MF_PROTO_SUPPORT_ISCSI 0x2 |
#define | MF_PROTO_SUPPORT_FCOE 0x4 |
#define | CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) |
#define | CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) |
#define | CHIP_NUM_57710 0x164e |
#define | CHIP_NUM_57711 0x164f |
#define | CHIP_NUM_57711E 0x1650 |
#define | CHIP_NUM_57712 0x1662 |
#define | CHIP_NUM_57712_MF 0x1663 |
#define | CHIP_NUM_57712_VF 0x166f |
#define | CHIP_NUM_57800 0x168a |
#define | CHIP_NUM_57800_MF 0x16a5 |
#define | CHIP_NUM_57800_VF 0x16a9 |
#define | CHIP_NUM_57810 0x168e |
#define | CHIP_NUM_57810_MF 0x16ae |
#define | CHIP_NUM_57810_VF 0x16af |
#define | CHIP_NUM_57811 0x163d |
#define | CHIP_NUM_57811_MF 0x163e |
#define | CHIP_NUM_57811_VF 0x163f |
#define | CHIP_NUM_57840_OBS 0x168d |
#define | CHIP_NUM_57840_OBS_MF 0x16ab |
#define | CHIP_NUM_57840_4_10 0x16a1 |
#define | CHIP_NUM_57840_2_20 0x16a2 |
#define | CHIP_NUM_57840_MF 0x16a4 |
#define | CHIP_NUM_57840_VF 0x16ad |
#define | CHIP_REV_SHIFT 12 |
#define | CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) |
#define | CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) |
#define | CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) |
#define | CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) |
#define | CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) |
#define | CHIP_REV_IS_SLOW(sc) (CHIP_REV(sc) > 0x00005000) |
#define | CHIP_REV_IS_FPGA(sc) (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) |
#define | CHIP_REV_IS_EMUL(sc) (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) |
#define | CHIP_REV_IS_ASIC(sc) (!CHIP_REV_IS_SLOW(sc)) |
#define | CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) |
#define | CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) |
#define | CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) |
#define | CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) |
#define | CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) |
#define | CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) |
#define | CHIP_IS_E1H(sc) |
#define | CHIP_IS_E1x(sc) |
#define | CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) |
#define | CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) |
#define | CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) |
#define | CHIP_IS_E2(sc) |
#define | CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) |
#define | CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) |
#define | CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) |
#define | CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) |
#define | CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) |
#define | CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) |
#define | CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) |
#define | CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) |
#define | CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) |
#define | CHIP_IS_57840(sc) |
#define | CHIP_IS_57840_MF(sc) |
#define | CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) |
#define | CHIP_IS_E3(sc) |
#define | CHIP_IS_E3A0(sc) |
#define | CHIP_IS_E3B0(sc) |
#define | USES_WARPCORE(sc) (CHIP_IS_E3(sc)) |
#define | CHIP_IS_E2E3(sc) |
#define | CHIP_IS_MF_CAP(sc) |
#define | IS_VF(sc) |
#define | IS_PF(sc) (!IS_VF(sc)) |
#define | CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) |
#define | CHIP_4_PORT_MODE 0x0 |
#define | CHIP_2_PORT_MODE 0x1 |
#define | CHIP_PORT_MODE_NONE 0x2 |
#define | CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) |
#define | CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) |
#define | INT_BLOCK_HC 0 |
#define | INT_BLOCK_IGU 1 |
#define | INT_BLOCK_MODE_NORMAL 0 |
#define | INT_BLOCK_MODE_BW_COMP 2 |
#define | CHIP_INT_MODE_IS_NBC(sc) |
#define | CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) |
#define | NVRAM_1MB_SIZE 0x20000 |
#define | NVRAM_TIMEOUT_COUNT 30000 |
#define | NVRAM_PAGE_SIZE 256 |
#define | BXE_PM_CAPABLE_FLAG 0x00000001 |
#define | BXE_PCIE_CAPABLE_FLAG 0x00000002 |
#define | BXE_MSI_CAPABLE_FLAG 0x00000004 |
#define | BXE_MSIX_CAPABLE_FLAG 0x00000008 |
#define | BXE_STATE_CLOSED 0x0000 |
#define | BXE_STATE_OPENING_WAITING_LOAD 0x1000 |
#define | BXE_STATE_OPENING_WAITING_PORT 0x2000 |
#define | BXE_STATE_OPEN 0x3000 |
#define | BXE_STATE_CLOSING_WAITING_HALT 0x4000 |
#define | BXE_STATE_CLOSING_WAITING_DELETE 0x5000 |
#define | BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 |
#define | BXE_STATE_DISABLED 0xD000 |
#define | BXE_STATE_DIAG 0xE000 |
#define | BXE_STATE_ERROR 0xF000 |
#define | BXE_ONE_PORT_FLAG 0x00000001 |
#define | BXE_NO_ISCSI 0x00000002 |
#define | BXE_NO_FCOE 0x00000004 |
#define | BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) |
#define | BXE_NO_MCP_FLAG 0x00000200 |
#define | BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) |
#define | BXE_MF_FUNC_DIS 0x00000800 |
#define | BXE_TX_SWITCHING 0x00001000 |
#define | BXE_NO_PULSE 0x00002000 |
#define | MAX_BARS 5 |
#define | PERIODIC_STOP 0 |
#define | PERIODIC_GO 1 |
#define | CHIP_TQ_NONE 0 |
#define | CHIP_TQ_START 1 |
#define | CHIP_TQ_STOP 2 |
#define | CHIP_TQ_REINIT 3 |
#define | SC_PATH(sc) (sc->path_id) |
#define | SC_PORT(sc) (sc->pfunc_rel & 1) |
#define | SC_FUNC(sc) (sc->pfunc_rel) |
#define | SC_ABS_FUNC(sc) (sc->pfunc_abs) |
#define | SC_VN(sc) (sc->pfunc_rel >> 1) |
#define | SC_L_ID(sc) (SC_VN(sc) << 2) |
#define | PORT_ID(sc) SC_PORT(sc) |
#define | PATH_ID(sc) SC_PATH(sc) |
#define | VNIC_ID(sc) SC_VN(sc) |
#define | FUNC_ID(sc) SC_FUNC(sc) |
#define | ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) |
#define | SC_FW_MB_IDX_VN(sc, vn) |
#define | SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) |
#define | BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) |
#define | BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) |
#define | BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) |
#define | BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) |
#define | BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) |
#define | BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) |
#define | BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) |
#define | BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) |
#define | BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) |
#define | BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) |
#define | BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) |
#define | BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) |
#define | BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) |
#define | BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) |
#define | BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) |
#define | BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) |
#define | BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) |
#define | BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) |
#define | BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) |
#define | BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx); |
#define | BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx); |
#define | BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) |
#define | DMAE_READY(sc) (sc->dmae_ready) |
#define | BXE_RECOVERY_DONE 1 |
#define | BXE_RECOVERY_INIT 2 |
#define | BXE_RECOVERY_WAIT 3 |
#define | BXE_RECOVERY_FAILED 4 |
#define | BXE_RECOVERY_NIC_LOADING 5 |
#define | BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ |
#define | BXE_ERR_MISC 0x2 /* MISC ERR */ |
#define | BXE_ERR_PARITY 0x4 /* Parity error detected. */ |
#define | BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ |
#define | BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ |
#define | BXE_ERR_PANIC 0x20 /* Driver asserted. */ |
#define | BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ |
#define | BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ |
#define | BXE_RX_MODE_NONE 0 |
#define | BXE_RX_MODE_NORMAL 1 |
#define | BXE_RX_MODE_ALLMULTI 2 |
#define | BXE_RX_MODE_PROMISC 3 |
#define | BXE_MAX_MULTICAST 64 |
#define | AUTO_GREEN_HW_DEFAULT 0 |
#define | AUTO_GREEN_FORCE_ON 1 |
#define | AUTO_GREEN_FORCE_OFF 2 |
#define | INTR_MODE_INTX 0 |
#define | INTR_MODE_MSI 1 |
#define | INTR_MODE_MSIX 2 |
#define | DEF_SB_IGU_ID 16 |
#define | DEF_SB_ID HC_SP_SB_ID |
#define | HC_SP_INDEX_ETH_DEF_CONS 3 |
#define | HC_SP_INDEX_EQ_CONS 7 |
#define | HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 |
#define | HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 |
#define | HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 |
#define | HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 |
#define | NUM_EQ_PAGES 1 /* must be a power of 2 */ |
#define | EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) |
#define | EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) |
#define | NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) |
#define | EQ_DESC_MASK (NUM_EQ_DESC - 1) |
#define | MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) |
#define | NEXT_EQ_IDX(x) |
#define | EQ_DESC(x) ((x) & EQ_DESC_MASK) |
#define | SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
#define | MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
#define | MAX_SPQ_PENDING 8 |
#define | GUNZIP_BUF(sc) (sc->gz_buf) |
#define | GUNZIP_OUTLEN(sc) (sc->gz_outlen) |
#define | GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) |
#define | FW_BUF_SIZE 0x40000 |
#define | INIT_MODE_FLAGS(sc) (sc->init_mode_flags) |
#define | INIT_OPS(sc) (sc->init_ops) |
#define | INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) |
#define | INIT_DATA(sc) (sc->init_data) |
#define | INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) |
#define | INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) |
#define | INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) |
#define | INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) |
#define | INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) |
#define | INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) |
#define | INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) |
#define | INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) |
#define | ILT_MAX_L2_LINES 8 |
#define | ILT_MAX_LINES 256 |
#define | BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) |
#define | BXE_L2_MAX_CID(sc) (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) |
#define | BXE_L2_CID_COUNT(sc) (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) |
#define | L2_ILT_LINES(sc) (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) |
#define | BXE_DCB_STATE_OFF 0 |
#define | BXE_DCB_STATE_ON 1 |
#define | BXE_DCBX_ENABLED_OFF 0 |
#define | BXE_DCBX_ENABLED_ON_NEG_OFF 1 |
#define | BXE_DCBX_ENABLED_ON_NEG_ON 2 |
#define | BXE_DCBX_ENABLED_INVALID -1 |
#define | CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ |
#define | CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ |
#define | CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ |
#define | BXE_MAX_PRIORITY 8 |
#define | BXE_IOC_RD_NVRAM 1 |
#define | BXE_IOC_WR_NVRAM 2 |
#define | BXE_IOC_STATS_SHOW_NUM 3 |
#define | BXE_IOC_STATS_SHOW_STR 4 |
#define | BXE_IOC_STATS_SHOW_CNT 5 |
#define | FUNC_FLG_RSS 0x0001 |
#define | FUNC_FLG_STATS 0x0002 |
#define | FUNC_FLG_TPA 0x0008 |
#define | FUNC_FLG_SPQ 0x0010 |
#define | FUNC_FLG_LEADING 0x0020 /* PF only */ |
#define | BAR0 0 |
#define | BAR1 2 |
#define | BAR2 4 |
#define | REG_WR8(sc, offset, val) |
#define | REG_WR16(sc, offset, val) |
#define | REG_WR32(sc, offset, val) |
#define | REG_RD8(sc, offset) |
#define | REG_RD16(sc, offset) |
#define | REG_RD32(sc, offset) |
#define | REG_RD(sc, offset) REG_RD32(sc, offset) |
#define | REG_WR(sc, offset, val) REG_WR32(sc, offset, val) |
#define | REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) |
#define | REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) |
#define | BXE_SP(sc, var) (&(sc)->sp->var) |
#define | BXE_SP_MAPPING(sc, var) (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) |
#define | BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) |
#define | BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) |
#define | REG_RD_DMAE(sc, offset, valp, len32) |
#define | REG_WR_DMAE(sc, offset, valp, len32) |
#define | REG_WR_DMAE_LEN(sc, offset, valp, len32) REG_WR_DMAE(sc, offset, valp, len32) |
#define | REG_RD_DMAE_LEN(sc, offset, valp, len32) REG_RD_DMAE(sc, offset, valp, len32) |
#define | VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) |
#define | BXE_DB_MIN_SHIFT 3 /* 8 bytes */ |
#define | BXE_DB_SHIFT 7 /* 128 bytes */ |
#define | DPM_TRIGGER_TYPE 0x40 |
#define | DOORBELL(sc, cid, val) |
#define | SHMEM_ADDR(sc, field) (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) |
#define | SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) |
#define | SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) |
#define | SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) |
#define | SHMEM2_ADDR(sc, field) (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) |
#define | SHMEM2_HAS(sc, field) |
#define | SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) |
#define | SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) |
#define | MFCFG_ADDR(sc, field) (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) |
#define | MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) |
#define | MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) |
#define | MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) |
#define | DMAE_TIMEOUT -1 |
#define | DMAE_PCI_ERROR -2 /* E2 and onward */ |
#define | DMAE_NOT_RDY -3 |
#define | DMAE_PCI_ERR_FLAG 0x80000000 |
#define | DMAE_SRC_PCI 0 |
#define | DMAE_SRC_GRC 1 |
#define | DMAE_DST_NONE 0 |
#define | DMAE_DST_PCI 1 |
#define | DMAE_DST_GRC 2 |
#define | DMAE_COMP_PCI 0 |
#define | DMAE_COMP_GRC 1 |
#define | DMAE_COMP_REGULAR 0 |
#define | DMAE_COM_SET_ERR 1 |
#define | DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) |
#define | DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) |
#define | DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) |
#define | DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) |
#define | DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) |
#define | DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) |
#define | DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) |
#define | DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) |
#define | DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) |
#define | DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) |
#define | DMAE_CMD_PORT_0 0 |
#define | DMAE_CMD_PORT_1 DMAE_CMD_PORT |
#define | DMAE_SRC_PF 0 |
#define | DMAE_SRC_VF 1 |
#define | DMAE_DST_PF 0 |
#define | DMAE_DST_VF 1 |
#define | DMAE_C_SRC 0 |
#define | DMAE_C_DST 1 |
#define | DMAE_LEN32_RD_MAX 0x80 |
#define | DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) |
#define | DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ |
#define | MAX_DMAE_C_PER_PORT 8 |
#define | INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) |
#define | PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) |
#define | ATTN_NIG_FOR_FUNC (1L << 8) |
#define | ATTN_SW_TIMER_4_FUNC (1L << 9) |
#define | GPIO_2_FUNC (1L << 10) |
#define | GPIO_3_FUNC (1L << 11) |
#define | GPIO_4_FUNC (1L << 12) |
#define | ATTN_GENERAL_ATTN_1 (1L << 13) |
#define | ATTN_GENERAL_ATTN_2 (1L << 14) |
#define | ATTN_GENERAL_ATTN_3 (1L << 15) |
#define | ATTN_GENERAL_ATTN_4 (1L << 13) |
#define | ATTN_GENERAL_ATTN_5 (1L << 14) |
#define | ATTN_GENERAL_ATTN_6 (1L << 15) |
#define | ATTN_HARD_WIRED_MASK 0xff00 |
#define | ATTENTION_ID 4 |
#define | AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |
#define | MAX_IGU_ATTN_ACK_TO 100 |
#define | STORM_ASSERT_ARRAY_SIZE 50 |
#define | BXE_PMF_LINK_ASSERT(sc) GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) |
#define | BXE_MC_ASSERT_BITS |
#define | BXE_MCP_ASSERT GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) |
#define | BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
#define | BXE_GRC_RSV |
#define | MULTI_MASK 0x7f |
#define | PFS_PER_PORT(sc) ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) |
#define | SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) |
#define | FIRST_ABS_FUNC_IN_PORT(sc) |
#define | FOREACH_ABS_FUNC_IN_PORT(sc, i) |
#define | BXE_SWCID_SHIFT 17 |
#define | BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) |
#define | SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) |
#define | CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) |
#define | CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
#define | CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) |
#define | CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) |
#define | CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) |
#define | CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) |
#define | HW_CID(sc, x) ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) |
#define | SPEED_10 10 |
#define | SPEED_100 100 |
#define | SPEED_1000 1000 |
#define | SPEED_2500 2500 |
#define | SPEED_10000 10000 |
#define | PCI_PM_D0 1 |
#define | PCI_PM_D3hot 2 |
#define | DUPLEX_UNKNOWN (0xff) |
#define | SPEED_UNKNOWN (-1) |
#define | AUTONEG_DISABLE 0x00 |
#define | AUTONEG_ENABLE 0x01 |
#define | PORT_TP 0x00 |
#define | PORT_AUI 0x01 |
#define | PORT_MII 0x02 |
#define | PORT_FIBRE 0x03 |
#define | PORT_BNC 0x04 |
#define | PORT_DA 0x05 |
#define | PORT_NONE 0xef |
#define | PORT_OTHER 0xff |
#define | DBG_LOAD 0x00000001 /* load and unload */ |
#define | DBG_INTR 0x00000002 /* interrupt handling */ |
#define | DBG_SP 0x00000004 /* slowpath handling */ |
#define | DBG_STATS 0x00000008 /* stats updates */ |
#define | DBG_TX 0x00000010 /* packet transmit */ |
#define | DBG_RX 0x00000020 /* packet receive */ |
#define | DBG_PHY 0x00000040 /* phy/link handling */ |
#define | DBG_IOCTL 0x00000080 /* ioctl handling */ |
#define | DBG_MBUF 0x00000100 /* dumping mbuf info */ |
#define | DBG_REGS 0x00000200 /* register access */ |
#define | DBG_LRO 0x00000400 /* lro processing */ |
#define | DBG_ASSERT 0x80000000 /* debug assert */ |
#define | DBG_ALL 0xFFFFFFFF /* flying monkeys */ |
#define | DBASSERT(sc, exp, msg) |
#define | BLOGD(sc, codepath, format, args...) |
#define | BLOGI(sc, format, args...) |
#define | BLOGW(sc, format, args...) |
#define | BLOGE(sc, format, args...) |
#define | bxe_panic(sc, msg) device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); |
#define | CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); |
#define | CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) |
#define | BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) |
#define | BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) |
Enumerations | |
enum | { OOO_IDX_OFFSET , FCOE_IDX_OFFSET , FWD_IDX_OFFSET } |
enum | { BXE_PORT_QUERY_IDX , BXE_PF_QUERY_IDX , BXE_FCOE_QUERY_IDX , BXE_FIRST_QUEUE_QUERY_IDX } |
enum | { BXE_LINK_REPORT_FULL_DUPLEX , BXE_LINK_REPORT_LINK_DOWN , BXE_LINK_REPORT_RX_FC_ON , BXE_LINK_REPORT_TX_FC_ON } |
Functions | |
__FBSDID ("$FreeBSD$") | |
static int | bxe_ilog2 (int x) |
int | bxe_test_bit (int nr, volatile unsigned long *addr) |
void | bxe_set_bit (unsigned int nr, volatile unsigned long *addr) |
void | bxe_clear_bit (int nr, volatile unsigned long *addr) |
int | bxe_test_and_set_bit (int nr, volatile unsigned long *addr) |
int | bxe_test_and_clear_bit (int nr, volatile unsigned long *addr) |
int | bxe_cmpxchg (volatile int *addr, int old, int new) |
void | bxe_reg_wr_ind (struct bxe_softc *sc, uint32_t addr, uint32_t val) |
uint32_t | bxe_reg_rd_ind (struct bxe_softc *sc, uint32_t addr) |
int | bxe_dma_alloc (struct bxe_softc *sc, bus_size_t size, struct bxe_dma *dma, const char *msg) |
void | bxe_dma_free (struct bxe_softc *sc, struct bxe_dma *dma) |
uint32_t | bxe_dmae_opcode_add_comp (uint32_t opcode, uint8_t comp_type) |
uint32_t | bxe_dmae_opcode_clr_src_reset (uint32_t opcode) |
uint32_t | bxe_dmae_opcode (struct bxe_softc *sc, uint8_t src_type, uint8_t dst_type, uint8_t with_comp, uint8_t comp_type) |
void | bxe_post_dmae (struct bxe_softc *sc, struct dmae_cmd *dmae, int idx) |
void | bxe_read_dmae (struct bxe_softc *sc, uint32_t src_addr, uint32_t len32) |
void | bxe_write_dmae (struct bxe_softc *sc, bus_addr_t dma_addr, uint32_t dst_addr, uint32_t len32) |
void | bxe_write_dmae_phys_len (struct bxe_softc *sc, bus_addr_t phys_addr, uint32_t addr, uint32_t len) |
void | bxe_set_ctx_validation (struct bxe_softc *sc, struct eth_context *cxt, uint32_t cid) |
void | bxe_update_coalesce_sb_index (struct bxe_softc *sc, uint8_t fw_sb_id, uint8_t sb_index, uint8_t disable, uint16_t usec) |
int | bxe_sp_post (struct bxe_softc *sc, int command, int cid, uint32_t data_hi, uint32_t data_lo, int cmd_type) |
void | bxe_igu_ack_sb (struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t segment, uint16_t index, uint8_t op, uint8_t update) |
void | ecore_init_e1_firmware (struct bxe_softc *sc) |
void | ecore_init_e1h_firmware (struct bxe_softc *sc) |
void | ecore_init_e2_firmware (struct bxe_softc *sc) |
void | ecore_storm_memset_struct (struct bxe_softc *sc, uint32_t addr, size_t size, uint32_t *data) |
void | bxe_dump_mem (struct bxe_softc *sc, char *tag, uint8_t *mem, uint32_t len) |
void | bxe_dump_mbuf_data (struct bxe_softc *sc, char *pTag, struct mbuf *m, uint8_t contents) |
static uint32_t | reg_poll (struct bxe_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait) |
static void | bxe_update_fp_sb_idx (struct bxe_fastpath *fp) |
static void | bxe_igu_ack_sb_gen (struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t segment, uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr) |
static void | bxe_hc_ack_sb (struct bxe_softc *sc, uint8_t sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update) |
static void | bxe_ack_sb (struct bxe_softc *sc, uint8_t igu_sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update) |
static uint16_t | bxe_hc_ack_int (struct bxe_softc *sc) |
static uint16_t | bxe_igu_ack_int (struct bxe_softc *sc) |
static uint16_t | bxe_ack_int (struct bxe_softc *sc) |
static int | func_by_vn (struct bxe_softc *sc, int vn) |
static uint8_t | bxe_stats_id (struct bxe_fastpath *fp) |
Variables | |
static const uint32_t | dmae_reg_go_c [] |
#define __SGE_MASK_CLEAR_BIT | ( | el, | |
bit | |||
) |
#define __SGE_MASK_SET_BIT | ( | el, | |
bit | |||
) |
#define ABS_FUNC_ID | ( | sc | ) | SC_ABS_FUNC(sc) |
#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |
#define AFEX_VLAN_MODE | ( | sc | ) | ((sc)->devinfo.mf_info.afex_vlan_mode) |
#define BCM_PAGE_ALIGN | ( | addr | ) | ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) |
#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) |
#define BD_TH_HI | ( | sc | ) | (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) |
#define BD_TH_LO | ( | sc | ) |
#define BLOGD | ( | sc, | |
codepath, | |||
format, | |||
args... | |||
) |
#define BLOGE | ( | sc, | |
format, | |||
args... | |||
) |
#define BLOGI | ( | sc, | |
format, | |||
args... | |||
) |
#define BLOGW | ( | sc, | |
format, | |||
args... | |||
) |
#define BRB_SIZE | ( | sc | ) | (CHIP_IS_E3(sc) ? 1024 : 512) |
#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) |
#define BXE_CORE_LOCK_ASSERT | ( | sc | ) | sx_assert(&sc->core_sx, SA_XLOCKED) |
#define BXE_DMAE_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->dmae_mtx, MA_OWNED) |
#define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ |
#define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ |
#define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ |
#define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ |
#define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ |
#define bxe_fcoe | ( | sc, | |
var | |||
) | (bxe_fcoe_fp(sc)->var) |
#define bxe_fcoe_inner_sp_obj | ( | sc | ) | (&sc->sp_objs[FCOE_IDX(sc)]) |
#define bxe_fcoe_sp_obj | ( | sc, | |
var | |||
) | (bxe_fcoe_inner_sp_obj(sc)->var) |
#define bxe_fcoe_tx | ( | sc, | |
var | |||
) | (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) |
#define BXE_FP_RX_LOCK_ASSERT | ( | fp | ) | mtx_assert(&fp->rx_mtx, MA_OWNED) |
#define BXE_FP_TX_LOCK_ASSERT | ( | fp | ) | mtx_assert(&fp->tx_mtx, MA_OWNED) |
#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) |
#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) |
#define bxe_fwd | ( | sc, | |
var | |||
) | (bxe_fwd_fp(sc)->var) |
#define bxe_fwd_inner_sp_obj | ( | sc | ) | (&sc->sp_objs[FWD_IDX(sc)]) |
#define bxe_fwd_sp_obj | ( | sc, | |
var | |||
) | (bxe_fwd_inner_sp_obj(sc)->var) |
#define bxe_fwd_txdata | ( | fp | ) | (fp->txdata_ptr[FIRST_TX_COS_INDEX]) |
#define BXE_FWMB_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->fwmb_mtx, MA_OWNED) |
#define BXE_GRC_RSV |
#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
#define BXE_L2_CID_COUNT | ( | sc | ) | (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) |
#define BXE_L2_MAX_CID | ( | sc | ) | (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) |
#define BXE_MAX_RSS_COUNT | ( | sc | ) | ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) |
#define BXE_MC_ASSERT_BITS |
#define BXE_MCAST_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->mcast_mtx, MA_OWNED) |
#define BXE_MCP_ASSERT GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) |
#define BXE_NOMCP | ( | sc | ) | (sc->flags & BXE_NO_MCP_FLAG) |
#define BXE_NUM_ETH_QUEUES | ( | sc | ) | BXE_NUM_QUEUES(sc) |
#define BXE_NUM_NON_CNIC_QUEUES | ( | sc | ) | BXE_NUM_QUEUES(sc) |
#define BXE_NUM_RX_QUEUES | ( | sc | ) | BXE_NUM_QUEUES(sc) |
#define BXE_ONE_PORT | ( | sc | ) | (sc->flags & BXE_ONE_PORT_FLAG) |
#define bxe_ooo | ( | sc, | |
var | |||
) | (bxe_ooo_fp(sc)->var) |
#define bxe_ooo_inner_sp_obj | ( | sc | ) | (&sc->sp_objs[OOO_IDX(sc)]) |
#define bxe_ooo_sp_obj | ( | sc, | |
var | |||
) | (bxe_ooo_inner_sp_obj(sc)->var) |
#define bxe_panic | ( | sc, | |
msg | |||
) | device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); |
#define BXE_PHY_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->port.phy_mtx, MA_OWNED) |
#define BXE_PMF_LINK_ASSERT | ( | sc | ) | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) |
#define BXE_PRINT_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->print_mtx, MA_OWNED) |
#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ |
#define BXE_SET_ERROR_BIT | ( | sc, | |
error | |||
) |
#define BXE_SET_FLOWID | ( | m | ) | M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) |
#define BXE_SP_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->sp_mtx, MA_OWNED) |
#define BXE_SP_MAPPING | ( | sc, | |
var | |||
) | (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) |
#define BXE_STATS_LOCK_ASSERT | ( | sc | ) | mtx_assert(&sc->stats_mtx, MA_OWNED) |
#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) |
#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) |
#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) |
#define BXE_VALID_FLOWID | ( | m | ) | (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) |
#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) |
#define CATC_TRIGGER | ( | sc, | |
data | |||
) | REG_WR((sc), 0x2000, (data)); |
#define CATC_TRIGGER_START | ( | sc | ) | CATC_TRIGGER((sc), 0xcafecafe) |
#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ |
#define CHIP_BOND_ID | ( | sc | ) | ((sc->devinfo.chip_id) & 0x0000000f) |
#define CHIP_INT_MODE_IS_BC | ( | sc | ) | (!CHIP_INT_MODE_IS_NBC(sc)) |
#define CHIP_INT_MODE_IS_NBC | ( | sc | ) |
#define CHIP_IS_57710 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57710) |
#define CHIP_IS_57711 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57711) |
#define CHIP_IS_57711E | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57711E) |
#define CHIP_IS_57712 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57712) |
#define CHIP_IS_57712_MF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57712_MF) |
#define CHIP_IS_57712_VF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57712_VF) |
#define CHIP_IS_57800 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57800) |
#define CHIP_IS_57800_MF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57800_MF) |
#define CHIP_IS_57800_VF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57800_VF) |
#define CHIP_IS_57810 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57810) |
#define CHIP_IS_57810_MF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57810_MF) |
#define CHIP_IS_57810_VF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57810_VF) |
#define CHIP_IS_57811 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57811) |
#define CHIP_IS_57811_MF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57811_MF) |
#define CHIP_IS_57811_VF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57811_VF) |
#define CHIP_IS_57840 | ( | sc | ) |
#define CHIP_IS_57840_MF | ( | sc | ) |
#define CHIP_IS_57840_VF | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57840_VF) |
#define CHIP_IS_E1 | ( | sc | ) | (CHIP_NUM(sc) == CHIP_NUM_57710) |
#define CHIP_IS_E1H | ( | sc | ) |
#define CHIP_IS_E1x | ( | sc | ) |
#define CHIP_IS_E2 | ( | sc | ) |
#define CHIP_IS_E2E3 | ( | sc | ) |
#define CHIP_IS_E3 | ( | sc | ) |
#define CHIP_IS_E3A0 | ( | sc | ) |
#define CHIP_IS_E3B0 | ( | sc | ) |
#define CHIP_IS_MF_CAP | ( | sc | ) |
#define CHIP_IS_MODE_4_PORT | ( | sc | ) | (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) |
#define CHIP_METAL | ( | sc | ) | ((sc->devinfo.chip_id) & 0x00000ff0) |
#define CHIP_REV | ( | sc | ) | ((sc)->devinfo.chip_id & CHIP_REV_MASK) |
#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) |
#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) |
#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) |
#define CHIP_REV_IS_ASIC | ( | sc | ) | (!CHIP_REV_IS_SLOW(sc)) |
#define CHIP_REV_IS_EMUL | ( | sc | ) | (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) |
#define CHIP_REV_IS_FPGA | ( | sc | ) | (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) |
#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) |
#define CID_TO_FP | ( | cid, | |
sc | |||
) | ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) |
#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) |
#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
#define CONFIGURE_NIC_MODE | ( | sc | ) | (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) |
#define CQE_BD_REL |
#define CQE_CMD | ( | x | ) | (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) |
#define CQE_TYPE | ( | cqe_fp_flags | ) | ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
#define CQE_TYPE_FAST | ( | cqe_type | ) | ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) |
#define CQE_TYPE_SLOW | ( | cqe_type | ) | ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) |
#define CQE_TYPE_START | ( | cqe_type | ) | ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) |
#define CQE_TYPE_STOP | ( | cqe_type | ) | ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) |
#define DBASSERT | ( | sc, | |
exp, | |||
msg | |||
) |
#define DEF_SB_ID HC_SP_SB_ID |
#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) |
#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) |
#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) |
#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) |
#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) |
#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) |
#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) |
#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) |
#define DMAE_CMD_PORT_1 DMAE_CMD_PORT |
#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) |
#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) |
#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ |
#define DMAE_LEN32_WR_MAX | ( | sc | ) | (CHIP_IS_E1(sc) ? 0x400 : 0x2000) |
#define DOORBELL | ( | sc, | |
cid, | |||
val | |||
) |
#define EQ_DESC | ( | x | ) | ((x) & EQ_DESC_MASK) |
#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) |
#define EQ_DESC_MASK (NUM_EQ_DESC - 1) |
#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) |
#define FCOE_IDX | ( | sc | ) | (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) |
#define FIRST_ABS_FUNC_IN_PORT | ( | sc | ) |
#define FOR_EACH_CNIC_QUEUE | ( | sc, | |
var | |||
) |
#define FOR_EACH_COS_IN_TX_QUEUE | ( | sc, | |
var | |||
) | for ((var) = 0; (var) < (sc)->max_cos; (var)++) |
#define FOR_EACH_ETH_QUEUE | ( | sc, | |
var | |||
) | for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) |
#define FOR_EACH_NONDEFAULT_ETH_QUEUE | ( | sc, | |
var | |||
) | for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) |
#define FOR_EACH_NONDEFAULT_QUEUE | ( | sc, | |
var | |||
) | for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) |
#define FOR_EACH_QUEUE | ( | sc, | |
var | |||
) | for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) |
#define FOREACH_ABS_FUNC_IN_PORT | ( | sc, | |
i | |||
) |
#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 |
#define FUNC_ILT_BASE | ( | func | ) | (func * ILT_PER_FUNC) |
#define FW_DROP_LEVEL | ( | sc | ) | (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) |
#define FWD_IDX | ( | sc | ) | (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) |
#define GET_FIELD | ( | value, | |
fname | |||
) | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) |
#define GET_FLAG | ( | value, | |
mask | |||
) | (((value) & (mask)) >> (mask##_SHIFT)) |
#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 |
#define HW_CID | ( | sc, | |
x | |||
) | ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) |
#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) |
#define INIT_CSEM_INT_TABLE_DATA | ( | sc | ) | (sc->csem_int_table_data) |
#define INIT_DMAE_C | ( | sc | ) | ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) |
#define INIT_TSEM_INT_TABLE_DATA | ( | sc | ) | (sc->tsem_int_table_data) |
#define INIT_USEM_INT_TABLE_DATA | ( | sc | ) | (sc->usem_int_table_data) |
#define INIT_XSEM_INT_TABLE_DATA | ( | sc | ) | (sc->xsem_int_table_data) |
#define IS_ETH_FP | ( | fp | ) | ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) |
#define IS_MF | ( | sc | ) |
#define IS_MF_AFEX | ( | sc | ) |
#define IS_MF_AFEX_MODE | ( | sc | ) | IS_MF_AFEX(sc) |
#define IS_MF_SD | ( | sc | ) |
#define IS_MF_SI | ( | sc | ) |
#define IS_MULTI_VNIC | ( | sc | ) | ((sc)->devinfo.mf_info.multi_vnics_mode) |
#define IS_VF | ( | sc | ) |
#define L2_ILT_LINES | ( | sc | ) | (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) |
#define MAX_AGG_QS | ( | sc | ) |
#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) |
#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
#define MFCFG_ADDR | ( | sc, | |
field | |||
) | (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) |
#define MFCFG_RD | ( | sc, | |
field | |||
) | REG_RD(sc, MFCFG_ADDR(sc, field)) |
#define MFCFG_RD16 | ( | sc, | |
field | |||
) | REG_RD16(sc, MFCFG_ADDR(sc, field)) |
#define MFCFG_WR | ( | sc, | |
field, | |||
val | |||
) | REG_WR(sc, MFCFG_ADDR(sc, field), val) |
#define MIN_RX_AVAIL | ( | sc | ) | ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) |
#define MIN_RX_SIZE_NONTPA | ( | sc | ) | (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) |
#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA |
#define MIN_RX_SIZE_TPA | ( | sc | ) | (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) |
#define MIN_RX_SIZE_TPA_HW | ( | sc | ) |
#define NEXT_EQ_IDX | ( | x | ) |
#define NIV_ALLOWED_PRIORITIES | ( | sc | ) | ((sc)->devinfo.mf_info.niv_allowed_priorities) |
#define NIV_DEFAULT_COS | ( | sc | ) | ((sc)->devinfo.mf_info.niv_default_cos) |
#define NIV_DEFAULT_VLAN | ( | sc | ) | ((sc)->devinfo.mf_info.default_vlan) |
#define NUM_BD_PG_REQ | ( | sc | ) | ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) |
#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) |
#define NUM_RCQ_PG_REQ | ( | sc | ) | ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) |
#define NUM_SGE_PG_REQ | ( | sc | ) | ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) |
#define NUM_SGE_REQ | ( | sc | ) | (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) |
#define ONCHIP_ADDR1 | ( | x | ) | ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) |
#define ONCHIP_ADDR2 | ( | x | ) | ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) |
#define OOO_IDX | ( | sc | ) | (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) |
#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) |
#define PFS_PER_PORT | ( | sc | ) | ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) |
#define PMF_DMAE_C | ( | sc | ) | ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) |
#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ |
#define RCQ_IDX | ( | x | ) | ((x) & RCQ_USABLE_PER_PAGE) |
#define RCQ_NEXT | ( | x | ) |
#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ |
#define RCQ_PAGE | ( | x | ) | (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) |
#define RCQ_TH_HI | ( | sc | ) | (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) |
#define RCQ_TH_LO | ( | sc | ) |
#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) |
#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) |
#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) |
#define REG_RD16 | ( | sc, | |
offset | |||
) |
#define REG_RD32 | ( | sc, | |
offset | |||
) |
#define REG_RD8 | ( | sc, | |
offset | |||
) |
#define REG_RD_DMAE | ( | sc, | |
offset, | |||
valp, | |||
len32 | |||
) |
#define REG_RD_DMAE_LEN | ( | sc, | |
offset, | |||
valp, | |||
len32 | |||
) | REG_RD_DMAE(sc, offset, valp, len32) |
#define REG_RD_IND | ( | sc, | |
offset | |||
) | bxe_reg_rd_ind(sc, offset) |
#define REG_WR16 | ( | sc, | |
offset, | |||
val | |||
) |
#define REG_WR32 | ( | sc, | |
offset, | |||
val | |||
) |
#define REG_WR8 | ( | sc, | |
offset, | |||
val | |||
) |
#define REG_WR_DMAE | ( | sc, | |
offset, | |||
valp, | |||
len32 | |||
) |
#define REG_WR_DMAE_LEN | ( | sc, | |
offset, | |||
valp, | |||
len32 | |||
) | REG_WR_DMAE(sc, offset, valp, len32) |
#define REG_WR_IND | ( | sc, | |
offset, | |||
val | |||
) | bxe_reg_wr_ind(sc, offset, val) |
#define RX_BD_IDX | ( | x | ) | ((x) & RX_BD_PER_PAGE_MASK) |
#define RX_BD_MAX (RX_BD_TOTAL - 1) |
#define RX_BD_NEXT | ( | x | ) |
#define RX_BD_PAGE | ( | x | ) | (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) |
#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) |
#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) |
#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) |
#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) |
#define RX_SGE | ( | x | ) | ((x) & RX_SGE_MAX) |
#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) |
#define RX_SGE_MASK_LEN ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) |
#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
#define RX_SGE_MAX (RX_SGE_TOTAL - 1) |
#define RX_SGE_NEXT | ( | x | ) |
#define RX_SGE_NEXT_MASK_ELEM | ( | el | ) | (((el) + 1) & RX_SGE_MASK_LEN_MASK) |
#define RX_SGE_ONES_MASK | ( | idx | ) | (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) |
#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) |
#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) |
#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) |
#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) |
#define SC_FW_MB_IDX | ( | sc | ) | SC_FW_MB_IDX_VN(sc, SC_VN(sc)) |
#define SC_FW_MB_IDX_VN | ( | sc, | |
vn | |||
) |
#define SC_MAX_VN_NUM | ( | sc | ) | PFS_PER_PORT(sc) |
#define SET_FLAG | ( | value, | |
mask, | |||
flag | |||
) |
#define SGE_MASK_CLEAR_BIT | ( | fp, | |
idx | |||
) |
#define SGE_MASK_SET_BIT | ( | fp, | |
idx | |||
) |
#define SGE_PAGE_ALIGN | ( | addr | ) | BCM_PAGE_ALIGN(addr) |
#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT |
#define SGE_PAGE_SIZE BCM_PAGE_SIZE |
#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) |
#define SGE_TH_HI | ( | sc | ) | (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) |
#define SGE_TH_LO | ( | sc | ) | (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) |
#define SHMEM2_ADDR | ( | sc, | |
field | |||
) | (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) |
#define SHMEM2_HAS | ( | sc, | |
field | |||
) |
#define SHMEM2_RD | ( | sc, | |
field | |||
) | REG_RD(sc, SHMEM2_ADDR(sc, field)) |
#define SHMEM2_WR | ( | sc, | |
field, | |||
val | |||
) | REG_WR(sc, SHMEM2_ADDR(sc, field), val) |
#define SHMEM_ADDR | ( | sc, | |
field | |||
) | (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) |
#define SHMEM_RD | ( | sc, | |
field | |||
) | REG_RD(sc, SHMEM_ADDR(sc, field)) |
#define SHMEM_RD16 | ( | sc, | |
field | |||
) | REG_RD16(sc, SHMEM_ADDR(sc, field)) |
#define SHMEM_WR | ( | sc, | |
field, | |||
val | |||
) | REG_WR(sc, SHMEM_ADDR(sc, field), val) |
#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ |
#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) |
#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ |
#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) |
#define SRC_T2_SZ SRC_ILT_SZ |
#define SUB_S16 | ( | a, | |
b | |||
) | (int16_t)((int16_t)(a) - (int16_t)(b)) |
#define SW_CID | ( | x | ) | (le32toh(x) & BXE_SWCID_MASK) |
#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) |
#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) |
#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ |
#define TM_ILT_SZ (8 * TM_CONN_NUM) |
#define TX_BD_IDX | ( | x | ) | ((x) & TX_BD_USABLE_PER_PAGE) |
#define TX_BD_MAX (TX_BD_TOTAL - 1) |
#define TX_BD_NEXT | ( | x | ) |
#define TX_BD_PAGE | ( | x | ) | (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) |
#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) |
#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) |
#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) |
#define USES_WARPCORE | ( | sc | ) | (CHIP_IS_E3(sc)) |
#define VIRT_WR_DMAE_LEN | ( | sc, | |
data, | |||
addr, | |||
len32, | |||
le32_swap | |||
) |
#define VNICS_PER_PATH | ( | sc | ) |
#define VNICS_PER_PORT | ( | sc | ) | ((sc)->devinfo.mf_info.vnics_per_port) |
anonymous enum |
anonymous enum |
anonymous enum |
__FBSDID | ( | "$FreeBSD$" | ) |
|
inlinestatic |
Definition at line 2412 of file bxe.h.
References bxe_hc_ack_int(), bxe_igu_ack_int(), bxe_softc::devinfo, bxe_devinfo::int_block, and INT_BLOCK_HC.
Referenced by bxe_igu_int_enable(), and bxe_intr_legacy().
|
inlinestatic |
Definition at line 2363 of file bxe.h.
References ATTENTION_ID, bxe_hc_ack_sb(), bxe_igu_ack_sb(), CHIP_INT_MODE_IS_BC, bxe_softc::devinfo, bxe_softc::igu_dsb_id, IGU_SEG_ACCESS_ATTN, IGU_SEG_ACCESS_DEF, bxe_devinfo::int_block, and INT_BLOCK_HC.
Referenced by bxe_handle_fp_tq(), bxe_handle_sp_tq(), bxe_init_def_sb(), bxe_init_hw_func(), bxe_intr_fp(), bxe_intr_legacy(), bxe_intr_sp(), bxe_setup_queue(), and bxe_task_fp().
void bxe_clear_bit | ( | int | nr, |
volatile unsigned long * | addr | ||
) |
Definition at line 818 of file bxe.c.
References addr.
Referenced by bxe_handle_rx_mode_eqe().
int bxe_cmpxchg | ( | volatile int * | addr, |
int | old, | ||
int | new | ||
) |
int bxe_dma_alloc | ( | struct bxe_softc * | sc, |
bus_size_t | size, | ||
struct bxe_dma * | dma, | ||
const char * | msg | ||
) |
Definition at line 898 of file bxe.c.
References BCM_PAGE_SIZE, BLOGE, bxe_dma_map_addr(), bxe_dma::map, bxe_dma::msg, bxe_softc::parent_dma_tag, bxe_dma::sc, size, bxe_dma::size, bxe_dma::tag, and bxe_dma::vaddr.
Referenced by bxe_alloc_fw_stats_mem(), bxe_alloc_hsi_mem(), and bxe_alloc_mem().
Definition at line 966 of file bxe.c.
References DBASSERT, bxe_dma::map, bxe_dma::sc, bxe_dma::size, bxe_dma::tag, and bxe_dma::vaddr.
Referenced by bxe_alloc_hsi_mem(), bxe_free_fw_stats_mem(), bxe_free_hsi_mem(), and bxe_free_mem().
uint32_t bxe_dmae_opcode | ( | struct bxe_softc * | sc, |
uint8_t | src_type, | ||
uint8_t | dst_type, | ||
uint8_t | with_comp, | ||
uint8_t | comp_type | ||
) |
Definition at line 1537 of file bxe.c.
References bxe_dmae_opcode_add_comp(), DMAE_CMD_DST_RESET, DMAE_CMD_DST_SHIFT, DMAE_CMD_DST_VN_SHIFT, DMAE_CMD_E1HVN_SHIFT, DMAE_CMD_ENDIANITY_B_DW_SWAP, DMAE_CMD_ENDIANITY_DW_SWAP, DMAE_CMD_ERR_POLICY_SHIFT, DMAE_CMD_PORT_0, DMAE_CMD_PORT_1, DMAE_CMD_SRC_RESET, DMAE_CMD_SRC_SHIFT, DMAE_COM_SET_ERR, dmae_cmd::opcode, SC_PORT, and SC_VN.
Referenced by bxe_func_stats_init(), bxe_hw_stats_post(), bxe_port_stats_base_init(), bxe_port_stats_init(), bxe_port_stats_stop(), bxe_prep_dmae_with_comp(), and bxe_stats_pmf_update().
uint32_t bxe_dmae_opcode_add_comp | ( | uint32_t | opcode, |
uint8_t | comp_type | ||
) |
Definition at line 1523 of file bxe.c.
References DMAE_CMD_C_DST_SHIFT, DMAE_CMD_C_TYPE_ENABLE, and dmae_cmd::opcode.
Referenced by bxe_dmae_opcode(), bxe_port_stats_stop(), and bxe_stats_pmf_update().
uint32_t bxe_dmae_opcode_clr_src_reset | ( | uint32_t | opcode | ) |
Definition at line 1531 of file bxe.c.
References DMAE_CMD_SRC_RESET, and dmae_cmd::opcode.
Referenced by bxe_hw_stats_post().
void bxe_dump_mbuf_data | ( | struct bxe_softc * | sc, |
char * | pTag, | ||
struct mbuf * | m, | ||
uint8_t | contents | ||
) |
Definition at line 230 of file bxe_debug.c.
References BLOGI, and bxe_prev_mtx.
Referenced by bxe_dump_mbuf().
void bxe_dump_mem | ( | struct bxe_softc * | sc, |
char * | tag, | ||
uint8_t * | mem, | ||
uint32_t | len | ||
) |
Definition at line 192 of file bxe_debug.c.
References BLOGI, and bxe_prev_mtx.
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inlinestatic |
Definition at line 2388 of file bxe.h.
References COMMAND_REG_SIMD_MASK, HC_REG_COMMAND_REG, REG_RD, and SC_PORT.
Referenced by bxe_ack_int().
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inlinestatic |
Definition at line 2336 of file bxe.h.
References bxe_softc::bar, COMMAND_REG_INT_ACK, bxe_bar::handle, HC_REG_COMMAND_REG, REG_WR, SC_PORT, and bxe_bar::tag.
Referenced by bxe_ack_sb().
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inlinestatic |
Definition at line 2399 of file bxe.h.
References BAR_IGU_INTMEM, BLOGD, DBG_INTR, IGU_REG_SISR_MDPC_WMASK_LSB_UPPER, and REG_RD.
Referenced by bxe_ack_int().
void bxe_igu_ack_sb | ( | struct bxe_softc * | sc, |
uint8_t | igu_sb_id, | ||
uint8_t | segment, | ||
uint16_t | index, | ||
uint8_t | op, | ||
uint8_t | update | ||
) |
Definition at line 16511 of file bxe.c.
References bxe_igu_ack_sb_gen(), bxe_softc::igu_base_addr, and IGU_CMD_INT_ACK_BASE.
Referenced by bxe_ack_sb().
|
inlinestatic |
Definition at line 2309 of file bxe.h.
References bxe_softc::bar, BLOGD, DBG_INTR, bxe_bar::handle, IGU_REGULAR_BUPDATE_SHIFT, IGU_REGULAR_ENABLE_INT_SHIFT, IGU_REGULAR_SB_INDEX_SHIFT, IGU_REGULAR_SEGMENT_ACCESS_SHIFT, REG_WR, igu_regular::sb_id_and_flags, and bxe_bar::tag.
Referenced by bxe_igu_ack_sb().
Definition at line 1507 of file bxe.c.
References DMAE_REG_CMD_MEM, dmae_reg_go_c, and REG_WR.
Referenced by bxe_hw_stats_post(), and bxe_issue_dmae_with_comp().
void bxe_read_dmae | ( | struct bxe_softc * | sc, |
uint32_t | src_addr, | ||
uint32_t | len32 | ||
) |
Definition at line 1633 of file bxe.c.
References bxe_issue_dmae_with_comp(), bxe_panic, bxe_prep_dmae_with_comp(), bxe_reg_rd_ind(), BXE_SP, BXE_SP_MAPPING, CHIP_IS_E1, DBASSERT, DMAE_DST_PCI, bxe_softc::dmae_ready, DMAE_SRC_GRC, dmae_cmd::dst_addr_hi, dmae_cmd::dst_addr_lo, REG_RD, dmae_cmd::src_addr_hi, dmae_cmd::src_addr_lo, U64_HI, and U64_LO.
Referenced by bxe_init_hw_common(), bxe_init_hw_func(), and bxe_int_mem_test().
uint32_t bxe_reg_rd_ind | ( | struct bxe_softc * | sc, |
uint32_t | addr | ||
) |
Definition at line 998 of file bxe.c.
References addr, bxe_softc::dev, PCICFG_GRC_ADDRESS, PCICFG_GRC_DATA, and bxe_dma::sc.
Referenced by bxe_read_dmae().
void bxe_reg_wr_ind | ( | struct bxe_softc * | sc, |
uint32_t | addr, | ||
uint32_t | val | ||
) |
Definition at line 988 of file bxe.c.
References addr, bxe_softc::dev, PCICFG_GRC_ADDRESS, PCICFG_GRC_DATA, and bxe_dma::sc.
Referenced by ecore_reg_wr_ind().
void bxe_set_bit | ( | unsigned int | nr, |
volatile unsigned long * | addr | ||
) |
Definition at line 811 of file bxe.c.
References addr.
Referenced by bxe_chip_cleanup(), bxe_config_rss_pf(), bxe_del_all_macs(), bxe_fan_failure(), bxe_fill_accept_flags(), bxe_fill_report_data(), bxe_func_stop(), bxe_func_wait_started(), bxe_get_common_flags(), bxe_get_q_flags(), bxe_pf_q_prep_init(), bxe_reset_hw(), bxe_set_eth_mac(), bxe_set_mac_one(), bxe_set_q_rx_mode(), bxe_set_rx_mode(), bxe_set_storm_rx_mode(), bxe_setup_queue(), bxe_squeeze_objects(), and bxe_stop_queue().
void bxe_set_ctx_validation | ( | struct bxe_softc * | sc, |
struct eth_context * | cxt, | ||
uint32_t | cid | ||
) |
Definition at line 1733 of file bxe.c.
References CDU_REGION_NUMBER_UCM_AG, CDU_REGION_NUMBER_XCM_AG, CDU_RSRVD_VALUE_TYPE_A, ETH_CONNECTION_TYPE, HW_CID, eth_context::ustorm_ag_context, and eth_context::xstorm_ag_context.
int bxe_sp_post | ( | struct bxe_softc * | sc, |
int | command, | ||
int | cid, | ||
uint32_t | data_hi, | ||
uint32_t | data_lo, | ||
int | cmd_type | ||
) |
bxe_sp_post - place a single command on an SP ring
@sc: driver handle @command: command to place (e.g. SETUP, FILTER_RULES, etc.) @cid: SW CID the command is related to @data_hi: command private data address (high 32 bits) @data_lo: command private data address (low 32 bits) @cmd_type: command type (e.g. NONE, ETH)
SP data is handled as if it's always an address pair, thus data fields are not swapped to little endian in upper functions. Instead this function swaps data as if it's two uint32 fields.
Definition at line 2399 of file bxe.c.
References BLOGD, BLOGE, bxe_is_contextless_ramrod(), BXE_SP, bxe_sp_get_next(), BXE_SP_LOCK, BXE_SP_MAPPING, bxe_sp_prod_update(), BXE_SP_UNLOCK, spe_hdr_t::conn_and_cmd_data, bxe_softc::cq_spq_left, eth_spe::data, DBG_SP, bxe_softc::eq_spq_left, eth_spe::hdr, regpair_t::hi, HW_CID, regpair_t::lo, bxe_dma::paddr, SC_FUNC, SPE_HDR_T_CMD_ID_SHIFT, SPE_HDR_T_CONN_TYPE, SPE_HDR_T_CONN_TYPE_SHIFT, SPE_HDR_T_FUNCTION_ID, SPE_HDR_T_FUNCTION_ID_SHIFT, bxe_softc::spq, bxe_softc::spq_dma, bxe_softc::spq_prod_bd, bxe_softc::spq_prod_idx, spe_hdr_t::type, U64_HI, U64_LO, and eth_specific_data::update_data_addr.
Referenced by bxe_storm_stats_post().
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inlinestatic |
Definition at line 2434 of file bxe.h.
References CHIP_IS_E1x, bxe_fastpath::cl_id, bxe_softc::fp, FP_SB_MAX_E1x, bxe_fastpath::sc, and SC_PORT.
Referenced by bxe_pf_q_prep_general(), and bxe_prep_fw_stats_req().
int bxe_test_and_clear_bit | ( | int | nr, |
volatile unsigned long * | addr | ||
) |
Definition at line 838 of file bxe.c.
References addr.
Referenced by bxe_handle_rx_mode_eqe(), and bxe_link_report_locked().
int bxe_test_and_set_bit | ( | int | nr, |
volatile unsigned long * | addr | ||
) |
int bxe_test_bit | ( | int | nr, |
volatile unsigned long * | addr | ||
) |
Definition at line 804 of file bxe.c.
References addr.
Referenced by bxe_chip_cleanup(), bxe_link_report_locked(), bxe_set_mac_one(), and bxe_set_rx_mode().
void bxe_update_coalesce_sb_index | ( | struct bxe_softc * | sc, |
uint8_t | fw_sb_id, | ||
uint8_t | sb_index, | ||
uint8_t | disable, | ||
uint16_t | usec | ||
) |
Definition at line 1791 of file bxe.c.
References bxe_storm_memset_hc_disable(), bxe_storm_memset_hc_timeout(), and SC_PORT.
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inlinestatic |
Definition at line 2302 of file bxe.h.
References bxe_fastpath::fp_hc_idx, bxe_fastpath::sb_running_index, and SM_RX_ID.
Referenced by bxe_handle_fp_tq(), bxe_init_eth_fp(), and bxe_task_fp().
void bxe_write_dmae | ( | struct bxe_softc * | sc, |
bus_addr_t | dma_addr, | ||
uint32_t | dst_addr, | ||
uint32_t | len32 | ||
) |
Definition at line 1672 of file bxe.c.
References bxe_issue_dmae_with_comp(), bxe_panic, bxe_prep_dmae_with_comp(), BXE_SP, CHIP_IS_E1, DBASSERT, DMAE_DST_GRC, bxe_softc::dmae_ready, DMAE_SRC_PCI, dmae_cmd::dst_addr_hi, dmae_cmd::dst_addr_lo, ecore_init_ind_wr(), ecore_init_str_wr(), dmae_cmd::src_addr_hi, dmae_cmd::src_addr_lo, U64_HI, and U64_LO.
Referenced by bxe_init_hw_func(), and bxe_write_dmae_phys_len().
void bxe_write_dmae_phys_len | ( | struct bxe_softc * | sc, |
bus_addr_t | phys_addr, | ||
uint32_t | addr, | ||
uint32_t | len | ||
) |
Definition at line 1709 of file bxe.c.
References addr, bxe_write_dmae(), DMAE_LEN32_WR_MAX, and offset.
Referenced by ecore_write_dmae_phys_len().
void ecore_init_e1_firmware | ( | struct bxe_softc * | sc | ) |
Definition at line 31198 of file 57710_init_values.c.
References csem_int_table_data_e1, csem_pram_data_e1, INIT_CSEM_INT_TABLE_DATA, INIT_CSEM_PRAM_DATA, INIT_DATA, init_data_e1, INIT_OPS, init_ops_e1, INIT_OPS_OFFSETS, init_ops_offsets_e1, INIT_TSEM_INT_TABLE_DATA, INIT_TSEM_PRAM_DATA, INIT_USEM_INT_TABLE_DATA, INIT_USEM_PRAM_DATA, INIT_XSEM_INT_TABLE_DATA, INIT_XSEM_PRAM_DATA, tsem_int_table_data_e1, tsem_pram_data_e1, usem_int_table_data_e1, usem_pram_data_e1, xsem_int_table_data_e1, and xsem_pram_data_e1.
Referenced by bxe_init_firmware().
void ecore_init_e1h_firmware | ( | struct bxe_softc * | sc | ) |
Definition at line 32815 of file 57711_init_values.c.
References csem_int_table_data_e1h, csem_pram_data_e1h, INIT_CSEM_INT_TABLE_DATA, INIT_CSEM_PRAM_DATA, INIT_DATA, init_data_e1h, INIT_OPS, init_ops_e1h, INIT_OPS_OFFSETS, init_ops_offsets_e1h, INIT_TSEM_INT_TABLE_DATA, INIT_TSEM_PRAM_DATA, INIT_USEM_INT_TABLE_DATA, INIT_USEM_PRAM_DATA, INIT_XSEM_INT_TABLE_DATA, INIT_XSEM_PRAM_DATA, tsem_int_table_data_e1h, tsem_pram_data_e1h, usem_int_table_data_e1h, usem_pram_data_e1h, xsem_int_table_data_e1h, and xsem_pram_data_e1h.
Referenced by bxe_init_firmware().
void ecore_init_e2_firmware | ( | struct bxe_softc * | sc | ) |
Definition at line 57651 of file 57712_init_values.c.
References csem_int_table_data_e2, csem_pram_data_e2, INIT_CSEM_INT_TABLE_DATA, INIT_CSEM_PRAM_DATA, INIT_DATA, init_data_e2, INIT_OPS, init_ops_e2, INIT_OPS_OFFSETS, init_ops_offsets_e2, INIT_TSEM_INT_TABLE_DATA, INIT_TSEM_PRAM_DATA, INIT_USEM_INT_TABLE_DATA, INIT_USEM_PRAM_DATA, INIT_XSEM_INT_TABLE_DATA, INIT_XSEM_PRAM_DATA, tsem_int_table_data_e2, tsem_pram_data_e2, usem_int_table_data_e2, usem_pram_data_e2, xsem_int_table_data_e2, and xsem_pram_data_e2.
Referenced by bxe_init_firmware().
void ecore_storm_memset_struct | ( | struct bxe_softc * | sc, |
uint32_t | addr, | ||
size_t | size, | ||
uint32_t * | data | ||
) |
Definition at line 18624 of file bxe.c.
References addr, REG_WR, and size.
Referenced by __storm_memset_mac_filters(), storm_memset_cmng(), storm_memset_eq_data(), and storm_memset_func_cfg().
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inlinestatic |
Definition at line 2423 of file bxe.h.
References SC_PORT.
Referenced by storm_memset_cmng().
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inlinestatic |
Definition at line 2281 of file bxe.h.
References REG_RD.
Referenced by bxe_init_hw_common().
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static |
Definition at line 2001 of file bxe.h.
Referenced by bxe_hw_stats_post(), bxe_poll_hw_usage_counters(), bxe_port_stats_init(), bxe_port_stats_stop(), bxe_post_dmae(), and bxe_stats_pmf_update().