32#ifndef ECORE_INIT_OPS_H
33#define ECORE_INIT_OPS_H
51 const uint32_t *data, uint32_t len)
55 for (i = 0; i < len; i++)
60 const uint32_t *data, uint32_t len)
64 for (i = 0; i < len; i++)
84 uint32_t len, uint8_t wb)
87 uint32_t buf_len32 = buf_len/4;
92 for (i = 0; i < len; i += buf_len32) {
93 uint32_t cur_len = min(buf_len32, len - i);
114 const uint32_t *data, uint32_t len64)
117 uint32_t len = len64*2;
122 data64 =
HILO_U64((*(data + 1)), (*data));
125 for (i = 0; i < len64; i++) {
126 uint64_t *pdata = ((uint64_t *)(
GUNZIP_BUF(sc))) + i;
131 for (i = 0; i < len; i += buf_len32) {
132 uint32_t cur_len = min(buf_len32, len - i);
146#define IF_IS_INT_TABLE_ADDR(base, addr) \
147 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
149#define IF_IS_PRAM_ADDR(base, addr) \
150 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
183 const uint32_t *data, uint32_t len)
197#ifndef FW_ZIP_SUPPORT
200 const uint8_t *data = NULL;
221 uint32_t wb_write[2];
223 wb_write[0] = val_lo;
224 wb_write[1] = val_hi;
231 const uint8_t *data = NULL;
243 for (i = 0; i < len; i++)
259 uint32_t op_idx, op_type,
addr, len;
260 const uint32_t *data, *data_base;
263 if (op_start == op_end)
268 for (op_idx = op_start; op_idx < op_end; op_idx++) {
272 op_type = op->
raw.
op;
294#ifndef FW_ZIP_SUPPORT
370 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
371 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
372 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
373 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
374 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
375 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
376 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
377 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
378 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
379{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
380 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
381 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
382 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
383 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
384 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
385 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
386 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
387 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
388 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
389{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
390 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
391 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
392 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
393 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
394 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
395 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
396 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
397 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
398 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
403 { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
404 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
405 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
406 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
407 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
408 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
409 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
410 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
411 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
412{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
413 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
414 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
415 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
512 ECORE_MSG(sc,
"read order of %d order adjusted to %d\n",
517 ECORE_MSG(sc,
"write order of %d order adjusted to %d\n",
522 ECORE_MSG(sc,
"write order adjusted to 1 for FPGA\n");
525 ECORE_MSG(sc,
"read order %d write order %d\n", r_order, w_order);
600 val = ((w_order == 0) ? 2 : 3);
617#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
637#define ILT_MEMOP_ALLOC 0
638#define ILT_MEMOP_FREE 1
645#define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
646#define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
647#define ILT_RANGE(f, l) (((l) << 10) | f)
671 if (!ilt || !ilt->
lines)
677 for (rc = 0, i = ilt_cli->
start; i <= ilt_cli->
end && !rc; i++) {
721 struct ecore_ilt *ilt,
int idx, uint8_t initop)
742 uint32_t ilt_start, uint8_t initop)
744 uint32_t start_reg = 0;
745 uint32_t end_reg = 0;
768 (ilt_start + ilt_cli->
end)));
788 REG_WR(sc, start_reg, (ilt_start + ilt_cli->
start));
789 REG_WR(sc, end_reg, (ilt_start + ilt_cli->
end));
803 for (i = ilt_cli->
start; i <= ilt_cli->
end; i++)
819 int cli_num, uint8_t initop)
843 uint32_t psz_reg, uint8_t initop)
881#define QM_QUEUES_PER_FUNC 16
882#define QM_INIT_MIN_CID_COUNT 31
883#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
897 qm_cid_count/16 - 1);
906 uint32_t base_reg, uint32_t reg)
909 uint32_t wb_data[2] = {0, 0};
911 REG_WR(sc, base_reg + i*4,
953 for (i = 0; i < src_cid_count-1; i++)
954 t2[i].next = (uint64_t)(t2_mapping +
964 U64_LO((uint64_t)t2_mapping +
965 (src_cid_count-1) *
sizeof(
struct src_ent)),
966 U64_HI((uint64_t)t2_mapping +
967 (src_cid_count-1) *
sizeof(
struct src_ent)));
#define INIT_XSEM_INT_TABLE_DATA(sc)
#define INIT_OPS_OFFSETS(sc)
#define INIT_USEM_PRAM_DATA(sc)
#define INIT_MODE_FLAGS(sc)
#define INIT_TSEM_PRAM_DATA(sc)
#define INIT_CSEM_PRAM_DATA(sc)
#define INIT_XSEM_PRAM_DATA(sc)
#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap)
#define REG_WR_DMAE_LEN(sc, offset, valp, len32)
#define CHIP_REV_IS_FPGA(sc)
#define CONFIGURE_NIC_MODE(sc)
#define REG_RD(sc, offset)
#define INIT_CSEM_INT_TABLE_DATA(sc)
#define INIT_TSEM_INT_TABLE_DATA(sc)
#define REG_WR(sc, offset, val)
#define INIT_USEM_INT_TABLE_DATA(sc)
#define GUNZIP_OUTLEN(sc)
#define ILT_CLIENT_SKIP_MEM
#define ILT_CLIENT_SKIP_INIT
#define BLOCK_OPS_IDX(block, stage, end)
static const struct arb_line read_arb_addr[NUM_RD_Q-1]
static void ecore_ilt_init_client_psz(struct bxe_softc *sc, int cli_num, uint32_t psz_reg, uint8_t initop)
static void ecore_init_fw(struct bxe_softc *sc, uint32_t addr, uint32_t len)
static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD+1]
static void ecore_init_str_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data, uint32_t len)
static void ecore_ilt_client_init_op(struct bxe_softc *sc, struct ilt_client_info *ilt_cli, uint8_t initop)
static void ecore_wr_64(struct bxe_softc *sc, uint32_t reg, uint32_t val_lo, uint32_t val_hi)
static void ecore_ilt_client_init_op_ilt(struct bxe_softc *sc, struct ecore_ilt *ilt, struct ilt_client_info *ilt_cli, uint8_t initop)
static int ecore_ilt_line_mem_op(struct bxe_softc *sc, struct ilt_line *line, uint32_t size, uint8_t memop)
static void ecore_ilt_init_op(struct bxe_softc *sc, uint8_t initop)
static void ecore_init_fill(struct bxe_softc *sc, uint32_t addr, int fill, uint32_t len, uint8_t wb)
static void ecore_qm_init_ptr_table(struct bxe_softc *sc, int qm_cid_count, uint8_t initop)
static void ecore_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len, uint32_t blob_off)
static const struct arb_line write_arb_addr[NUM_WR_Q-1]
static int ecore_ilt_client_mem_op(struct bxe_softc *sc, int cli_num, uint8_t memop)
static void ecore_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val)
static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD+1]
static const uint8_t * ecore_sel_blob(struct bxe_softc *sc, uint32_t addr, const uint8_t *data)
static void ecore_init_wr_64(struct bxe_softc *sc, uint32_t addr, const uint32_t *data, uint32_t len64)
static void ecore_ilt_client_id_init_op(struct bxe_softc *sc, int cli_num, uint8_t initop)
#define QM_QUEUES_PER_FUNC
static void ecore_init_ind_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data, uint32_t len)
static void ecore_ilt_boundry_init_op(struct bxe_softc *sc, struct ilt_client_info *ilt_cli, uint32_t ilt_start, uint8_t initop)
#define IF_IS_INT_TABLE_ADDR(base, addr)
static int ecore_ilt_mem_op(struct bxe_softc *sc, uint8_t memop)
static void ecore_init_wr_wb(struct bxe_softc *sc, uint32_t addr, const uint32_t *data, uint32_t len)
static void ecore_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
static void ecore_qm_set_ptr_table(struct bxe_softc *sc, int qm_cid_count, uint32_t base_reg, uint32_t reg)
static void ecore_init_pxp_arb(struct bxe_softc *sc, int r_order, int w_order)
static int ecore_ilt_mem_op_cnic(struct bxe_softc *sc, uint8_t memop)
static void ecore_ilt_line_init_op(struct bxe_softc *sc, struct ecore_ilt *ilt, int idx, uint8_t initop)
static void ecore_ilt_init_page_size(struct bxe_softc *sc, uint8_t initop)
static void ecore_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
#define IF_IS_PRAM_ADDR(base, addr)
static int ecore_gunzip(struct bxe_softc *sc, const uint8_t *zbuf, int len)
static void ecore_ilt_init_op_cnic(struct bxe_softc *sc, uint8_t initop)
static void ecore_ilt_line_wr(struct bxe_softc *sc, int abs_idx, ecore_dma_addr_t page_mapping)
static void ecore_qm_init_cid_count(struct bxe_softc *sc, int qm_cid_count, uint8_t initop)
#define PCIE_REG_PCIER_TL_HDR_FC_ST
static void ecore_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len, uint8_t wb)
static void ecore_write_dmae_phys_len(struct bxe_softc *sc, ecore_dma_addr_t phys_addr, uint32_t addr, uint32_t len)
#define PXP2_REG_RQ_BW_RD_L12
#define PXP2_REG_RQ_ONCHIP_AT
#define PXP2_REG_RQ_BW_RD_ADD13
#define PXP2_REG_RQ_BW_RD_ADD23
#define PXP2_REG_RQ_BW_WR_UBOUND30
#define PXP2_REG_RQ_BW_RD_UBOUND14
#define PXP2_REG_RQ_BW_RD_UBOUND13
#define PXP2_REG_PSWRQ_BW_ADD28
#define PXP2_REG_WR_TSDM_MPS
#define PXP2_REG_WR_TM_MPS
#define PXP2_REG_RQ_BW_RD_L15
#define PXP2_REG_RQ_BW_RD_UBOUND20
#define PXP2_REG_PSWRQ_BW_L8
#define PXP2_REG_RQ_BW_RD_L19
#define USEM_REG_INT_TABLE
#define PXP2_REG_PSWRQ_BW_ADD1
#define PXP2_REG_PSWRQ_BW_L2
#define PXP2_REG_RQ_BW_RD_L18
#define PXP2_REG_RQ_BW_RD_L4
#define PXP2_REG_PSWRQ_BW_UB10
#define PXP2_REG_WR_USDMDP_TH
#define XSEM_REG_INT_TABLE
#define PXP2_REG_RQ_BW_RD_UBOUND12
#define QM_REG_PTRTBL_EXT_A
#define PXP2_REG_RQ_BW_RD_UBOUND0
#define PXP2_REG_RQ_BW_WR_ADD30
#define PXP2_REG_RQ_PDR_LIMIT
#define PXP2_REG_PSWRQ_BW_ADD3
#define PXP2_REG_RQ_BW_RD_ADD12
#define PXP2_REG_RQ_BW_RD_L20
#define PXP2_REG_RQ_BW_RD_UBOUND19
#define PXP2_REG_PSWRQ_BW_UB9
#define PXP2_REG_RQ_BW_RD_UBOUND27
#define PXP2_REG_WR_XSDM_MPS
#define PXP2_REG_RQ_RD_MBS0
#define PXP2_REG_RQ_SRC_P_SIZE
#define PXP2_REG_RQ_RD_MBS1
#define PXP2_REG_PSWRQ_BW_ADD9
#define SRC_REG_COUNTFREE0
#define PXP2_REG_RQ_CDU_P_SIZE
#define PXP2_REG_RQ_BW_RD_UBOUND17
#define PXP2_REG_PSWRQ_BW_UB8
#define PXP2_REG_RQ_BW_RD_ADD14
#define PXP2_REG_WR_DMAE_MPS
#define PXP2_REG_RQ_BW_RD_L5
#define PXP2_REG_RQ_WR_MBS1
#define PXP2_REG_RQ_BW_RD_ADD24
#define PXP2_REG_WR_QM_MPS
#define PXP2_REG_PSWRQ_SRC0_L2P
#define PXP2_REG_RQ_BW_RD_ADD15
#define PXP2_REG_WR_CDU_MPS
#define PXP2_REG_RQ_BW_RD_UBOUND23
#define PXP2_REG_RQ_BW_RD_L13
#define PXP2_REG_RQ_TM_FIRST_ILT
#define PXP2_REG_PSWRQ_BW_L9
#define PXP2_REG_RQ_BW_RD_UBOUND26
#define PXP2_REG_PSWRQ_QM0_L2P
#define PXP2_REG_RQ_BW_RD_UBOUND22
#define PXP2_REG_RQ_BW_RD_L0
#define PXP2_REG_RQ_BW_RD_L26
#define PXP2_REG_RQ_BW_RD_ADD26
#define PXP2_REG_RQ_BW_RD_UBOUND15
#define QM_REG_BASEADDR_EXT_A
#define PXP2_REG_PSWRQ_BW_UB2
#define PXP2_REG_PSWRQ_BW_ADD10
#define PXP2_REG_RQ_BW_RD_L14
#define PXP2_REG_PSWRQ_BW_UB11
#define TSEM_REG_INT_TABLE
#define PXP2_REG_RQ_BW_RD_UBOUND5
#define PXP2_REG_RQ_TM_P_SIZE
#define PXP2_REG_WR_SRC_MPS
#define PXP2_REG_PSWRQ_BW_UB28
#define PXP2_REG_RQ_BW_RD_L16
#define PXP2_REG_RQ_BW_RD_UBOUND25
#define PXP2_REG_PSWRQ_CDU0_L2P
#define PXP2_REG_RQ_BW_RD_L25
#define PXP2_REG_PSWRQ_TM0_L2P
#define PXP2_REG_RQ_BW_RD_ADD22
#define PXP2_REG_PSWRQ_BW_L28
#define PXP2_REG_PSWRQ_BW_L10
#define PXP2_REG_RQ_QM_FIRST_ILT
#define PXP2_REG_RQ_BW_RD_ADD17
#define PXP2_REG_RQ_BW_RD_UBOUND4
#define PXP2_REG_RQ_BW_WR_UBOUND29
#define PXP2_REG_WR_HC_MPS
#define PXP2_REG_RQ_BW_RD_ADD27
#define PXP2_REG_WR_CSDM_MPS
#define PXP2_REG_PSWRQ_BW_L7
#define PXP2_REG_RQ_BW_RD_UBOUND24
#define CSEM_REG_INT_TABLE
#define PXP2_REG_PSWRQ_BW_ADD8
#define PXP2_REG_WR_USDM_MPS
#define PXP2_REG_RQ_BW_RD_ADD19
#define PXP2_REG_RQ_BW_WR_L30
#define SRC_REG_LASTFREE0
#define PXP2_REG_RQ_BW_WR_L29
#define PXP2_REG_PSWRQ_BW_ADD6
#define PXP2_REG_PSWRQ_BW_L11
#define PXP2_REG_PSWRQ_BW_UB1
#define PXP2_REG_PSWRQ_BW_L6
#define PXP2_REG_RQ_ONCHIP_AT_B0
#define PXP2_REG_RQ_BW_RD_L24
#define PXP2_REG_RQ_BW_RD_L17
#define PXP2_REG_RQ_SRC_FIRST_ILT
#define PXP2_REG_RQ_BW_RD_ADD20
#define PXP2_REG_RQ_BW_RD_L23
#define PXP2_REG_RQ_BW_RD_ADD25
#define PXP2_REG_PSWRQ_BW_ADD7
#define PXP2_REG_RQ_CDU_FIRST_ILT
#define PXP2_REG_RQ_QM_P_SIZE
#define PXP2_REG_RQ_TM_LAST_ILT
#define PXP2_REG_PSWRQ_BW_L3
#define PXP2_REG_PSWRQ_BW_UB3
#define PXP2_REG_RQ_QM_LAST_ILT
#define PXP2_REG_RQ_BW_RD_ADD5
#define PXP2_REG_PSWRQ_BW_UB7
#define PXP2_REG_PSWRQ_BW_L1
#define PXP2_REG_PGL_TAGS_LIMIT
#define PXP2_REG_WR_DBG_MPS
#define PXP2_REG_RQ_CDU_LAST_ILT
#define PXP2_REG_RQ_BW_RD_UBOUND16
#define PXP2_REG_RQ_BW_RD_UBOUND18
#define PXP2_REG_PSWRQ_BW_UB6
#define PXP2_REG_RQ_SRC_LAST_ILT
#define PXP2_REG_PSWRQ_BW_ADD11
#define PXP2_REG_RQ_BW_RD_ADD0
#define PXP2_REG_RQ_BW_RD_ADD16
#define PXP2_REG_RQ_BW_WR_ADD29
#define PXP2_REG_PSWRQ_BW_WR
#define PXP2_REG_RQ_BW_RD_L27
#define SRC_REG_FIRSTFREE0
#define PXP2_REG_RQ_BW_RD_L22
#define PXP2_REG_RQ_WR_MBS0
#define PXP2_REG_RQ_BW_RD_ADD4
#define PXP2_REG_PSWRQ_BW_RD
#define PXP2_REG_PSWRQ_BW_ADD2
#define PXP2_REG_RQ_BW_RD_ADD18
#define ECORE_ILT_FREE(x, y, size)
bus_addr_t ecore_dma_addr_t
#define ECORE_MSG(sc, m,...)
#define ECORE_ILT_ZALLOC(x, y, size)
#define ECORE_CPU_TO_LE32(x)
#define ECORE_MEMSET(_a, _c, _s)
struct ilt_client_info clients[4]
ecore_dma_addr_t page_mapping
struct op_if_mode if_mode
struct op_arr_write arr_wr