33#include "ar9002/ar9280v1.ini"
34#include "ar9002/ar9280v2.ini"
71 const struct ieee80211_channel *chan);
83 .totalSizeDesired = { -55, -55, -55, -55, -62 },
84 .coarseHigh = { -14, -14, -14, -14, -12 },
85 .coarseLow = { -64, -64, -64, -64, -70 },
86 .firpwr = { -78, -78, -78, -78, -80 },
87 .maxSpurImmunityLevel = 7,
88 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
90 .firstep = { 0, 4, 8 },
112 chan !=
AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) {
119 if (IEEE80211_IS_CHAN_HALF(chan))
121 else if (IEEE80211_IS_CHAN_QUARTER(chan))
126 if (IEEE80211_IS_CHAN_HALF(chan))
128 else if (IEEE80211_IS_CHAN_QUARTER(chan))
130 if (IEEE80211_IS_CHAN_5GHZ(chan))
144#define EEP_MINOR(_ah) \
145 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
162 int8_t pwr_table_offset;
166 __func__, sc, (
void*) st, (
void*) sh);
172 "%s: cannot allocate memory for state block\n", __func__);
233 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
247 ar9280PciePhy_clkreq_always_on_L1_v2, 2);
249 ar9280Modes_fast_clock_v2, 3);
254 ar9280PciePhy_v1, 2);
297 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
298 "this driver\n", __func__,
321 printf(
"[ath] enabling AN_TOP2_FIXUP\n");
322 AH5416(ah)->ah_need_an_top2_fixup = 1;
331 ath_hal_printf(ah,
"[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
340 ar9280Modes_backoff_13db_rxgain_v2, 6);
344 ar9280Modes_backoff_23db_rxgain_v2, 6);
348 ar9280Modes_original_rxgain_v2, 6);
362 ar9280Modes_high_power_tx_gain_v2, 6);
366 ar9280Modes_original_tx_gain_v2, 6);
385 "%s: error getting mac address from EEPROM\n", __func__);
480 val &= (~AR_WA_D3_L1_DISABLE);
496 u_int modesIndex, freqIndex;
503 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
505 if (IEEE80211_IS_CHAN_HT40(chan))
507 else if (IEEE80211_IS_CHAN_108G(chan))
513 if (IEEE80211_IS_CHAN_HT40(chan) ||
514 IEEE80211_IS_CHAN_TURBO(chan))
529 ia = &
AH5212(ah)->ah_ini_modes;
532 modesIndex, regWrites);
535 for (i = 0; i < ia->
rows; i++) {
540 val &= ~AR_AN_TOP2_PWDCLKIND;
545 if (reg >= 0x7800 && reg < 0x7900)
553 modesIndex, regWrites);
555 modesIndex, regWrites);
564 modesIndex, regWrites);
568#define AR_BASE_FREQ_2GHZ 2300
569#define AR_BASE_FREQ_5GHZ 4900
570#define AR_SPUR_FEEQ_BOUND_HT40 19
571#define AR_SPUR_FEEQ_BOUND_HT20 10
580 static int inc[4] = { 0, 100, 0, 0 };
585 int bb_spur_off, spur_subchannel_sd;
587 int spur_delta_phase;
589 int upper, lower, cur_vit_mask;
599 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
622 cur_bb_spur = cur_bb_spur - freq;
624 if (IEEE80211_IS_CHAN_HT40(chan)) {
627 bb_spur = cur_bb_spur;
632 bb_spur = cur_bb_spur;
675 if (IEEE80211_IS_CHAN_HT40(chan)) {
677 spur_subchannel_sd = 1;
678 bb_spur_off = bb_spur + 10;
680 spur_subchannel_sd = 0;
681 bb_spur_off = bb_spur - 10;
684 spur_subchannel_sd = 0;
685 bb_spur_off = bb_spur;
692 if (IEEE80211_IS_CHAN_HT40(chan))
701 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40;
702 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
727 for (i = 0; i < 4; i++) {
731 for (bp = 0; bp < 30; bp++) {
732 if ((cur_bin > lower) && (cur_bin < upper)) {
733 pilot_mask = pilot_mask | 0x1 << bp;
734 chan_mask = chan_mask | 0x1 << bp;
766 for (i = 0; i < 123; i++) {
767 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
768 if ((
abs(cur_vit_mask - bin)) < 75) {
773 if (cur_vit_mask < 0) {
774 mask_m[
abs(cur_vit_mask / 100)] = mask_amt;
776 mask_p[cur_vit_mask / 100] = mask_amt;
782 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
783 | (mask_m[48] << 26) | (mask_m[49] << 24)
784 | (mask_m[50] << 22) | (mask_m[51] << 20)
785 | (mask_m[52] << 18) | (mask_m[53] << 16)
786 | (mask_m[54] << 14) | (mask_m[55] << 12)
787 | (mask_m[56] << 10) | (mask_m[57] << 8)
788 | (mask_m[58] << 6) | (mask_m[59] << 4)
789 | (mask_m[60] << 2) | (mask_m[61] << 0);
793 tmp_mask = (mask_m[31] << 28)
794 | (mask_m[32] << 26) | (mask_m[33] << 24)
795 | (mask_m[34] << 22) | (mask_m[35] << 20)
796 | (mask_m[36] << 18) | (mask_m[37] << 16)
797 | (mask_m[48] << 14) | (mask_m[39] << 12)
798 | (mask_m[40] << 10) | (mask_m[41] << 8)
799 | (mask_m[42] << 6) | (mask_m[43] << 4)
800 | (mask_m[44] << 2) | (mask_m[45] << 0);
804 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
805 | (mask_m[18] << 26) | (mask_m[18] << 24)
806 | (mask_m[20] << 22) | (mask_m[20] << 20)
807 | (mask_m[22] << 18) | (mask_m[22] << 16)
808 | (mask_m[24] << 14) | (mask_m[24] << 12)
809 | (mask_m[25] << 10) | (mask_m[26] << 8)
810 | (mask_m[27] << 6) | (mask_m[28] << 4)
811 | (mask_m[29] << 2) | (mask_m[30] << 0);
815 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
816 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
817 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
818 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
819 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
820 | (mask_m[10] << 10) | (mask_m[11] << 8)
821 | (mask_m[12] << 6) | (mask_m[13] << 4)
822 | (mask_m[14] << 2) | (mask_m[15] << 0);
826 tmp_mask = (mask_p[15] << 28)
827 | (mask_p[14] << 26) | (mask_p[13] << 24)
828 | (mask_p[12] << 22) | (mask_p[11] << 20)
829 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
830 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
831 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
832 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
833 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
837 tmp_mask = (mask_p[30] << 28)
838 | (mask_p[29] << 26) | (mask_p[28] << 24)
839 | (mask_p[27] << 22) | (mask_p[26] << 20)
840 | (mask_p[25] << 18) | (mask_p[24] << 16)
841 | (mask_p[23] << 14) | (mask_p[22] << 12)
842 | (mask_p[21] << 10) | (mask_p[20] << 8)
843 | (mask_p[19] << 6) | (mask_p[18] << 4)
844 | (mask_p[17] << 2) | (mask_p[16] << 0);
848 tmp_mask = (mask_p[45] << 28)
849 | (mask_p[44] << 26) | (mask_p[43] << 24)
850 | (mask_p[42] << 22) | (mask_p[41] << 20)
851 | (mask_p[40] << 18) | (mask_p[39] << 16)
852 | (mask_p[38] << 14) | (mask_p[37] << 12)
853 | (mask_p[36] << 10) | (mask_p[35] << 8)
854 | (mask_p[34] << 6) | (mask_p[33] << 4)
855 | (mask_p[32] << 2) | (mask_p[31] << 0);
859 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
860 | (mask_p[59] << 26) | (mask_p[58] << 24)
861 | (mask_p[57] << 22) | (mask_p[56] << 20)
862 | (mask_p[55] << 18) | (mask_p[54] << 16)
863 | (mask_p[53] << 14) | (mask_p[52] << 12)
864 | (mask_p[51] << 10) | (mask_p[50] << 8)
865 | (mask_p[49] << 6) | (mask_p[48] << 4)
866 | (mask_p[47] << 2) | (mask_p[46] << 0);
887 pCap->halWowMatchPatternDword =
AH_TRUE;
931#define ANTENNA0_CHAINMASK 0x1
932#define ANTENNA1_CHAINMASK 0x2
962#undef ANTENNA0_CHAINMASK
963#undef ANTENNA1_CHAINMASK
971 return "Atheros 9220";
973 return "Atheros 9280";
HAL_BOOL ath_hal_EepromDataRead(struct ath_hal *ah, u_int off, uint16_t *data)
int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, int col, int regWr)
@ HAL_ANI_NOISE_IMMUNITY_LEVEL
#define AR9280_DEVID_PCIE
#define ATHEROS_VENDOR_ID
@ AR_EEP_PWR_TABLE_OFFSET
HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah)
#define AR5416_EEP_TXGAIN_ORIG
#define AR5416_EEP_RXGAIN_23dB_BACKOFF
#define AR5416_EEP_RXGAIN_ORIG
#define AR5416_EEP_RXGAIN_13dB_BACKOFF
#define AR5416_EEPROM_MODAL_SPURS
#define AR5416_PWR_TABLE_OFFSET_DB
#define AR5416_EEP_TXGAIN_HIGH_POWER
#define OS_REG_SET_BIT(_a, _r, _f)
#define HAL_INI_INIT(_ia, _data, _cols)
#define ath_hal_eepromGet(_ah, _param, _val)
#define OS_REG_CLR_BIT(_a, _r, _f)
#define ath_hal_getSpurChan(_ah, _ix, _is2G)
void * ath_hal_malloc(size_t)
#define HAL_INI_VAL(_ia, _r, _c)
#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c)
#define HALDEBUG(_ah, __m,...)
void ath_hal_printf(struct ath_hal *, const char *,...)
bus_space_tag_t HAL_BUS_TAG
#define OS_MEMZERO(_a, _n)
#define OS_REG_WRITE(_ah, _reg, _val)
bus_space_handle_t HAL_BUS_HANDLE
#define OS_REG_READ(_ah, _reg)
HAL_BOOL ar5212ChipTest(struct ath_hal *ah)
#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
#define AR_PHY_BIN_MASK2_2
#define AR_PHY_TIMING11_SPUR_FREQ_SD
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
#define AR_PHY_BIN_MASK2_3
#define AR_PHY_BIN_MASK_1
#define AR_PHY_BIN_MASK2_4
#define AR_PHY_TIMING11_USE_SPUR_IN_AGC
#define AR_PHY_BIN_MASK2_1
#define AR_PHY_BIN_MASK_3
#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
#define AR_PHY_BIN_MASK_2
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE
#define AR_RADIO_SREV_MAJOR
void ar5416GetChannelCenters(struct ath_hal *, const struct ieee80211_channel *chan, CHAN_CENTERS *centers)
#define AR5416_SPUR_RSSI_THRESH
void ar5416InitState(struct ath_hal_5416 *, uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
HAL_BOOL ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *, HAL_RESET_TYPE)
HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
void ar5416AttachPCIE(struct ath_hal *ah)
HAL_BOOL ar5416FillCapabilityInfo(struct ath_hal *ah)
void ar5416AniAttach(struct ath_hal *, const struct ar5212AniParams *, const struct ar5212AniParams *, HAL_BOOL ena)
HAL_BOOL ar5416SetResetReg(struct ath_hal *, uint32_t type)
uint32_t ar5416GetRadioRev(struct ath_hal *ah)
void ar5416InitNfHistBuff(struct ar5212NfCalHist *h)
#define PER_MAX_LOG_COUNT
void ar5416AdcDcCalCollect(struct ath_hal *ah)
void ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)
void ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains)
void ar5416AdcGainCalCollect(struct ath_hal *ah)
void ar5416IQCalCollect(struct ath_hal *ah)
void ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains)
#define RTC_PLL_SETTLE_DELAY
#define AR_PHY_MASK2_M_16_30
#define AR_PHY_SEL_INTERNAL_ADDAC
#define AR_PHY_MASK2_P_30_16
#define AR_PHY_SFCORR_EXT
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL
#define AR_PHY_MASK2_M_00_15
#define AR_PHY_MASK2_M_31_45
#define AR_PHY_ADC_SERIAL_CTL
#define AR_PHY_PILOT_MASK_31_60
#define AR_PHY_SPUR_REG_MASK_RATE_SELECT
#define AR_PHY_MASK2_P_15_01
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
#define AR_PHY_CHANNEL_MASK_31_60
#define AR_PHY_FORCE_CLKEN_CCK
#define AR_PHY_PILOT_MASK_01_30
#define AR_PHY_MASK2_P_45_31
#define AR_PHY_CHANNEL_MASK_01_30
#define AR_PHY_VIT_MASK2_M_46_61
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM
#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
#define AR_PHY_TIMING_CTRL4_CHAIN(_i)
#define AR_PHY_MASK2_P_61_45
#define AR_RTC_SOWL_PLL_CLKSEL
#define AR9280_WA_DEFAULT
#define AR_RAD5133_SREV_MAJOR
#define AR_RTC_SOWL_PLL_DIV
#define AR_SREV_MERLIN_20_OR_LATER(_ah)
#define AR_PCIE_PM_CTRL_ENA
#define AR_SREV_MERLIN_10_OR_LATER(_ah)
#define AR_RAD2133_SREV_MAJOR
#define AR_XSREV_TYPE_HOST_MODE
#define AR_RTC_SOWL_PLL_REFDIV
#define AR_RTC_SLEEP_DERIVED_CLK
#define AR_RTC_PLL_CONTROL
#define AR_XSREV_REVISION
#define AR_SREV_MERLIN_20(_ah)
#define AR_WA_D3_L1_DISABLE
HAL_BOOL ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)
#define AR9280_DEFAULT_TXCHAINMASK
#define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ
#define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ
#define AR_PHY_CCA_NOM_VAL_9280_5GHZ
#define AR9280_DEFAULT_RXCHAINMASK
#define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ
#define AR_PHY_CCA_NOM_VAL_9280_2GHZ
#define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ
#define ANTENNA0_CHAINMASK
#define AR_SPUR_FEEQ_BOUND_HT40
static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah)
static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
#define AR_SPUR_FEEQ_BOUND_HT20
static struct ath_hal * ar9280Attach(uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
static const HAL_PERCAL_DATA ar9280_iq_cal
static void ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
static const HAL_PERCAL_DATA ar9280_adc_gain_cal
void ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
HAL_BOOL ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
static void ar9280AniSetup(struct ath_hal *ah)
static const HAL_PERCAL_DATA ar9280_adc_dc_cal
static const char * ar9280Probe(uint16_t vendorid, uint16_t devid)
static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal
#define ANTENNA1_CHAINMASK
void ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
#define AR_BASE_FREQ_2GHZ
#define AR_BASE_FREQ_5GHZ
AH_CHIP(AR9280, ar9280Probe, ar9280Attach)
static void ar9280DisablePCIE(struct ath_hal *ah)
HAL_BOOL ar9280SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
void ar9280olcTemperatureCompensation(struct ath_hal *ah)
void ar9280olcInit(struct ath_hal *ah)
uint32_t halMbssidAggrSupport
uint32_t halWowMatchPatternExact
uint32_t hal4AddrAggrSupport
uint32_t halAutoSleepSupport
uint32_t halTxStbcSupport
uint32_t halRifsTxSupport
uint32_t halUseCombinedRadarRssi
uint32_t halSupportsFastClock5GHz
uint32_t halRxStbcSupport
uint32_t halBtCoexSupport
uint32_t halExtChanDfsSupport
uint32_t halSpectralScanSupport
uint32_t halHasRxSelfLinkedTail
uint32_t halRifsRxSupport
uint32_t hal4kbSplitTransSupport
uint32_t halEnhancedDfsSupport
int maxNoiseImmunityLevel
HAL_INI_ARRAY ah_ini_common
uint8_t ah_macaddr[IEEE80211_ADDR_LEN]
struct ath_hal_private ah_priv
HAL_INI_ARRAY ah_ini_modes
HAL_INI_ARRAY ah_ini_xmodes
HAL_INI_ARRAY ah_ini_txgain
HAL_INI_ARRAY ah_ini_rxgain
HAL_BOOL __ahdecl(* ah_setAntennaSwitch)(struct ath_hal *, HAL_ANT_SETTING)
uint16_t ah_analog5GhzRev
void __ahdecl(* ah_detach)(struct ath_hal *)
void __ahdecl(* ah_disablePCIE)(struct ath_hal *)
void __ahdecl(* ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, HAL_BOOL power_off)