39 TAILQ_INSERT_TAIL(&ah_chip_list, ahc, node);
47 TAILQ_REMOVE(&ah_chip_list, ahc, node);
63 const char *
name = (*pchip)->probe(vendorid, devid);
69 TAILQ_FOREACH(pc, &ah_chip_list, node) {
70 const char *
name = pc->
probe(vendorid, devid);
117 TAILQ_FOREACH(pc, &ah_chip_list, node) {
223 TAILQ_INSERT_TAIL(&ah_rf_list, arf, node);
231 TAILQ_REMOVE(&ah_rf_list, arf, node);
251 TAILQ_FOREACH(rf, &ah_rf_list, node) {
307#define AH_TIMEOUT 5000
317 for (i = 0; i < timeout; i++) {
323 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
338 for (i = 0, retval = 0; i < n; i++) {
339 retval = (retval << 1) | (val & 1);
347#define OFDM_PLCP_BITS 22
353#define HT_LTF(n) ((n) * 4)
355#define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
356#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
357#define IS_HT_RATE(_rc) ( (_rc) & IEEE80211_RATE_MCS)
375 shortPreamble, includeSifs);
379 KASSERT(numStreams > 0 && numStreams <= 4,
380 (
"number of spatial streams needs to be 1..3: MCS rate 0x%x!",
389 26, 52, 78, 104, 156, 208, 234, 260,
390 52, 104, 156, 208, 312, 416, 468, 520,
391 78, 156, 234, 312, 468, 624, 702, 780,
392 104, 208, 312, 416, 624, 832, 936, 1040
395 54, 108, 162, 216, 324, 432, 486, 540,
396 108, 216, 324, 432, 648, 864, 972, 1080,
397 162, 324, 486, 648, 972, 1296, 1458, 1620,
398 216, 432, 648, 864, 1296, 1728, 1944, 2160
408 uint32_t bitsPerSymbol, numBits, numSymbols, txTime;
410 KASSERT(rate & IEEE80211_RATE_MCS, (
"not mcs %d", rate));
411 KASSERT((rate &~ IEEE80211_RATE_MCS) < 31, (
"bad mcs 0x%x", rate));
418 numSymbols =
howmany(numBits, bitsPerSymbol);
420 txTime = ((numSymbols * 18) + 4) / 5;
422 txTime = numSymbols * 4;
436 uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
451 switch (rates->
info[rateix].
phy) {
452 case IEEE80211_T_CCK:
456 numBits = frameLen << 3;
458 + ((numBits * 1000)/kbps);
462 case IEEE80211_T_OFDM:
467 numSymbols =
howmany(numBits, bitsPerSymbol);
473 case IEEE80211_T_OFDM_HALF:
478 numSymbols =
howmany(numBits, bitsPerSymbol);
484 case IEEE80211_T_OFDM_QUARTER:
489 numSymbols =
howmany(numBits, bitsPerSymbol);
495 case IEEE80211_T_TURBO:
500 numSymbols =
howmany(numBits, bitsPerSymbol);
508 "%s: unknown phy %u (rate ix %u)\n",
509 __func__, rates->
info[rateix].
phy, rateix);
525 if (IEEE80211_IS_CHAN_TURBO(chan))
529 if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan))
531 if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT40U(chan))
533 if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT40D(chan))
535 if (IEEE80211_IS_CHAN_A(chan))
539 if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan))
541 if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT40U(chan))
543 if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT40D(chan))
550 if (IEEE80211_IS_CHAN_G(chan))
552 if (IEEE80211_IS_CHAN_B(chan))
577 if (IEEE80211_IS_CHAN_B(chan))
579 if (IEEE80211_IS_CHAN_G(chan))
581 if (IEEE80211_IS_CHAN_108G(chan))
583 if (IEEE80211_IS_CHAN_TURBO(chan))
594#define CLOCK_FAST_RATE_5GHZ_OFDM 44
599 const struct ieee80211_channel *c =
AH_PRIVATE(ah)->ah_curchan;
606 if (IEEE80211_IS_CHAN_HT40(c))
610 if (IEEE80211_IS_CHAN_HT40(c))
616 if (c !=
AH_NULL && IEEE80211_IS_CHAN_HALF(c))
618 else if (c !=
AH_NULL && IEEE80211_IS_CHAN_QUARTER(c))
630 return (psec / 1000000);
639 const struct ieee80211_channel *c =
AH_PRIVATE(ah)->ah_curchan;
646 if (IEEE80211_IS_CHAN_HT40(c))
650 if (IEEE80211_IS_CHAN_HT40(c))
671#define N(a) (sizeof(a)/sizeof(a[0]))
703 uint32_t capability, uint32_t *result)
745 switch (capability) {
766 switch (capability) {
834 switch (capability) {
872 switch (capability) {
905 uint32_t capability, uint32_t setting,
HAL_STATUS *status)
910 switch (capability) {
924 switch (capability) {
926 AH_PRIVATE(ah)->ah_rfkillEnabled = (setting != 0);
954 void *dstbuf,
int space)
956 uint32_t *dp = dstbuf;
959 for (i = 0; space >= 2*
sizeof(uint32_t); i++) {
960 uint32_t r = regs[i].
start;
961 uint32_t e = regs[i].
end;
964 space -= 2*
sizeof(uint32_t);
967 r +=
sizeof(uint32_t);
968 space -=
sizeof(uint32_t);
969 }
while (r <= e && space >=
sizeof(uint32_t));
971 return (
char *) dp - (
char *) dstbuf;
985 const void *args, uint32_t argsize,
986 void **result, uint32_t *resultsize)
1003 *resultsize =
sizeof(
AH_PRIVATE(ah)->ah_fatalState);
1006 if (argsize !=
sizeof(uint16_t))
1010 *resultsize =
sizeof(uint16_t);
1012#ifdef AH_PRIVATE_DIAG
1023 if (argsize !=
sizeof(uint16_t))
1026#ifdef AH_SUPPORT_WRITE_EEPROM
1038 *resultsize =
sizeof(uint32_t);
1039 *((uint32_t *)(*result)) =
1041 }
else if (argsize ==
sizeof(uint32_t)) {
1042 AH_PRIVATE(ah)->ah_11nCompat = *(
const uint32_t *)args;
1066 "%s: inactive queue\n", __func__);
1125 "%s: inactive queue\n", __func__);
1165 "%s: invalid channel %u/0x%x; no mapping\n",
1166 __func__, chan->ic_freq, chan->ic_flags);
1189 const struct ieee80211_channel *chan, int16_t *nf_ctl,
1198 "%s: invalid channel %u/0x%x; no mapping\n",
1199 __func__, chan->ic_freq, chan->ic_flags);
1201 nf_ctl[i] = nf_ext[i] = 0;
1209 nf_ctl[i] = nf_ext[i] = 0;
1258 int16_t correct2, correct5;
1259 int16_t lowest2, lowest5;
1266 correct2 = lowest2 = 0;
1267 correct5 = lowest5 = 0;
1268 for (i = 0; i <
AH_PRIVATE(ah)->ah_nchan; i++) {
1295 for (i = 0; i <
AH_PRIVATE(ah)->ah_nchan; i++) {
1318 for (r = 0; r < ia->
rows; r++) {
1337 for (r = 0; r < ia->
rows; r++)
1343 const uint32_t data[],
int regWr)
1347 for (r = 0; r < ia->
rows; r++) {
1370 uint16_t *indexL, uint16_t *indexR)
1377 if (target <= pList[0]) {
1378 *indexL = *indexR = 0;
1381 if (target >= pList[listSize-1]) {
1382 *indexL = *indexR = (uint16_t)(listSize - 1);
1387 for (i = 0; i < listSize - 1; i++) {
1392 if (pList[i] == target) {
1393 *indexL = *indexR = i;
1400 if (target < pList[i + 1]) {
1402 *indexR = (uint16_t)(i + 1);
1407 *indexL = *indexR = 0;
1419 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
1422 uint8_t currPwr = pwrMin;
1423 uint16_t idxL, idxR;
1426 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
1431 if (idxL == numIntercepts - 1)
1432 idxL = (uint16_t)(numIntercepts - 2);
1433 if (pPwrList[idxL] == pPwrList[idxR])
1436 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
1437 (pPwrList[idxR] - pPwrList[idxL]) );
1439 pRetVpdList[i] = (uint8_t)k;
1453 int16_t targetLeft, int16_t targetRight)
1457 if (srcRight == srcLeft) {
1460 rv = (int16_t)( ((target - srcLeft) * targetRight +
1461 (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
1500 return ((diag & 0x500000) == 0);
1524#define ATH_DATA_EEPROM_SIZE 2048
1555 return ((
int) freq - 2407) / 5;
1557 return 15 + ((freq - 2512) / 20);
HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n)
HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi)
static const uint16_t ht20_bps[32]
HAL_BOOL ath_hal_waitfor(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val, uint32_t timeout)
void ath_hal_set_dfs_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL ena)
void ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta)
void ath_hal_survey_add_sample(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
int ath_hal_get_curmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
uint64_t ath_hal_mac_psec(struct ath_hal *ah, u_int clks)
void ath_hal_process_noisefloor(struct ath_hal *ah)
const char * ath_hal_probe(uint16_t vendorid, uint16_t devid)
void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt)
#define CLOCK_FAST_RATE_5GHZ_OFDM
struct ath_hal_rf * ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)
static const uint16_t ht40_bps[32]
u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
uint16_t ath_hal_computetxtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix, HAL_BOOL shortPreamble, HAL_BOOL includeSifs)
HAL_BOOL ath_hal_EepromDataRead(struct ath_hal *ah, u_int off, uint16_t *data)
uint32_t ath_hal_pkt_txtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble, HAL_BOOL includeSifs)
int16_t ath_hal_getChanNoise(struct ath_hal *ah, const struct ieee80211_channel *chan)
int ath_hal_mhz2ieee_2ghz(struct ath_hal *ah, int freq)
#define ATH_DATA_EEPROM_SIZE
void ath_hal_setcca(struct ath_hal *ah, int ena)
OS_SET_DECLARE(ah_chips, struct ath_hal_chip)
static const int16_t NOISE_FLOOR[]
HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t setting, HAL_STATUS *status)
int ath_hal_remove_rf(struct ath_hal_rf *arf)
static const uint8_t CLOCK_RATE[]
int ath_hal_get_mimo_chan_noise(struct ath_hal *ah, const struct ieee80211_channel *chan, int16_t *nf_ctl, int16_t *nf_ext)
struct ath_hal * ath_hal_attach(uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *error)
HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t *result)
static u_int ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs, void *dstbuf, int space)
uint32_t ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams, HAL_BOOL isht40, HAL_BOOL isShortGI)
void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, int col)
HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, uint16_t *indexL, uint16_t *indexR)
HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo)
int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, int col, int regWr)
int ath_hal_remove_chip(struct ath_hal_chip *ahc)
int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, int16_t targetLeft, int16_t targetRight)
const char * ath_hal_mac_name(struct ath_hal *ah)
u_int ath_hal_getwirelessmodes(struct ath_hal *ah)
static void ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space)
u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
#define HT_RC_2_STREAMS(_rc)
int ath_hal_getcca(struct ath_hal *ah)
void ath_hal_survey_clear(struct ath_hal *ah)
HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, const void *args, uint32_t argsize, void **result, uint32_t *resultsize)
HAL_BOOL ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)
static WIRELESS_MODE ath_hal_chan2wmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
const char * ath_hal_rf_name(struct ath_hal *ah)
int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, const uint32_t data[], int regWr)
@ HAL_MODE_11NG_HT40MINUS
@ HAL_MODE_11NA_HT40MINUS
#define CHANNEL_SURVEY_SAMPLE_COUNT
@ HAL_CAP_ENHANCED_DFS_SUPPORT
@ HAL_CAP_SPLIT_4KB_TRANS
@ HAL_CAP_ENHANCED_DMA_SUPPORT
@ HAL_CAP_COMBINED_RADAR_RSSI
@ HAL_CAP_MBSSID_AGGR_SUPPORT
@ HAL_CAP_RXDESC_SELFLINK
#define HAL_TXQ_USEDEFAULT
#define ATHEROS_VENDOR_ID
int ath_hal_add_rf(struct ath_hal_rf *arf)
#define OFDM_HALF_PREAMBLE_TIME
#define ath_hal_getWirelessModes(_ah)
#define OFDM_HALF_SIFS_TIME
#define TURBO_PREAMBLE_TIME
#define CCK_PREAMBLE_BITS
static OS_INLINE HAL_CHANNEL_INTERNAL * ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
#define OFDM_QUARTER_PLCP_BITS
#define TURBO_SYMBOL_TIME
#define OFDM_QUARTER_PREAMBLE_TIME
#define OFDM_HALF_SYMBOL_TIME
#define ath_hal_eepromWrite(_ah, _off, _data)
#define CHANNEL_MIMO_NF_VALID
#define OFDM_QUARTER_SIFS_TIME
#define HAL_INI_VAL(_ia, _r, _c)
#define OFDM_HALF_PLCP_BITS
#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c)
#define OFDM_QUARTER_SYMBOL_TIME
#define HALDEBUG(_ah, __m,...)
#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS
#define ath_hal_eepromRead(_ah, _off, _data)
#define WLAN_CTRL_FRAME_SIZE
#define OFDM_PREAMBLE_TIME
int ath_hal_add_chip(struct ath_hal_chip *ahc)
#define ath_hal_getNfAdjust(_ah, _c)
void ath_hal_printf(struct ath_hal *, const char *,...)
bus_space_tag_t HAL_BUS_TAG
#define OS_MEMZERO(_a, _n)
#define OS_REG_WRITE(_ah, _reg, _val)
#define OS_SET_FOREACH(pvar, set)
bus_space_handle_t HAL_BUS_HANDLE
#define OS_MEMCPY(_d, _s, _n)
#define OS_REG_READ(_ah, _reg)
#define AR_SREV_VERSION_MAUI_1
#define AR_SREV_VERSION_OAHU
#define AR_SREV_VERSION_CRETE
#define AR_SREV_VERSION_MAUI_2
#define AR_RAD5111_SREV_MAJOR
#define AR_RAD5112_SREV_2_0
#define AR_RAD2317_SREV_MAJOR
#define AR_SREV_VERSION_EAGLE
#define AR_RAD5111_SREV_PROD
#define AR_RAD2112_SREV_MAJOR
#define AR_SREV_VERSION_GRIFFIN
#define AR_RAD5112_SREV_MAJOR
#define AR_RAD5424_SREV_MAJOR
#define AR_SREV_VERSION_CONDOR
#define AR_RAD2111_SREV_MAJOR
#define AR_SREV_VERSION_VENICE
#define AR_RAD5413_SREV_MAJOR
#define AR_SREV_VERSION_COBRA
#define AR_RAD2112_SREV_2_0
#define AR_RADIO_SREV_MAJOR
#define AR_RAD2413_SREV_MAJOR
#define AR_RAD2112_SREV_2_1
#define AR_RAD2316_SREV_MAJOR
#define AR_RAD5112_SREV_2_1
#define AR_RAD5122_SREV_MAJOR
#define AR_RAD5133_SREV_MAJOR
#define AR_XSREV_VERSION_KITE
#define AR_XSREV_VERSION_MERLIN
#define AR_RAD2122_SREV_MAJOR
#define AR_XSREV_VERSION_KIWI
#define AR_XSREV_VERSION_HOWL
#define AR_RAD2133_SREV_MAJOR
#define AR_XSREV_VERSION_OWL_PCIE
#define AR_XSREV_VERSION_SOWL
#define AR_XSREV_VERSION_OWL_PCI
#define AR_SREV_VERSION_AR9340
#define AR_SREV_REVISION_AR9580_10
#define AR_SREV_VERSION_AR9380
#define AR_SREV_VERSION_QCA9530
#define AR_SREV_VERSION_AR9485
#define AR_SREV_VERSION_AR9330
#define AR_SREV_VERSION_QCA9565
#define AR_SREV_VERSION_AR9460
#define AR_SREV_VERSION_QCA9550
uint32_t halRfSilentSupport
uint32_t halMbssidAggrSupport
uint32_t halEnhancedDmaSupport
uint32_t hal4AddrAggrSupport
uint32_t halBssidMatchSupport
uint32_t halAutoSleepSupport
uint32_t halHwPhyCounterSupport
uint32_t halRxUsingLnaMixing
uint32_t halTxStbcSupport
HAL_MFP_OPT_T halMfpSupport
uint32_t halFastFramesSupport
uint32_t halUseCombinedRadarRssi
uint32_t halRxStbcSupport
uint32_t halBssIdMaskSupport
uint32_t halBtCoexSupport
uint32_t halAntDivCombSupport
uint32_t halSerialiseRegWar
uint32_t halCompressSupport
uint32_t halExtChanDfsSupport
uint32_t halFastCCSupport
uint32_t halMcastKeySrchSupport
uint32_t halSpectralScanSupport
uint32_t halHasRxSelfLinkedTail
uint32_t halHTSGI20Support
uint32_t hal4kbSplitTransSupport
uint32_t halEnhancedDfsSupport
int16_t noiseFloorExt[AH_MAX_CHAINS]
int16_t noiseFloorCtl[AH_MAX_CHAINS]
HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]
uint8_t dk_mac[IEEE80211_ADDR_LEN]
uint8_t rateCodeToIndex[256]
struct HAL_RATE_TABLE::@3 info[64]
HAL_TX_QUEUE_SUBTYPE tqi_subtype
HAL_TX_QUEUE_FLAGS tqi_qflags
uint32_t tqi_cbrOverflowLimit
HAL_TX_QUEUE_SUBTYPE tqi_subtype
HAL_TX_QUEUE_FLAGS tqi_qflags
uint32_t tqi_cbrOverflowLimit
struct ath_hal *(* attach)(uint16_t devid, HAL_SOFTC, HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_OPS_CONFIG *ah, HAL_STATUS *error)
const char *(* probe)(uint16_t vendorid, uint16_t devid)
HAL_BOOL(* probe)(struct ath_hal *ah)
HAL_BOOL __ahdecl(* ah_setKeyCacheEntry)(struct ath_hal *, uint16_t, const HAL_KEYVAL *, const uint8_t *, int)
HAL_BOOL __ahdecl(* ah_resetKeyCacheEntry)(struct ath_hal *, uint16_t)
uint16_t ah_analog2GhzRev
void __ahdecl(* ah_setDfsCacTxQuiet)(struct ath_hal *, HAL_BOOL)
uint16_t ah_analog5GhzRev