FreeBSD kernel ATH device code
ar5211reg.h
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1/*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $FreeBSD$
20 */
21#ifndef _DEV_ATH_AR5211REG_H
22#define _DEV_ATH_AR5211REG_H
23
24/*
25 * Definitions for the Atheros AR5211/5311 chipset.
26 */
27
28/*
29 * Maui2/Spirit specific registers/fields are indicated by AR5311.
30 * Oahu specific registers/fields are indicated by AR5211.
31 */
32
33/* DMA Control and Interrupt Registers */
34#define AR_CR 0x0008 /* control register */
35#define AR_RXDP 0x000C /* receive queue descriptor pointer */
36#define AR_CFG 0x0014 /* configuration and status register */
37#define AR_IER 0x0024 /* Interrupt enable register */
38#define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
39#define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
40#define AR_TXCFG 0x0030 /* tx DMA size config register */
41#define AR_RXCFG 0x0034 /* rx DMA size config register */
42#define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
43#define AR_MIBC 0x0040 /* MIB control register */
44#define AR_TOPS 0x0044 /* timeout prescale count */
45#define AR_RXNPTO 0x0048 /* no frame received timeout */
46#define AR_TXNPTO 0x004C /* no frame trasmitted timeout */
47#define AR_RFGTO 0x0050 /* receive frame gap timeout */
48#define AR_RFCNT 0x0054 /* receive frame count limit */
49#define AR_MACMISC 0x0058 /* miscellaneous control/status */
50#define AR5311_QDCLKGATE 0x005c /* QCU/DCU clock gating control */
51#define AR_ISR 0x0080 /* Primary interrupt status register */
52#define AR_ISR_S0 0x0084 /* Secondary interrupt status reg 0 */
53#define AR_ISR_S1 0x0088 /* Secondary interrupt status reg 1 */
54#define AR_ISR_S2 0x008c /* Secondary interrupt status reg 2 */
55#define AR_ISR_S3 0x0090 /* Secondary interrupt status reg 3 */
56#define AR_ISR_S4 0x0094 /* Secondary interrupt status reg 4 */
57#define AR_IMR 0x00a0 /* Primary interrupt mask register */
58#define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */
59#define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */
60#define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */
61#define AR_IMR_S3 0x00b0 /* Secondary interrupt mask reg 3 */
62#define AR_IMR_S4 0x00b4 /* Secondary interrupt mask reg 4 */
63#define AR_ISR_RAC 0x00c0 /* Primary interrupt status reg, */
64/* Shadow copies with read-and-clear access */
65#define AR_ISR_S0_S 0x00c4 /* Secondary interrupt status reg 0 */
66#define AR_ISR_S1_S 0x00c8 /* Secondary interrupt status reg 1 */
67#define AR_ISR_S2_S 0x00cc /* Secondary interrupt status reg 2 */
68#define AR_ISR_S3_S 0x00d0 /* Secondary interrupt status reg 3 */
69#define AR_ISR_S4_S 0x00d4 /* Secondary interrupt status reg 4 */
70
71#define AR_Q0_TXDP 0x0800 /* Transmit Queue descriptor pointer */
72#define AR_Q1_TXDP 0x0804 /* Transmit Queue descriptor pointer */
73#define AR_Q2_TXDP 0x0808 /* Transmit Queue descriptor pointer */
74#define AR_Q3_TXDP 0x080c /* Transmit Queue descriptor pointer */
75#define AR_Q4_TXDP 0x0810 /* Transmit Queue descriptor pointer */
76#define AR_Q5_TXDP 0x0814 /* Transmit Queue descriptor pointer */
77#define AR_Q6_TXDP 0x0818 /* Transmit Queue descriptor pointer */
78#define AR_Q7_TXDP 0x081c /* Transmit Queue descriptor pointer */
79#define AR_Q8_TXDP 0x0820 /* Transmit Queue descriptor pointer */
80#define AR_Q9_TXDP 0x0824 /* Transmit Queue descriptor pointer */
81#define AR_QTXDP(i) (AR_Q0_TXDP + ((i)<<2))
82
83#define AR_Q_TXE 0x0840 /* Transmit Queue enable */
84#define AR_Q_TXD 0x0880 /* Transmit Queue disable */
85
86#define AR_Q0_CBRCFG 0x08c0 /* CBR configuration */
87#define AR_Q1_CBRCFG 0x08c4 /* CBR configuration */
88#define AR_Q2_CBRCFG 0x08c8 /* CBR configuration */
89#define AR_Q3_CBRCFG 0x08cc /* CBR configuration */
90#define AR_Q4_CBRCFG 0x08d0 /* CBR configuration */
91#define AR_Q5_CBRCFG 0x08d4 /* CBR configuration */
92#define AR_Q6_CBRCFG 0x08d8 /* CBR configuration */
93#define AR_Q7_CBRCFG 0x08dc /* CBR configuration */
94#define AR_Q8_CBRCFG 0x08e0 /* CBR configuration */
95#define AR_Q9_CBRCFG 0x08e4 /* CBR configuration */
96#define AR_QCBRCFG(i) (AR_Q0_CBRCFG + ((i)<<2))
97
98#define AR_Q0_RDYTIMECFG 0x0900 /* ReadyTime configuration */
99#define AR_Q1_RDYTIMECFG 0x0904 /* ReadyTime configuration */
100#define AR_Q2_RDYTIMECFG 0x0908 /* ReadyTime configuration */
101#define AR_Q3_RDYTIMECFG 0x090c /* ReadyTime configuration */
102#define AR_Q4_RDYTIMECFG 0x0910 /* ReadyTime configuration */
103#define AR_Q5_RDYTIMECFG 0x0914 /* ReadyTime configuration */
104#define AR_Q6_RDYTIMECFG 0x0918 /* ReadyTime configuration */
105#define AR_Q7_RDYTIMECFG 0x091c /* ReadyTime configuration */
106#define AR_Q8_RDYTIMECFG 0x0920 /* ReadyTime configuration */
107#define AR_Q9_RDYTIMECFG 0x0924 /* ReadyTime configuration */
108#define AR_QRDYTIMECFG(i) (AR_Q0_RDYTIMECFG + ((i)<<2))
109
110#define AR_Q_ONESHOTARM_SC 0x0940 /* OneShotArm set control */
111#define AR_Q_ONESHOTARM_CC 0x0980 /* OneShotArm clear control */
112
113#define AR_Q0_MISC 0x09c0 /* Miscellaneous QCU settings */
114#define AR_Q1_MISC 0x09c4 /* Miscellaneous QCU settings */
115#define AR_Q2_MISC 0x09c8 /* Miscellaneous QCU settings */
116#define AR_Q3_MISC 0x09cc /* Miscellaneous QCU settings */
117#define AR_Q4_MISC 0x09d0 /* Miscellaneous QCU settings */
118#define AR_Q5_MISC 0x09d4 /* Miscellaneous QCU settings */
119#define AR_Q6_MISC 0x09d8 /* Miscellaneous QCU settings */
120#define AR_Q7_MISC 0x09dc /* Miscellaneous QCU settings */
121#define AR_Q8_MISC 0x09e0 /* Miscellaneous QCU settings */
122#define AR_Q9_MISC 0x09e4 /* Miscellaneous QCU settings */
123#define AR_QMISC(i) (AR_Q0_MISC + ((i)<<2))
124
125#define AR_Q0_STS 0x0a00 /* Miscellaneous QCU status */
126#define AR_Q1_STS 0x0a04 /* Miscellaneous QCU status */
127#define AR_Q2_STS 0x0a08 /* Miscellaneous QCU status */
128#define AR_Q3_STS 0x0a0c /* Miscellaneous QCU status */
129#define AR_Q4_STS 0x0a10 /* Miscellaneous QCU status */
130#define AR_Q5_STS 0x0a14 /* Miscellaneous QCU status */
131#define AR_Q6_STS 0x0a18 /* Miscellaneous QCU status */
132#define AR_Q7_STS 0x0a1c /* Miscellaneous QCU status */
133#define AR_Q8_STS 0x0a20 /* Miscellaneous QCU status */
134#define AR_Q9_STS 0x0a24 /* Miscellaneous QCU status */
135#define AR_QSTS(i) (AR_Q0_STS + ((i)<<2))
136
137#define AR_Q_RDYTIMESHDN 0x0a40 /* ReadyTimeShutdown status */
138#define AR_D0_QCUMASK 0x1000 /* QCU Mask */
139#define AR_D1_QCUMASK 0x1004 /* QCU Mask */
140#define AR_D2_QCUMASK 0x1008 /* QCU Mask */
141#define AR_D3_QCUMASK 0x100c /* QCU Mask */
142#define AR_D4_QCUMASK 0x1010 /* QCU Mask */
143#define AR_D5_QCUMASK 0x1014 /* QCU Mask */
144#define AR_D6_QCUMASK 0x1018 /* QCU Mask */
145#define AR_D7_QCUMASK 0x101c /* QCU Mask */
146#define AR_D8_QCUMASK 0x1020 /* QCU Mask */
147#define AR_D9_QCUMASK 0x1024 /* QCU Mask */
148#define AR_DQCUMASK(i) (AR_D0_QCUMASK + ((i)<<2))
149
150#define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */
151#define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */
152#define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */
153#define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */
154#define AR_D4_LCL_IFS 0x1050 /* DCU-specific IFS settings */
155#define AR_D5_LCL_IFS 0x1054 /* DCU-specific IFS settings */
156#define AR_D6_LCL_IFS 0x1058 /* DCU-specific IFS settings */
157#define AR_D7_LCL_IFS 0x105c /* DCU-specific IFS settings */
158#define AR_D8_LCL_IFS 0x1060 /* DCU-specific IFS settings */
159#define AR_D9_LCL_IFS 0x1064 /* DCU-specific IFS settings */
160#define AR_DLCL_IFS(i) (AR_D0_LCL_IFS + ((i)<<2))
161
162#define AR_D0_RETRY_LIMIT 0x1080 /* Retry limits */
163#define AR_D1_RETRY_LIMIT 0x1084 /* Retry limits */
164#define AR_D2_RETRY_LIMIT 0x1088 /* Retry limits */
165#define AR_D3_RETRY_LIMIT 0x108c /* Retry limits */
166#define AR_D4_RETRY_LIMIT 0x1090 /* Retry limits */
167#define AR_D5_RETRY_LIMIT 0x1094 /* Retry limits */
168#define AR_D6_RETRY_LIMIT 0x1098 /* Retry limits */
169#define AR_D7_RETRY_LIMIT 0x109c /* Retry limits */
170#define AR_D8_RETRY_LIMIT 0x10a0 /* Retry limits */
171#define AR_D9_RETRY_LIMIT 0x10a4 /* Retry limits */
172#define AR_DRETRY_LIMIT(i) (AR_D0_RETRY_LIMIT + ((i)<<2))
173
174#define AR_D0_CHNTIME 0x10c0 /* ChannelTime settings */
175#define AR_D1_CHNTIME 0x10c4 /* ChannelTime settings */
176#define AR_D2_CHNTIME 0x10c8 /* ChannelTime settings */
177#define AR_D3_CHNTIME 0x10cc /* ChannelTime settings */
178#define AR_D4_CHNTIME 0x10d0 /* ChannelTime settings */
179#define AR_D5_CHNTIME 0x10d4 /* ChannelTime settings */
180#define AR_D6_CHNTIME 0x10d8 /* ChannelTime settings */
181#define AR_D7_CHNTIME 0x10dc /* ChannelTime settings */
182#define AR_D8_CHNTIME 0x10e0 /* ChannelTime settings */
183#define AR_D9_CHNTIME 0x10e4 /* ChannelTime settings */
184#define AR_DCHNTIME(i) (AR_D0_CHNTIME + ((i)<<2))
185
186#define AR_D0_MISC 0x1100 /* Misc DCU-specific settings */
187#define AR_D1_MISC 0x1104 /* Misc DCU-specific settings */
188#define AR_D2_MISC 0x1108 /* Misc DCU-specific settings */
189#define AR_D3_MISC 0x110c /* Misc DCU-specific settings */
190#define AR_D4_MISC 0x1110 /* Misc DCU-specific settings */
191#define AR_D5_MISC 0x1114 /* Misc DCU-specific settings */
192#define AR_D6_MISC 0x1118 /* Misc DCU-specific settings */
193#define AR_D7_MISC 0x111c /* Misc DCU-specific settings */
194#define AR_D8_MISC 0x1120 /* Misc DCU-specific settings */
195#define AR_D9_MISC 0x1124 /* Misc DCU-specific settings */
196#define AR_DMISC(i) (AR_D0_MISC + ((i)<<2))
197
198#define AR_D0_SEQNUM 0x1140 /* Frame seqnum control/status */
199#define AR_D1_SEQNUM 0x1144 /* Frame seqnum control/status */
200#define AR_D2_SEQNUM 0x1148 /* Frame seqnum control/status */
201#define AR_D3_SEQNUM 0x114c /* Frame seqnum control/status */
202#define AR_D4_SEQNUM 0x1150 /* Frame seqnum control/status */
203#define AR_D5_SEQNUM 0x1154 /* Frame seqnum control/status */
204#define AR_D6_SEQNUM 0x1158 /* Frame seqnum control/status */
205#define AR_D7_SEQNUM 0x115c /* Frame seqnum control/status */
206#define AR_D8_SEQNUM 0x1160 /* Frame seqnum control/status */
207#define AR_D9_SEQNUM 0x1164 /* Frame seqnum control/status */
208#define AR_DSEQNUM(i) (AR_D0_SEQNUM + ((i<<2)))
209
210/* MAC DCU-global IFS settings */
211#define AR_D_GBL_IFS_SIFS 0x1030 /* DCU global SIFS settings */
212#define AR_D_GBL_IFS_SLOT 0x1070 /* DC global slot interval */
213#define AR_D_GBL_IFS_EIFS 0x10b0 /* DCU global EIFS setting */
214#define AR_D_GBL_IFS_MISC 0x10f0 /* DCU global misc. IFS settings */
215#define AR_D_FPCTL 0x1230 /* DCU frame prefetch settings */
216#define AR_D_TXPSE 0x1270 /* DCU transmit pause control/status */
217#define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */
218#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */
219#define AR_D_TXBLK_CLR 0x143c /* DCU clear tx filter (w/only) */
220#define AR_D_TXBLK_SET 0x147c /* DCU set tx filter (w/only) */
221
222#define AR_D_TXPSE 0x1270 /* DCU transmit pause control/status */
223
224#define AR_RC 0x4000 /* Warm reset control register */
225#define AR_SCR 0x4004 /* Sleep control register */
226#define AR_INTPEND 0x4008 /* Interrupt Pending register */
227#define AR_SFR 0x400C /* Sleep force register */
228#define AR_PCICFG 0x4010 /* PCI configuration register */
229#define AR_GPIOCR 0x4014 /* GPIO control register */
230#define AR_GPIODO 0x4018 /* GPIO data output access register */
231#define AR_GPIODI 0x401C /* GPIO data input access register */
232#define AR_SREV 0x4020 /* Silicon Revision register */
233
234#define AR_EEPROM_ADDR 0x6000 /* EEPROM address register (10 bit) */
235#define AR_EEPROM_DATA 0x6004 /* EEPROM data register (16 bit) */
236#define AR_EEPROM_CMD 0x6008 /* EEPROM command register */
237#define AR_EEPROM_STS 0x600c /* EEPROM status register */
238#define AR_EEPROM_CFG 0x6010 /* EEPROM configuration register */
239
240#define AR_STA_ID0 0x8000 /* station ID0 - low 32 bits */
241#define AR_STA_ID1 0x8004 /* station ID1 - upper 16 bits */
242#define AR_BSS_ID0 0x8008 /* BSSID low 32 bits */
243#define AR_BSS_ID1 0x800C /* BSSID upper 16 bits / AID */
244#define AR_SLOT_TIME 0x8010 /* Time-out after a collision */
245#define AR_TIME_OUT 0x8014 /* ACK & CTS time-out */
246#define AR_RSSI_THR 0x8018 /* RSSI warning & missed beacon threshold */
247#define AR_USEC 0x801c /* transmit latency register */
248#define AR_BEACON 0x8020 /* beacon control value/mode bits */
249#define AR_CFP_PERIOD 0x8024 /* CFP Interval (TU/msec) */
250#define AR_TIMER0 0x8028 /* Next beacon time (TU/msec) */
251#define AR_TIMER1 0x802c /* DMA beacon alert time (1/8 TU) */
252#define AR_TIMER2 0x8030 /* Software beacon alert (1/8 TU) */
253#define AR_TIMER3 0x8034 /* ATIM window time */
254#define AR_CFP_DUR 0x8038 /* maximum CFP duration in TU */
255#define AR_RX_FILTER 0x803C /* receive filter register */
256#define AR_MCAST_FIL0 0x8040 /* multicast filter lower 32 bits */
257#define AR_MCAST_FIL1 0x8044 /* multicast filter upper 32 bits */
258#define AR_DIAG_SW 0x8048 /* PCU control register */
259#define AR_TSF_L32 0x804c /* local clock lower 32 bits */
260#define AR_TSF_U32 0x8050 /* local clock upper 32 bits */
261#define AR_TST_ADDAC 0x8054 /* ADDAC test register */
262#define AR_DEF_ANTENNA 0x8058 /* default antenna register */
263
264#define AR_LAST_TSTP 0x8080 /* Time stamp of the last beacon rcvd */
265#define AR_NAV 0x8084 /* current NAV value */
266#define AR_RTS_OK 0x8088 /* RTS exchange success counter */
267#define AR_RTS_FAIL 0x808c /* RTS exchange failure counter */
268#define AR_ACK_FAIL 0x8090 /* ACK failure counter */
269#define AR_FCS_FAIL 0x8094 /* FCS check failure counter */
270#define AR_BEACON_CNT 0x8098 /* Valid beacon counter */
271
272#define AR_KEYTABLE_0 0x8800 /* Encryption key table */
273#define AR_KEYTABLE(n) (AR_KEYTABLE_0 + ((n)*32))
274
275#define AR_CR_RXE 0x00000004 /* Receive enable */
276#define AR_CR_RXD 0x00000020 /* Receive disable */
277#define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
278#define AR_CR_BITS "\20\3RXE\6RXD\7SWI"
279
280#define AR_CFG_SWTD 0x00000001 /* byteswap tx descriptor words */
281#define AR_CFG_SWTB 0x00000002 /* byteswap tx data buffer words */
282#define AR_CFG_SWRD 0x00000004 /* byteswap rx descriptor words */
283#define AR_CFG_SWRB 0x00000008 /* byteswap rx data buffer words */
284#define AR_CFG_SWRG 0x00000010 /* byteswap register access data words */
285#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
286#define AR_CFG_PHOK 0x00000100 /* PHY OK status */
287#define AR_CFG_EEBS 0x00000200 /* EEPROM busy */
288#define AR_CFG_CLK_GATE_DIS 0x00000400 /* Clock gating disable (Oahu only) */
289#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 /* Mask of PCI core master request queue full threshold */
290#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 /* Shift for PCI core master request queue full threshold */
291#define AR_CFG_BITS \
292 "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\10PHYOK11EEBS"
293
294#define AR_IER_ENABLE 0x00000001 /* Global interrupt enable */
295#define AR_IER_DISABLE 0x00000000 /* Global interrupt disable */
296#define AR_IER_BITS "\20\1ENABLE"
297
298#define AR_RTSD0_RTS_DURATION_6_M 0x000000FF
299#define AR_RTSD0_RTS_DURATION_6_S 0
300#define AR_RTSD0_RTS_DURATION_9_M 0x0000FF00
301#define AR_RTSD0_RTS_DURATION_9_S 8
302#define AR_RTSD0_RTS_DURATION_12_M 0x00FF0000
303#define AR_RTSD0_RTS_DURATION_12_S 16
304#define AR_RTSD0_RTS_DURATION_18_M 0xFF000000
305#define AR_RTSD0_RTS_DURATION_18_S 24
306
307#define AR_RTSD0_RTS_DURATION_24_M 0x000000FF
308#define AR_RTSD0_RTS_DURATION_24_S 0
309#define AR_RTSD0_RTS_DURATION_36_M 0x0000FF00
310#define AR_RTSD0_RTS_DURATION_36_S 8
311#define AR_RTSD0_RTS_DURATION_48_M 0x00FF0000
312#define AR_RTSD0_RTS_DURATION_48_S 16
313#define AR_RTSD0_RTS_DURATION_54_M 0xFF000000
314#define AR_RTSD0_RTS_DURATION_54_S 24
315
316#define AR_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
317#define AR_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
318#define AR_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
319#define AR_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
320#define AR_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
321#define AR_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
322#define AR_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
323#define AR_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
324
325#define AR_TXCFG_FTRIG_M 0x000003F0 /* Mask for Frame trigger level */
326#define AR_TXCFG_FTRIG_S 4 /* Shift for Frame trigger level */
327#define AR_TXCFG_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
328#define AR_TXCFG_FTRIG_64B 0x00000010 /* default */
329#define AR_TXCFG_FTRIG_128B 0x00000020
330#define AR_TXCFG_FTRIG_192B 0x00000030
331#define AR_TXCFG_FTRIG_256B 0x00000040 /* 5 bits total */
332#define AR_TXCFG_BITS "\20"
333
334#define AR5311_RXCFG_DEF_RX_ANTENNA 0x00000008 /* Default Receive Antenna */
335 /* Maui2/Spirit only - reserved on Oahu */
336#define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
337#define AR_RXCFG_EN_JUM 0x00000020 /* Enable jumbo rx descriptors */
338#define AR_RXCFG_WR_JUM 0x00000040 /* Wrap jumbo rx descriptors */
339
340#define AR_MIBC_COW 0x00000001 /* counter overflow warning */
341#define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */
342#define AR_MIBC_CMC 0x00000004 /* clear MIB counters */
343#define AR_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
344
345#define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
346
347#define AR_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
348
349#define AR_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
350#define AR_TXNPTO_QCU_MASK 0x03FFFC00 /* Mask indicating the set of QCUs */
351 /* for which frame completions will cause */
352 /* a reset of the no frame transmitted timeout */
353
354#define AR_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
355
356#define AR_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
357
358#define AR_MACMISC_DMA_OBS_M 0x000001E0 /* Mask for DMA observation bus mux select */
359#define AR_MACMISC_DMA_OBS_S 5 /* Shift for DMA observation bus mux select */
360#define AR_MACMISC_MISC_OBS_M 0x00000E00 /* Mask for MISC observation bus mux select */
361#define AR_MACMISC_MISC_OBS_S 9 /* Shift for MISC observation bus mux select */
362#define AR_MACMISC_MAC_OBS_BUS_LSB_M 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
363#define AR_MACMISC_MAC_OBS_BUS_LSB_S 12 /* Shift for MAC observation bus mux select (lsb) */
364#define AR_MACMISC_MAC_OBS_BUS_MSB_M 0x00038000 /* Mask for MAC observation bus mux select (msb) */
365#define AR_MACMISC_MAC_OBS_BUS_MSB_S 15 /* Shift for MAC observation bus mux select (msb) */
366
367 /* Maui2/Spirit only. */
368#define AR5311_QDCLKGATE_QCU_M 0x0000FFFF /* Mask for QCU clock disable */
369#define AR5311_QDCLKGATE_DCU_M 0x07FF0000 /* Mask for DCU clock disable */
370
371 /* Interrupt Status Registers */
372#define AR_ISR_RXOK 0x00000001 /* At least one frame received sans errors */
373#define AR_ISR_RXDESC 0x00000002 /* Receive interrupt request */
374#define AR_ISR_RXERR 0x00000004 /* Receive error interrupt */
375#define AR_ISR_RXNOPKT 0x00000008 /* No frame received within timeout clock */
376#define AR_ISR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
377#define AR_ISR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
378#define AR_ISR_TXOK 0x00000040 /* Transmit okay interrupt */
379#define AR_ISR_TXDESC 0x00000080 /* Transmit interrupt request */
380#define AR_ISR_TXERR 0x00000100 /* Transmit error interrupt */
381#define AR_ISR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
382#define AR_ISR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
383#define AR_ISR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
384#define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
385#define AR_ISR_SWI 0x00002000 /* Software interrupt */
386#define AR_ISR_RXPHY 0x00004000 /* PHY receive error interrupt */
387#define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
388#define AR_ISR_SWBA 0x00010000 /* Software beacon alert interrupt */
389#define AR_ISR_BRSSI 0x00020000 /* Beacon threshold interrupt */
390#define AR_ISR_BMISS 0x00040000 /* Beacon missed interrupt */
391#define AR_ISR_HIUERR 0x00080000 /* An unexpected bus error has occurred */
392#define AR_ISR_BNR 0x00100000 /* Beacon not ready interrupt */
393#define AR_ISR_TIM 0x00800000 /* TIM interrupt */
394#define AR_ISR_GPIO 0x01000000 /* GPIO Interrupt */
395#define AR_ISR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
396#define AR_ISR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
397#define AR_ISR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
398#define AR_ISR_RESV0 0xF0000000 /* Reserved */
399
400#define AR_ISR_S0_QCU_TXOK_M 0x000003FF /* Mask for TXOK (QCU 0-9) */
401#define AR_ISR_S0_QCU_TXDESC_M 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
402
403#define AR_ISR_S1_QCU_TXERR_M 0x000003FF /* Mask for TXERR (QCU 0-9) */
404#define AR_ISR_S1_QCU_TXEOL_M 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
405
406#define AR_ISR_S2_QCU_TXURN_M 0x000003FF /* Mask for TXURN (QCU 0-9) */
407#define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
408#define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */
409#define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */
410#define AR_ISR_S2_RESV0 0xFFF80000 /* Reserved */
411
412#define AR_ISR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
413#define AR_ISR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
414
415#define AR_ISR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
416#define AR_ISR_S4_RESV0 0xFFFFFC00 /* Reserved */
417
418 /* Interrupt Mask Registers */
419#define AR_IMR_RXOK 0x00000001 /* At least one frame received sans errors */
420#define AR_IMR_RXDESC 0x00000002 /* Receive interrupt request */
421#define AR_IMR_RXERR 0x00000004 /* Receive error interrupt */
422#define AR_IMR_RXNOPKT 0x00000008 /* No frame received within timeout clock */
423#define AR_IMR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
424#define AR_IMR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
425#define AR_IMR_TXOK 0x00000040 /* Transmit okay interrupt */
426#define AR_IMR_TXDESC 0x00000080 /* Transmit interrupt request */
427#define AR_IMR_TXERR 0x00000100 /* Transmit error interrupt */
428#define AR_IMR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
429#define AR_IMR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
430#define AR_IMR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
431#define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
432#define AR_IMR_SWI 0x00002000 /* Software interrupt */
433#define AR_IMR_RXPHY 0x00004000 /* PHY receive error interrupt */
434#define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
435#define AR_IMR_SWBA 0x00010000 /* Software beacon alert interrupt */
436#define AR_IMR_BRSSI 0x00020000 /* Beacon threshold interrupt */
437#define AR_IMR_BMISS 0x00040000 /* Beacon missed interrupt */
438#define AR_IMR_HIUERR 0x00080000 /* An unexpected bus error has occurred */
439#define AR_IMR_BNR 0x00100000 /* BNR interrupt */
440#define AR_IMR_TIM 0x00800000 /* TIM interrupt */
441#define AR_IMR_GPIO 0x01000000 /* GPIO Interrupt */
442#define AR_IMR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
443#define AR_IMR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
444#define AR_IMR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
445#define AR_IMR_RESV0 0xF0000000 /* Reserved */
446
447#define AR_IMR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
448#define AR_IMR_S0_QCU_TXOK_S 0
449#define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
450#define AR_IMR_S0_QCU_TXDESC_S 16 /* Shift for TXDESC (QCU 0-9) */
451
452#define AR_IMR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
453#define AR_IMR_S1_QCU_TXERR_S 0
454#define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
455#define AR_IMR_S1_QCU_TXEOL_S 16 /* Shift for TXEOL (QCU 0-9) */
456
457#define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
458#define AR_IMR_S2_QCU_TXURN_S 0
459#define AR_IMR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
460#define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */
461#define AR_IMR_S2_DPERR 0x00040000 /* PCI bus parity error */
462#define AR_IMR_S2_RESV0 0xFFF80000 /* Reserved */
463
464#define AR_IMR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
465#define AR_IMR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
466#define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
467
468#define AR_IMR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
469#define AR_IMR_S4_RESV0 0xFFFFFC00 /* Reserved */
470
471 /* Interrupt status registers (read-and-clear access, secondary shadow copies) */
472
473 /* QCU registers */
474#define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
475#define AR_QCU_0 0x0001
476#define AR_QCU_1 0x0002
477#define AR_QCU_2 0x0004
478#define AR_QCU_3 0x0008
479#define AR_QCU_4 0x0010
480#define AR_QCU_5 0x0020
481#define AR_QCU_6 0x0040
482#define AR_QCU_7 0x0080
483#define AR_QCU_8 0x0100
484#define AR_QCU_9 0x0200
485
486#define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
487
488#define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
489
490#define AR_Q_CBRCFG_CBR_INTERVAL 0x00FFFFFF /* Mask for CBR interval (us) */
491#define AR_Q_CBRCFG_CBR_INTERVAL_S 0 /* Shift for CBR interval */
492#define AR_Q_CBRCFG_CBR_OVF_THRESH 0xFF000000 /* Mask for CBR overflow threshold */
493#define AR_Q_CBRCFG_CBR_OVF_THRESH_S 24 /* Shift for " " " */
494
495#define AR_Q_RDYTIMECFG_INT 0x00FFFFFF /* CBR interval (us) */
496#define AR_Q_RDYTIMECFG_INT_S 0 /* Shift for ReadyTime Interval (us) */
497#define AR_Q_RDYTIMECFG_DURATION_M 0x00FFFFFF /* Mask for CBR interval (us) */
498#define AR_Q_RDYTIMECFG_EN 0x01000000 /* ReadyTime enable */
499#define AR_Q_RDYTIMECFG_RESV0 0xFE000000 /* Reserved */
500
501#define AR_Q_ONESHOTARM_SC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */
502#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFF0000 /* Reserved */
503
504#define AR_Q_ONESHOTARM_CC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */
505#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFF0000 /* Reserved */
506
507#define AR_Q_MISC_FSP_M 0x0000000F /* Mask for Frame Scheduling Policy */
508#define AR_Q_MISC_FSP_ASAP 0 /* ASAP */
509#define AR_Q_MISC_FSP_CBR 1 /* CBR */
510#define AR_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
511#define AR_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
512#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
513#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 /* OneShot enable */
514#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 /* Disable CBR expired counter
515 incr (empty q) */
516#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 /* Disable CBR expired counter
517 incr (empty beacon q) */
518#define AR_Q_MISC_BEACON_USE 0x00000080 /* Beacon use indication */
519#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 /* CBR expired counter limit enable */
520#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
521#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 /* Reset CBR expired counter */
522#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 /* DCU frame early termination request control */
523#define AR_Q_MISC_RESV0 0xFFFFF000 /* Reserved */
524
525#define AR_Q_STS_PEND_FR_CNT_M 0x00000003 /* Mask for Pending Frame Count */
526#define AR_Q_STS_RESV0 0x000000FC /* Reserved */
527#define AR_Q_STS_CBR_EXP_CNT_M 0x0000FF00 /* Mask for CBR expired counter */
528#define AR_Q_STS_RESV1 0xFFFF0000 /* Reserved */
529
530#define AR_Q_RDYTIMESHDN_M 0x000003FF /* Mask for ReadyTimeShutdown status (QCU 0-9) */
531
532 /* DCU registers */
533#define AR_NUM_DCU 10 /* Only use 10 DCU's for forward QCU/DCU compatibility */
534#define AR_DCU_0 0x0001
535#define AR_DCU_1 0x0002
536#define AR_DCU_2 0x0004
537#define AR_DCU_3 0x0008
538#define AR_DCU_4 0x0010
539#define AR_DCU_5 0x0020
540#define AR_DCU_6 0x0040
541#define AR_DCU_7 0x0080
542#define AR_DCU_8 0x0100
543#define AR_DCU_9 0x0200
544
545#define AR_D_QCUMASK_M 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
546#define AR_D_QCUMASK_RESV0 0xFFFFFC00 /* Reserved */
547
548#define AR_D_LCL_IFS_CWMIN 0x000003FF /* Mask for CW_MIN */
549#define AR_D_LCL_IFS_CWMIN_S 0 /* Shift for CW_MIN */
550#define AR_D_LCL_IFS_CWMAX 0x000FFC00 /* Mask for CW_MAX */
551#define AR_D_LCL_IFS_CWMAX_S 10 /* Shift for CW_MAX */
552#define AR_D_LCL_IFS_AIFS 0x0FF00000 /* Mask for AIFS */
553#define AR_D_LCL_IFS_AIFS_S 20 /* Shift for AIFS */
554#define AR_D_LCL_IFS_RESV0 0xF0000000 /* Reserved */
555
556#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F /* Mask for frame short retry limit */
557#define AR_D_RETRY_LIMIT_FR_SH_S 0 /* Shift for frame short retry limit */
558#define AR_D_RETRY_LIMIT_FR_LG 0x000000F0 /* Mask for frame long retry limit */
559#define AR_D_RETRY_LIMIT_FR_LG_S 4 /* Shift for frame long retry limit */
560#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 /* Mask for station short retry limit */
561#define AR_D_RETRY_LIMIT_STA_SH_S 8 /* Shift for station short retry limit */
562#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 /* Mask for station short retry limit */
563#define AR_D_RETRY_LIMIT_STA_LG_S 14 /* Shift for station short retry limit */
564#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 /* Reserved */
565
566#define AR_D_CHNTIME_EN 0x00100000 /* ChannelTime enable */
567#define AR_D_CHNTIME_RESV0 0xFFE00000 /* Reserved */
568#define AR_D_CHNTIME_DUR 0x000FFFFF /* Mask for ChannelTime duration (us) */
569#define AR_D_CHNTIME_DUR_S 0 /* Shift for ChannelTime duration */
570
571#define AR_D_MISC_BKOFF_THRESH_M 0x000007FF /* Mask for Backoff threshold setting */
572#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 /* Backoff during a frag burst */
573#define AR_D_MISC_HCF_POLL_EN 0x00000800 /* HFC poll enable */
574#define AR_D_MISC_BKOFF_PERSISTENCE 0x00001000 /* Backoff persistence factor setting */
575#define AR_D_MISC_FR_PREFETCH_EN 0x00002000 /* Frame prefetch enable */
576#define AR_D_MISC_VIR_COL_HANDLING_M 0x0000C000 /* Mask for Virtual collision handling policy */
577#define AR_D_MISC_VIR_COL_HANDLING_NORMAL 0 /* Normal */
578#define AR_D_MISC_VIR_COL_HANDLING_MODIFIED 1 /* Modified */
579#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 2 /* Ignore */
580#define AR_D_MISC_BEACON_USE 0x00010000 /* Beacon use indication */
581#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 /* Mask for DCU arbiter lockout control */
582#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 /* Shift for DCU arbiter lockout control */
583#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout */
584#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
585#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
586#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 /* DCU arbiter lockout ignore control */
587#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Sequence number increment disable */
588#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
589#define AR_D_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual coll. handling policy */
590#define AR_D_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS handling policy */
591#define AR5311_D_MISC_SEQ_NUM_CONTROL 0x01000000 /* Sequence Number local or global */
592 /* Maui2/Spirit only, reserved on Oahu */
593#define AR_D_MISC_RESV0 0xFE000000 /* Reserved */
594
595#define AR_D_SEQNUM_M 0x00000FFF /* Mask for value of sequence number */
596#define AR_D_SEQNUM_RESV0 0xFFFFF000 /* Reserved */
597
598#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 /* Mask forLFSR slice select */
599#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode indication */
600#define AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC 0x000003F0 /* Mask for SIFS duration (us) */
601#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 /* Mask for microsecond duration */
602#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 /* Mask for DCU arbiter delay */
603#define AR_D_GBL_IFS_MISC_RESV0 0xFFC00000 /* Reserved */
604
605/* Oahu only */
606#define AR_D_TXPSE_CTRL_M 0x000003FF /* Mask of DCUs to pause (DCUs 0-9) */
607#define AR_D_TXPSE_RESV0 0x0000FC00 /* Reserved */
608#define AR_D_TXPSE_STATUS 0x00010000 /* Transmit pause status */
609#define AR_D_TXPSE_RESV1 0xFFFE0000 /* Reserved */
610
611 /* DMA & PCI Registers in PCI space (usable during sleep) */
612#define AR_RC_MAC 0x00000001 /* MAC reset */
613#define AR_RC_BB 0x00000002 /* Baseband reset */
614#define AR_RC_RESV0 0x00000004 /* Reserved */
615#define AR_RC_RESV1 0x00000008 /* Reserved */
616#define AR_RC_PCI 0x00000010 /* PCI-core reset */
617#define AR_RC_BITS "\20\1MAC\2BB\3RESV0\4RESV1\5RPCI"
618
619#define AR_SCR_SLDUR 0x0000ffff /* sleep duration mask, units of 128us */
620#define AR_SCR_SLDUR_S 0
621#define AR_SCR_SLE 0x00030000 /* sleep enable mask */
622#define AR_SCR_SLE_S 16 /* sleep enable bits shift */
623/*
624 * The previous values for the following three defines were:
625 *
626 * AR_SCR_SLE_WAKE 0x00000000
627 * AR_SCR_SLE_SLP 0x00010000
628 * AR_SCR_SLE_NORM 0x00020000
629 *
630 * However, these have been pre-shifted with AR_SCR_SLE_S. The
631 * OS_REG_READ() macro would attempt to shift them again, effectively
632 * shifting out any of the set bits completely.
633 */
634#define AR_SCR_SLE_WAKE 0 /* force wake */
635#define AR_SCR_SLE_SLP 1 /* force sleep */
636#define AR_SCR_SLE_NORM 2 /* sleep logic normal operation */
637#define AR_SCR_SLE_UNITS 0x00000008 /* SCR units/TU */
638#define AR_SCR_BITS "\20\20SLE_SLP\21SLE"
639
640#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */
641#define AR_INTPEND_BITS "\20\1IP"
642
643#define AR_SFR_SLEEP 0x00000001 /* force sleep */
644
645#define AR_PCICFG_CLKRUNEN 0x00000004 /* enable PCI CLKRUN function */
646#define AR_PCICFG_EEPROM_SIZE_M 0x00000018 /* Mask for EEPROM size */
647#define AR_PCICFG_EEPROM_SIZE_S 3 /* Mask for EEPROM size */
648#define AR_PCICFG_EEPROM_SIZE_4K 0 /* EEPROM size 4 Kbit */
649#define AR_PCICFG_EEPROM_SIZE_8K 1 /* EEPROM size 8 Kbit */
650#define AR_PCICFG_EEPROM_SIZE_16K 2 /* EEPROM size 16 Kbit */
651#define AR_PCICFG_EEPROM_SIZE_FAILED 3 /* Failure */
652#define AR_PCICFG_LEDCTL 0x00000060 /* LED control Status */
653#define AR_PCICFG_LEDCTL_NONE 0x00000000 /* STA is not associated or trying */
654#define AR_PCICFG_LEDCTL_PEND 0x00000020 /* STA is trying to associate */
655#define AR_PCICFG_LEDCTL_ASSOC 0x00000040 /* STA is associated */
656#define AR_PCICFG_PCI_BUS_SEL_M 0x00000380 /* Mask for PCI observation bus mux select */
657#define AR_PCICFG_DIS_CBE_FIX 0x00000400 /* Disable fix for bad PCI CBE# generation */
658#define AR_PCICFG_SL_INTEN 0x00000800 /* enable interrupt line assertion when asleep */
659#define AR_PCICFG_RESV0 0x00001000 /* Reserved */
660#define AR_PCICFG_SL_INPEN 0x00002000 /* Force asleep when an interrupt is pending */
661#define AR_PCICFG_RESV1 0x0000C000 /* Reserved */
662#define AR_PCICFG_SPWR_DN 0x00010000 /* mask for sleep/awake indication */
663#define AR_PCICFG_LEDMODE 0x000E0000 /* LED mode */
664#define AR_PCICFG_LEDMODE_PROP 0x00000000 /* Blink prop to filtered tx/rx */
665#define AR_PCICFG_LEDMODE_RPROP 0x00020000 /* Blink prop to unfiltered tx/rx */
666#define AR_PCICFG_LEDMODE_SPLIT 0x00040000 /* Blink power for tx/net for rx */
667#define AR_PCICFG_LEDMODE_RAND 0x00060000 /* Blink randomly */
668#define AR_PCICFG_LEDBLINK 0x00700000 /* LED blink threshold select */
669#define AR_PCICFG_LEDBLINK_S 20
670#define AR_PCICFG_LEDSLOW 0x00800000 /* LED slowest blink rate mode */
671#define AR_PCICFG_RESV2 0xFF000000 /* Reserved */
672#define AR_PCICFG_BITS "\20\3CLKRUNEN\13SL_INTEN"
673
674#define AR_GPIOCR_CR_SHIFT 2 /* Each CR is 2 bits */
675#define AR_GPIOCR_0_CR_N 0x00000000 /* Input only mode for GPIODO[0] */
676#define AR_GPIOCR_0_CR_0 0x00000001 /* Output only if GPIODO[0] = 0 */
677#define AR_GPIOCR_0_CR_1 0x00000002 /* Output only if GPIODO[0] = 1 */
678#define AR_GPIOCR_0_CR_A 0x00000003 /* Always output */
679#define AR_GPIOCR_1_CR_N 0x00000000 /* Input only mode for GPIODO[1] */
680#define AR_GPIOCR_1_CR_0 0x00000004 /* Output only if GPIODO[1] = 0 */
681#define AR_GPIOCR_1_CR_1 0x00000008 /* Output only if GPIODO[1] = 1 */
682#define AR_GPIOCR_1_CR_A 0x0000000C /* Always output */
683#define AR_GPIOCR_2_CR_N 0x00000000 /* Input only mode for GPIODO[2] */
684#define AR_GPIOCR_2_CR_0 0x00000010 /* Output only if GPIODO[2] = 0 */
685#define AR_GPIOCR_2_CR_1 0x00000020 /* Output only if GPIODO[2] = 1 */
686#define AR_GPIOCR_2_CR_A 0x00000030 /* Always output */
687#define AR_GPIOCR_3_CR_N 0x00000000 /* Input only mode for GPIODO[3] */
688#define AR_GPIOCR_3_CR_0 0x00000040 /* Output only if GPIODO[3] = 0 */
689#define AR_GPIOCR_3_CR_1 0x00000080 /* Output only if GPIODO[3] = 1 */
690#define AR_GPIOCR_3_CR_A 0x000000C0 /* Always output */
691#define AR_GPIOCR_4_CR_N 0x00000000 /* Input only mode for GPIODO[4] */
692#define AR_GPIOCR_4_CR_0 0x00000100 /* Output only if GPIODO[4] = 0 */
693#define AR_GPIOCR_4_CR_1 0x00000200 /* Output only if GPIODO[4] = 1 */
694#define AR_GPIOCR_4_CR_A 0x00000300 /* Always output */
695#define AR_GPIOCR_5_CR_N 0x00000000 /* Input only mode for GPIODO[5] */
696#define AR_GPIOCR_5_CR_0 0x00000400 /* Output only if GPIODO[5] = 0 */
697#define AR_GPIOCR_5_CR_1 0x00000800 /* Output only if GPIODO[5] = 1 */
698#define AR_GPIOCR_5_CR_A 0x00000C00 /* Always output */
699#define AR_GPIOCR_INT_SHIFT 12 /* Interrupt select field shifter */
700#define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */
701#define AR_GPIOCR_INT_SEL0 0x00000000 /* Select Interrupt Pin GPIO_0 */
702#define AR_GPIOCR_INT_SEL1 0x00001000 /* Select Interrupt Pin GPIO_1 */
703#define AR_GPIOCR_INT_SEL2 0x00002000 /* Select Interrupt Pin GPIO_2 */
704#define AR_GPIOCR_INT_SEL3 0x00003000 /* Select Interrupt Pin GPIO_3 */
705#define AR_GPIOCR_INT_SEL4 0x00004000 /* Select Interrupt Pin GPIO_4 */
706#define AR_GPIOCR_INT_SEL5 0x00005000 /* Select Interrupt Pin GPIO_5 */
707#define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO Interrupt */
708#define AR_GPIOCR_INT_SELL 0x00000000 /* Generate Interrupt if selected pin is low */
709#define AR_GPIOCR_INT_SELH 0x00010000 /* Generate Interrupt if selected pin is high */
710
711#define AR_SREV_ID_M 0x000000FF /* Mask to read SREV info */
712#define AR_PCICFG_EEPROM_SIZE_16K 2 /* EEPROM size 16 Kbit */
713#define AR_SREV_ID_S 4 /* Major Rev Info */
714#define AR_SREV_REVISION_M 0x0000000F /* Chip revision level */
715#define AR_SREV_FPGA 1
716#define AR_SREV_D2PLUS 2
717#define AR_SREV_D2PLUS_MS 3 /* metal spin */
718#define AR_SREV_CRETE 4
719#define AR_SREV_CRETE_MS 5 /* FCS metal spin */
720#define AR_SREV_CRETE_MS23 7 /* 2.3 metal spin (6 skipped) */
721#define AR_SREV_CRETE_23 8 /* 2.3 full tape out */
722#define AR_SREV_VERSION_M 0x000000F0 /* Chip version indication */
723#define AR_SREV_VERSION_CRETE 0
724#define AR_SREV_VERSION_MAUI_1 1
725#define AR_SREV_VERSION_MAUI_2 2
726#define AR_SREV_VERSION_SPIRIT 3
727#define AR_SREV_VERSION_OAHU 4
728#define AR_SREV_OAHU_ES 0 /* Engineering Sample */
729#define AR_SREV_OAHU_PROD 2 /* Production */
730
731#define RAD5_SREV_MAJOR 0x10 /* All current supported ar5211 5 GHz radios are rev 0x10 */
732#define RAD5_SREV_PROD 0x15 /* Current production level radios */
733#define RAD2_SREV_MAJOR 0x20 /* All current supported ar5211 2 GHz radios are rev 0x10 */
734
735 /* EEPROM Registers in the MAC */
736#define AR_EEPROM_CMD_READ 0x00000001
737#define AR_EEPROM_CMD_WRITE 0x00000002
738#define AR_EEPROM_CMD_RESET 0x00000004
739
740#define AR_EEPROM_STS_READ_ERROR 0x00000001
741#define AR_EEPROM_STS_READ_COMPLETE 0x00000002
742#define AR_EEPROM_STS_WRITE_ERROR 0x00000004
743#define AR_EEPROM_STS_WRITE_COMPLETE 0x00000008
744
745#define AR_EEPROM_CFG_SIZE_M 0x00000003 /* Mask for EEPROM size determination override */
746#define AR_EEPROM_CFG_SIZE_AUTO 0
747#define AR_EEPROM_CFG_SIZE_4KBIT 1
748#define AR_EEPROM_CFG_SIZE_8KBIT 2
749#define AR_EEPROM_CFG_SIZE_16KBIT 3
750#define AR_EEPROM_CFG_DIS_WAIT_WRITE_COMPL 0x00000004 /* Disable wait for write completion */
751#define AR_EEPROM_CFG_CLOCK_M 0x00000018 /* Mask for EEPROM clock rate control */
752#define AR_EEPROM_CFG_CLOCK_S 3 /* Shift for EEPROM clock rate control */
753#define AR_EEPROM_CFG_CLOCK_156KHZ 0
754#define AR_EEPROM_CFG_CLOCK_312KHZ 1
755#define AR_EEPROM_CFG_CLOCK_625KHZ 2
756#define AR_EEPROM_CFG_RESV0 0x000000E0 /* Reserved */
757#define AR_EEPROM_CFG_PROT_KEY_M 0x00FFFF00 /* Mask for EEPROM protection key */
758#define AR_EEPROM_CFG_PROT_KEY_S 8 /* Shift for EEPROM protection key */
759#define AR_EEPROM_CFG_EN_L 0x01000000 /* EPRM_EN_L setting */
760
761 /* MAC PCU Registers */
762#define AR_STA_ID1_SADH_MASK 0x0000FFFF /* Mask for upper 16 bits of MAC addr */
763#define AR_STA_ID1_STA_AP 0x00010000 /* Device is AP */
764#define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
765#define AR_STA_ID1_PWR_SAV 0x00040000 /* Power save reporting in self-generated frames */
766#define AR_STA_ID1_KSRCHDIS 0x00080000 /* Key search disable */
767#define AR_STA_ID1_PCF 0x00100000 /* Observe PCF */
768#define AR_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
769#define AR_STA_ID1_DESC_ANTENNA 0x00400000 /* Update default antenna w/ TX antenna */
770#define AR_STA_ID1_RTS_USE_DEF 0x00800000 /* Use default antenna to send RTS */
771#define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mb/s rate for ACK & CTS */
772#define AR_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK & CTS */
773#define AR_STA_ID1_BITS \
774 "\20\20AP\21ADHOC\22PWR_SAV\23KSRCHDIS\25PCF"
775
776#define AR_BSS_ID1_U16_M 0x0000FFFF /* Mask for upper 16 bits of BSSID */
777#define AR_BSS_ID1_AID_M 0xFFFF0000 /* Mask for association ID */
778#define AR_BSS_ID1_AID_S 16 /* Shift for association ID */
779
780#define AR_SLOT_TIME_MASK 0x000007FF /* Slot time mask */
781
782#define AR_TIME_OUT_ACK 0x00001FFF /* Mask for ACK time-out */
783#define AR_TIME_OUT_ACK_S 0 /* Shift for ACK time-out */
784#define AR_TIME_OUT_CTS 0x1FFF0000 /* Mask for CTS time-out */
785#define AR_TIME_OUT_CTS_S 16 /* Shift for CTS time-out */
786
787#define AR_RSSI_THR_MASK 0x000000FF /* Mask for Beacon RSSI warning threshold */
788#define AR_RSSI_THR_BM_THR 0x0000FF00 /* Mask for Missed beacon threshold */
789#define AR_RSSI_THR_BM_THR_S 8 /* Shift for Missed beacon threshold */
790
791#define AR_USEC_M 0x0000007F /* Mask for clock cycles in 1 usec */
792#define AR_USEC_32_M 0x00003F80 /* Mask for number of 32MHz clock cycles in 1 usec */
793#define AR_USEC_32_S 7 /* Shift for number of 32MHz clock cycles in 1 usec */
794/*
795 * Tx/Rx latencies are to signal start and are in usecs.
796 *
797 * NOTE: AR5211/AR5311 difference: on Oahu, the TX latency field
798 * has increased from 6 bits to 9 bits. The RX latency field
799 * is unchanged, but is shifted over 3 bits.
800 */
801#define AR5311_USEC_TX_LAT_M 0x000FC000 /* Tx latency */
802#define AR5311_USEC_TX_LAT_S 14
803#define AR5311_USEC_RX_LAT_M 0x03F00000 /* Rx latency */
804#define AR5311_USEC_RX_LAT_S 20
805
806#define AR5211_USEC_TX_LAT_M 0x007FC000 /* Tx latency */
807#define AR5211_USEC_TX_LAT_S 14
808#define AR5211_USEC_RX_LAT_M 0x1F800000 /* Rx latency */
809#define AR5211_USEC_RX_LAT_S 23
810
811#define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period in TU/msec */
812#define AR_BEACON_PERIOD_S 0 /* Byte offset of PERIOD start*/
813#define AR_BEACON_TIM 0x007F0000 /* Byte offset of TIM start */
814#define AR_BEACON_TIM_S 16 /* Byte offset of TIM start */
815#define AR_BEACON_EN 0x00800000 /* beacon enable */
816#define AR_BEACON_RESET_TSF 0x01000000 /* Clears TSF to 0 */
817#define AR_BEACON_BITS "\20\27ENABLE\30RESET_TSF"
818
819#define AR_RX_FILTER_ALL 0x00000000 /* Disallow all frames */
820#define AR_RX_UCAST 0x00000001 /* Allow unicast frames */
821#define AR_RX_MCAST 0x00000002 /* Allow multicast frames */
822#define AR_RX_BCAST 0x00000004 /* Allow broadcast frames */
823#define AR_RX_CONTROL 0x00000008 /* Allow control frames */
824#define AR_RX_BEACON 0x00000010 /* Allow beacon frames */
825#define AR_RX_PROM 0x00000020 /* Promiscuous mode */
826#define AR_RX_PHY_ERR 0x00000040 /* Allow all phy errors */
827#define AR_RX_PHY_RADAR 0x00000080 /* Allow radar phy errors */
828#define AR_RX_FILTER_BITS \
829 "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC\7PHY_ERR\10PHY_RADAR"
830
831#define AR_DIAG_SW_CACHE_ACK 0x00000001 /* disable ACK if no valid key*/
832#define AR_DIAG_SW_DIS_ACK 0x00000002 /* disable ACK generation */
833#define AR_DIAG_SW_DIS_CTS 0x00000004 /* disable CTS generation */
834#define AR_DIAG_SW_DIS_ENCRYPT 0x00000008 /* disable encryption */
835#define AR_DIAG_SW_DIS_DECRYPT 0x00000010 /* disable decryption */
836#define AR_DIAG_SW_DIS_RX 0x00000020 /* disable receive */
837#define AR_DIAG_SW_CORR_FCS 0x00000080 /* corrupt FCS */
838#define AR_DIAG_SW_CHAN_INFO 0x00000100 /* dump channel info */
839#define AR_DIAG_SW_EN_SCRAMSD 0x00000200 /* enable fixed scrambler seed*/
840#define AR5311_DIAG_SW_USE_ECO 0x00000400 /* "super secret" use ECO enable bit */
841#define AR_DIAG_SW_SCRAM_SEED_M 0x0001FC00 /* Fixed scrambler seed mask */
842#define AR_DIAG_SW_SCRAM_SEED_S 10 /* Fixed scrambler seed shfit */
843#define AR_DIAG_SW_FRAME_NV0 0x00020000 /* accept frames of non-zero protocol version */
844#define AR_DIAG_SW_OBS_PT_SEL_M 0x000C0000 /* Observation point select */
845#define AR_DIAG_SW_OBS_PT_SEL_S 18 /* Observation point select */
846#define AR_DIAG_SW_BITS \
847 "\20\1DIS_CACHE_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_RX"\
848 "\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED\14USE_ECO\24FRAME_NV0"
849
850#define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */
851#define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */
852#define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */
853#define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */
854#define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */
855#define AR_KEYTABLE_TYPE(n) (AR_KEYTABLE(n) + 20) /* key type */
856#define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */
857#define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */
858#define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */
859#define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES 128 bit key */
860#define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */
861#define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */
862#define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */
863#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */
864
865#endif /* _DEV_ATH_AR5211REG_H */