33#include <sys/condvar.h>
34#include <sys/kernel.h>
36#include <sys/module.h>
39#include <sys/socket.h>
40#include <sys/sysctl.h>
41#include <sys/unistd.h>
44#include <net/if_var.h>
45#include <net/if_media.h>
48#include <netinet/in.h>
49#include <netinet/ip.h>
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
59#define USB_DEBUG_VAR ure_debug
71static int ure_debug = 0;
73static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
81#define DEVPRINTFN(n,dev,fmt,...) do { \
82 if ((USB_DEBUG_VAR) >= (n)) { \
83 device_printf((dev), "%s: " fmt, \
84 __FUNCTION__ ,##__VA_ARGS__); \
87#define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__)
89#define DEVPRINTF(...) do { } while (0)
90#define DEVPRINTFN(...) do { } while (0)
98#define URE_DEV(v,p,i) { \
99 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \
100 USB_IFACE_CLASS(UICLASS_VENDOR), \
101 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) }
104 URE_DEV(LENOVO, TBT3LANGEN2, 0),
107 URE_DEV(LENOVO, USBCLANGEN2, 0),
160static int ure_ioctl(
struct ifnet *, u_long, caddr_t);
170static int ure_txcsum(
struct mbuf *m,
int caps, uint32_t *regout);
216#define URE_SETBIT_1(sc, reg, index, x) \
217 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
218#define URE_SETBIT_2(sc, reg, index, x) \
219 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
220#define URE_SETBIT_4(sc, reg, index, x) \
221 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
223#define URE_CLRBIT_1(sc, reg, index, x) \
224 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
225#define URE_CLRBIT_2(sc, reg, index, x) \
226 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
227#define URE_CLRBIT_4(sc, reg, index, x) \
228 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
273 shift = (
reg & 3) << 3;
290 shift = (
reg & 2) << 3;
297 return (
val & 0xffff);
322 val <<= (shift << 3);
343 val <<= (shift << 3);
366 reg = (
addr & 0x0fff) | 0xb000;
377 reg = (
addr & 0x0fff) | 0xb000;
396 sc = device_get_softc(
dev);
397 locked = mtx_owned(&sc->
sc_mtx);
421 sc = device_get_softc(
dev);
425 locked = mtx_owned(&sc->
sc_mtx);
440 struct mii_data *mii;
444 sc = device_get_softc(
dev);
446 locked = mtx_owned(&sc->
sc_mtx);
451 if (mii == NULL || ifp == NULL ||
452 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
456 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
457 (IFM_ACTIVE | IFM_AVALID)) {
458 switch (IFM_SUBTYPE(mii->mii_media_active)) {
491 uaa = device_get_ivars(
dev);
518 mtx_init(&sc->
sc_mtx, device_get_nameunit(
dev), NULL, MTX_DEF);
535 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
543 device_printf(
dev,
"allocating USB RX transfers failed\n");
553 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
562 device_printf(
dev,
"allocating USB TX transfers failed\n");
574 device_printf(
dev,
"could not attach interface\n");
608 struct usb_page_search_res;
612 m = m_getm2(NULL,
len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR);
617 m_adj(m, ETHER_ALIGN);
619 m->m_pkthdr.len =
len;
621 for (mb = m;
len > 0; mb = mb->m_next) {
622 tlen = MIN(
len, M_TRAILINGSPACE(mb));
643 int actlen, off,
len;
653 caps = if_getcapenable(ifp);
656 if (actlen < (
int)(
sizeof(pkt))) {
657 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
663 actlen -=
sizeof(pkt);
668 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n",
682 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
687 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
691 if (
len >= (ETHER_HDR_LEN + ETHER_CRC_LEN))
696 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
700 if (caps & IFCAP_VLAN_HWTAGGING &&
702 m->m_pkthdr.ether_vtag =
705 m->m_flags |= M_VLANTAG;
728 DPRINTF(
"bulk read error, %s\n",
755 DPRINTFN(11,
"transfer complete\n");
756 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
767 caps = if_getcapenable(ifp);
771 while (rem >
sizeof(txpkt)) {
772 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
780 len = m->m_pkthdr.len;
783 "pkt len too large: %#x",
len);
785 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
793 IFQ_DRV_PREPEND(&ifp->if_snd, m);
801 if (m->m_flags & M_VLANTAG) {
803 bswap16(m->m_pkthdr.ether_vtag &
808 "pkt l4 off too large");
814 "txpkt: mbflg: %#x, %#x, %#x\n",
815 m->m_pkthdr.csum_flags, le32toh(txpkt.
ure_pktlen),
820 pos +=
sizeof(txpkt);
821 rem -=
sizeof(txpkt);
828 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
851 DPRINTFN(11,
"transfer error, %s\n",
854 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
855 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
928 "unknown version 0x%04x\n", ver);
940 sbuf_new_for_sysctl(&sb, NULL, 0,
req);
942 sbuf_printf(&sb,
"%04x", sc->
sc_ver);
944 error = sbuf_finish(&sb);
978 device_printf(sc->
sc_ue.
ue_dev,
"MAC assigned randomly\n");
988 struct sysctl_ctx_list *sctx;
989 struct sysctl_oid *soid;
996 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1000 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
1005 ifp->if_snd.ifq_drv_maxlen = 512;
1006 IFQ_SET_READY(&ifp->if_snd);
1008 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1009 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
1010 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);
1011 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1013 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);
1015 if_setcapenable(ifp, if_getcapabilities(ifp));
1021 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1022 ifmedia_set(&sc->
sc_ifmedia, IFM_ETHER | IFM_AUTO);
1023 sc->
sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
1029 BMSR_DEFCAPMASK, sc->
sc_phyno, MII_OFFSET_ANY, 0);
1035 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
"chipver",
1036 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1038 "Return string with chip version.");
1053 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1117 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1122 cpcr &= ~URE_CPCR_RX_VLAN;
1137 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1148 struct mii_data *mii;
1167 && mii->mii_media_status & IFM_ACTIVE &&
1168 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1179 uint32_t h, *hashes = arg;
1181 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
1183 hashes[0] |= (1 << h);
1185 hashes[1] |= (1 << (h - 32));
1198 uint32_t h, hashes[2] = { 0, 0 };
1206 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1207 if (ifp->if_flags & IFF_PROMISC)
1210 hashes[0] = hashes[1] = 0xffffffff;
1217 h = bswap32(hashes[0]);
1218 hashes[0] = bswap32(hashes[1]);
1262 device_printf(sc->
sc_ue.
ue_dev,
"reset never completed\n");
1272 struct ifmedia *ifm;
1273 struct mii_data *mii;
1274 struct mii_softc *miisc;
1283 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1286 locked = mtx_owned(&sc->
sc_mtx);
1290 reg &= ~URE_ADV_2500TFDX;
1293 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1295 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1296 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1300 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1301 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1303 ifp->if_baudrate = IF_Mbps(2500);
1306 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1307 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1308 ifp->if_baudrate = IF_Gbps(1);
1311 anar |= ANAR_TX | ANAR_TX_FD;
1312 ifp->if_baudrate = IF_Mbps(100);
1315 anar |= ANAR_10 | ANAR_10_FD;
1316 ifp->if_baudrate = IF_Mbps(10);
1319 device_printf(sc->
sc_ue.
ue_dev,
"unsupported media type\n");
1326 anar | ANAR_PAUSE_ASYM | ANAR_FC);
1330 BMCR_AUTOEN | BMCR_STARTNEG);
1339 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1341 error = mii_mediachg(mii);
1352 struct mii_data *mii;
1358 ifmr->ifm_status = IFM_AVALID;
1360 ifmr->ifm_status |= IFM_ACTIVE;
1365 ifmr->ifm_active |= IFM_FDX;
1367 ifmr->ifm_active |= IFM_HDX;
1369 ifmr->ifm_active |= IFM_10_T;
1371 ifmr->ifm_active |= IFM_100_TX;
1373 ifmr->ifm_active |= IFM_1000_T;
1375 ifmr->ifm_active |= IFM_2500_T;
1385 ifmr->ifm_active = mii->mii_media_active;
1386 ifmr->ifm_status = mii->mii_media_status;
1393 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1394 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1395 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1396 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1397 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1398 ifmedia_add(&sc->
sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
1407 if (ifp->if_link_state != LINK_STATE_UP) {
1408 if_link_state_change(ifp, LINK_STATE_UP);
1419 if (ifp->if_link_state != LINK_STATE_DOWN) {
1420 if_link_state_change(ifp, LINK_STATE_DOWN);
1444 int error, mask, reinit;
1447 ifr = (
struct ifreq *)
data;
1453 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1454 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1455 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1456 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1459 if ((mask & IFCAP_TXCSUM) != 0 &&
1460 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1461 ifp->if_capenable ^= IFCAP_TXCSUM;
1463 if ((mask & IFCAP_RXCSUM) != 0 &&
1464 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1465 ifp->if_capenable ^= IFCAP_RXCSUM;
1467 if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&
1468 (ifp->if_capabilities & IFCAP_TXCSUM_IPV6) != 0) {
1469 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1471 if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&
1472 (ifp->if_capabilities & IFCAP_RXCSUM_IPV6) != 0) {
1473 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1475 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
1476 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1490 if (ifr->ifr_mtu < ETHERMIN ||
1491 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN -
1492 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) {
1497 if (if_getmtu(ifp) != ifr->ifr_mtu)
1498 if_setmtu(ifp, ifr->ifr_mtu);
1536 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1566 memset(u1u2, 0x00,
sizeof(u1u2));
1578 "timeout waiting for chip autoload\n");
1589 "timeout waiting for phy to stabilize\n");
1595 val &= ~URE_PWD_DN_SCALE_MASK;
1607 val &= ~URE_DYNAMIC_BURST;
1628 val &= ~URE_SEN_VAL_MASK;
1638 memset(u1u2, 0xff,
sizeof(u1u2));
1658 val &= ~URE_U2P3_ENABLE;
1661 memset(u1u2, 0x00,
sizeof(u1u2));
1705 val &= ~URE_U2P3_ENABLE;
1708 memset(u1u2, 0xff,
sizeof(u1u2));
1738 for (i=0; i < 100; i++) {
1754 "timeout waiting for chip autoload\n");
1767 if (
val & BMCR_PDOWN) {
1826 val &= ~URE_CUR_LINK_OK;
1893 "timeout waiting for OOB control\n");
1904 "timeout waiting for OOB control\n");
1910 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
1914 val = if_getmtu(ifp);
1981 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2020 for (i = 0; i < 20; i++) {
2050 "timeout waiting for phy to stabilize\n");
2058 uint32_t rx_fifo1, rx_fifo2;
2083 "timeout waiting for OOB control\n");
2093 "timeout waiting for OOB control\n");
2124 uint32_t csum, misc;
2127 m->m_pkthdr.csum_flags = 0;
2129 if (!(capenb & IFCAP_RXCSUM))
2139 flags |= CSUM_IP_CHECKED;
2146 if (__predict_true((flags & CSUM_IP_CHECKED) &&
2148 flags |= CSUM_IP_VALID;
2153 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2154 m->m_pkthdr.csum_data = 0xFFFF;
2157 m->m_pkthdr.csum_flags = flags;
2173 struct ether_header *eh;
2181 flags = m->m_pkthdr.csum_flags;
2185 if (__predict_true(m->m_len >= (
int)
sizeof(*eh))) {
2186 eh = mtod(m,
struct ether_header *);
2187 type = eh->ether_type;
2189 m_copydata(m, offsetof(
struct ether_header, ether_type),
2194 case ETHERTYPE_IPV6:
2195 l3off = ETHER_HDR_LEN;
2197 case ETHERTYPE_VLAN:
2199 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2207 if (flags & CSUM_IP)
2210 data = m->m_pkthdr.csum_data;
2211 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) {
2212 m_copydata(m, l3off,
sizeof ip, (caddr_t)&ip);
2213 l4off = l3off + (ip.ip_hl << 2) +
data;
2218 if (flags & CSUM_IP_TCP)
2220 else if (flags & CSUM_IP_UDP)
2225 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
2226 l4off = l3off +
data;
2231 if (flags & CSUM_IP6_TCP)
2233 else if (flags & CSUM_IP6_UDP)
static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW|CTLFLAG_MPSAFE, 0, "USB DWC OTG")
SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+")
static uether_fn_t ure_attach_post
#define URE_SETBIT_2(sc, reg, index, x)
static u_int ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
static void ure_link_state(struct ure_softc *sc)
static struct mbuf * ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, usb_frlength_t len)
static uether_fn_t ure_init
static void ure_rtl8152_init(struct ure_softc *)
static usb_callback_t ure_bulk_read_callback
static uether_fn_t ure_stop
static uether_fn_t ure_rxfilter
#define URE_CLRBIT_2(sc, reg, index, x)
static const STRUCT_USB_HOST_ID ure_devs[]
static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t)
static void ure_disable_teredo(struct ure_softc *)
static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, void *, int)
MODULE_DEPEND(ure, uether, 1, 1, 1)
static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m)
static void ure_rtl8152_nic_reset(struct ure_softc *)
static device_attach_t ure_attach
static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t)
static miibus_readreg_t ure_miibus_readreg
static int ure_ioctl(struct ifnet *, u_long, caddr_t)
static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)
static void ure_add_media_types(struct ure_softc *)
static uether_fn_t ure_start
static void ure_rtl8153_init(struct ure_softc *)
static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, int)
static device_detach_t ure_detach
static int ure_get_link_status(struct ure_softc *)
static void ure_enable_aldps(struct ure_softc *, bool)
#define URE_SETBIT_1(sc, reg, index, x)
static device_method_t ure_methods[]
#define URE_CLRBIT_1(sc, reg, index, x)
static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t)
static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *)
static uether_fn_t ure_tick
static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, int)
#define URE_CLRBIT_4(sc, reg, index, x)
static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t)
static int ure_attach_post_sub(struct usb_ether *)
DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL)
static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t)
static device_probe_t ure_probe
static void ure_reset(struct ure_softc *)
static devclass_t ure_devclass
static driver_t ure_driver
static uint16_t ure_phy_status(struct ure_softc *, uint16_t)
static void ure_rtl8153b_init(struct ure_softc *)
static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t)
static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout)
USB_PNP_HOST_INFO(ure_devs)
static miibus_writereg_t ure_miibus_writereg
static const struct usb_ether_methods ure_ue_methods
static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t)
static int ure_ifmedia_upd(struct ifnet *)
static miibus_statchg_t ure_miibus_statchg
static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t)
static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t)
static void ure_rtl8153b_nic_reset(struct ure_softc *)
static void ure_read_chipver(struct ure_softc *)
static usb_callback_t ure_bulk_write_callback
#define URE_PHYSTATUS_FDX
#define URE_USB_U1U2_TIMER
#define URE_PKT_AVAIL_SPDWN_EN
#define URE_PHYSTATUS_100MBPS
#define URE_LOCK_ASSERT(_sc, t)
#define URE_SEN_VAL_NORMAL
#define URE_SRAM_10M_AMP2
#define URE_TXFIFO_THR_NORMAL
#define URE_USB_SSPHYLINK2
#define URE_USB_RX_BUF_TH
#define URE_RXDY_GATED_EN
#define URE_CHIP_VER_6000
#define URE_L4_OFFSET_MAX
#define URE_PHYSTATUS_10MBPS
#define URE_USB_WDT11_CTRL
#define URE_PLA_RXFIFO_CTRL1
#define URE_RESUME_INDICATE
#define URE_POLL_LINK_CHG
#define URE_BMU_RESET_EP_IN
#define URE_PLA_MAC_PWR_CTRL
#define URE_FRAMELEN(mtu)
#define URE_PLA_OCP_GPHY_BASE
#define URE_BYTE_EN_SIX_BYTES
#define URE_D3_CLK_GATED_EN
#define URE_RXPKT_IPV4_CS
#define URE_SPDWN_RXDV_MSK
#define URE_USB_UPT_RXDMA_OWN
#define URE_OCP_ALDPS_CONFIG
#define URE_RXPKT_VLAN_MASK
#define URE_LPM_TIMER_500US
#define URE_WDT6_SET_MODE
#define URE_TCR0_AUTO_FIFO
#define URE_USB_AFE_CTRL2
#define URE_TXPKT_LEN_MASK
#define URE_USB_RX_EXTRA_AGG_TMR
#define URE_RXFIFO_THR3_NORMAL
#define URE_TP100_SPDWN_EN
#define URE_PLA_INDICATE_FALG
#define URE_FMC_FCR_MCU_EN
#define URE_8156_RX_BUFSZ
#define URE_RXFIFO_THR3_HIGH
#define URE_PLA_MAC_PWR_CTRL2
#define URE_PLA_MAC_PWR_CTRL4
#define URE_TP1000_SPDWN_EN
#define URE_PLA_PHYSTATUS
#define URE_PLA_TEREDO_TIMER
#define URE_CRWECR_CONFIG
#define URE_SPDWN_LINKCHG_MSK
#define URE_PLA_SUSPEND_FLAG
#define URE_USB_MSC_TIMER
#define URE_USB_LPM_CONFIG
#define URE_CHIP_VER_5C10
#define URE_PHY_STAT_PWRDN
#define URE_TP500_SPDWN_EN
#define URE_SRAM_10M_AMP1
#define URE_U1U2_SPDWN_EN
#define URE_PHY_STAT_MASK
#define URE_LINK_LIST_READY
#define URE_OCP_PHY_STATUS
#define URE_PHY_STAT_LAN_ON
#define URE_PLA_TXFIFO_CTRL
#define URE_PLA_TEREDO_CFG
#define URE_FC_PATCH_TASK
#define URE_PWD_DN_SCALE(x)
#define URE_USB_CSR_DUMMY1
#define URE_PHYSTATUS_2500MBPS
#define URE_TX_AGG_MAX_THRESHOLD
#define URE_SRAM_IMPEDANCE
#define URE_LINK_CHANGE_FLAG
#define URE_CHIP_VER_4C00
#define URE_USB_CSR_DUMMY2
#define URE_OCP_DOWN_SPEED
#define URE_USB_BMU_RESET
#define URE_DYNAMIC_BURST
#define URE_USB_RX_EARLY_SIZE
#define URE_RXFIFO_THR2_HIGH
#define URE_COALESCE_HIGH
#define URE_OCP_POWER_CFG
#define URE_TX_10M_IDLE_EN
#define URE_CTAP_SHORT_EN
#define URE_CHIP_VER_7400
#define URE_CTRL_TIMER_EN
#define URE_OCP_SRAM_ADDR
#define URE_RXPKT_IPV6_CS
#define URE_UPCOMING_RUNTIME_D3
#define URE_PLA_MCU_SPDWN_EN
#define URE_USB_POWER_CUT
#define URE_USB_CONNECT_TIMER
#define URE_RXPKT_RX_VLAN_TAG
#define URE_PLA_BOOT_CTRL
#define URE_BMU_RESET_EP_OUT
#define URE_TX_SIZE_ADJUST1
#define URE_RXFIFO_THR2_NORMAL
#define URE_PLA_RXFIFO_CTRL2
#define URE_AUTOLOAD_DONE
#define URE_CHIP_VER_5C00
#define URE_PHYSTATUS_1000MBPS
#define URE_LINK_OFF_WAKE_EN
#define URE_LPM_TIMER_500MS
#define URE_COALESCE_SLOW
#define URE_TXPKT_IPV6_CS
#define URE_EEE_CLKDIV_EN
#define URE_TXPKT_IPV4_CS
#define URE_CHIP_VER_7020
#define URE_PLA_SFF_STS_7
#define URE_PLA_LED_FEATURE
#define URE_SUSPEND_SPDWN_EN
#define URE_L4_OFFSET_SHIFT
#define URE_CRWECR_NORAML
#define URE_BYTE_EN_DWORD
#define URE_TXPKT_VLAN_MASK
#define URE_FIFO_EMPTY_1FB
#define URE_PLA_MAC_PWR_CTRL3
#define URE_USB_BURST_SIZE
#define URE_CHIP_VER_5C30
#define URE_EN_10M_PLLOFF
#define URE_TEREDO_RS_EVENT_MASK
#define URE_USB_TOLERANCE
#define URE_8152_RX_BUFSZ
#define URE_CHIP_VER_4C10
#define URE_EEE_SPDWN_RATIO
#define URE_PWRSAVE_SPDWN_EN
#define URE_USB2PHY_SUSPEND
#define URE_USB_PM_CTRL_STATUS
#define URE_PLA_REALWOW_TIMER
#define URE_PHY_STAT_EXT_INIT
#define URE_CHIP_VER_6010
#define URE_RXFIFO_THR2_FULL
#define URE_LED_MODE_MASK
#define URE_TXFIFO_THR_NORMAL2
#define URE_MCU_CLK_RATIO
#define URE_RXFIFO_THR1_NORMAL
#define URE_FLOW_CTRL_PATCH_OPT
#define URE_OOB_TEREDO_EN
#define URE_ALDPS_SPDWN_RATIO
#define URE_PLA_RXFIFO_CTRL0
#define URE_TEST_MODE_DISABLE
#define URE_OCP_SRAM_DATA
#define URE_USB_RX_EARLY_AGG
#define URE_SPEED_DOWN_MSK
#define URE_LINK_CHG_EVENT
#define URE_COALESCE_SUPER
#define URE_CHIP_VER_5C20
#define URE_MAC_CLK_SPDWN_EN
#define URE_8153_RX_BUFSZ
#define URE_PLA_WDT6_CTRL
#define URE_USB_U2P3_CTRL
#define URE_RX_AGG_DISABLE
#define URE_CHIP_VER_7030
#define URE_RXPKT_LEN_MASK
#define URE_PFM_PWM_SWITCH
#define URE_PLA_GPHY_INTR_IMR
#define URE_RXFIFO_THR3_FULL
#define URE_CHIP_VER_7410
#define URE_PHYSTATUS_LINK
#define URE_RXDV_SPDWN_EN
#define URE_PLA_EXTRA_STATUS
struct ifmedia sc_ifmedia
struct usb_xfer * sc_rx_xfer[URE_MAX_RX]
struct usb_xfer * sc_tx_xfer[URE_MAX_TX]
enum usb_hc_mode usb_mode
struct usbd_lookup_info info
struct usb_device * device
void(* ue_mii_sts)(struct ifnet *, struct ifmediareq *)
uether_fn_t * ue_attach_post
const struct usb_ether_methods * ue_methods
struct usb_device * ue_udev
uint8_t ue_eaddr[ETHER_ADDR_LEN]
#define UT_WRITE_VENDOR_DEVICE
#define UT_READ_VENDOR_DEVICE
void usbd_copy_in(struct usb_page_cache *cache, usb_frlength_t offset, const void *ptr, usb_frlength_t len)
void usbd_copy_out(struct usb_page_cache *cache, usb_frlength_t offset, void *ptr, usb_frlength_t len)
enum usb_dev_speed usbd_get_speed(struct usb_device *udev)
const char * usbd_errstr(usb_error_t err)
void uether_rxflush(struct usb_ether *ue)
void uether_ifdetach(struct usb_ether *ue)
void * uether_getsc(struct usb_ether *ue)
struct ifnet * uether_getifp(struct usb_ether *ue)
uint8_t uether_pause(struct usb_ether *ue, unsigned int _ticks)
int uether_rxmbuf(struct usb_ether *ue, struct mbuf *m, unsigned int len)
int uether_ifmedia_upd(struct ifnet *ifp)
void uether_init(void *arg)
int uether_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
int uether_ifattach(struct usb_ether *ue)
void uether_start(struct ifnet *ifp)
#define uether_do_request(ue, req, data, timo)
void() uether_fn_t(struct usb_ether *)
int usbd_lookup_id_by_uaa(const struct usb_device_id *id, usb_size_t sizeof_id, struct usb_attach_arg *uaa)
void usbd_transfer_submit(struct usb_xfer *xfer)
void usbd_transfer_unsetup(struct usb_xfer **pxfer, uint16_t n_setup)
void usbd_xfer_set_frame_len(struct usb_xfer *xfer, usb_frcount_t frindex, usb_frlength_t len)
struct usb_page_cache * usbd_xfer_get_frame(struct usb_xfer *xfer, usb_frcount_t frindex)
usb_error_t usbd_transfer_setup(struct usb_device *udev, const uint8_t *ifaces, struct usb_xfer **ppxfer, const struct usb_config *setup_start, uint16_t n_setup, void *priv_sc, struct mtx *xfer_mtx)
void usbd_transfer_start(struct usb_xfer *xfer)
void * usbd_xfer_softc(struct usb_xfer *xfer)
void usbd_xfer_set_stall(struct usb_xfer *xfer)
void usbd_transfer_stop(struct usb_xfer *xfer)
void usbd_xfer_status(struct usb_xfer *xfer, int *actlen, int *sumlen, int *aframes, int *nframes)
usb_frlength_t usbd_xfer_max_len(struct usb_xfer *xfer)
void device_set_usb_desc(device_t dev)
#define USB_ST_TRANSFERRED
void usbd_m_copy_in(struct usb_page_cache *cache, usb_frlength_t dst_offset, struct mbuf *m, usb_size_t src_offset, usb_frlength_t src_len)
void() usb_callback_t(struct usb_xfer *, usb_error_t)
#define STRUCT_USB_HOST_ID
#define USB_GET_DRIVER_INFO(did)
#define USB_GET_STATE(xfer)