FreeBSD kernel usb device Code
xhci.h File Reference
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Data Structures

struct  xhci_dev_ctx_addr
 
struct  xhci_slot_ctx
 
struct  xhci_slot_ctx64
 
struct  xhci_endp_ctx
 
struct  xhci_endp_ctx64
 
struct  xhci_input_ctx
 
struct  xhci_input_ctx64
 
struct  xhci_input_dev_ctx
 
struct  xhci_input_dev_ctx64
 
struct  xhci_dev_ctx
 
struct  xhci_dev_ctx64
 
struct  xhci_stream_ctx
 
struct  xhci_trb
 
struct  xhci_dev_endpoint_trbs
 
struct  xhci_td
 
struct  xhci_command
 
struct  xhci_event_ring_seg
 
struct  xhci_hw_root
 
struct  xhci_endpoint_ext
 
struct  xhci_hw_dev
 
struct  xhci_hw_softc
 
struct  xhci_config_desc
 
struct  xhci_bos_desc
 
union  xhci_hub_desc
 
struct  xhci_softc
 

Macros

#define XHCI_MAX_DEVICES   MIN(USB_MAX_DEVICES, 128)
 
#define XHCI_MAX_ENDPOINTS   32 /* hardcoded - do not change */
 
#define XHCI_MAX_SCRATCHPADS   256 /* theoretical max is 1023 */
 
#define XHCI_MAX_EVENTS   232
 
#define XHCI_MAX_COMMANDS   (16 * 1)
 
#define XHCI_MAX_RSEG   1
 
#define XHCI_MAX_TRANSFERS   4
 
#define XHCI_DEV_CTX_ADDR_ALIGN   64 /* bytes */
 
#define XHCI_DEV_CTX_ALIGN   64 /* bytes */
 
#define XHCI_INPUT_CTX_ALIGN   64 /* bytes */
 
#define XHCI_SLOT_CTX_ALIGN   32 /* bytes */
 
#define XHCI_ENDP_CTX_ALIGN   32 /* bytes */
 
#define XHCI_STREAM_CTX_ALIGN   16 /* bytes */
 
#define XHCI_TRANS_RING_SEG_ALIGN   16 /* bytes */
 
#define XHCI_CMD_RING_SEG_ALIGN   64 /* bytes */
 
#define XHCI_EVENT_RING_SEG_ALIGN   64 /* bytes */
 
#define XHCI_SCRATCH_BUF_ARRAY_ALIGN   64 /* bytes */
 
#define XHCI_SCRATCH_BUFFER_ALIGN   USB_PAGE_SIZE
 
#define XHCI_TRB_ALIGN   16 /* bytes */
 
#define XHCI_TD_ALIGN   64 /* bytes */
 
#define XHCI_PAGE_SIZE   4096 /* bytes */
 
#define XHCI_EPNO2EPID(x)    ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR)))
 
#define XHCI_SCTX_0_ROUTE_SET(x)   ((x) & 0xFFFFF)
 
#define XHCI_SCTX_0_ROUTE_GET(x)   ((x) & 0xFFFFF)
 
#define XHCI_SCTX_0_SPEED_SET(x)   (((x) & 0xF) << 20)
 
#define XHCI_SCTX_0_SPEED_GET(x)   (((x) >> 20) & 0xF)
 
#define XHCI_SCTX_0_MTT_SET(x)   (((x) & 0x1) << 25)
 
#define XHCI_SCTX_0_MTT_GET(x)   (((x) >> 25) & 0x1)
 
#define XHCI_SCTX_0_HUB_SET(x)   (((x) & 0x1) << 26)
 
#define XHCI_SCTX_0_HUB_GET(x)   (((x) >> 26) & 0x1)
 
#define XHCI_SCTX_0_CTX_NUM_SET(x)   (((x) & 0x1F) << 27)
 
#define XHCI_SCTX_0_CTX_NUM_GET(x)   (((x) >> 27) & 0x1F)
 
#define XHCI_SCTX_1_MAX_EL_SET(x)   ((x) & 0xFFFF)
 
#define XHCI_SCTX_1_MAX_EL_GET(x)   ((x) & 0xFFFF)
 
#define XHCI_SCTX_1_RH_PORT_SET(x)   (((x) & 0xFF) << 16)
 
#define XHCI_SCTX_1_RH_PORT_GET(x)   (((x) >> 16) & 0xFF)
 
#define XHCI_SCTX_1_NUM_PORTS_SET(x)   (((x) & 0xFF) << 24)
 
#define XHCI_SCTX_1_NUM_PORTS_GET(x)   (((x) >> 24) & 0xFF)
 
#define XHCI_SCTX_2_TT_HUB_SID_SET(x)   ((x) & 0xFF)
 
#define XHCI_SCTX_2_TT_HUB_SID_GET(x)   ((x) & 0xFF)
 
#define XHCI_SCTX_2_TT_PORT_NUM_SET(x)   (((x) & 0xFF) << 8)
 
#define XHCI_SCTX_2_TT_PORT_NUM_GET(x)   (((x) >> 8) & 0xFF)
 
#define XHCI_SCTX_2_TT_THINK_TIME_SET(x)   (((x) & 0x3) << 16)
 
#define XHCI_SCTX_2_TT_THINK_TIME_GET(x)   (((x) >> 16) & 0x3)
 
#define XHCI_SCTX_2_IRQ_TARGET_SET(x)   (((x) & 0x3FF) << 22)
 
#define XHCI_SCTX_2_IRQ_TARGET_GET(x)   (((x) >> 22) & 0x3FF)
 
#define XHCI_SCTX_3_DEV_ADDR_SET(x)   ((x) & 0xFF)
 
#define XHCI_SCTX_3_DEV_ADDR_GET(x)   ((x) & 0xFF)
 
#define XHCI_SCTX_3_SLOT_STATE_SET(x)   (((x) & 0x1F) << 27)
 
#define XHCI_SCTX_3_SLOT_STATE_GET(x)   (((x) >> 27) & 0x1F)
 
#define XHCI_EPCTX_0_EPSTATE_SET(x)   ((x) & 0x7)
 
#define XHCI_EPCTX_0_EPSTATE_GET(x)   ((x) & 0x7)
 
#define XHCI_EPCTX_0_EPSTATE_DISABLED   0
 
#define XHCI_EPCTX_0_EPSTATE_RUNNING   1
 
#define XHCI_EPCTX_0_EPSTATE_HALTED   2
 
#define XHCI_EPCTX_0_EPSTATE_STOPPED   3
 
#define XHCI_EPCTX_0_EPSTATE_ERROR   4
 
#define XHCI_EPCTX_0_EPSTATE_RESERVED_5   5
 
#define XHCI_EPCTX_0_EPSTATE_RESERVED_6   6
 
#define XHCI_EPCTX_0_EPSTATE_RESERVED_7   7
 
#define XHCI_EPCTX_0_MULT_SET(x)   (((x) & 0x3) << 8)
 
#define XHCI_EPCTX_0_MULT_GET(x)   (((x) >> 8) & 0x3)
 
#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x)   (((x) & 0x1F) << 10)
 
#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x)   (((x) >> 10) & 0x1F)
 
#define XHCI_EPCTX_0_LSA_SET(x)   (((x) & 0x1) << 15)
 
#define XHCI_EPCTX_0_LSA_GET(x)   (((x) >> 15) & 0x1)
 
#define XHCI_EPCTX_0_IVAL_SET(x)   (((x) & 0xFF) << 16)
 
#define XHCI_EPCTX_0_IVAL_GET(x)   (((x) >> 16) & 0xFF)
 
#define XHCI_EPCTX_1_CERR_SET(x)   (((x) & 0x3) << 1)
 
#define XHCI_EPCTX_1_CERR_GET(x)   (((x) >> 1) & 0x3)
 
#define XHCI_EPCTX_1_EPTYPE_SET(x)   (((x) & 0x7) << 3)
 
#define XHCI_EPCTX_1_EPTYPE_GET(x)   (((x) >> 3) & 0x7)
 
#define XHCI_EPCTX_1_HID_SET(x)   (((x) & 0x1) << 7)
 
#define XHCI_EPCTX_1_HID_GET(x)   (((x) >> 7) & 0x1)
 
#define XHCI_EPCTX_1_MAXB_SET(x)   (((x) & 0xFF) << 8)
 
#define XHCI_EPCTX_1_MAXB_GET(x)   (((x) >> 8) & 0xFF)
 
#define XHCI_EPCTX_1_MAXP_SIZE_SET(x)   (((x) & 0xFFFF) << 16)
 
#define XHCI_EPCTX_1_MAXP_SIZE_GET(x)   (((x) >> 16) & 0xFFFF)
 
#define XHCI_EPCTX_2_DCS_SET(x)   ((x) & 0x1)
 
#define XHCI_EPCTX_2_DCS_GET(x)   ((x) & 0x1)
 
#define XHCI_EPCTX_2_TR_DQ_PTR_MASK   0xFFFFFFFFFFFFFFF0U
 
#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x)   ((x) & 0xFFFF)
 
#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x)   ((x) & 0xFFFF)
 
#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x)   (((x) & 0xFFFF) << 16)
 
#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x)   (((x) >> 16) & 0xFFFF)
 
#define XHCI_INCTX_NON_CTRL_MASK   0xFFFFFFFCU
 
#define XHCI_INCTX_0_DROP_MASK(n)   (1U << (n))
 
#define XHCI_INCTX_1_ADD_MASK(n)   (1U << (n))
 
#define XHCI_SCTX_0_DCS_GET(x)   ((x) & 0x1)
 
#define XHCI_SCTX_0_DCS_SET(x)   ((x) & 0x1)
 
#define XHCI_SCTX_0_SCT_SET(x)   (((x) & 0x7) << 1)
 
#define XHCI_SCTX_0_SCT_GET(x)   (((x) >> 1) & 0x7)
 
#define XHCI_SCTX_0_SCT_SEC_TR_RING   0x0
 
#define XHCI_SCTX_0_SCT_PRIM_TR_RING   0x1
 
#define XHCI_SCTX_0_SCT_PRIM_SSA_8   0x2
 
#define XHCI_SCTX_0_SCT_PRIM_SSA_16   0x3
 
#define XHCI_SCTX_0_SCT_PRIM_SSA_32   0x4
 
#define XHCI_SCTX_0_SCT_PRIM_SSA_64   0x5
 
#define XHCI_SCTX_0_SCT_PRIM_SSA_128   0x6
 
#define XHCI_SCTX_0_SCT_PRIM_SSA_256   0x7
 
#define XHCI_SCTX_0_TR_DQ_PTR_MASK   0xFFFFFFFFFFFFFFF0U
 
#define XHCI_TRB_0_DIR_IN_MASK   (0x80ULL << 0)
 
#define XHCI_TRB_0_WLENGTH_MASK   (0xFFFFULL << 48)
 
#define XHCI_TRB_2_ERROR_GET(x)   (((x) >> 24) & 0xFF)
 
#define XHCI_TRB_2_ERROR_SET(x)   (((x) & 0xFF) << 24)
 
#define XHCI_TRB_2_TDSZ_GET(x)   (((x) >> 17) & 0x1F)
 
#define XHCI_TRB_2_TDSZ_SET(x)   (((x) & 0x1F) << 17)
 
#define XHCI_TRB_2_REM_GET(x)   ((x) & 0xFFFFFF)
 
#define XHCI_TRB_2_REM_SET(x)   ((x) & 0xFFFFFF)
 
#define XHCI_TRB_2_BYTES_GET(x)   ((x) & 0x1FFFF)
 
#define XHCI_TRB_2_BYTES_SET(x)   ((x) & 0x1FFFF)
 
#define XHCI_TRB_2_IRQ_GET(x)   (((x) >> 22) & 0x3FF)
 
#define XHCI_TRB_2_IRQ_SET(x)   (((x) & 0x3FF) << 22)
 
#define XHCI_TRB_2_STREAM_GET(x)   (((x) >> 16) & 0xFFFF)
 
#define XHCI_TRB_2_STREAM_SET(x)   (((x) & 0xFFFF) << 16)
 
#define XHCI_TRB_3_TYPE_GET(x)   (((x) >> 10) & 0x3F)
 
#define XHCI_TRB_3_TYPE_SET(x)   (((x) & 0x3F) << 10)
 
#define XHCI_TRB_3_CYCLE_BIT   (1U << 0)
 
#define XHCI_TRB_3_TC_BIT   (1U << 1) /* command ring only */
 
#define XHCI_TRB_3_ENT_BIT   (1U << 1) /* transfer ring only */
 
#define XHCI_TRB_3_ISP_BIT   (1U << 2)
 
#define XHCI_TRB_3_NSNOOP_BIT   (1U << 3)
 
#define XHCI_TRB_3_CHAIN_BIT   (1U << 4)
 
#define XHCI_TRB_3_IOC_BIT   (1U << 5)
 
#define XHCI_TRB_3_IDT_BIT   (1U << 6)
 
#define XHCI_TRB_3_TBC_GET(x)   (((x) >> 7) & 3)
 
#define XHCI_TRB_3_TBC_SET(x)   (((x) & 3) << 7)
 
#define XHCI_TRB_3_BEI_BIT   (1U << 9)
 
#define XHCI_TRB_3_DCEP_BIT   (1U << 9)
 
#define XHCI_TRB_3_PRSV_BIT   (1U << 9)
 
#define XHCI_TRB_3_BSR_BIT   (1U << 9)
 
#define XHCI_TRB_3_TRT_MASK   (3U << 16)
 
#define XHCI_TRB_3_TRT_NONE   (0U << 16)
 
#define XHCI_TRB_3_TRT_OUT   (2U << 16)
 
#define XHCI_TRB_3_TRT_IN   (3U << 16)
 
#define XHCI_TRB_3_DIR_IN   (1U << 16)
 
#define XHCI_TRB_3_TLBPC_GET(x)   (((x) >> 16) & 0xF)
 
#define XHCI_TRB_3_TLBPC_SET(x)   (((x) & 0xF) << 16)
 
#define XHCI_TRB_3_EP_GET(x)   (((x) >> 16) & 0x1F)
 
#define XHCI_TRB_3_EP_SET(x)   (((x) & 0x1F) << 16)
 
#define XHCI_TRB_3_FRID_GET(x)   (((x) >> 20) & 0x7FF)
 
#define XHCI_TRB_3_FRID_SET(x)   (((x) & 0x7FF) << 20)
 
#define XHCI_TRB_3_ISO_SIA_BIT   (1U << 31)
 
#define XHCI_TRB_3_SUSP_EP_BIT   (1U << 23)
 
#define XHCI_TRB_3_SLOT_GET(x)   (((x) >> 24) & 0xFF)
 
#define XHCI_TRB_3_SLOT_SET(x)   (((x) & 0xFF) << 24)
 
#define XHCI_TRB_TYPE_RESERVED   0x00
 
#define XHCI_TRB_TYPE_NORMAL   0x01
 
#define XHCI_TRB_TYPE_SETUP_STAGE   0x02
 
#define XHCI_TRB_TYPE_DATA_STAGE   0x03
 
#define XHCI_TRB_TYPE_STATUS_STAGE   0x04
 
#define XHCI_TRB_TYPE_ISOCH   0x05
 
#define XHCI_TRB_TYPE_LINK   0x06
 
#define XHCI_TRB_TYPE_EVENT_DATA   0x07
 
#define XHCI_TRB_TYPE_NOOP   0x08
 
#define XHCI_TRB_TYPE_ENABLE_SLOT   0x09
 
#define XHCI_TRB_TYPE_DISABLE_SLOT   0x0A
 
#define XHCI_TRB_TYPE_ADDRESS_DEVICE   0x0B
 
#define XHCI_TRB_TYPE_CONFIGURE_EP   0x0C
 
#define XHCI_TRB_TYPE_EVALUATE_CTX   0x0D
 
#define XHCI_TRB_TYPE_RESET_EP   0x0E
 
#define XHCI_TRB_TYPE_STOP_EP   0x0F
 
#define XHCI_TRB_TYPE_SET_TR_DEQUEUE   0x10
 
#define XHCI_TRB_TYPE_RESET_DEVICE   0x11
 
#define XHCI_TRB_TYPE_FORCE_EVENT   0x12
 
#define XHCI_TRB_TYPE_NEGOTIATE_BW   0x13
 
#define XHCI_TRB_TYPE_SET_LATENCY_TOL   0x14
 
#define XHCI_TRB_TYPE_GET_PORT_BW   0x15
 
#define XHCI_TRB_TYPE_FORCE_HEADER   0x16
 
#define XHCI_TRB_TYPE_NOOP_CMD   0x17
 
#define XHCI_TRB_EVENT_TRANSFER   0x20
 
#define XHCI_TRB_EVENT_CMD_COMPLETE   0x21
 
#define XHCI_TRB_EVENT_PORT_STS_CHANGE   0x22
 
#define XHCI_TRB_EVENT_BW_REQUEST   0x23
 
#define XHCI_TRB_EVENT_DOORBELL   0x24
 
#define XHCI_TRB_EVENT_HOST_CTRL   0x25
 
#define XHCI_TRB_EVENT_DEVICE_NOTIFY   0x26
 
#define XHCI_TRB_EVENT_MFINDEX_WRAP   0x27
 
#define XHCI_TRB_ERROR_INVALID   0x00
 
#define XHCI_TRB_ERROR_SUCCESS   0x01
 
#define XHCI_TRB_ERROR_DATA_BUF   0x02
 
#define XHCI_TRB_ERROR_BABBLE   0x03
 
#define XHCI_TRB_ERROR_XACT   0x04
 
#define XHCI_TRB_ERROR_TRB   0x05
 
#define XHCI_TRB_ERROR_STALL   0x06
 
#define XHCI_TRB_ERROR_RESOURCE   0x07
 
#define XHCI_TRB_ERROR_BANDWIDTH   0x08
 
#define XHCI_TRB_ERROR_NO_SLOTS   0x09
 
#define XHCI_TRB_ERROR_STREAM_TYPE   0x0A
 
#define XHCI_TRB_ERROR_SLOT_NOT_ON   0x0B
 
#define XHCI_TRB_ERROR_ENDP_NOT_ON   0x0C
 
#define XHCI_TRB_ERROR_SHORT_PKT   0x0D
 
#define XHCI_TRB_ERROR_RING_UNDERRUN   0x0E
 
#define XHCI_TRB_ERROR_RING_OVERRUN   0x0F
 
#define XHCI_TRB_ERROR_VF_RING_FULL   0x10
 
#define XHCI_TRB_ERROR_PARAMETER   0x11
 
#define XHCI_TRB_ERROR_BW_OVERRUN   0x12
 
#define XHCI_TRB_ERROR_CONTEXT_STATE   0x13
 
#define XHCI_TRB_ERROR_NO_PING_RESP   0x14
 
#define XHCI_TRB_ERROR_EV_RING_FULL   0x15
 
#define XHCI_TRB_ERROR_INCOMPAT_DEV   0x16
 
#define XHCI_TRB_ERROR_MISSED_SERVICE   0x17
 
#define XHCI_TRB_ERROR_CMD_RING_STOP   0x18
 
#define XHCI_TRB_ERROR_CMD_ABORTED   0x19
 
#define XHCI_TRB_ERROR_STOPPED   0x1A
 
#define XHCI_TRB_ERROR_LENGTH   0x1B
 
#define XHCI_TRB_ERROR_BAD_MELAT   0x1D
 
#define XHCI_TRB_ERROR_ISOC_OVERRUN   0x1F
 
#define XHCI_TRB_ERROR_EVENT_LOST   0x20
 
#define XHCI_TRB_ERROR_UNDEFINED   0x21
 
#define XHCI_TRB_ERROR_INVALID_SID   0x22
 
#define XHCI_TRB_ERROR_SEC_BW   0x23
 
#define XHCI_TRB_ERROR_SPLIT_XACT   0x24
 
#define XHCI_TD_PAYLOAD_MAX   65536 /* bytes */
 
#define XHCI_TD_PAGE_SIZE    ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX)
 
#define XHCI_TD_PAGE_NBUF    (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1)
 
#define XHCI_CMD_LOCK(sc)   sx_xlock(&(sc)->sc_cmd_sx)
 
#define XHCI_CMD_UNLOCK(sc)   sx_xunlock(&(sc)->sc_cmd_sx)
 
#define XHCI_CMD_ASSERT_LOCKED(sc)   sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED)
 

Typedefs

typedef int() xhci_port_route_t(device_t, uint32_t, uint32_t)
 

Enumerations

enum  {
  XHCI_ST_DISABLED , XHCI_ST_ENABLED , XHCI_ST_DEFAULT , XHCI_ST_ADDRESSED ,
  XHCI_ST_CONFIGURED , XHCI_ST_MAX
}
 

Functions

struct xhci_dev_ctx __aligned (XHCI_DEV_CTX_ALIGN)
 
struct xhci_trb __aligned (4)
 
struct xhci_td __aligned (XHCI_TRB_ALIGN)
 
 CTASSERT (sizeof(struct xhci_hw_root)==XHCI_PAGE_SIZE)
 
uint8_t xhci_use_polling (void)
 
usb_error_t xhci_halt_controller (struct xhci_softc *)
 
usb_error_t xhci_reset_controller (struct xhci_softc *)
 
usb_error_t xhci_init (struct xhci_softc *, device_t, uint8_t)
 
usb_error_t xhci_start_controller (struct xhci_softc *)
 
void xhci_interrupt (struct xhci_softc *)
 
void xhci_uninit (struct xhci_softc *)
 
int xhci_pci_attach (device_t)
 
 DECLARE_CLASS (xhci_pci_driver)
 

Variables

volatile uint64_t dummy
 
struct xhci_slot_ctx ctx_slot
 
struct xhci_endp_ctx ctx_ep [XHCI_MAX_ENDPOINTS - 1]
 
struct xhci_stream_ctx __aligned
 
volatile uint64_t qwTrb0
 
volatile uint32_t dwTrb2
 
volatile uint32_t dwTrb3
 
struct xhci_trb td_trb [XHCI_TD_PAGE_NBUF+1]
 
uint64_t td_self
 
struct xhci_tdnext
 
struct xhci_tdalt_next
 
struct xhci_tdobj_next
 
struct usb_page_cachepage_cache
 
uint32_t len
 
uint32_t remainder
 
uint8_t ntrb
 
uint8_t status
 
struct xhci_config_desc __packed
 

Macro Definition Documentation

◆ XHCI_CMD_ASSERT_LOCKED

#define XHCI_CMD_ASSERT_LOCKED (   sc)    sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED)

Definition at line 570 of file xhci.h.

◆ XHCI_CMD_LOCK

#define XHCI_CMD_LOCK (   sc)    sx_xlock(&(sc)->sc_cmd_sx)

Definition at line 568 of file xhci.h.

◆ XHCI_CMD_RING_SEG_ALIGN

#define XHCI_CMD_RING_SEG_ALIGN   64 /* bytes */

Definition at line 56 of file xhci.h.

◆ XHCI_CMD_UNLOCK

#define XHCI_CMD_UNLOCK (   sc)    sx_xunlock(&(sc)->sc_cmd_sx)

Definition at line 569 of file xhci.h.

◆ XHCI_DEV_CTX_ADDR_ALIGN

#define XHCI_DEV_CTX_ADDR_ALIGN   64 /* bytes */

Definition at line 49 of file xhci.h.

◆ XHCI_DEV_CTX_ALIGN

#define XHCI_DEV_CTX_ALIGN   64 /* bytes */

Definition at line 50 of file xhci.h.

◆ XHCI_ENDP_CTX_ALIGN

#define XHCI_ENDP_CTX_ALIGN   32 /* bytes */

Definition at line 53 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_DISABLED

#define XHCI_EPCTX_0_EPSTATE_DISABLED   0

Definition at line 123 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_ERROR

#define XHCI_EPCTX_0_EPSTATE_ERROR   4

Definition at line 127 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_GET

#define XHCI_EPCTX_0_EPSTATE_GET (   x)    ((x) & 0x7)

Definition at line 122 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_HALTED

#define XHCI_EPCTX_0_EPSTATE_HALTED   2

Definition at line 125 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_RESERVED_5

#define XHCI_EPCTX_0_EPSTATE_RESERVED_5   5

Definition at line 128 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_RESERVED_6

#define XHCI_EPCTX_0_EPSTATE_RESERVED_6   6

Definition at line 129 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_RESERVED_7

#define XHCI_EPCTX_0_EPSTATE_RESERVED_7   7

Definition at line 130 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_RUNNING

#define XHCI_EPCTX_0_EPSTATE_RUNNING   1

Definition at line 124 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_SET

#define XHCI_EPCTX_0_EPSTATE_SET (   x)    ((x) & 0x7)

Definition at line 121 of file xhci.h.

◆ XHCI_EPCTX_0_EPSTATE_STOPPED

#define XHCI_EPCTX_0_EPSTATE_STOPPED   3

Definition at line 126 of file xhci.h.

◆ XHCI_EPCTX_0_IVAL_GET

#define XHCI_EPCTX_0_IVAL_GET (   x)    (((x) >> 16) & 0xFF)

Definition at line 138 of file xhci.h.

◆ XHCI_EPCTX_0_IVAL_SET

#define XHCI_EPCTX_0_IVAL_SET (   x)    (((x) & 0xFF) << 16)

Definition at line 137 of file xhci.h.

◆ XHCI_EPCTX_0_LSA_GET

#define XHCI_EPCTX_0_LSA_GET (   x)    (((x) >> 15) & 0x1)

Definition at line 136 of file xhci.h.

◆ XHCI_EPCTX_0_LSA_SET

#define XHCI_EPCTX_0_LSA_SET (   x)    (((x) & 0x1) << 15)

Definition at line 135 of file xhci.h.

◆ XHCI_EPCTX_0_MAXP_STREAMS_GET

#define XHCI_EPCTX_0_MAXP_STREAMS_GET (   x)    (((x) >> 10) & 0x1F)

Definition at line 134 of file xhci.h.

◆ XHCI_EPCTX_0_MAXP_STREAMS_SET

#define XHCI_EPCTX_0_MAXP_STREAMS_SET (   x)    (((x) & 0x1F) << 10)

Definition at line 133 of file xhci.h.

◆ XHCI_EPCTX_0_MULT_GET

#define XHCI_EPCTX_0_MULT_GET (   x)    (((x) >> 8) & 0x3)

Definition at line 132 of file xhci.h.

◆ XHCI_EPCTX_0_MULT_SET

#define XHCI_EPCTX_0_MULT_SET (   x)    (((x) & 0x3) << 8)

Definition at line 131 of file xhci.h.

◆ XHCI_EPCTX_1_CERR_GET

#define XHCI_EPCTX_1_CERR_GET (   x)    (((x) >> 1) & 0x3)

Definition at line 141 of file xhci.h.

◆ XHCI_EPCTX_1_CERR_SET

#define XHCI_EPCTX_1_CERR_SET (   x)    (((x) & 0x3) << 1)

Definition at line 140 of file xhci.h.

◆ XHCI_EPCTX_1_EPTYPE_GET

#define XHCI_EPCTX_1_EPTYPE_GET (   x)    (((x) >> 3) & 0x7)

Definition at line 143 of file xhci.h.

◆ XHCI_EPCTX_1_EPTYPE_SET

#define XHCI_EPCTX_1_EPTYPE_SET (   x)    (((x) & 0x7) << 3)

Definition at line 142 of file xhci.h.

◆ XHCI_EPCTX_1_HID_GET

#define XHCI_EPCTX_1_HID_GET (   x)    (((x) >> 7) & 0x1)

Definition at line 145 of file xhci.h.

◆ XHCI_EPCTX_1_HID_SET

#define XHCI_EPCTX_1_HID_SET (   x)    (((x) & 0x1) << 7)

Definition at line 144 of file xhci.h.

◆ XHCI_EPCTX_1_MAXB_GET

#define XHCI_EPCTX_1_MAXB_GET (   x)    (((x) >> 8) & 0xFF)

Definition at line 147 of file xhci.h.

◆ XHCI_EPCTX_1_MAXB_SET

#define XHCI_EPCTX_1_MAXB_SET (   x)    (((x) & 0xFF) << 8)

Definition at line 146 of file xhci.h.

◆ XHCI_EPCTX_1_MAXP_SIZE_GET

#define XHCI_EPCTX_1_MAXP_SIZE_GET (   x)    (((x) >> 16) & 0xFFFF)

Definition at line 149 of file xhci.h.

◆ XHCI_EPCTX_1_MAXP_SIZE_SET

#define XHCI_EPCTX_1_MAXP_SIZE_SET (   x)    (((x) & 0xFFFF) << 16)

Definition at line 148 of file xhci.h.

◆ XHCI_EPCTX_2_DCS_GET

#define XHCI_EPCTX_2_DCS_GET (   x)    ((x) & 0x1)

Definition at line 152 of file xhci.h.

◆ XHCI_EPCTX_2_DCS_SET

#define XHCI_EPCTX_2_DCS_SET (   x)    ((x) & 0x1)

Definition at line 151 of file xhci.h.

◆ XHCI_EPCTX_2_TR_DQ_PTR_MASK

#define XHCI_EPCTX_2_TR_DQ_PTR_MASK   0xFFFFFFFFFFFFFFF0U

Definition at line 153 of file xhci.h.

◆ XHCI_EPCTX_4_AVG_TRB_LEN_GET

#define XHCI_EPCTX_4_AVG_TRB_LEN_GET (   x)    ((x) & 0xFFFF)

Definition at line 156 of file xhci.h.

◆ XHCI_EPCTX_4_AVG_TRB_LEN_SET

#define XHCI_EPCTX_4_AVG_TRB_LEN_SET (   x)    ((x) & 0xFFFF)

Definition at line 155 of file xhci.h.

◆ XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET

#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET (   x)    (((x) >> 16) & 0xFFFF)

Definition at line 158 of file xhci.h.

◆ XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET

#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET (   x)    (((x) & 0xFFFF) << 16)

Definition at line 157 of file xhci.h.

◆ XHCI_EPNO2EPID

#define XHCI_EPNO2EPID (   x)     ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR)))

Definition at line 72 of file xhci.h.

◆ XHCI_EVENT_RING_SEG_ALIGN

#define XHCI_EVENT_RING_SEG_ALIGN   64 /* bytes */

Definition at line 57 of file xhci.h.

◆ XHCI_INCTX_0_DROP_MASK

#define XHCI_INCTX_0_DROP_MASK (   n)    (1U << (n))

Definition at line 172 of file xhci.h.

◆ XHCI_INCTX_1_ADD_MASK

#define XHCI_INCTX_1_ADD_MASK (   n)    (1U << (n))

Definition at line 174 of file xhci.h.

◆ XHCI_INCTX_NON_CTRL_MASK

#define XHCI_INCTX_NON_CTRL_MASK   0xFFFFFFFCU

Definition at line 170 of file xhci.h.

◆ XHCI_INPUT_CTX_ALIGN

#define XHCI_INPUT_CTX_ALIGN   64 /* bytes */

Definition at line 51 of file xhci.h.

◆ XHCI_MAX_COMMANDS

#define XHCI_MAX_COMMANDS   (16 * 1)

Definition at line 37 of file xhci.h.

◆ XHCI_MAX_DEVICES

#define XHCI_MAX_DEVICES   MIN(USB_MAX_DEVICES, 128)

Definition at line 33 of file xhci.h.

◆ XHCI_MAX_ENDPOINTS

#define XHCI_MAX_ENDPOINTS   32 /* hardcoded - do not change */

Definition at line 34 of file xhci.h.

◆ XHCI_MAX_EVENTS

#define XHCI_MAX_EVENTS   232

Definition at line 36 of file xhci.h.

◆ XHCI_MAX_RSEG

#define XHCI_MAX_RSEG   1

Definition at line 38 of file xhci.h.

◆ XHCI_MAX_SCRATCHPADS

#define XHCI_MAX_SCRATCHPADS   256 /* theoretical max is 1023 */

Definition at line 35 of file xhci.h.

◆ XHCI_MAX_TRANSFERS

#define XHCI_MAX_TRANSFERS   4

Definition at line 39 of file xhci.h.

◆ XHCI_PAGE_SIZE

#define XHCI_PAGE_SIZE   4096 /* bytes */

Definition at line 62 of file xhci.h.

◆ XHCI_SCRATCH_BUF_ARRAY_ALIGN

#define XHCI_SCRATCH_BUF_ARRAY_ALIGN   64 /* bytes */

Definition at line 58 of file xhci.h.

◆ XHCI_SCRATCH_BUFFER_ALIGN

#define XHCI_SCRATCH_BUFFER_ALIGN   USB_PAGE_SIZE

Definition at line 59 of file xhci.h.

◆ XHCI_SCTX_0_CTX_NUM_GET

#define XHCI_SCTX_0_CTX_NUM_GET (   x)    (((x) >> 27) & 0x1F)

Definition at line 86 of file xhci.h.

◆ XHCI_SCTX_0_CTX_NUM_SET

#define XHCI_SCTX_0_CTX_NUM_SET (   x)    (((x) & 0x1F) << 27)

Definition at line 85 of file xhci.h.

◆ XHCI_SCTX_0_DCS_GET

#define XHCI_SCTX_0_DCS_GET (   x)    ((x) & 0x1)

Definition at line 212 of file xhci.h.

◆ XHCI_SCTX_0_DCS_SET

#define XHCI_SCTX_0_DCS_SET (   x)    ((x) & 0x1)

Definition at line 213 of file xhci.h.

◆ XHCI_SCTX_0_HUB_GET

#define XHCI_SCTX_0_HUB_GET (   x)    (((x) >> 26) & 0x1)

Definition at line 84 of file xhci.h.

◆ XHCI_SCTX_0_HUB_SET

#define XHCI_SCTX_0_HUB_SET (   x)    (((x) & 0x1) << 26)

Definition at line 83 of file xhci.h.

◆ XHCI_SCTX_0_MTT_GET

#define XHCI_SCTX_0_MTT_GET (   x)    (((x) >> 25) & 0x1)

Definition at line 82 of file xhci.h.

◆ XHCI_SCTX_0_MTT_SET

#define XHCI_SCTX_0_MTT_SET (   x)    (((x) & 0x1) << 25)

Definition at line 81 of file xhci.h.

◆ XHCI_SCTX_0_ROUTE_GET

#define XHCI_SCTX_0_ROUTE_GET (   x)    ((x) & 0xFFFFF)

Definition at line 78 of file xhci.h.

◆ XHCI_SCTX_0_ROUTE_SET

#define XHCI_SCTX_0_ROUTE_SET (   x)    ((x) & 0xFFFFF)

Definition at line 77 of file xhci.h.

◆ XHCI_SCTX_0_SCT_GET

#define XHCI_SCTX_0_SCT_GET (   x)    (((x) >> 1) & 0x7)

Definition at line 215 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_SSA_128

#define XHCI_SCTX_0_SCT_PRIM_SSA_128   0x6

Definition at line 222 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_SSA_16

#define XHCI_SCTX_0_SCT_PRIM_SSA_16   0x3

Definition at line 219 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_SSA_256

#define XHCI_SCTX_0_SCT_PRIM_SSA_256   0x7

Definition at line 223 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_SSA_32

#define XHCI_SCTX_0_SCT_PRIM_SSA_32   0x4

Definition at line 220 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_SSA_64

#define XHCI_SCTX_0_SCT_PRIM_SSA_64   0x5

Definition at line 221 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_SSA_8

#define XHCI_SCTX_0_SCT_PRIM_SSA_8   0x2

Definition at line 218 of file xhci.h.

◆ XHCI_SCTX_0_SCT_PRIM_TR_RING

#define XHCI_SCTX_0_SCT_PRIM_TR_RING   0x1

Definition at line 217 of file xhci.h.

◆ XHCI_SCTX_0_SCT_SEC_TR_RING

#define XHCI_SCTX_0_SCT_SEC_TR_RING   0x0

Definition at line 216 of file xhci.h.

◆ XHCI_SCTX_0_SCT_SET

#define XHCI_SCTX_0_SCT_SET (   x)    (((x) & 0x7) << 1)

Definition at line 214 of file xhci.h.

◆ XHCI_SCTX_0_SPEED_GET

#define XHCI_SCTX_0_SPEED_GET (   x)    (((x) >> 20) & 0xF)

Definition at line 80 of file xhci.h.

◆ XHCI_SCTX_0_SPEED_SET

#define XHCI_SCTX_0_SPEED_SET (   x)    (((x) & 0xF) << 20)

Definition at line 79 of file xhci.h.

◆ XHCI_SCTX_0_TR_DQ_PTR_MASK

#define XHCI_SCTX_0_TR_DQ_PTR_MASK   0xFFFFFFFFFFFFFFF0U

Definition at line 224 of file xhci.h.

◆ XHCI_SCTX_1_MAX_EL_GET

#define XHCI_SCTX_1_MAX_EL_GET (   x)    ((x) & 0xFFFF)

Definition at line 89 of file xhci.h.

◆ XHCI_SCTX_1_MAX_EL_SET

#define XHCI_SCTX_1_MAX_EL_SET (   x)    ((x) & 0xFFFF)

Definition at line 88 of file xhci.h.

◆ XHCI_SCTX_1_NUM_PORTS_GET

#define XHCI_SCTX_1_NUM_PORTS_GET (   x)    (((x) >> 24) & 0xFF)

Definition at line 93 of file xhci.h.

◆ XHCI_SCTX_1_NUM_PORTS_SET

#define XHCI_SCTX_1_NUM_PORTS_SET (   x)    (((x) & 0xFF) << 24)

Definition at line 92 of file xhci.h.

◆ XHCI_SCTX_1_RH_PORT_GET

#define XHCI_SCTX_1_RH_PORT_GET (   x)    (((x) >> 16) & 0xFF)

Definition at line 91 of file xhci.h.

◆ XHCI_SCTX_1_RH_PORT_SET

#define XHCI_SCTX_1_RH_PORT_SET (   x)    (((x) & 0xFF) << 16)

Definition at line 90 of file xhci.h.

◆ XHCI_SCTX_2_IRQ_TARGET_GET

#define XHCI_SCTX_2_IRQ_TARGET_GET (   x)    (((x) >> 22) & 0x3FF)

Definition at line 102 of file xhci.h.

◆ XHCI_SCTX_2_IRQ_TARGET_SET

#define XHCI_SCTX_2_IRQ_TARGET_SET (   x)    (((x) & 0x3FF) << 22)

Definition at line 101 of file xhci.h.

◆ XHCI_SCTX_2_TT_HUB_SID_GET

#define XHCI_SCTX_2_TT_HUB_SID_GET (   x)    ((x) & 0xFF)

Definition at line 96 of file xhci.h.

◆ XHCI_SCTX_2_TT_HUB_SID_SET

#define XHCI_SCTX_2_TT_HUB_SID_SET (   x)    ((x) & 0xFF)

Definition at line 95 of file xhci.h.

◆ XHCI_SCTX_2_TT_PORT_NUM_GET

#define XHCI_SCTX_2_TT_PORT_NUM_GET (   x)    (((x) >> 8) & 0xFF)

Definition at line 98 of file xhci.h.

◆ XHCI_SCTX_2_TT_PORT_NUM_SET

#define XHCI_SCTX_2_TT_PORT_NUM_SET (   x)    (((x) & 0xFF) << 8)

Definition at line 97 of file xhci.h.

◆ XHCI_SCTX_2_TT_THINK_TIME_GET

#define XHCI_SCTX_2_TT_THINK_TIME_GET (   x)    (((x) >> 16) & 0x3)

Definition at line 100 of file xhci.h.

◆ XHCI_SCTX_2_TT_THINK_TIME_SET

#define XHCI_SCTX_2_TT_THINK_TIME_SET (   x)    (((x) & 0x3) << 16)

Definition at line 99 of file xhci.h.

◆ XHCI_SCTX_3_DEV_ADDR_GET

#define XHCI_SCTX_3_DEV_ADDR_GET (   x)    ((x) & 0xFF)

Definition at line 105 of file xhci.h.

◆ XHCI_SCTX_3_DEV_ADDR_SET

#define XHCI_SCTX_3_DEV_ADDR_SET (   x)    ((x) & 0xFF)

Definition at line 104 of file xhci.h.

◆ XHCI_SCTX_3_SLOT_STATE_GET

#define XHCI_SCTX_3_SLOT_STATE_GET (   x)    (((x) >> 27) & 0x1F)

Definition at line 107 of file xhci.h.

◆ XHCI_SCTX_3_SLOT_STATE_SET

#define XHCI_SCTX_3_SLOT_STATE_SET (   x)    (((x) & 0x1F) << 27)

Definition at line 106 of file xhci.h.

◆ XHCI_SLOT_CTX_ALIGN

#define XHCI_SLOT_CTX_ALIGN   32 /* bytes */

Definition at line 52 of file xhci.h.

◆ XHCI_STREAM_CTX_ALIGN

#define XHCI_STREAM_CTX_ALIGN   16 /* bytes */

Definition at line 54 of file xhci.h.

◆ XHCI_TD_ALIGN

#define XHCI_TD_ALIGN   64 /* bytes */

Definition at line 61 of file xhci.h.

◆ XHCI_TD_PAGE_NBUF

#define XHCI_TD_PAGE_NBUF    (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1)

Definition at line 371 of file xhci.h.

◆ XHCI_TD_PAGE_SIZE

#define XHCI_TD_PAGE_SIZE    ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX)

Definition at line 367 of file xhci.h.

◆ XHCI_TD_PAYLOAD_MAX

#define XHCI_TD_PAYLOAD_MAX   65536 /* bytes */

Definition at line 364 of file xhci.h.

◆ XHCI_TRANS_RING_SEG_ALIGN

#define XHCI_TRANS_RING_SEG_ALIGN   16 /* bytes */

Definition at line 55 of file xhci.h.

◆ XHCI_TRB_0_DIR_IN_MASK

#define XHCI_TRB_0_DIR_IN_MASK   (0x80ULL << 0)

Definition at line 1 of file xhci.h.

◆ XHCI_TRB_0_WLENGTH_MASK

#define XHCI_TRB_0_WLENGTH_MASK   (0xFFFFULL << 48)

Definition at line 2 of file xhci.h.

◆ XHCI_TRB_2_BYTES_GET

#define XHCI_TRB_2_BYTES_GET (   x)    ((x) & 0x1FFFF)

Definition at line 10 of file xhci.h.

◆ XHCI_TRB_2_BYTES_SET

#define XHCI_TRB_2_BYTES_SET (   x)    ((x) & 0x1FFFF)

Definition at line 11 of file xhci.h.

◆ XHCI_TRB_2_ERROR_GET

#define XHCI_TRB_2_ERROR_GET (   x)    (((x) >> 24) & 0xFF)

Definition at line 4 of file xhci.h.

◆ XHCI_TRB_2_ERROR_SET

#define XHCI_TRB_2_ERROR_SET (   x)    (((x) & 0xFF) << 24)

Definition at line 5 of file xhci.h.

◆ XHCI_TRB_2_IRQ_GET

#define XHCI_TRB_2_IRQ_GET (   x)    (((x) >> 22) & 0x3FF)

Definition at line 12 of file xhci.h.

◆ XHCI_TRB_2_IRQ_SET

#define XHCI_TRB_2_IRQ_SET (   x)    (((x) & 0x3FF) << 22)

Definition at line 13 of file xhci.h.

◆ XHCI_TRB_2_REM_GET

#define XHCI_TRB_2_REM_GET (   x)    ((x) & 0xFFFFFF)

Definition at line 8 of file xhci.h.

◆ XHCI_TRB_2_REM_SET

#define XHCI_TRB_2_REM_SET (   x)    ((x) & 0xFFFFFF)

Definition at line 9 of file xhci.h.

◆ XHCI_TRB_2_STREAM_GET

#define XHCI_TRB_2_STREAM_GET (   x)    (((x) >> 16) & 0xFFFF)

Definition at line 14 of file xhci.h.

◆ XHCI_TRB_2_STREAM_SET

#define XHCI_TRB_2_STREAM_SET (   x)    (((x) & 0xFFFF) << 16)

Definition at line 15 of file xhci.h.

◆ XHCI_TRB_2_TDSZ_GET

#define XHCI_TRB_2_TDSZ_GET (   x)    (((x) >> 17) & 0x1F)

Definition at line 6 of file xhci.h.

◆ XHCI_TRB_2_TDSZ_SET

#define XHCI_TRB_2_TDSZ_SET (   x)    (((x) & 0x1F) << 17)

Definition at line 7 of file xhci.h.

◆ XHCI_TRB_3_BEI_BIT

#define XHCI_TRB_3_BEI_BIT   (1U << 9)

Definition at line 30 of file xhci.h.

◆ XHCI_TRB_3_BSR_BIT

#define XHCI_TRB_3_BSR_BIT   (1U << 9)

Definition at line 33 of file xhci.h.

◆ XHCI_TRB_3_CHAIN_BIT

#define XHCI_TRB_3_CHAIN_BIT   (1U << 4)

Definition at line 25 of file xhci.h.

◆ XHCI_TRB_3_CYCLE_BIT

#define XHCI_TRB_3_CYCLE_BIT   (1U << 0)

Definition at line 20 of file xhci.h.

◆ XHCI_TRB_3_DCEP_BIT

#define XHCI_TRB_3_DCEP_BIT   (1U << 9)

Definition at line 31 of file xhci.h.

◆ XHCI_TRB_3_DIR_IN

#define XHCI_TRB_3_DIR_IN   (1U << 16)

Definition at line 38 of file xhci.h.

◆ XHCI_TRB_3_ENT_BIT

#define XHCI_TRB_3_ENT_BIT   (1U << 1) /* transfer ring only */

Definition at line 22 of file xhci.h.

◆ XHCI_TRB_3_EP_GET

#define XHCI_TRB_3_EP_GET (   x)    (((x) >> 16) & 0x1F)

Definition at line 41 of file xhci.h.

◆ XHCI_TRB_3_EP_SET

#define XHCI_TRB_3_EP_SET (   x)    (((x) & 0x1F) << 16)

Definition at line 42 of file xhci.h.

◆ XHCI_TRB_3_FRID_GET

#define XHCI_TRB_3_FRID_GET (   x)    (((x) >> 20) & 0x7FF)

Definition at line 43 of file xhci.h.

◆ XHCI_TRB_3_FRID_SET

#define XHCI_TRB_3_FRID_SET (   x)    (((x) & 0x7FF) << 20)

Definition at line 44 of file xhci.h.

◆ XHCI_TRB_3_IDT_BIT

#define XHCI_TRB_3_IDT_BIT   (1U << 6)

Definition at line 27 of file xhci.h.

◆ XHCI_TRB_3_IOC_BIT

#define XHCI_TRB_3_IOC_BIT   (1U << 5)

Definition at line 26 of file xhci.h.

◆ XHCI_TRB_3_ISO_SIA_BIT

#define XHCI_TRB_3_ISO_SIA_BIT   (1U << 31)

Definition at line 45 of file xhci.h.

◆ XHCI_TRB_3_ISP_BIT

#define XHCI_TRB_3_ISP_BIT   (1U << 2)

Definition at line 23 of file xhci.h.

◆ XHCI_TRB_3_NSNOOP_BIT

#define XHCI_TRB_3_NSNOOP_BIT   (1U << 3)

Definition at line 24 of file xhci.h.

◆ XHCI_TRB_3_PRSV_BIT

#define XHCI_TRB_3_PRSV_BIT   (1U << 9)

Definition at line 32 of file xhci.h.

◆ XHCI_TRB_3_SLOT_GET

#define XHCI_TRB_3_SLOT_GET (   x)    (((x) >> 24) & 0xFF)

Definition at line 47 of file xhci.h.

◆ XHCI_TRB_3_SLOT_SET

#define XHCI_TRB_3_SLOT_SET (   x)    (((x) & 0xFF) << 24)

Definition at line 48 of file xhci.h.

◆ XHCI_TRB_3_SUSP_EP_BIT

#define XHCI_TRB_3_SUSP_EP_BIT   (1U << 23)

Definition at line 46 of file xhci.h.

◆ XHCI_TRB_3_TBC_GET

#define XHCI_TRB_3_TBC_GET (   x)    (((x) >> 7) & 3)

Definition at line 28 of file xhci.h.

◆ XHCI_TRB_3_TBC_SET

#define XHCI_TRB_3_TBC_SET (   x)    (((x) & 3) << 7)

Definition at line 29 of file xhci.h.

◆ XHCI_TRB_3_TC_BIT

#define XHCI_TRB_3_TC_BIT   (1U << 1) /* command ring only */

Definition at line 21 of file xhci.h.

◆ XHCI_TRB_3_TLBPC_GET

#define XHCI_TRB_3_TLBPC_GET (   x)    (((x) >> 16) & 0xF)

Definition at line 39 of file xhci.h.

◆ XHCI_TRB_3_TLBPC_SET

#define XHCI_TRB_3_TLBPC_SET (   x)    (((x) & 0xF) << 16)

Definition at line 40 of file xhci.h.

◆ XHCI_TRB_3_TRT_IN

#define XHCI_TRB_3_TRT_IN   (3U << 16)

Definition at line 37 of file xhci.h.

◆ XHCI_TRB_3_TRT_MASK

#define XHCI_TRB_3_TRT_MASK   (3U << 16)

Definition at line 34 of file xhci.h.

◆ XHCI_TRB_3_TRT_NONE

#define XHCI_TRB_3_TRT_NONE   (0U << 16)

Definition at line 35 of file xhci.h.

◆ XHCI_TRB_3_TRT_OUT

#define XHCI_TRB_3_TRT_OUT   (2U << 16)

Definition at line 36 of file xhci.h.

◆ XHCI_TRB_3_TYPE_GET

#define XHCI_TRB_3_TYPE_GET (   x)    (((x) >> 10) & 0x3F)

Definition at line 18 of file xhci.h.

◆ XHCI_TRB_3_TYPE_SET

#define XHCI_TRB_3_TYPE_SET (   x)    (((x) & 0x3F) << 10)

Definition at line 19 of file xhci.h.

◆ XHCI_TRB_ALIGN

#define XHCI_TRB_ALIGN   16 /* bytes */

Definition at line 60 of file xhci.h.

◆ XHCI_TRB_ERROR_BABBLE

#define XHCI_TRB_ERROR_BABBLE   0x03

Definition at line 90 of file xhci.h.

◆ XHCI_TRB_ERROR_BAD_MELAT

#define XHCI_TRB_ERROR_BAD_MELAT   0x1D

Definition at line 115 of file xhci.h.

◆ XHCI_TRB_ERROR_BANDWIDTH

#define XHCI_TRB_ERROR_BANDWIDTH   0x08

Definition at line 95 of file xhci.h.

◆ XHCI_TRB_ERROR_BW_OVERRUN

#define XHCI_TRB_ERROR_BW_OVERRUN   0x12

Definition at line 105 of file xhci.h.

◆ XHCI_TRB_ERROR_CMD_ABORTED

#define XHCI_TRB_ERROR_CMD_ABORTED   0x19

Definition at line 112 of file xhci.h.

◆ XHCI_TRB_ERROR_CMD_RING_STOP

#define XHCI_TRB_ERROR_CMD_RING_STOP   0x18

Definition at line 111 of file xhci.h.

◆ XHCI_TRB_ERROR_CONTEXT_STATE

#define XHCI_TRB_ERROR_CONTEXT_STATE   0x13

Definition at line 106 of file xhci.h.

◆ XHCI_TRB_ERROR_DATA_BUF

#define XHCI_TRB_ERROR_DATA_BUF   0x02

Definition at line 89 of file xhci.h.

◆ XHCI_TRB_ERROR_ENDP_NOT_ON

#define XHCI_TRB_ERROR_ENDP_NOT_ON   0x0C

Definition at line 99 of file xhci.h.

◆ XHCI_TRB_ERROR_EV_RING_FULL

#define XHCI_TRB_ERROR_EV_RING_FULL   0x15

Definition at line 108 of file xhci.h.

◆ XHCI_TRB_ERROR_EVENT_LOST

#define XHCI_TRB_ERROR_EVENT_LOST   0x20

Definition at line 117 of file xhci.h.

◆ XHCI_TRB_ERROR_INCOMPAT_DEV

#define XHCI_TRB_ERROR_INCOMPAT_DEV   0x16

Definition at line 109 of file xhci.h.

◆ XHCI_TRB_ERROR_INVALID

#define XHCI_TRB_ERROR_INVALID   0x00

Definition at line 87 of file xhci.h.

◆ XHCI_TRB_ERROR_INVALID_SID

#define XHCI_TRB_ERROR_INVALID_SID   0x22

Definition at line 119 of file xhci.h.

◆ XHCI_TRB_ERROR_ISOC_OVERRUN

#define XHCI_TRB_ERROR_ISOC_OVERRUN   0x1F

Definition at line 116 of file xhci.h.

◆ XHCI_TRB_ERROR_LENGTH

#define XHCI_TRB_ERROR_LENGTH   0x1B

Definition at line 114 of file xhci.h.

◆ XHCI_TRB_ERROR_MISSED_SERVICE

#define XHCI_TRB_ERROR_MISSED_SERVICE   0x17

Definition at line 110 of file xhci.h.

◆ XHCI_TRB_ERROR_NO_PING_RESP

#define XHCI_TRB_ERROR_NO_PING_RESP   0x14

Definition at line 107 of file xhci.h.

◆ XHCI_TRB_ERROR_NO_SLOTS

#define XHCI_TRB_ERROR_NO_SLOTS   0x09

Definition at line 96 of file xhci.h.

◆ XHCI_TRB_ERROR_PARAMETER

#define XHCI_TRB_ERROR_PARAMETER   0x11

Definition at line 104 of file xhci.h.

◆ XHCI_TRB_ERROR_RESOURCE

#define XHCI_TRB_ERROR_RESOURCE   0x07

Definition at line 94 of file xhci.h.

◆ XHCI_TRB_ERROR_RING_OVERRUN

#define XHCI_TRB_ERROR_RING_OVERRUN   0x0F

Definition at line 102 of file xhci.h.

◆ XHCI_TRB_ERROR_RING_UNDERRUN

#define XHCI_TRB_ERROR_RING_UNDERRUN   0x0E

Definition at line 101 of file xhci.h.

◆ XHCI_TRB_ERROR_SEC_BW

#define XHCI_TRB_ERROR_SEC_BW   0x23

Definition at line 120 of file xhci.h.

◆ XHCI_TRB_ERROR_SHORT_PKT

#define XHCI_TRB_ERROR_SHORT_PKT   0x0D

Definition at line 100 of file xhci.h.

◆ XHCI_TRB_ERROR_SLOT_NOT_ON

#define XHCI_TRB_ERROR_SLOT_NOT_ON   0x0B

Definition at line 98 of file xhci.h.

◆ XHCI_TRB_ERROR_SPLIT_XACT

#define XHCI_TRB_ERROR_SPLIT_XACT   0x24

Definition at line 121 of file xhci.h.

◆ XHCI_TRB_ERROR_STALL

#define XHCI_TRB_ERROR_STALL   0x06

Definition at line 93 of file xhci.h.

◆ XHCI_TRB_ERROR_STOPPED

#define XHCI_TRB_ERROR_STOPPED   0x1A

Definition at line 113 of file xhci.h.

◆ XHCI_TRB_ERROR_STREAM_TYPE

#define XHCI_TRB_ERROR_STREAM_TYPE   0x0A

Definition at line 97 of file xhci.h.

◆ XHCI_TRB_ERROR_SUCCESS

#define XHCI_TRB_ERROR_SUCCESS   0x01

Definition at line 88 of file xhci.h.

◆ XHCI_TRB_ERROR_TRB

#define XHCI_TRB_ERROR_TRB   0x05

Definition at line 92 of file xhci.h.

◆ XHCI_TRB_ERROR_UNDEFINED

#define XHCI_TRB_ERROR_UNDEFINED   0x21

Definition at line 118 of file xhci.h.

◆ XHCI_TRB_ERROR_VF_RING_FULL

#define XHCI_TRB_ERROR_VF_RING_FULL   0x10

Definition at line 103 of file xhci.h.

◆ XHCI_TRB_ERROR_XACT

#define XHCI_TRB_ERROR_XACT   0x04

Definition at line 91 of file xhci.h.

◆ XHCI_TRB_EVENT_BW_REQUEST

#define XHCI_TRB_EVENT_BW_REQUEST   0x23

Definition at line 80 of file xhci.h.

◆ XHCI_TRB_EVENT_CMD_COMPLETE

#define XHCI_TRB_EVENT_CMD_COMPLETE   0x21

Definition at line 78 of file xhci.h.

◆ XHCI_TRB_EVENT_DEVICE_NOTIFY

#define XHCI_TRB_EVENT_DEVICE_NOTIFY   0x26

Definition at line 83 of file xhci.h.

◆ XHCI_TRB_EVENT_DOORBELL

#define XHCI_TRB_EVENT_DOORBELL   0x24

Definition at line 81 of file xhci.h.

◆ XHCI_TRB_EVENT_HOST_CTRL

#define XHCI_TRB_EVENT_HOST_CTRL   0x25

Definition at line 82 of file xhci.h.

◆ XHCI_TRB_EVENT_MFINDEX_WRAP

#define XHCI_TRB_EVENT_MFINDEX_WRAP   0x27

Definition at line 84 of file xhci.h.

◆ XHCI_TRB_EVENT_PORT_STS_CHANGE

#define XHCI_TRB_EVENT_PORT_STS_CHANGE   0x22

Definition at line 79 of file xhci.h.

◆ XHCI_TRB_EVENT_TRANSFER

#define XHCI_TRB_EVENT_TRANSFER   0x20

Definition at line 77 of file xhci.h.

◆ XHCI_TRB_TYPE_ADDRESS_DEVICE

#define XHCI_TRB_TYPE_ADDRESS_DEVICE   0x0B

Definition at line 62 of file xhci.h.

◆ XHCI_TRB_TYPE_CONFIGURE_EP

#define XHCI_TRB_TYPE_CONFIGURE_EP   0x0C

Definition at line 63 of file xhci.h.

◆ XHCI_TRB_TYPE_DATA_STAGE

#define XHCI_TRB_TYPE_DATA_STAGE   0x03

Definition at line 54 of file xhci.h.

◆ XHCI_TRB_TYPE_DISABLE_SLOT

#define XHCI_TRB_TYPE_DISABLE_SLOT   0x0A

Definition at line 61 of file xhci.h.

◆ XHCI_TRB_TYPE_ENABLE_SLOT

#define XHCI_TRB_TYPE_ENABLE_SLOT   0x09

Definition at line 60 of file xhci.h.

◆ XHCI_TRB_TYPE_EVALUATE_CTX

#define XHCI_TRB_TYPE_EVALUATE_CTX   0x0D

Definition at line 64 of file xhci.h.

◆ XHCI_TRB_TYPE_EVENT_DATA

#define XHCI_TRB_TYPE_EVENT_DATA   0x07

Definition at line 58 of file xhci.h.

◆ XHCI_TRB_TYPE_FORCE_EVENT

#define XHCI_TRB_TYPE_FORCE_EVENT   0x12

Definition at line 69 of file xhci.h.

◆ XHCI_TRB_TYPE_FORCE_HEADER

#define XHCI_TRB_TYPE_FORCE_HEADER   0x16

Definition at line 73 of file xhci.h.

◆ XHCI_TRB_TYPE_GET_PORT_BW

#define XHCI_TRB_TYPE_GET_PORT_BW   0x15

Definition at line 72 of file xhci.h.

◆ XHCI_TRB_TYPE_ISOCH

#define XHCI_TRB_TYPE_ISOCH   0x05

Definition at line 56 of file xhci.h.

◆ XHCI_TRB_TYPE_LINK

#define XHCI_TRB_TYPE_LINK   0x06

Definition at line 57 of file xhci.h.

◆ XHCI_TRB_TYPE_NEGOTIATE_BW

#define XHCI_TRB_TYPE_NEGOTIATE_BW   0x13

Definition at line 70 of file xhci.h.

◆ XHCI_TRB_TYPE_NOOP

#define XHCI_TRB_TYPE_NOOP   0x08

Definition at line 59 of file xhci.h.

◆ XHCI_TRB_TYPE_NOOP_CMD

#define XHCI_TRB_TYPE_NOOP_CMD   0x17

Definition at line 74 of file xhci.h.

◆ XHCI_TRB_TYPE_NORMAL

#define XHCI_TRB_TYPE_NORMAL   0x01

Definition at line 52 of file xhci.h.

◆ XHCI_TRB_TYPE_RESERVED

#define XHCI_TRB_TYPE_RESERVED   0x00

Definition at line 51 of file xhci.h.

◆ XHCI_TRB_TYPE_RESET_DEVICE

#define XHCI_TRB_TYPE_RESET_DEVICE   0x11

Definition at line 68 of file xhci.h.

◆ XHCI_TRB_TYPE_RESET_EP

#define XHCI_TRB_TYPE_RESET_EP   0x0E

Definition at line 65 of file xhci.h.

◆ XHCI_TRB_TYPE_SET_LATENCY_TOL

#define XHCI_TRB_TYPE_SET_LATENCY_TOL   0x14

Definition at line 71 of file xhci.h.

◆ XHCI_TRB_TYPE_SET_TR_DEQUEUE

#define XHCI_TRB_TYPE_SET_TR_DEQUEUE   0x10

Definition at line 67 of file xhci.h.

◆ XHCI_TRB_TYPE_SETUP_STAGE

#define XHCI_TRB_TYPE_SETUP_STAGE   0x02

Definition at line 53 of file xhci.h.

◆ XHCI_TRB_TYPE_STATUS_STAGE

#define XHCI_TRB_TYPE_STATUS_STAGE   0x04

Definition at line 55 of file xhci.h.

◆ XHCI_TRB_TYPE_STOP_EP

#define XHCI_TRB_TYPE_STOP_EP   0x0F

Definition at line 66 of file xhci.h.

Typedef Documentation

◆ xhci_port_route_t

typedef int() xhci_port_route_t(device_t, uint32_t, uint32_t)

Definition at line 488 of file xhci.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
XHCI_ST_DISABLED 
XHCI_ST_ENABLED 
XHCI_ST_DEFAULT 
XHCI_ST_ADDRESSED 
XHCI_ST_CONFIGURED 
XHCI_ST_MAX 

Definition at line 427 of file xhci.h.

Function Documentation

◆ __aligned() [1/3]

struct xhci_trb __aligned ( )

◆ __aligned() [2/3]

struct xhci_dev_ctx __aligned ( XHCI_DEV_CTX_ALIGN  )

◆ __aligned() [3/3]

struct xhci_td __aligned ( XHCI_TRB_ALIGN  )

◆ CTASSERT()

CTASSERT ( sizeof(struct xhci_hw_root = =XHCI_PAGE_SIZE)

◆ DECLARE_CLASS()

DECLARE_CLASS ( xhci_pci_driver  )

◆ xhci_halt_controller()

usb_error_t xhci_halt_controller ( struct xhci_softc sc)

◆ xhci_init()

usb_error_t xhci_init ( struct xhci_softc sc,
device_t  self,
uint8_t  dma32 
)

◆ xhci_interrupt()

void xhci_interrupt ( struct xhci_softc sc)

Definition at line 1603 of file xhci.c.

References xhci_softc::sc_bus, status, USB_BUS_LOCK, USB_BUS_UNLOCK, XHCI_IMAN, XHCI_IMAN_INTR_PEND, xhci_interrupt_poll(), xhci_root_intr(), XHCI_STS_HCE, XHCI_STS_HCH, XHCI_STS_HSE, XHCI_STS_PCD, XHCI_USBSTS, XREAD4, and XWRITE4.

Referenced by generic_xhci_attach(), snps_dwc3_attach_xhci(), xhci_interrupt_poll(), and xhci_pci_attach().

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◆ xhci_pci_attach()

◆ xhci_reset_controller()

usb_error_t xhci_reset_controller ( struct xhci_softc sc)

Definition at line 484 of file xhci.c.

References DPRINTF, usb_bus::parent, xhci_softc::sc_bus, USB_ERR_IOERROR, usb_pause_mtx(), XHCI_CMD_HCRST, XHCI_STS_CNR, XHCI_USBCMD, XHCI_USBSTS, XREAD4, and XWRITE4.

Referenced by xhci_pci_detach(), xhci_set_hw_power_sleep(), and xhci_start_controller().

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◆ xhci_start_controller()

◆ xhci_uninit()

void xhci_uninit ( struct xhci_softc sc)

Definition at line 644 of file xhci.c.

References xhci_softc::sc_bus, xhci_softc::sc_cmd_cv, xhci_softc::sc_cmd_sx, usb_bus_mem_free_all(), and xhci_iterate_hw_softc().

Referenced by generic_xhci_detach(), and xhci_pci_detach().

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◆ xhci_use_polling()

uint8_t xhci_use_polling ( void  )

Definition at line 213 of file xhci.c.

Referenced by xhci_pci_attach().

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Variable Documentation

◆ __aligned

struct xhci_command __aligned

◆ __packed

◆ alt_next

struct xhci_td* alt_next

Definition at line 8 of file xhci.h.

◆ ctx_ep

struct xhci_endp_ctx64 ctx_ep

Definition at line 1 of file xhci.h.

Referenced by xhci_configure_endpoint(), and xhci_get_endpoint_state().

◆ ctx_slot

struct xhci_slot_ctx64 ctx_slot

Definition at line 0 of file xhci.h.

Referenced by xhci_configure_device(), xhci_configure_mask(), and xhci_set_address().

◆ dummy

volatile uint64_t dummy

Definition at line 0 of file xhci.h.

◆ dwTrb2

volatile uint32_t dwTrb2

Definition at line 3 of file xhci.h.

Referenced by xhci_configure_endpoint_by_xfer().

◆ dwTrb3

volatile uint32_t dwTrb3

Definition at line 17 of file xhci.h.

Referenced by xhci_configure_endpoint_by_xfer().

◆ len

uint32_t len

Definition at line 11 of file xhci.h.

◆ next

struct xhci_td* next

Definition at line 7 of file xhci.h.

◆ ntrb

uint8_t ntrb

Definition at line 13 of file xhci.h.

◆ obj_next

struct xhci_td* obj_next

Definition at line 9 of file xhci.h.

◆ page_cache

struct usb_page_cache* page_cache

Definition at line 10 of file xhci.h.

◆ qwTrb0

volatile uint64_t qwTrb0

Definition at line 0 of file xhci.h.

Referenced by xhci_configure_endpoint_by_xfer().

◆ remainder

uint32_t remainder

Definition at line 12 of file xhci.h.

Referenced by rum_setup_tx_desc(), ural_setup_tx_desc(), and xhci_check_transfer().

◆ status

◆ td_self

uint64_t td_self

Definition at line 6 of file xhci.h.

◆ td_trb

struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF+1]

Definition at line 1 of file xhci.h.