FreeBSD kernel usb device Code
musb_otg.c
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1/* $FreeBSD$ */
2/*-
3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 *
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
31 * at their homepage.
32 */
33
34/*
35 * This file contains the driver for the Mentor Graphics Inventra USB
36 * 2.0 High Speed Dual-Role controller.
37 *
38 */
39
40#ifdef USB_GLOBAL_INCLUDE_FILE
41#include USB_GLOBAL_INCLUDE_FILE
42#else
43#include <sys/stdint.h>
44#include <sys/stddef.h>
45#include <sys/param.h>
46#include <sys/queue.h>
47#include <sys/types.h>
48#include <sys/systm.h>
49#include <sys/kernel.h>
50#include <sys/bus.h>
51#include <sys/module.h>
52#include <sys/lock.h>
53#include <sys/mutex.h>
54#include <sys/condvar.h>
55#include <sys/sysctl.h>
56#include <sys/sx.h>
57#include <sys/unistd.h>
58#include <sys/callout.h>
59#include <sys/malloc.h>
60#include <sys/priv.h>
61
62#include <dev/usb/usb.h>
63#include <dev/usb/usbdi.h>
64
65#define USB_DEBUG_VAR musbotgdebug
66
67#include <dev/usb/usb_core.h>
68#include <dev/usb/usb_debug.h>
69#include <dev/usb/usb_busdma.h>
70#include <dev/usb/usb_process.h>
71#include <dev/usb/usb_transfer.h>
72#include <dev/usb/usb_device.h>
73#include <dev/usb/usb_hub.h>
74#include <dev/usb/usb_util.h>
75
76#include <dev/usb/usb_controller.h>
77#include <dev/usb/usb_bus.h>
78#endif /* USB_GLOBAL_INCLUDE_FILE */
79
80#include <dev/usb/controller/musb_otg.h>
81
82#define MUSBOTG_INTR_ENDPT 1
83
84#define MUSBOTG_BUS2SC(bus) \
85 __containerof(bus, struct musbotg_softc, sc_bus)
86
87#define MUSBOTG_PC2SC(pc) \
88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
89
90#ifdef USB_DEBUG
91static int musbotgdebug = 0;
92
93static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
94 "USB musbotg");
95SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
96 &musbotgdebug, 0, "Debug level");
97#endif
98
99#define MAX_NAK_TO 16
100
101/* prototypes */
102
103static const struct usb_bus_methods musbotg_bus_methods;
104static const struct usb_pipe_methods musbotg_device_bulk_methods;
105static const struct usb_pipe_methods musbotg_device_ctrl_methods;
106static const struct usb_pipe_methods musbotg_device_intr_methods;
107static const struct usb_pipe_methods musbotg_device_isoc_methods;
108
109/* Control transfers: Device mode */
110static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
111static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
112static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
113static musbotg_cmd_t musbotg_dev_ctrl_status;
114
115/* Control transfers: Host mode */
116static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
117static musbotg_cmd_t musbotg_host_ctrl_data_rx;
118static musbotg_cmd_t musbotg_host_ctrl_data_tx;
119static musbotg_cmd_t musbotg_host_ctrl_status_rx;
120static musbotg_cmd_t musbotg_host_ctrl_status_tx;
121
122/* Bulk, Interrupt, Isochronous: Device mode */
123static musbotg_cmd_t musbotg_dev_data_rx;
124static musbotg_cmd_t musbotg_dev_data_tx;
125
126/* Bulk, Interrupt, Isochronous: Host mode */
127static musbotg_cmd_t musbotg_host_data_rx;
128static musbotg_cmd_t musbotg_host_data_tx;
129
130static void musbotg_device_done(struct usb_xfer *, usb_error_t);
131static void musbotg_do_poll(struct usb_bus *);
132static void musbotg_standard_done(struct usb_xfer *);
133static void musbotg_interrupt_poll(struct musbotg_softc *);
134static void musbotg_root_intr(struct musbotg_softc *);
135static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
136static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
137static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
138
139/*
140 * Here is a configuration that the chip supports.
141 */
142static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
143 [0] = {
144 .max_in_frame_size = 64,/* fixed */
145 .max_out_frame_size = 64, /* fixed */
146 .is_simplex = 1,
147 .support_control = 1,
148 }
149};
150
151static const struct musb_otg_ep_cfg musbotg_ep_default[] = {
152 {
153 .ep_end = 1,
154 .ep_fifosz_shift = 12,
155 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB,
156 },
157 {
158 .ep_end = 7,
159 .ep_fifosz_shift = 10,
160 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB,
161 },
162 {
163 .ep_end = 15,
164 .ep_fifosz_shift = 7,
165 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128,
166 },
167 {
168 .ep_end = -1,
169 },
170};
171
172static int
173musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
174{
175 int ch;
176 int ep;
177
178 ep = td->ep_no;
179
180 /* In device mode each EP got its own channel */
181 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
182 musbotg_ep_int_set(sc, ep, 1);
183 return (ep);
184 }
185
186 /*
187 * All control transactions go through EP0
188 */
189 if (ep == 0) {
190 if (sc->sc_channel_mask & (1 << 0))
191 return (-1);
192 sc->sc_channel_mask |= (1 << 0);
193 musbotg_ep_int_set(sc, ep, 1);
194 return (0);
195 }
196
197 for (ch = sc->sc_ep_max; ch != 0; ch--) {
198 if (sc->sc_channel_mask & (1 << ch))
199 continue;
200
201 /* check FIFO size requirement */
202 if (is_tx) {
203 if (td->max_frame_size >
204 sc->sc_hw_ep_profile[ch].max_in_frame_size)
205 continue;
206 } else {
207 if (td->max_frame_size >
208 sc->sc_hw_ep_profile[ch].max_out_frame_size)
209 continue;
210 }
211 sc->sc_channel_mask |= (1 << ch);
212 musbotg_ep_int_set(sc, ch, 1);
213 return (ch);
214 }
215
216 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
217
218 return (-1);
219}
220
221static void
222musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
223{
224
225 DPRINTFN(1, "ep_no=%d\n", td->channel);
226
227 if (sc->sc_mode == MUSB2_DEVICE_MODE)
228 return;
229
230 if (td == NULL)
231 return;
232 if (td->channel == -1)
233 return;
234
235 musbotg_ep_int_set(sc, td->channel, 0);
236 sc->sc_channel_mask &= ~(1 << td->channel);
237
238 td->channel = -1;
239}
240
241static void
242musbotg_get_hw_ep_profile(struct usb_device *udev,
243 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
244{
245 struct musbotg_softc *sc;
246
247 sc = MUSBOTG_BUS2SC(udev->bus);
248
249 if (ep_addr == 0) {
250 /* control endpoint */
251 *ppf = musbotg_ep_profile;
252 } else if (ep_addr <= sc->sc_ep_max) {
253 /* other endpoints */
254 *ppf = sc->sc_hw_ep_profile + ep_addr;
255 } else {
256 *ppf = NULL;
257 }
258}
259
260static void
261musbotg_clocks_on(struct musbotg_softc *sc)
262{
263 if (sc->sc_flags.clocks_off &&
264 sc->sc_flags.port_powered) {
265 DPRINTFN(4, "\n");
266
267 if (sc->sc_clocks_on) {
268 (sc->sc_clocks_on) (sc->sc_clocks_arg);
269 }
270 sc->sc_flags.clocks_off = 0;
271
272 /* XXX enable Transceiver */
273 }
274}
275
276static void
277musbotg_clocks_off(struct musbotg_softc *sc)
278{
279 if (!sc->sc_flags.clocks_off) {
280 DPRINTFN(4, "\n");
281
282 /* XXX disable Transceiver */
283
284 if (sc->sc_clocks_off) {
285 (sc->sc_clocks_off) (sc->sc_clocks_arg);
286 }
287 sc->sc_flags.clocks_off = 1;
288 }
289}
290
291static void
292musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
293{
294 uint8_t temp;
295
296 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
297 if (on)
298 temp |= MUSB2_MASK_SOFTC;
299 else
300 temp &= ~MUSB2_MASK_SOFTC;
301
302 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
303}
304
305static void
306musbotg_pull_up(struct musbotg_softc *sc)
307{
308 /* pullup D+, if possible */
309
310 if (!sc->sc_flags.d_pulled_up &&
311 sc->sc_flags.port_powered) {
312 sc->sc_flags.d_pulled_up = 1;
313 musbotg_pull_common(sc, 1);
314 }
315}
316
317static void
318musbotg_pull_down(struct musbotg_softc *sc)
319{
320 /* pulldown D+, if possible */
321
322 if (sc->sc_flags.d_pulled_up) {
323 sc->sc_flags.d_pulled_up = 0;
324 musbotg_pull_common(sc, 0);
325 }
326}
327
328static void
329musbotg_suspend_host(struct musbotg_softc *sc)
330{
331 uint8_t temp;
332
333 if (sc->sc_flags.status_suspend) {
334 return;
335 }
336
337 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
338 temp |= MUSB2_MASK_SUSPMODE;
339 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
340 sc->sc_flags.status_suspend = 1;
341}
342
343static void
344musbotg_wakeup_host(struct musbotg_softc *sc)
345{
346 uint8_t temp;
347
348 if (!(sc->sc_flags.status_suspend)) {
349 return;
350 }
351
352 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
353 temp &= ~MUSB2_MASK_SUSPMODE;
354 temp |= MUSB2_MASK_RESUME;
355 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
356
357 /* wait 20 milliseconds */
358 /* Wait for reset to complete. */
359 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
360
361 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
362 temp &= ~MUSB2_MASK_RESUME;
363 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
364
365 sc->sc_flags.status_suspend = 0;
366}
367
368static void
369musbotg_wakeup_peer(struct musbotg_softc *sc)
370{
371 uint8_t temp;
372
373 if (!(sc->sc_flags.status_suspend)) {
374 return;
375 }
376
377 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
378 temp |= MUSB2_MASK_RESUME;
379 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
380
381 /* wait 8 milliseconds */
382 /* Wait for reset to complete. */
383 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
384
385 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
386 temp &= ~MUSB2_MASK_RESUME;
387 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
388}
389
390static void
391musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
392{
393 DPRINTFN(4, "addr=%d\n", addr);
394 addr &= 0x7F;
395 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
396}
397
398static uint8_t
399musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
400{
401 struct musbotg_softc *sc;
402 struct usb_device_request req;
403 uint16_t count;
404 uint8_t csr;
405
406 /* get pointer to softc */
407 sc = MUSBOTG_PC2SC(td->pc);
408
409 if (td->channel == -1)
410 td->channel = musbotg_channel_alloc(sc, td, 0);
411
412 /* EP0 is busy, wait */
413 if (td->channel == -1)
414 return (1);
415
416 DPRINTFN(1, "ep_no=%d\n", td->channel);
417
418 /* select endpoint 0 */
419 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
420
421 /* read out FIFO status */
422 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
423
424 DPRINTFN(4, "csr=0x%02x\n", csr);
425
426 /*
427 * NOTE: If DATAEND is set we should not call the
428 * callback, hence the status stage is not complete.
429 */
430 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
431 /* do not stall at this point */
432 td->did_stall = 1;
433 /* wait for interrupt */
434 DPRINTFN(1, "CSR0 DATAEND\n");
435 goto not_complete;
436 }
437
438 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
439 /* clear SENTSTALL */
440 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
441 /* get latest status */
442 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
443 /* update EP0 state */
444 sc->sc_ep0_busy = 0;
445 }
446 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
447 /* clear SETUPEND */
448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
449 MUSB2_MASK_CSR0L_SETUPEND_CLR);
450 /* get latest status */
451 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
452 /* update EP0 state */
453 sc->sc_ep0_busy = 0;
454 }
455 if (sc->sc_ep0_busy) {
456 DPRINTFN(1, "EP0 BUSY\n");
457 goto not_complete;
458 }
459 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
460 goto not_complete;
461 }
462 /* get the packet byte count */
463 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
464
465 /* verify data length */
466 if (count != td->remainder) {
467 DPRINTFN(1, "Invalid SETUP packet "
468 "length, %d bytes\n", count);
469 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
470 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
471 /* don't clear stall */
472 td->did_stall = 1;
473 goto not_complete;
474 }
475 if (count != sizeof(req)) {
476 DPRINTFN(1, "Unsupported SETUP packet "
477 "length, %d bytes\n", count);
478 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
479 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
480 /* don't clear stall */
481 td->did_stall = 1;
482 goto not_complete;
483 }
484 /* clear did stall flag */
485 td->did_stall = 0;
486
487 /* receive data */
488 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
489 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
490
491 /* copy data into real buffer */
492 usbd_copy_in(td->pc, 0, &req, sizeof(req));
493
494 td->offset = sizeof(req);
495 td->remainder = 0;
496
497 /* set pending command */
498 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
499
500 /* we need set stall or dataend after this */
501 sc->sc_ep0_busy = 1;
502
503 /* sneak peek the set address */
504 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
505 (req.bRequest == UR_SET_ADDRESS)) {
506 sc->sc_dv_addr = req.wValue[0] & 0x7F;
507 } else {
508 sc->sc_dv_addr = 0xFF;
509 }
510
511 musbotg_channel_free(sc, td);
512 return (0); /* complete */
513
514not_complete:
515 /* abort any ongoing transfer */
516 if (!td->did_stall) {
517 DPRINTFN(4, "stalling\n");
518 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
519 MUSB2_MASK_CSR0L_SENDSTALL);
520 td->did_stall = 1;
521 }
522 return (1); /* not complete */
523}
524
525static uint8_t
526musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
527{
528 struct musbotg_softc *sc;
529 struct usb_device_request req;
530 uint8_t csr, csrh;
531
532 /* get pointer to softc */
533 sc = MUSBOTG_PC2SC(td->pc);
534
535 if (td->channel == -1)
536 td->channel = musbotg_channel_alloc(sc, td, 1);
537
538 /* EP0 is busy, wait */
539 if (td->channel == -1)
540 return (1);
541
542 DPRINTFN(1, "ep_no=%d\n", td->channel);
543
544 /* select endpoint 0 */
545 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
546
547 /* read out FIFO status */
548 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
549 DPRINTFN(4, "csr=0x%02x\n", csr);
550
551 /* Not ready yet yet */
552 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
553 return (1);
554
555 /* Failed */
556 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
557 MUSB2_MASK_CSR0L_ERROR))
558 {
559 /* Clear status bit */
560 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
561 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
562 td->error = 1;
563 }
564
565 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
566 DPRINTFN(1, "NAK timeout\n");
567
568 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
569 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
570 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
571 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
572 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
573 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
574 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
575 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
576 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
577 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
578 }
579 }
580
581 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
582 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
583
584 td->error = 1;
585 }
586
587 if (td->error) {
588 musbotg_channel_free(sc, td);
589 return (0);
590 }
591
592 /* Fifo is not empty and there is no NAK timeout */
593 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
594 return (1);
595
596 /* check if we are complete */
597 if (td->remainder == 0) {
598 /* we are complete */
599 musbotg_channel_free(sc, td);
600 return (0);
601 }
602
603 /* copy data into real buffer */
604 usbd_copy_out(td->pc, 0, &req, sizeof(req));
605
606 /* send data */
607 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
608 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
609
610 /* update offset and remainder */
611 td->offset += sizeof(req);
612 td->remainder -= sizeof(req);
613
614 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
615 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
616 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
617 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
618 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
619
620 /* write command */
621 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
622 MUSB2_MASK_CSR0L_TXPKTRDY |
623 MUSB2_MASK_CSR0L_SETUPPKT);
624
625 /* Just to be consistent, not used above */
626 td->transaction_started = 1;
627
628 return (1); /* in progress */
629}
630
631/* Control endpoint only data handling functions (RX/TX/SYNC) */
632
633static uint8_t
634musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
635{
636 struct usb_page_search buf_res;
637 struct musbotg_softc *sc;
638 uint16_t count;
639 uint8_t csr;
640 uint8_t got_short;
641
642 /* get pointer to softc */
643 sc = MUSBOTG_PC2SC(td->pc);
644
645 /* select endpoint 0 */
646 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
647
648 /* check if a command is pending */
649 if (sc->sc_ep0_cmd) {
650 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
651 sc->sc_ep0_cmd = 0;
652 }
653 /* read out FIFO status */
654 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
655
656 DPRINTFN(4, "csr=0x%02x\n", csr);
657
658 got_short = 0;
659
660 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
661 MUSB2_MASK_CSR0L_SENTSTALL)) {
662 if (td->remainder == 0) {
663 /*
664 * We are actually complete and have
665 * received the next SETUP
666 */
667 DPRINTFN(4, "faking complete\n");
668 return (0); /* complete */
669 }
670 /*
671 * USB Host Aborted the transfer.
672 */
673 td->error = 1;
674 return (0); /* complete */
675 }
676 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
677 return (1); /* not complete */
678 }
679 /* get the packet byte count */
680 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
681
682 /* verify the packet byte count */
683 if (count != td->max_frame_size) {
684 if (count < td->max_frame_size) {
685 /* we have a short packet */
686 td->short_pkt = 1;
687 got_short = 1;
688 } else {
689 /* invalid USB packet */
690 td->error = 1;
691 return (0); /* we are complete */
692 }
693 }
694 /* verify the packet byte count */
695 if (count > td->remainder) {
696 /* invalid USB packet */
697 td->error = 1;
698 return (0); /* we are complete */
699 }
700 while (count > 0) {
701 uint32_t temp;
702
703 usbd_get_page(td->pc, td->offset, &buf_res);
704
705 /* get correct length */
706 if (buf_res.length > count) {
707 buf_res.length = count;
708 }
709 /* check for unaligned memory address */
710 if (USB_P2U(buf_res.buffer) & 3) {
711 temp = count & ~3;
712
713 if (temp) {
714 /* receive data 4 bytes at a time */
715 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
716 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
717 temp / 4);
718 }
719 temp = count & 3;
720 if (temp) {
721 /* receive data 1 byte at a time */
722 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
723 MUSB2_REG_EPFIFO(0),
724 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
725 }
726 usbd_copy_in(td->pc, td->offset,
727 sc->sc_bounce_buf, count);
728
729 /* update offset and remainder */
730 td->offset += count;
731 td->remainder -= count;
732 break;
733 }
734 /* check if we can optimise */
735 if (buf_res.length >= 4) {
736 /* receive data 4 bytes at a time */
737 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
738 MUSB2_REG_EPFIFO(0), buf_res.buffer,
739 buf_res.length / 4);
740
741 temp = buf_res.length & ~3;
742
743 /* update counters */
744 count -= temp;
745 td->offset += temp;
746 td->remainder -= temp;
747 continue;
748 }
749 /* receive data */
750 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
751 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
752
753 /* update counters */
754 count -= buf_res.length;
755 td->offset += buf_res.length;
756 td->remainder -= buf_res.length;
757 }
758
759 /* check if we are complete */
760 if ((td->remainder == 0) || got_short) {
761 if (td->short_pkt) {
762 /* we are complete */
763 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
764 return (0);
765 }
766 /* else need to receive a zero length packet */
767 }
768 /* write command - need more data */
769 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
770 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
771 return (1); /* not complete */
772}
773
774static uint8_t
775musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
776{
777 struct usb_page_search buf_res;
778 struct musbotg_softc *sc;
779 uint16_t count;
780 uint8_t csr;
781
782 /* get pointer to softc */
783 sc = MUSBOTG_PC2SC(td->pc);
784
785 /* select endpoint 0 */
786 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
787
788 /* check if a command is pending */
789 if (sc->sc_ep0_cmd) {
790 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
791 sc->sc_ep0_cmd = 0;
792 }
793 /* read out FIFO status */
794 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
795
796 DPRINTFN(4, "csr=0x%02x\n", csr);
797
798 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
799 MUSB2_MASK_CSR0L_SENTSTALL)) {
800 /*
801 * The current transfer was aborted
802 * by the USB Host
803 */
804 td->error = 1;
805 return (0); /* complete */
806 }
807 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
808 return (1); /* not complete */
809 }
810 count = td->max_frame_size;
811 if (td->remainder < count) {
812 /* we have a short packet */
813 td->short_pkt = 1;
814 count = td->remainder;
815 }
816 while (count > 0) {
817 uint32_t temp;
818
819 usbd_get_page(td->pc, td->offset, &buf_res);
820
821 /* get correct length */
822 if (buf_res.length > count) {
823 buf_res.length = count;
824 }
825 /* check for unaligned memory address */
826 if (USB_P2U(buf_res.buffer) & 3) {
827 usbd_copy_out(td->pc, td->offset,
828 sc->sc_bounce_buf, count);
829
830 temp = count & ~3;
831
832 if (temp) {
833 /* transmit data 4 bytes at a time */
834 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
835 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
836 temp / 4);
837 }
838 temp = count & 3;
839 if (temp) {
840 /* receive data 1 byte at a time */
841 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
842 MUSB2_REG_EPFIFO(0),
843 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
844 }
845 /* update offset and remainder */
846 td->offset += count;
847 td->remainder -= count;
848 break;
849 }
850 /* check if we can optimise */
851 if (buf_res.length >= 4) {
852 /* transmit data 4 bytes at a time */
853 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
854 MUSB2_REG_EPFIFO(0), buf_res.buffer,
855 buf_res.length / 4);
856
857 temp = buf_res.length & ~3;
858
859 /* update counters */
860 count -= temp;
861 td->offset += temp;
862 td->remainder -= temp;
863 continue;
864 }
865 /* transmit data */
866 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
867 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
868
869 /* update counters */
870 count -= buf_res.length;
871 td->offset += buf_res.length;
872 td->remainder -= buf_res.length;
873 }
874
875 /* check remainder */
876 if (td->remainder == 0) {
877 if (td->short_pkt) {
878 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
879 return (0); /* complete */
880 }
881 /* else we need to transmit a short packet */
882 }
883 /* write command */
884 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
885 MUSB2_MASK_CSR0L_TXPKTRDY);
886
887 return (1); /* not complete */
888}
889
890static uint8_t
891musbotg_host_ctrl_data_rx(struct musbotg_td *td)
892{
893 struct usb_page_search buf_res;
894 struct musbotg_softc *sc;
895 uint16_t count;
896 uint8_t csr;
897 uint8_t got_short;
898
899 /* get pointer to softc */
900 sc = MUSBOTG_PC2SC(td->pc);
901
902 if (td->channel == -1)
903 td->channel = musbotg_channel_alloc(sc, td, 0);
904
905 /* EP0 is busy, wait */
906 if (td->channel == -1)
907 return (1);
908
909 DPRINTFN(1, "ep_no=%d\n", td->channel);
910
911 /* select endpoint 0 */
912 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
913
914 /* read out FIFO status */
915 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
916
917 DPRINTFN(4, "csr=0x%02x\n", csr);
918
919 got_short = 0;
920 if (!td->transaction_started) {
921 td->transaction_started = 1;
922
923 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
924
925 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
926 td->dev_addr);
927 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
928 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
929 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
930
931 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
932 MUSB2_MASK_CSR0L_REQPKT);
933
934 return (1);
935 }
936
937 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
938 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
939 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
940
941 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
942 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
943
944 td->error = 1;
945 }
946
947 /* Failed */
948 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
949 MUSB2_MASK_CSR0L_ERROR))
950 {
951 /* Clear status bit */
952 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
953 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
954 td->error = 1;
955 }
956
957 if (td->error) {
958 musbotg_channel_free(sc, td);
959 return (0); /* we are complete */
960 }
961
962 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
963 return (1); /* not yet */
964
965 /* get the packet byte count */
966 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
967
968 /* verify the packet byte count */
969 if (count != td->max_frame_size) {
970 if (count < td->max_frame_size) {
971 /* we have a short packet */
972 td->short_pkt = 1;
973 got_short = 1;
974 } else {
975 /* invalid USB packet */
976 td->error = 1;
977 musbotg_channel_free(sc, td);
978 return (0); /* we are complete */
979 }
980 }
981 /* verify the packet byte count */
982 if (count > td->remainder) {
983 /* invalid USB packet */
984 td->error = 1;
985 musbotg_channel_free(sc, td);
986 return (0); /* we are complete */
987 }
988 while (count > 0) {
989 uint32_t temp;
990
991 usbd_get_page(td->pc, td->offset, &buf_res);
992
993 /* get correct length */
994 if (buf_res.length > count) {
995 buf_res.length = count;
996 }
997 /* check for unaligned memory address */
998 if (USB_P2U(buf_res.buffer) & 3) {
999 temp = count & ~3;
1000
1001 if (temp) {
1002 /* receive data 4 bytes at a time */
1003 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1004 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
1005 temp / 4);
1006 }
1007 temp = count & 3;
1008 if (temp) {
1009 /* receive data 1 byte at a time */
1010 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1011 MUSB2_REG_EPFIFO(0),
1012 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
1013 }
1014 usbd_copy_in(td->pc, td->offset,
1015 sc->sc_bounce_buf, count);
1016
1017 /* update offset and remainder */
1018 td->offset += count;
1019 td->remainder -= count;
1020 break;
1021 }
1022 /* check if we can optimise */
1023 if (buf_res.length >= 4) {
1024 /* receive data 4 bytes at a time */
1025 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1026 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1027 buf_res.length / 4);
1028
1029 temp = buf_res.length & ~3;
1030
1031 /* update counters */
1032 count -= temp;
1033 td->offset += temp;
1034 td->remainder -= temp;
1035 continue;
1036 }
1037 /* receive data */
1038 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1039 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1040
1041 /* update counters */
1042 count -= buf_res.length;
1043 td->offset += buf_res.length;
1044 td->remainder -= buf_res.length;
1045 }
1046
1047 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1048 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1049
1050 /* check if we are complete */
1051 if ((td->remainder == 0) || got_short) {
1052 if (td->short_pkt) {
1053 /* we are complete */
1054
1055 musbotg_channel_free(sc, td);
1056 return (0);
1057 }
1058 /* else need to receive a zero length packet */
1059 }
1060
1061 td->transaction_started = 1;
1062 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1063 MUSB2_MASK_CSR0L_REQPKT);
1064
1065 return (1); /* not complete */
1066}
1067
1068static uint8_t
1069musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1070{
1071 struct usb_page_search buf_res;
1072 struct musbotg_softc *sc;
1073 uint16_t count;
1074 uint8_t csr, csrh;
1075
1076 /* get pointer to softc */
1077 sc = MUSBOTG_PC2SC(td->pc);
1078
1079 if (td->channel == -1)
1080 td->channel = musbotg_channel_alloc(sc, td, 1);
1081
1082 /* No free EPs */
1083 if (td->channel == -1)
1084 return (1);
1085
1086 DPRINTFN(1, "ep_no=%d\n", td->channel);
1087
1088 /* select endpoint */
1089 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1090
1091 /* read out FIFO status */
1092 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1093 DPRINTFN(4, "csr=0x%02x\n", csr);
1094
1095 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1096 MUSB2_MASK_CSR0L_ERROR)) {
1097 /* clear status bits */
1098 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1099 td->error = 1;
1100 }
1101
1102 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1103 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1104 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1105 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1106 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1107 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1108 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1109 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1110 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1111 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1112 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1113 }
1114 }
1115
1116 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1117 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1118
1119 td->error = 1;
1120 }
1121
1122 if (td->error) {
1123 musbotg_channel_free(sc, td);
1124 return (0); /* complete */
1125 }
1126
1127 /*
1128 * Wait while FIFO is empty.
1129 * Do not flush it because it will cause transactions
1130 * with size more then packet size. It might upset
1131 * some devices
1132 */
1133 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1134 return (1);
1135
1136 /* Packet still being processed */
1137 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1138 return (1);
1139
1140 if (td->transaction_started) {
1141 /* check remainder */
1142 if (td->remainder == 0) {
1143 if (td->short_pkt) {
1144 musbotg_channel_free(sc, td);
1145 return (0); /* complete */
1146 }
1147 /* else we need to transmit a short packet */
1148 }
1149
1150 /* We're not complete - more transactions required */
1151 td->transaction_started = 0;
1152 }
1153
1154 /* check for short packet */
1155 count = td->max_frame_size;
1156 if (td->remainder < count) {
1157 /* we have a short packet */
1158 td->short_pkt = 1;
1159 count = td->remainder;
1160 }
1161
1162 while (count > 0) {
1163 uint32_t temp;
1164
1165 usbd_get_page(td->pc, td->offset, &buf_res);
1166
1167 /* get correct length */
1168 if (buf_res.length > count) {
1169 buf_res.length = count;
1170 }
1171 /* check for unaligned memory address */
1172 if (USB_P2U(buf_res.buffer) & 3) {
1173 usbd_copy_out(td->pc, td->offset,
1174 sc->sc_bounce_buf, count);
1175
1176 temp = count & ~3;
1177
1178 if (temp) {
1179 /* transmit data 4 bytes at a time */
1180 bus_space_write_multi_4(sc->sc_io_tag,
1181 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1182 sc->sc_bounce_buf, temp / 4);
1183 }
1184 temp = count & 3;
1185 if (temp) {
1186 /* receive data 1 byte at a time */
1187 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1188 MUSB2_REG_EPFIFO(0),
1189 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1190 }
1191 /* update offset and remainder */
1192 td->offset += count;
1193 td->remainder -= count;
1194 break;
1195 }
1196 /* check if we can optimise */
1197 if (buf_res.length >= 4) {
1198 /* transmit data 4 bytes at a time */
1199 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1200 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1201 buf_res.length / 4);
1202
1203 temp = buf_res.length & ~3;
1204
1205 /* update counters */
1206 count -= temp;
1207 td->offset += temp;
1208 td->remainder -= temp;
1209 continue;
1210 }
1211 /* transmit data */
1212 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1213 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1214 buf_res.length);
1215
1216 /* update counters */
1217 count -= buf_res.length;
1218 td->offset += buf_res.length;
1219 td->remainder -= buf_res.length;
1220 }
1221
1222 /* Function address */
1223 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1224 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1225 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1226 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1227
1228 /* TX NAK timeout */
1229 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1230
1231 /* write command */
1232 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1233 MUSB2_MASK_CSR0L_TXPKTRDY);
1234
1235 td->transaction_started = 1;
1236
1237 return (1); /* not complete */
1238}
1239
1240static uint8_t
1241musbotg_dev_ctrl_status(struct musbotg_td *td)
1242{
1243 struct musbotg_softc *sc;
1244 uint8_t csr;
1245
1246 /* get pointer to softc */
1247 sc = MUSBOTG_PC2SC(td->pc);
1248
1249 /* select endpoint 0 */
1250 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1251
1252 if (sc->sc_ep0_busy) {
1253 sc->sc_ep0_busy = 0;
1254 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1255 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1256 sc->sc_ep0_cmd = 0;
1257 }
1258 /* read out FIFO status */
1259 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1260
1261 DPRINTFN(4, "csr=0x%02x\n", csr);
1262
1263 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1264 /* wait for interrupt */
1265 return (1); /* not complete */
1266 }
1267 if (sc->sc_dv_addr != 0xFF) {
1268 /* write function address */
1269 musbotg_set_address(sc, sc->sc_dv_addr);
1270 }
1271
1272 musbotg_channel_free(sc, td);
1273 return (0); /* complete */
1274}
1275
1276static uint8_t
1277musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1278{
1279 struct musbotg_softc *sc;
1280 uint8_t csr, csrh;
1281
1282 /* get pointer to softc */
1283 sc = MUSBOTG_PC2SC(td->pc);
1284
1285 if (td->channel == -1)
1286 td->channel = musbotg_channel_alloc(sc, td, 0);
1287
1288 /* EP0 is busy, wait */
1289 if (td->channel == -1)
1290 return (1);
1291
1292 DPRINTFN(1, "ep_no=%d\n", td->channel);
1293
1294 /* select endpoint 0 */
1295 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1296
1297 if (!td->transaction_started) {
1298 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1299 td->dev_addr);
1300
1301 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1302 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1303 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1304
1305 /* RX NAK timeout */
1306 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1307
1308 td->transaction_started = 1;
1309
1310 /* Disable PING */
1311 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1312 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1313 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1314
1315 /* write command */
1316 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1317 MUSB2_MASK_CSR0L_STATUSPKT |
1318 MUSB2_MASK_CSR0L_REQPKT);
1319
1320 return (1); /* Just started */
1321 }
1322
1323 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1324
1325 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1326
1327 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1328 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1329 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1330 musbotg_channel_free(sc, td);
1331 return (0); /* complete */
1332 }
1333
1334 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1335 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1336 MUSB2_MASK_CSR0L_REQPKT);
1337 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1338
1339 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1340 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1341 td->error = 1;
1342 }
1343
1344 /* Failed */
1345 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1346 MUSB2_MASK_CSR0L_ERROR))
1347 {
1348 /* Clear status bit */
1349 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1350 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1351 td->error = 1;
1352 }
1353
1354 if (td->error) {
1355 musbotg_channel_free(sc, td);
1356 return (0);
1357 }
1358
1359 return (1); /* Not ready yet */
1360}
1361
1362static uint8_t
1363musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1364{
1365 struct musbotg_softc *sc;
1366 uint8_t csr;
1367
1368 /* get pointer to softc */
1369 sc = MUSBOTG_PC2SC(td->pc);
1370
1371 if (td->channel == -1)
1372 td->channel = musbotg_channel_alloc(sc, td, 1);
1373
1374 /* EP0 is busy, wait */
1375 if (td->channel == -1)
1376 return (1);
1377
1378 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1379 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1380
1381 /* select endpoint 0 */
1382 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1383
1384 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1385 DPRINTFN(4, "csr=0x%02x\n", csr);
1386
1387 /* Not yet */
1388 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1389 return (1);
1390
1391 /* Failed */
1392 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1393 MUSB2_MASK_CSR0L_ERROR))
1394 {
1395 /* Clear status bit */
1396 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1397 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1398 td->error = 1;
1399 musbotg_channel_free(sc, td);
1400 return (0); /* complete */
1401 }
1402
1403 if (td->transaction_started) {
1404 musbotg_channel_free(sc, td);
1405 return (0); /* complete */
1406 }
1407
1408 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1409
1410 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1411 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1412 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1413 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1414
1415 /* TX NAK timeout */
1416 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1417
1418 td->transaction_started = 1;
1419
1420 /* write command */
1421 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1422 MUSB2_MASK_CSR0L_STATUSPKT |
1423 MUSB2_MASK_CSR0L_TXPKTRDY);
1424
1425 return (1); /* wait for interrupt */
1426}
1427
1428static uint8_t
1429musbotg_dev_data_rx(struct musbotg_td *td)
1430{
1431 struct usb_page_search buf_res;
1432 struct musbotg_softc *sc;
1433 uint16_t count;
1434 uint8_t csr;
1435 uint8_t to;
1436 uint8_t got_short;
1437
1438 to = 8; /* don't loop forever! */
1439 got_short = 0;
1440
1441 /* get pointer to softc */
1442 sc = MUSBOTG_PC2SC(td->pc);
1443
1444 if (td->channel == -1)
1445 td->channel = musbotg_channel_alloc(sc, td, 0);
1446
1447 /* EP0 is busy, wait */
1448 if (td->channel == -1)
1449 return (1);
1450
1451 /* select endpoint */
1452 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1453
1454repeat:
1455 /* read out FIFO status */
1456 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1457
1458 DPRINTFN(4, "csr=0x%02x\n", csr);
1459
1460 /* clear overrun */
1461 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1462 /* make sure we don't clear "RXPKTRDY" */
1463 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1464 MUSB2_MASK_CSRL_RXPKTRDY);
1465 }
1466
1467 /* check status */
1468 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1469 return (1); /* not complete */
1470
1471 /* get the packet byte count */
1472 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1473
1474 DPRINTFN(4, "count=0x%04x\n", count);
1475
1476 /*
1477 * Check for short or invalid packet:
1478 */
1479 if (count != td->max_frame_size) {
1480 if (count < td->max_frame_size) {
1481 /* we have a short packet */
1482 td->short_pkt = 1;
1483 got_short = 1;
1484 } else {
1485 /* invalid USB packet */
1486 td->error = 1;
1487 musbotg_channel_free(sc, td);
1488 return (0); /* we are complete */
1489 }
1490 }
1491 /* verify the packet byte count */
1492 if (count > td->remainder) {
1493 /* invalid USB packet */
1494 td->error = 1;
1495 musbotg_channel_free(sc, td);
1496 return (0); /* we are complete */
1497 }
1498 while (count > 0) {
1499 uint32_t temp;
1500
1501 usbd_get_page(td->pc, td->offset, &buf_res);
1502
1503 /* get correct length */
1504 if (buf_res.length > count) {
1505 buf_res.length = count;
1506 }
1507 /* check for unaligned memory address */
1508 if (USB_P2U(buf_res.buffer) & 3) {
1509 temp = count & ~3;
1510
1511 if (temp) {
1512 /* receive data 4 bytes at a time */
1513 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1514 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1515 temp / 4);
1516 }
1517 temp = count & 3;
1518 if (temp) {
1519 /* receive data 1 byte at a time */
1520 bus_space_read_multi_1(sc->sc_io_tag,
1521 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1522 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1523 }
1524 usbd_copy_in(td->pc, td->offset,
1525 sc->sc_bounce_buf, count);
1526
1527 /* update offset and remainder */
1528 td->offset += count;
1529 td->remainder -= count;
1530 break;
1531 }
1532 /* check if we can optimise */
1533 if (buf_res.length >= 4) {
1534 /* receive data 4 bytes at a time */
1535 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1536 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1537 buf_res.length / 4);
1538
1539 temp = buf_res.length & ~3;
1540
1541 /* update counters */
1542 count -= temp;
1543 td->offset += temp;
1544 td->remainder -= temp;
1545 continue;
1546 }
1547 /* receive data */
1548 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1549 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1550 buf_res.length);
1551
1552 /* update counters */
1553 count -= buf_res.length;
1554 td->offset += buf_res.length;
1555 td->remainder -= buf_res.length;
1556 }
1557
1558 /* clear status bits */
1559 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1560
1561 /* check if we are complete */
1562 if ((td->remainder == 0) || got_short) {
1563 if (td->short_pkt) {
1564 /* we are complete */
1565 musbotg_channel_free(sc, td);
1566 return (0);
1567 }
1568 /* else need to receive a zero length packet */
1569 }
1570 if (--to) {
1571 goto repeat;
1572 }
1573 return (1); /* not complete */
1574}
1575
1576static uint8_t
1577musbotg_dev_data_tx(struct musbotg_td *td)
1578{
1579 struct usb_page_search buf_res;
1580 struct musbotg_softc *sc;
1581 uint16_t count;
1582 uint8_t csr;
1583 uint8_t to;
1584
1585 to = 8; /* don't loop forever! */
1586
1587 /* get pointer to softc */
1588 sc = MUSBOTG_PC2SC(td->pc);
1589
1590 if (td->channel == -1)
1591 td->channel = musbotg_channel_alloc(sc, td, 1);
1592
1593 /* EP0 is busy, wait */
1594 if (td->channel == -1)
1595 return (1);
1596
1597 /* select endpoint */
1598 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1599
1600repeat:
1601
1602 /* read out FIFO status */
1603 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1604
1605 DPRINTFN(4, "csr=0x%02x\n", csr);
1606
1607 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1608 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1609 /* clear status bits */
1610 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1611 }
1612 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1613 return (1); /* not complete */
1614 }
1615 /* check for short packet */
1616 count = td->max_frame_size;
1617 if (td->remainder < count) {
1618 /* we have a short packet */
1619 td->short_pkt = 1;
1620 count = td->remainder;
1621 }
1622 while (count > 0) {
1623 uint32_t temp;
1624
1625 usbd_get_page(td->pc, td->offset, &buf_res);
1626
1627 /* get correct length */
1628 if (buf_res.length > count) {
1629 buf_res.length = count;
1630 }
1631 /* check for unaligned memory address */
1632 if (USB_P2U(buf_res.buffer) & 3) {
1633 usbd_copy_out(td->pc, td->offset,
1634 sc->sc_bounce_buf, count);
1635
1636 temp = count & ~3;
1637
1638 if (temp) {
1639 /* transmit data 4 bytes at a time */
1640 bus_space_write_multi_4(sc->sc_io_tag,
1641 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1642 sc->sc_bounce_buf, temp / 4);
1643 }
1644 temp = count & 3;
1645 if (temp) {
1646 /* receive data 1 byte at a time */
1647 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1648 MUSB2_REG_EPFIFO(td->channel),
1649 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1650 }
1651 /* update offset and remainder */
1652 td->offset += count;
1653 td->remainder -= count;
1654 break;
1655 }
1656 /* check if we can optimise */
1657 if (buf_res.length >= 4) {
1658 /* transmit data 4 bytes at a time */
1659 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1660 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1661 buf_res.length / 4);
1662
1663 temp = buf_res.length & ~3;
1664
1665 /* update counters */
1666 count -= temp;
1667 td->offset += temp;
1668 td->remainder -= temp;
1669 continue;
1670 }
1671 /* transmit data */
1672 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1673 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1674 buf_res.length);
1675
1676 /* update counters */
1677 count -= buf_res.length;
1678 td->offset += buf_res.length;
1679 td->remainder -= buf_res.length;
1680 }
1681
1682 /* Max packet size */
1683 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1684
1685 /* write command */
1686 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1687 MUSB2_MASK_CSRL_TXPKTRDY);
1688
1689 /* check remainder */
1690 if (td->remainder == 0) {
1691 if (td->short_pkt) {
1692 musbotg_channel_free(sc, td);
1693 return (0); /* complete */
1694 }
1695 /* else we need to transmit a short packet */
1696 }
1697 if (--to) {
1698 goto repeat;
1699 }
1700 return (1); /* not complete */
1701}
1702
1703static uint8_t
1704musbotg_host_data_rx(struct musbotg_td *td)
1705{
1706 struct usb_page_search buf_res;
1707 struct musbotg_softc *sc;
1708 uint16_t count;
1709 uint8_t csr, csrh;
1710 uint8_t to;
1711 uint8_t got_short;
1712
1713 /* get pointer to softc */
1714 sc = MUSBOTG_PC2SC(td->pc);
1715
1716 if (td->channel == -1)
1717 td->channel = musbotg_channel_alloc(sc, td, 0);
1718
1719 /* No free EPs */
1720 if (td->channel == -1)
1721 return (1);
1722
1723 DPRINTFN(1, "ep_no=%d\n", td->channel);
1724
1725 to = 8; /* don't loop forever! */
1726 got_short = 0;
1727
1728 /* select endpoint */
1729 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1730
1731repeat:
1732 /* read out FIFO status */
1733 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1734 DPRINTFN(4, "csr=0x%02x\n", csr);
1735
1736 if (!td->transaction_started) {
1737 /* Function address */
1738 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1739 td->dev_addr);
1740
1741 /* SPLIT transaction */
1742 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1743 td->haddr);
1744 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1745 td->hport);
1746
1747 /* RX NAK timeout */
1748 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1749 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1750 else
1751 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1752
1753 /* Protocol, speed, device endpoint */
1754 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1755
1756 /* Max packet size */
1757 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1758
1759 /* Data Toggle */
1760 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1761 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1762
1763 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1764 if (td->toggle)
1765 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1766 else
1767 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1768
1769 /* Set data toggle */
1770 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1771
1772 /* write command */
1773 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1774 MUSB2_MASK_CSRL_RXREQPKT);
1775
1776 td->transaction_started = 1;
1777 return (1);
1778 }
1779
1780 /* clear NAK timeout */
1781 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1782 DPRINTFN(4, "NAK Timeout\n");
1783 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1784 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1785 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1786
1787 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1788 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1789 }
1790
1791 td->error = 1;
1792 }
1793
1794 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1795 DPRINTFN(4, "RXERROR\n");
1796 td->error = 1;
1797 }
1798
1799 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1800 DPRINTFN(4, "RXSTALL\n");
1801 td->error = 1;
1802 }
1803
1804 if (td->error) {
1805 musbotg_channel_free(sc, td);
1806 return (0); /* we are complete */
1807 }
1808
1809 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1810 /* No data available yet */
1811 return (1);
1812 }
1813
1814 td->toggle ^= 1;
1815 /* get the packet byte count */
1816 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1817 DPRINTFN(4, "count=0x%04x\n", count);
1818
1819 /*
1820 * Check for short or invalid packet:
1821 */
1822 if (count != td->max_frame_size) {
1823 if (count < td->max_frame_size) {
1824 /* we have a short packet */
1825 td->short_pkt = 1;
1826 got_short = 1;
1827 } else {
1828 /* invalid USB packet */
1829 td->error = 1;
1830 musbotg_channel_free(sc, td);
1831 return (0); /* we are complete */
1832 }
1833 }
1834
1835 /* verify the packet byte count */
1836 if (count > td->remainder) {
1837 /* invalid USB packet */
1838 td->error = 1;
1839 musbotg_channel_free(sc, td);
1840 return (0); /* we are complete */
1841 }
1842
1843 while (count > 0) {
1844 uint32_t temp;
1845
1846 usbd_get_page(td->pc, td->offset, &buf_res);
1847
1848 /* get correct length */
1849 if (buf_res.length > count) {
1850 buf_res.length = count;
1851 }
1852 /* check for unaligned memory address */
1853 if (USB_P2U(buf_res.buffer) & 3) {
1854 temp = count & ~3;
1855
1856 if (temp) {
1857 /* receive data 4 bytes at a time */
1858 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1859 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1860 temp / 4);
1861 }
1862 temp = count & 3;
1863 if (temp) {
1864 /* receive data 1 byte at a time */
1865 bus_space_read_multi_1(sc->sc_io_tag,
1866 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1867 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1868 }
1869 usbd_copy_in(td->pc, td->offset,
1870 sc->sc_bounce_buf, count);
1871
1872 /* update offset and remainder */
1873 td->offset += count;
1874 td->remainder -= count;
1875 break;
1876 }
1877 /* check if we can optimise */
1878 if (buf_res.length >= 4) {
1879 /* receive data 4 bytes at a time */
1880 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1881 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1882 buf_res.length / 4);
1883
1884 temp = buf_res.length & ~3;
1885
1886 /* update counters */
1887 count -= temp;
1888 td->offset += temp;
1889 td->remainder -= temp;
1890 continue;
1891 }
1892 /* receive data */
1893 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1894 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1895 buf_res.length);
1896
1897 /* update counters */
1898 count -= buf_res.length;
1899 td->offset += buf_res.length;
1900 td->remainder -= buf_res.length;
1901 }
1902
1903 /* clear status bits */
1904 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1905
1906 /* check if we are complete */
1907 if ((td->remainder == 0) || got_short) {
1908 if (td->short_pkt) {
1909 /* we are complete */
1910 musbotg_channel_free(sc, td);
1911 return (0);
1912 }
1913 /* else need to receive a zero length packet */
1914 }
1915
1916 /* Reset transaction state and restart */
1917 td->transaction_started = 0;
1918
1919 if (--to)
1920 goto repeat;
1921
1922 return (1); /* not complete */
1923}
1924
1925static uint8_t
1926musbotg_host_data_tx(struct musbotg_td *td)
1927{
1928 struct usb_page_search buf_res;
1929 struct musbotg_softc *sc;
1930 uint16_t count;
1931 uint8_t csr, csrh;
1932
1933 /* get pointer to softc */
1934 sc = MUSBOTG_PC2SC(td->pc);
1935
1936 if (td->channel == -1)
1937 td->channel = musbotg_channel_alloc(sc, td, 1);
1938
1939 /* No free EPs */
1940 if (td->channel == -1)
1941 return (1);
1942
1943 DPRINTFN(1, "ep_no=%d\n", td->channel);
1944
1945 /* select endpoint */
1946 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1947
1948 /* read out FIFO status */
1949 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1950 DPRINTFN(4, "csr=0x%02x\n", csr);
1951
1952 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1953 MUSB2_MASK_CSRL_TXERROR)) {
1954 /* clear status bits */
1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1956 td->error = 1;
1957 musbotg_channel_free(sc, td);
1958 return (0); /* complete */
1959 }
1960
1961 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1962 /*
1963 * Flush TX FIFO before clearing NAK TO
1964 */
1965 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1966 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1967 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1968 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1969 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1970 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1971 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1972 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1973 }
1974 }
1975
1976 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1977 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1978
1979 td->error = 1;
1980 musbotg_channel_free(sc, td);
1981 return (0); /* complete */
1982 }
1983
1984 /*
1985 * Wait while FIFO is empty.
1986 * Do not flush it because it will cause transactions
1987 * with size more then packet size. It might upset
1988 * some devices
1989 */
1990 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1991 return (1);
1992
1993 /* Packet still being processed */
1994 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1995 return (1);
1996
1997 if (td->transaction_started) {
1998 /* check remainder */
1999 if (td->remainder == 0) {
2000 if (td->short_pkt) {
2001 musbotg_channel_free(sc, td);
2002 return (0); /* complete */
2003 }
2004 /* else we need to transmit a short packet */
2005 }
2006
2007 /* We're not complete - more transactions required */
2008 td->transaction_started = 0;
2009 }
2010
2011 /* check for short packet */
2012 count = td->max_frame_size;
2013 if (td->remainder < count) {
2014 /* we have a short packet */
2015 td->short_pkt = 1;
2016 count = td->remainder;
2017 }
2018
2019 while (count > 0) {
2020 uint32_t temp;
2021
2022 usbd_get_page(td->pc, td->offset, &buf_res);
2023
2024 /* get correct length */
2025 if (buf_res.length > count) {
2026 buf_res.length = count;
2027 }
2028 /* check for unaligned memory address */
2029 if (USB_P2U(buf_res.buffer) & 3) {
2030 usbd_copy_out(td->pc, td->offset,
2031 sc->sc_bounce_buf, count);
2032
2033 temp = count & ~3;
2034
2035 if (temp) {
2036 /* transmit data 4 bytes at a time */
2037 bus_space_write_multi_4(sc->sc_io_tag,
2038 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2039 sc->sc_bounce_buf, temp / 4);
2040 }
2041 temp = count & 3;
2042 if (temp) {
2043 /* receive data 1 byte at a time */
2044 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2045 MUSB2_REG_EPFIFO(td->channel),
2046 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2047 }
2048 /* update offset and remainder */
2049 td->offset += count;
2050 td->remainder -= count;
2051 break;
2052 }
2053 /* check if we can optimise */
2054 if (buf_res.length >= 4) {
2055 /* transmit data 4 bytes at a time */
2056 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2057 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2058 buf_res.length / 4);
2059
2060 temp = buf_res.length & ~3;
2061
2062 /* update counters */
2063 count -= temp;
2064 td->offset += temp;
2065 td->remainder -= temp;
2066 continue;
2067 }
2068 /* transmit data */
2069 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2070 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2071 buf_res.length);
2072
2073 /* update counters */
2074 count -= buf_res.length;
2075 td->offset += buf_res.length;
2076 td->remainder -= buf_res.length;
2077 }
2078
2079 /* Function address */
2080 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2081 td->dev_addr);
2082
2083 /* SPLIT transaction */
2084 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2085 td->haddr);
2086 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2087 td->hport);
2088
2089 /* TX NAK timeout */
2090 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2091 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2092 else
2093 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2094
2095 /* Protocol, speed, device endpoint */
2096 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2097
2098 /* Max packet size */
2099 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2100
2101 if (!td->transaction_started) {
2102 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2103 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2104
2105 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2106 if (td->toggle)
2107 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2108 else
2109 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2110
2111 /* Set data toggle */
2112 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2113 }
2114
2115 /* write command */
2116 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2117 MUSB2_MASK_CSRL_TXPKTRDY);
2118
2119 /* Update Data Toggle */
2120 td->toggle ^= 1;
2121 td->transaction_started = 1;
2122
2123 return (1); /* not complete */
2124}
2125
2126static uint8_t
2127musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2128{
2129 struct musbotg_softc *sc;
2130 struct musbotg_td *td;
2131
2132 DPRINTFN(8, "\n");
2133 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2134
2135 td = xfer->td_transfer_cache;
2136 while (1) {
2137 if ((td->func) (td)) {
2138 /* operation in progress */
2139 break;
2140 }
2141
2142 if (((void *)td) == xfer->td_transfer_last) {
2143 goto done;
2144 }
2145 if (td->error) {
2146 goto done;
2147 } else if (td->remainder > 0) {
2148 /*
2149 * We had a short transfer. If there is no alternate
2150 * next, stop processing !
2151 */
2152 if (!td->alt_next) {
2153 goto done;
2154 }
2155 }
2156 /*
2157 * Fetch the next transfer descriptor and transfer
2158 * some flags to the next transfer descriptor
2159 */
2160 td = td->obj_next;
2161 xfer->td_transfer_cache = td;
2162 }
2163
2164 return (1); /* not complete */
2165done:
2166 /* compute all actual lengths */
2167 musbotg_standard_done(xfer);
2168
2169 return (0); /* complete */
2170}
2171
2172static void
2173musbotg_interrupt_poll(struct musbotg_softc *sc)
2174{
2175 struct usb_xfer *xfer;
2176
2177repeat:
2178 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2179 if (!musbotg_xfer_do_fifo(xfer)) {
2180 /* queue has been modified */
2181 goto repeat;
2182 }
2183 }
2184}
2185
2186void
2187musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2188{
2189 DPRINTFN(4, "vbus = %u\n", is_on);
2190
2191 USB_BUS_LOCK(&sc->sc_bus);
2192 if (is_on) {
2193 if (!sc->sc_flags.status_vbus) {
2194 sc->sc_flags.status_vbus = 1;
2195
2196 /* complete root HUB interrupt endpoint */
2197 musbotg_root_intr(sc);
2198 }
2199 } else {
2200 if (sc->sc_flags.status_vbus) {
2201 sc->sc_flags.status_vbus = 0;
2202 sc->sc_flags.status_bus_reset = 0;
2203 sc->sc_flags.status_suspend = 0;
2204 sc->sc_flags.change_suspend = 0;
2205 sc->sc_flags.change_connect = 1;
2206
2207 /* complete root HUB interrupt endpoint */
2208 musbotg_root_intr(sc);
2209 }
2210 }
2211
2212 USB_BUS_UNLOCK(&sc->sc_bus);
2213}
2214
2215void
2216musbotg_connect_interrupt(struct musbotg_softc *sc)
2217{
2218 USB_BUS_LOCK(&sc->sc_bus);
2219 sc->sc_flags.change_connect = 1;
2220
2221 /* complete root HUB interrupt endpoint */
2222 musbotg_root_intr(sc);
2223 USB_BUS_UNLOCK(&sc->sc_bus);
2224}
2225
2226void
2227musbotg_interrupt(struct musbotg_softc *sc,
2228 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2229{
2230 uint16_t rx_status;
2231 uint16_t tx_status;
2232 uint8_t usb_status;
2233 uint8_t temp;
2234 uint8_t to = 2;
2235
2236 USB_BUS_LOCK(&sc->sc_bus);
2237
2238repeat:
2239
2240 /* read all interrupt registers */
2241 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2242
2243 /* read all FIFO interrupts */
2244 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2245 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2246 rx_status |= rxstat;
2247 tx_status |= txstat;
2248 usb_status |= stat;
2249
2250 /* Clear platform flags after first time */
2251 rxstat = 0;
2252 txstat = 0;
2253 stat = 0;
2254
2255 /* check for any bus state change interrupts */
2256
2257 if (usb_status & (MUSB2_MASK_IRESET |
2258 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2259 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC |
2260 MUSB2_MASK_IVBUSERR)) {
2261 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2262
2263 if (usb_status & MUSB2_MASK_IRESET) {
2264 /* set correct state */
2265 sc->sc_flags.status_bus_reset = 1;
2266 sc->sc_flags.status_suspend = 0;
2267 sc->sc_flags.change_suspend = 0;
2268 sc->sc_flags.change_connect = 1;
2269
2270 /* determine line speed */
2271 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2272 if (temp & MUSB2_MASK_HSMODE)
2273 sc->sc_flags.status_high_speed = 1;
2274 else
2275 sc->sc_flags.status_high_speed = 0;
2276
2277 /*
2278 * After reset all interrupts are on and we need to
2279 * turn them off!
2280 */
2281 temp = MUSB2_MASK_IRESET;
2282 /* disable resume interrupt */
2283 temp &= ~MUSB2_MASK_IRESUME;
2284 /* enable suspend interrupt */
2285 temp |= MUSB2_MASK_ISUSP;
2286 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2287 /* disable TX and RX interrupts */
2288 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2289 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2290 }
2291 /*
2292 * If RXRSM and RXSUSP is set at the same time we interpret
2293 * that like RESUME. Resume is set when there is at least 3
2294 * milliseconds of inactivity on the USB BUS.
2295 */
2296 if (usb_status & MUSB2_MASK_IRESUME) {
2297 if (sc->sc_flags.status_suspend) {
2298 sc->sc_flags.status_suspend = 0;
2299 sc->sc_flags.change_suspend = 1;
2300
2301 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2302 /* disable resume interrupt */
2303 temp &= ~MUSB2_MASK_IRESUME;
2304 /* enable suspend interrupt */
2305 temp |= MUSB2_MASK_ISUSP;
2306 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2307 }
2308 } else if (usb_status & MUSB2_MASK_ISUSP) {
2309 if (!sc->sc_flags.status_suspend) {
2310 sc->sc_flags.status_suspend = 1;
2311 sc->sc_flags.change_suspend = 1;
2312
2313 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2314 /* disable suspend interrupt */
2315 temp &= ~MUSB2_MASK_ISUSP;
2316 /* enable resume interrupt */
2317 temp |= MUSB2_MASK_IRESUME;
2318 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2319 }
2320 }
2321 if (usb_status &
2322 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2323 sc->sc_flags.change_connect = 1;
2324
2325 /*
2326 * Host Mode: There is no IRESET so assume bus is
2327 * always in reset state once device is connected.
2328 */
2329 if (sc->sc_mode == MUSB2_HOST_MODE) {
2330 /* check for VBUS error in USB host mode */
2331 if (usb_status & MUSB2_MASK_IVBUSERR) {
2332 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2333 temp |= MUSB2_MASK_SESS;
2334 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2335 }
2336 if (usb_status & MUSB2_MASK_ICONN)
2337 sc->sc_flags.status_bus_reset = 1;
2338 if (usb_status & MUSB2_MASK_IDISC)
2339 sc->sc_flags.status_bus_reset = 0;
2340 }
2341
2342 /* complete root HUB interrupt endpoint */
2343 musbotg_root_intr(sc);
2344 }
2345 /* check for any endpoint interrupts */
2346
2347 if (rx_status || tx_status) {
2348 DPRINTFN(4, "real endpoint interrupt "
2349 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2350 }
2351 /* poll one time regardless of FIFO status */
2352
2353 musbotg_interrupt_poll(sc);
2354
2355 if (--to)
2356 goto repeat;
2357
2358 USB_BUS_UNLOCK(&sc->sc_bus);
2359}
2360
2361static void
2362musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2363{
2364 struct musbotg_td *td;
2365
2366 /* get current Transfer Descriptor */
2367 td = temp->td_next;
2368 temp->td = td;
2369
2370 /* prepare for next TD */
2371 temp->td_next = td->obj_next;
2372
2373 /* fill out the Transfer Descriptor */
2374 td->func = temp->func;
2375 td->pc = temp->pc;
2376 td->offset = temp->offset;
2377 td->remainder = temp->len;
2378 td->error = 0;
2379 td->transaction_started = 0;
2380 td->did_stall = temp->did_stall;
2381 td->short_pkt = temp->short_pkt;
2382 td->alt_next = temp->setup_alt_next;
2383 td->channel = temp->channel;
2384 td->dev_addr = temp->dev_addr;
2385 td->haddr = temp->haddr;
2386 td->hport = temp->hport;
2387 td->transfer_type = temp->transfer_type;
2388}
2389
2390static void
2391musbotg_setup_standard_chain(struct usb_xfer *xfer)
2392{
2393 struct musbotg_std_temp temp;
2394 struct musbotg_softc *sc;
2395 struct musbotg_td *td;
2396 uint32_t x;
2397 uint8_t ep_no;
2398 uint8_t xfer_type;
2399 enum usb_dev_speed speed;
2400 int tx;
2401 int dev_addr;
2402
2403 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2404 xfer->address, UE_GET_ADDR(xfer->endpointno),
2405 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2406
2407 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2408 ep_no = (xfer->endpointno & UE_ADDR);
2409
2410 temp.max_frame_size = xfer->max_frame_size;
2411
2412 td = xfer->td_start[0];
2413 xfer->td_transfer_first = td;
2414 xfer->td_transfer_cache = td;
2415
2416 /* setup temp */
2417 dev_addr = xfer->address;
2418
2419 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2420
2421 temp.pc = NULL;
2422 temp.td = NULL;
2423 temp.td_next = xfer->td_start[0];
2424 temp.offset = 0;
2425 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
2426 xfer->flags_int.isochronous_xfr;
2427 temp.did_stall = !xfer->flags_int.control_stall;
2428 temp.channel = -1;
2429 temp.dev_addr = dev_addr;
2430 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2431 temp.hport = xfer->xroot->udev->hs_port_no;
2432
2433 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2434 speed = usbd_get_speed(xfer->xroot->udev);
2435
2436 switch (speed) {
2437 case USB_SPEED_LOW:
2438 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2439 break;
2440 case USB_SPEED_FULL:
2441 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2442 break;
2443 case USB_SPEED_HIGH:
2444 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2445 break;
2446 default:
2447 temp.transfer_type = 0;
2448 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2449 break;
2450 }
2451
2452 switch (xfer_type) {
2453 case UE_CONTROL:
2454 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2455 break;
2456 case UE_ISOCHRONOUS:
2457 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2458 break;
2459 case UE_BULK:
2460 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2461 break;
2462 case UE_INTERRUPT:
2463 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2464 break;
2465 default:
2466 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2467 xfer_type);
2468 break;
2469 }
2470
2471 temp.transfer_type |= ep_no;
2472 td->toggle = xfer->endpoint->toggle_next;
2473 }
2474
2475 /* check if we should prepend a setup message */
2476
2477 if (xfer->flags_int.control_xfr) {
2478 if (xfer->flags_int.control_hdr) {
2479 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2480 temp.func = &musbotg_dev_ctrl_setup_rx;
2481 else
2482 temp.func = &musbotg_host_ctrl_setup_tx;
2483
2484 temp.len = xfer->frlengths[0];
2485 temp.pc = xfer->frbuffers + 0;
2486 temp.short_pkt = temp.len ? 1 : 0;
2487
2488 musbotg_setup_standard_chain_sub(&temp);
2489 }
2490 x = 1;
2491 } else {
2492 x = 0;
2493 }
2494
2495 tx = 0;
2496
2497 if (x != xfer->nframes) {
2498 if (xfer->endpointno & UE_DIR_IN)
2499 tx = 1;
2500
2501 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2502 tx = !tx;
2503
2504 if (tx) {
2505 if (xfer->flags_int.control_xfr)
2506 temp.func = &musbotg_host_ctrl_data_tx;
2507 else
2508 temp.func = &musbotg_host_data_tx;
2509 } else {
2510 if (xfer->flags_int.control_xfr)
2511 temp.func = &musbotg_host_ctrl_data_rx;
2512 else
2513 temp.func = &musbotg_host_data_rx;
2514 }
2515
2516 } else {
2517 if (tx) {
2518 if (xfer->flags_int.control_xfr)
2519 temp.func = &musbotg_dev_ctrl_data_tx;
2520 else
2521 temp.func = &musbotg_dev_data_tx;
2522 } else {
2523 if (xfer->flags_int.control_xfr)
2524 temp.func = &musbotg_dev_ctrl_data_rx;
2525 else
2526 temp.func = &musbotg_dev_data_rx;
2527 }
2528 }
2529
2530 /* setup "pc" pointer */
2531 temp.pc = xfer->frbuffers + x;
2532 }
2533 while (x != xfer->nframes) {
2534 /* DATA0 / DATA1 message */
2535
2536 temp.len = xfer->frlengths[x];
2537
2538 x++;
2539
2540 if (x == xfer->nframes) {
2541 if (xfer->flags_int.control_xfr) {
2542 if (xfer->flags_int.control_act) {
2543 temp.setup_alt_next = 0;
2544 }
2545 } else {
2546 temp.setup_alt_next = 0;
2547 }
2548 }
2549 if (temp.len == 0) {
2550 /* make sure that we send an USB packet */
2551
2552 temp.short_pkt = 0;
2553
2554 } else {
2555 if (xfer->flags_int.isochronous_xfr) {
2556 /* isochronous data transfer */
2557 /* don't force short */
2558 temp.short_pkt = 1;
2559 } else {
2560 /* regular data transfer */
2561 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2562 }
2563 }
2564
2565 musbotg_setup_standard_chain_sub(&temp);
2566
2567 if (xfer->flags_int.isochronous_xfr) {
2568 temp.offset += temp.len;
2569 } else {
2570 /* get next Page Cache pointer */
2571 temp.pc = xfer->frbuffers + x;
2572 }
2573 }
2574
2575 /* check for control transfer */
2576 if (xfer->flags_int.control_xfr) {
2577 /* always setup a valid "pc" pointer for status and sync */
2578 temp.pc = xfer->frbuffers + 0;
2579 temp.len = 0;
2580 temp.short_pkt = 0;
2581 temp.setup_alt_next = 0;
2582
2583 /* check if we should append a status stage */
2584 if (!xfer->flags_int.control_act) {
2585 /*
2586 * Send a DATA1 message and invert the current
2587 * endpoint direction.
2588 */
2589 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2590 temp.func = &musbotg_dev_ctrl_status;
2591 else {
2592 if (xfer->endpointno & UE_DIR_IN)
2593 temp.func = musbotg_host_ctrl_status_tx;
2594 else
2595 temp.func = musbotg_host_ctrl_status_rx;
2596 }
2597 musbotg_setup_standard_chain_sub(&temp);
2598 }
2599 }
2600 /* must have at least one frame! */
2601 td = temp.td;
2602 xfer->td_transfer_last = td;
2603}
2604
2605static void
2606musbotg_timeout(void *arg)
2607{
2608 struct usb_xfer *xfer = arg;
2609
2610 DPRINTFN(1, "xfer=%p\n", xfer);
2611
2612 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2613
2614 /* transfer is transferred */
2615 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2616}
2617
2618static void
2619musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2620{
2621 uint16_t temp;
2622
2623 /*
2624 * Only enable the endpoint interrupt when we are
2625 * actually waiting for data, hence we are dealing
2626 * with level triggered interrupts !
2627 */
2628 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2629
2630 if (channel == -1)
2631 return;
2632
2633 if (channel == 0) {
2634 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2635 if (on)
2636 temp |= MUSB2_MASK_EPINT(0);
2637 else
2638 temp &= ~MUSB2_MASK_EPINT(0);
2639
2640 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2641 } else {
2642 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2643 if (on)
2644 temp |= MUSB2_MASK_EPINT(channel);
2645 else
2646 temp &= ~MUSB2_MASK_EPINT(channel);
2647 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2648
2649 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2650 if (on)
2651 temp |= MUSB2_MASK_EPINT(channel);
2652 else
2653 temp &= ~MUSB2_MASK_EPINT(channel);
2654 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2655 }
2656
2657 if (sc->sc_ep_int_set)
2658 sc->sc_ep_int_set(sc, channel, on);
2659}
2660
2661static void
2662musbotg_start_standard_chain(struct usb_xfer *xfer)
2663{
2664 DPRINTFN(8, "\n");
2665
2666 /* poll one time */
2667 if (musbotg_xfer_do_fifo(xfer)) {
2668 DPRINTFN(14, "enabled interrupts on endpoint\n");
2669
2670 /* put transfer on interrupt queue */
2671 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2672
2673 /* start timeout, if any */
2674 if (xfer->timeout != 0) {
2675 usbd_transfer_timeout_ms(xfer,
2676 &musbotg_timeout, xfer->timeout);
2677 }
2678 }
2679}
2680
2681static void
2682musbotg_root_intr(struct musbotg_softc *sc)
2683{
2684 DPRINTFN(8, "\n");
2685
2686 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2687
2688 /* set port bit */
2689 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2690
2691 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2692 sizeof(sc->sc_hub_idata));
2693}
2694
2695static usb_error_t
2696musbotg_standard_done_sub(struct usb_xfer *xfer)
2697{
2698 struct musbotg_td *td;
2699 uint32_t len;
2700 uint8_t error;
2701
2702 DPRINTFN(8, "\n");
2703
2704 td = xfer->td_transfer_cache;
2705
2706 do {
2707 len = td->remainder;
2708
2709 xfer->endpoint->toggle_next = td->toggle;
2710
2711 if (xfer->aframes != xfer->nframes) {
2712 /*
2713 * Verify the length and subtract
2714 * the remainder from "frlengths[]":
2715 */
2716 if (len > xfer->frlengths[xfer->aframes]) {
2717 td->error = 1;
2718 } else {
2719 xfer->frlengths[xfer->aframes] -= len;
2720 }
2721 }
2722 /* Check for transfer error */
2723 if (td->error) {
2724 /* the transfer is finished */
2725 error = 1;
2726 td = NULL;
2727 break;
2728 }
2729 /* Check for short transfer */
2730 if (len > 0) {
2731 if (xfer->flags_int.short_frames_ok ||
2732 xfer->flags_int.isochronous_xfr) {
2733 /* follow alt next */
2734 if (td->alt_next) {
2735 td = td->obj_next;
2736 } else {
2737 td = NULL;
2738 }
2739 } else {
2740 /* the transfer is finished */
2741 td = NULL;
2742 }
2743 error = 0;
2744 break;
2745 }
2746 td = td->obj_next;
2747
2748 /* this USB frame is complete */
2749 error = 0;
2750 break;
2751
2752 } while (0);
2753
2754 /* update transfer cache */
2755
2756 xfer->td_transfer_cache = td;
2757
2758 return (error ?
2759 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2760}
2761
2762static void
2763musbotg_standard_done(struct usb_xfer *xfer)
2764{
2765 usb_error_t err = 0;
2766
2767 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2768 xfer, xfer->endpoint);
2769
2770 /* reset scanner */
2771
2772 xfer->td_transfer_cache = xfer->td_transfer_first;
2773
2774 if (xfer->flags_int.control_xfr) {
2775 if (xfer->flags_int.control_hdr) {
2776 err = musbotg_standard_done_sub(xfer);
2777 }
2778 xfer->aframes = 1;
2779
2780 if (xfer->td_transfer_cache == NULL) {
2781 goto done;
2782 }
2783 }
2784 while (xfer->aframes != xfer->nframes) {
2785 err = musbotg_standard_done_sub(xfer);
2786 xfer->aframes++;
2787
2788 if (xfer->td_transfer_cache == NULL) {
2789 goto done;
2790 }
2791 }
2792
2793 if (xfer->flags_int.control_xfr &&
2794 !xfer->flags_int.control_act) {
2795 err = musbotg_standard_done_sub(xfer);
2796 }
2797done:
2798 musbotg_device_done(xfer, err);
2799}
2800
2801/*------------------------------------------------------------------------*
2802 * musbotg_device_done
2803 *
2804 * NOTE: this function can be called more than one time on the
2805 * same USB transfer!
2806 *------------------------------------------------------------------------*/
2807static void
2808musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2809{
2810 struct musbotg_td *td;
2811 struct musbotg_softc *sc;
2812
2813 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2814
2815 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2816 xfer, xfer->endpoint, error);
2817
2818 DPRINTFN(14, "disabled interrupts on endpoint\n");
2819
2820 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2821 td = xfer->td_transfer_cache;
2822
2823 if (td && (td->channel != -1))
2824 musbotg_channel_free(sc, td);
2825
2826 /* dequeue transfer and start next transfer */
2827 usbd_transfer_done(xfer, error);
2828}
2829
2830static void
2831musbotg_xfer_stall(struct usb_xfer *xfer)
2832{
2833 musbotg_device_done(xfer, USB_ERR_STALLED);
2834}
2835
2836static void
2837musbotg_set_stall(struct usb_device *udev,
2838 struct usb_endpoint *ep, uint8_t *did_stall)
2839{
2840 struct musbotg_softc *sc;
2841 uint8_t ep_no;
2842
2843 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2844
2845 DPRINTFN(4, "endpoint=%p\n", ep);
2846
2847 /* set FORCESTALL */
2848 sc = MUSBOTG_BUS2SC(udev->bus);
2849
2850 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2851
2852 /* select endpoint */
2853 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2854
2855 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2856 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2857 MUSB2_MASK_CSRL_TXSENDSTALL);
2858 } else {
2859 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2860 MUSB2_MASK_CSRL_RXSENDSTALL);
2861 }
2862}
2863
2864static void
2865musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2866 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2867{
2868 uint16_t mps;
2869 uint16_t temp;
2870 uint8_t csr;
2871
2872 if (ep_type == UE_CONTROL) {
2873 /* clearing stall is not needed */
2874 return;
2875 }
2876 /* select endpoint */
2877 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2878
2879 /* compute max frame size */
2880 mps = wMaxPacket & 0x7FF;
2881 switch ((wMaxPacket >> 11) & 3) {
2882 case 1:
2883 mps *= 2;
2884 break;
2885 case 2:
2886 mps *= 3;
2887 break;
2888 default:
2889 break;
2890 }
2891
2892 if (ep_dir == UE_DIR_IN) {
2893 temp = 0;
2894
2895 /* Configure endpoint */
2896 switch (ep_type) {
2897 case UE_INTERRUPT:
2898 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2899 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2900 MUSB2_MASK_CSRH_TXMODE | temp);
2901 break;
2902 case UE_ISOCHRONOUS:
2903 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2904 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2905 MUSB2_MASK_CSRH_TXMODE |
2906 MUSB2_MASK_CSRH_TXISO | temp);
2907 break;
2908 case UE_BULK:
2909 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2910 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2911 MUSB2_MASK_CSRH_TXMODE | temp);
2912 break;
2913 default:
2914 break;
2915 }
2916
2917 /* Need to flush twice in case of double bufring */
2918 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2919 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2920 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2921 MUSB2_MASK_CSRL_TXFFLUSH);
2922 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2923 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2924 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2925 MUSB2_MASK_CSRL_TXFFLUSH);
2926 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2927 }
2928 }
2929 /* reset data toggle */
2930 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2931 MUSB2_MASK_CSRL_TXDT_CLR);
2932 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2933 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2934
2935 /* set double/single buffering */
2936 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2937 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2938 max_in_frame_size / 2)) {
2939 /* double buffer */
2940 temp &= ~(1 << ep_no);
2941 } else {
2942 /* single buffer */
2943 temp |= (1 << ep_no);
2944 }
2945 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2946
2947 /* clear sent stall */
2948 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2949 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2950 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2951 }
2952 } else {
2953 temp = 0;
2954
2955 /* Configure endpoint */
2956 switch (ep_type) {
2957 case UE_INTERRUPT:
2958 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2959 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2960 MUSB2_MASK_CSRH_RXNYET | temp);
2961 break;
2962 case UE_ISOCHRONOUS:
2963 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2964 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2965 MUSB2_MASK_CSRH_RXNYET |
2966 MUSB2_MASK_CSRH_RXISO | temp);
2967 break;
2968 case UE_BULK:
2969 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2970 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2971 break;
2972 default:
2973 break;
2974 }
2975
2976 /* Need to flush twice in case of double bufring */
2977 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2978 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2979 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2980 MUSB2_MASK_CSRL_RXFFLUSH);
2981 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2982 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2983 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2984 MUSB2_MASK_CSRL_RXFFLUSH);
2985 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2986 }
2987 }
2988 /* reset data toggle */
2989 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2990 MUSB2_MASK_CSRL_RXDT_CLR);
2991 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2992 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2993
2994 /* set double/single buffering */
2995 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
2996 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2997 max_out_frame_size / 2)) {
2998 /* double buffer */
2999 temp &= ~(1 << ep_no);
3000 } else {
3001 /* single buffer */
3002 temp |= (1 << ep_no);
3003 }
3004 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3005
3006 /* clear sent stall */
3007 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3008 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3009 }
3010 }
3011}
3012
3013static void
3014musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3015{
3016 struct musbotg_softc *sc;
3017 struct usb_endpoint_descriptor *ed;
3018
3019 DPRINTFN(4, "endpoint=%p\n", ep);
3020
3021 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3022
3023 /* check mode */
3024 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3025 /* not supported */
3026 return;
3027 }
3028 /* get softc */
3029 sc = MUSBOTG_BUS2SC(udev->bus);
3030
3031 /* get endpoint descriptor */
3032 ed = ep->edesc;
3033
3034 /* reset endpoint */
3035 musbotg_clear_stall_sub(sc,
3036 UGETW(ed->wMaxPacketSize),
3037 (ed->bEndpointAddress & UE_ADDR),
3038 (ed->bmAttributes & UE_XFERTYPE),
3039 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3040}
3041
3042usb_error_t
3043musbotg_init(struct musbotg_softc *sc)
3044{
3045 const struct musb_otg_ep_cfg *cfg;
3046 struct usb_hw_ep_profile *pf;
3047 int i;
3048 uint16_t offset;
3049 uint8_t nrx;
3050 uint8_t ntx;
3051 uint8_t temp;
3052 uint8_t fsize;
3053 uint8_t frx;
3054 uint8_t ftx;
3055 uint8_t dynfifo;
3056
3057 DPRINTFN(1, "start\n");
3058
3059 /* set up the bus structure */
3060 sc->sc_bus.usbrev = USB_REV_2_0;
3061 sc->sc_bus.methods = &musbotg_bus_methods;
3062
3063 /* Set a default endpoint configuration */
3064 if (sc->sc_ep_cfg == NULL)
3065 sc->sc_ep_cfg = musbotg_ep_default;
3066
3067 USB_BUS_LOCK(&sc->sc_bus);
3068
3069 /* turn on clocks */
3070
3071 if (sc->sc_clocks_on) {
3072 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3073 }
3074
3075 /* wait a little for things to stabilise */
3076 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3077
3078 /* disable all interrupts */
3079
3080 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3081 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3082
3083 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3084 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3085 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3086
3087 /* disable pullup */
3088
3089 musbotg_pull_common(sc, 0);
3090
3091 /* wait a little bit (10ms) */
3092 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3093
3094 /* disable double packet buffering */
3095 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3096 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3097
3098 /* enable HighSpeed and ISO Update flags */
3099
3100 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3101 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3102
3103 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3104 /* clear Session bit, if set */
3105 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3106 temp &= ~MUSB2_MASK_SESS;
3107 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3108 } else {
3109 /* Enter session for Host mode */
3110 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3111 temp |= MUSB2_MASK_SESS;
3112 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3113 }
3114
3115 /* wait a little for things to stabilise */
3116 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3117
3118 DPRINTF("DEVCTL=0x%02x\n", temp);
3119
3120 /* disable testmode */
3121
3122 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3123
3124 /* set default value */
3125
3126 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3127
3128 /* select endpoint index 0 */
3129
3130 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3131
3132 if (sc->sc_ep_max == 0) {
3133 /* read out number of endpoints */
3134
3135 nrx =
3136 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3137
3138 ntx =
3139 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3140
3141 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3142 } else {
3143 nrx = ntx = sc->sc_ep_max;
3144 }
3145
3146 /* these numbers exclude the control endpoint */
3147
3148 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3149
3150 if (sc->sc_ep_max == 0) {
3151 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3152 }
3153 /* read out configuration data */
3154
3155 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3156
3157 DPRINTFN(2, "Config Data: 0x%02x\n",
3158 sc->sc_conf_data);
3159
3160 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3161
3162 if (dynfifo) {
3163 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3164 "assuming 16Kbytes of FIFO RAM\n");
3165 }
3166
3167 DPRINTFN(2, "HW version: 0x%04x\n",
3168 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3169
3170 /* initialise endpoint profiles */
3171
3172 offset = 0;
3173
3174 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3175 pf = sc->sc_hw_ep_profile + temp;
3176
3177 /* select endpoint */
3178 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3179
3180 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3181 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3182 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3183
3184 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3185 temp, ftx, frx, dynfifo);
3186
3187 if (dynfifo) {
3188 if (frx && (temp <= nrx)) {
3189 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) {
3190 cfg = &sc->sc_ep_cfg[i];
3191 if (temp <= cfg->ep_end) {
3192 frx = cfg->ep_fifosz_shift;
3193 MUSB2_WRITE_1(sc,
3194 MUSB2_REG_RXFIFOSZ,
3195 cfg->ep_fifosz_reg);
3196 break;
3197 }
3198 }
3199
3200 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3201 offset >> 3);
3202
3203 offset += (1 << frx);
3204 }
3205 if (ftx && (temp <= ntx)) {
3206 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) {
3207 cfg = &sc->sc_ep_cfg[i];
3208 if (temp <= cfg->ep_end) {
3209 ftx = cfg->ep_fifosz_shift;
3210 MUSB2_WRITE_1(sc,
3211 MUSB2_REG_TXFIFOSZ,
3212 cfg->ep_fifosz_reg);
3213 break;
3214 }
3215 }
3216
3217 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3218 offset >> 3);
3219
3220 offset += (1 << ftx);
3221 }
3222 }
3223
3224 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3225 pf->max_in_frame_size = 1 << ftx;
3226 pf->max_out_frame_size = 1 << frx;
3227 pf->is_simplex = 0; /* duplex */
3228 pf->support_multi_buffer = 1;
3229 pf->support_bulk = 1;
3230 pf->support_interrupt = 1;
3231 pf->support_isochronous = 1;
3232 pf->support_in = 1;
3233 pf->support_out = 1;
3234 } else if (frx && (temp <= nrx)) {
3235 pf->max_out_frame_size = 1 << frx;
3236 pf->max_in_frame_size = 0;
3237 pf->is_simplex = 1; /* simplex */
3238 pf->support_multi_buffer = 1;
3239 pf->support_bulk = 1;
3240 pf->support_interrupt = 1;
3241 pf->support_isochronous = 1;
3242 pf->support_out = 1;
3243 } else if (ftx && (temp <= ntx)) {
3244 pf->max_in_frame_size = 1 << ftx;
3245 pf->max_out_frame_size = 0;
3246 pf->is_simplex = 1; /* simplex */
3247 pf->support_multi_buffer = 1;
3248 pf->support_bulk = 1;
3249 pf->support_interrupt = 1;
3250 pf->support_isochronous = 1;
3251 pf->support_in = 1;
3252 }
3253 }
3254
3255 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3256
3257 /* turn on default interrupts */
3258
3259 if (sc->sc_mode == MUSB2_HOST_MODE)
3260 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3261 else
3262 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3263 MUSB2_MASK_IRESET);
3264
3265 musbotg_clocks_off(sc);
3266
3267 USB_BUS_UNLOCK(&sc->sc_bus);
3268
3269 /* catch any lost interrupts */
3270
3271 musbotg_do_poll(&sc->sc_bus);
3272
3273 return (0); /* success */
3274}
3275
3276void
3277musbotg_uninit(struct musbotg_softc *sc)
3278{
3279 USB_BUS_LOCK(&sc->sc_bus);
3280
3281 /* disable all interrupts */
3282 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3283 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3284 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3285
3286 sc->sc_flags.port_powered = 0;
3287 sc->sc_flags.status_vbus = 0;
3288 sc->sc_flags.status_bus_reset = 0;
3289 sc->sc_flags.status_suspend = 0;
3290 sc->sc_flags.change_suspend = 0;
3291 sc->sc_flags.change_connect = 1;
3292
3293 musbotg_pull_down(sc);
3294 musbotg_clocks_off(sc);
3295 USB_BUS_UNLOCK(&sc->sc_bus);
3296}
3297
3298static void
3299musbotg_do_poll(struct usb_bus *bus)
3300{
3301 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3302
3303 USB_BUS_LOCK(&sc->sc_bus);
3304 musbotg_interrupt_poll(sc);
3305 USB_BUS_UNLOCK(&sc->sc_bus);
3306}
3307
3308/*------------------------------------------------------------------------*
3309 * musbotg bulk support
3310 *------------------------------------------------------------------------*/
3311static void
3312musbotg_device_bulk_open(struct usb_xfer *xfer)
3313{
3314 return;
3315}
3316
3317static void
3318musbotg_device_bulk_close(struct usb_xfer *xfer)
3319{
3320 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3321}
3322
3323static void
3324musbotg_device_bulk_enter(struct usb_xfer *xfer)
3325{
3326 return;
3327}
3328
3329static void
3330musbotg_device_bulk_start(struct usb_xfer *xfer)
3331{
3332 /* setup TDs */
3333 musbotg_setup_standard_chain(xfer);
3334 musbotg_start_standard_chain(xfer);
3335}
3336
3337static const struct usb_pipe_methods musbotg_device_bulk_methods =
3338{
3339 .open = musbotg_device_bulk_open,
3340 .close = musbotg_device_bulk_close,
3341 .enter = musbotg_device_bulk_enter,
3342 .start = musbotg_device_bulk_start,
3343};
3344
3345/*------------------------------------------------------------------------*
3346 * musbotg control support
3347 *------------------------------------------------------------------------*/
3348static void
3349musbotg_device_ctrl_open(struct usb_xfer *xfer)
3350{
3351 return;
3352}
3353
3354static void
3355musbotg_device_ctrl_close(struct usb_xfer *xfer)
3356{
3357 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3358}
3359
3360static void
3361musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3362{
3363 return;
3364}
3365
3366static void
3367musbotg_device_ctrl_start(struct usb_xfer *xfer)
3368{
3369 /* setup TDs */
3370 musbotg_setup_standard_chain(xfer);
3371 musbotg_start_standard_chain(xfer);
3372}
3373
3374static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3375{
3376 .open = musbotg_device_ctrl_open,
3377 .close = musbotg_device_ctrl_close,
3378 .enter = musbotg_device_ctrl_enter,
3379 .start = musbotg_device_ctrl_start,
3380};
3381
3382/*------------------------------------------------------------------------*
3383 * musbotg interrupt support
3384 *------------------------------------------------------------------------*/
3385static void
3386musbotg_device_intr_open(struct usb_xfer *xfer)
3387{
3388 return;
3389}
3390
3391static void
3392musbotg_device_intr_close(struct usb_xfer *xfer)
3393{
3394 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3395}
3396
3397static void
3398musbotg_device_intr_enter(struct usb_xfer *xfer)
3399{
3400 return;
3401}
3402
3403static void
3404musbotg_device_intr_start(struct usb_xfer *xfer)
3405{
3406 /* setup TDs */
3407 musbotg_setup_standard_chain(xfer);
3408 musbotg_start_standard_chain(xfer);
3409}
3410
3411static const struct usb_pipe_methods musbotg_device_intr_methods =
3412{
3413 .open = musbotg_device_intr_open,
3414 .close = musbotg_device_intr_close,
3415 .enter = musbotg_device_intr_enter,
3416 .start = musbotg_device_intr_start,
3417};
3418
3419/*------------------------------------------------------------------------*
3420 * musbotg full speed isochronous support
3421 *------------------------------------------------------------------------*/
3422static void
3423musbotg_device_isoc_open(struct usb_xfer *xfer)
3424{
3425 return;
3426}
3427
3428static void
3429musbotg_device_isoc_close(struct usb_xfer *xfer)
3430{
3431 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3432}
3433
3434static void
3435musbotg_device_isoc_enter(struct usb_xfer *xfer)
3436{
3437 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3438 uint32_t nframes;
3439
3440 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3441 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3442
3443 /* get the current frame index */
3444
3445 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3446
3447 if (usbd_xfer_get_isochronous_start_frame(
3448 xfer, nframes, 0, 1, MUSB2_MASK_FRAME, NULL))
3449 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3450
3451 /* setup TDs */
3452 musbotg_setup_standard_chain(xfer);
3453}
3454
3455static void
3456musbotg_device_isoc_start(struct usb_xfer *xfer)
3457{
3458 /* start TD chain */
3459 musbotg_start_standard_chain(xfer);
3460}
3461
3462static const struct usb_pipe_methods musbotg_device_isoc_methods =
3463{
3464 .open = musbotg_device_isoc_open,
3465 .close = musbotg_device_isoc_close,
3466 .enter = musbotg_device_isoc_enter,
3467 .start = musbotg_device_isoc_start,
3468};
3469
3470/*------------------------------------------------------------------------*
3471 * musbotg root control support
3472 *------------------------------------------------------------------------*
3473 * Simulate a hardware HUB by handling all the necessary requests.
3474 *------------------------------------------------------------------------*/
3475
3476static const struct usb_device_descriptor musbotg_devd = {
3477 .bLength = sizeof(struct usb_device_descriptor),
3478 .bDescriptorType = UDESC_DEVICE,
3479 .bcdUSB = {0x00, 0x02},
3480 .bDeviceClass = UDCLASS_HUB,
3481 .bDeviceSubClass = UDSUBCLASS_HUB,
3482 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3483 .bMaxPacketSize = 64,
3484 .bcdDevice = {0x00, 0x01},
3485 .iManufacturer = 1,
3486 .iProduct = 2,
3487 .bNumConfigurations = 1,
3488};
3489
3490static const struct usb_device_qualifier musbotg_odevd = {
3491 .bLength = sizeof(struct usb_device_qualifier),
3492 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3493 .bcdUSB = {0x00, 0x02},
3494 .bDeviceClass = UDCLASS_HUB,
3495 .bDeviceSubClass = UDSUBCLASS_HUB,
3496 .bDeviceProtocol = UDPROTO_FSHUB,
3497 .bMaxPacketSize0 = 0,
3498 .bNumConfigurations = 0,
3499};
3500
3501static const struct musbotg_config_desc musbotg_confd = {
3502 .confd = {
3503 .bLength = sizeof(struct usb_config_descriptor),
3504 .bDescriptorType = UDESC_CONFIG,
3505 .wTotalLength[0] = sizeof(musbotg_confd),
3506 .bNumInterface = 1,
3507 .bConfigurationValue = 1,
3508 .iConfiguration = 0,
3509 .bmAttributes = UC_SELF_POWERED,
3510 .bMaxPower = 0,
3511 },
3512 .ifcd = {
3513 .bLength = sizeof(struct usb_interface_descriptor),
3514 .bDescriptorType = UDESC_INTERFACE,
3515 .bNumEndpoints = 1,
3516 .bInterfaceClass = UICLASS_HUB,
3517 .bInterfaceSubClass = UISUBCLASS_HUB,
3518 .bInterfaceProtocol = 0,
3519 },
3520 .endpd = {
3521 .bLength = sizeof(struct usb_endpoint_descriptor),
3522 .bDescriptorType = UDESC_ENDPOINT,
3523 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3524 .bmAttributes = UE_INTERRUPT,
3525 .wMaxPacketSize[0] = 8,
3526 .bInterval = 255,
3527 },
3528};
3529#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3530
3531static const struct usb_hub_descriptor_min musbotg_hubd = {
3532 .bDescLength = sizeof(musbotg_hubd),
3533 .bDescriptorType = UDESC_HUB,
3534 .bNbrPorts = 1,
3535 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3536 .bPwrOn2PwrGood = 50,
3537 .bHubContrCurrent = 0,
3538 .DeviceRemovable = {0}, /* port is removable */
3539};
3540
3541#define STRING_VENDOR \
3542 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3543
3544#define STRING_PRODUCT \
3545 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3546
3547USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3548USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3549
3550static usb_error_t
3551musbotg_roothub_exec(struct usb_device *udev,
3552 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3553{
3554 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3555 const void *ptr;
3556 uint16_t len;
3557 uint16_t value;
3558 uint16_t index;
3559 uint8_t reg;
3560 usb_error_t err;
3561
3562 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3563
3564 /* buffer reset */
3565 ptr = (const void *)&sc->sc_hub_temp;
3566 len = 0;
3567 err = 0;
3568
3569 value = UGETW(req->wValue);
3570 index = UGETW(req->wIndex);
3571
3572 /* demultiplex the control request */
3573
3574 switch (req->bmRequestType) {
3575 case UT_READ_DEVICE:
3576 switch (req->bRequest) {
3577 case UR_GET_DESCRIPTOR:
3578 goto tr_handle_get_descriptor;
3579 case UR_GET_CONFIG:
3580 goto tr_handle_get_config;
3581 case UR_GET_STATUS:
3582 goto tr_handle_get_status;
3583 default:
3584 goto tr_stalled;
3585 }
3586 break;
3587
3588 case UT_WRITE_DEVICE:
3589 switch (req->bRequest) {
3590 case UR_SET_ADDRESS:
3591 goto tr_handle_set_address;
3592 case UR_SET_CONFIG:
3593 goto tr_handle_set_config;
3594 case UR_CLEAR_FEATURE:
3595 goto tr_valid; /* nop */
3596 case UR_SET_DESCRIPTOR:
3597 goto tr_valid; /* nop */
3598 case UR_SET_FEATURE:
3599 default:
3600 goto tr_stalled;
3601 }
3602 break;
3603
3604 case UT_WRITE_ENDPOINT:
3605 switch (req->bRequest) {
3606 case UR_CLEAR_FEATURE:
3607 switch (UGETW(req->wValue)) {
3608 case UF_ENDPOINT_HALT:
3609 goto tr_handle_clear_halt;
3610 case UF_DEVICE_REMOTE_WAKEUP:
3611 goto tr_handle_clear_wakeup;
3612 default:
3613 goto tr_stalled;
3614 }
3615 break;
3616 case UR_SET_FEATURE:
3617 switch (UGETW(req->wValue)) {
3618 case UF_ENDPOINT_HALT:
3619 goto tr_handle_set_halt;
3620 case UF_DEVICE_REMOTE_WAKEUP:
3621 goto tr_handle_set_wakeup;
3622 default:
3623 goto tr_stalled;
3624 }
3625 break;
3626 case UR_SYNCH_FRAME:
3627 goto tr_valid; /* nop */
3628 default:
3629 goto tr_stalled;
3630 }
3631 break;
3632
3633 case UT_READ_ENDPOINT:
3634 switch (req->bRequest) {
3635 case UR_GET_STATUS:
3636 goto tr_handle_get_ep_status;
3637 default:
3638 goto tr_stalled;
3639 }
3640 break;
3641
3642 case UT_WRITE_INTERFACE:
3643 switch (req->bRequest) {
3644 case UR_SET_INTERFACE:
3645 goto tr_handle_set_interface;
3646 case UR_CLEAR_FEATURE:
3647 goto tr_valid; /* nop */
3648 case UR_SET_FEATURE:
3649 default:
3650 goto tr_stalled;
3651 }
3652 break;
3653
3654 case UT_READ_INTERFACE:
3655 switch (req->bRequest) {
3656 case UR_GET_INTERFACE:
3657 goto tr_handle_get_interface;
3658 case UR_GET_STATUS:
3659 goto tr_handle_get_iface_status;
3660 default:
3661 goto tr_stalled;
3662 }
3663 break;
3664
3665 case UT_WRITE_CLASS_INTERFACE:
3666 case UT_WRITE_VENDOR_INTERFACE:
3667 /* XXX forward */
3668 break;
3669
3670 case UT_READ_CLASS_INTERFACE:
3671 case UT_READ_VENDOR_INTERFACE:
3672 /* XXX forward */
3673 break;
3674
3675 case UT_WRITE_CLASS_DEVICE:
3676 switch (req->bRequest) {
3677 case UR_CLEAR_FEATURE:
3678 goto tr_valid;
3679 case UR_SET_DESCRIPTOR:
3680 case UR_SET_FEATURE:
3681 break;
3682 default:
3683 goto tr_stalled;
3684 }
3685 break;
3686
3687 case UT_WRITE_CLASS_OTHER:
3688 switch (req->bRequest) {
3689 case UR_CLEAR_FEATURE:
3690 goto tr_handle_clear_port_feature;
3691 case UR_SET_FEATURE:
3692 goto tr_handle_set_port_feature;
3693 case UR_CLEAR_TT_BUFFER:
3694 case UR_RESET_TT:
3695 case UR_STOP_TT:
3696 goto tr_valid;
3697
3698 default:
3699 goto tr_stalled;
3700 }
3701 break;
3702
3703 case UT_READ_CLASS_OTHER:
3704 switch (req->bRequest) {
3705 case UR_GET_TT_STATE:
3706 goto tr_handle_get_tt_state;
3707 case UR_GET_STATUS:
3708 goto tr_handle_get_port_status;
3709 default:
3710 goto tr_stalled;
3711 }
3712 break;
3713
3714 case UT_READ_CLASS_DEVICE:
3715 switch (req->bRequest) {
3716 case UR_GET_DESCRIPTOR:
3717 goto tr_handle_get_class_descriptor;
3718 case UR_GET_STATUS:
3719 goto tr_handle_get_class_status;
3720
3721 default:
3722 goto tr_stalled;
3723 }
3724 break;
3725 default:
3726 goto tr_stalled;
3727 }
3728 goto tr_valid;
3729
3730tr_handle_get_descriptor:
3731 switch (value >> 8) {
3732 case UDESC_DEVICE:
3733 if (value & 0xff) {
3734 goto tr_stalled;
3735 }
3736 len = sizeof(musbotg_devd);
3737 ptr = (const void *)&musbotg_devd;
3738 goto tr_valid;
3739 case UDESC_DEVICE_QUALIFIER:
3740 if (value & 0xff) {
3741 goto tr_stalled;
3742 }
3743 len = sizeof(musbotg_odevd);
3744 ptr = (const void *)&musbotg_odevd;
3745 goto tr_valid;
3746 case UDESC_CONFIG:
3747 if (value & 0xff) {
3748 goto tr_stalled;
3749 }
3750 len = sizeof(musbotg_confd);
3751 ptr = (const void *)&musbotg_confd;
3752 goto tr_valid;
3753 case UDESC_STRING:
3754 switch (value & 0xff) {
3755 case 0: /* Language table */
3756 len = sizeof(usb_string_lang_en);
3757 ptr = (const void *)&usb_string_lang_en;
3758 goto tr_valid;
3759
3760 case 1: /* Vendor */
3761 len = sizeof(musbotg_vendor);
3762 ptr = (const void *)&musbotg_vendor;
3763 goto tr_valid;
3764
3765 case 2: /* Product */
3766 len = sizeof(musbotg_product);
3767 ptr = (const void *)&musbotg_product;
3768 goto tr_valid;
3769 default:
3770 break;
3771 }
3772 break;
3773 default:
3774 goto tr_stalled;
3775 }
3776 goto tr_stalled;
3777
3778tr_handle_get_config:
3779 len = 1;
3780 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3781 goto tr_valid;
3782
3783tr_handle_get_status:
3784 len = 2;
3785 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3786 goto tr_valid;
3787
3788tr_handle_set_address:
3789 if (value & 0xFF00) {
3790 goto tr_stalled;
3791 }
3792 sc->sc_rt_addr = value;
3793 goto tr_valid;
3794
3795tr_handle_set_config:
3796 if (value >= 2) {
3797 goto tr_stalled;
3798 }
3799 sc->sc_conf = value;
3800 goto tr_valid;
3801
3802tr_handle_get_interface:
3803 len = 1;
3804 sc->sc_hub_temp.wValue[0] = 0;
3805 goto tr_valid;
3806
3807tr_handle_get_tt_state:
3808tr_handle_get_class_status:
3809tr_handle_get_iface_status:
3810tr_handle_get_ep_status:
3811 len = 2;
3812 USETW(sc->sc_hub_temp.wValue, 0);
3813 goto tr_valid;
3814
3815tr_handle_set_halt:
3816tr_handle_set_interface:
3817tr_handle_set_wakeup:
3818tr_handle_clear_wakeup:
3819tr_handle_clear_halt:
3820 goto tr_valid;
3821
3822tr_handle_clear_port_feature:
3823 if (index != 1) {
3824 goto tr_stalled;
3825 }
3826 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3827
3828 switch (value) {
3829 case UHF_PORT_SUSPEND:
3830 if (sc->sc_mode == MUSB2_HOST_MODE)
3831 musbotg_wakeup_host(sc);
3832 else
3833 musbotg_wakeup_peer(sc);
3834 break;
3835
3836 case UHF_PORT_ENABLE:
3837 sc->sc_flags.port_enabled = 0;
3838 break;
3839
3840 case UHF_C_PORT_ENABLE:
3841 sc->sc_flags.change_enabled = 0;
3842 break;
3843
3844 case UHF_C_PORT_OVER_CURRENT:
3845 sc->sc_flags.change_over_current = 0;
3846 break;
3847
3848 case UHF_C_PORT_RESET:
3849 sc->sc_flags.change_reset = 0;
3850 break;
3851
3852 case UHF_PORT_TEST:
3853 case UHF_PORT_INDICATOR:
3854 /* nops */
3855 break;
3856
3857 case UHF_PORT_POWER:
3858 sc->sc_flags.port_powered = 0;
3859 musbotg_pull_down(sc);
3860 musbotg_clocks_off(sc);
3861 break;
3862 case UHF_C_PORT_CONNECTION:
3863 sc->sc_flags.change_connect = 0;
3864 break;
3865 case UHF_C_PORT_SUSPEND:
3866 sc->sc_flags.change_suspend = 0;
3867 break;
3868 default:
3869 err = USB_ERR_IOERROR;
3870 goto done;
3871 }
3872 goto tr_valid;
3873
3874tr_handle_set_port_feature:
3875 if (index != 1) {
3876 goto tr_stalled;
3877 }
3878 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3879
3880 switch (value) {
3881 case UHF_PORT_ENABLE:
3882 sc->sc_flags.port_enabled = 1;
3883 break;
3884 case UHF_PORT_SUSPEND:
3885 if (sc->sc_mode == MUSB2_HOST_MODE)
3886 musbotg_suspend_host(sc);
3887 break;
3888
3889 case UHF_PORT_RESET:
3890 if (sc->sc_mode == MUSB2_HOST_MODE) {
3891 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3892 reg |= MUSB2_MASK_RESET;
3893 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3894
3895 /* Wait for 20 msec */
3896 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3897
3898 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3899 reg &= ~MUSB2_MASK_RESET;
3900 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3901
3902 /* determine line speed */
3903 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3904 if (reg & MUSB2_MASK_HSMODE)
3905 sc->sc_flags.status_high_speed = 1;
3906 else
3907 sc->sc_flags.status_high_speed = 0;
3908
3909 sc->sc_flags.change_reset = 1;
3910 } else
3911 err = USB_ERR_IOERROR;
3912 break;
3913
3914 case UHF_PORT_TEST:
3915 case UHF_PORT_INDICATOR:
3916 /* nops */
3917 break;
3918 case UHF_PORT_POWER:
3919 sc->sc_flags.port_powered = 1;
3920 break;
3921 default:
3922 err = USB_ERR_IOERROR;
3923 goto done;
3924 }
3925 goto tr_valid;
3926
3927tr_handle_get_port_status:
3928
3929 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3930
3931 if (index != 1) {
3932 goto tr_stalled;
3933 }
3934 if (sc->sc_flags.status_vbus) {
3935 musbotg_clocks_on(sc);
3936 musbotg_pull_up(sc);
3937 } else {
3938 musbotg_pull_down(sc);
3939 musbotg_clocks_off(sc);
3940 }
3941
3942 /* Select Device Side Mode */
3943 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3944 value = UPS_PORT_MODE_DEVICE;
3945 else
3946 value = 0;
3947
3948 if (sc->sc_flags.status_high_speed) {
3949 value |= UPS_HIGH_SPEED;
3950 }
3951 if (sc->sc_flags.port_powered) {
3952 value |= UPS_PORT_POWER;
3953 }
3954 if (sc->sc_flags.port_enabled) {
3955 value |= UPS_PORT_ENABLED;
3956 }
3957
3958 if (sc->sc_flags.port_over_current)
3959 value |= UPS_OVERCURRENT_INDICATOR;
3960
3961 if (sc->sc_flags.status_vbus &&
3962 sc->sc_flags.status_bus_reset) {
3963 value |= UPS_CURRENT_CONNECT_STATUS;
3964 }
3965 if (sc->sc_flags.status_suspend) {
3966 value |= UPS_SUSPEND;
3967 }
3968 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3969
3970 value = 0;
3971
3972 if (sc->sc_flags.change_connect) {
3973 value |= UPS_C_CONNECT_STATUS;
3974
3975 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3976 if (sc->sc_flags.status_vbus &&
3977 sc->sc_flags.status_bus_reset) {
3978 /* reset EP0 state */
3979 sc->sc_ep0_busy = 0;
3980 sc->sc_ep0_cmd = 0;
3981 }
3982 }
3983 }
3984 if (sc->sc_flags.change_suspend)
3985 value |= UPS_C_SUSPEND;
3986 if (sc->sc_flags.change_reset)
3987 value |= UPS_C_PORT_RESET;
3988 if (sc->sc_flags.change_over_current)
3989 value |= UPS_C_OVERCURRENT_INDICATOR;
3990
3991 USETW(sc->sc_hub_temp.ps.wPortChange, value);
3992 len = sizeof(sc->sc_hub_temp.ps);
3993 goto tr_valid;
3994
3995tr_handle_get_class_descriptor:
3996 if (value & 0xFF) {
3997 goto tr_stalled;
3998 }
3999 ptr = (const void *)&musbotg_hubd;
4000 len = sizeof(musbotg_hubd);
4001 goto tr_valid;
4002
4003tr_stalled:
4004 err = USB_ERR_STALLED;
4005tr_valid:
4006done:
4007 *plength = len;
4008 *pptr = ptr;
4009 return (err);
4010}
4011
4012static void
4013musbotg_xfer_setup(struct usb_setup_params *parm)
4014{
4015 struct musbotg_softc *sc;
4016 struct usb_xfer *xfer;
4017 void *last_obj;
4018 uint32_t ntd;
4019 uint32_t n;
4020 uint8_t ep_no;
4021
4022 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4023 xfer = parm->curr_xfer;
4024
4025 /*
4026 * NOTE: This driver does not use any of the parameters that
4027 * are computed from the following values. Just set some
4028 * reasonable dummies:
4029 */
4030 parm->hc_max_packet_size = 0x400;
4031 parm->hc_max_frame_size = 0xc00;
4032
4033 if ((parm->methods == &musbotg_device_isoc_methods) ||
4034 (parm->methods == &musbotg_device_intr_methods))
4035 parm->hc_max_packet_count = 3;
4036 else
4037 parm->hc_max_packet_count = 1;
4038
4039 usbd_transfer_setup_sub(parm);
4040
4041 /*
4042 * compute maximum number of TDs
4043 */
4044 if (parm->methods == &musbotg_device_ctrl_methods) {
4045 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4046
4047 } else if (parm->methods == &musbotg_device_bulk_methods) {
4048 ntd = xfer->nframes + 1 /* SYNC */ ;
4049
4050 } else if (parm->methods == &musbotg_device_intr_methods) {
4051 ntd = xfer->nframes + 1 /* SYNC */ ;
4052
4053 } else if (parm->methods == &musbotg_device_isoc_methods) {
4054 ntd = xfer->nframes + 1 /* SYNC */ ;
4055
4056 } else {
4057 ntd = 0;
4058 }
4059
4060 /*
4061 * check if "usbd_transfer_setup_sub" set an error
4062 */
4063 if (parm->err) {
4064 return;
4065 }
4066 /*
4067 * allocate transfer descriptors
4068 */
4069 last_obj = NULL;
4070
4071 ep_no = xfer->endpointno & UE_ADDR;
4072
4073 /*
4074 * Check for a valid endpoint profile in USB device mode:
4075 */
4076 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4077 const struct usb_hw_ep_profile *pf;
4078
4079 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4080
4081 if (pf == NULL) {
4082 /* should not happen */
4083 parm->err = USB_ERR_INVAL;
4084 return;
4085 }
4086 }
4087
4088 /* align data */
4089 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4090
4091 for (n = 0; n != ntd; n++) {
4092 struct musbotg_td *td;
4093
4094 if (parm->buf) {
4095 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4096
4097 /* init TD */
4098 td->max_frame_size = xfer->max_frame_size;
4099 td->reg_max_packet = xfer->max_packet_size |
4100 ((xfer->max_packet_count - 1) << 11);
4101 td->ep_no = ep_no;
4102 td->obj_next = last_obj;
4103
4104 last_obj = td;
4105 }
4106 parm->size[0] += sizeof(*td);
4107 }
4108
4109 xfer->td_start[0] = last_obj;
4110}
4111
4112static void
4113musbotg_xfer_unsetup(struct usb_xfer *xfer)
4114{
4115 return;
4116}
4117
4118static void
4119musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4120{
4121 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4122
4123 if (sc->sc_mode == MUSB2_HOST_MODE)
4124 *pus = 2000; /* microseconds */
4125 else
4126 *pus = 0;
4127}
4128
4129static void
4130musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4131 struct usb_endpoint *ep)
4132{
4133 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4134
4135 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4136 ep, udev->address,
4137 edesc->bEndpointAddress, udev->flags.usb_mode,
4138 sc->sc_rt_addr);
4139
4140 if (udev->device_index != sc->sc_rt_addr) {
4141 switch (edesc->bmAttributes & UE_XFERTYPE) {
4142 case UE_CONTROL:
4143 ep->methods = &musbotg_device_ctrl_methods;
4144 break;
4145 case UE_INTERRUPT:
4146 ep->methods = &musbotg_device_intr_methods;
4147 break;
4148 case UE_ISOCHRONOUS:
4149 ep->methods = &musbotg_device_isoc_methods;
4150 break;
4151 case UE_BULK:
4152 ep->methods = &musbotg_device_bulk_methods;
4153 break;
4154 default:
4155 /* do nothing */
4156 break;
4157 }
4158 }
4159}
4160
4161static void
4162musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4163{
4164 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4165
4166 switch (state) {
4167 case USB_HW_POWER_SUSPEND:
4168 musbotg_uninit(sc);
4169 break;
4170 case USB_HW_POWER_SHUTDOWN:
4171 musbotg_uninit(sc);
4172 break;
4173 case USB_HW_POWER_RESUME:
4174 musbotg_init(sc);
4175 break;
4176 default:
4177 break;
4178 }
4179}
4180
4181static const struct usb_bus_methods musbotg_bus_methods =
4182{
4183 .endpoint_init = &musbotg_ep_init,
4184 .get_dma_delay = &musbotg_get_dma_delay,
4185 .xfer_setup = &musbotg_xfer_setup,
4186 .xfer_unsetup = &musbotg_xfer_unsetup,
4187 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4188 .xfer_stall = &musbotg_xfer_stall,
4189 .set_stall = &musbotg_set_stall,
4190 .clear_stall = &musbotg_clear_stall,
4191 .roothub_exec = &musbotg_roothub_exec,
4192 .xfer_poll = &musbotg_do_poll,
4193 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,
4194};
debug
static int debug
Definition: cfumass.c:73
SYSCTL_NODE
static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW|CTLFLAG_MPSAFE, 0, "USB DWC OTG")
SYSCTL_INT
SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+")
len
uint16_t len
Definition: ehci.h:41
reg
uint32_t reg
Definition: if_rum.c:283
n
uint8_t n
Definition: if_run.c:612
tx
struct @110 tx
error
struct @109 error
musbotg_device_bulk_close
static void musbotg_device_bulk_close(struct usb_xfer *xfer)
Definition: musb_otg.c:3318
musbotg_confd
static const struct musbotg_config_desc musbotg_confd
Definition: musb_otg.c:3501
musbotg_device_ctrl_start
static void musbotg_device_ctrl_start(struct usb_xfer *xfer)
Definition: musb_otg.c:3367
MAX_NAK_TO
#define MAX_NAK_TO
Definition: musb_otg.c:99
musbotg_clocks_off
static void musbotg_clocks_off(struct musbotg_softc *sc)
Definition: musb_otg.c:277
musbotg_channel_alloc
static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t)
Definition: musb_otg.c:173
musbotg_dev_data_tx
static musbotg_cmd_t musbotg_dev_data_tx
Definition: musb_otg.c:124
musbotg_clear_stall_sub
static void musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
Definition: musb_otg.c:2865
musbotg_roothub_exec
static usb_error_t musbotg_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength)
Definition: musb_otg.c:3551
musbotg_dev_ctrl_setup_rx
static musbotg_cmd_t musbotg_dev_ctrl_setup_rx
Definition: musb_otg.c:110
STRING_VENDOR
#define STRING_VENDOR
Definition: musb_otg.c:3541
musbotg_timeout
static void musbotg_timeout(void *arg)
Definition: musb_otg.c:2606
musbotg_ep_init
static void musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep)
Definition: musb_otg.c:4130
musbotg_get_dma_delay
static void musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
Definition: musb_otg.c:4119
musbotg_host_ctrl_setup_tx
static musbotg_cmd_t musbotg_host_ctrl_setup_tx
Definition: musb_otg.c:116
musbotg_device_intr_enter
static void musbotg_device_intr_enter(struct usb_xfer *xfer)
Definition: musb_otg.c:3398
musbotg_device_intr_close
static void musbotg_device_intr_close(struct usb_xfer *xfer)
Definition: musb_otg.c:3392
musbotg_host_data_rx
static musbotg_cmd_t musbotg_host_data_rx
Definition: musb_otg.c:127
musbotg_interrupt_poll
static void musbotg_interrupt_poll(struct musbotg_softc *)
Definition: musb_otg.c:2173
musbotg_device_intr_start
static void musbotg_device_intr_start(struct usb_xfer *xfer)
Definition: musb_otg.c:3404
musbotg_pull_down
static void musbotg_pull_down(struct musbotg_softc *sc)
Definition: musb_otg.c:318
MUSBOTG_PC2SC
#define MUSBOTG_PC2SC(pc)
Definition: musb_otg.c:87
musbotg_ep_int_set
static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
Definition: musb_otg.c:2619
musbotg_clear_stall
static void musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
Definition: musb_otg.c:3014
musbotg_dev_ctrl_status
static musbotg_cmd_t musbotg_dev_ctrl_status
Definition: musb_otg.c:113
musbotg_standard_done_sub
static usb_error_t musbotg_standard_done_sub(struct usb_xfer *xfer)
Definition: musb_otg.c:2696
musbotg_ep_default
static const struct musb_otg_ep_cfg musbotg_ep_default[]
Definition: musb_otg.c:151
musbotg_set_hw_power_sleep
static void musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
Definition: musb_otg.c:4162
musbotg_device_bulk_methods
static const struct usb_pipe_methods musbotg_device_bulk_methods
Definition: musb_otg.c:104
musbotg_host_data_tx
static musbotg_cmd_t musbotg_host_data_tx
Definition: musb_otg.c:128
musbotg_host_ctrl_data_rx
static musbotg_cmd_t musbotg_host_ctrl_data_rx
Definition: musb_otg.c:117
musbotg_device_intr_open
static void musbotg_device_intr_open(struct usb_xfer *xfer)
Definition: musb_otg.c:3386
musbotg_xfer_do_fifo
static uint8_t musbotg_xfer_do_fifo(struct usb_xfer *xfer)
Definition: musb_otg.c:2127
musbotg_host_ctrl_status_rx
static musbotg_cmd_t musbotg_host_ctrl_status_rx
Definition: musb_otg.c:119
musbotg_uninit
void musbotg_uninit(struct musbotg_softc *sc)
Definition: musb_otg.c:3277
musbotg_setup_standard_chain_sub
static void musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
Definition: musb_otg.c:2362
musbotg_device_isoc_close
static void musbotg_device_isoc_close(struct usb_xfer *xfer)
Definition: musb_otg.c:3429
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static const struct usb_pipe_methods musbotg_device_ctrl_methods
Definition: musb_otg.c:105
musbotg_device_done
static void musbotg_device_done(struct usb_xfer *, usb_error_t)
Definition: musb_otg.c:2808
musbotg_host_ctrl_data_tx
static musbotg_cmd_t musbotg_host_ctrl_data_tx
Definition: musb_otg.c:118
musbotg_wakeup_peer
static void musbotg_wakeup_peer(struct musbotg_softc *sc)
Definition: musb_otg.c:369
musbotg_channel_free
static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td)
Definition: musb_otg.c:222
musbotg_dev_data_rx
static musbotg_cmd_t musbotg_dev_data_rx
Definition: musb_otg.c:123
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static void musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
Definition: musb_otg.c:391
musbotg_host_ctrl_status_tx
static musbotg_cmd_t musbotg_host_ctrl_status_tx
Definition: musb_otg.c:120
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static const struct usb_hub_descriptor_min musbotg_hubd
Definition: musb_otg.c:3531
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static void musbotg_pull_up(struct musbotg_softc *sc)
Definition: musb_otg.c:306
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static void musbotg_root_intr(struct musbotg_softc *)
Definition: musb_otg.c:2682
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void musbotg_connect_interrupt(struct musbotg_softc *sc)
Definition: musb_otg.c:2216
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static void musbotg_xfer_unsetup(struct usb_xfer *xfer)
Definition: musb_otg.c:4113
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static const struct usb_hw_ep_profile musbotg_ep_profile[1]
Definition: musb_otg.c:142
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static const struct usb_device_qualifier musbotg_odevd
Definition: musb_otg.c:3490
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static void musbotg_device_isoc_open(struct usb_xfer *xfer)
Definition: musb_otg.c:3423
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static void musbotg_device_isoc_enter(struct usb_xfer *xfer)
Definition: musb_otg.c:3435
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static void musbotg_start_standard_chain(struct usb_xfer *xfer)
Definition: musb_otg.c:2662
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#define MUSBOTG_INTR_ENDPT
Definition: musb_otg.c:82
musbotg_bus_methods
static const struct usb_bus_methods musbotg_bus_methods
Definition: musb_otg.c:103
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static void musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
Definition: musb_otg.c:292
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static void musbotg_do_poll(struct usb_bus *)
Definition: musb_otg.c:3299
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static const struct usb_pipe_methods musbotg_device_intr_methods
Definition: musb_otg.c:106
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static void musbotg_device_bulk_start(struct usb_xfer *xfer)
Definition: musb_otg.c:3330
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static void musbotg_get_hw_ep_profile(struct usb_device *udev, const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
Definition: musb_otg.c:242
musbotg_device_bulk_enter
static void musbotg_device_bulk_enter(struct usb_xfer *xfer)
Definition: musb_otg.c:3324
STRING_PRODUCT
#define STRING_PRODUCT
Definition: musb_otg.c:3544
musbotg_device_isoc_methods
static const struct usb_pipe_methods musbotg_device_isoc_methods
Definition: musb_otg.c:107
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static void musbotg_set_stall(struct usb_device *udev, struct usb_endpoint *ep, uint8_t *did_stall)
Definition: musb_otg.c:2837
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static void musbotg_device_ctrl_close(struct usb_xfer *xfer)
Definition: musb_otg.c:3355
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void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
Definition: musb_otg.c:2187
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static void musbotg_device_ctrl_enter(struct usb_xfer *xfer)
Definition: musb_otg.c:3361
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static musbotg_cmd_t musbotg_dev_ctrl_data_rx
Definition: musb_otg.c:111
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static void musbotg_device_isoc_start(struct usb_xfer *xfer)
Definition: musb_otg.c:3456
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#define HSETW(ptr, val)
Definition: musb_otg.c:3529
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void musbotg_interrupt(struct musbotg_softc *sc, uint16_t rxstat, uint16_t txstat, uint8_t stat)
Definition: musb_otg.c:2227
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static void musbotg_clocks_on(struct musbotg_softc *sc)
Definition: musb_otg.c:261
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static void musbotg_xfer_setup(struct usb_setup_params *parm)
Definition: musb_otg.c:4013
MUSBOTG_BUS2SC
#define MUSBOTG_BUS2SC(bus)
Definition: musb_otg.c:84
musbotg_standard_done
static void musbotg_standard_done(struct usb_xfer *)
Definition: musb_otg.c:2763
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static const struct usb_device_descriptor musbotg_devd
Definition: musb_otg.c:3476
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static void musbotg_setup_standard_chain(struct usb_xfer *xfer)
Definition: musb_otg.c:2391
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static void musbotg_suspend_host(struct musbotg_softc *sc)
Definition: musb_otg.c:329
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static void musbotg_device_bulk_open(struct usb_xfer *xfer)
Definition: musb_otg.c:3312
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static musbotg_cmd_t musbotg_dev_ctrl_data_tx
Definition: musb_otg.c:112
USB_MAKE_STRING_DESC
USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor)
musbotg_init
usb_error_t musbotg_init(struct musbotg_softc *sc)
Definition: musb_otg.c:3043
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static void musbotg_wakeup_host(struct musbotg_softc *sc)
Definition: musb_otg.c:344
musbotg_device_ctrl_open
static void musbotg_device_ctrl_open(struct usb_xfer *xfer)
Definition: musb_otg.c:3349
musbotg_xfer_stall
static void musbotg_xfer_stall(struct usb_xfer *xfer)
Definition: musb_otg.c:2831
musb_otg.h
MUSB2_MASK_CSR0L_ERROR
#define MUSB2_MASK_CSR0L_ERROR
Definition: musb_otg.h:127
MUSB2_REG_RXDBDIS
#define MUSB2_REG_RXDBDIS
Definition: musb_otg.h:268
MUSB2_MASK_CSRH_RXISO
#define MUSB2_MASK_CSRH_RXISO
Definition: musb_otg.h:169
MUSB2_MASK_CSR0L_STATUSPKT
#define MUSB2_MASK_CSR0L_STATUSPKT
Definition: musb_otg.h:129
MUSB2_MASK_TI_SPEED_HS
#define MUSB2_MASK_TI_SPEED_HS
Definition: musb_otg.h:183
MUSB2_READ_1
#define MUSB2_READ_1(sc, reg)
Definition: musb_otg.h:295
MUSB2_MASK_CSRL_RXFFLUSH
#define MUSB2_MASK_CSRL_RXFFLUSH
Definition: musb_otg.h:155
MUSB2_MASK_CSR0L_SETUPEND
#define MUSB2_MASK_CSR0L_SETUPEND
Definition: musb_otg.h:118
MUSB2_MASK_FIFODB
#define MUSB2_MASK_FIFODB
Definition: musb_otg.h:228
MUSB2_MASK_CSRL_TXPKTRDY
#define MUSB2_MASK_CSRL_TXPKTRDY
Definition: musb_otg.h:100
MUSB2_REG_RXNAKLIMIT
#define MUSB2_REG_RXNAKLIMIT
Definition: musb_otg.h:191
MUSB2_MASK_CSRL_RXOVERRUN
#define MUSB2_MASK_CSRL_RXOVERRUN
Definition: musb_otg.h:151
MUSB2_REG_TXCSRL
#define MUSB2_REG_TXCSRL
Definition: musb_otg.h:99
MUSB2_MASK_ISUSP
#define MUSB2_MASK_ISUSP
Definition: musb_otg.h:65
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#define MUSB2_MASK_IRESET
Definition: musb_otg.h:67
MUSB2_VAL_FIFOSZ_4096
#define MUSB2_VAL_FIFOSZ_4096
Definition: musb_otg.h:239
MUSB2_MASK_CSRL_TXUNDERRUN
#define MUSB2_MASK_CSRL_TXUNDERRUN
Definition: musb_otg.h:102
MUSB2_MASK_CSRL_RXSENTSTALL
#define MUSB2_MASK_CSRL_RXSENTSTALL
Definition: musb_otg.h:158
MUSB2_MASK_CSR0L_SETUPEND_CLR
#define MUSB2_MASK_CSR0L_SETUPEND_CLR
Definition: musb_otg.h:121
MUSB2_MASK_CSRH_RXNYET
#define MUSB2_MASK_CSRH_RXNYET
Definition: musb_otg.h:167
MUSB2_MASK_TI_SPEED_LO
#define MUSB2_MASK_TI_SPEED_LO
Definition: musb_otg.h:181
MUSB2_DEVICE_MODE
#define MUSB2_DEVICE_MODE
Definition: musb_otg.h:286
MUSB2_REG_RXHUBPORT
#define MUSB2_REG_RXHUBPORT(n)
Definition: musb_otg.h:282
MUSB2_REG_RXCSRH
#define MUSB2_REG_RXCSRH
Definition: musb_otg.h:162
MUSB2_MASK_CSRL_TXSENTSTALL
#define MUSB2_MASK_CSRL_TXSENTSTALL
Definition: musb_otg.h:107
MUSB2_REG_INTTX
#define MUSB2_REG_INTTX
Definition: musb_otg.h:56
MUSB2_REG_RXFIFOADD
#define MUSB2_REG_RXFIFOADD
Definition: musb_otg.h:242
MUSB2_MASK_CSRL_RXSTALL
#define MUSB2_MASK_CSRL_RXSTALL
Definition: musb_otg.h:159
MUSB2_REG_INTTXE
#define MUSB2_REG_INTTXE
Definition: musb_otg.h:58
MUSB2_REG_RXCSRL
#define MUSB2_REG_RXCSRL
Definition: musb_otg.h:148
MUSB2_MASK_HSMODE
#define MUSB2_MASK_HSMODE
Definition: musb_otg.h:49
MUSB2_MASK_CSRL_RXERROR
#define MUSB2_MASK_CSRL_RXERROR
Definition: musb_otg.h:152
MUSB2_MASK_CSRH_TXDT_VAL
#define MUSB2_MASK_CSRH_TXDT_VAL
Definition: musb_otg.h:133
MUSB2_MASK_CSRL_TXINCOMP
#define MUSB2_MASK_CSRL_TXINCOMP
Definition: musb_otg.h:110
MUSB2_REG_RXFIFOSZ
#define MUSB2_REG_RXFIFOSZ
Definition: musb_otg.h:227
MUSB2_MASK_CSR0L_DATAEND
#define MUSB2_MASK_CSR0L_DATAEND
Definition: musb_otg.h:117
MUSB2_MASK_CSR0L_REQPKT
#define MUSB2_MASK_CSR0L_REQPKT
Definition: musb_otg.h:128
MUSB2_REG_TXNAKLIMIT
#define MUSB2_REG_TXNAKLIMIT
Definition: musb_otg.h:190
MUSB2_REG_TXMAXP
#define MUSB2_REG_TXMAXP
Definition: musb_otg.h:94
MUSB2_MASK_CSR0L_SENTSTALL
#define MUSB2_MASK_CSR0L_SENTSTALL
Definition: musb_otg.h:116
MUSB2_REG_TXFIFOADD
#define MUSB2_REG_TXFIFOADD
Definition: musb_otg.h:241
MUSB2_MASK_CSR0L_TXPKTRDY
#define MUSB2_MASK_CSR0L_TXPKTRDY
Definition: musb_otg.h:115
MUSB2_MASK_CSR0H_FFLUSH
#define MUSB2_MASK_CSR0H_FFLUSH
Definition: musb_otg.h:143
MUSB2_MASK_CSR0L_RXPKTRDY
#define MUSB2_MASK_CSR0L_RXPKTRDY
Definition: musb_otg.h:114
MUSB2_REG_EPINFO
#define MUSB2_REG_EPINFO
Definition: musb_otg.h:250
MUSB2_REG_RXMAXP
#define MUSB2_REG_RXMAXP
Definition: musb_otg.h:95
MUSB2_MASK_RESET
#define MUSB2_MASK_RESET
Definition: musb_otg.h:48
MUSB2_MASK_TI_SPEED_FS
#define MUSB2_MASK_TI_SPEED_FS
Definition: musb_otg.h:182
MUSB2_REG_TESTMODE
#define MUSB2_REG_TESTMODE
Definition: musb_otg.h:82
MUSB2_MASK_CSRL_TXSTALLED
#define MUSB2_MASK_CSRL_TXSTALLED
Definition: musb_otg.h:108
MUSB2_MASK_TI_PROTO_BULK
#define MUSB2_MASK_TI_PROTO_BULK
Definition: musb_otg.h:186
MUSB2_MASK_CSRL_TXERROR
#define MUSB2_MASK_CSRL_TXERROR
Definition: musb_otg.h:103
MUSB2_REG_RXCOUNT
#define MUSB2_REG_RXCOUNT
Definition: musb_otg.h:173
MUSB2_WRITE_1
#define MUSB2_WRITE_1(sc, reg, data)
Definition: musb_otg.h:298
MUSB2_WRITE_2
#define MUSB2_WRITE_2(sc, reg, data)
Definition: musb_otg.h:292
MUSB2_REG_RXFADDR
#define MUSB2_REG_RXFADDR(n)
Definition: musb_otg.h:280
MUSB2_MASK_CD_DYNFIFOSZ
#define MUSB2_MASK_CD_DYNFIFOSZ
Definition: musb_otg.h:203
MUSB2_REG_TXDBDIS
#define MUSB2_REG_TXDBDIS
Definition: musb_otg.h:269
MUSB2_MASK_SOFTC
#define MUSB2_MASK_SOFTC
Definition: musb_otg.h:51
MUSB2_MASK_RESUME
#define MUSB2_MASK_RESUME
Definition: musb_otg.h:47
MUSB2_REG_TXFIFOSZ
#define MUSB2_REG_TXFIFOSZ
Definition: musb_otg.h:226
MUSB2_MASK_HSENAB
#define MUSB2_MASK_HSENAB
Definition: musb_otg.h:50
MUSB2_REG_INTUSB
#define MUSB2_REG_INTUSB
Definition: musb_otg.h:64
MUSB2_MASK_EPINT
#define MUSB2_MASK_EPINT(epn)
Definition: musb_otg.h:60
MUSB2_MASK_CSR0L_NAKTIMO
#define MUSB2_MASK_CSR0L_NAKTIMO
Definition: musb_otg.h:130
MUSB2_MASK_TI_PROTO_ISOC
#define MUSB2_MASK_TI_PROTO_ISOC
Definition: musb_otg.h:185
MUSB2_MASK_SUSPMODE
#define MUSB2_MASK_SUSPMODE
Definition: musb_otg.h:46
MUSB2_MASK_CSR0L_TXFIFONEMPTY
#define MUSB2_MASK_CSR0L_TXFIFONEMPTY
Definition: musb_otg.h:124
MUSB2_MASK_IRESUME
#define MUSB2_MASK_IRESUME
Definition: musb_otg.h:66
MUSB2_MASK_CSR0H_PING_DIS
#define MUSB2_MASK_CSR0H_PING_DIS
Definition: musb_otg.h:146
MUSB2_MASK_CSRL_RXDT_CLR
#define MUSB2_MASK_CSRL_RXDT_CLR
Definition: musb_otg.h:160
MUSB2_HOST_MODE
#define MUSB2_HOST_MODE
Definition: musb_otg.h:287
MUSB2_MASK_CSRL_RXSENDSTALL
#define MUSB2_MASK_CSRL_RXSENDSTALL
Definition: musb_otg.h:156
MUSB2_REG_EPFIFO
#define MUSB2_REG_EPFIFO(n)
Definition: musb_otg.h:198
MUSB2_REG_INTUSBE
#define MUSB2_REG_INTUSBE
Definition: musb_otg.h:75
MUSB2_MASK_CSRH_TXISO
#define MUSB2_MASK_CSRH_TXISO
Definition: musb_otg.h:140
MUSB2_MASK_CSRH_RXDT_VAL
#define MUSB2_MASK_CSRH_RXDT_VAL
Definition: musb_otg.h:164
MUSB2_REG_FRAME
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Definition: musb_otg.h:76
MUSB2_MASK_SESS
#define MUSB2_MASK_SESS
Definition: musb_otg.h:213
MUSB2_MASK_CSR0L_RXPKTRDY_CLR
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Definition: musb_otg.h:120
MUSB2_REG_FADDR
#define MUSB2_REG_FADDR
Definition: musb_otg.h:41
MUSB2_REG_INTRX
#define MUSB2_REG_INTRX
Definition: musb_otg.h:57
MUSB2_MASK_CSRL_RXNAKTO
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Definition: musb_otg.h:154
MUSB2_REG_DEVCTL
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Definition: musb_otg.h:212
MUSB2_MASK_CSRL_TXNAKTO
#define MUSB2_MASK_CSRL_TXNAKTO
Definition: musb_otg.h:111
MUSB2_VAL_FIFOSZ_512
#define MUSB2_VAL_FIFOSZ_512
Definition: musb_otg.h:236
MUSB2_MASK_CSRL_RXREQPKT
#define MUSB2_MASK_CSRL_RXREQPKT
Definition: musb_otg.h:157
MUSB2_VAL_FIFOSZ_128
#define MUSB2_VAL_FIFOSZ_128
Definition: musb_otg.h:234
MUSB2_REG_CONFDATA
#define MUSB2_REG_CONFDATA
Definition: musb_otg.h:200
MUSB2_REG_TXTI
#define MUSB2_REG_TXTI
Definition: musb_otg.h:176
MUSB2_REG_TXFADDR
#define MUSB2_REG_TXFADDR(n)
Definition: musb_otg.h:277
MUSB2_MASK_CSR0L_RXSTALL
#define MUSB2_MASK_CSR0L_RXSTALL
Definition: musb_otg.h:125
MUSB2_MASK_CSRL_TXFFLUSH
#define MUSB2_MASK_CSRL_TXFFLUSH
Definition: musb_otg.h:104
MUSB2_REG_RXHADDR
#define MUSB2_REG_RXHADDR(n)
Definition: musb_otg.h:281
MUSB2_MASK_TX_FSIZE
#define MUSB2_MASK_TX_FSIZE
Definition: musb_otg.h:196
MUSB2_REG_POWER
#define MUSB2_REG_POWER
Definition: musb_otg.h:44
MUSB2_MASK_CSRH_TXMODE
#define MUSB2_MASK_CSRH_TXMODE
Definition: musb_otg.h:139
MUSB2_REG_TXCSRH
#define MUSB2_REG_TXCSRH
Definition: musb_otg.h:132
MUSB2_MASK_CSRL_TXSENDSTALL
#define MUSB2_MASK_CSRL_TXSENDSTALL
Definition: musb_otg.h:105
MUSB2_REG_MISC
#define MUSB2_REG_MISC
Definition: musb_otg.h:222
MUSB2_MASK_CSRL_RXPKTRDY
#define MUSB2_MASK_CSRL_RXPKTRDY
Definition: musb_otg.h:149
MUSB2_REG_TXHUBPORT
#define MUSB2_REG_TXHUBPORT(n)
Definition: musb_otg.h:279
MUSB2_MASK_CSRL_TXFIFONEMPTY
#define MUSB2_MASK_CSRL_TXFIFONEMPTY
Definition: musb_otg.h:101
MUSB2_MASK_ISOUPD
#define MUSB2_MASK_ISOUPD
Definition: musb_otg.h:52
MUSB2_MASK_CSRH_RXDT_WREN
#define MUSB2_MASK_CSRH_RXDT_WREN
Definition: musb_otg.h:165
MUSB2_READ_2
#define MUSB2_READ_2(sc, reg)
Definition: musb_otg.h:289
MUSB2_REG_RXTI
#define MUSB2_REG_RXTI
Definition: musb_otg.h:177
MUSB2_MASK_CSRH_TXDT_WREN
#define MUSB2_MASK_CSRH_TXDT_WREN
Definition: musb_otg.h:134
MUSB2_REG_INTRXE
#define MUSB2_REG_INTRXE
Definition: musb_otg.h:59
MUSB2_MASK_IDISC
#define MUSB2_MASK_IDISC
Definition: musb_otg.h:71
MUSB2_MASK_FRAME
#define MUSB2_MASK_FRAME
Definition: musb_otg.h:77
MUSB2_MASK_IVBUSERR
#define MUSB2_MASK_IVBUSERR
Definition: musb_otg.h:73
MUSB2_MASK_TI_PROTO_INTR
#define MUSB2_MASK_TI_PROTO_INTR
Definition: musb_otg.h:187
MUSB2_MASK_CSR0L_SENDSTALL
#define MUSB2_MASK_CSR0L_SENDSTALL
Definition: musb_otg.h:119
MUSB2_MASK_CSRL_TXDT_CLR
#define MUSB2_MASK_CSRL_TXDT_CLR
Definition: musb_otg.h:109
MUSB2_REG_EPINDEX
#define MUSB2_REG_EPINDEX
Definition: musb_otg.h:79
MUSB2_REG_FSIZE
#define MUSB2_REG_FSIZE
Definition: musb_otg.h:194
MUSB2_MASK_CSR0L_SETUPPKT
#define MUSB2_MASK_CSR0L_SETUPPKT
Definition: musb_otg.h:126
MUSB2_MASK_TI_PROTO_CTRL
#define MUSB2_MASK_TI_PROTO_CTRL
Definition: musb_otg.h:184
MUSB2_MASK_RX_FSIZE
#define MUSB2_MASK_RX_FSIZE
Definition: musb_otg.h:195
MUSB2_MASK_ICONN
#define MUSB2_MASK_ICONN
Definition: musb_otg.h:70
MUSB2_REG_TXHADDR
#define MUSB2_REG_TXHADDR(n)
Definition: musb_otg.h:278
musbotg_cmd_t
uint8_t() musbotg_cmd_t(struct musbotg_td *td)
Definition: musb_otg.h:304
MUSB2_REG_HWVERS
#define MUSB2_REG_HWVERS
Definition: musb_otg.h:247
value
uint32_t value
index
u_int index
pf
device_t pf
state
int state
count
int * count
bus
u_int bus
addr
uint64_t * addr
musb_otg_ep_cfg
Definition: musb_otg.h:390
musb_otg_ep_cfg::ep_end
int ep_end
Definition: musb_otg.h:391
musb_otg_ep_cfg::ep_fifosz_shift
int ep_fifosz_shift
Definition: musb_otg.h:392
musb_otg_ep_cfg::ep_fifosz_reg
uint8_t ep_fifosz_reg
Definition: musb_otg.h:393
musbotg_config_desc
Definition: musb_otg.h:360
musbotg_config_desc::confd
struct usb_config_descriptor confd
Definition: musb_otg.h:361
musbotg_flags::change_suspend
uint8_t change_suspend
Definition: musb_otg.h:373
musbotg_flags::port_enabled
uint8_t port_enabled
Definition: musb_otg.h:385
musbotg_flags::clocks_off
uint8_t clocks_off
Definition: musb_otg.h:383
musbotg_flags::status_suspend
uint8_t status_suspend
Definition: musb_otg.h:377
musbotg_flags::status_bus_reset
uint8_t status_bus_reset
Definition: musb_otg.h:379
musbotg_flags::port_powered
uint8_t port_powered
Definition: musb_otg.h:384
musbotg_flags::change_reset
uint8_t change_reset
Definition: musb_otg.h:374
musbotg_flags::change_connect
uint8_t change_connect
Definition: musb_otg.h:372
musbotg_flags::status_high_speed
uint8_t status_high_speed
Definition: musb_otg.h:380
musbotg_flags::d_pulled_up
uint8_t d_pulled_up
Definition: musb_otg.h:387
musbotg_flags::change_over_current
uint8_t change_over_current
Definition: musb_otg.h:375
musbotg_flags::status_vbus
uint8_t status_vbus
Definition: musb_otg.h:378
musbotg_flags::change_enabled
uint8_t change_enabled
Definition: musb_otg.h:376
musbotg_flags::port_over_current
uint8_t port_over_current
Definition: musb_otg.h:386
musbotg_softc
Definition: musb_otg.h:396
musbotg_softc::sc_clocks_on
void(* sc_clocks_on)(void *arg)
Definition: musb_otg.h:409
musbotg_softc::sc_ep_int_set
void(* sc_ep_int_set)(struct musbotg_softc *sc, int ep, int on)
Definition: musb_otg.h:411
musbotg_softc::sc_rt_addr
uint8_t sc_rt_addr
Definition: musb_otg.h:418
musbotg_softc::sc_hub_idata
uint8_t sc_hub_idata[1]
Definition: musb_otg.h:425
musbotg_softc::sc_hub_temp
union musbotg_hub_temp sc_hub_temp
Definition: musb_otg.h:398
musbotg_softc::sc_dv_addr
uint8_t sc_dv_addr
Definition: musb_otg.h:419
musbotg_softc::sc_io_tag
bus_space_tag_t sc_io_tag
Definition: musb_otg.h:406
musbotg_softc::sc_channel_mask
uint16_t sc_channel_mask
Definition: musb_otg.h:426
musbotg_softc::sc_io_hdl
bus_space_handle_t sc_io_hdl
Definition: musb_otg.h:407
musbotg_softc::sc_conf_data
uint8_t sc_conf_data
Definition: musb_otg.h:423
musbotg_softc::sc_clocks_off
void(* sc_clocks_off)(void *arg)
Definition: musb_otg.h:410
musbotg_softc::sc_ep0_cmd
uint8_t sc_ep0_cmd
Definition: musb_otg.h:422
musbotg_softc::sc_bounce_buf
uint32_t sc_bounce_buf[(1024 *3)/4]
Definition: musb_otg.h:414
musbotg_softc::sc_hw_ep_profile
struct usb_hw_ep_profile sc_hw_ep_profile[MUSB2_EP_MAX]
Definition: musb_otg.h:399
musbotg_softc::sc_ep0_busy
uint8_t sc_ep0_busy
Definition: musb_otg.h:421
musbotg_softc::sc_mode
uint8_t sc_mode
Definition: musb_otg.h:430
musbotg_softc::sc_ep_max
uint8_t sc_ep_max
Definition: musb_otg.h:416
musbotg_softc::sc_flags
struct musbotg_flags sc_flags
Definition: musb_otg.h:428
musbotg_softc::sc_ep_cfg
const struct musb_otg_ep_cfg * sc_ep_cfg
Definition: musb_otg.h:432
musbotg_softc::sc_bus
struct usb_bus sc_bus
Definition: musb_otg.h:397
musbotg_softc::sc_conf
uint8_t sc_conf
Definition: musb_otg.h:420
musbotg_softc::sc_clocks_arg
void * sc_clocks_arg
Definition: musb_otg.h:412
musbotg_std_temp
Definition: musb_otg.h:338
musbotg_std_temp::len
uint32_t len
Definition: musb_otg.h:343
musbotg_std_temp::func
musbotg_cmd_t * func
Definition: musb_otg.h:339
musbotg_std_temp::short_pkt
uint8_t short_pkt
Definition: musb_otg.h:346
musbotg_std_temp::did_stall
uint8_t did_stall
Definition: musb_otg.h:352
musbotg_std_temp::td
struct musbotg_td * td
Definition: musb_otg.h:341
musbotg_std_temp::max_frame_size
uint16_t max_frame_size
Definition: musb_otg.h:345
musbotg_std_temp::transfer_type
uint8_t transfer_type
Definition: musb_otg.h:357
musbotg_std_temp::offset
uint32_t offset
Definition: musb_otg.h:344
musbotg_std_temp::haddr
uint8_t haddr
Definition: musb_otg.h:355
musbotg_std_temp::pc
struct usb_page_cache * pc
Definition: musb_otg.h:340
musbotg_std_temp::hport
uint8_t hport
Definition: musb_otg.h:356
musbotg_std_temp::dev_addr
uint8_t dev_addr
Definition: musb_otg.h:353
musbotg_std_temp::td_next
struct musbotg_td * td_next
Definition: musb_otg.h:342
musbotg_std_temp::setup_alt_next
uint8_t setup_alt_next
Definition: musb_otg.h:351
musbotg_std_temp::channel
int8_t channel
Definition: musb_otg.h:354
musbotg_td
Definition: musb_otg.h:314
musbotg_td::func
musbotg_cmd_t * func
Definition: musb_otg.h:316
musbotg_td::transaction_started
uint8_t transaction_started
Definition: musb_otg.h:330
musbotg_td::dev_addr
uint8_t dev_addr
Definition: musb_otg.h:331
musbotg_td::toggle
uint8_t toggle
Definition: musb_otg.h:332
musbotg_td::obj_next
struct musbotg_td * obj_next
Definition: musb_otg.h:315
musbotg_td::transfer_type
uint8_t transfer_type
Definition: musb_otg.h:323
musbotg_td::haddr
uint8_t haddr
Definition: musb_otg.h:334
musbotg_td::did_stall
uint8_t did_stall
Definition: musb_otg.h:328
musbotg_td::pc
struct usb_page_cache * pc
Definition: musb_otg.h:317
musbotg_td::max_frame_size
uint16_t max_frame_size
Definition: musb_otg.h:320
musbotg_td::reg_max_packet
uint16_t reg_max_packet
Definition: musb_otg.h:321
musbotg_td::short_pkt
uint8_t short_pkt
Definition: musb_otg.h:326
musbotg_td::channel
int8_t channel
Definition: musb_otg.h:333
musbotg_td::remainder
uint32_t remainder
Definition: musb_otg.h:319
musbotg_td::alt_next
uint8_t alt_next
Definition: musb_otg.h:325
musbotg_td::hport
uint8_t hport
Definition: musb_otg.h:335
musbotg_td::offset
uint32_t offset
Definition: musb_otg.h:318
musbotg_td::ep_no
uint8_t ep_no
Definition: musb_otg.h:322
musbotg_td::error
uint8_t error
Definition: musb_otg.h:324
usb_bus_methods
Definition: usb_controller.h:56
usb_bus_methods::endpoint_init
void(* endpoint_init)(struct usb_device *, struct usb_endpoint_descriptor *, struct usb_endpoint *)
Definition: usb_controller.h:61
usb_bus
Definition: usb_bus.h:48
usb_bus::usbrev
enum usb_revision usbrev
Definition: usb_bus.h:119
usb_bus::bdev
device_t bdev
Definition: usb_bus.h:101
usb_bus::bus_mtx
struct mtx bus_mtx
Definition: usb_bus.h:95
usb_bus::methods
const struct usb_bus_methods * methods
Definition: usb_bus.h:107
usb_bus::intr_q
struct usb_xfer_queue intr_q
Definition: usb_bus.h:97
usb_config_descriptor
Definition: usb.h:385
usb_config_descriptor::bDescriptorType
uByte bDescriptorType
Definition: usb.h:387
usb_config_descriptor::bNumInterface
uByte bNumInterface
Definition: usb.h:389
usb_config_descriptor::bmAttributes
uByte bmAttributes
Definition: usb.h:393
usb_config_descriptor::bLength
uByte bLength
Definition: usb.h:386
usb_config_descriptor::bMaxPower
uByte bMaxPower
Definition: usb.h:397
usb_config_descriptor::iConfiguration
uByte iConfiguration
Definition: usb.h:392
usb_config_descriptor::bConfigurationValue
uByte bConfigurationValue
Definition: usb.h:390
usb_device_descriptor
Definition: usb.h:288
usb_device_descriptor::bLength
uByte bLength
Definition: usb.h:289
usb_device_descriptor::bDescriptorType
uByte bDescriptorType
Definition: usb.h:290
usb_device_flags::usb_mode
enum usb_hc_mode usb_mode
Definition: usb_device.h:94
usb_device_qualifier
Definition: usb.h:658
usb_device_qualifier::bLength
uByte bLength
Definition: usb.h:659
usb_device_qualifier::bDescriptorType
uByte bDescriptorType
Definition: usb.h:660
usb_device_request
Definition: usb.h:147
usb_device
Definition: usb_device.h:190
usb_device::hs_port_no
uint8_t hs_port_no
Definition: usb_device.h:253
usb_device::bus
struct usb_bus * bus
Definition: usb_device.h:216
usb_device::device_index
uint8_t device_index
Definition: usb_device.h:244
usb_device::address
uint8_t address
Definition: usb_device.h:243
usb_device::hs_hub_addr
uint8_t hs_hub_addr
Definition: usb_device.h:252
usb_device::flags
struct usb_device_flags flags
Definition: usb_device.h:266
usb_endpoint_descriptor
Definition: usb.h:525
usb_endpoint_descriptor::bInterval
uByte bInterval
Definition: usb.h:560
usb_endpoint_descriptor::bEndpointAddress
uByte bEndpointAddress
Definition: usb.h:528
usb_endpoint_descriptor::bDescriptorType
uByte bDescriptorType
Definition: usb.h:527
usb_endpoint_descriptor::wMaxPacketSize
uWord wMaxPacketSize
Definition: usb.h:558
usb_endpoint_descriptor::bmAttributes
uByte bmAttributes
Definition: usb.h:539
usb_endpoint
Definition: usbdi.h:140
usb_endpoint::toggle_next
uint8_t toggle_next
Definition: usbdi.h:150
usb_endpoint::isoc_next
uint16_t isoc_next
Definition: usbdi.h:148
usb_endpoint::methods
const struct usb_pipe_methods * methods
Definition: usbdi.h:146
usb_endpoint::edesc
struct usb_endpoint_descriptor * edesc
Definition: usbdi.h:144
usb_hub_descriptor_min
Definition: usb.h:646
usb_hub_descriptor_min::bNbrPorts
uByte bNbrPorts
Definition: usb.h:649
usb_hub_descriptor_min::bPwrOn2PwrGood
uByte bPwrOn2PwrGood
Definition: usb.h:651
usb_hub_descriptor_min::bHubContrCurrent
uByte bHubContrCurrent
Definition: usb.h:652
usb_hub_descriptor_min::bDescLength
uByte bDescLength
Definition: usb.h:647
usb_hub_descriptor_min::wHubCharacteristics
uWord wHubCharacteristics
Definition: usb.h:650
usb_hub_descriptor_min::DeviceRemovable
uByte DeviceRemovable[1]
Definition: usb.h:653
usb_hub_descriptor_min::bDescriptorType
uByte bDescriptorType
Definition: usb.h:648
usb_hw_ep_profile
Definition: usb_controller.h:175
usb_hw_ep_profile::max_in_frame_size
uint16_t max_in_frame_size
Definition: usb_controller.h:176
usb_hw_ep_profile::max_out_frame_size
uint16_t max_out_frame_size
Definition: usb_controller.h:177
usb_interface_descriptor
Definition: usb.h:402
usb_interface_descriptor::bDescriptorType
uByte bDescriptorType
Definition: usb.h:404
usb_page_search
Definition: usb_busdma.h:77
usb_page_search::buffer
void * buffer
Definition: usb_busdma.h:78
usb_page_search::length
usb_size_t length
Definition: usb_busdma.h:82
usb_pipe_methods
Definition: usb_controller.h:157
usb_pipe_methods::open
void(* open)(struct usb_xfer *)
Definition: usb_controller.h:160
usb_port_status::wPortStatus
uWord wPortStatus
Definition: usb.h:704
usb_port_status::wPortChange
uWord wPortChange
Definition: usb.h:735
usb_setup_params
Definition: usb_transfer.h:97
usb_setup_params::hc_max_frame_size
uint32_t hc_max_frame_size
Definition: usb_transfer.h:115
usb_setup_params::buf
void * buf
Definition: usb_transfer.h:108
usb_setup_params::size
usb_size_t size[7]
Definition: usb_transfer.h:111
usb_setup_params::hc_max_packet_count
uint8_t hc_max_packet_count
Definition: usb_transfer.h:117
usb_setup_params::udev
struct usb_device * udev
Definition: usb_transfer.h:104
usb_setup_params::curr_xfer
struct usb_xfer * curr_xfer
Definition: usb_transfer.h:105
usb_setup_params::hc_max_packet_size
uint16_t hc_max_packet_size
Definition: usb_transfer.h:116
usb_setup_params::err
usb_error_t err
Definition: usb_transfer.h:120
usb_setup_params::methods
const struct usb_pipe_methods * methods
Definition: usb_transfer.h:107
usb_status
Definition: usb.h:685
usb_xfer_flags_int::control_hdr
uint8_t control_hdr
Definition: usb_core.h:104
usb_xfer_flags_int::usb_mode
enum usb_hc_mode usb_mode
Definition: usb_core.h:91
usb_xfer_flags_int::control_act
uint8_t control_act
Definition: usb_core.h:106
usb_xfer_flags_int::short_frames_ok
uint8_t short_frames_ok
Definition: usb_core.h:110
usb_xfer_flags_int::isochronous_xfr
uint8_t isochronous_xfr
Definition: usb_core.h:120
usb_xfer_flags_int::control_stall
uint8_t control_stall
Definition: usb_core.h:107
usb_xfer_flags_int::control_xfr
uint8_t control_xfr
Definition: usb_core.h:103
usb_xfer_flags::force_short_xfer
uint8_t force_short_xfer
Definition: usbdi.h:196
usb_xfer_root::bus
struct usb_bus * bus
Definition: usb_transfer.h:78
usb_xfer_root::udev
struct usb_device * udev
Definition: usb_transfer.h:79
usb_xfer
Definition: usb_core.h:132
usb_xfer::frlengths
usb_frlength_t * frlengths
Definition: usb_core.h:150
usb_xfer::nframes
usb_frcount_t nframes
Definition: usb_core.h:162
usb_xfer::frbuffers
struct usb_page_cache * frbuffers
Definition: usb_core.h:151
usb_xfer::max_packet_count
uint8_t max_packet_count
Definition: usb_core.h:175
usb_xfer::td_start
void * td_start[2]
Definition: usb_core.h:143
usb_xfer::timeout
usb_timeout_t timeout
Definition: usb_core.h:158
usb_xfer::aframes
usb_frcount_t aframes
Definition: usb_core.h:163
usb_xfer::endpoint
struct usb_endpoint * endpoint
Definition: usb_core.h:140
usb_xfer::flags_int
struct usb_xfer_flags_int flags_int
Definition: usb_core.h:182
usb_xfer::address
uint8_t address
Definition: usb_core.h:173
usb_xfer::flags
struct usb_xfer_flags flags
Definition: usb_core.h:181
usb_xfer::td_transfer_cache
void * td_transfer_cache
Definition: usb_core.h:146
usb_xfer::xroot
struct usb_xfer_root * xroot
Definition: usb_core.h:141
usb_xfer::max_frame_size
uint16_t max_frame_size
Definition: usb_core.h:168
usb_xfer::td_transfer_last
void * td_transfer_last
Definition: usb_core.h:145
usb_xfer::td_transfer_first
void * td_transfer_first
Definition: usb_core.h:144
usb_xfer::max_packet_size
uint16_t max_packet_size
Definition: usb_core.h:167
usb_xfer::sumlen
usb_frlength_t sumlen
Definition: usb_core.h:156
usb_xfer::endpointno
uint8_t endpointno
Definition: usb_core.h:174
DPRINTF
#define DPRINTF(...)
Definition: umass.c:179
musbotg_hub_temp::ps
struct usb_port_status ps
Definition: musb_otg.h:368
musbotg_hub_temp::wValue
uWord wValue
Definition: musb_otg.h:367
UE_INTERRUPT
#define UE_INTERRUPT
Definition: usb.h:544
UR_SET_CONFIG
#define UR_SET_CONFIG
Definition: usb.h:219
UPS_C_PORT_RESET
#define UPS_C_PORT_RESET
Definition: usb.h:740
UDSUBCLASS_HUB
#define UDSUBCLASS_HUB
Definition: usb.h:374
UC_SELF_POWERED
#define UC_SELF_POWERED
Definition: usb.h:395
UT_WRITE_INTERFACE
#define UT_WRITE_INTERFACE
Definition: usb.h:170
UR_SET_DESCRIPTOR
#define UR_SET_DESCRIPTOR
Definition: usb.h:217
UE_ADDR
#define UE_ADDR
Definition: usb.h:536
UE_BULK
#define UE_BULK
Definition: usb.h:543
UHF_PORT_POWER
#define UHF_PORT_POWER
Definition: usb.h:254
UF_ENDPOINT_HALT
#define UF_ENDPOINT_HALT
Definition: usb.h:238
UR_GET_CONFIG
#define UR_GET_CONFIG
Definition: usb.h:218
UT_WRITE_CLASS_OTHER
#define UT_WRITE_CLASS_OTHER
Definition: usb.h:178
UISUBCLASS_HUB
#define UISUBCLASS_HUB
Definition: usb.h:480
UT_WRITE_CLASS_DEVICE
#define UT_WRITE_CLASS_DEVICE
Definition: usb.h:176
UR_SET_ADDRESS
#define UR_SET_ADDRESS
Definition: usb.h:193
UT_WRITE_DEVICE
#define UT_WRITE_DEVICE
Definition: usb.h:169
UDESC_CONFIG
#define UDESC_CONFIG
Definition: usb.h:196
UR_GET_INTERFACE
#define UR_GET_INTERFACE
Definition: usb.h:220
UPS_C_OVERCURRENT_INDICATOR
#define UPS_C_OVERCURRENT_INDICATOR
Definition: usb.h:739
UDCLASS_HUB
#define UDCLASS_HUB
Definition: usb.h:373
UR_CLEAR_TT_BUFFER
#define UR_CLEAR_TT_BUFFER
Definition: usb.h:228
UR_GET_STATUS
#define UR_GET_STATUS
Definition: usb.h:190
UHF_C_PORT_SUSPEND
#define UHF_C_PORT_SUSPEND
Definition: usb.h:259
UR_CLEAR_FEATURE
#define UR_CLEAR_FEATURE
Definition: usb.h:191
UDESC_ENDPOINT
#define UDESC_ENDPOINT
Definition: usb.h:200
UT_READ_CLASS_INTERFACE
#define UT_READ_CLASS_INTERFACE
Definition: usb.h:173
UDESC_DEVICE_QUALIFIER
#define UDESC_DEVICE_QUALIFIER
Definition: usb.h:201
UE_GET_ADDR
#define UE_GET_ADDR(a)
Definition: usb.h:538
UDS_SELF_POWERED
#define UDS_SELF_POWERED
Definition: usb.h:688
UHF_PORT_TEST
#define UHF_PORT_TEST
Definition: usb.h:262
UPS_PORT_POWER
#define UPS_PORT_POWER
Definition: usb.h:727
UDESC_HUB
#define UDESC_HUB
Definition: usb.h:214
UF_DEVICE_REMOTE_WAKEUP
#define UF_DEVICE_REMOTE_WAKEUP
Definition: usb.h:239
UT_READ_VENDOR_INTERFACE
#define UT_READ_VENDOR_INTERFACE
Definition: usb.h:181
UDESC_STRING
#define UDESC_STRING
Definition: usb.h:197
UHF_C_PORT_OVER_CURRENT
#define UHF_C_PORT_OVER_CURRENT
Definition: usb.h:260
UHF_PORT_SUSPEND
#define UHF_PORT_SUSPEND
Definition: usb.h:250
UR_STOP_TT
#define UR_STOP_TT
Definition: usb.h:231
UE_DIR_IN
#define UE_DIR_IN
Definition: usb.h:531
UR_SYNCH_FRAME
#define UR_SYNCH_FRAME
Definition: usb.h:222
UT_READ_DEVICE
#define UT_READ_DEVICE
Definition: usb.h:166
UDPROTO_HSHUBSTT
#define UDPROTO_HSHUBSTT
Definition: usb.h:376
UR_GET_TT_STATE
#define UR_GET_TT_STATE
Definition: usb.h:230
UPS_PORT_MODE_DEVICE
#define UPS_PORT_MODE_DEVICE
Definition: usb.h:734
UE_XFERTYPE
#define UE_XFERTYPE
Definition: usb.h:540
UHF_PORT_ENABLE
#define UHF_PORT_ENABLE
Definition: usb.h:249
UICLASS_HUB
#define UICLASS_HUB
Definition: usb.h:479
UDESC_DEVICE
#define UDESC_DEVICE
Definition: usb.h:195
UDESC_INTERFACE
#define UDESC_INTERFACE
Definition: usb.h:199
UPS_HIGH_SPEED
#define UPS_HIGH_SPEED
Definition: usb.h:730
usb_dev_speed
usb_dev_speed
Definition: usb.h:751
USB_SPEED_LOW
@ USB_SPEED_LOW
Definition: usb.h:753
USB_SPEED_FULL
@ USB_SPEED_FULL
Definition: usb.h:754
USB_SPEED_HIGH
@ USB_SPEED_HIGH
Definition: usb.h:755
UR_RESET_TT
#define UR_RESET_TT
Definition: usb.h:229
UE_DIR_OUT
#define UE_DIR_OUT
Definition: usb.h:532
USB_MODE_HOST
@ USB_MODE_HOST
Definition: usb.h:778
USB_MODE_DEVICE
@ USB_MODE_DEVICE
Definition: usb.h:779
UHD_OC_INDIVIDUAL
#define UHD_OC_INDIVIDUAL
Definition: usb.h:614
UPS_PORT_ENABLED
#define UPS_PORT_ENABLED
Definition: usb.h:706
UT_WRITE_ENDPOINT
#define UT_WRITE_ENDPOINT
Definition: usb.h:171
UT_READ_CLASS_DEVICE
#define UT_READ_CLASS_DEVICE
Definition: usb.h:172
UHF_PORT_RESET
#define UHF_PORT_RESET
Definition: usb.h:252
UDPROTO_FSHUB
#define UDPROTO_FSHUB
Definition: usb.h:375
UR_SET_INTERFACE
#define UR_SET_INTERFACE
Definition: usb.h:221
UT_WRITE_CLASS_INTERFACE
#define UT_WRITE_CLASS_INTERFACE
Definition: usb.h:177
UT_READ_CLASS_OTHER
#define UT_READ_CLASS_OTHER
Definition: usb.h:174
UE_CONTROL
#define UE_CONTROL
Definition: usb.h:541
UHF_PORT_INDICATOR
#define UHF_PORT_INDICATOR
Definition: usb.h:263
UT_READ_ENDPOINT
#define UT_READ_ENDPOINT
Definition: usb.h:168
UHF_C_PORT_RESET
#define UHF_C_PORT_RESET
Definition: usb.h:261
USB_REV_2_0
@ USB_REV_2_0
Definition: usb.h:768
UPS_C_SUSPEND
#define UPS_C_SUSPEND
Definition: usb.h:738
UHD_PWR_NO_SWITCH
#define UHD_PWR_NO_SWITCH
Definition: usb.h:610
UPS_C_CONNECT_STATUS
#define UPS_C_CONNECT_STATUS
Definition: usb.h:736
UPS_CURRENT_CONNECT_STATUS
#define UPS_CURRENT_CONNECT_STATUS
Definition: usb.h:705
UE_ISOCHRONOUS
#define UE_ISOCHRONOUS
Definition: usb.h:542
UHF_C_PORT_ENABLE
#define UHF_C_PORT_ENABLE
Definition: usb.h:258
UT_WRITE_VENDOR_INTERFACE
#define UT_WRITE_VENDOR_INTERFACE
Definition: usb.h:185
UR_SET_FEATURE
#define UR_SET_FEATURE
Definition: usb.h:192
UPS_OVERCURRENT_INDICATOR
#define UPS_OVERCURRENT_INDICATOR
Definition: usb.h:708
UPS_SUSPEND
#define UPS_SUSPEND
Definition: usb.h:707
UT_READ_INTERFACE
#define UT_READ_INTERFACE
Definition: usb.h:167
UR_GET_DESCRIPTOR
#define UR_GET_DESCRIPTOR
Definition: usb.h:194
UHF_C_PORT_CONNECTION
#define UHF_C_PORT_CONNECTION
Definition: usb.h:257
usb_bus.h
usbd_get_page
void usbd_get_page(struct usb_page_cache *pc, usb_frlength_t offset, struct usb_page_search *res)
Definition: usb_busdma.c:86
usbd_copy_in
void usbd_copy_in(struct usb_page_cache *cache, usb_frlength_t offset, const void *ptr, usb_frlength_t len)
Definition: usb_busdma.c:166
usbd_copy_out
void usbd_copy_out(struct usb_page_cache *cache, usb_frlength_t offset, void *ptr, usb_frlength_t len)
Definition: usb_busdma.c:283
usb_busdma.h
usb_controller.h
USB_HW_POWER_RESUME
#define USB_HW_POWER_RESUME
Definition: usb_controller.h:102
USB_HW_POWER_SUSPEND
#define USB_HW_POWER_SUSPEND
Definition: usb_controller.h:98
USB_HW_POWER_SHUTDOWN
#define USB_HW_POWER_SHUTDOWN
Definition: usb_controller.h:106
usb_string_lang_en
const struct usb_string_lang usb_string_lang_en
Definition: usb_core.c:63
usb_core.h
USB_P2U
#define USB_P2U(ptr)
Definition: usb_core.h:60
USB_BUS_LOCK
#define USB_BUS_LOCK(_b)
Definition: usb_core.h:45
USB_ADD_BYTES
#define USB_ADD_BYTES(ptr, size)
Definition: usb_core.h:64
USB_BUS_UNLOCK
#define USB_BUS_UNLOCK(_b)
Definition: usb_core.h:46
USB_BUS_LOCK_ASSERT
#define USB_BUS_LOCK_ASSERT(_b, _t)
Definition: usb_core.h:47
usb_debug.h
usbd_get_speed
enum usb_dev_speed usbd_get_speed(struct usb_device *udev)
Definition: usb_device.c:2589
usb_device.h
USETW
#define USETW(w, v)
Definition: usb_endian.h:77
UGETW
#define UGETW(w)
Definition: usb_endian.h:53
USB_HOST_ALIGN
#define USB_HOST_ALIGN
Definition: usb_freebsd.h:70
uhub_root_intr
void uhub_root_intr(struct usb_bus *bus, const uint8_t *ptr, uint8_t len)
Definition: usb_hub.c:960
usb_hub.h
pptr
void ** pptr
Definition: usb_if.m:52
offset
uint16_t offset
Definition: usb_if.m:54
req
const void * req
Definition: usb_if.m:51
usb_process.h
usbd_transfer_setup_sub
void usbd_transfer_setup_sub(struct usb_setup_params *parm)
Definition: usb_transfer.c:457
usbd_transfer_done
void usbd_transfer_done(struct usb_xfer *xfer, usb_error_t error)
Definition: usb_transfer.c:2593
usbd_transfer_enqueue
void usbd_transfer_enqueue(struct usb_xfer_queue *pq, struct usb_xfer *xfer)
Definition: usb_transfer.c:2569
usbd_xfer_get_isochronous_start_frame
uint8_t usbd_xfer_get_isochronous_start_frame(struct usb_xfer *xfer, uint32_t frame_curr, uint32_t frame_min, uint32_t frame_ms, uint32_t frame_mask, uint32_t *p_frame_start)
Definition: usb_transfer.c:3692
usbd_transfer_timeout_ms
void usbd_transfer_timeout_ms(struct usb_xfer *xfer, void(*cb)(void *arg), usb_timeout_t ms)
Definition: usb_transfer.c:2934
usb_transfer.h
usb_pause_mtx
void usb_pause_mtx(struct mtx *mtx, int timo)
Definition: usb_util.c:135
usb_util.h
usb_error_t
usb_error_t
Definition: usbdi.h:45
USB_ERR_NORMAL_COMPLETION
@ USB_ERR_NORMAL_COMPLETION
Definition: usbdi.h:46
USB_ERR_STALLED
@ USB_ERR_STALLED
Definition: usbdi.h:68
USB_ERR_IOERROR
@ USB_ERR_IOERROR
Definition: usbdi.h:64
USB_ERR_CANCELLED
@ USB_ERR_CANCELLED
Definition: usbdi.h:51
USB_ERR_INVAL
@ USB_ERR_INVAL
Definition: usbdi.h:49
USB_ERR_TIMEOUT
@ USB_ERR_TIMEOUT
Definition: usbdi.h:66