37#define MUSB2_MAX_DEVICES USB_MAX_DEVICES
41#define MUSB2_REG_FADDR 0x0000
42#define MUSB2_MASK_FADDR 0x7F
44#define MUSB2_REG_POWER 0x0001
45#define MUSB2_MASK_SUSPM_ENA 0x01
46#define MUSB2_MASK_SUSPMODE 0x02
47#define MUSB2_MASK_RESUME 0x04
48#define MUSB2_MASK_RESET 0x08
49#define MUSB2_MASK_HSMODE 0x10
50#define MUSB2_MASK_HSENAB 0x20
51#define MUSB2_MASK_SOFTC 0x40
52#define MUSB2_MASK_ISOUPD 0x80
56#define MUSB2_REG_INTTX 0x0002
57#define MUSB2_REG_INTRX 0x0004
58#define MUSB2_REG_INTTXE 0x0006
59#define MUSB2_REG_INTRXE 0x0008
60#define MUSB2_MASK_EPINT(epn) (1 << (epn))
64#define MUSB2_REG_INTUSB 0x000A
65#define MUSB2_MASK_ISUSP 0x01
66#define MUSB2_MASK_IRESUME 0x02
67#define MUSB2_MASK_IRESET 0x04
68#define MUSB2_MASK_IBABBLE 0x04
69#define MUSB2_MASK_ISOF 0x08
70#define MUSB2_MASK_ICONN 0x10
71#define MUSB2_MASK_IDISC 0x20
72#define MUSB2_MASK_ISESSRQ 0x40
73#define MUSB2_MASK_IVBUSERR 0x80
75#define MUSB2_REG_INTUSBE 0x000B
76#define MUSB2_REG_FRAME 0x000C
77#define MUSB2_MASK_FRAME 0x3FF
79#define MUSB2_REG_EPINDEX 0x000E
80#define MUSB2_MASK_EPINDEX 0x0F
82#define MUSB2_REG_TESTMODE 0x000F
83#define MUSB2_MASK_TSE0_NAK 0x01
84#define MUSB2_MASK_TJ 0x02
85#define MUSB2_MASK_TK 0x04
86#define MUSB2_MASK_TPACKET 0x08
87#define MUSB2_MASK_TFORCE_HS 0x10
88#define MUSB2_MASK_TFORCE_LS 0x20
89#define MUSB2_MASK_TFIFO_ACC 0x40
90#define MUSB2_MASK_TFORCE_HC 0x80
92#define MUSB2_REG_INDEXED_CSR 0x0010
94#define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR)
95#define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR)
96#define MUSB2_MASK_PKTSIZE 0x03FF
97#define MUSB2_MASK_PKTMULT 0xFC00
99#define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR)
100#define MUSB2_MASK_CSRL_TXPKTRDY 0x01
101#define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02
102#define MUSB2_MASK_CSRL_TXUNDERRUN 0x04
103#define MUSB2_MASK_CSRL_TXERROR 0x04
104#define MUSB2_MASK_CSRL_TXFFLUSH 0x08
105#define MUSB2_MASK_CSRL_TXSENDSTALL 0x10
106#define MUSB2_MASK_CSRL_TXSETUPPKT 0x10
107#define MUSB2_MASK_CSRL_TXSENTSTALL 0x20
108#define MUSB2_MASK_CSRL_TXSTALLED 0x20
109#define MUSB2_MASK_CSRL_TXDT_CLR 0x40
110#define MUSB2_MASK_CSRL_TXINCOMP 0x80
111#define MUSB2_MASK_CSRL_TXNAKTO 0x80
114#define MUSB2_MASK_CSR0L_RXPKTRDY 0x01
115#define MUSB2_MASK_CSR0L_TXPKTRDY 0x02
116#define MUSB2_MASK_CSR0L_SENTSTALL 0x04
117#define MUSB2_MASK_CSR0L_DATAEND 0x08
118#define MUSB2_MASK_CSR0L_SETUPEND 0x10
119#define MUSB2_MASK_CSR0L_SENDSTALL 0x20
120#define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40
121#define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80
124#define MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02
125#define MUSB2_MASK_CSR0L_RXSTALL 0x04
126#define MUSB2_MASK_CSR0L_SETUPPKT 0x08
127#define MUSB2_MASK_CSR0L_ERROR 0x10
128#define MUSB2_MASK_CSR0L_REQPKT 0x20
129#define MUSB2_MASK_CSR0L_STATUSPKT 0x40
130#define MUSB2_MASK_CSR0L_NAKTIMO 0x80
132#define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR)
133#define MUSB2_MASK_CSRH_TXDT_VAL 0x01
134#define MUSB2_MASK_CSRH_TXDT_WREN 0x02
135#define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04
136#define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08
137#define MUSB2_MASK_CSRH_TXDMAREQENA 0x10
138#define MUSB2_MASK_CSRH_RXMODE 0x00
139#define MUSB2_MASK_CSRH_TXMODE 0x20
140#define MUSB2_MASK_CSRH_TXISO 0x40
141#define MUSB2_MASK_CSRH_TXAUTOSET 0x80
143#define MUSB2_MASK_CSR0H_FFLUSH 0x01
144#define MUSB2_MASK_CSR0H_DT 0x02
145#define MUSB2_MASK_CSR0H_DT_WREN 0x04
146#define MUSB2_MASK_CSR0H_PING_DIS 0x08
148#define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR)
149#define MUSB2_MASK_CSRL_RXPKTRDY 0x01
150#define MUSB2_MASK_CSRL_RXFIFOFULL 0x02
151#define MUSB2_MASK_CSRL_RXOVERRUN 0x04
152#define MUSB2_MASK_CSRL_RXERROR 0x04
153#define MUSB2_MASK_CSRL_RXDATAERR 0x08
154#define MUSB2_MASK_CSRL_RXNAKTO 0x08
155#define MUSB2_MASK_CSRL_RXFFLUSH 0x10
156#define MUSB2_MASK_CSRL_RXSENDSTALL 0x20
157#define MUSB2_MASK_CSRL_RXREQPKT 0x20
158#define MUSB2_MASK_CSRL_RXSENTSTALL 0x40
159#define MUSB2_MASK_CSRL_RXSTALL 0x40
160#define MUSB2_MASK_CSRL_RXDT_CLR 0x80
162#define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR)
163#define MUSB2_MASK_CSRH_RXINCOMP 0x01
164#define MUSB2_MASK_CSRH_RXDT_VAL 0x02
165#define MUSB2_MASK_CSRH_RXDT_WREN 0x04
166#define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08
167#define MUSB2_MASK_CSRH_RXNYET 0x10
168#define MUSB2_MASK_CSRH_RXDMAREQENA 0x20
169#define MUSB2_MASK_CSRH_RXISO 0x40
170#define MUSB2_MASK_CSRH_RXAUTOREQ 0x40
171#define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80
173#define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR)
174#define MUSB2_MASK_RXCOUNT 0xFFFF
176#define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR)
177#define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR)
180#define MUSB2_MASK_TI_SPEED 0xC0
181#define MUSB2_MASK_TI_SPEED_LO 0xC0
182#define MUSB2_MASK_TI_SPEED_FS 0x80
183#define MUSB2_MASK_TI_SPEED_HS 0x40
184#define MUSB2_MASK_TI_PROTO_CTRL 0x00
185#define MUSB2_MASK_TI_PROTO_ISOC 0x10
186#define MUSB2_MASK_TI_PROTO_BULK 0x20
187#define MUSB2_MASK_TI_PROTO_INTR 0x30
188#define MUSB2_MASK_TI_EP_NUM 0x0F
190#define MUSB2_REG_TXNAKLIMIT (0x000B + MUSB2_REG_INDEXED_CSR)
191#define MUSB2_REG_RXNAKLIMIT (0x000D + MUSB2_REG_INDEXED_CSR)
192#define MUSB2_MASK_NAKLIMIT 0xFF
194#define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR)
195#define MUSB2_MASK_RX_FSIZE 0xF0
196#define MUSB2_MASK_TX_FSIZE 0x0F
198#define MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n)))
200#define MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR)
201#define MUSB2_MASK_CD_UTMI_DW 0x01
202#define MUSB2_MASK_CD_SOFTCONE 0x02
203#define MUSB2_MASK_CD_DYNFIFOSZ 0x04
204#define MUSB2_MASK_CD_HBTXE 0x08
205#define MUSB2_MASK_CD_HBRXE 0x10
206#define MUSB2_MASK_CD_BIGEND 0x20
207#define MUSB2_MASK_CD_MPTXE 0x40
208#define MUSB2_MASK_CD_MPRXE 0x80
212#define MUSB2_REG_DEVCTL 0x0060
213#define MUSB2_MASK_SESS 0x01
214#define MUSB2_MASK_HOSTREQ 0x02
215#define MUSB2_MASK_HOSTMD 0x04
216#define MUSB2_MASK_VBUS0 0x08
217#define MUSB2_MASK_VBUS1 0x10
218#define MUSB2_MASK_LSDEV 0x20
219#define MUSB2_MASK_FSDEV 0x40
220#define MUSB2_MASK_BDEV 0x80
222#define MUSB2_REG_MISC 0x0061
223#define MUSB2_MASK_RXEDMA 0x01
224#define MUSB2_MASK_TXEDMA 0x02
226#define MUSB2_REG_TXFIFOSZ 0x0062
227#define MUSB2_REG_RXFIFOSZ 0x0063
228#define MUSB2_MASK_FIFODB 0x10
229#define MUSB2_MASK_FIFOSZ 0x0F
230#define MUSB2_VAL_FIFOSZ_8 0
231#define MUSB2_VAL_FIFOSZ_16 1
232#define MUSB2_VAL_FIFOSZ_32 2
233#define MUSB2_VAL_FIFOSZ_64 3
234#define MUSB2_VAL_FIFOSZ_128 4
235#define MUSB2_VAL_FIFOSZ_256 5
236#define MUSB2_VAL_FIFOSZ_512 6
237#define MUSB2_VAL_FIFOSZ_1024 7
238#define MUSB2_VAL_FIFOSZ_2048 8
239#define MUSB2_VAL_FIFOSZ_4096 9
241#define MUSB2_REG_TXFIFOADD 0x0064
242#define MUSB2_REG_RXFIFOADD 0x0066
243#define MUSB2_MASK_FIFOADD 0xFFF
245#define MUSB2_REG_VSTATUS 0x0068
246#define MUSB2_REG_VCONTROL 0x0068
247#define MUSB2_REG_HWVERS 0x006C
248#define MUSB2_REG_ULPI_BASE 0x0070
250#define MUSB2_REG_EPINFO 0x0078
251#define MUSB2_MASK_NRXEP 0xF0
252#define MUSB2_MASK_NTXEP 0x0F
254#define MUSB2_REG_RAMINFO 0x0079
255#define MUSB2_REG_LINKINFO 0x007A
257#define MUSB2_REG_VPLEN 0x007B
258#define MUSB2_MASK_VPLEN 0xFF
260#define MUSB2_REG_HS_EOF1 0x007C
261#define MUSB2_REG_FS_EOF1 0x007D
262#define MUSB2_REG_LS_EOF1 0x007E
263#define MUSB2_REG_SOFT_RST 0x007F
264#define MUSB2_MASK_SRST 0x01
265#define MUSB2_MASK_SRSTX 0x02
267#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n))
268#define MUSB2_REG_RXDBDIS 0x0340
269#define MUSB2_REG_TXDBDIS 0x0342
270#define MUSB2_MASK_DB(n) (1 << (n))
272#define MUSB2_REG_CHIRPTO 0x0344
273#define MUSB2_REG_HSRESUM 0x0346
277#define MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n)))
278#define MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n)))
279#define MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n)))
280#define MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n)))
281#define MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n)))
282#define MUSB2_REG_RXHUBPORT(n) (0x0087 + (8*(n)))
284#define MUSB2_EP_MAX 16
286#define MUSB2_DEVICE_MODE 0
287#define MUSB2_HOST_MODE 1
289#define MUSB2_READ_2(sc, reg) \
290 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
292#define MUSB2_WRITE_2(sc, reg, data) \
293 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
295#define MUSB2_READ_1(sc, reg) \
296 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
298#define MUSB2_WRITE_1(sc, reg, data) \
299 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
440 uint16_t rxstat, uint16_t txstat, uint8_t stat);
void musbotg_uninit(struct musbotg_softc *sc)
#define MUSB2_MAX_DEVICES
void musbotg_connect_interrupt(struct musbotg_softc *sc)
struct musbotg_config_desc __packed
void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
void musbotg_interrupt(struct musbotg_softc *sc, uint16_t rxstat, uint16_t txstat, uint8_t stat)
usb_error_t musbotg_init(struct musbotg_softc *sc)
uint8_t() musbotg_cmd_t(struct musbotg_td *td)
struct usb_interface_descriptor ifcd
struct usb_endpoint_descriptor endpd
struct usb_config_descriptor confd
struct musbotg_softc * sc
uint8_t status_high_speed
uint8_t change_over_current
uint8_t port_over_current
void(* sc_clocks_on)(void *arg)
struct resource * sc_io_res
void(* sc_ep_int_set)(struct musbotg_softc *sc, int ep, int on)
union musbotg_hub_temp sc_hub_temp
struct usb_device * sc_devices[MUSB2_MAX_DEVICES]
bus_space_tag_t sc_io_tag
bus_space_handle_t sc_io_hdl
struct resource * sc_irq_res
void(* sc_clocks_off)(void *arg)
uint32_t sc_bounce_buf[(1024 *3)/4]
struct usb_hw_ep_profile sc_hw_ep_profile[MUSB2_EP_MAX]
struct musbotg_flags sc_flags
const struct musb_otg_ep_cfg * sc_ep_cfg
struct usb_page_cache * pc
struct musbotg_td * td_next
uint8_t transaction_started
struct musbotg_td * obj_next
uint8_t support_multi_buffer
struct usb_page_cache * pc
struct usb_port_status ps