Go to the source code of this file.
Data Structures | |
| struct | musbotg_dma |
| struct | musbotg_td |
| struct | musbotg_std_temp |
| struct | musbotg_config_desc |
| union | musbotg_hub_temp |
| struct | musbotg_flags |
| struct | musb_otg_ep_cfg |
| struct | musbotg_softc |
Macros | |
| #define | MUSB2_MAX_DEVICES USB_MAX_DEVICES |
| #define | MUSB2_REG_FADDR 0x0000 /* function address register */ |
| #define | MUSB2_MASK_FADDR 0x7F |
| #define | MUSB2_REG_POWER 0x0001 /* power register */ |
| #define | MUSB2_MASK_SUSPM_ENA 0x01 |
| #define | MUSB2_MASK_SUSPMODE 0x02 |
| #define | MUSB2_MASK_RESUME 0x04 |
| #define | MUSB2_MASK_RESET 0x08 |
| #define | MUSB2_MASK_HSMODE 0x10 |
| #define | MUSB2_MASK_HSENAB 0x20 |
| #define | MUSB2_MASK_SOFTC 0x40 |
| #define | MUSB2_MASK_ISOUPD 0x80 |
| #define | MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */ |
| #define | MUSB2_REG_INTRX 0x0004 /* receive interrupt register */ |
| #define | MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */ |
| #define | MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */ |
| #define | MUSB2_MASK_EPINT(epn) (1 << (epn)) /* epn = [0..15] */ |
| #define | MUSB2_REG_INTUSB 0x000A /* USB interrupt register */ |
| #define | MUSB2_MASK_ISUSP 0x01 |
| #define | MUSB2_MASK_IRESUME 0x02 |
| #define | MUSB2_MASK_IRESET 0x04 |
| #define | MUSB2_MASK_IBABBLE 0x04 |
| #define | MUSB2_MASK_ISOF 0x08 |
| #define | MUSB2_MASK_ICONN 0x10 |
| #define | MUSB2_MASK_IDISC 0x20 |
| #define | MUSB2_MASK_ISESSRQ 0x40 |
| #define | MUSB2_MASK_IVBUSERR 0x80 |
| #define | MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */ |
| #define | MUSB2_REG_FRAME 0x000C /* USB frame register */ |
| #define | MUSB2_MASK_FRAME 0x3FF /* 0..1023 */ |
| #define | MUSB2_REG_EPINDEX 0x000E /* endpoint index register */ |
| #define | MUSB2_MASK_EPINDEX 0x0F |
| #define | MUSB2_REG_TESTMODE 0x000F /* test mode register */ |
| #define | MUSB2_MASK_TSE0_NAK 0x01 |
| #define | MUSB2_MASK_TJ 0x02 |
| #define | MUSB2_MASK_TK 0x04 |
| #define | MUSB2_MASK_TPACKET 0x08 |
| #define | MUSB2_MASK_TFORCE_HS 0x10 |
| #define | MUSB2_MASK_TFORCE_LS 0x20 |
| #define | MUSB2_MASK_TFIFO_ACC 0x40 |
| #define | MUSB2_MASK_TFORCE_HC 0x80 |
| #define | MUSB2_REG_INDEXED_CSR 0x0010 /* EP control status register offset */ |
| #define | MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */ |
| #define | MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */ |
| #define | MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_CSRL_TXPKTRDY 0x01 |
| #define | MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02 |
| #define | MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */ |
| #define | MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_TXFFLUSH 0x08 |
| #define | MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */ |
| #define | MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */ |
| #define | MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_TXDT_CLR 0x40 |
| #define | MUSB2_MASK_CSRL_TXINCOMP 0x80 /* Device mode */ |
| #define | MUSB2_MASK_CSRL_TXNAKTO 0x80 /* Host mode */ |
| #define | MUSB2_MASK_CSR0L_RXPKTRDY 0x01 |
| #define | MUSB2_MASK_CSR0L_TXPKTRDY 0x02 |
| #define | MUSB2_MASK_CSR0L_SENTSTALL 0x04 |
| #define | MUSB2_MASK_CSR0L_DATAEND 0x08 |
| #define | MUSB2_MASK_CSR0L_SETUPEND 0x10 |
| #define | MUSB2_MASK_CSR0L_SENDSTALL 0x20 |
| #define | MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40 |
| #define | MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80 |
| #define | MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02 |
| #define | MUSB2_MASK_CSR0L_RXSTALL 0x04 |
| #define | MUSB2_MASK_CSR0L_SETUPPKT 0x08 |
| #define | MUSB2_MASK_CSR0L_ERROR 0x10 |
| #define | MUSB2_MASK_CSR0L_REQPKT 0x20 |
| #define | MUSB2_MASK_CSR0L_STATUSPKT 0x40 |
| #define | MUSB2_MASK_CSR0L_NAKTIMO 0x80 |
| #define | MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */ |
| #define | MUSB2_MASK_CSRH_TXDT_WREN 0x02 /* Host Mode */ |
| #define | MUSB2_MASK_CSRH_TXDMAREQMODE 0x04 |
| #define | MUSB2_MASK_CSRH_TXDT_SWITCH 0x08 |
| #define | MUSB2_MASK_CSRH_TXDMAREQENA 0x10 |
| #define | MUSB2_MASK_CSRH_RXMODE 0x00 |
| #define | MUSB2_MASK_CSRH_TXMODE 0x20 |
| #define | MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */ |
| #define | MUSB2_MASK_CSRH_TXAUTOSET 0x80 |
| #define | MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */ |
| #define | MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */ |
| #define | MUSB2_MASK_CSR0H_DT_WREN 0x04 /* Host Side */ |
| #define | MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */ |
| #define | MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_CSRL_RXPKTRDY 0x01 |
| #define | MUSB2_MASK_CSRL_RXFIFOFULL 0x02 |
| #define | MUSB2_MASK_CSRL_RXOVERRUN 0x04 /* Device Mode */ |
| #define | MUSB2_MASK_CSRL_RXERROR 0x04 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_RXDATAERR 0x08 /* Device Mode */ |
| #define | MUSB2_MASK_CSRL_RXNAKTO 0x08 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_RXFFLUSH 0x10 |
| #define | MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */ |
| #define | MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */ |
| #define | MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */ |
| #define | MUSB2_MASK_CSRL_RXDT_CLR 0x80 |
| #define | MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_CSRH_RXINCOMP 0x01 |
| #define | MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */ |
| #define | MUSB2_MASK_CSRH_RXDT_WREN 0x04 /* Host Mode */ |
| #define | MUSB2_MASK_CSRH_RXDMAREQMODE 0x08 |
| #define | MUSB2_MASK_CSRH_RXNYET 0x10 |
| #define | MUSB2_MASK_CSRH_RXDMAREQENA 0x20 |
| #define | MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */ |
| #define | MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */ |
| #define | MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80 |
| #define | MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_RXCOUNT 0xFFFF |
| #define | MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_TI_SPEED 0xC0 |
| #define | MUSB2_MASK_TI_SPEED_LO 0xC0 |
| #define | MUSB2_MASK_TI_SPEED_FS 0x80 |
| #define | MUSB2_MASK_TI_SPEED_HS 0x40 |
| #define | MUSB2_MASK_TI_PROTO_CTRL 0x00 |
| #define | MUSB2_MASK_TI_PROTO_ISOC 0x10 |
| #define | MUSB2_MASK_TI_PROTO_BULK 0x20 |
| #define | MUSB2_MASK_TI_PROTO_INTR 0x30 |
| #define | MUSB2_MASK_TI_EP_NUM 0x0F |
| #define | MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_NAKLIMIT 0xFF |
| #define | MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR) |
| #define | MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2**n bytes */ |
| #define | MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2**n bytes */ |
| #define | MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n))) |
| #define | MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR) /* EPN=0 */ |
| #define | MUSB2_MASK_CD_UTMI_DW 0x01 |
| #define | MUSB2_MASK_CD_SOFTCONE 0x02 |
| #define | MUSB2_MASK_CD_DYNFIFOSZ 0x04 |
| #define | MUSB2_MASK_CD_HBTXE 0x08 |
| #define | MUSB2_MASK_CD_HBRXE 0x10 |
| #define | MUSB2_MASK_CD_BIGEND 0x20 |
| #define | MUSB2_MASK_CD_MPTXE 0x40 |
| #define | MUSB2_MASK_CD_MPRXE 0x80 |
| #define | MUSB2_REG_DEVCTL 0x0060 |
| #define | MUSB2_MASK_SESS 0x01 |
| #define | MUSB2_MASK_HOSTREQ 0x02 |
| #define | MUSB2_MASK_HOSTMD 0x04 |
| #define | MUSB2_MASK_VBUS0 0x08 |
| #define | MUSB2_MASK_VBUS1 0x10 |
| #define | MUSB2_MASK_LSDEV 0x20 |
| #define | MUSB2_MASK_FSDEV 0x40 |
| #define | MUSB2_MASK_BDEV 0x80 |
| #define | MUSB2_REG_MISC 0x0061 |
| #define | MUSB2_MASK_RXEDMA 0x01 |
| #define | MUSB2_MASK_TXEDMA 0x02 |
| #define | MUSB2_REG_TXFIFOSZ 0x0062 |
| #define | MUSB2_REG_RXFIFOSZ 0x0063 |
| #define | MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */ |
| #define | MUSB2_MASK_FIFOSZ 0x0F |
| #define | MUSB2_VAL_FIFOSZ_8 0 |
| #define | MUSB2_VAL_FIFOSZ_16 1 |
| #define | MUSB2_VAL_FIFOSZ_32 2 |
| #define | MUSB2_VAL_FIFOSZ_64 3 |
| #define | MUSB2_VAL_FIFOSZ_128 4 |
| #define | MUSB2_VAL_FIFOSZ_256 5 |
| #define | MUSB2_VAL_FIFOSZ_512 6 |
| #define | MUSB2_VAL_FIFOSZ_1024 7 |
| #define | MUSB2_VAL_FIFOSZ_2048 8 |
| #define | MUSB2_VAL_FIFOSZ_4096 9 |
| #define | MUSB2_REG_TXFIFOADD 0x0064 |
| #define | MUSB2_REG_RXFIFOADD 0x0066 |
| #define | MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */ |
| #define | MUSB2_REG_VSTATUS 0x0068 |
| #define | MUSB2_REG_VCONTROL 0x0068 |
| #define | MUSB2_REG_HWVERS 0x006C |
| #define | MUSB2_REG_ULPI_BASE 0x0070 |
| #define | MUSB2_REG_EPINFO 0x0078 |
| #define | MUSB2_MASK_NRXEP 0xF0 |
| #define | MUSB2_MASK_NTXEP 0x0F |
| #define | MUSB2_REG_RAMINFO 0x0079 |
| #define | MUSB2_REG_LINKINFO 0x007A |
| #define | MUSB2_REG_VPLEN 0x007B |
| #define | MUSB2_MASK_VPLEN 0xFF |
| #define | MUSB2_REG_HS_EOF1 0x007C |
| #define | MUSB2_REG_FS_EOF1 0x007D |
| #define | MUSB2_REG_LS_EOF1 0x007E |
| #define | MUSB2_REG_SOFT_RST 0x007F |
| #define | MUSB2_MASK_SRST 0x01 |
| #define | MUSB2_MASK_SRSTX 0x02 |
| #define | MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n)) |
| #define | MUSB2_REG_RXDBDIS 0x0340 |
| #define | MUSB2_REG_TXDBDIS 0x0342 |
| #define | MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */ |
| #define | MUSB2_REG_CHIRPTO 0x0344 |
| #define | MUSB2_REG_HSRESUM 0x0346 |
| #define | MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n))) |
| #define | MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n))) |
| #define | MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n))) |
| #define | MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n))) |
| #define | MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n))) |
| #define | MUSB2_REG_RXHUBPORT(n) (0x0087 + (8*(n))) |
| #define | MUSB2_EP_MAX 16 /* maximum number of endpoints */ |
| #define | MUSB2_DEVICE_MODE 0 |
| #define | MUSB2_HOST_MODE 1 |
| #define | MUSB2_READ_2(sc, reg) bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) |
| #define | MUSB2_WRITE_2(sc, reg, data) bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) |
| #define | MUSB2_READ_1(sc, reg) bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) |
| #define | MUSB2_WRITE_1(sc, reg, data) bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) |
Typedefs | |
| typedef uint8_t() | musbotg_cmd_t(struct musbotg_td *td) |
Functions | |
| usb_error_t | musbotg_init (struct musbotg_softc *sc) |
| void | musbotg_uninit (struct musbotg_softc *sc) |
| void | musbotg_interrupt (struct musbotg_softc *sc, uint16_t rxstat, uint16_t txstat, uint8_t stat) |
| void | musbotg_vbus_interrupt (struct musbotg_softc *sc, uint8_t is_on) |
| void | musbotg_connect_interrupt (struct musbotg_softc *sc) |
Variables | |
| struct musbotg_config_desc | __packed |
Macro Definition Documentation
◆ MUSB2_DEVICE_MODE
| #define MUSB2_DEVICE_MODE 0 |
Definition at line 286 of file musb_otg.h.
◆ MUSB2_EP_MAX
| #define MUSB2_EP_MAX 16 /* maximum number of endpoints */ |
Definition at line 284 of file musb_otg.h.
◆ MUSB2_HOST_MODE
| #define MUSB2_HOST_MODE 1 |
Definition at line 287 of file musb_otg.h.
◆ MUSB2_MASK_BDEV
| #define MUSB2_MASK_BDEV 0x80 |
Definition at line 220 of file musb_otg.h.
◆ MUSB2_MASK_CD_BIGEND
| #define MUSB2_MASK_CD_BIGEND 0x20 |
Definition at line 206 of file musb_otg.h.
◆ MUSB2_MASK_CD_DYNFIFOSZ
| #define MUSB2_MASK_CD_DYNFIFOSZ 0x04 |
Definition at line 203 of file musb_otg.h.
◆ MUSB2_MASK_CD_HBRXE
| #define MUSB2_MASK_CD_HBRXE 0x10 |
Definition at line 205 of file musb_otg.h.
◆ MUSB2_MASK_CD_HBTXE
| #define MUSB2_MASK_CD_HBTXE 0x08 |
Definition at line 204 of file musb_otg.h.
◆ MUSB2_MASK_CD_MPRXE
| #define MUSB2_MASK_CD_MPRXE 0x80 |
Definition at line 208 of file musb_otg.h.
◆ MUSB2_MASK_CD_MPTXE
| #define MUSB2_MASK_CD_MPTXE 0x40 |
Definition at line 207 of file musb_otg.h.
◆ MUSB2_MASK_CD_SOFTCONE
| #define MUSB2_MASK_CD_SOFTCONE 0x02 |
Definition at line 202 of file musb_otg.h.
◆ MUSB2_MASK_CD_UTMI_DW
| #define MUSB2_MASK_CD_UTMI_DW 0x01 |
Definition at line 201 of file musb_otg.h.
◆ MUSB2_MASK_CSR0H_DT
| #define MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */ |
Definition at line 144 of file musb_otg.h.
◆ MUSB2_MASK_CSR0H_DT_WREN
| #define MUSB2_MASK_CSR0H_DT_WREN 0x04 /* Host Side */ |
Definition at line 145 of file musb_otg.h.
◆ MUSB2_MASK_CSR0H_FFLUSH
| #define MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */ |
Definition at line 143 of file musb_otg.h.
◆ MUSB2_MASK_CSR0H_PING_DIS
| #define MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */ |
Definition at line 146 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_DATAEND
| #define MUSB2_MASK_CSR0L_DATAEND 0x08 |
Definition at line 117 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_ERROR
| #define MUSB2_MASK_CSR0L_ERROR 0x10 |
Definition at line 127 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_NAKTIMO
| #define MUSB2_MASK_CSR0L_NAKTIMO 0x80 |
Definition at line 130 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_REQPKT
| #define MUSB2_MASK_CSR0L_REQPKT 0x20 |
Definition at line 128 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_RXPKTRDY
| #define MUSB2_MASK_CSR0L_RXPKTRDY 0x01 |
Definition at line 114 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_RXPKTRDY_CLR
| #define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40 |
Definition at line 120 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_RXSTALL
| #define MUSB2_MASK_CSR0L_RXSTALL 0x04 |
Definition at line 125 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_SENDSTALL
| #define MUSB2_MASK_CSR0L_SENDSTALL 0x20 |
Definition at line 119 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_SENTSTALL
| #define MUSB2_MASK_CSR0L_SENTSTALL 0x04 |
Definition at line 116 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_SETUPEND
| #define MUSB2_MASK_CSR0L_SETUPEND 0x10 |
Definition at line 118 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_SETUPEND_CLR
| #define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80 |
Definition at line 121 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_SETUPPKT
| #define MUSB2_MASK_CSR0L_SETUPPKT 0x08 |
Definition at line 126 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_STATUSPKT
| #define MUSB2_MASK_CSR0L_STATUSPKT 0x40 |
Definition at line 129 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_TXFIFONEMPTY
| #define MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02 |
Definition at line 124 of file musb_otg.h.
◆ MUSB2_MASK_CSR0L_TXPKTRDY
| #define MUSB2_MASK_CSR0L_TXPKTRDY 0x02 |
Definition at line 115 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXAUTOCLEAR
| #define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80 |
Definition at line 171 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXAUTOREQ
| #define MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */ |
Definition at line 170 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXDMAREQENA
| #define MUSB2_MASK_CSRH_RXDMAREQENA 0x20 |
Definition at line 168 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXDMAREQMODE
| #define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08 |
Definition at line 166 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXDT_VAL
| #define MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */ |
Definition at line 164 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXDT_WREN
| #define MUSB2_MASK_CSRH_RXDT_WREN 0x04 /* Host Mode */ |
Definition at line 165 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXINCOMP
| #define MUSB2_MASK_CSRH_RXINCOMP 0x01 |
Definition at line 163 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXISO
| #define MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */ |
Definition at line 169 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXMODE
| #define MUSB2_MASK_CSRH_RXMODE 0x00 |
Definition at line 138 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_RXNYET
| #define MUSB2_MASK_CSRH_RXNYET 0x10 |
Definition at line 167 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXAUTOSET
| #define MUSB2_MASK_CSRH_TXAUTOSET 0x80 |
Definition at line 141 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXDMAREQENA
| #define MUSB2_MASK_CSRH_TXDMAREQENA 0x10 |
Definition at line 137 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXDMAREQMODE
| #define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04 |
Definition at line 135 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXDT_SWITCH
| #define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08 |
Definition at line 136 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXDT_VAL
| #define MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */ |
Definition at line 133 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXDT_WREN
| #define MUSB2_MASK_CSRH_TXDT_WREN 0x02 /* Host Mode */ |
Definition at line 134 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXISO
| #define MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */ |
Definition at line 140 of file musb_otg.h.
◆ MUSB2_MASK_CSRH_TXMODE
| #define MUSB2_MASK_CSRH_TXMODE 0x20 |
Definition at line 139 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXDATAERR
| #define MUSB2_MASK_CSRL_RXDATAERR 0x08 /* Device Mode */ |
Definition at line 153 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXDT_CLR
| #define MUSB2_MASK_CSRL_RXDT_CLR 0x80 |
Definition at line 160 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXERROR
| #define MUSB2_MASK_CSRL_RXERROR 0x04 /* Host Mode */ |
Definition at line 152 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXFFLUSH
| #define MUSB2_MASK_CSRL_RXFFLUSH 0x10 |
Definition at line 155 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXFIFOFULL
| #define MUSB2_MASK_CSRL_RXFIFOFULL 0x02 |
Definition at line 150 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXNAKTO
| #define MUSB2_MASK_CSRL_RXNAKTO 0x08 /* Host Mode */ |
Definition at line 154 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXOVERRUN
| #define MUSB2_MASK_CSRL_RXOVERRUN 0x04 /* Device Mode */ |
Definition at line 151 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXPKTRDY
| #define MUSB2_MASK_CSRL_RXPKTRDY 0x01 |
Definition at line 149 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXREQPKT
| #define MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */ |
Definition at line 157 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXSENDSTALL
| #define MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */ |
Definition at line 156 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXSENTSTALL
| #define MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */ |
Definition at line 158 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_RXSTALL
| #define MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */ |
Definition at line 159 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXDT_CLR
| #define MUSB2_MASK_CSRL_TXDT_CLR 0x40 |
Definition at line 109 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXERROR
| #define MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */ |
Definition at line 103 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXFFLUSH
| #define MUSB2_MASK_CSRL_TXFFLUSH 0x08 |
Definition at line 104 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXFIFONEMPTY
| #define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02 |
Definition at line 101 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXINCOMP
| #define MUSB2_MASK_CSRL_TXINCOMP 0x80 /* Device mode */ |
Definition at line 110 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXNAKTO
| #define MUSB2_MASK_CSRL_TXNAKTO 0x80 /* Host mode */ |
Definition at line 111 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXPKTRDY
| #define MUSB2_MASK_CSRL_TXPKTRDY 0x01 |
Definition at line 100 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXSENDSTALL
| #define MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */ |
Definition at line 105 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXSENTSTALL
| #define MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */ |
Definition at line 107 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXSETUPPKT
| #define MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */ |
Definition at line 106 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXSTALLED
| #define MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */ |
Definition at line 108 of file musb_otg.h.
◆ MUSB2_MASK_CSRL_TXUNDERRUN
| #define MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */ |
Definition at line 102 of file musb_otg.h.
◆ MUSB2_MASK_DB
Definition at line 270 of file musb_otg.h.
◆ MUSB2_MASK_EPINDEX
| #define MUSB2_MASK_EPINDEX 0x0F |
Definition at line 80 of file musb_otg.h.
◆ MUSB2_MASK_EPINT
| #define MUSB2_MASK_EPINT | ( | epn | ) | (1 << (epn)) /* epn = [0..15] */ |
Definition at line 60 of file musb_otg.h.
◆ MUSB2_MASK_FADDR
| #define MUSB2_MASK_FADDR 0x7F |
Definition at line 42 of file musb_otg.h.
◆ MUSB2_MASK_FIFOADD
| #define MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */ |
Definition at line 243 of file musb_otg.h.
◆ MUSB2_MASK_FIFODB
| #define MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */ |
Definition at line 228 of file musb_otg.h.
◆ MUSB2_MASK_FIFOSZ
| #define MUSB2_MASK_FIFOSZ 0x0F |
Definition at line 229 of file musb_otg.h.
◆ MUSB2_MASK_FRAME
| #define MUSB2_MASK_FRAME 0x3FF /* 0..1023 */ |
Definition at line 77 of file musb_otg.h.
◆ MUSB2_MASK_FSDEV
| #define MUSB2_MASK_FSDEV 0x40 |
Definition at line 219 of file musb_otg.h.
◆ MUSB2_MASK_HOSTMD
| #define MUSB2_MASK_HOSTMD 0x04 |
Definition at line 215 of file musb_otg.h.
◆ MUSB2_MASK_HOSTREQ
| #define MUSB2_MASK_HOSTREQ 0x02 |
Definition at line 214 of file musb_otg.h.
◆ MUSB2_MASK_HSENAB
| #define MUSB2_MASK_HSENAB 0x20 |
Definition at line 50 of file musb_otg.h.
◆ MUSB2_MASK_HSMODE
| #define MUSB2_MASK_HSMODE 0x10 |
Definition at line 49 of file musb_otg.h.
◆ MUSB2_MASK_IBABBLE
| #define MUSB2_MASK_IBABBLE 0x04 |
Definition at line 68 of file musb_otg.h.
◆ MUSB2_MASK_ICONN
| #define MUSB2_MASK_ICONN 0x10 |
Definition at line 70 of file musb_otg.h.
◆ MUSB2_MASK_IDISC
| #define MUSB2_MASK_IDISC 0x20 |
Definition at line 71 of file musb_otg.h.
◆ MUSB2_MASK_IRESET
| #define MUSB2_MASK_IRESET 0x04 |
Definition at line 67 of file musb_otg.h.
◆ MUSB2_MASK_IRESUME
| #define MUSB2_MASK_IRESUME 0x02 |
Definition at line 66 of file musb_otg.h.
◆ MUSB2_MASK_ISESSRQ
| #define MUSB2_MASK_ISESSRQ 0x40 |
Definition at line 72 of file musb_otg.h.
◆ MUSB2_MASK_ISOF
| #define MUSB2_MASK_ISOF 0x08 |
Definition at line 69 of file musb_otg.h.
◆ MUSB2_MASK_ISOUPD
| #define MUSB2_MASK_ISOUPD 0x80 |
Definition at line 52 of file musb_otg.h.
◆ MUSB2_MASK_ISUSP
| #define MUSB2_MASK_ISUSP 0x01 |
Definition at line 65 of file musb_otg.h.
◆ MUSB2_MASK_IVBUSERR
| #define MUSB2_MASK_IVBUSERR 0x80 |
Definition at line 73 of file musb_otg.h.
◆ MUSB2_MASK_LSDEV
| #define MUSB2_MASK_LSDEV 0x20 |
Definition at line 218 of file musb_otg.h.
◆ MUSB2_MASK_NAKLIMIT
| #define MUSB2_MASK_NAKLIMIT 0xFF |
Definition at line 192 of file musb_otg.h.
◆ MUSB2_MASK_NRXEP
| #define MUSB2_MASK_NRXEP 0xF0 |
Definition at line 251 of file musb_otg.h.
◆ MUSB2_MASK_NTXEP
| #define MUSB2_MASK_NTXEP 0x0F |
Definition at line 252 of file musb_otg.h.
◆ MUSB2_MASK_PKTMULT
| #define MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */ |
Definition at line 97 of file musb_otg.h.
◆ MUSB2_MASK_PKTSIZE
| #define MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */ |
Definition at line 96 of file musb_otg.h.
◆ MUSB2_MASK_RESET
| #define MUSB2_MASK_RESET 0x08 |
Definition at line 48 of file musb_otg.h.
◆ MUSB2_MASK_RESUME
| #define MUSB2_MASK_RESUME 0x04 |
Definition at line 47 of file musb_otg.h.
◆ MUSB2_MASK_RX_FSIZE
| #define MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2**n bytes */ |
Definition at line 195 of file musb_otg.h.
◆ MUSB2_MASK_RXCOUNT
| #define MUSB2_MASK_RXCOUNT 0xFFFF |
Definition at line 174 of file musb_otg.h.
◆ MUSB2_MASK_RXEDMA
| #define MUSB2_MASK_RXEDMA 0x01 |
Definition at line 223 of file musb_otg.h.
◆ MUSB2_MASK_SESS
| #define MUSB2_MASK_SESS 0x01 |
Definition at line 213 of file musb_otg.h.
◆ MUSB2_MASK_SOFTC
| #define MUSB2_MASK_SOFTC 0x40 |
Definition at line 51 of file musb_otg.h.
◆ MUSB2_MASK_SRST
| #define MUSB2_MASK_SRST 0x01 |
Definition at line 264 of file musb_otg.h.
◆ MUSB2_MASK_SRSTX
| #define MUSB2_MASK_SRSTX 0x02 |
Definition at line 265 of file musb_otg.h.
◆ MUSB2_MASK_SUSPM_ENA
| #define MUSB2_MASK_SUSPM_ENA 0x01 |
Definition at line 45 of file musb_otg.h.
◆ MUSB2_MASK_SUSPMODE
| #define MUSB2_MASK_SUSPMODE 0x02 |
Definition at line 46 of file musb_otg.h.
◆ MUSB2_MASK_TFIFO_ACC
| #define MUSB2_MASK_TFIFO_ACC 0x40 |
Definition at line 89 of file musb_otg.h.
◆ MUSB2_MASK_TFORCE_HC
| #define MUSB2_MASK_TFORCE_HC 0x80 |
Definition at line 90 of file musb_otg.h.
◆ MUSB2_MASK_TFORCE_HS
| #define MUSB2_MASK_TFORCE_HS 0x10 |
Definition at line 87 of file musb_otg.h.
◆ MUSB2_MASK_TFORCE_LS
| #define MUSB2_MASK_TFORCE_LS 0x20 |
Definition at line 88 of file musb_otg.h.
◆ MUSB2_MASK_TI_EP_NUM
| #define MUSB2_MASK_TI_EP_NUM 0x0F |
Definition at line 188 of file musb_otg.h.
◆ MUSB2_MASK_TI_PROTO_BULK
| #define MUSB2_MASK_TI_PROTO_BULK 0x20 |
Definition at line 186 of file musb_otg.h.
◆ MUSB2_MASK_TI_PROTO_CTRL
| #define MUSB2_MASK_TI_PROTO_CTRL 0x00 |
Definition at line 184 of file musb_otg.h.
◆ MUSB2_MASK_TI_PROTO_INTR
| #define MUSB2_MASK_TI_PROTO_INTR 0x30 |
Definition at line 187 of file musb_otg.h.
◆ MUSB2_MASK_TI_PROTO_ISOC
| #define MUSB2_MASK_TI_PROTO_ISOC 0x10 |
Definition at line 185 of file musb_otg.h.
◆ MUSB2_MASK_TI_SPEED
| #define MUSB2_MASK_TI_SPEED 0xC0 |
Definition at line 180 of file musb_otg.h.
◆ MUSB2_MASK_TI_SPEED_FS
| #define MUSB2_MASK_TI_SPEED_FS 0x80 |
Definition at line 182 of file musb_otg.h.
◆ MUSB2_MASK_TI_SPEED_HS
| #define MUSB2_MASK_TI_SPEED_HS 0x40 |
Definition at line 183 of file musb_otg.h.
◆ MUSB2_MASK_TI_SPEED_LO
| #define MUSB2_MASK_TI_SPEED_LO 0xC0 |
Definition at line 181 of file musb_otg.h.
◆ MUSB2_MASK_TJ
| #define MUSB2_MASK_TJ 0x02 |
Definition at line 84 of file musb_otg.h.
◆ MUSB2_MASK_TK
| #define MUSB2_MASK_TK 0x04 |
Definition at line 85 of file musb_otg.h.
◆ MUSB2_MASK_TPACKET
| #define MUSB2_MASK_TPACKET 0x08 |
Definition at line 86 of file musb_otg.h.
◆ MUSB2_MASK_TSE0_NAK
| #define MUSB2_MASK_TSE0_NAK 0x01 |
Definition at line 83 of file musb_otg.h.
◆ MUSB2_MASK_TX_FSIZE
| #define MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2**n bytes */ |
Definition at line 196 of file musb_otg.h.
◆ MUSB2_MASK_TXEDMA
| #define MUSB2_MASK_TXEDMA 0x02 |
Definition at line 224 of file musb_otg.h.
◆ MUSB2_MASK_VBUS0
| #define MUSB2_MASK_VBUS0 0x08 |
Definition at line 216 of file musb_otg.h.
◆ MUSB2_MASK_VBUS1
| #define MUSB2_MASK_VBUS1 0x10 |
Definition at line 217 of file musb_otg.h.
◆ MUSB2_MASK_VPLEN
| #define MUSB2_MASK_VPLEN 0xFF |
Definition at line 258 of file musb_otg.h.
◆ MUSB2_MAX_DEVICES
| #define MUSB2_MAX_DEVICES USB_MAX_DEVICES |
Definition at line 37 of file musb_otg.h.
◆ MUSB2_READ_1
Definition at line 295 of file musb_otg.h.
◆ MUSB2_READ_2
Definition at line 289 of file musb_otg.h.
◆ MUSB2_REG_CHIRPTO
| #define MUSB2_REG_CHIRPTO 0x0344 |
Definition at line 272 of file musb_otg.h.
◆ MUSB2_REG_CONFDATA
| #define MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR) /* EPN=0 */ |
Definition at line 200 of file musb_otg.h.
◆ MUSB2_REG_DEVCTL
| #define MUSB2_REG_DEVCTL 0x0060 |
Definition at line 212 of file musb_otg.h.
◆ MUSB2_REG_EPFIFO
Definition at line 198 of file musb_otg.h.
◆ MUSB2_REG_EPINDEX
Definition at line 79 of file musb_otg.h.
◆ MUSB2_REG_EPINFO
| #define MUSB2_REG_EPINFO 0x0078 |
Definition at line 250 of file musb_otg.h.
◆ MUSB2_REG_FADDR
| #define MUSB2_REG_FADDR 0x0000 /* function address register */ |
Definition at line 41 of file musb_otg.h.
◆ MUSB2_REG_FRAME
| #define MUSB2_REG_FRAME 0x000C /* USB frame register */ |
Definition at line 76 of file musb_otg.h.
◆ MUSB2_REG_FS_EOF1
| #define MUSB2_REG_FS_EOF1 0x007D |
Definition at line 261 of file musb_otg.h.
◆ MUSB2_REG_FSIZE
| #define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR) |
Definition at line 194 of file musb_otg.h.
◆ MUSB2_REG_HS_EOF1
| #define MUSB2_REG_HS_EOF1 0x007C |
Definition at line 260 of file musb_otg.h.
◆ MUSB2_REG_HSRESUM
| #define MUSB2_REG_HSRESUM 0x0346 |
Definition at line 273 of file musb_otg.h.
◆ MUSB2_REG_HWVERS
| #define MUSB2_REG_HWVERS 0x006C |
Definition at line 247 of file musb_otg.h.
◆ MUSB2_REG_INDEXED_CSR
Definition at line 92 of file musb_otg.h.
◆ MUSB2_REG_INTRX
| #define MUSB2_REG_INTRX 0x0004 /* receive interrupt register */ |
Definition at line 57 of file musb_otg.h.
◆ MUSB2_REG_INTRXE
| #define MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */ |
Definition at line 59 of file musb_otg.h.
◆ MUSB2_REG_INTTX
| #define MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */ |
Definition at line 56 of file musb_otg.h.
◆ MUSB2_REG_INTTXE
| #define MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */ |
Definition at line 58 of file musb_otg.h.
◆ MUSB2_REG_INTUSB
| #define MUSB2_REG_INTUSB 0x000A /* USB interrupt register */ |
Definition at line 64 of file musb_otg.h.
◆ MUSB2_REG_INTUSBE
| #define MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */ |
Definition at line 75 of file musb_otg.h.
◆ MUSB2_REG_LINKINFO
| #define MUSB2_REG_LINKINFO 0x007A |
Definition at line 255 of file musb_otg.h.
◆ MUSB2_REG_LS_EOF1
| #define MUSB2_REG_LS_EOF1 0x007E |
Definition at line 262 of file musb_otg.h.
◆ MUSB2_REG_MISC
| #define MUSB2_REG_MISC 0x0061 |
Definition at line 222 of file musb_otg.h.
◆ MUSB2_REG_POWER
| #define MUSB2_REG_POWER 0x0001 /* power register */ |
Definition at line 44 of file musb_otg.h.
◆ MUSB2_REG_RAMINFO
| #define MUSB2_REG_RAMINFO 0x0079 |
Definition at line 254 of file musb_otg.h.
◆ MUSB2_REG_RQPKTCOUNT
Definition at line 267 of file musb_otg.h.
◆ MUSB2_REG_RXCOUNT
| #define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR) |
Definition at line 173 of file musb_otg.h.
◆ MUSB2_REG_RXCSRH
| #define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR) |
Definition at line 162 of file musb_otg.h.
◆ MUSB2_REG_RXCSRL
| #define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR) |
Definition at line 148 of file musb_otg.h.
◆ MUSB2_REG_RXDBDIS
| #define MUSB2_REG_RXDBDIS 0x0340 |
Definition at line 268 of file musb_otg.h.
◆ MUSB2_REG_RXFADDR
Definition at line 280 of file musb_otg.h.
◆ MUSB2_REG_RXFIFOADD
| #define MUSB2_REG_RXFIFOADD 0x0066 |
Definition at line 242 of file musb_otg.h.
◆ MUSB2_REG_RXFIFOSZ
| #define MUSB2_REG_RXFIFOSZ 0x0063 |
Definition at line 227 of file musb_otg.h.
◆ MUSB2_REG_RXHADDR
Definition at line 281 of file musb_otg.h.
◆ MUSB2_REG_RXHUBPORT
Definition at line 282 of file musb_otg.h.
◆ MUSB2_REG_RXMAXP
| #define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR) |
Definition at line 95 of file musb_otg.h.
◆ MUSB2_REG_RXNAKLIMIT
| #define MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) |
Definition at line 191 of file musb_otg.h.
◆ MUSB2_REG_RXTI
| #define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR) |
Definition at line 177 of file musb_otg.h.
◆ MUSB2_REG_SOFT_RST
| #define MUSB2_REG_SOFT_RST 0x007F |
Definition at line 263 of file musb_otg.h.
◆ MUSB2_REG_TESTMODE
| #define MUSB2_REG_TESTMODE 0x000F /* test mode register */ |
Definition at line 82 of file musb_otg.h.
◆ MUSB2_REG_TXCSRH
| #define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR) |
Definition at line 132 of file musb_otg.h.
◆ MUSB2_REG_TXCSRL
| #define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR) |
Definition at line 99 of file musb_otg.h.
◆ MUSB2_REG_TXDBDIS
| #define MUSB2_REG_TXDBDIS 0x0342 |
Definition at line 269 of file musb_otg.h.
◆ MUSB2_REG_TXFADDR
Definition at line 277 of file musb_otg.h.
◆ MUSB2_REG_TXFIFOADD
| #define MUSB2_REG_TXFIFOADD 0x0064 |
Definition at line 241 of file musb_otg.h.
◆ MUSB2_REG_TXFIFOSZ
| #define MUSB2_REG_TXFIFOSZ 0x0062 |
Definition at line 226 of file musb_otg.h.
◆ MUSB2_REG_TXHADDR
Definition at line 278 of file musb_otg.h.
◆ MUSB2_REG_TXHUBPORT
Definition at line 279 of file musb_otg.h.
◆ MUSB2_REG_TXMAXP
| #define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR) |
Definition at line 94 of file musb_otg.h.
◆ MUSB2_REG_TXNAKLIMIT
| #define MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) |
Definition at line 190 of file musb_otg.h.
◆ MUSB2_REG_TXTI
| #define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR) |
Definition at line 176 of file musb_otg.h.
◆ MUSB2_REG_ULPI_BASE
| #define MUSB2_REG_ULPI_BASE 0x0070 |
Definition at line 248 of file musb_otg.h.
◆ MUSB2_REG_VCONTROL
| #define MUSB2_REG_VCONTROL 0x0068 |
Definition at line 246 of file musb_otg.h.
◆ MUSB2_REG_VPLEN
| #define MUSB2_REG_VPLEN 0x007B |
Definition at line 257 of file musb_otg.h.
◆ MUSB2_REG_VSTATUS
| #define MUSB2_REG_VSTATUS 0x0068 |
Definition at line 245 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_1024
| #define MUSB2_VAL_FIFOSZ_1024 7 |
Definition at line 237 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_128
| #define MUSB2_VAL_FIFOSZ_128 4 |
Definition at line 234 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_16
| #define MUSB2_VAL_FIFOSZ_16 1 |
Definition at line 231 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_2048
| #define MUSB2_VAL_FIFOSZ_2048 8 |
Definition at line 238 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_256
| #define MUSB2_VAL_FIFOSZ_256 5 |
Definition at line 235 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_32
| #define MUSB2_VAL_FIFOSZ_32 2 |
Definition at line 232 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_4096
| #define MUSB2_VAL_FIFOSZ_4096 9 |
Definition at line 239 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_512
| #define MUSB2_VAL_FIFOSZ_512 6 |
Definition at line 236 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_64
| #define MUSB2_VAL_FIFOSZ_64 3 |
Definition at line 233 of file musb_otg.h.
◆ MUSB2_VAL_FIFOSZ_8
| #define MUSB2_VAL_FIFOSZ_8 0 |
Definition at line 230 of file musb_otg.h.
◆ MUSB2_WRITE_1
| #define MUSB2_WRITE_1 | ( | sc, | |
| reg, | |||
| data | |||
| ) | bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) |
Definition at line 298 of file musb_otg.h.
◆ MUSB2_WRITE_2
| #define MUSB2_WRITE_2 | ( | sc, | |
| reg, | |||
| data | |||
| ) | bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) |
Definition at line 292 of file musb_otg.h.
Typedef Documentation
◆ musbotg_cmd_t
| typedef uint8_t() musbotg_cmd_t(struct musbotg_td *td) |
Definition at line 304 of file musb_otg.h.
Function Documentation
◆ musbotg_connect_interrupt()
| void musbotg_connect_interrupt | ( | struct musbotg_softc * | sc | ) |
Definition at line 2216 of file musb_otg.c.
References musbotg_flags::change_connect, musbotg_root_intr(), musbotg_softc::sc_bus, musbotg_softc::sc_flags, USB_BUS_LOCK, and USB_BUS_UNLOCK.
◆ musbotg_init()
| usb_error_t musbotg_init | ( | struct musbotg_softc * | sc | ) |
Definition at line 3043 of file musb_otg.c.
References usb_bus::bdev, usb_bus::bus_mtx, DPRINTF, musb_otg_ep_cfg::ep_end, musb_otg_ep_cfg::ep_fifosz_reg, musb_otg_ep_cfg::ep_fifosz_shift, usb_bus::methods, MUSB2_DEVICE_MODE, MUSB2_HOST_MODE, MUSB2_MASK_CD_DYNFIFOSZ, MUSB2_MASK_HSENAB, MUSB2_MASK_IRESET, MUSB2_MASK_ISOUPD, MUSB2_MASK_RX_FSIZE, MUSB2_MASK_SESS, MUSB2_MASK_TX_FSIZE, MUSB2_READ_1, MUSB2_REG_CONFDATA, MUSB2_REG_DEVCTL, MUSB2_REG_EPINDEX, MUSB2_REG_EPINFO, MUSB2_REG_FSIZE, MUSB2_REG_HWVERS, MUSB2_REG_INTRXE, MUSB2_REG_INTTXE, MUSB2_REG_INTUSBE, MUSB2_REG_MISC, MUSB2_REG_POWER, MUSB2_REG_RXDBDIS, MUSB2_REG_RXFIFOADD, MUSB2_REG_RXFIFOSZ, MUSB2_REG_TESTMODE, MUSB2_REG_TXDBDIS, MUSB2_REG_TXFIFOADD, MUSB2_REG_TXFIFOSZ, MUSB2_WRITE_1, MUSB2_WRITE_2, musbotg_bus_methods, musbotg_clocks_off(), musbotg_do_poll(), musbotg_ep_default, musbotg_pull_common(), offset, pf, musbotg_softc::sc_bus, musbotg_softc::sc_clocks_arg, musbotg_softc::sc_clocks_on, musbotg_softc::sc_conf_data, musbotg_softc::sc_ep_cfg, musbotg_softc::sc_ep_max, musbotg_softc::sc_hw_ep_profile, musbotg_softc::sc_mode, USB_BUS_LOCK, USB_BUS_UNLOCK, usb_pause_mtx(), USB_REV_2_0, and usb_bus::usbrev.
Referenced by awusbdrd_attach(), and musbotg_set_hw_power_sleep().
◆ musbotg_interrupt()
| void musbotg_interrupt | ( | struct musbotg_softc * | sc, |
| uint16_t | rxstat, | ||
| uint16_t | txstat, | ||
| uint8_t | stat | ||
| ) |
Definition at line 2227 of file musb_otg.c.
References musbotg_flags::change_connect, musbotg_flags::change_suspend, MUSB2_HOST_MODE, MUSB2_MASK_HSMODE, MUSB2_MASK_ICONN, MUSB2_MASK_IDISC, MUSB2_MASK_IRESET, MUSB2_MASK_IRESUME, MUSB2_MASK_ISUSP, MUSB2_MASK_IVBUSERR, MUSB2_MASK_SESS, MUSB2_READ_1, MUSB2_READ_2, MUSB2_REG_DEVCTL, MUSB2_REG_INTRX, MUSB2_REG_INTRXE, MUSB2_REG_INTTX, MUSB2_REG_INTTXE, MUSB2_REG_INTUSB, MUSB2_REG_INTUSBE, MUSB2_REG_POWER, MUSB2_WRITE_1, MUSB2_WRITE_2, musbotg_interrupt_poll(), musbotg_root_intr(), musbotg_softc::sc_bus, musbotg_softc::sc_flags, musbotg_softc::sc_mode, musbotg_flags::status_bus_reset, musbotg_flags::status_high_speed, musbotg_flags::status_suspend, USB_BUS_LOCK, and USB_BUS_UNLOCK.
Referenced by awusbdrd_intr().
◆ musbotg_uninit()
| void musbotg_uninit | ( | struct musbotg_softc * | sc | ) |
Definition at line 3277 of file musb_otg.c.
References musbotg_flags::change_connect, musbotg_flags::change_suspend, MUSB2_REG_INTRXE, MUSB2_REG_INTTXE, MUSB2_REG_INTUSBE, MUSB2_WRITE_1, MUSB2_WRITE_2, musbotg_clocks_off(), musbotg_pull_down(), musbotg_flags::port_powered, musbotg_softc::sc_bus, musbotg_softc::sc_flags, musbotg_flags::status_bus_reset, musbotg_flags::status_suspend, musbotg_flags::status_vbus, USB_BUS_LOCK, and USB_BUS_UNLOCK.
Referenced by awusbdrd_detach(), and musbotg_set_hw_power_sleep().
◆ musbotg_vbus_interrupt()
| void musbotg_vbus_interrupt | ( | struct musbotg_softc * | sc, |
| uint8_t | is_on | ||
| ) |
Definition at line 2187 of file musb_otg.c.
References musbotg_flags::change_connect, musbotg_flags::change_suspend, musbotg_root_intr(), musbotg_softc::sc_bus, musbotg_softc::sc_flags, musbotg_flags::status_bus_reset, musbotg_flags::status_suspend, musbotg_flags::status_vbus, USB_BUS_LOCK, and USB_BUS_UNLOCK.
Referenced by awusbdrd_attach().
Variable Documentation
◆ __packed
| struct musbotg_config_desc __packed |
