FreeBSD kernel IXGBE device code
ixgbe_phy.c
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1/******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
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19 this software without specific prior written permission.
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31 POSSIBILITY OF SUCH DAMAGE.
32
33******************************************************************************/
34/*$FreeBSD$*/
35
36#include "ixgbe_api.h"
37#include "ixgbe_common.h"
38#include "ixgbe_phy.h"
39
40static void ixgbe_i2c_start(struct ixgbe_hw *hw);
41static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
42static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
43static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
44static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
45static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
46static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
47static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
49static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
50static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
51static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
52 u8 *sff8472_data);
53
61static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
62{
63 s32 status;
64
65 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 if (status)
67 return status;
68 return ixgbe_get_i2c_ack(hw);
69}
70
78static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
79{
80 ixgbe_clock_in_i2c_byte(hw, byte);
81 /* ACK */
82 return ixgbe_clock_out_i2c_bit(hw, false);
83}
84
92static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
93{
94 u16 sum = add1 + add2;
95
96 sum = (sum & 0xFF) + (sum >> 8);
97 return sum & 0xFF;
98}
99
110s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
111 u16 *val, bool lock)
112{
113 u32 swfw_mask = hw->phy.phy_semaphore_mask;
114 int max_retry = 3;
115 int retry = 0;
116 u8 csum_byte;
117 u8 high_bits;
118 u8 low_bits;
119 u8 reg_high;
120 u8 csum;
121
122 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
123 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
124 csum = ~csum;
125 do {
126 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
127 return IXGBE_ERR_SWFW_SYNC;
128 ixgbe_i2c_start(hw);
129 /* Device Address and write indication */
130 if (ixgbe_out_i2c_byte_ack(hw, addr))
131 goto fail;
132 /* Write bits 14:8 */
133 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
134 goto fail;
135 /* Write bits 7:0 */
136 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
137 goto fail;
138 /* Write csum */
139 if (ixgbe_out_i2c_byte_ack(hw, csum))
140 goto fail;
141 /* Re-start condition */
142 ixgbe_i2c_start(hw);
143 /* Device Address and read indication */
144 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
145 goto fail;
146 /* Get upper bits */
147 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
148 goto fail;
149 /* Get low bits */
150 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
151 goto fail;
152 /* Get csum */
153 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
154 /* NACK */
155 if (ixgbe_clock_out_i2c_bit(hw, false))
156 goto fail;
157 ixgbe_i2c_stop(hw);
158 if (lock)
159 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
160 *val = (high_bits << 8) | low_bits;
161 return 0;
162
163fail:
164 ixgbe_i2c_bus_clear(hw);
165 if (lock)
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
167 if (retry < max_retry)
168 DEBUGOUT("I2C byte read combined error - Retrying.\n");
169 else
170 DEBUGOUT("I2C byte read combined error.\n");
171 retry++;
172 } while (retry <= max_retry);
173
174 return IXGBE_ERR_I2C;
175}
176
187s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
188 u16 val, bool lock)
189{
190 u32 swfw_mask = hw->phy.phy_semaphore_mask;
191 int max_retry = 1;
192 int retry = 0;
193 u8 reg_high;
194 u8 csum;
195
196 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
197 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
198 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
199 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
200 csum = ~csum;
201 do {
202 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
203 return IXGBE_ERR_SWFW_SYNC;
204 ixgbe_i2c_start(hw);
205 /* Device Address and write indication */
206 if (ixgbe_out_i2c_byte_ack(hw, addr))
207 goto fail;
208 /* Write bits 14:8 */
209 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
210 goto fail;
211 /* Write bits 7:0 */
212 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
213 goto fail;
214 /* Write data 15:8 */
215 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
216 goto fail;
217 /* Write data 7:0 */
218 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
219 goto fail;
220 /* Write csum */
221 if (ixgbe_out_i2c_byte_ack(hw, csum))
222 goto fail;
223 ixgbe_i2c_stop(hw);
224 if (lock)
225 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
226 return 0;
227
228fail:
229 ixgbe_i2c_bus_clear(hw);
230 if (lock)
231 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
232 if (retry < max_retry)
233 DEBUGOUT("I2C byte write combined error - Retrying.\n");
234 else
235 DEBUGOUT("I2C byte write combined error.\n");
236 retry++;
237 } while (retry <= max_retry);
238
239 return IXGBE_ERR_I2C;
240}
241
248s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
249{
250 struct ixgbe_phy_info *phy = &hw->phy;
251
252 DEBUGFUNC("ixgbe_init_phy_ops_generic");
253
254 /* PHY */
255 phy->ops.identify = ixgbe_identify_phy_generic;
256 phy->ops.reset = ixgbe_reset_phy_generic;
257 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
258 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
259 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
260 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
261 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
262 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
263 phy->ops.check_link = NULL;
264 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
265 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
266 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
267 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
268 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
269 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
270 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
271 phy->ops.identify_sfp = ixgbe_identify_module_generic;
272 phy->sfp_type = ixgbe_sfp_type_unknown;
273 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
274 phy->ops.write_i2c_byte_unlocked =
275 ixgbe_write_i2c_byte_generic_unlocked;
276 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
277 return IXGBE_SUCCESS;
278}
279
287static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
288{
289 u16 ext_ability = 0;
290
291 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
292 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
293 phy_addr);
294 return false;
295 }
296
297 if (ixgbe_get_phy_id(hw))
298 return false;
299
300 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
301
302 if (hw->phy.type == ixgbe_phy_unknown) {
303 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
304 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
305 if (ext_ability &
306 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
307 IXGBE_MDIO_PHY_1000BASET_ABILITY))
308 hw->phy.type = ixgbe_phy_cu_unknown;
309 else
310 hw->phy.type = ixgbe_phy_generic;
311 }
312
313 return true;
314}
315
322s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
323{
324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
325 u16 phy_addr;
326
327 DEBUGFUNC("ixgbe_identify_phy_generic");
328
329 if (!hw->phy.phy_semaphore_mask) {
330 if (hw->bus.lan_id)
331 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
332 else
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
334 }
335
336 if (hw->phy.type != ixgbe_phy_unknown)
337 return IXGBE_SUCCESS;
338
339 if (hw->phy.nw_mng_if_sel) {
340 phy_addr = (hw->phy.nw_mng_if_sel &
341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
342 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
343 if (ixgbe_probe_phy(hw, phy_addr))
344 return IXGBE_SUCCESS;
345 else
346 return IXGBE_ERR_PHY_ADDR_INVALID;
347 }
348
349 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
350 if (ixgbe_probe_phy(hw, phy_addr)) {
351 status = IXGBE_SUCCESS;
352 break;
353 }
354 }
355
356 /* Certain media types do not have a phy so an address will not
357 * be found and the code will take this path. Caller has to
358 * decide if it is an error or not.
359 */
360 if (status != IXGBE_SUCCESS)
361 hw->phy.addr = 0;
362
363 return status;
364}
365
375s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
376{
377 u32 mmngc;
378
379 DEBUGFUNC("ixgbe_check_reset_blocked");
380
381 /* If we don't have this bit, it can't be blocking */
382 if (hw->mac.type == ixgbe_mac_82598EB)
383 return false;
384
385 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
386 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
387 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
388 "MNG_VETO bit detected.\n");
389 return true;
390 }
391
392 return false;
393}
394
401bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
402{
403 u16 phy_id = 0;
404 bool valid = false;
405
406 DEBUGFUNC("ixgbe_validate_phy_addr");
407
408 hw->phy.addr = phy_addr;
409 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
410 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
411
412 if (phy_id != 0xFFFF && phy_id != 0x0)
413 valid = true;
414
415 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
416
417 return valid;
418}
419
425s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
426{
427 u32 status;
428 u16 phy_id_high = 0;
429 u16 phy_id_low = 0;
430
431 DEBUGFUNC("ixgbe_get_phy_id");
432
433 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
434 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
435 &phy_id_high);
436
437 if (status == IXGBE_SUCCESS) {
438 hw->phy.id = (u32)(phy_id_high << 16);
439 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
440 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
441 &phy_id_low);
442 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
443 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
444 }
445 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
446 phy_id_high, phy_id_low);
447
448 return status;
449}
450
456enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
457{
458 enum ixgbe_phy_type phy_type;
459
460 DEBUGFUNC("ixgbe_get_phy_type_from_id");
461
462 switch (phy_id) {
463 case TN1010_PHY_ID:
464 phy_type = ixgbe_phy_tn;
465 break;
466 case X550_PHY_ID2:
467 case X550_PHY_ID3:
468 case X540_PHY_ID:
469 phy_type = ixgbe_phy_aq;
470 break;
471 case QT2022_PHY_ID:
472 phy_type = ixgbe_phy_qt;
473 break;
474 case ATH_PHY_ID:
475 phy_type = ixgbe_phy_nl;
476 break;
477 case X557_PHY_ID:
478 case X557_PHY_ID2:
479 phy_type = ixgbe_phy_x550em_ext_t;
480 break;
481 case IXGBE_M88E1500_E_PHY_ID:
482 case IXGBE_M88E1543_E_PHY_ID:
483 phy_type = ixgbe_phy_ext_1g_t;
484 break;
485 default:
486 phy_type = ixgbe_phy_unknown;
487 break;
488 }
489 return phy_type;
490}
491
496s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
497{
498 u32 i;
499 u16 ctrl = 0;
500 s32 status = IXGBE_SUCCESS;
501
502 DEBUGFUNC("ixgbe_reset_phy_generic");
503
504 if (hw->phy.type == ixgbe_phy_unknown)
505 status = ixgbe_identify_phy_generic(hw);
506
507 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
508 goto out;
509
510 /* Don't reset PHY if it's shut down due to overtemp. */
511 if (!hw->phy.reset_if_overtemp &&
512 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
513 goto out;
514
515 /* Blocked by MNG FW so bail */
516 if (ixgbe_check_reset_blocked(hw))
517 goto out;
518
519 /*
520 * Perform soft PHY reset to the PHY_XS.
521 * This will cause a soft reset to the PHY
522 */
523 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
524 IXGBE_MDIO_PHY_XS_DEV_TYPE,
525 IXGBE_MDIO_PHY_XS_RESET);
526
527 /*
528 * Poll for reset bit to self-clear indicating reset is complete.
529 * Some PHYs could take up to 3 seconds to complete and need about
530 * 1.7 usec delay after the reset is complete.
531 */
532 for (i = 0; i < 30; i++) {
533 msec_delay(100);
534 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
535 status = hw->phy.ops.read_reg(hw,
536 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
537 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
538 &ctrl);
539 if (status != IXGBE_SUCCESS)
540 return status;
541
542 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
543 usec_delay(2);
544 break;
545 }
546 } else {
547 status = hw->phy.ops.read_reg(hw,
548 IXGBE_MDIO_PHY_XS_CONTROL,
549 IXGBE_MDIO_PHY_XS_DEV_TYPE,
550 &ctrl);
551 if (status != IXGBE_SUCCESS)
552 return status;
553
554 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
555 usec_delay(2);
556 break;
557 }
558 }
559 }
560
561 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
562 status = IXGBE_ERR_RESET_FAILED;
563 ERROR_REPORT1(IXGBE_ERROR_POLLING,
564 "PHY reset polling failed to complete.\n");
565 }
566
567out:
568 return status;
569}
570
575void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
576{
577 u16 autoneg_reg;
578
579 /* Check if PHY reset is blocked by MNG FW */
580 if (ixgbe_check_reset_blocked(hw))
581 return;
582
583 /* Restart PHY auto-negotiation. */
584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
585 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
586 autoneg_reg |= IXGBE_MII_RESTART;
587 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
589}
590
599s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
600 u16 *phy_data)
601{
602 u32 i, data, command;
603
604 /* Setup and write the address cycle command */
605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
609
610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
611
612 /*
613 * Check every 10 usec to see if the address cycle completed.
614 * The MDI Command bit will clear when the operation is
615 * complete
616 */
617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
618 usec_delay(10);
619
620 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
622 break;
623 }
624
625
626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
628 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
629 return IXGBE_ERR_PHY;
630 }
631
632 /*
633 * Address cycle complete, setup and write the read
634 * command
635 */
636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
640
641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
642
643 /*
644 * Check every 10 usec to see if the address cycle
645 * completed. The MDI Command bit will clear when the
646 * operation is complete
647 */
648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
649 usec_delay(10);
650
651 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
653 break;
654 }
655
656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
658 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
659 return IXGBE_ERR_PHY;
660 }
661
662 /*
663 * Read operation is complete. Get the data
664 * from MSRWD
665 */
666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
668 *phy_data = (u16)(data);
669
670 return IXGBE_SUCCESS;
671}
672
681s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
682 u32 device_type, u16 *phy_data)
683{
684 s32 status;
685 u32 gssr = hw->phy.phy_semaphore_mask;
686
687 DEBUGFUNC("ixgbe_read_phy_reg_generic");
688
689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
690 return IXGBE_ERR_SWFW_SYNC;
691
692 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
693
694 hw->mac.ops.release_swfw_sync(hw, gssr);
695
696 return status;
697}
698
707s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
708 u32 device_type, u16 phy_data)
709{
710 u32 i, command;
711
712 /* Put the data in the MDI single read and write data register*/
713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
714
715 /* Setup and write the address cycle command */
716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
720
721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
722
723 /*
724 * Check every 10 usec to see if the address cycle completed.
725 * The MDI Command bit will clear when the operation is
726 * complete
727 */
728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
729 usec_delay(10);
730
731 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
733 break;
734 }
735
736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
738 return IXGBE_ERR_PHY;
739 }
740
741 /*
742 * Address cycle complete, setup and write the write
743 * command
744 */
745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
749
750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
751
752 /*
753 * Check every 10 usec to see if the address cycle
754 * completed. The MDI Command bit will clear when the
755 * operation is complete
756 */
757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
758 usec_delay(10);
759
760 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
762 break;
763 }
764
765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
767 return IXGBE_ERR_PHY;
768 }
769
770 return IXGBE_SUCCESS;
771}
772
781s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
782 u32 device_type, u16 phy_data)
783{
784 s32 status;
785 u32 gssr = hw->phy.phy_semaphore_mask;
786
787 DEBUGFUNC("ixgbe_write_phy_reg_generic");
788
789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
790 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
791 phy_data);
792 hw->mac.ops.release_swfw_sync(hw, gssr);
793 } else {
794 status = IXGBE_ERR_SWFW_SYNC;
795 }
796
797 return status;
798}
799
806s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
807{
808 s32 status = IXGBE_SUCCESS;
809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
810 bool autoneg = false;
811 ixgbe_link_speed speed;
812
813 DEBUGFUNC("ixgbe_setup_phy_link_generic");
814
815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
816
817 /* Set or unset auto-negotiation 10G advertisement */
818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
820 &autoneg_reg);
821
822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
824 (speed & IXGBE_LINK_SPEED_10GB_FULL))
825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
826
827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
829 autoneg_reg);
830
831 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
833 &autoneg_reg);
834
835 if (hw->mac.type == ixgbe_mac_X550) {
836 /* Set or unset auto-negotiation 5G advertisement */
837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
839 (speed & IXGBE_LINK_SPEED_5GB_FULL))
840 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
841
842 /* Set or unset auto-negotiation 2.5G advertisement */
843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
844 if ((hw->phy.autoneg_advertised &
845 IXGBE_LINK_SPEED_2_5GB_FULL) &&
846 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
847 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
848 }
849
850 /* Set or unset auto-negotiation 1G advertisement */
851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
853 (speed & IXGBE_LINK_SPEED_1GB_FULL))
854 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
855
856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
858 autoneg_reg);
859
860 /* Set or unset auto-negotiation 100M advertisement */
861 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
863 &autoneg_reg);
864
865 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
866 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
867 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
868 (speed & IXGBE_LINK_SPEED_100_FULL))
869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
870
871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
873 autoneg_reg);
874
875 ixgbe_restart_auto_neg(hw);
876 return status;
877}
878
885s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
886 ixgbe_link_speed speed,
887 bool autoneg_wait_to_complete)
888{
889 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
890
891 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
892
893 /*
894 * Clear autoneg_advertised and set new values based on input link
895 * speed.
896 */
897 hw->phy.autoneg_advertised = 0;
898
899 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
901
902 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
904
905 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
907
908 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
910
911 if (speed & IXGBE_LINK_SPEED_100_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
913
914 if (speed & IXGBE_LINK_SPEED_10_FULL)
915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
916
917 /* Setup link based on the new speed settings */
918 ixgbe_setup_phy_link(hw);
919
920 return IXGBE_SUCCESS;
921}
922
930static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
931{
932 s32 status;
933 u16 speed_ability;
934
935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
936 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
937 &speed_ability);
938 if (status)
939 return status;
940
941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
945 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
947
948 switch (hw->mac.type) {
949 case ixgbe_mac_X550:
950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
951 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
952 break;
953 case ixgbe_mac_X550EM_x:
954 case ixgbe_mac_X550EM_a:
955 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
956 break;
957 default:
958 break;
959 }
960
961 return status;
962}
963
970s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
971 ixgbe_link_speed *speed,
972 bool *autoneg)
973{
974 s32 status = IXGBE_SUCCESS;
975
976 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
977
978 *autoneg = true;
979 if (!hw->phy.speeds_supported)
980 status = ixgbe_get_copper_speeds_supported(hw);
981
982 *speed = hw->phy.speeds_supported;
983 return status;
984}
985
995s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
996 bool *link_up)
997{
998 s32 status = IXGBE_SUCCESS;
999 u32 time_out;
1000 u32 max_time_out = 10;
1001 u16 phy_link = 0;
1002 u16 phy_speed = 0;
1003 u16 phy_data = 0;
1004
1005 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1006
1007 /* Initialize speed and link to default case */
1008 *link_up = false;
1009 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1010
1011 /*
1012 * Check current speed and link status of the PHY register.
1013 * This is a vendor specific register and may have to
1014 * be changed for other copper PHYs.
1015 */
1016 for (time_out = 0; time_out < max_time_out; time_out++) {
1017 usec_delay(10);
1018 status = hw->phy.ops.read_reg(hw,
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1021 &phy_data);
1022 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1023 phy_speed = phy_data &
1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1025 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1026 *link_up = true;
1027 if (phy_speed ==
1028 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1029 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1030 break;
1031 }
1032 }
1033
1034 return status;
1035}
1036
1043s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1044{
1045 s32 status = IXGBE_SUCCESS;
1046 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1047 bool autoneg = false;
1048 ixgbe_link_speed speed;
1049
1050 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1051
1052 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1053
1054 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1055 /* Set or unset auto-negotiation 10G advertisement */
1056 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1058 &autoneg_reg);
1059
1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1061 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1062 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1063
1064 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1065 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066 autoneg_reg);
1067 }
1068
1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1070 /* Set or unset auto-negotiation 1G advertisement */
1071 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1073 &autoneg_reg);
1074
1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1077 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1078
1079 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081 autoneg_reg);
1082 }
1083
1084 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1085 /* Set or unset auto-negotiation 100M advertisement */
1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1088 &autoneg_reg);
1089
1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1092 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1093
1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1096 autoneg_reg);
1097 }
1098
1099 ixgbe_restart_auto_neg(hw);
1100 return status;
1101}
1102
1108s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1109 u16 *firmware_version)
1110{
1111 s32 status;
1112
1113 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1114
1115 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1116 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1117 firmware_version);
1118
1119 return status;
1120}
1121
1127s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1128 u16 *firmware_version)
1129{
1130 s32 status;
1131
1132 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1133
1134 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1135 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1136 firmware_version);
1137
1138 return status;
1139}
1140
1145s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1146{
1147 u16 phy_offset, control, eword, edata, block_crc;
1148 bool end_data = false;
1149 u16 list_offset, data_offset;
1150 u16 phy_data = 0;
1151 s32 ret_val = IXGBE_SUCCESS;
1152 u32 i;
1153
1154 DEBUGFUNC("ixgbe_reset_phy_nl");
1155
1156 /* Blocked by MNG FW so bail */
1157 if (ixgbe_check_reset_blocked(hw))
1158 goto out;
1159
1160 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1161 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1162
1163 /* reset the PHY and poll for completion */
1164 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1165 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1166 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1167
1168 for (i = 0; i < 100; i++) {
1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1171 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1172 break;
1173 msec_delay(10);
1174 }
1175
1176 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1177 DEBUGOUT("PHY reset did not complete.\n");
1178 ret_val = IXGBE_ERR_PHY;
1179 goto out;
1180 }
1181
1182 /* Get init offsets */
1183 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1184 &data_offset);
1185 if (ret_val != IXGBE_SUCCESS)
1186 goto out;
1187
1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1189 data_offset++;
1190 while (!end_data) {
1191 /*
1192 * Read control word from PHY init contents offset
1193 */
1194 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1195 if (ret_val)
1196 goto err_eeprom;
1197 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1198 IXGBE_CONTROL_SHIFT_NL;
1199 edata = eword & IXGBE_DATA_MASK_NL;
1200 switch (control) {
1201 case IXGBE_DELAY_NL:
1202 data_offset++;
1203 DEBUGOUT1("DELAY: %d MS\n", edata);
1204 msec_delay(edata);
1205 break;
1206 case IXGBE_DATA_NL:
1207 DEBUGOUT("DATA:\n");
1208 data_offset++;
1209 ret_val = hw->eeprom.ops.read(hw, data_offset,
1210 &phy_offset);
1211 if (ret_val)
1212 goto err_eeprom;
1213 data_offset++;
1214 for (i = 0; i < edata; i++) {
1215 ret_val = hw->eeprom.ops.read(hw, data_offset,
1216 &eword);
1217 if (ret_val)
1218 goto err_eeprom;
1219 hw->phy.ops.write_reg(hw, phy_offset,
1220 IXGBE_TWINAX_DEV, eword);
1221 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1222 phy_offset);
1223 data_offset++;
1224 phy_offset++;
1225 }
1226 break;
1227 case IXGBE_CONTROL_NL:
1228 data_offset++;
1229 DEBUGOUT("CONTROL:\n");
1230 if (edata == IXGBE_CONTROL_EOL_NL) {
1231 DEBUGOUT("EOL\n");
1232 end_data = true;
1233 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1234 DEBUGOUT("SOL\n");
1235 } else {
1236 DEBUGOUT("Bad control value\n");
1237 ret_val = IXGBE_ERR_PHY;
1238 goto out;
1239 }
1240 break;
1241 default:
1242 DEBUGOUT("Bad control type\n");
1243 ret_val = IXGBE_ERR_PHY;
1244 goto out;
1245 }
1246 }
1247
1248out:
1249 return ret_val;
1250
1251err_eeprom:
1252 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1253 "eeprom read at offset %d failed", data_offset);
1254 return IXGBE_ERR_PHY;
1255}
1256
1263s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1264{
1265 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1266
1267 DEBUGFUNC("ixgbe_identify_module_generic");
1268
1269 switch (hw->mac.ops.get_media_type(hw)) {
1270 case ixgbe_media_type_fiber:
1271 status = ixgbe_identify_sfp_module_generic(hw);
1272 break;
1273
1274 case ixgbe_media_type_fiber_qsfp:
1275 status = ixgbe_identify_qsfp_module_generic(hw);
1276 break;
1277
1278 default:
1279 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1280 status = IXGBE_ERR_SFP_NOT_PRESENT;
1281 break;
1282 }
1283
1284 return status;
1285}
1286
1293s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1294{
1295 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1296 u32 vendor_oui = 0;
1297 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1298 u8 identifier = 0;
1299 u8 comp_codes_1g = 0;
1300 u8 comp_codes_10g = 0;
1301 u8 oui_bytes[3] = {0, 0, 0};
1302 u8 cable_tech = 0;
1303 u8 cable_spec = 0;
1304 u16 enforce_sfp = 0;
1305
1306 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1307
1308 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1309 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1310 status = IXGBE_ERR_SFP_NOT_PRESENT;
1311 goto out;
1312 }
1313
1314 /* LAN ID is needed for I2C access */
1315 hw->mac.ops.set_lan_id(hw);
1316
1317 status = hw->phy.ops.read_i2c_eeprom(hw,
1318 IXGBE_SFF_IDENTIFIER,
1319 &identifier);
1320
1321 if (status != IXGBE_SUCCESS)
1322 goto err_read_i2c_eeprom;
1323
1324 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1325 hw->phy.type = ixgbe_phy_sfp_unsupported;
1326 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1327 } else {
1328 status = hw->phy.ops.read_i2c_eeprom(hw,
1329 IXGBE_SFF_1GBE_COMP_CODES,
1330 &comp_codes_1g);
1331
1332 if (status != IXGBE_SUCCESS)
1333 goto err_read_i2c_eeprom;
1334
1335 status = hw->phy.ops.read_i2c_eeprom(hw,
1336 IXGBE_SFF_10GBE_COMP_CODES,
1337 &comp_codes_10g);
1338
1339 if (status != IXGBE_SUCCESS)
1340 goto err_read_i2c_eeprom;
1341 status = hw->phy.ops.read_i2c_eeprom(hw,
1342 IXGBE_SFF_CABLE_TECHNOLOGY,
1343 &cable_tech);
1344
1345 if (status != IXGBE_SUCCESS)
1346 goto err_read_i2c_eeprom;
1347
1348 /* ID Module
1349 * =========
1350 * 0 SFP_DA_CU
1351 * 1 SFP_SR
1352 * 2 SFP_LR
1353 * 3 SFP_DA_CORE0 - 82599-specific
1354 * 4 SFP_DA_CORE1 - 82599-specific
1355 * 5 SFP_SR/LR_CORE0 - 82599-specific
1356 * 6 SFP_SR/LR_CORE1 - 82599-specific
1357 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1358 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1359 * 9 SFP_1g_cu_CORE0 - 82599-specific
1360 * 10 SFP_1g_cu_CORE1 - 82599-specific
1361 * 11 SFP_1g_sx_CORE0 - 82599-specific
1362 * 12 SFP_1g_sx_CORE1 - 82599-specific
1363 */
1364 if (hw->mac.type == ixgbe_mac_82598EB) {
1365 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1366 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1367 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1368 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1369 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1370 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1371 else
1372 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1373 } else {
1374 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1375 if (hw->bus.lan_id == 0)
1376 hw->phy.sfp_type =
1377 ixgbe_sfp_type_da_cu_core0;
1378 else
1379 hw->phy.sfp_type =
1380 ixgbe_sfp_type_da_cu_core1;
1381 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1382 hw->phy.ops.read_i2c_eeprom(
1383 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1384 &cable_spec);
1385 if (cable_spec &
1386 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1387 if (hw->bus.lan_id == 0)
1388 hw->phy.sfp_type =
1389 ixgbe_sfp_type_da_act_lmt_core0;
1390 else
1391 hw->phy.sfp_type =
1392 ixgbe_sfp_type_da_act_lmt_core1;
1393 } else {
1394 hw->phy.sfp_type =
1395 ixgbe_sfp_type_unknown;
1396 }
1397 } else if (comp_codes_10g &
1398 (IXGBE_SFF_10GBASESR_CAPABLE |
1399 IXGBE_SFF_10GBASELR_CAPABLE)) {
1400 if (hw->bus.lan_id == 0)
1401 hw->phy.sfp_type =
1402 ixgbe_sfp_type_srlr_core0;
1403 else
1404 hw->phy.sfp_type =
1405 ixgbe_sfp_type_srlr_core1;
1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1407 if (hw->bus.lan_id == 0)
1408 hw->phy.sfp_type =
1409 ixgbe_sfp_type_1g_cu_core0;
1410 else
1411 hw->phy.sfp_type =
1412 ixgbe_sfp_type_1g_cu_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1415 hw->phy.sfp_type =
1416 ixgbe_sfp_type_1g_sx_core0;
1417 else
1418 hw->phy.sfp_type =
1419 ixgbe_sfp_type_1g_sx_core1;
1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1421 if (hw->bus.lan_id == 0)
1422 hw->phy.sfp_type =
1423 ixgbe_sfp_type_1g_lx_core0;
1424 else
1425 hw->phy.sfp_type =
1426 ixgbe_sfp_type_1g_lx_core1;
1427 } else {
1428 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1429 }
1430 }
1431
1432 if (hw->phy.sfp_type != stored_sfp_type)
1433 hw->phy.sfp_setup_needed = true;
1434
1435 /* Determine if the SFP+ PHY is dual speed or not. */
1436 hw->phy.multispeed_fiber = false;
1437 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1438 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1439 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1440 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1441 hw->phy.multispeed_fiber = true;
1442
1443 /* Determine PHY vendor */
1444 if (hw->phy.type != ixgbe_phy_nl) {
1445 hw->phy.id = identifier;
1446 status = hw->phy.ops.read_i2c_eeprom(hw,
1447 IXGBE_SFF_VENDOR_OUI_BYTE0,
1448 &oui_bytes[0]);
1449
1450 if (status != IXGBE_SUCCESS)
1451 goto err_read_i2c_eeprom;
1452
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE1,
1455 &oui_bytes[1]);
1456
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1459
1460 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 IXGBE_SFF_VENDOR_OUI_BYTE2,
1462 &oui_bytes[2]);
1463
1464 if (status != IXGBE_SUCCESS)
1465 goto err_read_i2c_eeprom;
1466
1467 vendor_oui =
1468 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1469 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1470 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1471
1472 switch (vendor_oui) {
1473 case IXGBE_SFF_VENDOR_OUI_TYCO:
1474 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1475 hw->phy.type =
1476 ixgbe_phy_sfp_passive_tyco;
1477 break;
1478 case IXGBE_SFF_VENDOR_OUI_FTL:
1479 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1480 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1481 else
1482 hw->phy.type = ixgbe_phy_sfp_ftl;
1483 break;
1484 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1485 hw->phy.type = ixgbe_phy_sfp_avago;
1486 break;
1487 case IXGBE_SFF_VENDOR_OUI_INTEL:
1488 hw->phy.type = ixgbe_phy_sfp_intel;
1489 break;
1490 default:
1491 hw->phy.type = ixgbe_phy_sfp_unknown;
1492 break;
1493 }
1494 }
1495
1496 /* Allow any DA cable vendor */
1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1498 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1503 status = IXGBE_SUCCESS;
1504 goto out;
1505 }
1506
1507 /* Verify supported 1G SFP modules */
1508 if (comp_codes_10g == 0 &&
1509 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1515 hw->phy.type = ixgbe_phy_sfp_unsupported;
1516 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1517 goto out;
1518 }
1519
1520 /* Anything else 82598-based is supported */
1521 if (hw->mac.type == ixgbe_mac_82598EB) {
1522 status = IXGBE_SUCCESS;
1523 goto out;
1524 }
1525
1526 ixgbe_get_device_caps(hw, &enforce_sfp);
1527 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1528 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1534 /* Make sure we're a supported PHY type */
1535 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1536 status = IXGBE_SUCCESS;
1537 } else {
1538 if (hw->allow_unsupported_sfp == true) {
1539 EWARN(hw,
1540 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1541 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1542 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1543 status = IXGBE_SUCCESS;
1544 } else {
1545 DEBUGOUT("SFP+ module not supported\n");
1546 hw->phy.type =
1547 ixgbe_phy_sfp_unsupported;
1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1549 }
1550 }
1551 } else {
1552 status = IXGBE_SUCCESS;
1553 }
1554 }
1555
1556out:
1557 return status;
1558
1559err_read_i2c_eeprom:
1560 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1561 if (hw->phy.type != ixgbe_phy_nl) {
1562 hw->phy.id = 0;
1563 hw->phy.type = ixgbe_phy_unknown;
1564 }
1565 return IXGBE_ERR_SFP_NOT_PRESENT;
1566}
1567
1574u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1575{
1576 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1577 u8 comp_codes_10g = 0;
1578 u8 comp_codes_1g = 0;
1579
1580 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1581
1582 hw->phy.ops.identify_sfp(hw);
1583 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584 return physical_layer;
1585
1586 switch (hw->phy.type) {
1587 case ixgbe_phy_sfp_passive_tyco:
1588 case ixgbe_phy_sfp_passive_unknown:
1589 case ixgbe_phy_qsfp_passive_unknown:
1590 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1591 break;
1592 case ixgbe_phy_sfp_ftl_active:
1593 case ixgbe_phy_sfp_active_unknown:
1594 case ixgbe_phy_qsfp_active_unknown:
1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1596 break;
1597 case ixgbe_phy_sfp_avago:
1598 case ixgbe_phy_sfp_ftl:
1599 case ixgbe_phy_sfp_intel:
1600 case ixgbe_phy_sfp_unknown:
1601 hw->phy.ops.read_i2c_eeprom(hw,
1602 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1603 hw->phy.ops.read_i2c_eeprom(hw,
1604 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1605 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1607 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1609 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1610 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1611 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1613 break;
1614 case ixgbe_phy_qsfp_intel:
1615 case ixgbe_phy_qsfp_unknown:
1616 hw->phy.ops.read_i2c_eeprom(hw,
1617 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1618 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1620 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1622 break;
1623 default:
1624 break;
1625 }
1626
1627 return physical_layer;
1628}
1629
1636s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1637{
1638 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1639 u32 vendor_oui = 0;
1640 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1641 u8 identifier = 0;
1642 u8 comp_codes_1g = 0;
1643 u8 comp_codes_10g = 0;
1644 u8 oui_bytes[3] = {0, 0, 0};
1645 u16 enforce_sfp = 0;
1646 u8 connector = 0;
1647 u8 cable_length = 0;
1648 u8 device_tech = 0;
1649 bool active_cable = false;
1650
1651 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1652
1653 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1654 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1655 status = IXGBE_ERR_SFP_NOT_PRESENT;
1656 goto out;
1657 }
1658
1659 /* LAN ID is needed for I2C access */
1660 hw->mac.ops.set_lan_id(hw);
1661
1662 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1663 &identifier);
1664
1665 if (status != IXGBE_SUCCESS)
1666 goto err_read_i2c_eeprom;
1667
1668 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1669 hw->phy.type = ixgbe_phy_sfp_unsupported;
1670 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1671 goto out;
1672 }
1673
1674 hw->phy.id = identifier;
1675
1676 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1677 &comp_codes_10g);
1678
1679 if (status != IXGBE_SUCCESS)
1680 goto err_read_i2c_eeprom;
1681
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1683 &comp_codes_1g);
1684
1685 if (status != IXGBE_SUCCESS)
1686 goto err_read_i2c_eeprom;
1687
1688 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1689 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1690 if (hw->bus.lan_id == 0)
1691 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1692 else
1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1694 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1695 IXGBE_SFF_10GBASELR_CAPABLE)) {
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1698 else
1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1700 } else {
1701 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1702 active_cable = true;
1703
1704 if (!active_cable) {
1705 /* check for active DA cables that pre-date
1706 * SFF-8436 v3.6 */
1707 hw->phy.ops.read_i2c_eeprom(hw,
1708 IXGBE_SFF_QSFP_CONNECTOR,
1709 &connector);
1710
1711 hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_CABLE_LENGTH,
1713 &cable_length);
1714
1715 hw->phy.ops.read_i2c_eeprom(hw,
1716 IXGBE_SFF_QSFP_DEVICE_TECH,
1717 &device_tech);
1718
1719 if ((connector ==
1720 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1721 (cable_length > 0) &&
1722 ((device_tech >> 4) ==
1723 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1724 active_cable = true;
1725 }
1726
1727 if (active_cable) {
1728 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1729 if (hw->bus.lan_id == 0)
1730 hw->phy.sfp_type =
1731 ixgbe_sfp_type_da_act_lmt_core0;
1732 else
1733 hw->phy.sfp_type =
1734 ixgbe_sfp_type_da_act_lmt_core1;
1735 } else {
1736 /* unsupported module type */
1737 hw->phy.type = ixgbe_phy_sfp_unsupported;
1738 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1739 goto out;
1740 }
1741 }
1742
1743 if (hw->phy.sfp_type != stored_sfp_type)
1744 hw->phy.sfp_setup_needed = true;
1745
1746 /* Determine if the QSFP+ PHY is dual speed or not. */
1747 hw->phy.multispeed_fiber = false;
1748 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1749 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1750 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1751 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1752 hw->phy.multispeed_fiber = true;
1753
1754 /* Determine PHY vendor for optical modules */
1755 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1756 IXGBE_SFF_10GBASELR_CAPABLE)) {
1757 status = hw->phy.ops.read_i2c_eeprom(hw,
1758 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1759 &oui_bytes[0]);
1760
1761 if (status != IXGBE_SUCCESS)
1762 goto err_read_i2c_eeprom;
1763
1764 status = hw->phy.ops.read_i2c_eeprom(hw,
1765 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1766 &oui_bytes[1]);
1767
1768 if (status != IXGBE_SUCCESS)
1769 goto err_read_i2c_eeprom;
1770
1771 status = hw->phy.ops.read_i2c_eeprom(hw,
1772 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1773 &oui_bytes[2]);
1774
1775 if (status != IXGBE_SUCCESS)
1776 goto err_read_i2c_eeprom;
1777
1778 vendor_oui =
1779 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1780 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1781 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1782
1783 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1784 hw->phy.type = ixgbe_phy_qsfp_intel;
1785 else
1786 hw->phy.type = ixgbe_phy_qsfp_unknown;
1787
1788 ixgbe_get_device_caps(hw, &enforce_sfp);
1789 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1790 /* Make sure we're a supported PHY type */
1791 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1792 status = IXGBE_SUCCESS;
1793 } else {
1794 if (hw->allow_unsupported_sfp == true) {
1795 EWARN(hw,
1796 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1797 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1798 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1799 status = IXGBE_SUCCESS;
1800 } else {
1801 DEBUGOUT("QSFP module not supported\n");
1802 hw->phy.type =
1803 ixgbe_phy_sfp_unsupported;
1804 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1805 }
1806 }
1807 } else {
1808 status = IXGBE_SUCCESS;
1809 }
1810 }
1811
1812out:
1813 return status;
1814
1815err_read_i2c_eeprom:
1816 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1817 hw->phy.id = 0;
1818 hw->phy.type = ixgbe_phy_unknown;
1819
1820 return IXGBE_ERR_SFP_NOT_PRESENT;
1821}
1822
1832s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1833 u16 *list_offset,
1834 u16 *data_offset)
1835{
1836 u16 sfp_id;
1837 u16 sfp_type = hw->phy.sfp_type;
1838
1839 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1840
1841 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1842 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1843
1844 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1845 return IXGBE_ERR_SFP_NOT_PRESENT;
1846
1847 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1848 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1849 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1850
1851 /*
1852 * Limiting active cables and 1G Phys must be initialized as
1853 * SR modules
1854 */
1855 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1856 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1857 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1858 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1859 sfp_type = ixgbe_sfp_type_srlr_core0;
1860 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1861 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1862 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1863 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1864 sfp_type = ixgbe_sfp_type_srlr_core1;
1865
1866 /* Read offset to PHY init contents */
1867 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1868 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1869 "eeprom read at offset %d failed",
1870 IXGBE_PHY_INIT_OFFSET_NL);
1871 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1872 }
1873
1874 if ((!*list_offset) || (*list_offset == 0xFFFF))
1875 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1876
1877 /* Shift offset to first ID word */
1878 (*list_offset)++;
1879
1880 /*
1881 * Find the matching SFP ID in the EEPROM
1882 * and program the init sequence
1883 */
1884 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1885 goto err_phy;
1886
1887 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1888 if (sfp_id == sfp_type) {
1889 (*list_offset)++;
1890 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1891 goto err_phy;
1892 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1893 DEBUGOUT("SFP+ module not supported\n");
1894 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1895 } else {
1896 break;
1897 }
1898 } else {
1899 (*list_offset) += 2;
1900 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1901 goto err_phy;
1902 }
1903 }
1904
1905 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1906 DEBUGOUT("No matching SFP+ module found\n");
1907 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1908 }
1909
1910 return IXGBE_SUCCESS;
1911
1912err_phy:
1913 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1914 "eeprom read at offset %d failed", *list_offset);
1915 return IXGBE_ERR_PHY;
1916}
1917
1926s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1927 u8 *eeprom_data)
1928{
1929 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1930
1931 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1932 IXGBE_I2C_EEPROM_DEV_ADDR,
1933 eeprom_data);
1934}
1935
1944static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1945 u8 *sff8472_data)
1946{
1947 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1948 IXGBE_I2C_EEPROM_DEV_ADDR2,
1949 sff8472_data);
1950}
1951
1960s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1961 u8 eeprom_data)
1962{
1963 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1964
1965 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1966 IXGBE_I2C_EEPROM_DEV_ADDR,
1967 eeprom_data);
1968}
1969
1976static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1977{
1978 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1979 offset == IXGBE_SFF_IDENTIFIER &&
1980 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1981 return true;
1982 return false;
1983}
1984
1996static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1997 u8 dev_addr, u8 *data, bool lock)
1998{
1999 s32 status;
2000 u32 max_retry = 10;
2001 u32 retry = 0;
2002 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2003 bool nack = 1;
2004 *data = 0;
2005
2006 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2007
2008 if (hw->mac.type >= ixgbe_mac_X550)
2009 max_retry = 3;
2010 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2011 max_retry = IXGBE_SFP_DETECT_RETRIES;
2012
2013 do {
2014 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2015 return IXGBE_ERR_SWFW_SYNC;
2016
2017 ixgbe_i2c_start(hw);
2018
2019 /* Device Address and write indication */
2020 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2021 if (status != IXGBE_SUCCESS)
2022 goto fail;
2023
2024 status = ixgbe_get_i2c_ack(hw);
2025 if (status != IXGBE_SUCCESS)
2026 goto fail;
2027
2028 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2029 if (status != IXGBE_SUCCESS)
2030 goto fail;
2031
2032 status = ixgbe_get_i2c_ack(hw);
2033 if (status != IXGBE_SUCCESS)
2034 goto fail;
2035
2036 ixgbe_i2c_start(hw);
2037
2038 /* Device Address and read indication */
2039 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2040 if (status != IXGBE_SUCCESS)
2041 goto fail;
2042
2043 status = ixgbe_get_i2c_ack(hw);
2044 if (status != IXGBE_SUCCESS)
2045 goto fail;
2046
2047 ixgbe_clock_in_i2c_byte(hw, data);
2048
2049 status = ixgbe_clock_out_i2c_bit(hw, nack);
2050 if (status != IXGBE_SUCCESS)
2051 goto fail;
2052
2053 ixgbe_i2c_stop(hw);
2054 if (lock)
2055 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2056 return IXGBE_SUCCESS;
2057
2058fail:
2059 ixgbe_i2c_bus_clear(hw);
2060 if (lock) {
2061 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2062 msec_delay(100);
2063 }
2064 if (retry < max_retry)
2065 DEBUGOUT("I2C byte read error - Retrying.\n");
2066 else
2067 DEBUGOUT("I2C byte read error.\n");
2068 retry++;
2069 } while (retry <= max_retry);
2070
2071 return status;
2072}
2073
2084s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2085 u8 dev_addr, u8 *data)
2086{
2087 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2088 data, true);
2089}
2090
2101s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2102 u8 dev_addr, u8 *data)
2103{
2104 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2105 data, false);
2106}
2107
2119static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2120 u8 dev_addr, u8 data, bool lock)
2121{
2122 s32 status;
2123 u32 max_retry = 1;
2124 u32 retry = 0;
2125 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2126
2127 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2128
2129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2130 IXGBE_SUCCESS)
2131 return IXGBE_ERR_SWFW_SYNC;
2132
2133 do {
2134 ixgbe_i2c_start(hw);
2135
2136 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2137 if (status != IXGBE_SUCCESS)
2138 goto fail;
2139
2140 status = ixgbe_get_i2c_ack(hw);
2141 if (status != IXGBE_SUCCESS)
2142 goto fail;
2143
2144 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2145 if (status != IXGBE_SUCCESS)
2146 goto fail;
2147
2148 status = ixgbe_get_i2c_ack(hw);
2149 if (status != IXGBE_SUCCESS)
2150 goto fail;
2151
2152 status = ixgbe_clock_out_i2c_byte(hw, data);
2153 if (status != IXGBE_SUCCESS)
2154 goto fail;
2155
2156 status = ixgbe_get_i2c_ack(hw);
2157 if (status != IXGBE_SUCCESS)
2158 goto fail;
2159
2160 ixgbe_i2c_stop(hw);
2161 if (lock)
2162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2163 return IXGBE_SUCCESS;
2164
2165fail:
2166 ixgbe_i2c_bus_clear(hw);
2167 if (retry < max_retry)
2168 DEBUGOUT("I2C byte write error - Retrying.\n");
2169 else
2170 DEBUGOUT("I2C byte write error.\n");
2171 retry++;
2172 } while (retry <= max_retry);
2173
2174 if (lock)
2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176
2177 return status;
2178}
2179
2190s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2191 u8 dev_addr, u8 data)
2192{
2193 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2194 data, true);
2195}
2196
2207s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2208 u8 dev_addr, u8 data)
2209{
2210 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2211 data, false);
2212}
2213
2221static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2222{
2223 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2224
2225 DEBUGFUNC("ixgbe_i2c_start");
2226
2227 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2228
2229 /* Start condition must begin with data and clock high */
2230 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2231 ixgbe_raise_i2c_clk(hw, &i2cctl);
2232
2233 /* Setup time for start condition (4.7us) */
2234 usec_delay(IXGBE_I2C_T_SU_STA);
2235
2236 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2237
2238 /* Hold time for start condition (4us) */
2239 usec_delay(IXGBE_I2C_T_HD_STA);
2240
2241 ixgbe_lower_i2c_clk(hw, &i2cctl);
2242
2243 /* Minimum low period of clock is 4.7 us */
2244 usec_delay(IXGBE_I2C_T_LOW);
2245
2246}
2247
2256static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2257{
2258 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2259 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2260 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2261 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2262
2263 DEBUGFUNC("ixgbe_i2c_stop");
2264
2265 /* Stop condition must begin with data low and clock high */
2266 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2267 ixgbe_raise_i2c_clk(hw, &i2cctl);
2268
2269 /* Setup time for stop condition (4us) */
2270 usec_delay(IXGBE_I2C_T_SU_STO);
2271
2272 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2273
2274 /* bus free time between stop and start (4.7us)*/
2275 usec_delay(IXGBE_I2C_T_BUF);
2276
2277 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2278 i2cctl &= ~bb_en_bit;
2279 i2cctl |= data_oe_bit | clk_oe_bit;
2280 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2281 IXGBE_WRITE_FLUSH(hw);
2282 }
2283}
2284
2292static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2293{
2294 s32 i;
2295 bool bit = 0;
2296
2297 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2298
2299 *data = 0;
2300 for (i = 7; i >= 0; i--) {
2301 ixgbe_clock_in_i2c_bit(hw, &bit);
2302 *data |= bit << i;
2303 }
2304}
2305
2313static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2314{
2315 s32 status = IXGBE_SUCCESS;
2316 s32 i;
2317 u32 i2cctl;
2318 bool bit;
2319
2320 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2321
2322 for (i = 7; i >= 0; i--) {
2323 bit = (data >> i) & 0x1;
2324 status = ixgbe_clock_out_i2c_bit(hw, bit);
2325
2326 if (status != IXGBE_SUCCESS)
2327 break;
2328 }
2329
2330 /* Release SDA line (set high) */
2331 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2332 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2333 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2334 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2335 IXGBE_WRITE_FLUSH(hw);
2336
2337 return status;
2338}
2339
2346static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2347{
2348 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2349 s32 status = IXGBE_SUCCESS;
2350 u32 i = 0;
2351 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2352 u32 timeout = 10;
2353 bool ack = 1;
2354
2355 DEBUGFUNC("ixgbe_get_i2c_ack");
2356
2357 if (data_oe_bit) {
2358 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2359 i2cctl |= data_oe_bit;
2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2361 IXGBE_WRITE_FLUSH(hw);
2362 }
2363 ixgbe_raise_i2c_clk(hw, &i2cctl);
2364
2365 /* Minimum high period of clock is 4us */
2366 usec_delay(IXGBE_I2C_T_HIGH);
2367
2368 /* Poll for ACK. Note that ACK in I2C spec is
2369 * transition from 1 to 0 */
2370 for (i = 0; i < timeout; i++) {
2371 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2372 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2373
2374 usec_delay(1);
2375 if (!ack)
2376 break;
2377 }
2378
2379 if (ack) {
2380 DEBUGOUT("I2C ack was not received.\n");
2381 status = IXGBE_ERR_I2C;
2382 }
2383
2384 ixgbe_lower_i2c_clk(hw, &i2cctl);
2385
2386 /* Minimum low period of clock is 4.7 us */
2387 usec_delay(IXGBE_I2C_T_LOW);
2388
2389 return status;
2390}
2391
2399static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2400{
2401 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2402 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2403
2404 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2405
2406 if (data_oe_bit) {
2407 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2408 i2cctl |= data_oe_bit;
2409 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2410 IXGBE_WRITE_FLUSH(hw);
2411 }
2412 ixgbe_raise_i2c_clk(hw, &i2cctl);
2413
2414 /* Minimum high period of clock is 4us */
2415 usec_delay(IXGBE_I2C_T_HIGH);
2416
2417 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2418 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2419
2420 ixgbe_lower_i2c_clk(hw, &i2cctl);
2421
2422 /* Minimum low period of clock is 4.7 us */
2423 usec_delay(IXGBE_I2C_T_LOW);
2424}
2425
2433static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2434{
2435 s32 status;
2436 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2437
2438 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2439
2440 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2441 if (status == IXGBE_SUCCESS) {
2442 ixgbe_raise_i2c_clk(hw, &i2cctl);
2443
2444 /* Minimum high period of clock is 4us */
2445 usec_delay(IXGBE_I2C_T_HIGH);
2446
2447 ixgbe_lower_i2c_clk(hw, &i2cctl);
2448
2449 /* Minimum low period of clock is 4.7 us.
2450 * This also takes care of the data hold time.
2451 */
2452 usec_delay(IXGBE_I2C_T_LOW);
2453 } else {
2454 status = IXGBE_ERR_I2C;
2455 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2456 "I2C data was not set to %X\n", data);
2457 }
2458
2459 return status;
2460}
2461
2470static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2471{
2472 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2473 u32 i = 0;
2474 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2475 u32 i2cctl_r = 0;
2476
2477 DEBUGFUNC("ixgbe_raise_i2c_clk");
2478
2479 if (clk_oe_bit) {
2480 *i2cctl |= clk_oe_bit;
2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2482 }
2483
2484 for (i = 0; i < timeout; i++) {
2485 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2486
2487 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2488 IXGBE_WRITE_FLUSH(hw);
2489 /* SCL rise time (1000ns) */
2490 usec_delay(IXGBE_I2C_T_RISE);
2491
2492 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2493 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2494 break;
2495 }
2496}
2497
2506static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2507{
2508 DEBUGFUNC("ixgbe_lower_i2c_clk");
2509
2510 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2511 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2512
2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2514 IXGBE_WRITE_FLUSH(hw);
2515
2516 /* SCL fall time (300ns) */
2517 usec_delay(IXGBE_I2C_T_FALL);
2518}
2519
2529static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2530{
2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2532 s32 status = IXGBE_SUCCESS;
2533
2534 DEBUGFUNC("ixgbe_set_i2c_data");
2535
2536 if (data)
2537 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2538 else
2539 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2540 *i2cctl &= ~data_oe_bit;
2541
2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2543 IXGBE_WRITE_FLUSH(hw);
2544
2545 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2546 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2547
2548 if (!data) /* Can't verify data in this case */
2549 return IXGBE_SUCCESS;
2550 if (data_oe_bit) {
2551 *i2cctl |= data_oe_bit;
2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553 IXGBE_WRITE_FLUSH(hw);
2554 }
2555
2556 /* Verify data was set correctly */
2557 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2558 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2559 status = IXGBE_ERR_I2C;
2560 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2561 "Error - I2C data was not set to %X.\n",
2562 data);
2563 }
2564
2565 return status;
2566}
2567
2576static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2577{
2578 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2579 bool data;
2580
2581 DEBUGFUNC("ixgbe_get_i2c_data");
2582
2583 if (data_oe_bit) {
2584 *i2cctl |= data_oe_bit;
2585 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2586 IXGBE_WRITE_FLUSH(hw);
2587 usec_delay(IXGBE_I2C_T_FALL);
2588 }
2589
2590 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2591 data = 1;
2592 else
2593 data = 0;
2594
2595 return data;
2596}
2597
2605void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2606{
2607 u32 i2cctl;
2608 u32 i;
2609
2610 DEBUGFUNC("ixgbe_i2c_bus_clear");
2611
2612 ixgbe_i2c_start(hw);
2613 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2614
2615 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2616
2617 for (i = 0; i < 9; i++) {
2618 ixgbe_raise_i2c_clk(hw, &i2cctl);
2619
2620 /* Min high period of clock is 4us */
2621 usec_delay(IXGBE_I2C_T_HIGH);
2622
2623 ixgbe_lower_i2c_clk(hw, &i2cctl);
2624
2625 /* Min low period of clock is 4.7us*/
2626 usec_delay(IXGBE_I2C_T_LOW);
2627 }
2628
2629 ixgbe_i2c_start(hw);
2630
2631 /* Put the i2c bus back to default state */
2632 ixgbe_i2c_stop(hw);
2633}
2634
2641s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2642{
2643 s32 status = IXGBE_SUCCESS;
2644 u16 phy_data = 0;
2645
2646 DEBUGFUNC("ixgbe_tn_check_overtemp");
2647
2648 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2649 goto out;
2650
2651 /* Check that the LASI temp alarm status was triggered */
2652 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2653 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2654
2655 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2656 goto out;
2657
2658 status = IXGBE_ERR_OVERTEMP;
2659 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2660out:
2661 return status;
2662}
2663
2669s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2670{
2671 u32 status;
2672 u16 reg;
2673
2674 if (!on && ixgbe_mng_present(hw))
2675 return 0;
2676
2677 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2678 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2679 &reg);
2680 if (status)
2681 return status;
2682
2683 if (on) {
2684 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2685 } else {
2686 if (ixgbe_check_reset_blocked(hw))
2687 return 0;
2688 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2689 }
2690
2691 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2692 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2693 reg);
2694 return status;
2695}
ixgbe_get_device_caps
s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
Definition: ixgbe_api.c:387
ixgbe_setup_phy_link
s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:595
ixgbe_api.h
ixgbe_mng_present
bool ixgbe_mng_present(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:5444
ixgbe_common.h
msec_delay
#define msec_delay(x)
Definition: ixgbe_osdep.h:72
IXGBE_READ_REG
#define IXGBE_READ_REG(a, reg)
Definition: ixgbe_osdep.h:224
EWARN
#define EWARN(H, W)
Definition: ixgbe_osdep.h:59
DEBUGOUT
#define DEBUGOUT(S)
Definition: ixgbe_osdep.h:104
u64
uint64_t u64
Definition: ixgbe_osdep.h:149
usec_delay
#define usec_delay(x)
Definition: ixgbe_osdep.h:71
DEBUGOUT2
#define DEBUGOUT2(S, A, B)
Definition: ixgbe_osdep.h:106
ERROR_REPORT1
#define ERROR_REPORT1(S, A)
Definition: ixgbe_osdep.h:113
u8
uint8_t u8
Definition: ixgbe_osdep.h:143
DEBUGFUNC
#define DEBUGFUNC(F)
Definition: ixgbe_osdep.h:76
DEBUGOUT1
#define DEBUGOUT1(S, A)
Definition: ixgbe_osdep.h:105
UNREFERENCED_1PARAMETER
#define UNREFERENCED_1PARAMETER(_p)
Definition: ixgbe_osdep.h:126
IXGBE_WRITE_FLUSH
#define IXGBE_WRITE_FLUSH(a)
Definition: ixgbe_osdep.h:221
IXGBE_WRITE_REG
#define IXGBE_WRITE_REG(a, reg, val)
Definition: ixgbe_osdep.h:227
u16
uint16_t u16
Definition: ixgbe_osdep.h:145
ERROR_REPORT2
#define ERROR_REPORT2(S, A, B)
Definition: ixgbe_osdep.h:114
IXGBE_ERROR_CAUTION
@ IXGBE_ERROR_CAUTION
Definition: ixgbe_osdep.h:67
IXGBE_ERROR_POLLING
@ IXGBE_ERROR_POLLING
Definition: ixgbe_osdep.h:63
IXGBE_ERROR_INVALID_STATE
@ IXGBE_ERROR_INVALID_STATE
Definition: ixgbe_osdep.h:64
IXGBE_ERROR_SOFTWARE
@ IXGBE_ERROR_SOFTWARE
Definition: ixgbe_osdep.h:62
s32
int32_t s32
Definition: ixgbe_osdep.h:148
u32
uint32_t u32
Definition: ixgbe_osdep.h:147
ixgbe_tn_check_overtemp
s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:2641
ixgbe_identify_phy_generic
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:322
ixgbe_clock_out_i2c_bit
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
Definition: ixgbe_phy.c:2433
ixgbe_get_phy_id
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:425
ixgbe_get_copper_link_capabilities_generic
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
Definition: ixgbe_phy.c:970
ixgbe_set_i2c_data
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
Definition: ixgbe_phy.c:2529
ixgbe_write_i2c_byte_generic_unlocked
s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data)
Definition: ixgbe_phy.c:2207
ixgbe_raise_i2c_clk
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
Definition: ixgbe_phy.c:2470
ixgbe_get_i2c_data
static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
Definition: ixgbe_phy.c:2576
ixgbe_write_i2c_byte_generic
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data)
Definition: ixgbe_phy.c:2190
ixgbe_get_sfp_init_sequence_offsets
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, u16 *list_offset, u16 *data_offset)
Definition: ixgbe_phy.c:1832
ixgbe_in_i2c_byte_ack
static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
Definition: ixgbe_phy.c:78
ixgbe_identify_module_generic
s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:1263
ixgbe_clock_in_i2c_bit
static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
Definition: ixgbe_phy.c:2399
ixgbe_get_phy_firmware_version_tnx
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version)
Definition: ixgbe_phy.c:1108
ixgbe_get_phy_type_from_id
enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
Definition: ixgbe_phy.c:456
ixgbe_setup_phy_link_generic
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:806
ixgbe_get_supported_phy_sfp_layer_generic
u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:1574
ixgbe_read_i2c_sff8472_generic
static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 *sff8472_data)
Definition: ixgbe_phy.c:1944
ixgbe_i2c_stop
static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:2256
ixgbe_validate_phy_addr
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
Definition: ixgbe_phy.c:401
ixgbe_set_copper_phy_power
s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
Definition: ixgbe_phy.c:2669
ixgbe_read_i2c_eeprom_generic
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
Definition: ixgbe_phy.c:1926
ixgbe_read_phy_reg_generic
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
Definition: ixgbe_phy.c:681
ixgbe_setup_phy_link_tnx
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:1043
ixgbe_setup_phy_link_speed_generic
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
Definition: ixgbe_phy.c:885
ixgbe_clock_out_i2c_byte
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
Definition: ixgbe_phy.c:2313
ixgbe_check_phy_link_tnx
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up)
Definition: ixgbe_phy.c:995
ixgbe_reset_phy_nl
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:1145
ixgbe_i2c_start
static void ixgbe_i2c_start(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:2221
ixgbe_init_phy_ops_generic
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:248
ixgbe_read_i2c_byte_generic_int
static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data, bool lock)
Definition: ixgbe_phy.c:1996
ixgbe_write_i2c_combined_generic_int
s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val, bool lock)
Definition: ixgbe_phy.c:187
ixgbe_read_i2c_byte_generic_unlocked
s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data)
Definition: ixgbe_phy.c:2101
ixgbe_get_i2c_ack
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:2346
ixgbe_identify_qsfp_module_generic
s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:1636
ixgbe_restart_auto_neg
void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:575
ixgbe_get_copper_speeds_supported
static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:930
ixgbe_probe_phy
static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
Definition: ixgbe_phy.c:287
ixgbe_write_phy_reg_mdi
s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
Definition: ixgbe_phy.c:707
ixgbe_check_reset_blocked
s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:375
ixgbe_i2c_bus_clear
void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:2605
ixgbe_out_i2c_byte_ack
static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
Definition: ixgbe_phy.c:61
ixgbe_write_phy_reg_generic
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
Definition: ixgbe_phy.c:781
ixgbe_ones_comp_byte_add
static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
Definition: ixgbe_phy.c:92
ixgbe_lower_i2c_clk
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
Definition: ixgbe_phy.c:2506
ixgbe_read_i2c_byte_generic
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data)
Definition: ixgbe_phy.c:2084
ixgbe_get_phy_firmware_version_generic
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, u16 *firmware_version)
Definition: ixgbe_phy.c:1127
ixgbe_is_sfp_probe
static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
Definition: ixgbe_phy.c:1976
ixgbe_write_i2c_byte_generic_int
static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data, bool lock)
Definition: ixgbe_phy.c:2119
ixgbe_identify_sfp_module_generic
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:1293
ixgbe_read_i2c_combined_generic_int
s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val, bool lock)
Definition: ixgbe_phy.c:110
ixgbe_read_phy_reg_mdi
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
Definition: ixgbe_phy.c:599
ixgbe_reset_phy_generic
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
Definition: ixgbe_phy.c:496
ixgbe_clock_in_i2c_byte
static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
Definition: ixgbe_phy.c:2292
ixgbe_write_i2c_eeprom_generic
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data)
Definition: ixgbe_phy.c:1960
ixgbe_phy.h
IXGBE_I2C_T_FALL
#define IXGBE_I2C_T_FALL
Definition: ixgbe_phy.h:146
IXGBE_SFF_1GBASELX_CAPABLE
#define IXGBE_SFF_1GBASELX_CAPABLE
Definition: ixgbe_phy.h:73
IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE
#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE
Definition: ixgbe_phy.h:83
IXGBE_SFF_QSFP_DEVICE_TECH
#define IXGBE_SFF_QSFP_DEVICE_TECH
Definition: ixgbe_phy.h:66
IXGBE_SFF_VENDOR_OUI_BYTE2
#define IXGBE_SFF_VENDOR_OUI_BYTE2
Definition: ixgbe_phy.h:49
IXGBE_SFF_VENDOR_OUI_TYCO
#define IXGBE_SFF_VENDOR_OUI_TYCO
Definition: ixgbe_phy.h:133
IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT
Definition: ixgbe_phy.h:130
IXGBE_SFF_QSFP_DA_ACTIVE_CABLE
#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE
Definition: ixgbe_phy.h:81
IXGBE_SFF_VENDOR_OUI_BYTE1
#define IXGBE_SFF_VENDOR_OUI_BYTE1
Definition: ixgbe_phy.h:48
IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1
Definition: ixgbe_phy.h:60
IXGBE_SFF_VENDOR_OUI_AVAGO
#define IXGBE_SFF_VENDOR_OUI_AVAGO
Definition: ixgbe_phy.h:135
IXGBE_SFF_IDENTIFIER
#define IXGBE_SFF_IDENTIFIER
Definition: ixgbe_phy.h:45
IXGBE_SFF_VENDOR_OUI_INTEL
#define IXGBE_SFF_VENDOR_OUI_INTEL
Definition: ixgbe_phy.h:136
IXGBE_SFF_VENDOR_OUI_BYTE0
#define IXGBE_SFF_VENDOR_OUI_BYTE0
Definition: ixgbe_phy.h:47
IXGBE_SFF_IDENTIFIER_QSFP_PLUS
#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS
Definition: ixgbe_phy.h:58
IXGBE_SFF_DA_PASSIVE_CABLE
#define IXGBE_SFF_DA_PASSIVE_CABLE
Definition: ixgbe_phy.h:69
IXGBE_SFF_CABLE_TECHNOLOGY
#define IXGBE_SFF_CABLE_TECHNOLOGY
Definition: ixgbe_phy.h:52
IXGBE_I2C_T_HD_STA
#define IXGBE_I2C_T_HD_STA
Definition: ixgbe_phy.h:139
IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2
Definition: ixgbe_phy.h:61
IXGBE_TN_LASI_STATUS_REG
#define IXGBE_TN_LASI_STATUS_REG
Definition: ixgbe_phy.h:152
IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT
Definition: ixgbe_phy.h:129
IXGBE_SFP_DETECT_RETRIES
#define IXGBE_SFP_DETECT_RETRIES
Definition: ixgbe_phy.h:150
IXGBE_SFF_QSFP_CABLE_LENGTH
#define IXGBE_SFF_QSFP_CABLE_LENGTH
Definition: ixgbe_phy.h:65
IXGBE_SFF_VENDOR_OUI_FTL
#define IXGBE_SFF_VENDOR_OUI_FTL
Definition: ixgbe_phy.h:134
IXGBE_I2C_T_SU_DATA
#define IXGBE_I2C_T_SU_DATA
Definition: ixgbe_phy.h:144
IXGBE_I2C_T_BUF
#define IXGBE_I2C_T_BUF
Definition: ixgbe_phy.h:148
IXGBE_SFF_10GBASELR_CAPABLE
#define IXGBE_SFF_10GBASELR_CAPABLE
Definition: ixgbe_phy.h:76
IXGBE_I2C_T_RISE
#define IXGBE_I2C_T_RISE
Definition: ixgbe_phy.h:145
IXGBE_SFF_QSFP_10GBE_COMP
#define IXGBE_SFF_QSFP_10GBE_COMP
Definition: ixgbe_phy.h:63
IXGBE_SFF_QSFP_1GBE_COMP
#define IXGBE_SFF_QSFP_1GBE_COMP
Definition: ixgbe_phy.h:64
IXGBE_SFF_DA_ACTIVE_CABLE
#define IXGBE_SFF_DA_ACTIVE_CABLE
Definition: ixgbe_phy.h:70
IXGBE_I2C_EEPROM_DEV_ADDR
#define IXGBE_I2C_EEPROM_DEV_ADDR
Definition: ixgbe_phy.h:40
IXGBE_I2C_EEPROM_DEV_ADDR2
#define IXGBE_I2C_EEPROM_DEV_ADDR2
Definition: ixgbe_phy.h:41
IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING
#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING
Definition: ixgbe_phy.h:71
IXGBE_I2C_T_LOW
#define IXGBE_I2C_T_LOW
Definition: ixgbe_phy.h:140
IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL
#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL
Definition: ixgbe_phy.h:84
IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT
Definition: ixgbe_phy.h:128
IXGBE_SFF_IDENTIFIER_SFP
#define IXGBE_SFF_IDENTIFIER_SFP
Definition: ixgbe_phy.h:46
IXGBE_SFF_10GBE_COMP_CODES
#define IXGBE_SFF_10GBE_COMP_CODES
Definition: ixgbe_phy.h:51
IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0
Definition: ixgbe_phy.h:59
IXGBE_SFF_QSFP_CONNECTOR
#define IXGBE_SFF_QSFP_CONNECTOR
Definition: ixgbe_phy.h:62
IXGBE_SFF_CABLE_SPEC_COMP
#define IXGBE_SFF_CABLE_SPEC_COMP
Definition: ixgbe_phy.h:53
IXGBE_I2C_T_HIGH
#define IXGBE_I2C_T_HIGH
Definition: ixgbe_phy.h:141
IXGBE_TN_LASI_STATUS_TEMP_ALARM
#define IXGBE_TN_LASI_STATUS_TEMP_ALARM
Definition: ixgbe_phy.h:153
IXGBE_I2C_T_SU_STO
#define IXGBE_I2C_T_SU_STO
Definition: ixgbe_phy.h:147
IXGBE_SFF_1GBE_COMP_CODES
#define IXGBE_SFF_1GBE_COMP_CODES
Definition: ixgbe_phy.h:50
IXGBE_SFF_QSFP_DA_PASSIVE_CABLE
#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE
Definition: ixgbe_phy.h:82
IXGBE_SFF_1GBASET_CAPABLE
#define IXGBE_SFF_1GBASET_CAPABLE
Definition: ixgbe_phy.h:74
IXGBE_I2C_T_SU_STA
#define IXGBE_I2C_T_SU_STA
Definition: ixgbe_phy.h:142
IXGBE_SFF_10GBASESR_CAPABLE
#define IXGBE_SFF_10GBASESR_CAPABLE
Definition: ixgbe_phy.h:75
IXGBE_SFF_1GBASESX_CAPABLE
#define IXGBE_SFF_1GBASESX_CAPABLE
Definition: ixgbe_phy.h:72
IXGBE_PHYSICAL_LAYER_10GBASE_SR
#define IXGBE_PHYSICAL_LAYER_10GBASE_SR
Definition: ixgbe_type.h:3466
IXGBE_I2C_DATA_OUT_BY_MAC
#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)
Definition: ixgbe_type.h:263
ixgbe_mac_X550
@ ixgbe_mac_X550
Definition: ixgbe_type.h:3679
ixgbe_mac_82598EB
@ ixgbe_mac_82598EB
Definition: ixgbe_type.h:3674
ixgbe_mac_X550EM_a
@ ixgbe_mac_X550EM_a
Definition: ixgbe_type.h:3681
ixgbe_mac_X550EM_x
@ ixgbe_mac_X550EM_x
Definition: ixgbe_type.h:3680
IXGBE_MSCA_NP_ADDR_SHIFT
#define IXGBE_MSCA_NP_ADDR_SHIFT
Definition: ixgbe_type.h:1532
IXGBE_MDIO_PHY_1000BASET_ABILITY
#define IXGBE_MDIO_PHY_1000BASET_ABILITY
Definition: ixgbe_type.h:1612
IXGBE_MSRWD
#define IXGBE_MSRWD
Definition: ixgbe_type.h:1376
IXGBE_ERR_SWFW_SYNC
#define IXGBE_ERR_SWFW_SYNC
Definition: ixgbe_type.h:4250
IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
Definition: ixgbe_type.h:3463
IXGBE_MMNGC_MNG_VETO
#define IXGBE_MMNGC_MNG_VETO
Definition: ixgbe_type.h:2239
IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG
#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG
Definition: ixgbe_type.h:1676
IXGBE_MDIO_PHY_EXT_ABILITY
#define IXGBE_MDIO_PHY_EXT_ABILITY
Definition: ixgbe_type.h:1610
IXGBE_M88E1500_E_PHY_ID
#define IXGBE_M88E1500_E_PHY_ID
Definition: ixgbe_type.h:1708
IXGBE_MDIO_PHY_SPEED_10G
#define IXGBE_MDIO_PHY_SPEED_10G
Definition: ixgbe_type.h:1607
IXGBE_MII_AUTONEG_REG
#define IXGBE_MII_AUTONEG_REG
Definition: ixgbe_type.h:1690
IXGBE_MSCA_PHY_ADDR_SHIFT
#define IXGBE_MSCA_PHY_ADDR_SHIFT
Definition: ixgbe_type.h:1536
IXGBE_MII_2_5GBASE_T_ADVERTISE
#define IXGBE_MII_2_5GBASE_T_ADVERTISE
Definition: ixgbe_type.h:1683
IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP
#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP
Definition: ixgbe_type.h:2465
IXGBE_MII_10GBASE_T_ADVERTISE
#define IXGBE_MII_10GBASE_T_ADVERTISE
Definition: ixgbe_type.h:1680
IXGBE_MSCA_WRITE
#define IXGBE_MSCA_WRITE
Definition: ixgbe_type.h:1540
TN1010_PHY_ID
#define TN1010_PHY_ID
Definition: ixgbe_type.h:1696
IXGBE_DEV_ID_82599_T3_LOM
#define IXGBE_DEV_ID_82599_T3_LOM
Definition: ixgbe_type.h:125
IXGBE_DATA_MASK_NL
#define IXGBE_DATA_MASK_NL
Definition: ixgbe_type.h:1715
IXGBE_MSCA
#define IXGBE_MSCA
Definition: ixgbe_type.h:1375
IXGBE_PHYSICAL_LAYER_UNKNOWN
#define IXGBE_PHYSICAL_LAYER_UNKNOWN
Definition: ixgbe_type.h:3459
IXGBE_ERR_I2C
#define IXGBE_ERR_I2C
Definition: ixgbe_type.h:4252
IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS
Definition: ixgbe_type.h:1584
IXGBE_PHYSICAL_LAYER_1000BASE_SX
#define IXGBE_PHYSICAL_LAYER_1000BASE_SX
Definition: ixgbe_type.h:3474
IXGBE_GSSR_PHY1_SM
#define IXGBE_GSSR_PHY1_SM
Definition: ixgbe_type.h:2305
IXGBE_LINK_SPEED_5GB_FULL
#define IXGBE_LINK_SPEED_5GB_FULL
Definition: ixgbe_type.h:3449
ixgbe_link_speed
u32 ixgbe_link_speed
Definition: ixgbe_type.h:3443
IXGBE_TWINAX_DEV
#define IXGBE_TWINAX_DEV
Definition: ixgbe_type.h:1579
IXGBE_MDIO_PHY_ID_HIGH
#define IXGBE_MDIO_PHY_ID_HIGH
Definition: ixgbe_type.h:1604
QT2022_PHY_ID
#define QT2022_PHY_ID
Definition: ixgbe_type.h:1704
IXGBE_SUCCESS
#define IXGBE_SUCCESS
Definition: ixgbe_type.h:4234
IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
Definition: ixgbe_type.h:1621
IXGBE_MDIO_PHY_SPEED_1G
#define IXGBE_MDIO_PHY_SPEED_1G
Definition: ixgbe_type.h:1608
IXGBE_ERR_PHY_ADDR_INVALID
#define IXGBE_ERR_PHY_ADDR_INVALID
Definition: ixgbe_type.h:4251
ixgbe_phy_type
ixgbe_phy_type
Definition: ixgbe_type.h:3688
ixgbe_phy_aq
@ ixgbe_phy_aq
Definition: ixgbe_type.h:3692
ixgbe_phy_qt
@ ixgbe_phy_qt
Definition: ixgbe_type.h:3699
ixgbe_phy_qsfp_intel
@ ixgbe_phy_qsfp_intel
Definition: ixgbe_type.h:3712
ixgbe_phy_unknown
@ ixgbe_phy_unknown
Definition: ixgbe_type.h:3689
ixgbe_phy_x550em_ext_t
@ ixgbe_phy_x550em_ext_t
Definition: ixgbe_type.h:3696
ixgbe_phy_nl
@ ixgbe_phy_nl
Definition: ixgbe_type.h:3701
ixgbe_phy_sfp_ftl_active
@ ixgbe_phy_sfp_ftl_active
Definition: ixgbe_type.h:3707
ixgbe_phy_sfp_avago
@ ixgbe_phy_sfp_avago
Definition: ixgbe_type.h:3705
ixgbe_phy_qsfp_active_unknown
@ ixgbe_phy_qsfp_active_unknown
Definition: ixgbe_type.h:3711
ixgbe_phy_sfp_ftl
@ ixgbe_phy_sfp_ftl
Definition: ixgbe_type.h:3706
ixgbe_phy_sfp_active_unknown
@ ixgbe_phy_sfp_active_unknown
Definition: ixgbe_type.h:3704
ixgbe_phy_sfp_passive_tyco
@ ixgbe_phy_sfp_passive_tyco
Definition: ixgbe_type.h:3702
ixgbe_phy_sfp_passive_unknown
@ ixgbe_phy_sfp_passive_unknown
Definition: ixgbe_type.h:3703
ixgbe_phy_sfp_unsupported
@ ixgbe_phy_sfp_unsupported
Definition: ixgbe_type.h:3714
ixgbe_phy_qsfp_passive_unknown
@ ixgbe_phy_qsfp_passive_unknown
Definition: ixgbe_type.h:3710
ixgbe_phy_cu_unknown
@ ixgbe_phy_cu_unknown
Definition: ixgbe_type.h:3698
ixgbe_phy_qsfp_unknown
@ ixgbe_phy_qsfp_unknown
Definition: ixgbe_type.h:3713
ixgbe_phy_ext_1g_t
@ ixgbe_phy_ext_1g_t
Definition: ixgbe_type.h:3697
ixgbe_phy_sfp_unknown
@ ixgbe_phy_sfp_unknown
Definition: ixgbe_type.h:3708
ixgbe_phy_tn
@ ixgbe_phy_tn
Definition: ixgbe_type.h:3691
ixgbe_phy_sfp_intel
@ ixgbe_phy_sfp_intel
Definition: ixgbe_type.h:3709
ixgbe_phy_generic
@ ixgbe_phy_generic
Definition: ixgbe_type.h:3717
ixgbe_phy_none
@ ixgbe_phy_none
Definition: ixgbe_type.h:3690
IXGBE_M88E1543_E_PHY_ID
#define IXGBE_M88E1543_E_PHY_ID
Definition: ixgbe_type.h:1709
X557_PHY_ID
#define X557_PHY_ID
Definition: ixgbe_type.h:1701
ATH_PHY_ID
#define ATH_PHY_ID
Definition: ixgbe_type.h:1705
IXGBE_MDIO_PHY_10GBASET_ABILITY
#define IXGBE_MDIO_PHY_10GBASET_ABILITY
Definition: ixgbe_type.h:1611
IXGBE_MSCA_MDI_COMMAND
#define IXGBE_MSCA_MDI_COMMAND
Definition: ixgbe_type.h:1547
IXGBE_I2C_DATA_IN_BY_MAC
#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)
Definition: ixgbe_type.h:256
IXGBE_PHY_REVISION_MASK
#define IXGBE_PHY_REVISION_MASK
Definition: ixgbe_type.h:1692
IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS
Definition: ixgbe_type.h:1585
ixgbe_media_type_fiber_qsfp
@ ixgbe_media_type_fiber_qsfp
Definition: ixgbe_type.h:3757
ixgbe_media_type_fiber
@ ixgbe_media_type_fiber
Definition: ixgbe_type.h:3755
IXGBE_GSSR_PHY0_SM
#define IXGBE_GSSR_PHY0_SM
Definition: ixgbe_type.h:2304
IXGBE_MMNGC
#define IXGBE_MMNGC
Definition: ixgbe_type.h:1397
IXGBE_MDIO_PHY_XS_RESET
#define IXGBE_MDIO_PHY_XS_RESET
Definition: ixgbe_type.h:1603
IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT
Definition: ixgbe_type.h:285
ixgbe_sfp_type
ixgbe_sfp_type
Definition: ixgbe_type.h:3733
ixgbe_sfp_type_1g_sx_core1
@ ixgbe_sfp_type_1g_sx_core1
Definition: ixgbe_type.h:3746
ixgbe_sfp_type_da_cu_core1
@ ixgbe_sfp_type_da_cu_core1
Definition: ixgbe_type.h:3738
ixgbe_sfp_type_da_cu
@ ixgbe_sfp_type_da_cu
Definition: ixgbe_type.h:3734
ixgbe_sfp_type_1g_cu_core1
@ ixgbe_sfp_type_1g_cu_core1
Definition: ixgbe_type.h:3744
ixgbe_sfp_type_lr
@ ixgbe_sfp_type_lr
Definition: ixgbe_type.h:3736
ixgbe_sfp_type_da_act_lmt_core1
@ ixgbe_sfp_type_da_act_lmt_core1
Definition: ixgbe_type.h:3742
ixgbe_sfp_type_unknown
@ ixgbe_sfp_type_unknown
Definition: ixgbe_type.h:3750
ixgbe_sfp_type_1g_lx_core0
@ ixgbe_sfp_type_1g_lx_core0
Definition: ixgbe_type.h:3747
ixgbe_sfp_type_sr
@ ixgbe_sfp_type_sr
Definition: ixgbe_type.h:3735
ixgbe_sfp_type_srlr_core1
@ ixgbe_sfp_type_srlr_core1
Definition: ixgbe_type.h:3740
ixgbe_sfp_type_da_act_lmt_core0
@ ixgbe_sfp_type_da_act_lmt_core0
Definition: ixgbe_type.h:3741
ixgbe_sfp_type_1g_cu_core0
@ ixgbe_sfp_type_1g_cu_core0
Definition: ixgbe_type.h:3743
ixgbe_sfp_type_da_cu_core0
@ ixgbe_sfp_type_da_cu_core0
Definition: ixgbe_type.h:3737
ixgbe_sfp_type_1g_lx_core1
@ ixgbe_sfp_type_1g_lx_core1
Definition: ixgbe_type.h:3748
ixgbe_sfp_type_not_present
@ ixgbe_sfp_type_not_present
Definition: ixgbe_type.h:3749
ixgbe_sfp_type_1g_sx_core0
@ ixgbe_sfp_type_1g_sx_core0
Definition: ixgbe_type.h:3745
ixgbe_sfp_type_srlr_core0
@ ixgbe_sfp_type_srlr_core0
Definition: ixgbe_type.h:3739
IXGBE_MDIO_PHY_SPEED_100M
#define IXGBE_MDIO_PHY_SPEED_100M
Definition: ixgbe_type.h:1609
IXGBE_DELAY_NL
#define IXGBE_DELAY_NL
Definition: ixgbe_type.h:1717
IXGBE_MDIO_PHY_XS_DEV_TYPE
#define IXGBE_MDIO_PHY_XS_DEV_TYPE
Definition: ixgbe_type.h:1576
IXGBE_MDIO_PMA_PMD_DEV_TYPE
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE
Definition: ixgbe_type.h:1574
IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX
#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX
Definition: ixgbe_type.h:1681
TNX_FW_REV
#define TNX_FW_REV
Definition: ixgbe_type.h:1697
IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL
Definition: ixgbe_type.h:1583
IXGBE_LINK_SPEED_10_FULL
#define IXGBE_LINK_SPEED_10_FULL
Definition: ixgbe_type.h:3445
IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
Definition: ixgbe_type.h:1578
IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD
Definition: ixgbe_type.h:4482
IXGBE_ERR_OVERTEMP
#define IXGBE_ERR_OVERTEMP
Definition: ixgbe_type.h:4260
IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT
#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT
Definition: ixgbe_type.h:4255
IXGBE_I2CCTL_BY_MAC
#define IXGBE_I2CCTL_BY_MAC(_hw)
Definition: ixgbe_type.h:176
IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG
#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG
Definition: ixgbe_type.h:1677
IXGBE_CONTROL_MASK_NL
#define IXGBE_CONTROL_MASK_NL
Definition: ixgbe_type.h:1714
IXGBE_MDIO_AUTO_NEG_CONTROL
#define IXGBE_MDIO_AUTO_NEG_CONTROL
Definition: ixgbe_type.h:1590
IXGBE_CONTROL_SOL_NL
#define IXGBE_CONTROL_SOL_NL
Definition: ixgbe_type.h:1721
IXGBE_MSCA_READ
#define IXGBE_MSCA_READ
Definition: ixgbe_type.h:1541
IXGBE_CONTROL_EOL_NL
#define IXGBE_CONTROL_EOL_NL
Definition: ixgbe_type.h:1720
AQ_FW_REV
#define AQ_FW_REV
Definition: ixgbe_type.h:1703
IXGBE_MDIO_TX_VENDOR_ALARMS_3
#define IXGBE_MDIO_TX_VENDOR_ALARMS_3
Definition: ixgbe_type.h:1620
IXGBE_MII_5GBASE_T_ADVERTISE
#define IXGBE_MII_5GBASE_T_ADVERTISE
Definition: ixgbe_type.h:1684
IXGBE_MDIO_PHY_XS_CONTROL
#define IXGBE_MDIO_PHY_XS_CONTROL
Definition: ixgbe_type.h:1602
IXGBE_I2C_DATA_OE_N_EN_BY_MAC
#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw)
Definition: ixgbe_type.h:270
IXGBE_MII_100BASE_T_ADVERTISE
#define IXGBE_MII_100BASE_T_ADVERTISE
Definition: ixgbe_type.h:1685
IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
Definition: ixgbe_type.h:3473
X550_PHY_ID3
#define X550_PHY_ID3
Definition: ixgbe_type.h:1700
IXGBE_MDIO_PHY_ID_LOW
#define IXGBE_MDIO_PHY_ID_LOW
Definition: ixgbe_type.h:1605
IXGBE_LINK_SPEED_100_FULL
#define IXGBE_LINK_SPEED_100_FULL
Definition: ixgbe_type.h:3446
IXGBE_ERR_PHY
#define IXGBE_ERR_PHY
Definition: ixgbe_type.h:4237
IXGBE_CONTROL_NL
#define IXGBE_CONTROL_NL
Definition: ixgbe_type.h:1719
IXGBE_MDIO_PHY_SET_LOW_POWER_MODE
#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE
Definition: ixgbe_type.h:1614
IXGBE_MDIO_AUTO_NEG_DEV_TYPE
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE
Definition: ixgbe_type.h:1577
IXGBE_LINK_SPEED_1GB_FULL
#define IXGBE_LINK_SPEED_1GB_FULL
Definition: ixgbe_type.h:3447
IXGBE_MDIO_PHY_SPEED_ABILITY
#define IXGBE_MDIO_PHY_SPEED_ABILITY
Definition: ixgbe_type.h:1606
IXGBE_MII_AUTONEG_ADVERTISE_REG
#define IXGBE_MII_AUTONEG_ADVERTISE_REG
Definition: ixgbe_type.h:1679
IXGBE_MDIO_COMMAND_TIMEOUT
#define IXGBE_MDIO_COMMAND_TIMEOUT
Definition: ixgbe_type.h:1581
IXGBE_I2C_BB_EN_BY_MAC
#define IXGBE_I2C_BB_EN_BY_MAC(_hw)
Definition: ixgbe_type.h:277
IXGBE_MSCA_DEV_TYPE_SHIFT
#define IXGBE_MSCA_DEV_TYPE_SHIFT
Definition: ixgbe_type.h:1534
IXGBE_I2C_CLK_OE_N_EN_BY_MAC
#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw)
Definition: ixgbe_type.h:284
IXGBE_MSRWD_READ_DATA_SHIFT
#define IXGBE_MSRWD_READ_DATA_SHIFT
Definition: ixgbe_type.h:1554
IXGBE_LINK_SPEED_2_5GB_FULL
#define IXGBE_LINK_SPEED_2_5GB_FULL
Definition: ixgbe_type.h:3448
IXGBE_MII_100BASE_T_ADVERTISE_HALF
#define IXGBE_MII_100BASE_T_ADVERTISE_HALF
Definition: ixgbe_type.h:1686
IXGBE_PHY_INIT_OFFSET_NL
#define IXGBE_PHY_INIT_OFFSET_NL
Definition: ixgbe_type.h:1712
IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT
Definition: ixgbe_type.h:4481
IXGBE_LINK_SPEED_10GB_FULL
#define IXGBE_LINK_SPEED_10GB_FULL
Definition: ixgbe_type.h:3450
IXGBE_I2C_CLK_IN_BY_MAC
#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)
Definition: ixgbe_type.h:242
X557_PHY_ID2
#define X557_PHY_ID2
Definition: ixgbe_type.h:1702
X550_PHY_ID2
#define X550_PHY_ID2
Definition: ixgbe_type.h:1699
IXGBE_PHY_INIT_END_NL
#define IXGBE_PHY_INIT_END_NL
Definition: ixgbe_type.h:1713
X540_PHY_ID
#define X540_PHY_ID
Definition: ixgbe_type.h:1698
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS
Definition: ixgbe_type.h:1586
IXGBE_MII_1GBASE_T_ADVERTISE
#define IXGBE_MII_1GBASE_T_ADVERTISE
Definition: ixgbe_type.h:1682
IXGBE_MAX_PHY_ADDR
#define IXGBE_MAX_PHY_ADDR
Definition: ixgbe_type.h:1693
IXGBE_PHYSICAL_LAYER_10GBASE_LR
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR
Definition: ixgbe_type.h:3464
IXGBE_MII_RESTART
#define IXGBE_MII_RESTART
Definition: ixgbe_type.h:1687
IXGBE_MSCA_ADDR_CYCLE
#define IXGBE_MSCA_ADDR_CYCLE
Definition: ixgbe_type.h:1539
IXGBE_I2C_CLK_OUT_BY_MAC
#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)
Definition: ixgbe_type.h:249
IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
Definition: ixgbe_type.h:96
IXGBE_ERR_SFP_NOT_PRESENT
#define IXGBE_ERR_SFP_NOT_PRESENT
Definition: ixgbe_type.h:4254
IXGBE_DATA_NL
#define IXGBE_DATA_NL
Definition: ixgbe_type.h:1718
IXGBE_PHYSICAL_LAYER_1000BASE_T
#define IXGBE_PHYSICAL_LAYER_1000BASE_T
Definition: ixgbe_type.h:3461
IXGBE_CONTROL_SHIFT_NL
#define IXGBE_CONTROL_SHIFT_NL
Definition: ixgbe_type.h:1716
IXGBE_ERR_SFP_NOT_SUPPORTED
#define IXGBE_ERR_SFP_NOT_SUPPORTED
Definition: ixgbe_type.h:4253
IXGBE_MII_AUTONEG_XNP_TX_REG
#define IXGBE_MII_AUTONEG_XNP_TX_REG
Definition: ixgbe_type.h:1678
IXGBE_ERR_RESET_FAILED
#define IXGBE_ERR_RESET_FAILED
Definition: ixgbe_type.h:4249
phy_speed
ixgbe_link_speed phy_speed
Definition: ixgbe_x550.c:443
ixgbe_bus_info::lan_id
u8 lan_id
Definition: ixgbe_type.h:3832
ixgbe_eeprom_info::ops
struct ixgbe_eeprom_operations ops
Definition: ixgbe_type.h:4103
ixgbe_eeprom_operations::read
s32(* read)(struct ixgbe_hw *, u16, u16 *)
Definition: ixgbe_type.h:3939
ixgbe_hw
Definition: ixgbe_type.h:4204
ixgbe_hw::mac
struct ixgbe_mac_info mac
Definition: ixgbe_type.h:4207
ixgbe_hw::bus
struct ixgbe_bus_info bus
Definition: ixgbe_type.h:4213
ixgbe_hw::device_id
u16 device_id
Definition: ixgbe_type.h:4216
ixgbe_hw::allow_unsupported_sfp
bool allow_unsupported_sfp
Definition: ixgbe_type.h:4224
ixgbe_hw::eeprom
struct ixgbe_eeprom_info eeprom
Definition: ixgbe_type.h:4212
ixgbe_hw::phy
struct ixgbe_phy_info phy
Definition: ixgbe_type.h:4210
ixgbe_mac_info::type
enum ixgbe_mac_type type
Definition: ixgbe_type.h:4115
ixgbe_mac_info::ops
struct ixgbe_mac_operations ops
Definition: ixgbe_type.h:4114
ixgbe_mac_operations::acquire_swfw_sync
s32(* acquire_swfw_sync)(struct ixgbe_hw *, u32)
Definition: ixgbe_type.h:3971
ixgbe_mac_operations::release_swfw_sync
void(* release_swfw_sync)(struct ixgbe_hw *, u32)
Definition: ixgbe_type.h:3972
ixgbe_mac_operations::set_lan_id
void(* set_lan_id)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3964
ixgbe_mac_operations::get_media_type
enum ixgbe_media_type(* get_media_type)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3954
ixgbe_phy_info
Definition: ixgbe_type.h:4150
ixgbe_phy_info::reset_if_overtemp
bool reset_if_overtemp
Definition: ixgbe_type.h:4168
ixgbe_phy_info::sfp_setup_needed
bool sfp_setup_needed
Definition: ixgbe_type.h:4156
ixgbe_phy_info::nw_mng_if_sel
u32 nw_mng_if_sel
Definition: ixgbe_type.h:4170
ixgbe_phy_info::type
enum ixgbe_phy_type type
Definition: ixgbe_type.h:4152
ixgbe_phy_info::speeds_supported
ixgbe_link_speed speeds_supported
Definition: ixgbe_type.h:4162
ixgbe_phy_info::autoneg_advertised
ixgbe_autoneg_advertised autoneg_advertised
Definition: ixgbe_type.h:4161
ixgbe_phy_info::multispeed_fiber
bool multispeed_fiber
Definition: ixgbe_type.h:4167
ixgbe_phy_info::revision
u32 revision
Definition: ixgbe_type.h:4157
ixgbe_phy_info::ops
struct ixgbe_phy_operations ops
Definition: ixgbe_type.h:4151
ixgbe_phy_info::addr
u32 addr
Definition: ixgbe_type.h:4153
ixgbe_phy_info::phy_semaphore_mask
u32 phy_semaphore_mask
Definition: ixgbe_type.h:4159
ixgbe_phy_info::sfp_type
enum ixgbe_sfp_type sfp_type
Definition: ixgbe_type.h:4155
ixgbe_phy_info::id
u32 id
Definition: ixgbe_type.h:4154
ixgbe_phy_operations::read_i2c_byte_unlocked
s32(* read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, u8 *value)
Definition: ixgbe_type.h:4082
ixgbe_phy_operations::read_i2c_eeprom
s32(* read_i2c_eeprom)(struct ixgbe_hw *, u8, u8 *)
Definition: ixgbe_type.h:4075
ixgbe_phy_operations::setup_link_speed
s32(* setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool)
Definition: ixgbe_type.h:4069
ixgbe_phy_operations::write_i2c_byte
s32(* write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8)
Definition: ixgbe_type.h:4073
ixgbe_phy_operations::read_i2c_byte
s32(* read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *)
Definition: ixgbe_type.h:4072
ixgbe_phy_operations::check_overtemp
s32(* check_overtemp)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4078
ixgbe_phy_operations::write_i2c_byte_unlocked
s32(* write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, u8 value)
Definition: ixgbe_type.h:4084
ixgbe_phy_operations::get_firmware_version
s32(* get_firmware_version)(struct ixgbe_hw *, u16 *)
Definition: ixgbe_type.h:4071
ixgbe_phy_operations::reset
s32(* reset)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4062
ixgbe_phy_operations::identify
s32(* identify)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4059
ixgbe_phy_operations::check_link
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
Definition: ixgbe_type.h:4070
ixgbe_phy_operations::read_reg_mdi
s32(* read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *)
Definition: ixgbe_type.h:4065
ixgbe_phy_operations::i2c_bus_clear
void(* i2c_bus_clear)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4077
ixgbe_phy_operations::write_reg_mdi
s32(* write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16)
Definition: ixgbe_type.h:4066
ixgbe_phy_operations::read_reg
s32(* read_reg)(struct ixgbe_hw *, u32, u32, u16 *)
Definition: ixgbe_type.h:4063
ixgbe_phy_operations::setup_link
s32(* setup_link)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4067
ixgbe_phy_operations::read_i2c_sff8472
s32(* read_i2c_sff8472)(struct ixgbe_hw *, u8, u8 *)
Definition: ixgbe_type.h:4074
ixgbe_phy_operations::write_i2c_eeprom
s32(* write_i2c_eeprom)(struct ixgbe_hw *, u8, u8)
Definition: ixgbe_type.h:4076
ixgbe_phy_operations::write_reg
s32(* write_reg)(struct ixgbe_hw *, u32, u32, u16)
Definition: ixgbe_type.h:4064
ixgbe_phy_operations::identify_sfp
s32(* identify_sfp)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4060