FreeBSD kernel IXGBE device code
ixgbe_common.c
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1/******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
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18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33******************************************************************************/
34/*$FreeBSD$*/
35
36#include "ixgbe_common.h"
37#include "ixgbe_phy.h"
38#include "ixgbe_dcb.h"
39#include "ixgbe_dcb_82599.h"
40#include "ixgbe_api.h"
41
42static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
43static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
44static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
45static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
46static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
47static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 u16 count);
49static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
50static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
52static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53
54static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
55static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 u16 *san_mac_offset);
57static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
60 u16 words, u16 *data);
61static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
62 u16 offset);
63
70s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71{
72 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
73 struct ixgbe_mac_info *mac = &hw->mac;
74 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
75
76 DEBUGFUNC("ixgbe_init_ops_generic");
77
78 /* EEPROM */
79 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
80 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
81 if (eec & IXGBE_EEC_PRES) {
82 eeprom->ops.read = ixgbe_read_eerd_generic;
83 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
84 } else {
85 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
86 eeprom->ops.read_buffer =
87 ixgbe_read_eeprom_buffer_bit_bang_generic;
88 }
89 eeprom->ops.write = ixgbe_write_eeprom_generic;
90 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
91 eeprom->ops.validate_checksum =
92 ixgbe_validate_eeprom_checksum_generic;
93 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
94 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95
96 /* MAC */
97 mac->ops.init_hw = ixgbe_init_hw_generic;
98 mac->ops.reset_hw = NULL;
99 mac->ops.start_hw = ixgbe_start_hw_generic;
100 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
101 mac->ops.get_media_type = NULL;
102 mac->ops.get_supported_physical_layer = NULL;
103 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
104 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
105 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
106 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
107 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
108 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
109 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
110 mac->ops.prot_autoc_read = prot_autoc_read_generic;
111 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112
113 /* LEDs */
114 mac->ops.led_on = ixgbe_led_on_generic;
115 mac->ops.led_off = ixgbe_led_off_generic;
116 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
117 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
118 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
119
120 /* RAR, Multicast, VLAN */
121 mac->ops.set_rar = ixgbe_set_rar_generic;
122 mac->ops.clear_rar = ixgbe_clear_rar_generic;
123 mac->ops.insert_mac_addr = NULL;
124 mac->ops.set_vmdq = NULL;
125 mac->ops.clear_vmdq = NULL;
126 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
127 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
128 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
129 mac->ops.enable_mc = ixgbe_enable_mc_generic;
130 mac->ops.disable_mc = ixgbe_disable_mc_generic;
131 mac->ops.clear_vfta = NULL;
132 mac->ops.set_vfta = NULL;
133 mac->ops.set_vlvf = NULL;
134 mac->ops.init_uta_tables = NULL;
135 mac->ops.enable_rx = ixgbe_enable_rx_generic;
136 mac->ops.disable_rx = ixgbe_disable_rx_generic;
137
138 /* Flow Control */
139 mac->ops.fc_enable = ixgbe_fc_enable_generic;
140 mac->ops.setup_fc = ixgbe_setup_fc_generic;
141 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
142
143 /* Link */
144 mac->ops.get_link_capabilities = NULL;
145 mac->ops.setup_link = NULL;
146 mac->ops.check_link = NULL;
147 mac->ops.dmac_config = NULL;
148 mac->ops.dmac_update_tcs = NULL;
149 mac->ops.dmac_config_tcs = NULL;
150
151 return IXGBE_SUCCESS;
152}
153
163bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
164{
165 bool supported = false;
166 ixgbe_link_speed speed;
167 bool link_up;
168
169 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
170
171 switch (hw->phy.media_type) {
172 case ixgbe_media_type_fiber_fixed:
173 case ixgbe_media_type_fiber_qsfp:
174 case ixgbe_media_type_fiber:
175 /* flow control autoneg black list */
176 switch (hw->device_id) {
177 case IXGBE_DEV_ID_X550EM_A_SFP:
178 case IXGBE_DEV_ID_X550EM_A_SFP_N:
179 case IXGBE_DEV_ID_X550EM_A_QSFP:
180 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
181 supported = false;
182 break;
183 default:
184 hw->mac.ops.check_link(hw, &speed, &link_up, false);
185 /* if link is down, assume supported */
186 if (link_up)
187 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
188 true : false;
189 else
190 supported = true;
191 }
192
193 break;
194 case ixgbe_media_type_backplane:
195 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
196 supported = false;
197 else
198 supported = true;
199 break;
200 case ixgbe_media_type_copper:
201 /* only some copper devices support flow control autoneg */
202 switch (hw->device_id) {
203 case IXGBE_DEV_ID_82599_T3_LOM:
204 case IXGBE_DEV_ID_X540T:
205 case IXGBE_DEV_ID_X540T1:
206 case IXGBE_DEV_ID_X540_BYPASS:
207 case IXGBE_DEV_ID_X550T:
208 case IXGBE_DEV_ID_X550T1:
209 case IXGBE_DEV_ID_X550EM_X_10G_T:
210 case IXGBE_DEV_ID_X550EM_A_10G_T:
211 case IXGBE_DEV_ID_X550EM_A_1G_T:
212 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
213 supported = true;
214 break;
215 default:
216 supported = false;
217 }
218 default:
219 break;
220 }
221
222 if (!supported)
223 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
224 "Device %x does not support flow control autoneg",
225 hw->device_id);
226
227 return supported;
228}
229
236s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
237{
238 s32 ret_val = IXGBE_SUCCESS;
239 u32 reg = 0, reg_bp = 0;
240 u16 reg_cu = 0;
241 bool locked = false;
242
243 DEBUGFUNC("ixgbe_setup_fc_generic");
244
245 /* Validate the requested mode */
246 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
247 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
248 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
249 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
250 goto out;
251 }
252
253 /*
254 * 10gig parts do not have a word in the EEPROM to determine the
255 * default flow control setting, so we explicitly set it to full.
256 */
257 if (hw->fc.requested_mode == ixgbe_fc_default)
258 hw->fc.requested_mode = ixgbe_fc_full;
259
260 /*
261 * Set up the 1G and 10G flow control advertisement registers so the
262 * HW will be able to do fc autoneg once the cable is plugged in. If
263 * we link at 10G, the 1G advertisement is harmless and vice versa.
264 */
265 switch (hw->phy.media_type) {
266 case ixgbe_media_type_backplane:
267 /* some MAC's need RMW protection on AUTOC */
268 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
269 if (ret_val != IXGBE_SUCCESS)
270 goto out;
271
272 /* only backplane uses autoc */
273 /* FALLTHROUGH */
274 case ixgbe_media_type_fiber_fixed:
275 case ixgbe_media_type_fiber_qsfp:
276 case ixgbe_media_type_fiber:
277 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
278
279 break;
280 case ixgbe_media_type_copper:
281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
282 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
283 break;
284 default:
285 break;
286 }
287
288 /*
289 * The possible values of fc.requested_mode are:
290 * 0: Flow control is completely disabled
291 * 1: Rx flow control is enabled (we can receive pause frames,
292 * but not send pause frames).
293 * 2: Tx flow control is enabled (we can send pause frames but
294 * we do not support receiving pause frames).
295 * 3: Both Rx and Tx flow control (symmetric) are enabled.
296 * other: Invalid.
297 */
298 switch (hw->fc.requested_mode) {
299 case ixgbe_fc_none:
300 /* Flow control completely disabled by software override. */
301 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
302 if (hw->phy.media_type == ixgbe_media_type_backplane)
303 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
304 IXGBE_AUTOC_ASM_PAUSE);
305 else if (hw->phy.media_type == ixgbe_media_type_copper)
306 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
307 break;
308 case ixgbe_fc_tx_pause:
309 /*
310 * Tx Flow control is enabled, and Rx Flow control is
311 * disabled by software override.
312 */
313 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
314 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
315 if (hw->phy.media_type == ixgbe_media_type_backplane) {
316 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
317 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
318 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
319 reg_cu |= IXGBE_TAF_ASM_PAUSE;
320 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
321 }
322 break;
323 case ixgbe_fc_rx_pause:
324 /*
325 * Rx Flow control is enabled and Tx Flow control is
326 * disabled by software override. Since there really
327 * isn't a way to advertise that we are capable of RX
328 * Pause ONLY, we will advertise that we support both
329 * symmetric and asymmetric Rx PAUSE, as such we fall
330 * through to the fc_full statement. Later, we will
331 * disable the adapter's ability to send PAUSE frames.
332 */
333 case ixgbe_fc_full:
334 /* Flow control (both Rx and Tx) is enabled by SW override. */
335 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
336 if (hw->phy.media_type == ixgbe_media_type_backplane)
337 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
338 IXGBE_AUTOC_ASM_PAUSE;
339 else if (hw->phy.media_type == ixgbe_media_type_copper)
340 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
341 break;
342 default:
343 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
344 "Flow control param set incorrectly\n");
345 ret_val = IXGBE_ERR_CONFIG;
346 goto out;
347 break;
348 }
349
350 if (hw->mac.type < ixgbe_mac_X540) {
351 /*
352 * Enable auto-negotiation between the MAC & PHY;
353 * the MAC will advertise clause 37 flow control.
354 */
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
356 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
357
358 /* Disable AN timeout */
359 if (hw->fc.strict_ieee)
360 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
361
362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
363 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
364 }
365
366 /*
367 * AUTOC restart handles negotiation of 1G and 10G on backplane
368 * and copper. There is no need to set the PCS1GCTL register.
369 *
370 */
371 if (hw->phy.media_type == ixgbe_media_type_backplane) {
372 reg_bp |= IXGBE_AUTOC_AN_RESTART;
373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
374 if (ret_val)
375 goto out;
376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
377 (ixgbe_device_supports_autoneg_fc(hw))) {
378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
379 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
380 }
381
382 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
383out:
384 return ret_val;
385}
386
396s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
397{
398 s32 ret_val;
399 u32 ctrl_ext;
400 u16 device_caps;
401
402 DEBUGFUNC("ixgbe_start_hw_generic");
403
404 /* Set the media type */
405 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
406
407 /* PHY ops initialization must be done in reset_hw() */
408
409 /* Clear the VLAN filter table */
410 hw->mac.ops.clear_vfta(hw);
411
412 /* Clear statistics registers */
413 hw->mac.ops.clear_hw_cntrs(hw);
414
415 /* Set No Snoop Disable */
416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
417 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
419 IXGBE_WRITE_FLUSH(hw);
420
421 /* Setup flow control */
422 ret_val = ixgbe_setup_fc(hw);
423 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
424 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
425 return ret_val;
426 }
427
428 /* Cache bit indicating need for crosstalk fix */
429 switch (hw->mac.type) {
430 case ixgbe_mac_82599EB:
431 case ixgbe_mac_X550EM_x:
432 case ixgbe_mac_X550EM_a:
433 hw->mac.ops.get_device_caps(hw, &device_caps);
434 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
435 hw->need_crosstalk_fix = false;
436 else
437 hw->need_crosstalk_fix = true;
438 break;
439 default:
440 hw->need_crosstalk_fix = false;
441 break;
442 }
443
444 /* Clear adapter stopped flag */
445 hw->adapter_stopped = false;
446
447 return IXGBE_SUCCESS;
448}
449
460void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
461{
462 u32 i;
463 u32 regval;
464
465 /* Clear the rate limiters */
466 for (i = 0; i < hw->mac.max_tx_queues; i++) {
467 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
468 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
469 }
470 IXGBE_WRITE_FLUSH(hw);
471
472 /* Disable relaxed ordering */
473 for (i = 0; i < hw->mac.max_tx_queues; i++) {
474 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
475 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
477 }
478
479 for (i = 0; i < hw->mac.max_rx_queues; i++) {
480 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
481 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
482 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
483 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
484 }
485}
486
497s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
498{
499 s32 status;
500
501 DEBUGFUNC("ixgbe_init_hw_generic");
502
503 /* Reset the hardware */
504 status = hw->mac.ops.reset_hw(hw);
505
506 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
507 /* Start the HW */
508 status = hw->mac.ops.start_hw(hw);
509 }
510
511 /* Initialize the LED link active for LED blink support */
512 if (hw->mac.ops.init_led_link_act)
513 hw->mac.ops.init_led_link_act(hw);
514
515 if (status != IXGBE_SUCCESS)
516 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
517
518 return status;
519}
520
528s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
529{
530 u16 i = 0;
531
532 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
533
534 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
535 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
536 IXGBE_READ_REG(hw, IXGBE_ERRBC);
537 IXGBE_READ_REG(hw, IXGBE_MSPDC);
538 for (i = 0; i < 8; i++)
539 IXGBE_READ_REG(hw, IXGBE_MPC(i));
540
541 IXGBE_READ_REG(hw, IXGBE_MLFC);
542 IXGBE_READ_REG(hw, IXGBE_MRFC);
543 IXGBE_READ_REG(hw, IXGBE_RLEC);
544 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
545 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
546 if (hw->mac.type >= ixgbe_mac_82599EB) {
547 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
548 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
549 } else {
550 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
551 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
552 }
553
554 for (i = 0; i < 8; i++) {
555 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
556 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
557 if (hw->mac.type >= ixgbe_mac_82599EB) {
558 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
559 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
560 } else {
561 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
562 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
563 }
564 }
565 if (hw->mac.type >= ixgbe_mac_82599EB)
566 for (i = 0; i < 8; i++)
567 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
568 IXGBE_READ_REG(hw, IXGBE_PRC64);
569 IXGBE_READ_REG(hw, IXGBE_PRC127);
570 IXGBE_READ_REG(hw, IXGBE_PRC255);
571 IXGBE_READ_REG(hw, IXGBE_PRC511);
572 IXGBE_READ_REG(hw, IXGBE_PRC1023);
573 IXGBE_READ_REG(hw, IXGBE_PRC1522);
574 IXGBE_READ_REG(hw, IXGBE_GPRC);
575 IXGBE_READ_REG(hw, IXGBE_BPRC);
576 IXGBE_READ_REG(hw, IXGBE_MPRC);
577 IXGBE_READ_REG(hw, IXGBE_GPTC);
578 IXGBE_READ_REG(hw, IXGBE_GORCL);
579 IXGBE_READ_REG(hw, IXGBE_GORCH);
580 IXGBE_READ_REG(hw, IXGBE_GOTCL);
581 IXGBE_READ_REG(hw, IXGBE_GOTCH);
582 if (hw->mac.type == ixgbe_mac_82598EB)
583 for (i = 0; i < 8; i++)
584 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
585 IXGBE_READ_REG(hw, IXGBE_RUC);
586 IXGBE_READ_REG(hw, IXGBE_RFC);
587 IXGBE_READ_REG(hw, IXGBE_ROC);
588 IXGBE_READ_REG(hw, IXGBE_RJC);
589 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
590 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
591 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
592 IXGBE_READ_REG(hw, IXGBE_TORL);
593 IXGBE_READ_REG(hw, IXGBE_TORH);
594 IXGBE_READ_REG(hw, IXGBE_TPR);
595 IXGBE_READ_REG(hw, IXGBE_TPT);
596 IXGBE_READ_REG(hw, IXGBE_PTC64);
597 IXGBE_READ_REG(hw, IXGBE_PTC127);
598 IXGBE_READ_REG(hw, IXGBE_PTC255);
599 IXGBE_READ_REG(hw, IXGBE_PTC511);
600 IXGBE_READ_REG(hw, IXGBE_PTC1023);
601 IXGBE_READ_REG(hw, IXGBE_PTC1522);
602 IXGBE_READ_REG(hw, IXGBE_MPTC);
603 IXGBE_READ_REG(hw, IXGBE_BPTC);
604 for (i = 0; i < 16; i++) {
605 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
606 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
607 if (hw->mac.type >= ixgbe_mac_82599EB) {
608 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
609 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
610 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
611 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
612 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
613 } else {
614 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
615 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
616 }
617 }
618
619 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
620 if (hw->phy.id == 0)
621 ixgbe_identify_phy(hw);
622 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
623 IXGBE_MDIO_PCS_DEV_TYPE, &i);
624 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
625 IXGBE_MDIO_PCS_DEV_TYPE, &i);
626 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
627 IXGBE_MDIO_PCS_DEV_TYPE, &i);
628 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
629 IXGBE_MDIO_PCS_DEV_TYPE, &i);
630 }
631
632 return IXGBE_SUCCESS;
633}
634
643s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
644 u32 pba_num_size)
645{
646 s32 ret_val;
647 u16 data;
648 u16 pba_ptr;
649 u16 offset;
650 u16 length;
651
652 DEBUGFUNC("ixgbe_read_pba_string_generic");
653
654 if (pba_num == NULL) {
655 DEBUGOUT("PBA string buffer was null\n");
656 return IXGBE_ERR_INVALID_ARGUMENT;
657 }
658
659 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
660 if (ret_val) {
661 DEBUGOUT("NVM Read Error\n");
662 return ret_val;
663 }
664
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
666 if (ret_val) {
667 DEBUGOUT("NVM Read Error\n");
668 return ret_val;
669 }
670
671 /*
672 * if data is not ptr guard the PBA must be in legacy format which
673 * means pba_ptr is actually our second data word for the PBA number
674 * and we can decode it into an ascii string
675 */
676 if (data != IXGBE_PBANUM_PTR_GUARD) {
677 DEBUGOUT("NVM PBA number is not stored as string\n");
678
679 /* we will need 11 characters to store the PBA */
680 if (pba_num_size < 11) {
681 DEBUGOUT("PBA string buffer too small\n");
682 return IXGBE_ERR_NO_SPACE;
683 }
684
685 /* extract hex string from data and pba_ptr */
686 pba_num[0] = (data >> 12) & 0xF;
687 pba_num[1] = (data >> 8) & 0xF;
688 pba_num[2] = (data >> 4) & 0xF;
689 pba_num[3] = data & 0xF;
690 pba_num[4] = (pba_ptr >> 12) & 0xF;
691 pba_num[5] = (pba_ptr >> 8) & 0xF;
692 pba_num[6] = '-';
693 pba_num[7] = 0;
694 pba_num[8] = (pba_ptr >> 4) & 0xF;
695 pba_num[9] = pba_ptr & 0xF;
696
697 /* put a null character on the end of our string */
698 pba_num[10] = '\0';
699
700 /* switch all the data but the '-' to hex char */
701 for (offset = 0; offset < 10; offset++) {
702 if (pba_num[offset] < 0xA)
703 pba_num[offset] += '0';
704 else if (pba_num[offset] < 0x10)
705 pba_num[offset] += 'A' - 0xA;
706 }
707
708 return IXGBE_SUCCESS;
709 }
710
711 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
712 if (ret_val) {
713 DEBUGOUT("NVM Read Error\n");
714 return ret_val;
715 }
716
717 if (length == 0xFFFF || length == 0) {
718 DEBUGOUT("NVM PBA number section invalid length\n");
719 return IXGBE_ERR_PBA_SECTION;
720 }
721
722 /* check if pba_num buffer is big enough */
723 if (pba_num_size < (((u32)length * 2) - 1)) {
724 DEBUGOUT("PBA string buffer too small\n");
725 return IXGBE_ERR_NO_SPACE;
726 }
727
728 /* trim pba length from start of string */
729 pba_ptr++;
730 length--;
731
732 for (offset = 0; offset < length; offset++) {
733 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
734 if (ret_val) {
735 DEBUGOUT("NVM Read Error\n");
736 return ret_val;
737 }
738 pba_num[offset * 2] = (u8)(data >> 8);
739 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
740 }
741 pba_num[offset * 2] = '\0';
742
743 return IXGBE_SUCCESS;
744}
745
753s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
754{
755 s32 ret_val;
756 u16 data;
757
758 DEBUGFUNC("ixgbe_read_pba_num_generic");
759
760 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
761 if (ret_val) {
762 DEBUGOUT("NVM Read Error\n");
763 return ret_val;
764 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
765 DEBUGOUT("NVM Not supported\n");
766 return IXGBE_NOT_IMPLEMENTED;
767 }
768 *pba_num = (u32)(data << 16);
769
770 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
771 if (ret_val) {
772 DEBUGOUT("NVM Read Error\n");
773 return ret_val;
774 }
775 *pba_num |= (u32)data;
776
777 return IXGBE_SUCCESS;
778}
779
792s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
793 u32 eeprom_buf_size, u16 max_pba_block_size,
794 struct ixgbe_pba *pba)
795{
796 s32 ret_val;
797 u16 pba_block_size;
798
799 if (pba == NULL)
800 return IXGBE_ERR_PARAM;
801
802 if (eeprom_buf == NULL) {
803 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
804 &pba->word[0]);
805 if (ret_val)
806 return ret_val;
807 } else {
808 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
809 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
810 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
811 } else {
812 return IXGBE_ERR_PARAM;
813 }
814 }
815
816 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
817 if (pba->pba_block == NULL)
818 return IXGBE_ERR_PARAM;
819
820 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
821 eeprom_buf_size,
822 &pba_block_size);
823 if (ret_val)
824 return ret_val;
825
826 if (pba_block_size > max_pba_block_size)
827 return IXGBE_ERR_PARAM;
828
829 if (eeprom_buf == NULL) {
830 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
831 pba_block_size,
832 pba->pba_block);
833 if (ret_val)
834 return ret_val;
835 } else {
836 if (eeprom_buf_size > (u32)(pba->word[1] +
837 pba_block_size)) {
838 memcpy(pba->pba_block,
839 &eeprom_buf[pba->word[1]],
840 pba_block_size * sizeof(u16));
841 } else {
842 return IXGBE_ERR_PARAM;
843 }
844 }
845 }
846
847 return IXGBE_SUCCESS;
848}
849
861s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
862 u32 eeprom_buf_size, struct ixgbe_pba *pba)
863{
864 s32 ret_val;
865
866 if (pba == NULL)
867 return IXGBE_ERR_PARAM;
868
869 if (eeprom_buf == NULL) {
870 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
871 &pba->word[0]);
872 if (ret_val)
873 return ret_val;
874 } else {
875 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
876 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
877 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
878 } else {
879 return IXGBE_ERR_PARAM;
880 }
881 }
882
883 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
884 if (pba->pba_block == NULL)
885 return IXGBE_ERR_PARAM;
886
887 if (eeprom_buf == NULL) {
888 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
889 pba->pba_block[0],
890 pba->pba_block);
891 if (ret_val)
892 return ret_val;
893 } else {
894 if (eeprom_buf_size > (u32)(pba->word[1] +
895 pba->pba_block[0])) {
896 memcpy(&eeprom_buf[pba->word[1]],
897 pba->pba_block,
898 pba->pba_block[0] * sizeof(u16));
899 } else {
900 return IXGBE_ERR_PARAM;
901 }
902 }
903 }
904
905 return IXGBE_SUCCESS;
906}
907
920s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
921 u32 eeprom_buf_size, u16 *pba_block_size)
922{
923 s32 ret_val;
924 u16 pba_word[2];
925 u16 length;
926
927 DEBUGFUNC("ixgbe_get_pba_block_size");
928
929 if (eeprom_buf == NULL) {
930 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
931 &pba_word[0]);
932 if (ret_val)
933 return ret_val;
934 } else {
935 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
936 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
937 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
938 } else {
939 return IXGBE_ERR_PARAM;
940 }
941 }
942
943 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
944 if (eeprom_buf == NULL) {
945 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
946 &length);
947 if (ret_val)
948 return ret_val;
949 } else {
950 if (eeprom_buf_size > pba_word[1])
951 length = eeprom_buf[pba_word[1] + 0];
952 else
953 return IXGBE_ERR_PARAM;
954 }
955
956 if (length == 0xFFFF || length == 0)
957 return IXGBE_ERR_PBA_SECTION;
958 } else {
959 /* PBA number in legacy format, there is no PBA Block. */
960 length = 0;
961 }
962
963 if (pba_block_size != NULL)
964 *pba_block_size = length;
965
966 return IXGBE_SUCCESS;
967}
968
978s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
979{
980 u32 rar_high;
981 u32 rar_low;
982 u16 i;
983
984 DEBUGFUNC("ixgbe_get_mac_addr_generic");
985
986 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
987 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
988
989 for (i = 0; i < 4; i++)
990 mac_addr[i] = (u8)(rar_low >> (i*8));
991
992 for (i = 0; i < 2; i++)
993 mac_addr[i+4] = (u8)(rar_high >> (i*8));
994
995 return IXGBE_SUCCESS;
996}
997
1005void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1006{
1007 struct ixgbe_mac_info *mac = &hw->mac;
1008
1009 if (hw->bus.type == ixgbe_bus_type_unknown)
1010 hw->bus.type = ixgbe_bus_type_pci_express;
1011
1012 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
1013 case IXGBE_PCI_LINK_WIDTH_1:
1014 hw->bus.width = ixgbe_bus_width_pcie_x1;
1015 break;
1016 case IXGBE_PCI_LINK_WIDTH_2:
1017 hw->bus.width = ixgbe_bus_width_pcie_x2;
1018 break;
1019 case IXGBE_PCI_LINK_WIDTH_4:
1020 hw->bus.width = ixgbe_bus_width_pcie_x4;
1021 break;
1022 case IXGBE_PCI_LINK_WIDTH_8:
1023 hw->bus.width = ixgbe_bus_width_pcie_x8;
1024 break;
1025 default:
1026 hw->bus.width = ixgbe_bus_width_unknown;
1027 break;
1028 }
1029
1030 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1031 case IXGBE_PCI_LINK_SPEED_2500:
1032 hw->bus.speed = ixgbe_bus_speed_2500;
1033 break;
1034 case IXGBE_PCI_LINK_SPEED_5000:
1035 hw->bus.speed = ixgbe_bus_speed_5000;
1036 break;
1037 case IXGBE_PCI_LINK_SPEED_8000:
1038 hw->bus.speed = ixgbe_bus_speed_8000;
1039 break;
1040 default:
1041 hw->bus.speed = ixgbe_bus_speed_unknown;
1042 break;
1043 }
1044
1045 mac->ops.set_lan_id(hw);
1046}
1047
1055s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1056{
1057 u16 link_status;
1058
1059 DEBUGFUNC("ixgbe_get_bus_info_generic");
1060
1061 /* Get the negotiated link width and speed from PCI config space */
1062 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1063
1064 ixgbe_set_pci_config_data_generic(hw, link_status);
1065
1066 return IXGBE_SUCCESS;
1067}
1068
1077void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1078{
1079 struct ixgbe_bus_info *bus = &hw->bus;
1080 u32 reg;
1081 u16 ee_ctrl_4;
1082
1083 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1084
1085 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1086 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1087 bus->lan_id = (u8)bus->func;
1088
1089 /* check for a port swap */
1090 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1091 if (reg & IXGBE_FACTPS_LFS)
1092 bus->func ^= 0x1;
1093
1094 /* Get MAC instance from EEPROM for configuring CS4227 */
1095 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1096 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1097 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1098 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1099 }
1100}
1101
1111s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1112{
1113 u32 reg_val;
1114 u16 i;
1115
1116 DEBUGFUNC("ixgbe_stop_adapter_generic");
1117
1118 /*
1119 * Set the adapter_stopped flag so other driver functions stop touching
1120 * the hardware
1121 */
1122 hw->adapter_stopped = true;
1123
1124 /* Disable the receive unit */
1125 ixgbe_disable_rx(hw);
1126
1127 /* Clear interrupt mask to stop interrupts from being generated */
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1129
1130 /* Clear any pending interrupts, flush previous writes */
1131 IXGBE_READ_REG(hw, IXGBE_EICR);
1132
1133 /* Disable the transmit unit. Each queue must be disabled. */
1134 for (i = 0; i < hw->mac.max_tx_queues; i++)
1135 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1136
1137 /* Disable the receive unit by stopping each queue */
1138 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1139 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1140 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1141 reg_val |= IXGBE_RXDCTL_SWFLSH;
1142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1143 }
1144
1145 /* flush all queues disables */
1146 IXGBE_WRITE_FLUSH(hw);
1147 msec_delay(2);
1148
1149 /*
1150 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1151 * access and verify no pending requests
1152 */
1153 return ixgbe_disable_pcie_master(hw);
1154}
1155
1163s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1164{
1165 struct ixgbe_mac_info *mac = &hw->mac;
1166 u32 led_reg, led_mode;
1167 u8 i;
1168
1169 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1170
1171 /* Get LED link active from the LEDCTL register */
1172 for (i = 0; i < 4; i++) {
1173 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1174
1175 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1176 IXGBE_LED_LINK_ACTIVE) {
1177 mac->led_link_act = i;
1178 return IXGBE_SUCCESS;
1179 }
1180 }
1181
1182 /*
1183 * If LEDCTL register does not have the LED link active set, then use
1184 * known MAC defaults.
1185 */
1186 switch (hw->mac.type) {
1187 case ixgbe_mac_X550EM_a:
1188 case ixgbe_mac_X550EM_x:
1189 mac->led_link_act = 1;
1190 break;
1191 default:
1192 mac->led_link_act = 2;
1193 }
1194 return IXGBE_SUCCESS;
1195}
1196
1202s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1203{
1204 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1205
1206 DEBUGFUNC("ixgbe_led_on_generic");
1207
1208 if (index > 3)
1209 return IXGBE_ERR_PARAM;
1210
1211 /* To turn on the LED, set mode to ON. */
1212 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1213 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1214 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1215 IXGBE_WRITE_FLUSH(hw);
1216
1217 return IXGBE_SUCCESS;
1218}
1219
1225s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1226{
1227 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1228
1229 DEBUGFUNC("ixgbe_led_off_generic");
1230
1231 if (index > 3)
1232 return IXGBE_ERR_PARAM;
1233
1234 /* To turn off the LED, set mode to OFF. */
1235 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1236 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1237 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1238 IXGBE_WRITE_FLUSH(hw);
1239
1240 return IXGBE_SUCCESS;
1241}
1242
1250s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1251{
1252 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1253 u32 eec;
1254 u16 eeprom_size;
1255
1256 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1257
1258 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1259 eeprom->type = ixgbe_eeprom_none;
1260 /* Set default semaphore delay to 10ms which is a well
1261 * tested value */
1262 eeprom->semaphore_delay = 10;
1263 /* Clear EEPROM page size, it will be initialized as needed */
1264 eeprom->word_page_size = 0;
1265
1266 /*
1267 * Check for EEPROM present first.
1268 * If not present leave as none
1269 */
1270 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1271 if (eec & IXGBE_EEC_PRES) {
1272 eeprom->type = ixgbe_eeprom_spi;
1273
1274 /*
1275 * SPI EEPROM is assumed here. This code would need to
1276 * change if a future EEPROM is not SPI.
1277 */
1278 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1279 IXGBE_EEC_SIZE_SHIFT);
1280 eeprom->word_size = 1 << (eeprom_size +
1281 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1282 }
1283
1284 if (eec & IXGBE_EEC_ADDR_SIZE)
1285 eeprom->address_bits = 16;
1286 else
1287 eeprom->address_bits = 8;
1288 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1289 "%d\n", eeprom->type, eeprom->word_size,
1290 eeprom->address_bits);
1291 }
1292
1293 return IXGBE_SUCCESS;
1294}
1295
1305s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1306 u16 words, u16 *data)
1307{
1308 s32 status = IXGBE_SUCCESS;
1309 u16 i, count;
1310
1311 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1312
1313 hw->eeprom.ops.init_params(hw);
1314
1315 if (words == 0) {
1316 status = IXGBE_ERR_INVALID_ARGUMENT;
1317 goto out;
1318 }
1319
1320 if (offset + words > hw->eeprom.word_size) {
1321 status = IXGBE_ERR_EEPROM;
1322 goto out;
1323 }
1324
1325 /*
1326 * The EEPROM page size cannot be queried from the chip. We do lazy
1327 * initialization. It is worth to do that when we write large buffer.
1328 */
1329 if ((hw->eeprom.word_page_size == 0) &&
1330 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1331 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1332
1333 /*
1334 * We cannot hold synchronization semaphores for too long
1335 * to avoid other entity starvation. However it is more efficient
1336 * to read in bursts than synchronizing access for each word.
1337 */
1338 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1339 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1340 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1341 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1342 count, &data[i]);
1343
1344 if (status != IXGBE_SUCCESS)
1345 break;
1346 }
1347
1348out:
1349 return status;
1350}
1351
1362static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1363 u16 words, u16 *data)
1364{
1365 s32 status;
1366 u16 word;
1367 u16 page_size;
1368 u16 i;
1369 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1370
1371 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1372
1373 /* Prepare the EEPROM for writing */
1374 status = ixgbe_acquire_eeprom(hw);
1375
1376 if (status == IXGBE_SUCCESS) {
1377 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1378 ixgbe_release_eeprom(hw);
1379 status = IXGBE_ERR_EEPROM;
1380 }
1381 }
1382
1383 if (status == IXGBE_SUCCESS) {
1384 for (i = 0; i < words; i++) {
1385 ixgbe_standby_eeprom(hw);
1386
1387 /* Send the WRITE ENABLE command (8 bit opcode ) */
1388 ixgbe_shift_out_eeprom_bits(hw,
1389 IXGBE_EEPROM_WREN_OPCODE_SPI,
1390 IXGBE_EEPROM_OPCODE_BITS);
1391
1392 ixgbe_standby_eeprom(hw);
1393
1394 /*
1395 * Some SPI eeproms use the 8th address bit embedded
1396 * in the opcode
1397 */
1398 if ((hw->eeprom.address_bits == 8) &&
1399 ((offset + i) >= 128))
1400 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1401
1402 /* Send the Write command (8-bit opcode + addr) */
1403 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1404 IXGBE_EEPROM_OPCODE_BITS);
1405 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1406 hw->eeprom.address_bits);
1407
1408 page_size = hw->eeprom.word_page_size;
1409
1410 /* Send the data in burst via SPI*/
1411 do {
1412 word = data[i];
1413 word = (word >> 8) | (word << 8);
1414 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1415
1416 if (page_size == 0)
1417 break;
1418
1419 /* do not wrap around page */
1420 if (((offset + i) & (page_size - 1)) ==
1421 (page_size - 1))
1422 break;
1423 } while (++i < words);
1424
1425 ixgbe_standby_eeprom(hw);
1426 msec_delay(10);
1427 }
1428 /* Done with writing - release the EEPROM */
1429 ixgbe_release_eeprom(hw);
1430 }
1431
1432 return status;
1433}
1434
1444s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1445{
1446 s32 status;
1447
1448 DEBUGFUNC("ixgbe_write_eeprom_generic");
1449
1450 hw->eeprom.ops.init_params(hw);
1451
1452 if (offset >= hw->eeprom.word_size) {
1453 status = IXGBE_ERR_EEPROM;
1454 goto out;
1455 }
1456
1457 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1458
1459out:
1460 return status;
1461}
1462
1472s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1473 u16 words, u16 *data)
1474{
1475 s32 status = IXGBE_SUCCESS;
1476 u16 i, count;
1477
1478 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1479
1480 hw->eeprom.ops.init_params(hw);
1481
1482 if (words == 0) {
1483 status = IXGBE_ERR_INVALID_ARGUMENT;
1484 goto out;
1485 }
1486
1487 if (offset + words > hw->eeprom.word_size) {
1488 status = IXGBE_ERR_EEPROM;
1489 goto out;
1490 }
1491
1492 /*
1493 * We cannot hold synchronization semaphores for too long
1494 * to avoid other entity starvation. However it is more efficient
1495 * to read in bursts than synchronizing access for each word.
1496 */
1497 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1498 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1499 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1500
1501 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1502 count, &data[i]);
1503
1504 if (status != IXGBE_SUCCESS)
1505 break;
1506 }
1507
1508out:
1509 return status;
1510}
1511
1521static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1522 u16 words, u16 *data)
1523{
1524 s32 status;
1525 u16 word_in;
1526 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1527 u16 i;
1528
1529 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1530
1531 /* Prepare the EEPROM for reading */
1532 status = ixgbe_acquire_eeprom(hw);
1533
1534 if (status == IXGBE_SUCCESS) {
1535 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1536 ixgbe_release_eeprom(hw);
1537 status = IXGBE_ERR_EEPROM;
1538 }
1539 }
1540
1541 if (status == IXGBE_SUCCESS) {
1542 for (i = 0; i < words; i++) {
1543 ixgbe_standby_eeprom(hw);
1544 /*
1545 * Some SPI eeproms use the 8th address bit embedded
1546 * in the opcode
1547 */
1548 if ((hw->eeprom.address_bits == 8) &&
1549 ((offset + i) >= 128))
1550 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1551
1552 /* Send the READ command (opcode + addr) */
1553 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1554 IXGBE_EEPROM_OPCODE_BITS);
1555 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1556 hw->eeprom.address_bits);
1557
1558 /* Read the data. */
1559 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1560 data[i] = (word_in >> 8) | (word_in << 8);
1561 }
1562
1563 /* End this read operation */
1564 ixgbe_release_eeprom(hw);
1565 }
1566
1567 return status;
1568}
1569
1578s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1579 u16 *data)
1580{
1581 s32 status;
1582
1583 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1584
1585 hw->eeprom.ops.init_params(hw);
1586
1587 if (offset >= hw->eeprom.word_size) {
1588 status = IXGBE_ERR_EEPROM;
1589 goto out;
1590 }
1591
1592 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1593
1594out:
1595 return status;
1596}
1597
1607s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1608 u16 words, u16 *data)
1609{
1610 u32 eerd;
1611 s32 status = IXGBE_SUCCESS;
1612 u32 i;
1613
1614 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1615
1616 hw->eeprom.ops.init_params(hw);
1617
1618 if (words == 0) {
1619 status = IXGBE_ERR_INVALID_ARGUMENT;
1620 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1621 goto out;
1622 }
1623
1624 if (offset >= hw->eeprom.word_size) {
1625 status = IXGBE_ERR_EEPROM;
1626 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1627 goto out;
1628 }
1629
1630 for (i = 0; i < words; i++) {
1631 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1632 IXGBE_EEPROM_RW_REG_START;
1633
1634 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1635 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1636
1637 if (status == IXGBE_SUCCESS) {
1638 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1639 IXGBE_EEPROM_RW_REG_DATA);
1640 } else {
1641 DEBUGOUT("Eeprom read timed out\n");
1642 goto out;
1643 }
1644 }
1645out:
1646 return status;
1647}
1648
1658static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1659 u16 offset)
1660{
1661 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1662 s32 status = IXGBE_SUCCESS;
1663 u16 i;
1664
1665 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1666
1667 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1668 data[i] = i;
1669
1670 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1672 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1673 hw->eeprom.word_page_size = 0;
1674 if (status != IXGBE_SUCCESS)
1675 goto out;
1676
1677 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1678 if (status != IXGBE_SUCCESS)
1679 goto out;
1680
1681 /*
1682 * When writing in burst more than the actual page size
1683 * EEPROM address wraps around current page.
1684 */
1685 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1686
1687 DEBUGOUT1("Detected EEPROM page size = %d words.",
1688 hw->eeprom.word_page_size);
1689out:
1690 return status;
1691}
1692
1701s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1702{
1703 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1704}
1705
1715s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1716 u16 words, u16 *data)
1717{
1718 u32 eewr;
1719 s32 status = IXGBE_SUCCESS;
1720 u16 i;
1721
1722 DEBUGFUNC("ixgbe_write_eewr_generic");
1723
1724 hw->eeprom.ops.init_params(hw);
1725
1726 if (words == 0) {
1727 status = IXGBE_ERR_INVALID_ARGUMENT;
1728 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1729 goto out;
1730 }
1731
1732 if (offset >= hw->eeprom.word_size) {
1733 status = IXGBE_ERR_EEPROM;
1734 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1735 goto out;
1736 }
1737
1738 for (i = 0; i < words; i++) {
1739 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1740 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1741 IXGBE_EEPROM_RW_REG_START;
1742
1743 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1744 if (status != IXGBE_SUCCESS) {
1745 DEBUGOUT("Eeprom write EEWR timed out\n");
1746 goto out;
1747 }
1748
1749 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1750
1751 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1752 if (status != IXGBE_SUCCESS) {
1753 DEBUGOUT("Eeprom write EEWR timed out\n");
1754 goto out;
1755 }
1756 }
1757
1758out:
1759 return status;
1760}
1761
1770s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1771{
1772 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1773}
1774
1783s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1784{
1785 u32 i;
1786 u32 reg;
1787 s32 status = IXGBE_ERR_EEPROM;
1788
1789 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1790
1791 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1792 if (ee_reg == IXGBE_NVM_POLL_READ)
1793 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1794 else
1795 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1796
1797 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1798 status = IXGBE_SUCCESS;
1799 break;
1800 }
1801 usec_delay(5);
1802 }
1803
1804 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1805 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1806 "EEPROM read/write done polling timed out");
1807
1808 return status;
1809}
1810
1818static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1819{
1820 s32 status = IXGBE_SUCCESS;
1821 u32 eec;
1822 u32 i;
1823
1824 DEBUGFUNC("ixgbe_acquire_eeprom");
1825
1826 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1827 != IXGBE_SUCCESS)
1828 status = IXGBE_ERR_SWFW_SYNC;
1829
1830 if (status == IXGBE_SUCCESS) {
1831 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1832
1833 /* Request EEPROM Access */
1834 eec |= IXGBE_EEC_REQ;
1835 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1836
1837 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1838 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1839 if (eec & IXGBE_EEC_GNT)
1840 break;
1841 usec_delay(5);
1842 }
1843
1844 /* Release if grant not acquired */
1845 if (!(eec & IXGBE_EEC_GNT)) {
1846 eec &= ~IXGBE_EEC_REQ;
1847 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1848 DEBUGOUT("Could not acquire EEPROM grant\n");
1849
1850 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1851 status = IXGBE_ERR_EEPROM;
1852 }
1853
1854 /* Setup EEPROM for Read/Write */
1855 if (status == IXGBE_SUCCESS) {
1856 /* Clear CS and SK */
1857 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1858 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1859 IXGBE_WRITE_FLUSH(hw);
1860 usec_delay(1);
1861 }
1862 }
1863 return status;
1864}
1865
1872static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1873{
1874 s32 status = IXGBE_ERR_EEPROM;
1875 u32 timeout = 2000;
1876 u32 i;
1877 u32 swsm;
1878
1879 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1880
1881
1882 /* Get SMBI software semaphore between device drivers first */
1883 for (i = 0; i < timeout; i++) {
1884 /*
1885 * If the SMBI bit is 0 when we read it, then the bit will be
1886 * set and we have the semaphore
1887 */
1888 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1889 if (!(swsm & IXGBE_SWSM_SMBI)) {
1890 status = IXGBE_SUCCESS;
1891 break;
1892 }
1893 usec_delay(50);
1894 }
1895
1896 if (i == timeout) {
1897 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1898 "not granted.\n");
1899 /*
1900 * this release is particularly important because our attempts
1901 * above to get the semaphore may have succeeded, and if there
1902 * was a timeout, we should unconditionally clear the semaphore
1903 * bits to free the driver to make progress
1904 */
1905 ixgbe_release_eeprom_semaphore(hw);
1906
1907 usec_delay(50);
1908 /*
1909 * one last try
1910 * If the SMBI bit is 0 when we read it, then the bit will be
1911 * set and we have the semaphore
1912 */
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1914 if (!(swsm & IXGBE_SWSM_SMBI))
1915 status = IXGBE_SUCCESS;
1916 }
1917
1918 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1919 if (status == IXGBE_SUCCESS) {
1920 for (i = 0; i < timeout; i++) {
1921 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1922
1923 /* Set the SW EEPROM semaphore bit to request access */
1924 swsm |= IXGBE_SWSM_SWESMBI;
1925 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1926
1927 /*
1928 * If we set the bit successfully then we got the
1929 * semaphore.
1930 */
1931 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1932 if (swsm & IXGBE_SWSM_SWESMBI)
1933 break;
1934
1935 usec_delay(50);
1936 }
1937
1938 /*
1939 * Release semaphores and return error if SW EEPROM semaphore
1940 * was not granted because we don't have access to the EEPROM
1941 */
1942 if (i >= timeout) {
1943 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1944 "SWESMBI Software EEPROM semaphore not granted.\n");
1945 ixgbe_release_eeprom_semaphore(hw);
1946 status = IXGBE_ERR_EEPROM;
1947 }
1948 } else {
1949 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1950 "Software semaphore SMBI between device drivers "
1951 "not granted.\n");
1952 }
1953
1954 return status;
1955}
1956
1963static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1964{
1965 u32 swsm;
1966
1967 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1968
1969 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1970
1971 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1972 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1973 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1974 IXGBE_WRITE_FLUSH(hw);
1975}
1976
1981static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1982{
1983 s32 status = IXGBE_SUCCESS;
1984 u16 i;
1985 u8 spi_stat_reg;
1986
1987 DEBUGFUNC("ixgbe_ready_eeprom");
1988
1989 /*
1990 * Read "Status Register" repeatedly until the LSB is cleared. The
1991 * EEPROM will signal that the command has been completed by clearing
1992 * bit 0 of the internal status register. If it's not cleared within
1993 * 5 milliseconds, then error out.
1994 */
1995 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1996 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1997 IXGBE_EEPROM_OPCODE_BITS);
1998 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1999 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
2000 break;
2001
2002 usec_delay(5);
2003 ixgbe_standby_eeprom(hw);
2004 }
2005
2006 /*
2007 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2008 * devices (and only 0-5mSec on 5V devices)
2009 */
2010 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
2011 DEBUGOUT("SPI EEPROM Status error\n");
2012 status = IXGBE_ERR_EEPROM;
2013 }
2014
2015 return status;
2016}
2017
2022static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2023{
2024 u32 eec;
2025
2026 DEBUGFUNC("ixgbe_standby_eeprom");
2027
2028 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2029
2030 /* Toggle CS to flush commands */
2031 eec |= IXGBE_EEC_CS;
2032 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2033 IXGBE_WRITE_FLUSH(hw);
2034 usec_delay(1);
2035 eec &= ~IXGBE_EEC_CS;
2036 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2037 IXGBE_WRITE_FLUSH(hw);
2038 usec_delay(1);
2039}
2040
2047static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2048 u16 count)
2049{
2050 u32 eec;
2051 u32 mask;
2052 u32 i;
2053
2054 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2055
2056 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2057
2058 /*
2059 * Mask is used to shift "count" bits of "data" out to the EEPROM
2060 * one bit at a time. Determine the starting bit based on count
2061 */
2062 mask = 0x01 << (count - 1);
2063
2064 for (i = 0; i < count; i++) {
2065 /*
2066 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2067 * "1", and then raising and then lowering the clock (the SK
2068 * bit controls the clock input to the EEPROM). A "0" is
2069 * shifted out to the EEPROM by setting "DI" to "0" and then
2070 * raising and then lowering the clock.
2071 */
2072 if (data & mask)
2073 eec |= IXGBE_EEC_DI;
2074 else
2075 eec &= ~IXGBE_EEC_DI;
2076
2077 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2078 IXGBE_WRITE_FLUSH(hw);
2079
2080 usec_delay(1);
2081
2082 ixgbe_raise_eeprom_clk(hw, &eec);
2083 ixgbe_lower_eeprom_clk(hw, &eec);
2084
2085 /*
2086 * Shift mask to signify next bit of data to shift in to the
2087 * EEPROM
2088 */
2089 mask = mask >> 1;
2090 }
2091
2092 /* We leave the "DI" bit set to "0" when we leave this routine. */
2093 eec &= ~IXGBE_EEC_DI;
2094 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2095 IXGBE_WRITE_FLUSH(hw);
2096}
2097
2103static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2104{
2105 u32 eec;
2106 u32 i;
2107 u16 data = 0;
2108
2109 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2110
2111 /*
2112 * In order to read a register from the EEPROM, we need to shift
2113 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2114 * the clock input to the EEPROM (setting the SK bit), and then reading
2115 * the value of the "DO" bit. During this "shifting in" process the
2116 * "DI" bit should always be clear.
2117 */
2118 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2119
2120 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2121
2122 for (i = 0; i < count; i++) {
2123 data = data << 1;
2124 ixgbe_raise_eeprom_clk(hw, &eec);
2125
2126 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2127
2128 eec &= ~(IXGBE_EEC_DI);
2129 if (eec & IXGBE_EEC_DO)
2130 data |= 1;
2131
2132 ixgbe_lower_eeprom_clk(hw, &eec);
2133 }
2134
2135 return data;
2136}
2137
2143static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2144{
2145 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2146
2147 /*
2148 * Raise the clock input to the EEPROM
2149 * (setting the SK bit), then delay
2150 */
2151 *eec = *eec | IXGBE_EEC_SK;
2152 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2153 IXGBE_WRITE_FLUSH(hw);
2154 usec_delay(1);
2155}
2156
2162static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2163{
2164 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2165
2166 /*
2167 * Lower the clock input to the EEPROM (clearing the SK bit), then
2168 * delay
2169 */
2170 *eec = *eec & ~IXGBE_EEC_SK;
2171 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2172 IXGBE_WRITE_FLUSH(hw);
2173 usec_delay(1);
2174}
2175
2180static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2181{
2182 u32 eec;
2183
2184 DEBUGFUNC("ixgbe_release_eeprom");
2185
2186 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2187
2188 eec |= IXGBE_EEC_CS; /* Pull CS high */
2189 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2190
2191 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2192 IXGBE_WRITE_FLUSH(hw);
2193
2194 usec_delay(1);
2195
2196 /* Stop requesting EEPROM access */
2197 eec &= ~IXGBE_EEC_REQ;
2198 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2199
2200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2201
2202 /* Delay before attempt to obtain semaphore again to allow FW access */
2203 msec_delay(hw->eeprom.semaphore_delay);
2204}
2205
2212s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2213{
2214 u16 i;
2215 u16 j;
2216 u16 checksum = 0;
2217 u16 length = 0;
2218 u16 pointer = 0;
2219 u16 word = 0;
2220
2221 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2222
2223 /* Include 0x0-0x3F in the checksum */
2224 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2225 if (hw->eeprom.ops.read(hw, i, &word)) {
2226 DEBUGOUT("EEPROM read failed\n");
2227 return IXGBE_ERR_EEPROM;
2228 }
2229 checksum += word;
2230 }
2231
2232 /* Include all data from pointers except for the fw pointer */
2233 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2234 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2235 DEBUGOUT("EEPROM read failed\n");
2236 return IXGBE_ERR_EEPROM;
2237 }
2238
2239 /* If the pointer seems invalid */
2240 if (pointer == 0xFFFF || pointer == 0)
2241 continue;
2242
2243 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2244 DEBUGOUT("EEPROM read failed\n");
2245 return IXGBE_ERR_EEPROM;
2246 }
2247
2248 if (length == 0xFFFF || length == 0)
2249 continue;
2250
2251 for (j = pointer + 1; j <= pointer + length; j++) {
2252 if (hw->eeprom.ops.read(hw, j, &word)) {
2253 DEBUGOUT("EEPROM read failed\n");
2254 return IXGBE_ERR_EEPROM;
2255 }
2256 checksum += word;
2257 }
2258 }
2259
2260 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2261
2262 return (s32)checksum;
2263}
2264
2273s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2274 u16 *checksum_val)
2275{
2276 s32 status;
2277 u16 checksum;
2278 u16 read_checksum = 0;
2279
2280 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2281
2282 /* Read the first word from the EEPROM. If this times out or fails, do
2283 * not continue or we could be in for a very long wait while every
2284 * EEPROM read fails
2285 */
2286 status = hw->eeprom.ops.read(hw, 0, &checksum);
2287 if (status) {
2288 DEBUGOUT("EEPROM read failed\n");
2289 return status;
2290 }
2291
2292 status = hw->eeprom.ops.calc_checksum(hw);
2293 if (status < 0)
2294 return status;
2295
2296 checksum = (u16)(status & 0xffff);
2297
2298 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2299 if (status) {
2300 DEBUGOUT("EEPROM read failed\n");
2301 return status;
2302 }
2303
2304 /* Verify read checksum from EEPROM is the same as
2305 * calculated checksum
2306 */
2307 if (read_checksum != checksum)
2308 status = IXGBE_ERR_EEPROM_CHECKSUM;
2309
2310 /* If the user cares, return the calculated checksum */
2311 if (checksum_val)
2312 *checksum_val = checksum;
2313
2314 return status;
2315}
2316
2321s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2322{
2323 s32 status;
2324 u16 checksum;
2325
2326 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2327
2328 /* Read the first word from the EEPROM. If this times out or fails, do
2329 * not continue or we could be in for a very long wait while every
2330 * EEPROM read fails
2331 */
2332 status = hw->eeprom.ops.read(hw, 0, &checksum);
2333 if (status) {
2334 DEBUGOUT("EEPROM read failed\n");
2335 return status;
2336 }
2337
2338 status = hw->eeprom.ops.calc_checksum(hw);
2339 if (status < 0)
2340 return status;
2341
2342 checksum = (u16)(status & 0xffff);
2343
2344 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2345
2346 return status;
2347}
2348
2355s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2356{
2357 s32 status = IXGBE_SUCCESS;
2358
2359 DEBUGFUNC("ixgbe_validate_mac_addr");
2360
2361 /* Make sure it is not a multicast address */
2362 if (IXGBE_IS_MULTICAST(mac_addr)) {
2363 status = IXGBE_ERR_INVALID_MAC_ADDR;
2364 /* Not a broadcast address */
2365 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2366 status = IXGBE_ERR_INVALID_MAC_ADDR;
2367 /* Reject the zero address */
2368 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2369 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2370 status = IXGBE_ERR_INVALID_MAC_ADDR;
2371 }
2372 return status;
2373}
2374
2385s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2386 u32 enable_addr)
2387{
2388 u32 rar_low, rar_high;
2389 u32 rar_entries = hw->mac.num_rar_entries;
2390
2391 DEBUGFUNC("ixgbe_set_rar_generic");
2392
2393 /* Make sure we are using a valid rar index range */
2394 if (index >= rar_entries) {
2395 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2396 "RAR index %d is out of range.\n", index);
2397 return IXGBE_ERR_INVALID_ARGUMENT;
2398 }
2399
2400 /* setup VMDq pool selection before this RAR gets enabled */
2401 hw->mac.ops.set_vmdq(hw, index, vmdq);
2402
2403 /*
2404 * HW expects these in little endian so we reverse the byte
2405 * order from network order (big endian) to little endian
2406 */
2407 rar_low = ((u32)addr[0] |
2408 ((u32)addr[1] << 8) |
2409 ((u32)addr[2] << 16) |
2410 ((u32)addr[3] << 24));
2411 /*
2412 * Some parts put the VMDq setting in the extra RAH bits,
2413 * so save everything except the lower 16 bits that hold part
2414 * of the address and the address valid bit.
2415 */
2416 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2417 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2418 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2419
2420 if (enable_addr != 0)
2421 rar_high |= IXGBE_RAH_AV;
2422
2423 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2424 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2425
2426 return IXGBE_SUCCESS;
2427}
2428
2436s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2437{
2438 u32 rar_high;
2439 u32 rar_entries = hw->mac.num_rar_entries;
2440
2441 DEBUGFUNC("ixgbe_clear_rar_generic");
2442
2443 /* Make sure we are using a valid rar index range */
2444 if (index >= rar_entries) {
2445 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2446 "RAR index %d is out of range.\n", index);
2447 return IXGBE_ERR_INVALID_ARGUMENT;
2448 }
2449
2450 /*
2451 * Some parts put the VMDq setting in the extra RAH bits,
2452 * so save everything except the lower 16 bits that hold part
2453 * of the address and the address valid bit.
2454 */
2455 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2456 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2457
2458 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2459 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2460
2461 /* clear VMDq pool/queue selection for this RAR */
2462 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2463
2464 return IXGBE_SUCCESS;
2465}
2466
2475s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2476{
2477 u32 i;
2478 u32 rar_entries = hw->mac.num_rar_entries;
2479
2480 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2481
2482 /*
2483 * If the current mac address is valid, assume it is a software override
2484 * to the permanent address.
2485 * Otherwise, use the permanent address from the eeprom.
2486 */
2487 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2488 IXGBE_ERR_INVALID_MAC_ADDR) {
2489 /* Get the MAC address from the RAR0 for later reference */
2490 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2491
2492 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2493 hw->mac.addr[0], hw->mac.addr[1],
2494 hw->mac.addr[2]);
2495 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2496 hw->mac.addr[4], hw->mac.addr[5]);
2497 } else {
2498 /* Setup the receive address. */
2499 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2500 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2501 hw->mac.addr[0], hw->mac.addr[1],
2502 hw->mac.addr[2]);
2503 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2504 hw->mac.addr[4], hw->mac.addr[5]);
2505
2506 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2507 }
2508
2509 /* clear VMDq pool/queue selection for RAR 0 */
2510 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2511
2512 hw->addr_ctrl.overflow_promisc = 0;
2513
2514 hw->addr_ctrl.rar_used_count = 1;
2515
2516 /* Zero out the other receive addresses. */
2517 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2518 for (i = 1; i < rar_entries; i++) {
2519 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2520 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2521 }
2522
2523 /* Clear the MTA */
2524 hw->addr_ctrl.mta_in_use = 0;
2525 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2526
2527 DEBUGOUT(" Clearing MTA\n");
2528 for (i = 0; i < hw->mac.mcft_size; i++)
2529 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2530
2531 ixgbe_init_uta_tables(hw);
2532
2533 return IXGBE_SUCCESS;
2534}
2535
2544void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2545{
2546 u32 rar_entries = hw->mac.num_rar_entries;
2547 u32 rar;
2548
2549 DEBUGFUNC("ixgbe_add_uc_addr");
2550
2551 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2552 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2553
2554 /*
2555 * Place this address in the RAR if there is room,
2556 * else put the controller into promiscuous mode
2557 */
2558 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2559 rar = hw->addr_ctrl.rar_used_count;
2560 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2561 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2562 hw->addr_ctrl.rar_used_count++;
2563 } else {
2564 hw->addr_ctrl.overflow_promisc++;
2565 }
2566
2567 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2568}
2569
2584s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2585 u32 addr_count, ixgbe_mc_addr_itr next)
2586{
2587 u8 *addr;
2588 u32 i;
2589 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2590 u32 uc_addr_in_use;
2591 u32 fctrl;
2592 u32 vmdq;
2593
2594 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2595
2596 /*
2597 * Clear accounting of old secondary address list,
2598 * don't count RAR[0]
2599 */
2600 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2601 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2602 hw->addr_ctrl.overflow_promisc = 0;
2603
2604 /* Zero out the other receive addresses */
2605 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2606 for (i = 0; i < uc_addr_in_use; i++) {
2607 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2608 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2609 }
2610
2611 /* Add the new addresses */
2612 for (i = 0; i < addr_count; i++) {
2613 DEBUGOUT(" Adding the secondary addresses:\n");
2614 addr = next(hw, &addr_list, &vmdq);
2615 ixgbe_add_uc_addr(hw, addr, vmdq);
2616 }
2617
2618 if (hw->addr_ctrl.overflow_promisc) {
2619 /* enable promisc if not already in overflow or set by user */
2620 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2621 DEBUGOUT(" Entering address overflow promisc mode\n");
2622 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2623 fctrl |= IXGBE_FCTRL_UPE;
2624 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2625 }
2626 } else {
2627 /* only disable if set by overflow, not by user */
2628 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2629 DEBUGOUT(" Leaving address overflow promisc mode\n");
2630 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2631 fctrl &= ~IXGBE_FCTRL_UPE;
2632 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2633 }
2634 }
2635
2636 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2637 return IXGBE_SUCCESS;
2638}
2639
2652static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2653{
2654 u32 vector = 0;
2655
2656 DEBUGFUNC("ixgbe_mta_vector");
2657
2658 switch (hw->mac.mc_filter_type) {
2659 case 0: /* use bits [47:36] of the address */
2660 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2661 break;
2662 case 1: /* use bits [46:35] of the address */
2663 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2664 break;
2665 case 2: /* use bits [45:34] of the address */
2666 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2667 break;
2668 case 3: /* use bits [43:32] of the address */
2669 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2670 break;
2671 default: /* Invalid mc_filter_type */
2672 DEBUGOUT("MC filter type param set incorrectly\n");
2673 ASSERT(0);
2674 break;
2675 }
2676
2677 /* vector can only be 12-bits or boundary will be exceeded */
2678 vector &= 0xFFF;
2679 return vector;
2680}
2681
2689void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2690{
2691 u32 vector;
2692 u32 vector_bit;
2693 u32 vector_reg;
2694
2695 DEBUGFUNC("ixgbe_set_mta");
2696
2697 hw->addr_ctrl.mta_in_use++;
2698
2699 vector = ixgbe_mta_vector(hw, mc_addr);
2700 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2701
2702 /*
2703 * The MTA is a register array of 128 32-bit registers. It is treated
2704 * like an array of 4096 bits. We want to set bit
2705 * BitArray[vector_value]. So we figure out what register the bit is
2706 * in, read it, OR in the new bit, then write back the new value. The
2707 * register is determined by the upper 7 bits of the vector value and
2708 * the bit within that register are determined by the lower 5 bits of
2709 * the value.
2710 */
2711 vector_reg = (vector >> 5) & 0x7F;
2712 vector_bit = vector & 0x1F;
2713 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2714}
2715
2727s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2728 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2729 bool clear)
2730{
2731 u32 i;
2732 u32 vmdq;
2733
2734 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2735
2736 /*
2737 * Set the new number of MC addresses that we are being requested to
2738 * use.
2739 */
2740 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2741 hw->addr_ctrl.mta_in_use = 0;
2742
2743 /* Clear mta_shadow */
2744 if (clear) {
2745 DEBUGOUT(" Clearing MTA\n");
2746 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2747 }
2748
2749 /* Update mta_shadow */
2750 for (i = 0; i < mc_addr_count; i++) {
2751 DEBUGOUT(" Adding the multicast addresses:\n");
2752 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2753 }
2754
2755 /* Enable mta */
2756 for (i = 0; i < hw->mac.mcft_size; i++)
2757 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2758 hw->mac.mta_shadow[i]);
2759
2760 if (hw->addr_ctrl.mta_in_use > 0)
2761 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2762 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2763
2764 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2765 return IXGBE_SUCCESS;
2766}
2767
2774s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2775{
2776 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2777
2778 DEBUGFUNC("ixgbe_enable_mc_generic");
2779
2780 if (a->mta_in_use > 0)
2781 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2782 hw->mac.mc_filter_type);
2783
2784 return IXGBE_SUCCESS;
2785}
2786
2793s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2794{
2795 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2796
2797 DEBUGFUNC("ixgbe_disable_mc_generic");
2798
2799 if (a->mta_in_use > 0)
2800 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2801
2802 return IXGBE_SUCCESS;
2803}
2804
2811s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2812{
2813 s32 ret_val = IXGBE_SUCCESS;
2814 u32 mflcn_reg, fccfg_reg;
2815 u32 reg;
2816 u32 fcrtl, fcrth;
2817 int i;
2818
2819 DEBUGFUNC("ixgbe_fc_enable_generic");
2820
2821 /* Validate the water mark configuration */
2822 if (!hw->fc.pause_time) {
2823 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2824 goto out;
2825 }
2826
2827 /* Low water mark of zero causes XOFF floods */
2828 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2829 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2830 hw->fc.high_water[i]) {
2831 if (!hw->fc.low_water[i] ||
2832 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2833 DEBUGOUT("Invalid water mark configuration\n");
2834 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2835 goto out;
2836 }
2837 }
2838 }
2839
2840 /* Negotiate the fc mode to use */
2841 hw->mac.ops.fc_autoneg(hw);
2842
2843 /* Disable any previous flow control settings */
2844 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2845 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2846
2847 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2848 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2849
2850 /*
2851 * The possible values of fc.current_mode are:
2852 * 0: Flow control is completely disabled
2853 * 1: Rx flow control is enabled (we can receive pause frames,
2854 * but not send pause frames).
2855 * 2: Tx flow control is enabled (we can send pause frames but
2856 * we do not support receiving pause frames).
2857 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2858 * other: Invalid.
2859 */
2860 switch (hw->fc.current_mode) {
2861 case ixgbe_fc_none:
2862 /*
2863 * Flow control is disabled by software override or autoneg.
2864 * The code below will actually disable it in the HW.
2865 */
2866 break;
2867 case ixgbe_fc_rx_pause:
2868 /*
2869 * Rx Flow control is enabled and Tx Flow control is
2870 * disabled by software override. Since there really
2871 * isn't a way to advertise that we are capable of RX
2872 * Pause ONLY, we will advertise that we support both
2873 * symmetric and asymmetric Rx PAUSE. Later, we will
2874 * disable the adapter's ability to send PAUSE frames.
2875 */
2876 mflcn_reg |= IXGBE_MFLCN_RFCE;
2877 break;
2878 case ixgbe_fc_tx_pause:
2879 /*
2880 * Tx Flow control is enabled, and Rx Flow control is
2881 * disabled by software override.
2882 */
2883 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2884 break;
2885 case ixgbe_fc_full:
2886 /* Flow control (both Rx and Tx) is enabled by SW override. */
2887 mflcn_reg |= IXGBE_MFLCN_RFCE;
2888 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2889 break;
2890 default:
2891 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2892 "Flow control param set incorrectly\n");
2893 ret_val = IXGBE_ERR_CONFIG;
2894 goto out;
2895 break;
2896 }
2897
2898 /* Set 802.3x based flow control settings. */
2899 mflcn_reg |= IXGBE_MFLCN_DPF;
2900 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2901 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2902
2903
2904 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2905 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2906 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2907 hw->fc.high_water[i]) {
2908 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2909 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2910 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2911 } else {
2912 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2913 /*
2914 * In order to prevent Tx hangs when the internal Tx
2915 * switch is enabled we must set the high water mark
2916 * to the Rx packet buffer size - 24KB. This allows
2917 * the Tx switch to function even under heavy Rx
2918 * workloads.
2919 */
2920 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2921 }
2922
2923 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2924 }
2925
2926 /* Configure pause time (2 TCs per register) */
2927 reg = hw->fc.pause_time * 0x00010001;
2928 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2929 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2930
2931 /* Configure flow control refresh threshold value */
2932 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2933
2934out:
2935 return ret_val;
2936}
2937
2951s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2952 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2953{
2954 if ((!(adv_reg)) || (!(lp_reg))) {
2955 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2956 "Local or link partner's advertised flow control "
2957 "settings are NULL. Local: %x, link partner: %x\n",
2958 adv_reg, lp_reg);
2959 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2960 }
2961
2962 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2963 /*
2964 * Now we need to check if the user selected Rx ONLY
2965 * of pause frames. In this case, we had to advertise
2966 * FULL flow control because we could not advertise RX
2967 * ONLY. Hence, we must now check to see if we need to
2968 * turn OFF the TRANSMISSION of PAUSE frames.
2969 */
2970 if (hw->fc.requested_mode == ixgbe_fc_full) {
2971 hw->fc.current_mode = ixgbe_fc_full;
2972 DEBUGOUT("Flow Control = FULL.\n");
2973 } else {
2974 hw->fc.current_mode = ixgbe_fc_rx_pause;
2975 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2976 }
2977 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2978 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2979 hw->fc.current_mode = ixgbe_fc_tx_pause;
2980 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2981 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2982 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2983 hw->fc.current_mode = ixgbe_fc_rx_pause;
2984 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2985 } else {
2986 hw->fc.current_mode = ixgbe_fc_none;
2987 DEBUGOUT("Flow Control = NONE.\n");
2988 }
2989 return IXGBE_SUCCESS;
2990}
2991
2998static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2999{
3000 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
3001 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3002
3003 /*
3004 * On multispeed fiber at 1g, bail out if
3005 * - link is up but AN did not complete, or if
3006 * - link is up and AN completed but timed out
3007 */
3008
3009 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3010 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
3011 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
3012 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3013 goto out;
3014 }
3015
3016 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3017 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3018
3019 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3020 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3021 IXGBE_PCS1GANA_ASM_PAUSE,
3022 IXGBE_PCS1GANA_SYM_PAUSE,
3023 IXGBE_PCS1GANA_ASM_PAUSE);
3024
3025out:
3026 return ret_val;
3027}
3028
3035static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3036{
3037 u32 links2, anlp1_reg, autoc_reg, links;
3038 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3039
3040 /*
3041 * On backplane, bail out if
3042 * - backplane autoneg was not completed, or if
3043 * - we are 82599 and link partner is not AN enabled
3044 */
3045 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3046 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3047 DEBUGOUT("Auto-Negotiation did not complete\n");
3048 goto out;
3049 }
3050
3051 if (hw->mac.type == ixgbe_mac_82599EB) {
3052 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3053 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3054 DEBUGOUT("Link partner is not AN enabled\n");
3055 goto out;
3056 }
3057 }
3058 /*
3059 * Read the 10g AN autoc and LP ability registers and resolve
3060 * local flow control settings accordingly
3061 */
3062 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3063 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3064
3065 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3066 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3067 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3068
3069out:
3070 return ret_val;
3071}
3072
3079static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3080{
3081 u16 technology_ability_reg = 0;
3082 u16 lp_technology_ability_reg = 0;
3083
3084 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3086 &technology_ability_reg);
3087 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3088 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3089 &lp_technology_ability_reg);
3090
3091 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3092 (u32)lp_technology_ability_reg,
3093 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3094 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3095}
3096
3104void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3105{
3106 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3107 ixgbe_link_speed speed;
3108 bool link_up;
3109
3110 DEBUGFUNC("ixgbe_fc_autoneg");
3111
3112 /*
3113 * AN should have completed when the cable was plugged in.
3114 * Look for reasons to bail out. Bail out if:
3115 * - FC autoneg is disabled, or if
3116 * - link is not up.
3117 */
3118 if (hw->fc.disable_fc_autoneg) {
3119 /* TODO: This should be just an informative log */
3120 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
3121 "Flow control autoneg is disabled");
3122 goto out;
3123 }
3124
3125 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3126 if (!link_up) {
3127 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3128 goto out;
3129 }
3130
3131 switch (hw->phy.media_type) {
3132 /* Autoneg flow control on fiber adapters */
3133 case ixgbe_media_type_fiber_fixed:
3134 case ixgbe_media_type_fiber_qsfp:
3135 case ixgbe_media_type_fiber:
3136 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3137 ret_val = ixgbe_fc_autoneg_fiber(hw);
3138 break;
3139
3140 /* Autoneg flow control on backplane adapters */
3141 case ixgbe_media_type_backplane:
3142 ret_val = ixgbe_fc_autoneg_backplane(hw);
3143 break;
3144
3145 /* Autoneg flow control on copper adapters */
3146 case ixgbe_media_type_copper:
3147 if (ixgbe_device_supports_autoneg_fc(hw))
3148 ret_val = ixgbe_fc_autoneg_copper(hw);
3149 break;
3150
3151 default:
3152 break;
3153 }
3154
3155out:
3156 if (ret_val == IXGBE_SUCCESS) {
3157 hw->fc.fc_was_autonegged = true;
3158 } else {
3159 hw->fc.fc_was_autonegged = false;
3160 hw->fc.current_mode = hw->fc.requested_mode;
3161 }
3162}
3163
3164/*
3165 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3166 * @hw: pointer to hardware structure
3167 *
3168 * System-wide timeout range is encoded in PCIe Device Control2 register.
3169 *
3170 * Add 10% to specified maximum and return the number of times to poll for
3171 * completion timeout, in units of 100 microsec. Never return less than
3172 * 800 = 80 millisec.
3173 */
3174static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3175{
3176 s16 devctl2;
3177 u32 pollcnt;
3178
3179 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3180 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3181
3182 switch (devctl2) {
3183 case IXGBE_PCIDEVCTRL2_65_130ms:
3184 pollcnt = 1300; /* 130 millisec */
3185 break;
3186 case IXGBE_PCIDEVCTRL2_260_520ms:
3187 pollcnt = 5200; /* 520 millisec */
3188 break;
3189 case IXGBE_PCIDEVCTRL2_1_2s:
3190 pollcnt = 20000; /* 2 sec */
3191 break;
3192 case IXGBE_PCIDEVCTRL2_4_8s:
3193 pollcnt = 80000; /* 8 sec */
3194 break;
3195 case IXGBE_PCIDEVCTRL2_17_34s:
3196 pollcnt = 34000; /* 34 sec */
3197 break;
3198 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3199 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3200 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3201 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3202 default:
3203 pollcnt = 800; /* 80 millisec minimum */
3204 break;
3205 }
3206
3207 /* add 10% to spec maximum */
3208 return (pollcnt * 11) / 10;
3209}
3210
3220s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3221{
3222 s32 status = IXGBE_SUCCESS;
3223 u32 i, poll;
3224 u16 value;
3225
3226 DEBUGFUNC("ixgbe_disable_pcie_master");
3227
3228 /* Always set this bit to ensure any future transactions are blocked */
3229 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3230
3231 /* Exit if master requests are blocked */
3232 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3233 IXGBE_REMOVED(hw->hw_addr))
3234 goto out;
3235
3236 /* Poll for master request bit to clear */
3237 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3238 usec_delay(100);
3239 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3240 goto out;
3241 }
3242
3243 /*
3244 * Two consecutive resets are required via CTRL.RST per datasheet
3245 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3246 * of this need. The first reset prevents new master requests from
3247 * being issued by our device. We then must wait 1usec or more for any
3248 * remaining completions from the PCIe bus to trickle in, and then reset
3249 * again to clear out any effects they may have had on our device.
3250 */
3251 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3252 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3253
3254 if (hw->mac.type >= ixgbe_mac_X550)
3255 goto out;
3256
3257 /*
3258 * Before proceeding, make sure that the PCIe block does not have
3259 * transactions pending.
3260 */
3261 poll = ixgbe_pcie_timeout_poll(hw);
3262 for (i = 0; i < poll; i++) {
3263 usec_delay(100);
3264 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3265 if (IXGBE_REMOVED(hw->hw_addr))
3266 goto out;
3267 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3268 goto out;
3269 }
3270
3271 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3272 "PCIe transaction pending bit also did not clear.\n");
3273 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3274
3275out:
3276 return status;
3277}
3278
3287s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3288{
3289 u32 gssr = 0;
3290 u32 swmask = mask;
3291 u32 fwmask = mask << 5;
3292 u32 timeout = 200;
3293 u32 i;
3294
3295 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3296
3297 for (i = 0; i < timeout; i++) {
3298 /*
3299 * SW NVM semaphore bit is used for access to all
3300 * SW_FW_SYNC bits (not just NVM)
3301 */
3302 if (ixgbe_get_eeprom_semaphore(hw))
3303 return IXGBE_ERR_SWFW_SYNC;
3304
3305 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3306 if (!(gssr & (fwmask | swmask))) {
3307 gssr |= swmask;
3308 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3309 ixgbe_release_eeprom_semaphore(hw);
3310 return IXGBE_SUCCESS;
3311 } else {
3312 /* Resource is currently in use by FW or SW */
3313 ixgbe_release_eeprom_semaphore(hw);
3314 msec_delay(5);
3315 }
3316 }
3317
3318 /* If time expired clear the bits holding the lock and retry */
3319 if (gssr & (fwmask | swmask))
3320 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3321
3322 msec_delay(5);
3323 return IXGBE_ERR_SWFW_SYNC;
3324}
3325
3334void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3335{
3336 u32 gssr;
3337 u32 swmask = mask;
3338
3339 DEBUGFUNC("ixgbe_release_swfw_sync");
3340
3341 ixgbe_get_eeprom_semaphore(hw);
3342
3343 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3344 gssr &= ~swmask;
3345 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3346
3347 ixgbe_release_eeprom_semaphore(hw);
3348}
3349
3357s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3358{
3359#define IXGBE_MAX_SECRX_POLL 4000
3360
3361 int i;
3362 int secrxreg;
3363
3364 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3365
3366
3367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3368 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3369 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3370 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3371 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3372 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3373 break;
3374 else
3375 /* Use interrupt-safe sleep just in case */
3376 usec_delay(10);
3377 }
3378
3379 /* For informational purposes only */
3380 if (i >= IXGBE_MAX_SECRX_POLL)
3381 DEBUGOUT("Rx unit being enabled before security "
3382 "path fully disabled. Continuing with init.\n");
3383
3384 return IXGBE_SUCCESS;
3385}
3386
3395s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3396{
3397 *locked = false;
3398 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3399 return IXGBE_SUCCESS;
3400}
3401
3411s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3412{
3413 UNREFERENCED_1PARAMETER(locked);
3414
3415 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3416 return IXGBE_SUCCESS;
3417}
3418
3425s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3426{
3427 u32 secrxreg;
3428
3429 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3430
3431 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3432 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3433 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3434 IXGBE_WRITE_FLUSH(hw);
3435
3436 return IXGBE_SUCCESS;
3437}
3438
3446s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3447{
3448 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3449
3450 if (regval & IXGBE_RXCTRL_RXEN)
3451 ixgbe_enable_rx(hw);
3452 else
3453 ixgbe_disable_rx(hw);
3454
3455 return IXGBE_SUCCESS;
3456}
3457
3463s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3464{
3465 ixgbe_link_speed speed = 0;
3466 bool link_up = 0;
3467 u32 autoc_reg = 0;
3468 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3469 s32 ret_val = IXGBE_SUCCESS;
3470 bool locked = false;
3471
3472 DEBUGFUNC("ixgbe_blink_led_start_generic");
3473
3474 if (index > 3)
3475 return IXGBE_ERR_PARAM;
3476
3477 /*
3478 * Link must be up to auto-blink the LEDs;
3479 * Force it if link is down.
3480 */
3481 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3482
3483 if (!link_up) {
3484 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3485 if (ret_val != IXGBE_SUCCESS)
3486 goto out;
3487
3488 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3489 autoc_reg |= IXGBE_AUTOC_FLU;
3490
3491 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3492 if (ret_val != IXGBE_SUCCESS)
3493 goto out;
3494
3495 IXGBE_WRITE_FLUSH(hw);
3496 msec_delay(10);
3497 }
3498
3499 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3500 led_reg |= IXGBE_LED_BLINK(index);
3501 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3502 IXGBE_WRITE_FLUSH(hw);
3503
3504out:
3505 return ret_val;
3506}
3507
3513s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3514{
3515 u32 autoc_reg = 0;
3516 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3517 s32 ret_val = IXGBE_SUCCESS;
3518 bool locked = false;
3519
3520 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3521
3522 if (index > 3)
3523 return IXGBE_ERR_PARAM;
3524
3525 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3526 if (ret_val != IXGBE_SUCCESS)
3527 goto out;
3528
3529 autoc_reg &= ~IXGBE_AUTOC_FLU;
3530 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3531
3532 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3533 if (ret_val != IXGBE_SUCCESS)
3534 goto out;
3535
3536 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3537 led_reg &= ~IXGBE_LED_BLINK(index);
3538 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3539 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3540 IXGBE_WRITE_FLUSH(hw);
3541
3542out:
3543 return ret_val;
3544}
3545
3555static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3556 u16 *san_mac_offset)
3557{
3558 s32 ret_val;
3559
3560 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3561
3562 /*
3563 * First read the EEPROM pointer to see if the MAC addresses are
3564 * available.
3565 */
3566 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3567 san_mac_offset);
3568 if (ret_val) {
3569 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3570 "eeprom at offset %d failed",
3571 IXGBE_SAN_MAC_ADDR_PTR);
3572 }
3573
3574 return ret_val;
3575}
3576
3587s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3588{
3589 u16 san_mac_data, san_mac_offset;
3590 u8 i;
3591 s32 ret_val;
3592
3593 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3594
3595 /*
3596 * First read the EEPROM pointer to see if the MAC addresses are
3597 * available. If they're not, no point in calling set_lan_id() here.
3598 */
3599 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3600 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3601 goto san_mac_addr_out;
3602
3603 /* make sure we know which port we need to program */
3604 hw->mac.ops.set_lan_id(hw);
3605 /* apply the port offset to the address offset */
3606 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3607 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3608 for (i = 0; i < 3; i++) {
3609 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3610 &san_mac_data);
3611 if (ret_val) {
3612 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3613 "eeprom read at offset %d failed",
3614 san_mac_offset);
3615 goto san_mac_addr_out;
3616 }
3617 san_mac_addr[i * 2] = (u8)(san_mac_data);
3618 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3619 san_mac_offset++;
3620 }
3621 return IXGBE_SUCCESS;
3622
3623san_mac_addr_out:
3624 /*
3625 * No addresses available in this EEPROM. It's not an
3626 * error though, so just wipe the local address and return.
3627 */
3628 for (i = 0; i < 6; i++)
3629 san_mac_addr[i] = 0xFF;
3630 return IXGBE_SUCCESS;
3631}
3632
3640s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3641{
3642 s32 ret_val;
3643 u16 san_mac_data, san_mac_offset;
3644 u8 i;
3645
3646 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3647
3648 /* Look for SAN mac address pointer. If not defined, return */
3649 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3650 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3651 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3652
3653 /* Make sure we know which port we need to write */
3654 hw->mac.ops.set_lan_id(hw);
3655 /* Apply the port offset to the address offset */
3656 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3657 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3658
3659 for (i = 0; i < 3; i++) {
3660 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3661 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3662 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3663 san_mac_offset++;
3664 }
3665
3666 return IXGBE_SUCCESS;
3667}
3668
3676u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3677{
3678 u16 msix_count = 1;
3679 u16 max_msix_count;
3680 u16 pcie_offset;
3681
3682 switch (hw->mac.type) {
3683 case ixgbe_mac_82598EB:
3684 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3685 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3686 break;
3687 case ixgbe_mac_82599EB:
3688 case ixgbe_mac_X540:
3689 case ixgbe_mac_X550:
3690 case ixgbe_mac_X550EM_x:
3691 case ixgbe_mac_X550EM_a:
3692 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3693 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3694 break;
3695 default:
3696 return msix_count;
3697 }
3698
3699 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3700 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3701 if (IXGBE_REMOVED(hw->hw_addr))
3702 msix_count = 0;
3703 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3704
3705 /* MSI-X count is zero-based in HW */
3706 msix_count++;
3707
3708 if (msix_count > max_msix_count)
3709 msix_count = max_msix_count;
3710
3711 return msix_count;
3712}
3713
3723s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3724{
3725 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3726 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3727 u32 rar;
3728 u32 rar_low, rar_high;
3729 u32 addr_low, addr_high;
3730
3731 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3732
3733 /* swap bytes for HW little endian */
3734 addr_low = addr[0] | (addr[1] << 8)
3735 | (addr[2] << 16)
3736 | (addr[3] << 24);
3737 addr_high = addr[4] | (addr[5] << 8);
3738
3739 /*
3740 * Either find the mac_id in rar or find the first empty space.
3741 * rar_highwater points to just after the highest currently used
3742 * rar in order to shorten the search. It grows when we add a new
3743 * rar to the top.
3744 */
3745 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3746 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3747
3748 if (((IXGBE_RAH_AV & rar_high) == 0)
3749 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3750 first_empty_rar = rar;
3751 } else if ((rar_high & 0xFFFF) == addr_high) {
3752 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3753 if (rar_low == addr_low)
3754 break; /* found it already in the rars */
3755 }
3756 }
3757
3758 if (rar < hw->mac.rar_highwater) {
3759 /* already there so just add to the pool bits */
3760 ixgbe_set_vmdq(hw, rar, vmdq);
3761 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3762 /* stick it into first empty RAR slot we found */
3763 rar = first_empty_rar;
3764 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3765 } else if (rar == hw->mac.rar_highwater) {
3766 /* add it to the top of the list and inc the highwater mark */
3767 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3768 hw->mac.rar_highwater++;
3769 } else if (rar >= hw->mac.num_rar_entries) {
3770 return IXGBE_ERR_INVALID_MAC_ADDR;
3771 }
3772
3773 /*
3774 * If we found rar[0], make sure the default pool bit (we use pool 0)
3775 * remains cleared to be sure default pool packets will get delivered
3776 */
3777 if (rar == 0)
3778 ixgbe_clear_vmdq(hw, rar, 0);
3779
3780 return rar;
3781}
3782
3789s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3790{
3791 u32 mpsar_lo, mpsar_hi;
3792 u32 rar_entries = hw->mac.num_rar_entries;
3793
3794 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3795
3796 /* Make sure we are using a valid rar index range */
3797 if (rar >= rar_entries) {
3798 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3799 "RAR index %d is out of range.\n", rar);
3800 return IXGBE_ERR_INVALID_ARGUMENT;
3801 }
3802
3803 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3804 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3805
3806 if (IXGBE_REMOVED(hw->hw_addr))
3807 goto done;
3808
3809 if (!mpsar_lo && !mpsar_hi)
3810 goto done;
3811
3812 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3813 if (mpsar_lo) {
3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3815 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3816 }
3817 if (mpsar_hi) {
3818 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3819 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3820 }
3821 } else if (vmdq < 32) {
3822 mpsar_lo &= ~(1 << vmdq);
3823 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3824 } else {
3825 mpsar_hi &= ~(1 << (vmdq - 32));
3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3827 }
3828
3829 /* was that the last pool using this rar? */
3830 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3831 rar != 0 && rar != hw->mac.san_mac_rar_index)
3832 hw->mac.ops.clear_rar(hw, rar);
3833done:
3834 return IXGBE_SUCCESS;
3835}
3836
3843s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3844{
3845 u32 mpsar;
3846 u32 rar_entries = hw->mac.num_rar_entries;
3847
3848 DEBUGFUNC("ixgbe_set_vmdq_generic");
3849
3850 /* Make sure we are using a valid rar index range */
3851 if (rar >= rar_entries) {
3852 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3853 "RAR index %d is out of range.\n", rar);
3854 return IXGBE_ERR_INVALID_ARGUMENT;
3855 }
3856
3857 if (vmdq < 32) {
3858 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3859 mpsar |= 1 << vmdq;
3860 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3861 } else {
3862 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3863 mpsar |= 1 << (vmdq - 32);
3864 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3865 }
3866 return IXGBE_SUCCESS;
3867}
3868
3879s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3880{
3881 u32 rar = hw->mac.san_mac_rar_index;
3882
3883 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3884
3885 if (vmdq < 32) {
3886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3888 } else {
3889 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3890 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3891 }
3892
3893 return IXGBE_SUCCESS;
3894}
3895
3900s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3901{
3902 int i;
3903
3904 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3905 DEBUGOUT(" Clearing UTA\n");
3906
3907 for (i = 0; i < 128; i++)
3908 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3909
3910 return IXGBE_SUCCESS;
3911}
3912
3924s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3925{
3926 s32 regindex, first_empty_slot;
3927 u32 bits;
3928
3929 /* short cut the special case */
3930 if (vlan == 0)
3931 return 0;
3932
3933 /* if vlvf_bypass is set we don't want to use an empty slot, we
3934 * will simply bypass the VLVF if there are no entries present in the
3935 * VLVF that contain our VLAN
3936 */
3937 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3938
3939 /* add VLAN enable bit for comparison */
3940 vlan |= IXGBE_VLVF_VIEN;
3941
3942 /* Search for the vlan id in the VLVF entries. Save off the first empty
3943 * slot found along the way.
3944 *
3945 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3946 */
3947 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3948 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3949 if (bits == vlan)
3950 return regindex;
3951 if (!first_empty_slot && !bits)
3952 first_empty_slot = regindex;
3953 }
3954
3955 /* If we are here then we didn't find the VLAN. Return first empty
3956 * slot we found during our search, else error.
3957 */
3958 if (!first_empty_slot)
3959 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3960
3961 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3962}
3963
3974s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3975 bool vlan_on, bool vlvf_bypass)
3976{
3977 u32 regidx, vfta_delta, vfta;
3978 s32 ret_val;
3979
3980 DEBUGFUNC("ixgbe_set_vfta_generic");
3981
3982 if (vlan > 4095 || vind > 63)
3983 return IXGBE_ERR_PARAM;
3984
3985 /*
3986 * this is a 2 part operation - first the VFTA, then the
3987 * VLVF and VLVFB if VT Mode is set
3988 * We don't write the VFTA until we know the VLVF part succeeded.
3989 */
3990
3991 /* Part 1
3992 * The VFTA is a bitstring made up of 128 32-bit registers
3993 * that enable the particular VLAN id, much like the MTA:
3994 * bits[11-5]: which register
3995 * bits[4-0]: which bit in the register
3996 */
3997 regidx = vlan / 32;
3998 vfta_delta = 1 << (vlan % 32);
3999 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
4000
4001 /*
4002 * vfta_delta represents the difference between the current value
4003 * of vfta and the value we want in the register. Since the diff
4004 * is an XOR mask we can just update the vfta using an XOR
4005 */
4006 vfta_delta &= vlan_on ? ~vfta : vfta;
4007 vfta ^= vfta_delta;
4008
4009 /* Part 2
4010 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4011 */
4012 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4013 vfta, vlvf_bypass);
4014 if (ret_val != IXGBE_SUCCESS) {
4015 if (vlvf_bypass)
4016 goto vfta_update;
4017 return ret_val;
4018 }
4019
4020vfta_update:
4021 /* Update VFTA now that we are ready for traffic */
4022 if (vfta_delta)
4023 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4024
4025 return IXGBE_SUCCESS;
4026}
4027
4041s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4042 bool vlan_on, u32 *vfta_delta, u32 vfta,
4043 bool vlvf_bypass)
4044{
4045 u32 bits;
4046 s32 vlvf_index;
4047
4048 DEBUGFUNC("ixgbe_set_vlvf_generic");
4049
4050 if (vlan > 4095 || vind > 63)
4051 return IXGBE_ERR_PARAM;
4052
4053 /* If VT Mode is set
4054 * Either vlan_on
4055 * make sure the vlan is in VLVF
4056 * set the vind bit in the matching VLVFB
4057 * Or !vlan_on
4058 * clear the pool bit and possibly the vind
4059 */
4060 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4061 return IXGBE_SUCCESS;
4062
4063 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4064 if (vlvf_index < 0)
4065 return vlvf_index;
4066
4067 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4068
4069 /* set the pool bit */
4070 bits |= 1 << (vind % 32);
4071 if (vlan_on)
4072 goto vlvf_update;
4073
4074 /* clear the pool bit */
4075 bits ^= 1 << (vind % 32);
4076
4077 if (!bits &&
4078 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4079 /* Clear VFTA first, then disable VLVF. Otherwise
4080 * we run the risk of stray packets leaking into
4081 * the PF via the default pool
4082 */
4083 if (*vfta_delta)
4084 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4085
4086 /* disable VLVF and clear remaining bit from pool */
4087 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4088 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4089
4090 return IXGBE_SUCCESS;
4091 }
4092
4093 /* If there are still bits set in the VLVFB registers
4094 * for the VLAN ID indicated we need to see if the
4095 * caller is requesting that we clear the VFTA entry bit.
4096 * If the caller has requested that we clear the VFTA
4097 * entry bit but there are still pools/VFs using this VLAN
4098 * ID entry then ignore the request. We're not worried
4099 * about the case where we're turning the VFTA VLAN ID
4100 * entry bit on, only when requested to turn it off as
4101 * there may be multiple pools and/or VFs using the
4102 * VLAN ID entry. In that case we cannot clear the
4103 * VFTA bit until all pools/VFs using that VLAN ID have also
4104 * been cleared. This will be indicated by "bits" being
4105 * zero.
4106 */
4107 *vfta_delta = 0;
4108
4109vlvf_update:
4110 /* record pool change and enable VLAN ID if not already enabled */
4111 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4113
4114 return IXGBE_SUCCESS;
4115}
4116
4123s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4124{
4125 u32 offset;
4126
4127 DEBUGFUNC("ixgbe_clear_vfta_generic");
4128
4129 for (offset = 0; offset < hw->mac.vft_size; offset++)
4130 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4131
4132 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4133 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4134 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4136 }
4137
4138 return IXGBE_SUCCESS;
4139}
4140
4148static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4149{
4150
4151 /* Does FW say we need the fix */
4152 if (!hw->need_crosstalk_fix)
4153 return false;
4154
4155 /* Only consider SFP+ PHYs i.e. media type fiber */
4156 switch (hw->mac.ops.get_media_type(hw)) {
4157 case ixgbe_media_type_fiber:
4158 case ixgbe_media_type_fiber_qsfp:
4159 break;
4160 default:
4161 return false;
4162 }
4163
4164 return true;
4165}
4166
4176s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4177 bool *link_up, bool link_up_wait_to_complete)
4178{
4179 u32 links_reg, links_orig;
4180 u32 i;
4181
4182 DEBUGFUNC("ixgbe_check_mac_link_generic");
4183
4184 /* If Crosstalk fix enabled do the sanity check of making sure
4185 * the SFP+ cage is full.
4186 */
4187 if (ixgbe_need_crosstalk_fix(hw)) {
4188 u32 sfp_cage_full;
4189
4190 switch (hw->mac.type) {
4191 case ixgbe_mac_82599EB:
4192 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4193 IXGBE_ESDP_SDP2;
4194 break;
4195 case ixgbe_mac_X550EM_x:
4196 case ixgbe_mac_X550EM_a:
4197 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4198 IXGBE_ESDP_SDP0;
4199 break;
4200 default:
4201 /* sanity check - No SFP+ devices here */
4202 sfp_cage_full = false;
4203 break;
4204 }
4205
4206 if (!sfp_cage_full) {
4207 *link_up = false;
4208 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4209 return IXGBE_SUCCESS;
4210 }
4211 }
4212
4213 /* clear the old state */
4214 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4215
4216 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4217
4218 if (links_orig != links_reg) {
4219 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4220 links_orig, links_reg);
4221 }
4222
4223 if (link_up_wait_to_complete) {
4224 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4225 if (links_reg & IXGBE_LINKS_UP) {
4226 *link_up = true;
4227 break;
4228 } else {
4229 *link_up = false;
4230 }
4231 msec_delay(100);
4232 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4233 }
4234 } else {
4235 if (links_reg & IXGBE_LINKS_UP)
4236 *link_up = true;
4237 else
4238 *link_up = false;
4239 }
4240
4241 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4242 case IXGBE_LINKS_SPEED_10G_82599:
4243 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4244 if (hw->mac.type >= ixgbe_mac_X550) {
4245 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4246 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4247 }
4248 break;
4249 case IXGBE_LINKS_SPEED_1G_82599:
4250 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4251 break;
4252 case IXGBE_LINKS_SPEED_100_82599:
4253 *speed = IXGBE_LINK_SPEED_100_FULL;
4254 if (hw->mac.type == ixgbe_mac_X550) {
4255 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4256 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4257 }
4258 break;
4259 case IXGBE_LINKS_SPEED_10_X550EM_A:
4260 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4261 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4262 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4263 *speed = IXGBE_LINK_SPEED_10_FULL;
4264 break;
4265 default:
4266 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4267 }
4268
4269 return IXGBE_SUCCESS;
4270}
4271
4282s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4283 u16 *wwpn_prefix)
4284{
4285 u16 offset, caps;
4286 u16 alt_san_mac_blk_offset;
4287
4288 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4289
4290 /* clear output first */
4291 *wwnn_prefix = 0xFFFF;
4292 *wwpn_prefix = 0xFFFF;
4293
4294 /* check if alternative SAN MAC is supported */
4295 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4296 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4297 goto wwn_prefix_err;
4298
4299 if ((alt_san_mac_blk_offset == 0) ||
4300 (alt_san_mac_blk_offset == 0xFFFF))
4301 goto wwn_prefix_out;
4302
4303 /* check capability in alternative san mac address block */
4304 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4305 if (hw->eeprom.ops.read(hw, offset, &caps))
4306 goto wwn_prefix_err;
4307 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4308 goto wwn_prefix_out;
4309
4310 /* get the corresponding prefix for WWNN/WWPN */
4311 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4312 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4313 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4314 "eeprom read at offset %d failed", offset);
4315 }
4316
4317 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4318 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4319 goto wwn_prefix_err;
4320
4321wwn_prefix_out:
4322 return IXGBE_SUCCESS;
4323
4324wwn_prefix_err:
4325 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4326 "eeprom read at offset %d failed", offset);
4327 return IXGBE_SUCCESS;
4328}
4329
4337s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4338{
4339 u16 offset, caps, flags;
4340 s32 status;
4341
4342 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4343
4344 /* clear output first */
4345 *bs = ixgbe_fcoe_bootstatus_unavailable;
4346
4347 /* check if FCOE IBA block is present */
4348 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4349 status = hw->eeprom.ops.read(hw, offset, &caps);
4350 if (status != IXGBE_SUCCESS)
4351 goto out;
4352
4353 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4354 goto out;
4355
4356 /* check if iSCSI FCOE block is populated */
4357 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4358 if (status != IXGBE_SUCCESS)
4359 goto out;
4360
4361 if ((offset == 0) || (offset == 0xFFFF))
4362 goto out;
4363
4364 /* read fcoe flags in iSCSI FCOE block */
4365 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4366 status = hw->eeprom.ops.read(hw, offset, &flags);
4367 if (status != IXGBE_SUCCESS)
4368 goto out;
4369
4370 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4371 *bs = ixgbe_fcoe_bootstatus_enabled;
4372 else
4373 *bs = ixgbe_fcoe_bootstatus_disabled;
4374
4375out:
4376 return status;
4377}
4378
4386void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4387{
4388 int vf_target_reg = vf >> 3;
4389 int vf_target_shift = vf % 8;
4390 u32 pfvfspoof;
4391
4392 if (hw->mac.type == ixgbe_mac_82598EB)
4393 return;
4394
4395 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4396 if (enable)
4397 pfvfspoof |= (1 << vf_target_shift);
4398 else
4399 pfvfspoof &= ~(1 << vf_target_shift);
4400 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4401}
4402
4410void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4411{
4412 int vf_target_reg = vf >> 3;
4413 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4414 u32 pfvfspoof;
4415
4416 if (hw->mac.type == ixgbe_mac_82598EB)
4417 return;
4418
4419 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4420 if (enable)
4421 pfvfspoof |= (1 << vf_target_shift);
4422 else
4423 pfvfspoof &= ~(1 << vf_target_shift);
4424 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4425}
4426
4435s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4436{
4437 DEBUGFUNC("ixgbe_get_device_caps_generic");
4438
4439 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4440
4441 return IXGBE_SUCCESS;
4442}
4443
4449void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4450{
4451 u32 regval;
4452 u32 i;
4453
4454 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4455
4456 /* Enable relaxed ordering */
4457 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4458 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4459 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4460 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4461 }
4462
4463 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4464 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4465 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4466 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4467 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4468 }
4469
4470}
4471
4479u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4480{
4481 u32 i;
4482 u8 sum = 0;
4483
4484 DEBUGFUNC("ixgbe_calculate_checksum");
4485
4486 if (!buffer)
4487 return 0;
4488
4489 for (i = 0; i < length; i++)
4490 sum += buffer[i];
4491
4492 return (u8) (0 - sum);
4493}
4494
4509s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4510 u32 timeout)
4511{
4512 u32 hicr, i, fwsts;
4513 u16 dword_len;
4514
4515 DEBUGFUNC("ixgbe_hic_unlocked");
4516
4517 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4518 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4519 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4520 }
4521
4522 /* Set bit 9 of FWSTS clearing FW reset indication */
4523 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4524 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4525
4526 /* Check that the host interface is enabled. */
4527 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4528 if (!(hicr & IXGBE_HICR_EN)) {
4529 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4530 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4531 }
4532
4533 /* Calculate length in DWORDs. We must be DWORD aligned */
4534 if (length % sizeof(u32)) {
4535 DEBUGOUT("Buffer length failure, not aligned to dword");
4536 return IXGBE_ERR_INVALID_ARGUMENT;
4537 }
4538
4539 dword_len = length >> 2;
4540
4541 /* The device driver writes the relevant command block
4542 * into the ram area.
4543 */
4544 for (i = 0; i < dword_len; i++)
4545 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4546 i, IXGBE_CPU_TO_LE32(buffer[i]));
4547
4548 /* Setting this bit tells the ARC that a new command is pending. */
4549 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4550
4551 for (i = 0; i < timeout; i++) {
4552 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4553 if (!(hicr & IXGBE_HICR_C))
4554 break;
4555 msec_delay(1);
4556 }
4557
4558 /* For each command except "Apply Update" perform
4559 * status checks in the HICR registry.
4560 */
4561 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) ==
4562 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD)
4563 return IXGBE_SUCCESS;
4564
4565 /* Check command completion */
4566 if ((timeout && i == timeout) ||
4567 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4568 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4569 "Command has failed with no status valid.\n");
4570 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4571 }
4572
4573 return IXGBE_SUCCESS;
4574}
4575
4594s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4595 u32 length, u32 timeout, bool return_data)
4596{
4597 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4598 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4599 u16 buf_len;
4600 s32 status;
4601 u32 bi;
4602 u32 dword_len;
4603
4604 DEBUGFUNC("ixgbe_host_interface_command");
4605
4606 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4607 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4608 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4609 }
4610
4611 /* Take management host interface semaphore */
4612 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4613 if (status)
4614 return status;
4615
4616 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4617 if (status)
4618 goto rel_out;
4619
4620 if (!return_data)
4621 goto rel_out;
4622
4623 /* Calculate length in DWORDs */
4624 dword_len = hdr_size >> 2;
4625
4626 /* first pull in the header so we know the buffer length */
4627 for (bi = 0; bi < dword_len; bi++) {
4628 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4629 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4630 }
4631
4632 /*
4633 * If there is any thing in data position pull it in
4634 * Read Flash command requires reading buffer length from
4635 * two byes instead of one byte
4636 */
4637 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
4638 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
4639 for (; bi < dword_len + 2; bi++) {
4640 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4641 bi);
4642 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4643 }
4644 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4645 & 0xF00) | resp->buf_len;
4646 hdr_size += (2 << 2);
4647 } else {
4648 buf_len = resp->buf_len;
4649 }
4650 if (!buf_len)
4651 goto rel_out;
4652
4653 if (length < buf_len + hdr_size) {
4654 DEBUGOUT("Buffer not large enough for reply message.\n");
4655 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4656 goto rel_out;
4657 }
4658
4659 /* Calculate length in DWORDs, add 3 for odd lengths */
4660 dword_len = (buf_len + 3) >> 2;
4661
4662 /* Pull in the rest of the buffer (bi is where we left off) */
4663 for (; bi <= dword_len; bi++) {
4664 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4665 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4666 }
4667
4668rel_out:
4669 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4670
4671 return status;
4672}
4673
4689s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4690 u8 build, u8 sub, u16 len,
4691 const char *driver_ver)
4692{
4693 struct ixgbe_hic_drv_info fw_cmd;
4694 int i;
4695 s32 ret_val = IXGBE_SUCCESS;
4696
4697 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4698 UNREFERENCED_2PARAMETER(len, driver_ver);
4699
4700 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4701 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4702 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4703 fw_cmd.port_num = (u8)hw->bus.func;
4704 fw_cmd.ver_maj = maj;
4705 fw_cmd.ver_min = min;
4706 fw_cmd.ver_build = build;
4707 fw_cmd.ver_sub = sub;
4708 fw_cmd.hdr.checksum = 0;
4709 fw_cmd.pad = 0;
4710 fw_cmd.pad2 = 0;
4711 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4712 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4713
4714 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4715 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4716 sizeof(fw_cmd),
4717 IXGBE_HI_COMMAND_TIMEOUT,
4718 true);
4719 if (ret_val != IXGBE_SUCCESS)
4720 continue;
4721
4722 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4723 FW_CEM_RESP_STATUS_SUCCESS)
4724 ret_val = IXGBE_SUCCESS;
4725 else
4726 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4727
4728 break;
4729 }
4730
4731 return ret_val;
4732}
4733
4741void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4742 int strategy)
4743{
4744 u32 pbsize = hw->mac.rx_pb_size;
4745 int i = 0;
4746 u32 rxpktsize, txpktsize, txpbthresh;
4747
4748 /* Reserve headroom */
4749 pbsize -= headroom;
4750
4751 if (!num_pb)
4752 num_pb = 1;
4753
4754 /* Divide remaining packet buffer space amongst the number of packet
4755 * buffers requested using supplied strategy.
4756 */
4757 switch (strategy) {
4758 case PBA_STRATEGY_WEIGHTED:
4759 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4760 * buffer with 5/8 of the packet buffer space.
4761 */
4762 rxpktsize = (pbsize * 5) / (num_pb * 4);
4763 pbsize -= rxpktsize * (num_pb / 2);
4764 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4765 for (; i < (num_pb / 2); i++)
4766 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4767 /* configure remaining packet buffers */
4768 /* FALLTHROUGH */
4769 case PBA_STRATEGY_EQUAL:
4770 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4771 for (; i < num_pb; i++)
4772 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4773 break;
4774 default:
4775 break;
4776 }
4777
4778 /* Only support an equally distributed Tx packet buffer strategy. */
4779 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4780 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4781 for (i = 0; i < num_pb; i++) {
4782 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4783 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4784 }
4785
4786 /* Clear unused TCs, if any, to zero buffer size*/
4787 for (; i < IXGBE_MAX_PB; i++) {
4788 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4789 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4790 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4791 }
4792}
4793
4802void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4803{
4804 u32 gcr_ext, hlreg0, i, poll;
4805 u16 value;
4806
4807 /*
4808 * If double reset is not requested then all transactions should
4809 * already be clear and as such there is no work to do
4810 */
4811 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4812 return;
4813
4814 /*
4815 * Set loopback enable to prevent any transmits from being sent
4816 * should the link come up. This assumes that the RXCTRL.RXEN bit
4817 * has already been cleared.
4818 */
4819 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4820 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4821
4822 /* Wait for a last completion before clearing buffers */
4823 IXGBE_WRITE_FLUSH(hw);
4824 msec_delay(3);
4825
4826 /*
4827 * Before proceeding, make sure that the PCIe block does not have
4828 * transactions pending.
4829 */
4830 poll = ixgbe_pcie_timeout_poll(hw);
4831 for (i = 0; i < poll; i++) {
4832 usec_delay(100);
4833 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4834 if (IXGBE_REMOVED(hw->hw_addr))
4835 goto out;
4836 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4837 goto out;
4838 }
4839
4840out:
4841 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4842 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4843 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4844 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4845
4846 /* Flush all writes and allow 20usec for all transactions to clear */
4847 IXGBE_WRITE_FLUSH(hw);
4848 usec_delay(20);
4849
4850 /* restore previous register values */
4851 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4852 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4853}
4854
4855static const u8 ixgbe_emc_temp_data[4] = {
4856 IXGBE_EMC_INTERNAL_DATA,
4857 IXGBE_EMC_DIODE1_DATA,
4858 IXGBE_EMC_DIODE2_DATA,
4859 IXGBE_EMC_DIODE3_DATA
4860};
4861static const u8 ixgbe_emc_therm_limit[4] = {
4862 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4863 IXGBE_EMC_DIODE1_THERM_LIMIT,
4864 IXGBE_EMC_DIODE2_THERM_LIMIT,
4865 IXGBE_EMC_DIODE3_THERM_LIMIT
4866};
4867
4874s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4875{
4876 s32 status = IXGBE_SUCCESS;
4877 u16 ets_offset;
4878 u16 ets_cfg;
4879 u16 ets_sensor;
4880 u8 num_sensors;
4881 u8 sensor_index;
4882 u8 sensor_location;
4883 u8 i;
4884 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4885
4886 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4887
4888 /* Only support thermal sensors attached to 82599 physical port 0 */
4889 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4890 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4891 status = IXGBE_NOT_IMPLEMENTED;
4892 goto out;
4893 }
4894
4895 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4896 if (status)
4897 goto out;
4898
4899 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4900 status = IXGBE_NOT_IMPLEMENTED;
4901 goto out;
4902 }
4903
4904 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4905 if (status)
4906 goto out;
4907
4908 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4909 != IXGBE_ETS_TYPE_EMC) {
4910 status = IXGBE_NOT_IMPLEMENTED;
4911 goto out;
4912 }
4913
4914 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4915 if (num_sensors > IXGBE_MAX_SENSORS)
4916 num_sensors = IXGBE_MAX_SENSORS;
4917
4918 for (i = 0; i < num_sensors; i++) {
4919 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4920 &ets_sensor);
4921 if (status)
4922 goto out;
4923
4924 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4925 IXGBE_ETS_DATA_INDEX_SHIFT);
4926 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4927 IXGBE_ETS_DATA_LOC_SHIFT);
4928
4929 if (sensor_location != 0) {
4930 status = hw->phy.ops.read_i2c_byte(hw,
4931 ixgbe_emc_temp_data[sensor_index],
4932 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4933 &data->sensor[i].temp);
4934 if (status)
4935 goto out;
4936 }
4937 }
4938out:
4939 return status;
4940}
4941
4949s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4950{
4951 s32 status = IXGBE_SUCCESS;
4952 u16 offset;
4953 u16 ets_offset;
4954 u16 ets_cfg;
4955 u16 ets_sensor;
4956 u8 low_thresh_delta;
4957 u8 num_sensors;
4958 u8 sensor_index;
4959 u8 sensor_location;
4960 u8 therm_limit;
4961 u8 i;
4962 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4963
4964 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4965
4966 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4967
4968 /* Only support thermal sensors attached to 82599 physical port 0 */
4969 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4970 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4971 return IXGBE_NOT_IMPLEMENTED;
4972
4973 offset = IXGBE_ETS_CFG;
4974 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4975 goto eeprom_err;
4976 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4977 return IXGBE_NOT_IMPLEMENTED;
4978
4979 offset = ets_offset;
4980 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4981 goto eeprom_err;
4982 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4983 != IXGBE_ETS_TYPE_EMC)
4984 return IXGBE_NOT_IMPLEMENTED;
4985
4986 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4987 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4988 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4989
4990 for (i = 0; i < num_sensors; i++) {
4991 offset = ets_offset + 1 + i;
4992 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4993 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4994 "eeprom read at offset %d failed",
4995 offset);
4996 continue;
4997 }
4998 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4999 IXGBE_ETS_DATA_INDEX_SHIFT);
5000 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
5001 IXGBE_ETS_DATA_LOC_SHIFT);
5002 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
5003
5004 hw->phy.ops.write_i2c_byte(hw,
5005 ixgbe_emc_therm_limit[sensor_index],
5006 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
5007
5008 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
5009 data->sensor[i].location = sensor_location;
5010 data->sensor[i].caution_thresh = therm_limit;
5011 data->sensor[i].max_op_thresh = therm_limit -
5012 low_thresh_delta;
5013 }
5014 }
5015 return status;
5016
5017eeprom_err:
5018 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
5019 "eeprom read at offset %d failed", offset);
5020 return IXGBE_NOT_IMPLEMENTED;
5021}
5022
5032#define IXGBE_BYPASS_BB_WAIT 1
5033s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
5034{
5035 int i;
5036 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
5037 u32 esdp;
5038
5039 if (!status)
5040 return IXGBE_ERR_PARAM;
5041
5042 *status = 0;
5043
5044 /* SDP vary by MAC type */
5045 switch (hw->mac.type) {
5046 case ixgbe_mac_82599EB:
5047 sck = IXGBE_ESDP_SDP7;
5048 sdi = IXGBE_ESDP_SDP0;
5049 sdo = IXGBE_ESDP_SDP6;
5050 dir_sck = IXGBE_ESDP_SDP7_DIR;
5051 dir_sdi = IXGBE_ESDP_SDP0_DIR;
5052 dir_sdo = IXGBE_ESDP_SDP6_DIR;
5053 break;
5054 case ixgbe_mac_X540:
5055 sck = IXGBE_ESDP_SDP2;
5056 sdi = IXGBE_ESDP_SDP0;
5057 sdo = IXGBE_ESDP_SDP1;
5058 dir_sck = IXGBE_ESDP_SDP2_DIR;
5059 dir_sdi = IXGBE_ESDP_SDP0_DIR;
5060 dir_sdo = IXGBE_ESDP_SDP1_DIR;
5061 break;
5062 default:
5063 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
5064 }
5065
5066 /* Set SDP pins direction */
5067 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5068 esdp |= dir_sck; /* SCK as output */
5069 esdp |= dir_sdi; /* SDI as output */
5070 esdp &= ~dir_sdo; /* SDO as input */
5071 esdp |= sck;
5072 esdp |= sdi;
5073 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5074 IXGBE_WRITE_FLUSH(hw);
5075 msec_delay(IXGBE_BYPASS_BB_WAIT);
5076
5077 /* Generate start condition */
5078 esdp &= ~sdi;
5079 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5080 IXGBE_WRITE_FLUSH(hw);
5081 msec_delay(IXGBE_BYPASS_BB_WAIT);
5082
5083 esdp &= ~sck;
5084 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5085 IXGBE_WRITE_FLUSH(hw);
5086 msec_delay(IXGBE_BYPASS_BB_WAIT);
5087
5088 /* Clock out the new control word and clock in the status */
5089 for (i = 0; i < 32; i++) {
5090 if ((cmd >> (31 - i)) & 0x01) {
5091 esdp |= sdi;
5092 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5093 } else {
5094 esdp &= ~sdi;
5095 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5096 }
5097 IXGBE_WRITE_FLUSH(hw);
5098 msec_delay(IXGBE_BYPASS_BB_WAIT);
5099
5100 esdp |= sck;
5101 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5102 IXGBE_WRITE_FLUSH(hw);
5103 msec_delay(IXGBE_BYPASS_BB_WAIT);
5104
5105 esdp &= ~sck;
5106 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5107 IXGBE_WRITE_FLUSH(hw);
5108 msec_delay(IXGBE_BYPASS_BB_WAIT);
5109
5110 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5111 if (esdp & sdo)
5112 *status = (*status << 1) | 0x01;
5113 else
5114 *status = (*status << 1) | 0x00;
5115 msec_delay(IXGBE_BYPASS_BB_WAIT);
5116 }
5117
5118 /* stop condition */
5119 esdp |= sck;
5120 esdp &= ~sdi;
5121 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5122 IXGBE_WRITE_FLUSH(hw);
5123 msec_delay(IXGBE_BYPASS_BB_WAIT);
5124
5125 esdp |= sdi;
5126 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5127 IXGBE_WRITE_FLUSH(hw);
5128
5129 /* set the page bits to match the cmd that the status it belongs to */
5130 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
5131
5132 return IXGBE_SUCCESS;
5133}
5134
5147bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
5148{
5149 u32 mask;
5150
5151 /* Page must match for all control pages */
5152 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
5153 return false;
5154
5155 switch (in_reg & BYPASS_PAGE_M) {
5156 case BYPASS_PAGE_CTL0:
5157 /* All the following can't change since the last write
5158 * - All the event actions
5159 * - The timeout value
5160 */
5161 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
5162 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
5163 BYPASS_WDTIMEOUT_M |
5164 BYPASS_WDT_VALUE_M;
5165 if ((out_reg & mask) != (in_reg & mask))
5166 return false;
5167
5168 /* 0x0 is never a valid value for bypass status */
5169 if (!(out_reg & BYPASS_STATUS_OFF_M))
5170 return false;
5171 break;
5172 case BYPASS_PAGE_CTL1:
5173 /* All the following can't change since the last write
5174 * - time valid bit
5175 * - time we last sent
5176 */
5177 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
5178 if ((out_reg & mask) != (in_reg & mask))
5179 return false;
5180 break;
5181 case BYPASS_PAGE_CTL2:
5182 /* All we can check in this page is control number
5183 * which is already done above.
5184 */
5185 break;
5186 }
5187
5188 /* We are as sure as we can be return true */
5189 return true;
5190}
5191
5203s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
5204 u32 action)
5205{
5206 u32 by_ctl = 0;
5207 u32 cmd, verify;
5208 u32 count = 0;
5209
5210 /* Get current values */
5211 cmd = ctrl; /* just reading only need control number */
5212 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5213 return IXGBE_ERR_INVALID_ARGUMENT;
5214
5215 /* Set to new action */
5216 cmd = (by_ctl & ~event) | BYPASS_WE | action;
5217 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5218 return IXGBE_ERR_INVALID_ARGUMENT;
5219
5220 /* Page 0 force a FW eeprom write which is slow so verify */
5221 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
5222 verify = BYPASS_PAGE_CTL0;
5223 do {
5224 if (count++ > 5)
5225 return IXGBE_BYPASS_FW_WRITE_FAILURE;
5226
5227 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
5228 return IXGBE_ERR_INVALID_ARGUMENT;
5229 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
5230 } else {
5231 /* We have give the FW time for the write to stick */
5232 msec_delay(100);
5233 }
5234
5235 return IXGBE_SUCCESS;
5236}
5237
5245s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
5246{
5247 u32 cmd;
5248 u32 status;
5249
5250
5251 /* send the request */
5252 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
5253 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
5254 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5255 return IXGBE_ERR_INVALID_ARGUMENT;
5256
5257 /* We have give the FW time for the write to stick */
5258 msec_delay(100);
5259
5260 /* now read the results */
5261 cmd &= ~BYPASS_WE;
5262 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5263 return IXGBE_ERR_INVALID_ARGUMENT;
5264
5265 *value = status & BYPASS_CTL2_DATA_M;
5266
5267 return IXGBE_SUCCESS;
5268}
5269
5279void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5280 struct ixgbe_nvm_version *nvm_ver)
5281{
5282 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5283
5284 nvm_ver->or_valid = false;
5285 /* Option Rom may or may not be present. Start with pointer */
5286 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5287
5288 /* make sure offset is valid */
5289 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5290 return;
5291
5292 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5293 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5294
5295 /* option rom exists and is valid */
5296 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5297 eeprom_cfg_blkl == NVM_VER_INVALID ||
5298 eeprom_cfg_blkh == NVM_VER_INVALID)
5299 return;
5300
5301 nvm_ver->or_valid = true;
5302 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5303 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5304 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5305 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5306}
5307
5317void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5318 struct ixgbe_nvm_version *nvm_ver)
5319{
5320 u16 rel_num, prod_ver, mod_len, cap, offset;
5321
5322 nvm_ver->oem_valid = false;
5323 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5324
5325 /* Return if offset to OEM Product Version block is invalid */
5326 if (offset == 0x0 || offset == NVM_INVALID_PTR)
5327 return;
5328
5329 /* Read product version block */
5330 hw->eeprom.ops.read(hw, offset, &mod_len);
5331 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5332
5333 /* Return if OEM product version block is invalid */
5334 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5335 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5336 return;
5337
5338 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5339 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5340
5341 /* Return if version is invalid */
5342 if ((rel_num | prod_ver) == 0x0 ||
5343 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5344 return;
5345
5346 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5347 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5348 nvm_ver->oem_release = rel_num;
5349 nvm_ver->oem_valid = true;
5350}
5351
5360void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5361{
5362 u16 etk_id_l, etk_id_h;
5363
5364 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5365 etk_id_l = NVM_VER_INVALID;
5366 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5367 etk_id_h = NVM_VER_INVALID;
5368
5369 /* The word order for the version format is determined by high order
5370 * word bit 15.
5371 */
5372 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5373 nvm_ver->etk_id = etk_id_h;
5374 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5375 } else {
5376 nvm_ver->etk_id = etk_id_l;
5377 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5378 }
5379}
5380
5381
5389void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5390{
5391 u32 reg, i;
5392
5393 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5394 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5395 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5396 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5397 return;
5398}
5399
5400void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5401{
5402 u32 pfdtxgswc;
5403 u32 rxctrl;
5404
5405 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5406 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5407 if (hw->mac.type != ixgbe_mac_82598EB) {
5408 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5409 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5410 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5411 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5412 hw->mac.set_lben = true;
5413 } else {
5414 hw->mac.set_lben = false;
5415 }
5416 }
5417 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5418 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5419 }
5420}
5421
5422void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5423{
5424 u32 pfdtxgswc;
5425 u32 rxctrl;
5426
5427 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5428 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5429
5430 if (hw->mac.type != ixgbe_mac_82598EB) {
5431 if (hw->mac.set_lben) {
5432 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5433 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5434 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5435 hw->mac.set_lben = false;
5436 }
5437 }
5438}
5439
5444bool ixgbe_mng_present(struct ixgbe_hw *hw)
5445{
5446 u32 fwsm;
5447
5448 if (hw->mac.type < ixgbe_mac_82599EB)
5449 return false;
5450
5451 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5452
5453 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5454}
5455
5462bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5463{
5464 u32 fwsm, manc, factps;
5465
5466 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5467 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5468 return false;
5469
5470 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5471 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5472 return false;
5473
5474 if (hw->mac.type <= ixgbe_mac_X540) {
5475 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5476 if (factps & IXGBE_FACTPS_MNGCG)
5477 return false;
5478 }
5479
5480 return true;
5481}
5482
5491s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5492 ixgbe_link_speed speed,
5493 bool autoneg_wait_to_complete)
5494{
5495 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5496 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5497 s32 status = IXGBE_SUCCESS;
5498 u32 speedcnt = 0;
5499 u32 i = 0;
5500 bool autoneg, link_up = false;
5501
5502 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5503
5504 /* Mask off requested but non-supported speeds */
5505 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5506 if (status != IXGBE_SUCCESS)
5507 return status;
5508
5509 speed &= link_speed;
5510
5511 /* Try each speed one by one, highest priority first. We do this in
5512 * software because 10Gb fiber doesn't support speed autonegotiation.
5513 */
5514 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5515 speedcnt++;
5516 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5517
5518 /* Set the module link speed */
5519 switch (hw->phy.media_type) {
5520 case ixgbe_media_type_fiber_fixed:
5521 case ixgbe_media_type_fiber:
5522 ixgbe_set_rate_select_speed(hw,
5523 IXGBE_LINK_SPEED_10GB_FULL);
5524 break;
5525 case ixgbe_media_type_fiber_qsfp:
5526 /* QSFP module automatically detects MAC link speed */
5527 break;
5528 default:
5529 DEBUGOUT("Unexpected media type.\n");
5530 break;
5531 }
5532
5533 /* Allow module to change analog characteristics (1G->10G) */
5534 msec_delay(40);
5535
5536 status = ixgbe_setup_mac_link(hw,
5537 IXGBE_LINK_SPEED_10GB_FULL,
5538 autoneg_wait_to_complete);
5539 if (status != IXGBE_SUCCESS)
5540 return status;
5541
5542 /* Flap the Tx laser if it has not already been done */
5543 ixgbe_flap_tx_laser(hw);
5544
5545 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5546 * Section 73.10.2, we may have to wait up to 1000ms if KR is
5547 * attempted. 82599 uses the same timing for 10g SFI.
5548 */
5549 for (i = 0; i < 10; i++) {
5550 /* Wait for the link partner to also set speed */
5551 msec_delay(100);
5552
5553 /* If we have link, just jump out */
5554 status = ixgbe_check_link(hw, &link_speed,
5555 &link_up, false);
5556 if (status != IXGBE_SUCCESS)
5557 return status;
5558
5559 if (link_up)
5560 goto out;
5561 }
5562 }
5563
5564 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5565 speedcnt++;
5566 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5567 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5568
5569 /* Set the module link speed */
5570 switch (hw->phy.media_type) {
5571 case ixgbe_media_type_fiber_fixed:
5572 case ixgbe_media_type_fiber:
5573 ixgbe_set_rate_select_speed(hw,
5574 IXGBE_LINK_SPEED_1GB_FULL);
5575 break;
5576 case ixgbe_media_type_fiber_qsfp:
5577 /* QSFP module automatically detects link speed */
5578 break;
5579 default:
5580 DEBUGOUT("Unexpected media type.\n");
5581 break;
5582 }
5583
5584 /* Allow module to change analog characteristics (10G->1G) */
5585 msec_delay(40);
5586
5587 status = ixgbe_setup_mac_link(hw,
5588 IXGBE_LINK_SPEED_1GB_FULL,
5589 autoneg_wait_to_complete);
5590 if (status != IXGBE_SUCCESS)
5591 return status;
5592
5593 /* Flap the Tx laser if it has not already been done */
5594 ixgbe_flap_tx_laser(hw);
5595
5596 /* Wait for the link partner to also set speed */
5597 msec_delay(100);
5598
5599 /* If we have link, just jump out */
5600 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5601 if (status != IXGBE_SUCCESS)
5602 return status;
5603
5604 if (link_up)
5605 goto out;
5606 }
5607
5608 /* We didn't get link. Configure back to the highest speed we tried,
5609 * (if there was more than one). We call ourselves back with just the
5610 * single highest speed that the user requested.
5611 */
5612 if (speedcnt > 1)
5613 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5614 highest_link_speed,
5615 autoneg_wait_to_complete);
5616
5617out:
5618 /* Set autoneg_advertised value based on input link speed */
5619 hw->phy.autoneg_advertised = 0;
5620
5621 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5622 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5623
5624 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5625 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5626
5627 return status;
5628}
5629
5637void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5638 ixgbe_link_speed speed)
5639{
5640 s32 status;
5641 u8 rs, eeprom_data;
5642
5643 switch (speed) {
5644 case IXGBE_LINK_SPEED_10GB_FULL:
5645 /* one bit mask same as setting on */
5646 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5647 break;
5648 case IXGBE_LINK_SPEED_1GB_FULL:
5649 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5650 break;
5651 default:
5652 DEBUGOUT("Invalid fixed module speed\n");
5653 return;
5654 }
5655
5656 /* Set RS0 */
5657 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5658 IXGBE_I2C_EEPROM_DEV_ADDR2,
5659 &eeprom_data);
5660 if (status) {
5661 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5662 goto out;
5663 }
5664
5665 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5666
5667 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5668 IXGBE_I2C_EEPROM_DEV_ADDR2,
5669 eeprom_data);
5670 if (status) {
5671 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5672 goto out;
5673 }
5674
5675 /* Set RS1 */
5676 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5677 IXGBE_I2C_EEPROM_DEV_ADDR2,
5678 &eeprom_data);
5679 if (status) {
5680 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5681 goto out;
5682 }
5683
5684 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5685
5686 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5687 IXGBE_I2C_EEPROM_DEV_ADDR2,
5688 eeprom_data);
5689 if (status) {
5690 DEBUGOUT("Failed to write Rx Rate Select RS1\n");
5691 goto out;
5692 }
5693out:
5694 return;
5695}
ixgbe_set_rate_select_speed
void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
Definition: ixgbe_api.c:1780
ixgbe_check_link
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
Definition: ixgbe_api.c:667
ixgbe_clear_vmdq
s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Definition: ixgbe_api.c:993
ixgbe_get_link_capabilities
s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
Definition: ixgbe_api.c:755
ixgbe_set_rar
s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr)
Definition: ixgbe_api.c:943
ixgbe_setup_mac_link
s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
Definition: ixgbe_api.c:739
ixgbe_flap_tx_laser
void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:707
ixgbe_enable_rx
void ixgbe_enable_rx(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:1767
ixgbe_identify_phy
s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:504
ixgbe_setup_fc
s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:1155
ixgbe_disable_rx
void ixgbe_disable_rx(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:1761
ixgbe_set_vmdq
s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Definition: ixgbe_api.c:969
ixgbe_init_uta_tables
s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
Definition: ixgbe_api.c:1503
ixgbe_api.h
ixgbe_set_mta
void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
Definition: ixgbe_common.c:2689
ixgbe_blink_led_start_generic
s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
Definition: ixgbe_common.c:3463
ixgbe_mng_present
bool ixgbe_mng_present(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:5444
ixgbe_set_vmdq_generic
s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Definition: ixgbe_common.c:3843
ixgbe_add_uc_addr
void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
Definition: ixgbe_common.c:2544
ixgbe_mta_vector
static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
Definition: ixgbe_common.c:2652
ixgbe_update_eeprom_checksum_generic
s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2321
ixgbe_clear_vmdq_generic
s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Definition: ixgbe_common.c:3789
ixgbe_led_off_generic
s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
Definition: ixgbe_common.c:1225
ixgbe_set_vmdq_san_mac_generic
s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
Definition: ixgbe_common.c:3879
ixgbe_write_eeprom_generic
s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
Definition: ixgbe_common.c:1444
ixgbe_set_vlan_anti_spoofing
void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
Definition: ixgbe_common.c:4410
ixgbe_write_pba_raw
s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, u32 eeprom_buf_size, struct ixgbe_pba *pba)
Definition: ixgbe_common.c:861
ixgbe_shift_out_eeprom_bits
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, u16 count)
Definition: ixgbe_common.c:2047
ixgbe_find_vlvf_slot
s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
Definition: ixgbe_common.c:3924
ixgbe_clear_rar_generic
s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
Definition: ixgbe_common.c:2436
ixgbe_bypass_valid_rd_generic
bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
Definition: ixgbe_common.c:5147
ixgbe_set_mac_anti_spoofing
void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
Definition: ixgbe_common.c:4386
ixgbe_enable_rx_dma_generic
s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
Definition: ixgbe_common.c:3446
ixgbe_init_thermal_sensor_thresh_generic
s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:4949
ixgbe_update_uc_addr_list_generic
s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, u32 addr_count, ixgbe_mc_addr_itr next)
Definition: ixgbe_common.c:2584
ixgbe_clear_vfta_generic
s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:4123
ixgbe_fc_autoneg_backplane
static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3035
ixgbe_device_supports_autoneg_fc
bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:163
ixgbe_set_rar_generic
s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr)
Definition: ixgbe_common.c:2385
IXGBE_BYPASS_BB_WAIT
#define IXGBE_BYPASS_BB_WAIT
Definition: ixgbe_common.c:5032
ixgbe_write_eeprom_buffer_bit_bang_generic
s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
Definition: ixgbe_common.c:1305
ixgbe_acquire_eeprom
static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1818
ixgbe_read_eeprom_buffer_bit_bang_generic
s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
Definition: ixgbe_common.c:1472
ixgbe_fc_enable_generic
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2811
ixgbe_emc_therm_limit
static const u8 ixgbe_emc_therm_limit[4]
Definition: ixgbe_common.c:4861
ixgbe_init_led_link_act_generic
s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1163
ixgbe_get_fcoe_boot_status_generic
s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
Definition: ixgbe_common.c:4337
ixgbe_init_uta_tables_generic
s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3900
ixgbe_shift_in_eeprom_bits
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
Definition: ixgbe_common.c:2103
ixgbe_enable_rx_generic
void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:5422
ixgbe_detect_eeprom_page_size_generic
static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, u16 offset)
Definition: ixgbe_common.c:1658
ixgbe_bypass_rw_generic
s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
Definition: ixgbe_common.c:5033
ixgbe_blink_led_stop_generic
s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
Definition: ixgbe_common.c:3513
ixgbe_enable_sec_rx_path_generic
s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3425
ixgbe_set_soft_rate_select_speed
void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
Definition: ixgbe_common.c:5637
ixgbe_setup_fc_generic
s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:236
ixgbe_fc_autoneg_copper
static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3079
ixgbe_get_mac_addr_generic
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
Definition: ixgbe_common.c:978
ixgbe_start_hw_generic
s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:396
ixgbe_set_lan_id_multi_port_pcie
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1077
ixgbe_read_pba_raw
s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, u32 eeprom_buf_size, u16 max_pba_block_size, struct ixgbe_pba *pba)
Definition: ixgbe_common.c:792
ixgbe_clear_hw_cntrs_generic
s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:528
ixgbe_init_hw_generic
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:497
ixgbe_set_pci_config_data_generic
void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
Definition: ixgbe_common.c:1005
ixgbe_set_rxpba_generic
void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, int strategy)
Definition: ixgbe_common.c:4741
ixgbe_release_eeprom
static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2180
ixgbe_enable_mc_generic
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2774
ixgbe_bypass_set_generic
s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, u32 action)
Definition: ixgbe_common.c:5203
ixgbe_get_pba_block_size
s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, u32 eeprom_buf_size, u16 *pba_block_size)
Definition: ixgbe_common.c:920
ixgbe_disable_rx_generic
void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:5400
IXGBE_MAX_SECRX_POLL
#define IXGBE_MAX_SECRX_POLL
ixgbe_read_pba_num_generic
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
Definition: ixgbe_common.c:753
ixgbe_standby_eeprom
static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2022
ixgbe_bypass_rd_eep_generic
s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
Definition: ixgbe_common.c:5245
ixgbe_calc_eeprom_checksum_generic
s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2212
ixgbe_disable_mc_generic
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2793
ixgbe_acquire_swfw_sync
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
Definition: ixgbe_common.c:3287
ixgbe_need_crosstalk_fix
static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:4148
ixgbe_get_san_mac_addr_offset
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset)
Definition: ixgbe_common.c:3555
ixgbe_get_orom_version
void ixgbe_get_orom_version(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
Definition: ixgbe_common.c:5279
ixgbe_raise_eeprom_clk
static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
Definition: ixgbe_common.c:2143
ixgbe_get_san_mac_addr_generic
s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
Definition: ixgbe_common.c:3587
ixgbe_enable_relaxed_ordering_gen2
void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:4449
ixgbe_get_device_caps_generic
s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
Definition: ixgbe_common.c:4435
ixgbe_init_ops_generic
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:70
ixgbe_set_vfta_generic
s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, bool vlvf_bypass)
Definition: ixgbe_common.c:3974
ixgbe_disable_pcie_master
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3220
ixgbe_emc_temp_data
static const u8 ixgbe_emc_temp_data[4]
Definition: ixgbe_common.c:4855
ixgbe_lower_eeprom_clk
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
Definition: ixgbe_common.c:2162
ixgbe_read_eerd_buffer_generic
s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
Definition: ixgbe_common.c:1607
prot_autoc_read_generic
s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
Definition: ixgbe_common.c:3395
ixgbe_read_eeprom_bit_bang_generic
s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
Definition: ixgbe_common.c:1578
ixgbe_init_eeprom_params_generic
s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1250
ixgbe_led_on_generic
s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
Definition: ixgbe_common.c:1202
ixgbe_stop_adapter_generic
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1111
ixgbe_start_hw_gen2
void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:460
ixgbe_get_etk_id
void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
Definition: ixgbe_common.c:5360
ixgbe_write_eeprom_buffer_bit_bang
static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
Definition: ixgbe_common.c:1362
ixgbe_release_eeprom_semaphore
static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1963
ixgbe_ready_eeprom
static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1981
ixgbe_setup_mac_link_multispeed_fiber
s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
Definition: ixgbe_common.c:5491
ixgbe_validate_eeprom_checksum_generic
s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, u16 *checksum_val)
Definition: ixgbe_common.c:2273
ixgbe_set_vlvf_generic
s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, u32 *vfta_delta, u32 vfta, bool vlvf_bypass)
Definition: ixgbe_common.c:4041
ixgbe_hic_unlocked
s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, u32 timeout)
Definition: ixgbe_common.c:4509
ixgbe_fc_autoneg_fiber
static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2998
ixgbe_check_mac_link_generic
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
Definition: ixgbe_common.c:4176
ixgbe_write_eewr_generic
s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
Definition: ixgbe_common.c:1770
ixgbe_read_eerd_generic
s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
Definition: ixgbe_common.c:1701
ixgbe_read_eeprom_buffer_bit_bang
static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
Definition: ixgbe_common.c:1521
ixgbe_poll_eerd_eewr_done
s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
Definition: ixgbe_common.c:1783
ixgbe_get_wwn_prefix_generic
s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix)
Definition: ixgbe_common.c:4282
ixgbe_init_rx_addrs_generic
s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:2475
ixgbe_calculate_checksum
u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
Definition: ixgbe_common.c:4479
ixgbe_read_pba_string_generic
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
Definition: ixgbe_common.c:643
ixgbe_set_fw_drv_ver_generic
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, u8 sub, u16 len, const char *driver_ver)
Definition: ixgbe_common.c:4689
ixgbe_fc_autoneg
void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3104
ixgbe_release_swfw_sync
void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
Definition: ixgbe_common.c:3334
ixgbe_set_san_mac_addr_generic
s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
Definition: ixgbe_common.c:3640
ixgbe_disable_sec_rx_path_generic
s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3357
ixgbe_write_eewr_buffer_generic
s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
Definition: ixgbe_common.c:1715
ixgbe_get_thermal_sensor_data_generic
s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:4874
ixgbe_insert_mac_addr_generic
s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
Definition: ixgbe_common.c:3723
ixgbe_validate_mac_addr
s32 ixgbe_validate_mac_addr(u8 *mac_addr)
Definition: ixgbe_common.c:2355
ixgbe_get_eeprom_semaphore
static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1872
ixgbe_get_bus_info_generic
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:1055
ixgbe_negotiate_fc
s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
Definition: ixgbe_common.c:2951
ixgbe_get_pcie_msix_count_generic
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3676
ixgbe_host_interface_command
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, u32 length, u32 timeout, bool return_data)
Definition: ixgbe_common.c:4594
ixgbe_mng_enabled
bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:5462
ixgbe_clear_tx_pending
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:4802
ixgbe_dcb_get_rtrup2tc_generic
void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
Definition: ixgbe_common.c:5389
ixgbe_get_oem_prod_version
void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
Definition: ixgbe_common.c:5317
ixgbe_update_mc_addr_list_generic
s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, u32 mc_addr_count, ixgbe_mc_addr_itr next, bool clear)
Definition: ixgbe_common.c:2727
ixgbe_pcie_timeout_poll
static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
Definition: ixgbe_common.c:3174
prot_autoc_write_generic
s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
Definition: ixgbe_common.c:3411
ixgbe_common.h
IXGBE_EMC_DIODE2_THERM_LIMIT
#define IXGBE_EMC_DIODE2_THERM_LIMIT
Definition: ixgbe_common.h:187
IXGBE_EMC_DIODE1_THERM_LIMIT
#define IXGBE_EMC_DIODE1_THERM_LIMIT
Definition: ixgbe_common.h:185
IXGBE_EMC_INTERNAL_DATA
#define IXGBE_EMC_INTERNAL_DATA
Definition: ixgbe_common.h:182
IXGBE_EMC_DIODE3_DATA
#define IXGBE_EMC_DIODE3_DATA
Definition: ixgbe_common.h:188
IXGBE_EMC_DIODE2_DATA
#define IXGBE_EMC_DIODE2_DATA
Definition: ixgbe_common.h:186
IXGBE_EMC_INTERNAL_THERM_LIMIT
#define IXGBE_EMC_INTERNAL_THERM_LIMIT
Definition: ixgbe_common.h:183
IXGBE_EMC_DIODE1_DATA
#define IXGBE_EMC_DIODE1_DATA
Definition: ixgbe_common.h:184
IXGBE_I2C_THERMAL_SENSOR_ADDR
#define IXGBE_I2C_THERMAL_SENSOR_ADDR
Definition: ixgbe_common.h:181
IXGBE_REMOVED
#define IXGBE_REMOVED(a)
Definition: ixgbe_common.h:45
IXGBE_EMC_DIODE3_THERM_LIMIT
#define IXGBE_EMC_DIODE3_THERM_LIMIT
Definition: ixgbe_common.h:189
ixgbe_dcb.h
IXGBE_DCB_MAX_USER_PRIORITY
#define IXGBE_DCB_MAX_USER_PRIORITY
Definition: ixgbe_dcb.h:53
ixgbe_dcb_82599.h
IXGBE_RTRUP2TC_UP_MASK
#define IXGBE_RTRUP2TC_UP_MASK
Definition: ixgbe_dcb_82599.h:49
IXGBE_RTRUP2TC_UP_SHIFT
#define IXGBE_RTRUP2TC_UP_SHIFT
Definition: ixgbe_dcb_82599.h:48
UNREFERENCED_2PARAMETER
#define UNREFERENCED_2PARAMETER(_p, _q)
Definition: ixgbe_osdep.h:127
msec_delay
#define msec_delay(x)
Definition: ixgbe_osdep.h:72
IXGBE_READ_REG
#define IXGBE_READ_REG(a, reg)
Definition: ixgbe_osdep.h:224
ERROR_REPORT3
#define ERROR_REPORT3(S, A, B, C)
Definition: ixgbe_osdep.h:115
IXGBE_LE32_TO_CPUS
#define IXGBE_LE32_TO_CPUS(x)
Definition: ixgbe_osdep.h:138
IXGBE_READ_PCIE_WORD
#define IXGBE_READ_PCIE_WORD
Definition: ixgbe_osdep.h:216
DEBUGOUT
#define DEBUGOUT(S)
Definition: ixgbe_osdep.h:104
IXGBE_READ_REG_ARRAY
#define IXGBE_READ_REG_ARRAY(a, reg, offset)
Definition: ixgbe_osdep.h:230
usec_delay
#define usec_delay(x)
Definition: ixgbe_osdep.h:71
DEBUGOUT2
#define DEBUGOUT2(S, A, B)
Definition: ixgbe_osdep.h:106
IXGBE_WRITE_REG_ARRAY
#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, val)
Definition: ixgbe_osdep.h:234
IXGBE_CPU_TO_LE32
#define IXGBE_CPU_TO_LE32
Definition: ixgbe_osdep.h:136
DEBUGOUT6
#define DEBUGOUT6(S, A, B, C, D, E, F)
Definition: ixgbe_osdep.h:110
DEBUGOUT3
#define DEBUGOUT3(S, A, B, C)
Definition: ixgbe_osdep.h:107
ERROR_REPORT1
#define ERROR_REPORT1(S, A)
Definition: ixgbe_osdep.h:113
u8
uint8_t u8
Definition: ixgbe_osdep.h:143
DEBUGFUNC
#define DEBUGFUNC(F)
Definition: ixgbe_osdep.h:76
s16
int16_t s16
Definition: ixgbe_osdep.h:146
DEBUGOUT1
#define DEBUGOUT1(S, A)
Definition: ixgbe_osdep.h:105
UNREFERENCED_1PARAMETER
#define UNREFERENCED_1PARAMETER(_p)
Definition: ixgbe_osdep.h:126
IXGBE_WRITE_FLUSH
#define IXGBE_WRITE_FLUSH(a)
Definition: ixgbe_osdep.h:221
IXGBE_WRITE_REG
#define IXGBE_WRITE_REG(a, reg, val)
Definition: ixgbe_osdep.h:227
ASSERT
#define ASSERT(x)
Definition: ixgbe_osdep.h:58
u16
uint16_t u16
Definition: ixgbe_osdep.h:145
ERROR_REPORT2
#define ERROR_REPORT2(S, A, B)
Definition: ixgbe_osdep.h:114
IXGBE_ERROR_CAUTION
@ IXGBE_ERROR_CAUTION
Definition: ixgbe_osdep.h:67
IXGBE_ERROR_POLLING
@ IXGBE_ERROR_POLLING
Definition: ixgbe_osdep.h:63
IXGBE_ERROR_INVALID_STATE
@ IXGBE_ERROR_INVALID_STATE
Definition: ixgbe_osdep.h:64
IXGBE_ERROR_SOFTWARE
@ IXGBE_ERROR_SOFTWARE
Definition: ixgbe_osdep.h:62
IXGBE_ERROR_ARGUMENT
@ IXGBE_ERROR_ARGUMENT
Definition: ixgbe_osdep.h:66
IXGBE_ERROR_UNSUPPORTED
@ IXGBE_ERROR_UNSUPPORTED
Definition: ixgbe_osdep.h:65
s32
int32_t s32
Definition: ixgbe_osdep.h:148
u32
uint32_t u32
Definition: ixgbe_osdep.h:147
ixgbe_phy.h
IXGBE_SFF_SFF_8472_OSCB
#define IXGBE_SFF_SFF_8472_OSCB
Definition: ixgbe_phy.h:56
IXGBE_SFF_SOFT_RS_SELECT_10G
#define IXGBE_SFF_SOFT_RS_SELECT_10G
Definition: ixgbe_phy.h:78
IXGBE_TAF_ASM_PAUSE
#define IXGBE_TAF_ASM_PAUSE
Definition: ixgbe_phy.h:125
IXGBE_SFF_SFF_8472_ESCB
#define IXGBE_SFF_SFF_8472_ESCB
Definition: ixgbe_phy.h:57
IXGBE_I2C_EEPROM_DEV_ADDR2
#define IXGBE_I2C_EEPROM_DEV_ADDR2
Definition: ixgbe_phy.h:41
IXGBE_TAF_SYM_PAUSE
#define IXGBE_TAF_SYM_PAUSE
Definition: ixgbe_phy.h:124
IXGBE_SFF_SOFT_RS_SELECT_1G
#define IXGBE_SFF_SOFT_RS_SELECT_1G
Definition: ixgbe_phy.h:79
IXGBE_DEV_ID_X540T1
#define IXGBE_DEV_ID_X540T1
Definition: ixgbe_type.h:133
IXGBE_PTC1522
#define IXGBE_PTC1522
Definition: ixgbe_type.h:1034
IXGBE_PCIDEVCTRL2_1_2ms
#define IXGBE_PCIDEVCTRL2_1_2ms
Definition: ixgbe_type.h:2534
BYPASS_WE
#define BYPASS_WE
Definition: ixgbe_type.h:4282
IXGBE_EEC_GNT
#define IXGBE_EEC_GNT
Definition: ixgbe_type.h:2328
FW_CEM_RESP_STATUS_SUCCESS
#define FW_CEM_RESP_STATUS_SUCCESS
Definition: ixgbe_type.h:3093
ixgbe_mac_X550
@ ixgbe_mac_X550
Definition: ixgbe_type.h:3679
ixgbe_mac_82598EB
@ ixgbe_mac_82598EB
Definition: ixgbe_type.h:3674
ixgbe_mac_X540
@ ixgbe_mac_X540
Definition: ixgbe_type.h:3677
ixgbe_mac_X550EM_a
@ ixgbe_mac_X550EM_a
Definition: ixgbe_type.h:3681
ixgbe_mac_X550EM_x
@ ixgbe_mac_X550EM_x
Definition: ixgbe_type.h:3680
ixgbe_mac_82599EB
@ ixgbe_mac_82599EB
Definition: ixgbe_type.h:3675
IXGBE_LED_BLINK
#define IXGBE_LED_BLINK(_i)
Definition: ixgbe_type.h:2165
IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
Definition: ixgbe_type.h:2493
IXGBE_EERD_EEWR_ATTEMPTS
#define IXGBE_EERD_EEWR_ATTEMPTS
Definition: ixgbe_type.h:2453
IXGBE_EE_CTRL_4_INST_ID_SHIFT
#define IXGBE_EE_CTRL_4_INST_ID_SHIFT
Definition: ixgbe_type.h:2355
IXGBE_DEV_ID_X550EM_A_SFP
#define IXGBE_DEV_ID_X550EM_A_SFP
Definition: ixgbe_type.h:144
IXGBE_NVM_POLL_READ
#define IXGBE_NVM_POLL_READ
Definition: ixgbe_type.h:2434
IXGBE_GPRC
#define IXGBE_GPRC
Definition: ixgbe_type.h:1009
IXGBE_GCR_EXT
#define IXGBE_GCR_EXT
Definition: ixgbe_type.h:1204
IXGBE_ESDP_SDP0
#define IXGBE_ESDP_SDP0
Definition: ixgbe_type.h:2138
NVM_OROM_SHIFT
#define NVM_OROM_SHIFT
Definition: ixgbe_type.h:313
NVM_OEM_PROD_VER_CAP_MASK
#define NVM_OEM_PROD_VER_CAP_MASK
Definition: ixgbe_type.h:321
IXGBE_ERR_SWFW_SYNC
#define IXGBE_ERR_SWFW_SYNC
Definition: ixgbe_type.h:4250
IXGBE_RXCTRL_RXEN
#define IXGBE_RXCTRL_RXEN
Definition: ixgbe_type.h:2592
IXGBE_TPT
#define IXGBE_TPT
Definition: ixgbe_type.h:1028
IXGBE_ERR_INVALID_MAC_ADDR
#define IXGBE_ERR_INVALID_MAC_ADDR
Definition: ixgbe_type.h:4244
NVM_ETK_SHIFT
#define NVM_ETK_SHIFT
Definition: ixgbe_type.h:325
IXGBE_PCS1GANA
#define IXGBE_PCS1GANA
Definition: ixgbe_type.h:1364
IXGBE_RXDCTL
#define IXGBE_RXDCTL(_i)
Definition: ixgbe_type.h:408
IXGBE_EEPROM_STATUS_RDY_SPI
#define IXGBE_EEPROM_STATUS_RDY_SPI
Definition: ixgbe_type.h:2415
IXGBE_LEDCTL
#define IXGBE_LEDCTL
Definition: ixgbe_type.h:182
NVM_INVALID_PTR
#define NVM_INVALID_PTR
Definition: ixgbe_type.h:328
NVM_ETK_VALID
#define NVM_ETK_VALID
Definition: ixgbe_type.h:327
IXGBE_MNGPRC
#define IXGBE_MNGPRC
Definition: ixgbe_type.h:1022
IXGBE_EEPROM_A8_OPCODE_SPI
#define IXGBE_EEPROM_A8_OPCODE_SPI
Definition: ixgbe_type.h:2418
IXGBE_PRC64
#define IXGBE_PRC64
Definition: ixgbe_type.h:1003
IXGBE_MFLCN
#define IXGBE_MFLCN
Definition: ixgbe_type.h:1384
IXGBE_STATUS_LAN_ID_SHIFT
#define IXGBE_STATUS_LAN_ID_SHIFT
Definition: ixgbe_type.h:2131
IXGBE_LINKS_KX_AN_COMP
#define IXGBE_LINKS_KX_AN_COMP
Definition: ixgbe_type.h:2242
IXGBE_SWSM_BY_MAC
#define IXGBE_SWSM_BY_MAC(_hw)
Definition: ixgbe_type.h:1182
IXGBE_EE_CTRL_4_INST_ID
#define IXGBE_EE_CTRL_4_INST_ID
Definition: ixgbe_type.h:2354
IXGBE_MFLCN_RPFCE_MASK
#define IXGBE_MFLCN_RPFCE_MASK
Definition: ixgbe_type.h:2666
IXGBE_PCS1GLSTA
#define IXGBE_PCS1GLSTA
Definition: ixgbe_type.h:1361
IXGBE_RXPBSIZE_SHIFT
#define IXGBE_RXPBSIZE_SHIFT
Definition: ixgbe_type.h:439
IXGBE_LXOFFRXCNT
#define IXGBE_LXOFFRXCNT
Definition: ixgbe_type.h:995
IXGBE_RJC
#define IXGBE_RJC
Definition: ixgbe_type.h:1021
IXGBE_RXCTRL
#define IXGBE_RXCTRL
Definition: ixgbe_type.h:437
IXGBE_MTA
#define IXGBE_MTA(_i)
Definition: ixgbe_type.h:450
IXGBE_SECRXSTAT_SECRX_RDY
#define IXGBE_SECRXSTAT_SECRX_RDY
Definition: ixgbe_type.h:791
IXGBE_ETS_DATA_INDEX_MASK
#define IXGBE_ETS_DATA_INDEX_MASK
Definition: ixgbe_type.h:2391
IXGBE_SAN_MAC_ADDR_PTR
#define IXGBE_SAN_MAC_ADDR_PTR
Definition: ixgbe_type.h:2395
IXGBE_LXONTXC
#define IXGBE_LXONTXC
Definition: ixgbe_type.h:990
IXGBE_EEPROM_READ_OPCODE_SPI
#define IXGBE_EEPROM_READ_OPCODE_SPI
Definition: ixgbe_type.h:2416
IXGBE_STATUS_LAN_ID
#define IXGBE_STATUS_LAN_ID
Definition: ixgbe_type.h:2130
IXGBE_DEV_ID_X550EM_A_QSFP
#define IXGBE_DEV_ID_X550EM_A_QSFP
Definition: ixgbe_type.h:142
IXGBE_PTC255
#define IXGBE_PTC255
Definition: ixgbe_type.h:1031
IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
Definition: ixgbe_type.h:2463
IXGBE_ETS_TYPE_MASK
#define IXGBE_ETS_TYPE_MASK
Definition: ixgbe_type.h:2385
IXGBE_PCIE_MSIX_TBL_SZ_MASK
#define IXGBE_PCIE_MSIX_TBL_SZ_MASK
Definition: ixgbe_type.h:2406
IXGBE_ISCSI_FCOE_BLK_PTR
#define IXGBE_ISCSI_FCOE_BLK_PTR
Definition: ixgbe_type.h:2485
IXGBE_ESDP_SDP2
#define IXGBE_ESDP_SDP2
Definition: ixgbe_type.h:2140
IXGBE_HI_COMMAND_TIMEOUT
#define IXGBE_HI_COMMAND_TIMEOUT
Definition: ixgbe_type.h:3080
ixgbe_bus_type_pci_express
@ ixgbe_bus_type_pci_express
Definition: ixgbe_type.h:3786
ixgbe_bus_type_unknown
@ ixgbe_bus_type_unknown
Definition: ixgbe_type.h:3783
IXGBE_PXOFFTXC
#define IXGBE_PXOFFTXC(_i)
Definition: ixgbe_type.h:1001
IXGBE_RAH_AV
#define IXGBE_RAH_AV
Definition: ixgbe_type.h:2557
BYPASS_CTL1_TIME_M
#define BYPASS_CTL1_TIME_M
Definition: ixgbe_type.h:4327
IXGBE_MANC_RCV_TCO_EN
#define IXGBE_MANC_RCV_TCO_EN
Definition: ixgbe_type.h:1100
IXGBE_MFLCN_DPF
#define IXGBE_MFLCN_DPF
Definition: ixgbe_type.h:2663
IXGBE_LDPCECL
#define IXGBE_LDPCECL
Definition: ixgbe_type.h:1652
IXGBE_PRC255
#define IXGBE_PRC255
Definition: ixgbe_type.h:1005
BYPASS_MAIN_ON_M
#define BYPASS_MAIN_ON_M
Definition: ixgbe_type.h:4300
IXGBE_DEV_ID_82599_T3_LOM
#define IXGBE_DEV_ID_82599_T3_LOM
Definition: ixgbe_type.h:125
IXGBE_PCIDEVCTRL2_16_32ms
#define IXGBE_PCIDEVCTRL2_16_32ms
Definition: ixgbe_type.h:2535
IXGBE_ETS_DATA_LOC_MASK
#define IXGBE_ETS_DATA_LOC_MASK
Definition: ixgbe_type.h:2389
IXGBE_DEV_ID_X550EM_A_1G_T_L
#define IXGBE_DEV_ID_X550EM_A_1G_T_L
Definition: ixgbe_type.h:146
IXGBE_RFC
#define IXGBE_RFC
Definition: ixgbe_type.h:1019
IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
Definition: ixgbe_type.h:2495
IXGBE_PCIDEVCTRL2_260_520ms
#define IXGBE_PCIDEVCTRL2_260_520ms
Definition: ixgbe_type.h:2537
IXGBE_FCRTH_FCEN
#define IXGBE_FCRTH_FCEN
Definition: ixgbe_type.h:1886
IXGBE_ROC
#define IXGBE_ROC
Definition: ixgbe_type.h:1020
IXGBE_HICR_C
#define IXGBE_HICR_C
Definition: ixgbe_type.h:1125
IXGBE_EEPROM_RW_ADDR_SHIFT
#define IXGBE_EEPROM_RW_ADDR_SHIFT
Definition: ixgbe_type.h:2432
IXGBE_MNGPTC
#define IXGBE_MNGPTC
Definition: ixgbe_type.h:1024
IXGBE_AUTOC_SYM_PAUSE
#define IXGBE_AUTOC_SYM_PAUSE
Definition: ixgbe_type.h:2187
IXGBE_ESDP_SDP7
#define IXGBE_ESDP_SDP7
Definition: ixgbe_type.h:2145
IXGBE_FWSM_MODE_MASK
#define IXGBE_FWSM_MODE_MASK
Definition: ixgbe_type.h:1105
IXGBE_PRC511
#define IXGBE_PRC511
Definition: ixgbe_type.h:1006
IXGBE_ESDP_SDP1
#define IXGBE_ESDP_SDP1
Definition: ixgbe_type.h:2139
IXGBE_GORCL
#define IXGBE_GORCL
Definition: ixgbe_type.h:1013
IXGBE_TXDCTL_SWFLSH
#define IXGBE_TXDCTL_SWFLSH
Definition: ixgbe_type.h:2580
IXGBE_DCB_MAX_TRAFFIC_CLASS
#define IXGBE_DCB_MAX_TRAFFIC_CLASS
Definition: ixgbe_type.h:709
IXGBE_PXONRXCNT
#define IXGBE_PXONRXCNT(_i)
Definition: ixgbe_type.h:996
IXGBE_VLVF_VIEN
#define IXGBE_VLVF_VIEN
Definition: ixgbe_type.h:2120
IXGBE_DEV_ID_X550EM_X_10G_T
#define IXGBE_DEV_ID_X550EM_X_10G_T
Definition: ixgbe_type.h:150
IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
Definition: ixgbe_type.h:2492
IXGBE_MAX_SENSORS
#define IXGBE_MAX_SENSORS
Definition: ixgbe_type.h:295
IXGBE_FACTPS_BY_MAC
#define IXGBE_FACTPS_BY_MAC(_hw)
Definition: ixgbe_type.h:1174
IXGBE_FACTPS_MNGCG
#define IXGBE_FACTPS_MNGCG
Definition: ixgbe_type.h:1491
IXGBE_ETS_CFG
#define IXGBE_ETS_CFG
Definition: ixgbe_type.h:2382
IXGBE_LINKS_SPEED_10G_82599
#define IXGBE_LINKS_SPEED_10G_82599
Definition: ixgbe_type.h:2261
BYPASS_CTL2_OFFSET_M
#define BYPASS_CTL2_OFFSET_M
Definition: ixgbe_type.h:4337
FW_CEM_MAX_RETRIES
#define FW_CEM_MAX_RETRIES
Definition: ixgbe_type.h:3092
IXGBE_PCS1GANLP
#define IXGBE_PCS1GANLP
Definition: ixgbe_type.h:1365
IXGBE_PCIE_ANALOG_PTR
#define IXGBE_PCIE_ANALOG_PTR
Definition: ixgbe_type.h:2356
IXGBE_FACTPS_LFS
#define IXGBE_FACTPS_LFS
Definition: ixgbe_type.h:1492
IXGBE_EEPROM_GRANT_ATTEMPTS
#define IXGBE_EEPROM_GRANT_ATTEMPTS
Definition: ixgbe_type.h:2449
IXGBE_EEPROM_MAX_RETRY_SPI
#define IXGBE_EEPROM_MAX_RETRY_SPI
Definition: ixgbe_type.h:2414
IXGBE_PBANUM1_PTR
#define IXGBE_PBANUM1_PTR
Definition: ixgbe_type.h:2377
IXGBE_QBRC_L
#define IXGBE_QBRC_L(_i)
Definition: ixgbe_type.h:1049
IXGBE_DCA_RXCTRL_HEAD_WRO_EN
#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN
Definition: ixgbe_type.h:1519
IXGBE_STATUS_LAN_ID_1
#define IXGBE_STATUS_LAN_ID_1
Definition: ixgbe_type.h:2135
NVM_ETK_OFF_HI
#define NVM_ETK_OFF_HI
Definition: ixgbe_type.h:324
IXGBE_BPRC
#define IXGBE_BPRC
Definition: ixgbe_type.h:1010
IXGBE_PCRC8ECL
#define IXGBE_PCRC8ECL
Definition: ixgbe_type.h:1649
IXGBE_LINK_SPEED_5GB_FULL
#define IXGBE_LINK_SPEED_5GB_FULL
Definition: ixgbe_type.h:3449
IXGBE_PCI_LINK_WIDTH
#define IXGBE_PCI_LINK_WIDTH
Definition: ixgbe_type.h:2518
ixgbe_link_speed
u32 ixgbe_link_speed
Definition: ixgbe_type.h:3443
IXGBE_PCI_LINK_SPEED_2500
#define IXGBE_PCI_LINK_SPEED_2500
Definition: ixgbe_type.h:2524
IXGBE_LED_MODE_SHIFT
#define IXGBE_LED_MODE_SHIFT(_i)
Definition: ixgbe_type.h:2163
IXGBE_PTC511
#define IXGBE_PTC511
Definition: ixgbe_type.h:1032
IXGBE_VLVF_ENTRIES
#define IXGBE_VLVF_ENTRIES
Definition: ixgbe_type.h:2121
BYPASS_CTL2_OFFSET_SHIFT
#define BYPASS_CTL2_OFFSET_SHIFT
Definition: ixgbe_type.h:4341
IXGBE_FCRTH_82599
#define IXGBE_FCRTH_82599(_i)
Definition: ixgbe_type.h:387
IXGBE_MPSAR_LO
#define IXGBE_MPSAR_LO(_i)
Definition: ixgbe_type.h:455
NVM_VER_MASK
#define NVM_VER_MASK
Definition: ixgbe_type.h:315
IXGBE_ANLP1
#define IXGBE_ANLP1
Definition: ixgbe_type.h:1393
IXGBE_ERR_EEPROM
#define IXGBE_ERR_EEPROM
Definition: ixgbe_type.h:4235
IXGBE_ERR_CONFIG
#define IXGBE_ERR_CONFIG
Definition: ixgbe_type.h:4238
IXGBE_LED_LINK_ACTIVE
#define IXGBE_LED_LINK_ACTIVE
Definition: ixgbe_type.h:2176
IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
Definition: ixgbe_type.h:4112
IXGBE_DEV_ID_X540T
#define IXGBE_DEV_ID_X540T
Definition: ixgbe_type.h:129
IXGBE_SUCCESS
#define IXGBE_SUCCESS
Definition: ixgbe_type.h:4234
IXGBE_PCI_LINK_WIDTH_4
#define IXGBE_PCI_LINK_WIDTH_4
Definition: ixgbe_type.h:2521
IXGBE_ILLERRC
#define IXGBE_ILLERRC
Definition: ixgbe_type.h:983
ixgbe_bus_speed_8000
@ ixgbe_bus_speed_8000
Definition: ixgbe_type.h:3801
ixgbe_bus_speed_unknown
@ ixgbe_bus_speed_unknown
Definition: ixgbe_type.h:3793
ixgbe_bus_speed_2500
@ ixgbe_bus_speed_2500
Definition: ixgbe_type.h:3799
ixgbe_bus_speed_5000
@ ixgbe_bus_speed_5000
Definition: ixgbe_type.h:3800
IXGBE_MPRC
#define IXGBE_MPRC
Definition: ixgbe_type.h:1011
IXGBE_ISCSI_FCOE_FLAGS_OFFSET
#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET
Definition: ixgbe_type.h:2486
IXGBE_TXPBSIZE_MAX
#define IXGBE_TXPBSIZE_MAX
Definition: ixgbe_type.h:1764
IXGBE_RXPBSIZE
#define IXGBE_RXPBSIZE(_i)
Definition: ixgbe_type.h:436
IXGBE_RAH
#define IXGBE_RAH(_i)
Definition: ixgbe_type.h:453
ixgbe_mc_addr_itr
u8 *(* ixgbe_mc_addr_itr)(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
Definition: ixgbe_type.h:3933
IXGBE_RNBC
#define IXGBE_RNBC(_i)
Definition: ixgbe_type.h:1017
IXGBE_ERR_HOST_INTERFACE_COMMAND
#define IXGBE_ERR_HOST_INTERFACE_COMMAND
Definition: ixgbe_type.h:4266
IXGBE_FWSTS
#define IXGBE_FWSTS
Definition: ixgbe_type.h:1114
IXGBE_DEV_ID_X540_BYPASS
#define IXGBE_DEV_ID_X540_BYPASS
Definition: ixgbe_type.h:132
IXGBE_PTC127
#define IXGBE_PTC127
Definition: ixgbe_type.h:1030
IXGBE_ERR_NO_SAN_ADDR_PTR
#define IXGBE_ERR_NO_SAN_ADDR_PTR
Definition: ixgbe_type.h:4256
IXGBE_LED_MODE_MASK_BASE
#define IXGBE_LED_MODE_MASK_BASE
Definition: ixgbe_type.h:2161
IXGBE_VLVFB
#define IXGBE_VLVFB(_i)
Definition: ixgbe_type.h:478
IXGBE_TXPBSIZE
#define IXGBE_TXPBSIZE(_i)
Definition: ixgbe_type.h:593
IXGBE_LINK_SPEED_UNKNOWN
#define IXGBE_LINK_SPEED_UNKNOWN
Definition: ixgbe_type.h:3444
IXGBE_LXONRXC
#define IXGBE_LXONRXC
Definition: ixgbe_type.h:991
IXGBE_SWSM
#define IXGBE_SWSM
Definition: ixgbe_type.h:1177
IXGBE_ERR_INVALID_LINK_SETTINGS
#define IXGBE_ERR_INVALID_LINK_SETTINGS
Definition: ixgbe_type.h:4247
IXGBE_DEV_ID_X550EM_A_1G_T
#define IXGBE_DEV_ID_X550EM_A_1G_T
Definition: ixgbe_type.h:145
IXGBE_PCIE_MSIX_82598_CAPS
#define IXGBE_PCIE_MSIX_82598_CAPS
Definition: ixgbe_type.h:2402
IXGBE_PXON2OFFCNT
#define IXGBE_PXON2OFFCNT(_i)
Definition: ixgbe_type.h:998
IXGBE_LINKS_SPEED_1G_82599
#define IXGBE_LINKS_SPEED_1G_82599
Definition: ixgbe_type.h:2262
IXGBE_QBRC
#define IXGBE_QBRC(_i)
Definition: ixgbe_type.h:1047
IXGBE_CTRL_GIO_DIS
#define IXGBE_CTRL_GIO_DIS
Definition: ixgbe_type.h:1485
IXGBE_ETS_LTHRES_DELTA_MASK
#define IXGBE_ETS_LTHRES_DELTA_MASK
Definition: ixgbe_type.h:2383
NVM_OEM_PROD_VER_MOD_LEN
#define NVM_OEM_PROD_VER_MOD_LEN
Definition: ixgbe_type.h:322
IXGBE_MRFC
#define IXGBE_MRFC
Definition: ixgbe_type.h:988
IXGBE_PCIDEVCTRL2_4_8s
#define IXGBE_PCIDEVCTRL2_4_8s
Definition: ixgbe_type.h:2539
IXGBE_AUTOC_ASM_PAUSE
#define IXGBE_AUTOC_ASM_PAUSE
Definition: ixgbe_type.h:2186
IXGBE_FCTTV
#define IXGBE_FCTTV(_i)
Definition: ixgbe_type.h:390
IXGBE_VT_CTL_VT_ENABLE
#define IXGBE_VT_CTL_VT_ENABLE
Definition: ixgbe_type.h:1819
IXGBE_LINKS_SPEED_10_X550EM_A
#define IXGBE_LINKS_SPEED_10_X550EM_A
Definition: ixgbe_type.h:2264
IXGBE_PCRC8ECH
#define IXGBE_PCRC8ECH
Definition: ixgbe_type.h:1650
IXGBE_LDPCECH
#define IXGBE_LDPCECH
Definition: ixgbe_type.h:1653
IXGBE_NOT_IMPLEMENTED
#define IXGBE_NOT_IMPLEMENTED
Definition: ixgbe_type.h:4275
IXGBE_BPTC
#define IXGBE_BPTC
Definition: ixgbe_type.h:1036
ixgbe_eeprom_spi
@ ixgbe_eeprom_spi
Definition: ixgbe_type.h:3667
ixgbe_eeprom_none
@ ixgbe_eeprom_none
Definition: ixgbe_type.h:3669
ixgbe_eeprom_uninitialized
@ ixgbe_eeprom_uninitialized
Definition: ixgbe_type.h:3666
BYPASS_PAGE_M
#define BYPASS_PAGE_M
Definition: ixgbe_type.h:4281
IXGBE_ETS_DATA_LOC_SHIFT
#define IXGBE_ETS_DATA_LOC_SHIFT
Definition: ixgbe_type.h:2390
NVM_VER_SHIFT
#define NVM_VER_SHIFT
Definition: ixgbe_type.h:316
IXGBE_PCS1GLSTA_AN_COMPLETE
#define IXGBE_PCS1GLSTA_AN_COMPLETE
Definition: ixgbe_type.h:2273
IXGBE_TORH
#define IXGBE_TORH
Definition: ixgbe_type.h:1026
IXGBE_EICR
#define IXGBE_EICR
Definition: ixgbe_type.h:350
IXGBE_MPC
#define IXGBE_MPC(_i)
Definition: ixgbe_type.h:986
IXGBE_EEC_PRES
#define IXGBE_EEC_PRES
Definition: ixgbe_type.h:2329
IXGBE_PCI_LINK_SPEED_8000
#define IXGBE_PCI_LINK_SPEED_8000
Definition: ixgbe_type.h:2526
IXGBE_VT_CTL
#define IXGBE_VT_CTL
Definition: ixgbe_type.h:482
IXGBE_TXPBTHRESH
#define IXGBE_TXPBTHRESH(_i)
Definition: ixgbe_type.h:570
IXGBE_FCOE_IBA_CAPS_FCOE
#define IXGBE_FCOE_IBA_CAPS_FCOE
Definition: ixgbe_type.h:2484
IXGBE_DEV_ID_X550EM_A_SFP_N
#define IXGBE_DEV_ID_X550EM_A_SFP_N
Definition: ixgbe_type.h:138
IXGBE_TPR
#define IXGBE_TPR
Definition: ixgbe_type.h:1027
IXGBE_EEPROM_RW_REG_DATA
#define IXGBE_EEPROM_RW_REG_DATA
Definition: ixgbe_type.h:2429
IXGBE_VLVF
#define IXGBE_VLVF(_i)
Definition: ixgbe_type.h:477
NVM_VER_INVALID
#define NVM_VER_INVALID
Definition: ixgbe_type.h:326
BYPASS_MAIN_OFF_M
#define BYPASS_MAIN_OFF_M
Definition: ixgbe_type.h:4301
NVM_OEM_PROD_VER_OFF_H
#define NVM_OEM_PROD_VER_OFF_H
Definition: ixgbe_type.h:320
IXGBE_SECRXCTRL
#define IXGBE_SECRXCTRL
Definition: ixgbe_type.h:777
IXGBE_GSSR_EEP_SM
#define IXGBE_GSSR_EEP_SM
Definition: ixgbe_type.h:2303
IXGBE_LINKS_SPEED_82599
#define IXGBE_LINKS_SPEED_82599
Definition: ixgbe_type.h:2260
IXGBE_CTRL_EXT
#define IXGBE_CTRL_EXT
Definition: ixgbe_type.h:167
IXGBE_PBANUM_PTR_GUARD
#define IXGBE_PBANUM_PTR_GUARD
Definition: ixgbe_type.h:2350
IXGBE_ETS_TYPE_EMC
#define IXGBE_ETS_TYPE_EMC
Definition: ixgbe_type.h:2387
IXGBE_PCI_MASTER_DISABLE_TIMEOUT
#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT
Definition: ixgbe_type.h:2543
IXGBE_SECRXSTAT
#define IXGBE_SECRXSTAT
Definition: ixgbe_type.h:778
IXGBE_ESDP_SDP0_DIR
#define IXGBE_ESDP_SDP0_DIR
Definition: ixgbe_type.h:2146
IXGBE_SWSM_SMBI
#define IXGBE_SWSM_SMBI
Definition: ixgbe_type.h:2297
IXGBE_QBTC_H
#define IXGBE_QBTC_H(_i)
Definition: ixgbe_type.h:1053
ixgbe_media_type_copper
@ ixgbe_media_type_copper
Definition: ixgbe_type.h:3758
ixgbe_media_type_fiber_qsfp
@ ixgbe_media_type_fiber_qsfp
Definition: ixgbe_type.h:3757
ixgbe_media_type_fiber
@ ixgbe_media_type_fiber
Definition: ixgbe_type.h:3755
ixgbe_media_type_backplane
@ ixgbe_media_type_backplane
Definition: ixgbe_type.h:3759
ixgbe_media_type_fiber_fixed
@ ixgbe_media_type_fiber_fixed
Definition: ixgbe_type.h:3756
IXGBE_EERD
#define IXGBE_EERD
Definition: ixgbe_type.h:196
IXGBE_LXOFFRXC
#define IXGBE_LXOFFRXC
Definition: ixgbe_type.h:993
IXGBE_RTRUP2TC
#define IXGBE_RTRUP2TC
Definition: ixgbe_type.h:874
IXGBE_RTTDQSEL
#define IXGBE_RTTDQSEL
Definition: ixgbe_type.h:883
IXGBE_HOST_INTERFACE_MASK_CMD
#define IXGBE_HOST_INTERFACE_MASK_CMD
Definition: ixgbe_type.h:4495
IXGBE_STATUS_GIO
#define IXGBE_STATUS_GIO
Definition: ixgbe_type.h:2132
IXGBE_LINKS_SPEED_NON_STD
#define IXGBE_LINKS_SPEED_NON_STD
Definition: ixgbe_type.h:2259
IXGBE_TORL
#define IXGBE_TORL
Definition: ixgbe_type.h:1025
IXGBE_ANLP1_ASM_PAUSE
#define IXGBE_ANLP1_ASM_PAUSE
Definition: ixgbe_type.h:2293
IXGBE_DCA_RXCTRL
#define IXGBE_DCA_RXCTRL(_i)
Definition: ixgbe_type.h:431
IXGBE_PXOFFRXC
#define IXGBE_PXOFFRXC(_i)
Definition: ixgbe_type.h:1002
IXGBE_MNGPDC
#define IXGBE_MNGPDC
Definition: ixgbe_type.h:1023
IXGBE_EEPROM_WORD_SIZE_SHIFT
#define IXGBE_EEPROM_WORD_SIZE_SHIFT
Definition: ixgbe_type.h:2340
IXGBE_MSPDC
#define IXGBE_MSPDC
Definition: ixgbe_type.h:985
IXGBE_BYPASS_FW_WRITE_FAILURE
#define IXGBE_BYPASS_FW_WRITE_FAILURE
Definition: ixgbe_type.h:4268
IXGBE_GSSR_SW_MNG_SM
#define IXGBE_GSSR_SW_MNG_SM
Definition: ixgbe_type.h:2309
IXGBE_RXDCTL_SWFLSH
#define IXGBE_RXDCTL_SWFLSH
Definition: ixgbe_type.h:2595
IXGBE_FCTRL
#define IXGBE_FCTRL
Definition: ixgbe_type.h:464
IXGBE_EIMC
#define IXGBE_EIMC
Definition: ixgbe_type.h:353
IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD
#define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD
Definition: ixgbe_type.h:4494
IXGBE_ETS_NUM_SENSORS_MASK
#define IXGBE_ETS_NUM_SENSORS_MASK
Definition: ixgbe_type.h:2388
IXGBE_PCIDEVCTRL2_1_2s
#define IXGBE_PCIDEVCTRL2_1_2s
Definition: ixgbe_type.h:2538
IXGBE_AUTOC_AN_RESTART
#define IXGBE_AUTOC_AN_RESTART
Definition: ixgbe_type.h:2196
IXGBE_IS_BROADCAST
#define IXGBE_IS_BROADCAST(Address)
Definition: ixgbe_type.h:2550
IXGBE_EEC_SK
#define IXGBE_EEC_SK
Definition: ixgbe_type.h:2319
IXGBE_MANC
#define IXGBE_MANC
Definition: ixgbe_type.h:1082
IXGBE_GCR_EXT_BUFFERS_CLEAR
#define IXGBE_GCR_EXT_BUFFERS_CLEAR
Definition: ixgbe_type.h:1260
IXGBE_LINK_SPEED_10_FULL
#define IXGBE_LINK_SPEED_10_FULL
Definition: ixgbe_type.h:3445
IXGBE_ERR_FC_NOT_NEGOTIATED
#define IXGBE_ERR_FC_NOT_NEGOTIATED
Definition: ixgbe_type.h:4261
IXGBE_PCI_LINK_STATUS
#define IXGBE_PCI_LINK_STATUS
Definition: ixgbe_type.h:2516
NVM_OEM_PROD_VER_OFF_L
#define NVM_OEM_PROD_VER_OFF_L
Definition: ixgbe_type.h:319
IXGBE_PCIDEVCTRL2_65_130ms
#define IXGBE_PCIDEVCTRL2_65_130ms
Definition: ixgbe_type.h:2536
IXGBE_DEV_ID_X550T
#define IXGBE_DEV_ID_X550T
Definition: ixgbe_type.h:134
IXGBE_ISCSI_FCOE_FLAGS_ENABLE
#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE
Definition: ixgbe_type.h:2487
IXGBE_PCS1GANA_SYM_PAUSE
#define IXGBE_PCS1GANA_SYM_PAUSE
Definition: ixgbe_type.h:2279
IXGBE_MPSAR_HI
#define IXGBE_MPSAR_HI(_i)
Definition: ixgbe_type.h:456
IXGBE_LED_ON
#define IXGBE_LED_ON
Definition: ixgbe_type.h:2178
BYPASS_PAGE_CTL0
#define BYPASS_PAGE_CTL0
Definition: ixgbe_type.h:4278
IXGBE_HOST_INTERFACE_FLASH_READ_CMD
#define IXGBE_HOST_INTERFACE_FLASH_READ_CMD
Definition: ixgbe_type.h:4486
IXGBE_DEV_ID_X550T1
#define IXGBE_DEV_ID_X550T1
Definition: ixgbe_type.h:135
IXGBE_PTC64
#define IXGBE_PTC64
Definition: ixgbe_type.h:1029
IXGBE_EEPROM_SUM
#define IXGBE_EEPROM_SUM
Definition: ixgbe_type.h:2352
IXGBE_EEPROM_CTRL_4
#define IXGBE_EEPROM_CTRL_4
Definition: ixgbe_type.h:2353
IXGBE_EEC_ADDR_SIZE
#define IXGBE_EEC_ADDR_SIZE
Definition: ixgbe_type.h:2335
BYPASS_WDTIMEOUT_M
#define BYPASS_WDTIMEOUT_M
Definition: ixgbe_type.h:4303
IXGBE_PTC1023
#define IXGBE_PTC1023
Definition: ixgbe_type.h:1033
BYPASS_STATUS_OFF_M
#define BYPASS_STATUS_OFF_M
Definition: ixgbe_type.h:4298
IXGBE_QBTC
#define IXGBE_QBTC(_i)
Definition: ixgbe_type.h:1048
NVM_OEM_PROD_VER_PTR
#define NVM_OEM_PROD_VER_PTR
Definition: ixgbe_type.h:317
IXGBE_LINKS2
#define IXGBE_LINKS2
Definition: ixgbe_type.h:1390
BYPASS_AUX_ON_M
#define BYPASS_AUX_ON_M
Definition: ixgbe_type.h:4299
IXGBE_LINKS
#define IXGBE_LINKS
Definition: ixgbe_type.h:1389
IXGBE_ESDP_SDP1_DIR
#define IXGBE_ESDP_SDP1_DIR
Definition: ixgbe_type.h:2147
PBA_STRATEGY_WEIGHTED
@ PBA_STRATEGY_WEIGHTED
Definition: ixgbe_type.h:1773
PBA_STRATEGY_EQUAL
@ PBA_STRATEGY_EQUAL
Definition: ixgbe_type.h:1771
IXGBE_MLFC
#define IXGBE_MLFC
Definition: ixgbe_type.h:987
IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
Definition: ixgbe_type.h:2515
IXGBE_PXONTXC
#define IXGBE_PXONTXC(_i)
Definition: ixgbe_type.h:999
IXGBE_PCIDEVCTRL2_17_34s
#define IXGBE_PCIDEVCTRL2_17_34s
Definition: ixgbe_type.h:2540
IXGBE_SPOOF_VLANAS_SHIFT
#define IXGBE_SPOOF_VLANAS_SHIFT
Definition: ixgbe_type.h:584
IXGBE_UTA
#define IXGBE_UTA(_i)
Definition: ixgbe_type.h:494
IXGBE_EEPROM_OPCODE_BITS
#define IXGBE_EEPROM_OPCODE_BITS
Definition: ixgbe_type.h:2341
IXGBE_ESDP_SDP6_DIR
#define IXGBE_ESDP_SDP6_DIR
Definition: ixgbe_type.h:2152
IXGBE_STATUS
#define IXGBE_STATUS
Definition: ixgbe_type.h:166
IXGBE_PRC1522
#define IXGBE_PRC1522
Definition: ixgbe_type.h:1008
IXGBE_GOTCH
#define IXGBE_GOTCH
Definition: ixgbe_type.h:1016
IXGBE_IS_MULTICAST
#define IXGBE_IS_MULTICAST(Address)
Definition: ixgbe_type.h:2546
IXGBE_PCS1GANA_ASM_PAUSE
#define IXGBE_PCS1GANA_ASM_PAUSE
Definition: ixgbe_type.h:2280
IXGBE_ETS_DATA_INDEX_SHIFT
#define IXGBE_ETS_DATA_INDEX_SHIFT
Definition: ixgbe_type.h:2392
NVM_ETK_OFF_LOW
#define NVM_ETK_OFF_LOW
Definition: ixgbe_type.h:323
IXGBE_FLEX_MNG
#define IXGBE_FLEX_MNG
Definition: ixgbe_type.h:1120
IXGBE_MAX_MSIX_VECTORS_82599
#define IXGBE_MAX_MSIX_VECTORS_82599
Definition: ixgbe_type.h:2401
IXGBE_MDIO_AUTO_NEG_ADVT
#define IXGBE_MDIO_AUTO_NEG_ADVT
Definition: ixgbe_type.h:1596
IXGBE_ESDP_SDP2_DIR
#define IXGBE_ESDP_SDP2_DIR
Definition: ixgbe_type.h:2148
IXGBE_QPRDC
#define IXGBE_QPRDC(_i)
Definition: ixgbe_type.h:1051
IXGBE_TXDCTL
#define IXGBE_TXDCTL(_i)
Definition: ixgbe_type.h:558
IXGBE_PFDTXGSWC
#define IXGBE_PFDTXGSWC
Definition: ixgbe_type.h:565
IXGBE_EEPROM_WRITE_OPCODE_SPI
#define IXGBE_EEPROM_WRITE_OPCODE_SPI
Definition: ixgbe_type.h:2417
NVM_OROM_PATCH_MASK
#define NVM_OROM_PATCH_MASK
Definition: ixgbe_type.h:312
IXGBE_HLREG0
#define IXGBE_HLREG0
Definition: ixgbe_type.h:1368
IXGBE_LINK_SPEED_100_FULL
#define IXGBE_LINK_SPEED_100_FULL
Definition: ixgbe_type.h:3446
IXGBE_ETS_DATA_HTHRESH_MASK
#define IXGBE_ETS_DATA_HTHRESH_MASK
Definition: ixgbe_type.h:2393
FW_CEM_HDR_LEN
#define FW_CEM_HDR_LEN
Definition: ixgbe_type.h:3087
IXGBE_PXONRXC
#define IXGBE_PXONRXC(_i)
Definition: ixgbe_type.h:1000
IXGBE_ERR_PARAM
#define IXGBE_ERR_PARAM
Definition: ixgbe_type.h:4239
IXGBE_MDIO_AUTO_NEG_LP
#define IXGBE_MDIO_AUTO_NEG_LP
Definition: ixgbe_type.h:1597
FW_CEM_CMD_RESERVED
#define FW_CEM_CMD_RESERVED
Definition: ixgbe_type.h:3090
IXGBE_PBANUM0_PTR
#define IXGBE_PBANUM0_PTR
Definition: ixgbe_type.h:2376
IXGBE_LINKS_SPEED_100_82599
#define IXGBE_LINKS_SPEED_100_82599
Definition: ixgbe_type.h:2263
IXGBE_MFLCN_RFCE
#define IXGBE_MFLCN_RFCE
Definition: ixgbe_type.h:2665
IXGBE_HICR
#define IXGBE_HICR
Definition: ixgbe_type.h:1113
IXGBE_PXOFFRXCNT
#define IXGBE_PXOFFRXCNT(_i)
Definition: ixgbe_type.h:997
IXGBE_PCI_LINK_WIDTH_2
#define IXGBE_PCI_LINK_WIDTH_2
Definition: ixgbe_type.h:2520
IXGBE_EEC_CS
#define IXGBE_EEC_CS
Definition: ixgbe_type.h:2320
IXGBE_LED_OFF
#define IXGBE_LED_OFF
Definition: ixgbe_type.h:2179
IXGBE_ANLP1_SYM_PAUSE
#define IXGBE_ANLP1_SYM_PAUSE
Definition: ixgbe_type.h:2292
IXGBE_ERR_INVALID_ARGUMENT
#define IXGBE_ERR_INVALID_ARGUMENT
Definition: ixgbe_type.h:4265
IXGBE_ESDP_SDP7_DIR
#define IXGBE_ESDP_SDP7_DIR
Definition: ixgbe_type.h:2153
IXGBE_CRCERRS
#define IXGBE_CRCERRS
Definition: ixgbe_type.h:982
IXGBE_GPTC
#define IXGBE_GPTC
Definition: ixgbe_type.h:1012
IXGBE_MDIO_AUTO_NEG_DEV_TYPE
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE
Definition: ixgbe_type.h:1577
IXGBE_DCA_TXCTRL_82599
#define IXGBE_DCA_TXCTRL_82599(_i)
Definition: ixgbe_type.h:591
IXGBE_LXOFFTXC
#define IXGBE_LXOFFTXC
Definition: ixgbe_type.h:992
IXGBE_ESDP_SDP6
#define IXGBE_ESDP_SDP6
Definition: ixgbe_type.h:2144
IXGBE_PFVFSPOOF
#define IXGBE_PFVFSPOOF(_i)
Definition: ixgbe_type.h:564
IXGBE_LINK_SPEED_1GB_FULL
#define IXGBE_LINK_SPEED_1GB_FULL
Definition: ixgbe_type.h:3447
IXGBE_AUTOC
#define IXGBE_AUTOC
Definition: ixgbe_type.h:1388
IXGBE_PCI_LINK_SPEED
#define IXGBE_PCI_LINK_SPEED
Definition: ixgbe_type.h:2523
IXGBE_MAX_PB
#define IXGBE_MAX_PB
Definition: ixgbe_type.h:1767
IXGBE_EEC_REQ
#define IXGBE_EEC_REQ
Definition: ixgbe_type.h:2327
IXGBE_FCRTL_XONE
#define IXGBE_FCRTL_XONE
Definition: ixgbe_type.h:1885
IXGBE_ERR_PBA_SECTION
#define IXGBE_ERR_PBA_SECTION
Definition: ixgbe_type.h:4264
IXGBE_MPTC
#define IXGBE_MPTC
Definition: ixgbe_type.h:1035
IXGBE_QBRC_H
#define IXGBE_QBRC_H(_i)
Definition: ixgbe_type.h:1050
IXGBE_LINKS_UP
#define IXGBE_LINKS_UP
Definition: ixgbe_type.h:2243
IXGBE_EEC_BY_MAC
#define IXGBE_EEC_BY_MAC(_hw)
Definition: ixgbe_type.h:194
IXGBE_LINKS2_AN_SUPPORTED
#define IXGBE_LINKS2_AN_SUPPORTED
Definition: ixgbe_type.h:2268
IXGBE_EEPROM_RW_REG_START
#define IXGBE_EEPROM_RW_REG_START
Definition: ixgbe_type.h:2431
IXGBE_AUTOC_FLU
#define IXGBE_AUTOC_FLU
Definition: ixgbe_type.h:2197
IXGBE_MCSTCTRL_MFE
#define IXGBE_MCSTCTRL_MFE
Definition: ixgbe_type.h:2885
IXGBE_DCA_TXCTRL_DESC_WRO_EN
#define IXGBE_DCA_TXCTRL_DESC_WRO_EN
Definition: ixgbe_type.h:1526
IXGBE_EEPROM_WREN_OPCODE_SPI
#define IXGBE_EEPROM_WREN_OPCODE_SPI
Definition: ixgbe_type.h:2419
IXGBE_GORCH
#define IXGBE_GORCH
Definition: ixgbe_type.h:1014
IXGBE_PCIDEVCTRL2_50_100us
#define IXGBE_PCIDEVCTRL2_50_100us
Definition: ixgbe_type.h:2533
NVM_OROM_OFFSET
#define NVM_OROM_OFFSET
Definition: ixgbe_type.h:309
IXGBE_RTTBCNRC
#define IXGBE_RTTBCNRC
Definition: ixgbe_type.h:893
IXGBE_GSSR
#define IXGBE_GSSR
Definition: ixgbe_type.h:1198
IXGBE_PCI_LINK_SPEED_5000
#define IXGBE_PCI_LINK_SPEED_5000
Definition: ixgbe_type.h:2525
IXGBE_PCI_DEVICE_CONTROL2
#define IXGBE_PCI_DEVICE_CONTROL2
Definition: ixgbe_type.h:2517
IXGBE_EEPROM_CHECKSUM
#define IXGBE_EEPROM_CHECKSUM
Definition: ixgbe_type.h:2351
IXGBE_ERR_NO_SPACE
#define IXGBE_ERR_NO_SPACE
Definition: ixgbe_type.h:4259
IXGBE_LINK_SPEED_2_5GB_FULL
#define IXGBE_LINK_SPEED_2_5GB_FULL
Definition: ixgbe_type.h:3448
IXGBE_PCI_LINK_WIDTH_8
#define IXGBE_PCI_LINK_WIDTH_8
Definition: ixgbe_type.h:2522
BYPASS_PAGE_CTL1
#define BYPASS_PAGE_CTL1
Definition: ixgbe_type.h:4279
IXGBE_PCIDEVCTRL2_16_32ms_def
#define IXGBE_PCIDEVCTRL2_16_32ms_def
Definition: ixgbe_type.h:2532
IXGBE_HLREG0_LPBK
#define IXGBE_HLREG0_LPBK
Definition: ixgbe_type.h:1802
IXGBE_FCTRL_UPE
#define IXGBE_FCTRL_UPE
Definition: ixgbe_type.h:2655
IXGBE_FCCFG_TFCE_802_3X
#define IXGBE_FCCFG_TFCE_802_3X
Definition: ixgbe_type.h:1902
IXGBE_LINK_SPEED_10GB_FULL
#define IXGBE_LINK_SPEED_10GB_FULL
Definition: ixgbe_type.h:3450
IXGBE_ERR_DEVICE_NOT_SUPPORTED
#define IXGBE_ERR_DEVICE_NOT_SUPPORTED
Definition: ixgbe_type.h:4245
IXGBE_PCS1GLSTA_AN_TIMED_OUT
#define IXGBE_PCS1GLSTA_AN_TIMED_OUT
Definition: ixgbe_type.h:2275
IXGBE_GOTCL
#define IXGBE_GOTCL
Definition: ixgbe_type.h:1015
FW_CEM_CMD_DRIVER_INFO
#define FW_CEM_CMD_DRIVER_INFO
Definition: ixgbe_type.h:3088
IXGBE_SWSM_SWESMBI
#define IXGBE_SWSM_SWESMBI
Definition: ixgbe_type.h:2298
IXGBE_FWSM_FW_MODE_PT
#define IXGBE_FWSM_FW_MODE_PT
Definition: ixgbe_type.h:1107
IXGBE_PCI_LINK_WIDTH_1
#define IXGBE_PCI_LINK_WIDTH_1
Definition: ixgbe_type.h:2519
IXGBE_DCA_RXCTRL_DATA_WRO_EN
#define IXGBE_DCA_RXCTRL_DATA_WRO_EN
Definition: ixgbe_type.h:1518
IXGBE_ERRBC
#define IXGBE_ERRBC
Definition: ixgbe_type.h:984
IXGBE_FWSM_BY_MAC
#define IXGBE_FWSM_BY_MAC(_hw)
Definition: ixgbe_type.h:1189
IXGBE_EEC_SIZE
#define IXGBE_EEC_SIZE
Definition: ixgbe_type.h:2336
IXGBE_PCIE_MSIX_82599_CAPS
#define IXGBE_PCIE_MSIX_82599_CAPS
Definition: ixgbe_type.h:2400
IXGBE_PFDTXGSWC_VT_LBEN
#define IXGBE_PFDTXGSWC_VT_LBEN
Definition: ixgbe_type.h:579
IXGBE_PCS1GLCTL
#define IXGBE_PCS1GLCTL
Definition: ixgbe_type.h:1360
IXGBE_QPTC
#define IXGBE_QPTC(_i)
Definition: ixgbe_type.h:1046
IXGBE_FWSTS_FWRI
#define IXGBE_FWSTS_FWRI
Definition: ixgbe_type.h:2316
FW_CEM_CMD_DRIVER_INFO_LEN
#define FW_CEM_CMD_DRIVER_INFO_LEN
Definition: ixgbe_type.h:3089
IXGBE_RAL
#define IXGBE_RAL(_i)
Definition: ixgbe_type.h:451
IXGBE_DEV_ID_X550EM_A_10G_T
#define IXGBE_DEV_ID_X550EM_A_10G_T
Definition: ixgbe_type.h:141
IXGBE_PCIDEVCTRL2_TIMEO_MASK
#define IXGBE_PCIDEVCTRL2_TIMEO_MASK
Definition: ixgbe_type.h:2531
IXGBE_FCCFG
#define IXGBE_FCCFG
Definition: ixgbe_type.h:394
NVM_OROM_BLK_LOW
#define NVM_OROM_BLK_LOW
Definition: ixgbe_type.h:310
IXGBE_ETS_LTHRES_DELTA_SHIFT
#define IXGBE_ETS_LTHRES_DELTA_SHIFT
Definition: ixgbe_type.h:2384
IXGBE_VFTA
#define IXGBE_VFTA(_i)
Definition: ixgbe_type.h:461
IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
Definition: ixgbe_type.h:2444
IXGBE_PRC127
#define IXGBE_PRC127
Definition: ixgbe_type.h:1004
IXGBE_EEPROM_PAGE_SIZE_MAX
#define IXGBE_EEPROM_PAGE_SIZE_MAX
Definition: ixgbe_type.h:2443
IXGBE_CTRL
#define IXGBE_CTRL
Definition: ixgbe_type.h:165
BYPASS_CTL1_VALID_M
#define BYPASS_CTL1_VALID_M
Definition: ixgbe_type.h:4328
IXGBE_HICR_EN
#define IXGBE_HICR_EN
Definition: ixgbe_type.h:1123
IXGBE_IRQ_CLEAR_MASK
#define IXGBE_IRQ_CLEAR_MASK
Definition: ixgbe_type.h:2058
NVM_OROM_BLK_HI
#define NVM_OROM_BLK_HI
Definition: ixgbe_type.h:311
IXGBE_ERR_MASTER_REQUESTS_PENDING
#define IXGBE_ERR_MASTER_REQUESTS_PENDING
Definition: ixgbe_type.h:4246
IXGBE_RLEC
#define IXGBE_RLEC
Definition: ixgbe_type.h:989
IXGBE_MAX_MSIX_VECTORS_82598
#define IXGBE_MAX_MSIX_VECTORS_82598
Definition: ixgbe_type.h:2403
IXGBE_FCRTV
#define IXGBE_FCRTV
Definition: ixgbe_type.h:393
IXGBE_ESDP
#define IXGBE_ESDP
Definition: ixgbe_type.h:168
IXGBE_QPRC
#define IXGBE_QPRC(_i)
Definition: ixgbe_type.h:1045
ixgbe_fc_none
@ ixgbe_fc_none
Definition: ixgbe_type.h:3766
ixgbe_fc_rx_pause
@ ixgbe_fc_rx_pause
Definition: ixgbe_type.h:3767
ixgbe_fc_tx_pause
@ ixgbe_fc_tx_pause
Definition: ixgbe_type.h:3768
ixgbe_fc_default
@ ixgbe_fc_default
Definition: ixgbe_type.h:3770
ixgbe_fc_full
@ ixgbe_fc_full
Definition: ixgbe_type.h:3769
IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR
#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR
Definition: ixgbe_type.h:2467
IXGBE_NVM_POLL_WRITE
#define IXGBE_NVM_POLL_WRITE
Definition: ixgbe_type.h:2433
IXGBE_FW_PTR
#define IXGBE_FW_PTR
Definition: ixgbe_type.h:2375
IXGBE_DEV_ID_X550EM_A_QSFP_N
#define IXGBE_DEV_ID_X550EM_A_QSFP_N
Definition: ixgbe_type.h:143
IXGBE_ETS_TYPE_SHIFT
#define IXGBE_ETS_TYPE_SHIFT
Definition: ixgbe_type.h:2386
IXGBE_EEPROM_RW_REG_DONE
#define IXGBE_EEPROM_RW_REG_DONE
Definition: ixgbe_type.h:2430
IXGBE_RUC
#define IXGBE_RUC
Definition: ixgbe_type.h:1018
IXGBE_TXPKT_SIZE_MAX
#define IXGBE_TXPKT_SIZE_MAX
Definition: ixgbe_type.h:1766
NVM_OEM_PROD_VER_CAP_OFF
#define NVM_OEM_PROD_VER_CAP_OFF
Definition: ixgbe_type.h:318
IXGBE_QBTC_L
#define IXGBE_QBTC_L(_i)
Definition: ixgbe_type.h:1052
IXGBE_LXONRXCNT
#define IXGBE_LXONRXCNT
Definition: ixgbe_type.h:994
IXGBE_FCCFG_TFCE_PRIORITY
#define IXGBE_FCCFG_TFCE_PRIORITY
Definition: ixgbe_type.h:1903
IXGBE_EEWR
#define IXGBE_EEWR
Definition: ixgbe_type.h:197
BYPASS_CTL2_DATA_M
#define BYPASS_CTL2_DATA_M
Definition: ixgbe_type.h:4336
IXGBE_SECRXCTRL_RX_DIS
#define IXGBE_SECRXCTRL_RX_DIS
Definition: ixgbe_type.h:789
IXGBE_MDIO_PCS_DEV_TYPE
#define IXGBE_MDIO_PCS_DEV_TYPE
Definition: ixgbe_type.h:1575
ixgbe_bus_width_unknown
@ ixgbe_bus_width_unknown
Definition: ixgbe_type.h:3807
ixgbe_bus_width_pcie_x1
@ ixgbe_bus_width_pcie_x1
Definition: ixgbe_type.h:3808
ixgbe_bus_width_pcie_x8
@ ixgbe_bus_width_pcie_x8
Definition: ixgbe_type.h:3811
ixgbe_bus_width_pcie_x2
@ ixgbe_bus_width_pcie_x2
Definition: ixgbe_type.h:3809
ixgbe_bus_width_pcie_x4
@ ixgbe_bus_width_pcie_x4
Definition: ixgbe_type.h:3810
IXGBE_FCOE_IBA_CAPS_BLK_PTR
#define IXGBE_FCOE_IBA_CAPS_BLK_PTR
Definition: ixgbe_type.h:2483
IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
Definition: ixgbe_type.h:2464
IXGBE_DEVICE_CAPS
#define IXGBE_DEVICE_CAPS
Definition: ixgbe_type.h:2396
IXGBE_EEPROM_RDSR_OPCODE_SPI
#define IXGBE_EEPROM_RDSR_OPCODE_SPI
Definition: ixgbe_type.h:2422
IXGBE_PRC1023
#define IXGBE_PRC1023
Definition: ixgbe_type.h:1007
IXGBE_FCRTL_82599
#define IXGBE_FCRTL_82599(_i)
Definition: ixgbe_type.h:388
IXGBE_ERR_SFP_NOT_PRESENT
#define IXGBE_ERR_SFP_NOT_PRESENT
Definition: ixgbe_type.h:4254
IXGBE_EEC_DO
#define IXGBE_EEC_DO
Definition: ixgbe_type.h:2322
IXGBE_EEC_SIZE_SHIFT
#define IXGBE_EEC_SIZE_SHIFT
Definition: ixgbe_type.h:2339
IXGBE_HI_MAX_BLOCK_BYTE_LENGTH
#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH
Definition: ixgbe_type.h:3078
IXGBE_PCI_DEVICE_STATUS
#define IXGBE_PCI_DEVICE_STATUS
Definition: ixgbe_type.h:2514
IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD
#define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD
Definition: ixgbe_type.h:4487
IXGBE_EEC_DI
#define IXGBE_EEC_DI
Definition: ixgbe_type.h:2321
IXGBE_DEV_ID_X550EM_X_XFI
#define IXGBE_DEV_ID_X550EM_X_XFI
Definition: ixgbe_type.h:152
IXGBE_HICR_SV
#define IXGBE_HICR_SV
Definition: ixgbe_type.h:1126
IXGBE_MCSTCTRL
#define IXGBE_MCSTCTRL
Definition: ixgbe_type.h:466
BYPASS_WDT_VALUE_M
#define BYPASS_WDT_VALUE_M
Definition: ixgbe_type.h:4305
IXGBE_CLEAR_VMDQ_ALL
#define IXGBE_CLEAR_VMDQ_ALL
Definition: ixgbe_type.h:2558
ixgbe_fcoe_bootstatus_disabled
@ ixgbe_fcoe_bootstatus_disabled
Definition: ixgbe_type.h:3660
ixgbe_fcoe_bootstatus_unavailable
@ ixgbe_fcoe_bootstatus_unavailable
Definition: ixgbe_type.h:3662
ixgbe_fcoe_bootstatus_enabled
@ ixgbe_fcoe_bootstatus_enabled
Definition: ixgbe_type.h:3661
BYPASS_PAGE_CTL2
#define BYPASS_PAGE_CTL2
Definition: ixgbe_type.h:4280
IXGBE_CTRL_EXT_NS_DIS
#define IXGBE_CTRL_EXT_NS_DIS
Definition: ixgbe_type.h:1500
IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
Definition: ixgbe_type.h:2488
BYPASS_AUX_OFF_M
#define BYPASS_AUX_OFF_M
Definition: ixgbe_type.h:4302
IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
Definition: ixgbe_type.h:2489
IXGBE_ERR_EEPROM_CHECKSUM
#define IXGBE_ERR_EEPROM_CHECKSUM
Definition: ixgbe_type.h:4236
ixgbe_addr_filter_info
Definition: ixgbe_type.h:3817
ixgbe_addr_filter_info::rar_used_count
u32 rar_used_count
Definition: ixgbe_type.h:3819
ixgbe_addr_filter_info::user_set_promisc
bool user_set_promisc
Definition: ixgbe_type.h:3822
ixgbe_addr_filter_info::overflow_promisc
u32 overflow_promisc
Definition: ixgbe_type.h:3821
ixgbe_addr_filter_info::num_mc_addrs
u32 num_mc_addrs
Definition: ixgbe_type.h:3818
ixgbe_addr_filter_info::mta_in_use
u32 mta_in_use
Definition: ixgbe_type.h:3820
ixgbe_bus_info
Definition: ixgbe_type.h:3826
ixgbe_bus_info::func
u16 func
Definition: ixgbe_type.h:3831
ixgbe_bus_info::instance_id
u16 instance_id
Definition: ixgbe_type.h:3833
ixgbe_bus_info::lan_id
u8 lan_id
Definition: ixgbe_type.h:3832
ixgbe_bus_info::width
enum ixgbe_bus_width width
Definition: ixgbe_type.h:3828
ixgbe_bus_info::speed
enum ixgbe_bus_speed speed
Definition: ixgbe_type.h:3827
ixgbe_bus_info::type
enum ixgbe_bus_type type
Definition: ixgbe_type.h:3829
ixgbe_eeprom_info
Definition: ixgbe_type.h:4102
ixgbe_eeprom_info::type
enum ixgbe_eeprom_type type
Definition: ixgbe_type.h:4104
ixgbe_eeprom_info::ops
struct ixgbe_eeprom_operations ops
Definition: ixgbe_type.h:4103
ixgbe_eeprom_info::word_page_size
u16 word_page_size
Definition: ixgbe_type.h:4108
ixgbe_eeprom_info::word_size
u16 word_size
Definition: ixgbe_type.h:4106
ixgbe_eeprom_info::address_bits
u16 address_bits
Definition: ixgbe_type.h:4107
ixgbe_eeprom_info::semaphore_delay
u32 semaphore_delay
Definition: ixgbe_type.h:4105
ixgbe_eeprom_operations::read_buffer
s32(* read_buffer)(struct ixgbe_hw *, u16, u16, u16 *)
Definition: ixgbe_type.h:3940
ixgbe_eeprom_operations::write_buffer
s32(* write_buffer)(struct ixgbe_hw *, u16, u16, u16 *)
Definition: ixgbe_type.h:3942
ixgbe_eeprom_operations::update_checksum
s32(* update_checksum)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3944
ixgbe_eeprom_operations::init_params
s32(* init_params)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3938
ixgbe_eeprom_operations::write
s32(* write)(struct ixgbe_hw *, u16, u16)
Definition: ixgbe_type.h:3941
ixgbe_eeprom_operations::read
s32(* read)(struct ixgbe_hw *, u16, u16 *)
Definition: ixgbe_type.h:3939
ixgbe_eeprom_operations::calc_checksum
s32(* calc_checksum)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3945
ixgbe_eeprom_operations::validate_checksum
s32(* validate_checksum)(struct ixgbe_hw *, u16 *)
Definition: ixgbe_type.h:3943
ixgbe_fc_info::current_mode
enum ixgbe_fc_mode current_mode
Definition: ixgbe_type.h:3845
ixgbe_fc_info::fc_was_autonegged
bool fc_was_autonegged
Definition: ixgbe_type.h:3844
ixgbe_fc_info::low_water
u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]
Definition: ixgbe_type.h:3839
ixgbe_fc_info::high_water
u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]
Definition: ixgbe_type.h:3838
ixgbe_fc_info::strict_ieee
bool strict_ieee
Definition: ixgbe_type.h:3842
ixgbe_fc_info::requested_mode
enum ixgbe_fc_mode requested_mode
Definition: ixgbe_type.h:3846
ixgbe_fc_info::disable_fc_autoneg
bool disable_fc_autoneg
Definition: ixgbe_type.h:3843
ixgbe_fc_info::pause_time
u16 pause_time
Definition: ixgbe_type.h:3840
ixgbe_hic_drv_info
Definition: ixgbe_type.h:3207
ixgbe_hic_drv_info::pad2
u16 pad2
Definition: ixgbe_type.h:3215
ixgbe_hic_drv_info::hdr
struct ixgbe_hic_hdr hdr
Definition: ixgbe_type.h:3208
ixgbe_hic_drv_info::ver_build
u8 ver_build
Definition: ixgbe_type.h:3211
ixgbe_hic_drv_info::ver_maj
u8 ver_maj
Definition: ixgbe_type.h:3213
ixgbe_hic_drv_info::port_num
u8 port_num
Definition: ixgbe_type.h:3209
ixgbe_hic_drv_info::ver_sub
u8 ver_sub
Definition: ixgbe_type.h:3210
ixgbe_hic_drv_info::ver_min
u8 ver_min
Definition: ixgbe_type.h:3212
ixgbe_hic_drv_info::pad
u8 pad
Definition: ixgbe_type.h:3214
ixgbe_hic_hdr
Definition: ixgbe_type.h:3178
ixgbe_hic_hdr::buf_len
u8 buf_len
Definition: ixgbe_type.h:3180
ixgbe_hic_hdr::checksum
u8 checksum
Definition: ixgbe_type.h:3185
ixgbe_hic_hdr::cmd_resv
u8 cmd_resv
Definition: ixgbe_type.h:3182
ixgbe_hic_hdr::cmd
u8 cmd
Definition: ixgbe_type.h:3179
ixgbe_hic_hdr::ret_status
u8 ret_status
Definition: ixgbe_type.h:3183
ixgbe_hic_hdr::cmd_or_resp
union ixgbe_hic_hdr::@3 cmd_or_resp
ixgbe_hw
Definition: ixgbe_type.h:4204
ixgbe_hw::adapter_stopped
bool adapter_stopped
Definition: ixgbe_type.h:4221
ixgbe_hw::mac
struct ixgbe_mac_info mac
Definition: ixgbe_type.h:4207
ixgbe_hw::addr_ctrl
struct ixgbe_addr_filter_info addr_ctrl
Definition: ixgbe_type.h:4208
ixgbe_hw::bus
struct ixgbe_bus_info bus
Definition: ixgbe_type.h:4213
ixgbe_hw::need_crosstalk_fix
bool need_crosstalk_fix
Definition: ixgbe_type.h:4226
ixgbe_hw::fc
struct ixgbe_fc_info fc
Definition: ixgbe_type.h:4209
ixgbe_hw::device_id
u16 device_id
Definition: ixgbe_type.h:4216
ixgbe_hw::eeprom
struct ixgbe_eeprom_info eeprom
Definition: ixgbe_type.h:4212
ixgbe_hw::hw_addr
u8 IOMEM * hw_addr
Definition: ixgbe_type.h:4205
ixgbe_hw::phy
struct ixgbe_phy_info phy
Definition: ixgbe_type.h:4210
ixgbe_mac_info
Definition: ixgbe_type.h:4113
ixgbe_mac_info::max_link_up_time
u32 max_link_up_time
Definition: ixgbe_type.h:4146
ixgbe_mac_info::max_tx_queues
u32 max_tx_queues
Definition: ixgbe_type.h:4131
ixgbe_mac_info::rar_highwater
u32 rar_highwater
Definition: ixgbe_type.h:4129
ixgbe_mac_info::rx_pb_size
u32 rx_pb_size
Definition: ixgbe_type.h:4130
ixgbe_mac_info::led_link_act
u8 led_link_act
Definition: ixgbe_type.h:4147
ixgbe_mac_info::mcft_size
u32 mcft_size
Definition: ixgbe_type.h:4126
ixgbe_mac_info::flags
u8 flags
Definition: ixgbe_type.h:4141
ixgbe_mac_info::mta_shadow
u32 mta_shadow[IXGBE_MAX_MTA]
Definition: ixgbe_type.h:4124
ixgbe_mac_info::type
enum ixgbe_mac_type type
Definition: ixgbe_type.h:4115
ixgbe_mac_info::mc_filter_type
s32 mc_filter_type
Definition: ixgbe_type.h:4125
ixgbe_mac_info::num_rar_entries
u32 num_rar_entries
Definition: ixgbe_type.h:4128
ixgbe_mac_info::thermal_sensor_data
struct ixgbe_thermal_sensor_data thermal_sensor_data
Definition: ixgbe_type.h:4142
ixgbe_mac_info::addr
u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
Definition: ixgbe_type.h:4116
ixgbe_mac_info::san_mac_rar_index
u8 san_mac_rar_index
Definition: ixgbe_type.h:4134
ixgbe_mac_info::set_lben
bool set_lben
Definition: ixgbe_type.h:4145
ixgbe_mac_info::vft_size
u32 vft_size
Definition: ixgbe_type.h:4127
ixgbe_mac_info::ops
struct ixgbe_mac_operations ops
Definition: ixgbe_type.h:4114
ixgbe_mac_info::max_rx_queues
u32 max_rx_queues
Definition: ixgbe_type.h:4132
ixgbe_mac_operations::set_vlvf
s32(* set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32, bool)
Definition: ixgbe_type.h:4017
ixgbe_mac_operations::reset_hw
s32(* reset_hw)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3950
ixgbe_mac_operations::init_hw
s32(* init_hw)(struct ixgbe_hw *)
Definition: ixgbe_type.h:3949
ixgbe_mac_operations::prot_autoc_read
s32(* prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *)
Definition: ixgbe_type.h:3974
ixgbe_mac_operations::dmac_config_tcs
s32(* dmac_config_tcs)(struct ixgbe_hw *hw)
Definition: ixgbe_type.h:4046
ixgbe_mac_operations::acquire_swfw_sync
s32(* acquire_swfw_sync)(struct ixgbe_hw *, u32)
Definition: ixgbe_type.h:3971
ixgbe_mac_operations::fc_enable
s32(* fc_enable)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4026
ixgbe_mac_operations::led_off
s32(* led_off)(struct ixgbe_hw *, u32)
Definition: ixgbe_type.h:3994
ixgbe_mac_operations::get_mac_addr
s32(* get_mac_addr)(struct ixgbe_hw *, u8 *)
Definition: ixgbe_type.h:3956
ixgbe_mac_operations::init_rx_addrs
s32(* init_rx_addrs)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4007
ixgbe_mac_operations::enable_rx_dma
s32(* enable_rx_dma)(struct ixgbe_hw *, u32)
Definition: ixgbe_type.h:3968
ixgbe_mac_operations::setup_link
s32(* setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool)
Definition: ixgbe_type.h:3982
ixgbe_mac_operations::set_rar
s32(* set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32)
Definition: ixgbe_type.h:4000
ixgbe_mac_operations::disable_mc
s32(* disable_mc)(struct ixgbe_hw *)
Definition: ixgbe_type.h:4014
ixgbe_mac_operations::release_swfw_sync
void(* release_swfw_sync)(struct ixgbe_hw *, u32)
Definition: ixgbe_type.h:3972
ixgbe_mac_operations::clear_vmdq
s32(* clear_vmdq)(struct ixgbe_hw *, u32, u32)
Definition: ixgbe_type.h:4006
ixgbe_mac_operations::enable_mc
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Definition: ixgbe_type.h:4013
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Definition: ixgbe_type.h:4015
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Definition: ixgbe_type.h:4041
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Definition: ixgbe_type.h:4004
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Definition: ixgbe_type.h:3984
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Definition: ixgbe_type.h:3975
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Definition: ixgbe_type.h:4016
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Definition: ixgbe_type.h:4008
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Definition: ixgbe_type.h:4010
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Definition: ixgbe_type.h:3997
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Definition: ixgbe_type.h:4040
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Definition: ixgbe_type.h:4019
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Definition: ixgbe_type.h:3959
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Definition: ixgbe_type.h:4028
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Definition: ixgbe_type.h:3993
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Definition: ixgbe_type.h:4027
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Definition: ixgbe_type.h:4047
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Definition: ixgbe_type.h:3985
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Definition: ixgbe_type.h:3964
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Definition: ixgbe_type.h:4002
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Definition: ixgbe_type.h:4003
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Definition: ixgbe_type.h:3996
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Definition: ixgbe_type.h:3952
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Definition: ixgbe_type.h:3954
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Definition: ixgbe_type.h:3963
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Definition: ixgbe_type.h:3995
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Definition: ixgbe_type.h:3951
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Definition: ixgbe_type.h:3962
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Definition: ixgbe_type.h:3955
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Definition: ixgbe_type.h:4045
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Definition: ixgbe_type.h:331
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Definition: ixgbe_type.h:343
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Definition: ixgbe_type.h:337
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Definition: ixgbe_type.h:345
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Definition: ixgbe_type.h:344
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Definition: ixgbe_type.h:338
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Definition: ixgbe_type.h:332
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Definition: ixgbe_type.h:342
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Definition: ixgbe_type.h:339
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Definition: ixgbe_type.h:340
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Definition: ixgbe_common.h:46
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Definition: ixgbe_common.h:48
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Definition: ixgbe_common.h:47
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Definition: ixgbe_type.h:4158
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Definition: ixgbe_type.h:4161
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Definition: ixgbe_type.h:4151
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Definition: ixgbe_type.h:4154
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Definition: ixgbe_type.h:4073
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Definition: ixgbe_type.h:4072
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Definition: ixgbe_type.h:4063
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Definition: ixgbe_type.h:4064
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Definition: ixgbe_type.h:300
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Definition: ixgbe_type.h:298
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Definition: ixgbe_type.h:301
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Definition: ixgbe_type.h:299
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Definition: ixgbe_type.h:304
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Definition: ixgbe_type.h:305