83#define IXGBE_INTEL_VENDOR_ID 0x8086
86#define IXGBE_DEV_ID_82598 0x10B6
87#define IXGBE_DEV_ID_82598_BX 0x1508
88#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
89#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
90#define IXGBE_DEV_ID_82598AT 0x10C8
91#define IXGBE_DEV_ID_82598AT2 0x150B
92#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
93#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
94#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
95#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
96#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
97#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
98#define IXGBE_DEV_ID_82599_KX4 0x10F7
99#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
100#define IXGBE_DEV_ID_82599_KR 0x1517
101#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
102#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
103#define IXGBE_DEV_ID_82599_CX4 0x10F9
104#define IXGBE_DEV_ID_82599_SFP 0x10FB
105#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
106#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
107#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
108#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
109#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
110#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
111#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159
112#define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D
113#define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008
114#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976
115#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE
116#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
117#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
118#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
119#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
120#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
121#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
122#define IXGBE_DEV_ID_82599EN_SFP 0x1557
123#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
124#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
125#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
126#define IXGBE_DEV_ID_82599_VF 0x10ED
127#define IXGBE_DEV_ID_82599_VF_HV 0x152E
128#define IXGBE_DEV_ID_82599_BYPASS 0x155D
129#define IXGBE_DEV_ID_X540T 0x1528
130#define IXGBE_DEV_ID_X540_VF 0x1515
131#define IXGBE_DEV_ID_X540_VF_HV 0x1530
132#define IXGBE_DEV_ID_X540_BYPASS 0x155C
133#define IXGBE_DEV_ID_X540T1 0x1560
134#define IXGBE_DEV_ID_X550T 0x1563
135#define IXGBE_DEV_ID_X550T1 0x15D1
136#define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
137#define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
138#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
139#define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
140#define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
141#define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8
142#define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA
143#define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC
144#define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
145#define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4
146#define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5
147#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
148#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
149#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
150#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
151#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
152#define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0
153#define IXGBE_DEV_ID_X550_VF_HV 0x1564
154#define IXGBE_DEV_ID_X550_VF 0x1565
155#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
156#define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4
157#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
158#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
160#define IXGBE_CAT(r, m) IXGBE_##r##m
162#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
165#define IXGBE_CTRL 0x00000
166#define IXGBE_STATUS 0x00008
167#define IXGBE_CTRL_EXT 0x00018
168#define IXGBE_ESDP 0x00020
169#define IXGBE_EODSDP 0x00028
170#define IXGBE_I2CCTL_82599 0x00028
171#define IXGBE_I2CCTL IXGBE_I2CCTL_82599
172#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599
173#define IXGBE_I2CCTL_X550 0x15F5C
174#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550
175#define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550
176#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
177#define IXGBE_PHY_GPIO 0x00028
178#define IXGBE_MAC_GPIO 0x00030
179#define IXGBE_PHYINT_STATUS0 0x00100
180#define IXGBE_PHYINT_STATUS1 0x00104
181#define IXGBE_PHYINT_STATUS2 0x00108
182#define IXGBE_LEDCTL 0x00200
183#define IXGBE_FRTIMER 0x00048
184#define IXGBE_TCPTIMER 0x0004C
185#define IXGBE_CORESPARE 0x00600
186#define IXGBE_EXVET 0x05078
189#define IXGBE_EEC 0x10010
190#define IXGBE_EEC_X540 IXGBE_EEC
191#define IXGBE_EEC_X550 IXGBE_EEC
192#define IXGBE_EEC_X550EM_x IXGBE_EEC
193#define IXGBE_EEC_X550EM_a 0x15FF8
194#define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC)
196#define IXGBE_EERD 0x10014
197#define IXGBE_EEWR 0x10018
199#define IXGBE_FLA 0x1001C
200#define IXGBE_FLA_X540 IXGBE_FLA
201#define IXGBE_FLA_X550 IXGBE_FLA
202#define IXGBE_FLA_X550EM_x IXGBE_FLA
203#define IXGBE_FLA_X550EM_a 0x15F68
204#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA)
206#define IXGBE_EEMNGCTL 0x10110
207#define IXGBE_EEMNGDATA 0x10114
208#define IXGBE_FLMNGCTL 0x10118
209#define IXGBE_FLMNGDATA 0x1011C
210#define IXGBE_FLMNGCNT 0x10120
211#define IXGBE_FLOP 0x1013C
213#define IXGBE_GRC 0x10200
214#define IXGBE_GRC_X540 IXGBE_GRC
215#define IXGBE_GRC_X550 IXGBE_GRC
216#define IXGBE_GRC_X550EM_x IXGBE_GRC
217#define IXGBE_GRC_X550EM_a 0x15F64
218#define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC)
220#define IXGBE_SRAMREL 0x10210
221#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL
222#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL
223#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL
224#define IXGBE_SRAMREL_X550EM_a 0x15F6C
225#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL)
227#define IXGBE_PHYDBG 0x10218
230#define IXGBE_GRC_MNG 0x00000001
231#define IXGBE_GRC_APME 0x00000002
233#define IXGBE_VPDDIAG0 0x10204
234#define IXGBE_VPDDIAG1 0x10208
237#define IXGBE_I2C_CLK_IN 0x00000001
238#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN
239#define IXGBE_I2C_CLK_IN_X550 0x00004000
240#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550
241#define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550
242#define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
244#define IXGBE_I2C_CLK_OUT 0x00000002
245#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT
246#define IXGBE_I2C_CLK_OUT_X550 0x00000200
247#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550
248#define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550
249#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
251#define IXGBE_I2C_DATA_IN 0x00000004
252#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN
253#define IXGBE_I2C_DATA_IN_X550 0x00001000
254#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550
255#define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550
256#define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
258#define IXGBE_I2C_DATA_OUT 0x00000008
259#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT
260#define IXGBE_I2C_DATA_OUT_X550 0x00000400
261#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550
262#define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550
263#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
265#define IXGBE_I2C_DATA_OE_N_EN 0
266#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN
267#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
268#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
269#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
270#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
272#define IXGBE_I2C_BB_EN 0
273#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN
274#define IXGBE_I2C_BB_EN_X550 0x00000100
275#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
276#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
277#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
279#define IXGBE_I2C_CLK_OE_N_EN 0
280#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN
281#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
282#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
283#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550
284#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
285#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
287#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
288#define IXGBE_EMC_INTERNAL_DATA 0x00
289#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
290#define IXGBE_EMC_DIODE1_DATA 0x01
291#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
292#define IXGBE_EMC_DIODE2_DATA 0x23
293#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
295#define IXGBE_MAX_SENSORS 3
309#define NVM_OROM_OFFSET 0x17
310#define NVM_OROM_BLK_LOW 0x83
311#define NVM_OROM_BLK_HI 0x84
312#define NVM_OROM_PATCH_MASK 0xFF
313#define NVM_OROM_SHIFT 8
315#define NVM_VER_MASK 0x00FF
316#define NVM_VER_SHIFT 8
317#define NVM_OEM_PROD_VER_PTR 0x1B
318#define NVM_OEM_PROD_VER_CAP_OFF 0x1
319#define NVM_OEM_PROD_VER_OFF_L 0x2
320#define NVM_OEM_PROD_VER_OFF_H 0x3
321#define NVM_OEM_PROD_VER_CAP_MASK 0xF
322#define NVM_OEM_PROD_VER_MOD_LEN 0x3
323#define NVM_ETK_OFF_LOW 0x2D
324#define NVM_ETK_OFF_HI 0x2E
325#define NVM_ETK_SHIFT 16
326#define NVM_VER_INVALID 0xFFFF
327#define NVM_ETK_VALID 0x8000
328#define NVM_INVALID_PTR 0xFFFF
329#define NVM_VER_SIZE 32
350#define IXGBE_EICR 0x00800
351#define IXGBE_EICS 0x00808
352#define IXGBE_EIMS 0x00880
353#define IXGBE_EIMC 0x00888
354#define IXGBE_EIAC 0x00810
355#define IXGBE_EIAM 0x00890
356#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
357#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
358#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
359#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
365#define IXGBE_MAX_INT_RATE 488281
366#define IXGBE_MIN_INT_RATE 956
367#define IXGBE_MAX_EITR 0x00000FF8
368#define IXGBE_MIN_EITR 8
369#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
370 (0x012300 + (((_i) - 24) * 4)))
371#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
372#define IXGBE_EITR_LLI_MOD 0x00008000
373#define IXGBE_EITR_CNT_WDIS 0x80000000
374#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4))
375#define IXGBE_IVAR_MISC 0x00A00
376#define IXGBE_EITRSEL 0x00894
377#define IXGBE_MSIXT 0x00000
378#define IXGBE_MSIXPBA 0x02000
379#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
380#define IXGBE_GPIE 0x00898
383#define IXGBE_FCADBUL 0x03210
384#define IXGBE_FCADBUH 0x03214
385#define IXGBE_FCAMACL 0x04328
386#define IXGBE_FCAMACH 0x0432C
387#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4))
388#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4))
389#define IXGBE_PFCTOP 0x03008
390#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4))
391#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8))
392#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8))
393#define IXGBE_FCRTV 0x032A0
394#define IXGBE_FCCFG 0x03D00
395#define IXGBE_TFCS 0x0CE00
398#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
399 (0x0D000 + (((_i) - 64) * 0x40)))
400#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
401 (0x0D004 + (((_i) - 64) * 0x40)))
402#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
403 (0x0D008 + (((_i) - 64) * 0x40)))
404#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
405 (0x0D010 + (((_i) - 64) * 0x40)))
406#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
407 (0x0D018 + (((_i) - 64) * 0x40)))
408#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
409 (0x0D028 + (((_i) - 64) * 0x40)))
410#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
411 (0x0D02C + (((_i) - 64) * 0x40)))
412#define IXGBE_RSCDBU 0x03028
413#define IXGBE_RDDCC 0x02F20
414#define IXGBE_RXMEMWRAP 0x03190
415#define IXGBE_STARCTRL 0x03024
422#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
423 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
424 (0x0D014 + (((_i) - 64) * 0x40))))
431#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
432 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
433 (0x0D00C + (((_i) - 64) * 0x40))))
434#define IXGBE_RDRXCTL 0x02F00
436#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
437#define IXGBE_RXCTRL 0x03000
438#define IXGBE_DROPEN 0x03D04
439#define IXGBE_RXPBSIZE_SHIFT 10
440#define IXGBE_RXPBSIZE_MASK 0x000FFC00
443#define IXGBE_RXCSUM 0x05000
444#define IXGBE_RFCTL 0x05008
445#define IXGBE_DRECCCTL 0x02F08
446#define IXGBE_DRECCCTL_DISABLE 0
447#define IXGBE_DRECCCTL2 0x02F8C
450#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
451#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
452 (0x0A200 + ((_i) * 8)))
453#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
454 (0x0A204 + ((_i) * 8)))
455#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
456#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
458#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
459 (0x0EA00 + ((_i) * 4)))
461#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
463#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
464#define IXGBE_FCTRL 0x05080
465#define IXGBE_VLNCTRL 0x05088
466#define IXGBE_MCSTCTRL 0x05090
467#define IXGBE_MRQC 0x05818
468#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4))
469#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4))
470#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4))
471#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4))
472#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4))
473#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4))
474#define IXGBE_SYNQF 0x0EC30
475#define IXGBE_RQTC 0x0EC70
476#define IXGBE_MTQC 0x08120
477#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4))
478#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))
479#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))
480#define IXGBE_PFFLPL 0x050B0
481#define IXGBE_PFFLPH 0x050B4
482#define IXGBE_VT_CTL 0x051B0
483#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i)))
485#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
486#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i)))
487#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i)))
488#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
489#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
490#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
491#define IXGBE_QDE 0x2F04
492#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4))
493#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4))
494#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
495#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
496#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
497#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
498#define IXGBE_LVMMC_RX 0x2FA8
499#define IXGBE_LVMMC_TX 0x8108
500#define IXGBE_LMVM_RX 0x2FA4
501#define IXGBE_LMVM_TX 0x8124
502#define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4))
503#define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4))
504#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4))
505#define IXGBE_RXFECCERR0 0x051B8
506#define IXGBE_LLITHRESH 0x0EC90
507#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4))
508#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4))
509#define IXGBE_IMIRVP 0x05AC0
510#define IXGBE_VMD_CTL 0x0581C
511#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4))
512#define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4))
513#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))
519#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4))
520#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
521#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
524#define IXGBE_FDIRCTRL 0x0EE00
525#define IXGBE_FDIRHKEY 0x0EE68
526#define IXGBE_FDIRSKEY 0x0EE6C
527#define IXGBE_FDIRDIP4M 0x0EE3C
528#define IXGBE_FDIRSIP4M 0x0EE40
529#define IXGBE_FDIRTCPM 0x0EE44
530#define IXGBE_FDIRUDPM 0x0EE48
531#define IXGBE_FDIRSCTPM 0x0EE78
532#define IXGBE_FDIRIP6M 0x0EE74
533#define IXGBE_FDIRM 0x0EE70
536#define IXGBE_FDIRFREE 0x0EE38
537#define IXGBE_FDIRLEN 0x0EE4C
538#define IXGBE_FDIRUSTAT 0x0EE50
539#define IXGBE_FDIRFSTAT 0x0EE54
540#define IXGBE_FDIRMATCH 0x0EE58
541#define IXGBE_FDIRMISS 0x0EE5C
544#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4))
545#define IXGBE_FDIRIPSA 0x0EE18
546#define IXGBE_FDIRIPDA 0x0EE1C
547#define IXGBE_FDIRPORT 0x0EE20
548#define IXGBE_FDIRVLAN 0x0EE24
549#define IXGBE_FDIRHASH 0x0EE28
550#define IXGBE_FDIRCMD 0x0EE2C
553#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))
554#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
555#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
556#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
557#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
558#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
559#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
560#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
561#define IXGBE_DTXCTL 0x07E00
563#define IXGBE_DMATXCTL 0x04A80
564#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4))
565#define IXGBE_PFDTXGSWC 0x08220
566#define IXGBE_DTXMXSZRQ 0x08100
567#define IXGBE_DTXTCPFLGL 0x04A88
568#define IXGBE_DTXTCPFLGH 0x04A8C
569#define IXGBE_LBDRPEN 0x0CA00
570#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4))
572#define IXGBE_DMATXCTL_TE 0x1
573#define IXGBE_DMATXCTL_NS 0x2
574#define IXGBE_DMATXCTL_GDV 0x8
575#define IXGBE_DMATXCTL_MDP_EN 0x20
576#define IXGBE_DMATXCTL_MBINTEN 0x40
577#define IXGBE_DMATXCTL_VT_SHIFT 16
579#define IXGBE_PFDTXGSWC_VT_LBEN 0x1
582#define IXGBE_SPOOF_MACAS_MASK 0xFF
583#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
584#define IXGBE_SPOOF_VLANAS_SHIFT 8
585#define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000
586#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16
587#define IXGBE_PFVFSPOOF_REG_COUNT 8
589#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
591#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
592#define IXGBE_TIPG 0x0CB00
593#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4))
594#define IXGBE_MNGTXMAP 0x0CD10
595#define IXGBE_TIPG_FIBER_DEFAULT 3
596#define IXGBE_TXPBSIZE_SHIFT 10
599#define IXGBE_WUC 0x05800
600#define IXGBE_WUFC 0x05808
601#define IXGBE_WUS 0x05810
602#define IXGBE_IPAV 0x05838
603#define IXGBE_IP4AT 0x05840
604#define IXGBE_IP6AT 0x05880
606#define IXGBE_WUPL 0x05900
607#define IXGBE_WUPM 0x05A00
608#define IXGBE_PROXYS 0x05F60
609#define IXGBE_PROXYFC 0x05F64
610#define IXGBE_VXLANCTRL 0x0000507C
613#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff
614#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000
615#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff
616#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
618#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100))
620#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
621#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
624#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
626#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
628#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8
629#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
632#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
633#define IXGBE_FHFT_LENGTH_OFFSET 0xFC
634#define IXGBE_FHFT_LENGTH_MASK 0x0FF
638#define IXGBE_WUC_PME_EN 0x00000002
639#define IXGBE_WUC_PME_STATUS 0x00000004
640#define IXGBE_WUC_WKEN 0x00000010
643#define IXGBE_WUFC_LNKC 0x00000001
644#define IXGBE_WUFC_MAG 0x00000002
645#define IXGBE_WUFC_EX 0x00000004
646#define IXGBE_WUFC_MC 0x00000008
647#define IXGBE_WUFC_BC 0x00000010
648#define IXGBE_WUFC_ARP 0x00000020
649#define IXGBE_WUFC_IPV4 0x00000040
650#define IXGBE_WUFC_IPV6 0x00000080
651#define IXGBE_WUFC_MNG 0x00000100
653#define IXGBE_WUFC_IGNORE_TCO 0x00008000
654#define IXGBE_WUFC_FLX0 0x00010000
655#define IXGBE_WUFC_FLX1 0x00020000
656#define IXGBE_WUFC_FLX2 0x00040000
657#define IXGBE_WUFC_FLX3 0x00080000
658#define IXGBE_WUFC_FLX4 0x00100000
659#define IXGBE_WUFC_FLX5 0x00200000
660#define IXGBE_WUFC_FLX_FILTERS 0x000F0000
661#define IXGBE_WUFC_FLX_FILTERS_6 0x003F0000
662#define IXGBE_WUFC_FLX_FILTERS_8 0x00FF0000
663#define IXGBE_WUFC_FW_RST_WK 0x80000000
665#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
666#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF
667#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF
668#define IXGBE_WUFC_ALL_FILTERS_8 0x00FF00FF
669#define IXGBE_WUFC_FLX_OFFSET 16
672#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
673#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
674#define IXGBE_WUS_EX IXGBE_WUFC_EX
675#define IXGBE_WUS_MC IXGBE_WUFC_MC
676#define IXGBE_WUS_BC IXGBE_WUFC_BC
677#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
678#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
679#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
680#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
681#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
682#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
683#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
684#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
685#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
686#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
687#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
688#define IXGBE_WUS_FW_RST_WK IXGBE_WUFC_FW_RST_WK
690#define IXGBE_PROXYS_EX 0x00000004
691#define IXGBE_PROXYS_ARP_DIR 0x00000020
692#define IXGBE_PROXYS_NS 0x00000200
693#define IXGBE_PROXYS_NS_DIR 0x00000400
694#define IXGBE_PROXYS_ARP 0x00000800
695#define IXGBE_PROXYS_MLD 0x00001000
698#define IXGBE_PROXYFC_ENABLE 0x00000001
699#define IXGBE_PROXYFC_EX 0x00000004
700#define IXGBE_PROXYFC_ARP_DIR 0x00000020
701#define IXGBE_PROXYFC_NS 0x00000200
702#define IXGBE_PROXYFC_ARP 0x00000800
703#define IXGBE_PROXYFC_MLD 0x00000800
704#define IXGBE_PROXYFC_NO_TCO 0x00008000
706#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
709#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
710#define IXGBE_RMCS 0x03D00
711#define IXGBE_DPMCS 0x07F40
712#define IXGBE_PDPMCS 0x0CD00
713#define IXGBE_RUPPBMR 0x050A0
714#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4))
715#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4))
716#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40))
717#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40))
718#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4))
719#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4))
736#define IXGBE_DMACRXT_10G 0x55
737#define IXGBE_DMACRXT_1G 0x09
738#define IXGBE_DMACRXT_100M 0x01
741#define IXGBE_DMCMNGTH 0x15F20
742#define IXGBE_DMACR 0x02400
743#define IXGBE_DMCTH(_i) (0x03300 + ((_i) * 4))
744#define IXGBE_DMCTLX 0x02404
746#define IXGBE_DMCMNGTH_DMCMNGTH_MASK 0x000FFFF0
747#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT 4
748#define IXGBE_DMACR_DMACWT_MASK 0x0000FFFF
749#define IXGBE_DMACR_HIGH_PRI_TC_MASK 0x00FF0000
750#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT 16
751#define IXGBE_DMACR_EN_MNG_IND 0x10000000
752#define IXGBE_DMACR_LX_COAL_IND 0x40000000
753#define IXGBE_DMACR_DMAC_EN 0x80000000
754#define IXGBE_DMCTH_DMACRXT_MASK 0x000001FF
755#define IXGBE_DMCTLX_TTLX_MASK 0x00000FFF
758#define IXGBE_EEER 0x043A0
759#define IXGBE_EEE_STAT 0x04398
760#define IXGBE_EEE_SU 0x04380
761#define IXGBE_EEE_SU_TEEE_DLY_SHIFT 26
762#define IXGBE_TLPIC 0x041F4
763#define IXGBE_RLPIC 0x041F8
766#define IXGBE_EEER_TX_LPI_EN 0x00010000
767#define IXGBE_EEER_RX_LPI_EN 0x00020000
768#define IXGBE_EEE_STAT_NEG 0x20000000
769#define IXGBE_EEE_RX_LPI_STATUS 0x40000000
770#define IXGBE_EEE_TX_LPI_STATUS 0x80000000
773#define IXGBE_SECTXCTRL 0x08800
774#define IXGBE_SECTXSTAT 0x08804
775#define IXGBE_SECTXBUFFAF 0x08808
776#define IXGBE_SECTXMINIFG 0x08810
777#define IXGBE_SECRXCTRL 0x08D00
778#define IXGBE_SECRXSTAT 0x08D04
781#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
782#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
783#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
785#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
786#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
788#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
789#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
791#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
792#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
795#define IXGBE_LSECTXCAP 0x08A00
796#define IXGBE_LSECRXCAP 0x08F00
797#define IXGBE_LSECTXCTRL 0x08A04
798#define IXGBE_LSECTXSCL 0x08A08
799#define IXGBE_LSECTXSCH 0x08A0C
800#define IXGBE_LSECTXSA 0x08A10
801#define IXGBE_LSECTXPN0 0x08A14
802#define IXGBE_LSECTXPN1 0x08A18
803#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n)))
804#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n)))
805#define IXGBE_LSECRXCTRL 0x08F04
806#define IXGBE_LSECRXSCL 0x08F08
807#define IXGBE_LSECRXSCH 0x08F0C
808#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i)))
809#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i)))
810#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
811#define IXGBE_LSECTXUT 0x08A3C
812#define IXGBE_LSECTXPKTE 0x08A40
813#define IXGBE_LSECTXPKTP 0x08A44
814#define IXGBE_LSECTXOCTE 0x08A48
815#define IXGBE_LSECTXOCTP 0x08A4C
816#define IXGBE_LSECRXUT 0x08F40
817#define IXGBE_LSECRXOCTD 0x08F44
818#define IXGBE_LSECRXOCTV 0x08F48
819#define IXGBE_LSECRXBAD 0x08F4C
820#define IXGBE_LSECRXNOSCI 0x08F50
821#define IXGBE_LSECRXUNSCI 0x08F54
822#define IXGBE_LSECRXUNCH 0x08F58
823#define IXGBE_LSECRXDELAY 0x08F5C
824#define IXGBE_LSECRXLATE 0x08F60
825#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n)))
826#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n)))
827#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n)))
828#define IXGBE_LSECRXUNSA 0x08F7C
829#define IXGBE_LSECRXNUSA 0x08F80
832#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
833#define IXGBE_LSECTXCAP_SUM_SHIFT 16
834#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
835#define IXGBE_LSECRXCAP_SUM_SHIFT 16
837#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
838#define IXGBE_LSECTXCTRL_DISABLE 0x0
839#define IXGBE_LSECTXCTRL_AUTH 0x1
840#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
841#define IXGBE_LSECTXCTRL_AISCI 0x00000020
842#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
843#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
845#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
846#define IXGBE_LSECRXCTRL_EN_SHIFT 2
847#define IXGBE_LSECRXCTRL_DISABLE 0x0
848#define IXGBE_LSECRXCTRL_CHECK 0x1
849#define IXGBE_LSECRXCTRL_STRICT 0x2
850#define IXGBE_LSECRXCTRL_DROP 0x3
851#define IXGBE_LSECRXCTRL_PLSH 0x00000040
852#define IXGBE_LSECRXCTRL_RP 0x00000080
853#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
856#define IXGBE_IPSTXIDX 0x08900
857#define IXGBE_IPSTXSALT 0x08904
858#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i)))
859#define IXGBE_IPSRXIDX 0x08E00
860#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i)))
861#define IXGBE_IPSRXSPI 0x08E14
862#define IXGBE_IPSRXIPIDX 0x08E18
863#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i)))
864#define IXGBE_IPSRXSALT 0x08E2C
865#define IXGBE_IPSRXMOD 0x08E30
867#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
870#define IXGBE_RTRPCS 0x02430
871#define IXGBE_RTTDCS 0x04900
872#define IXGBE_RTTDCS_ARBDIS 0x00000040
873#define IXGBE_RTTPCS 0x0CD00
874#define IXGBE_RTRUP2TC 0x03020
875#define IXGBE_RTTUP2TC 0x0C800
876#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4))
877#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4))
878#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4))
879#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4))
880#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4))
881#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4))
882#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4))
883#define IXGBE_RTTDQSEL 0x04904
884#define IXGBE_RTTDT1C 0x04908
885#define IXGBE_RTTDT1S 0x0490C
886#define IXGBE_RTTQCNCR 0x08B00
887#define IXGBE_RTTQCNTG 0x04A90
888#define IXGBE_RTTBCNRD 0x0498C
889#define IXGBE_RTTQCNRR 0x0498C
890#define IXGBE_RTTDTECC 0x04990
891#define IXGBE_RTTDTECC_NO_BCN 0x00000100
893#define IXGBE_RTTBCNRC 0x04984
894#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
895#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
896#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
897#define IXGBE_RTTBCNRC_RF_INT_MASK \
898 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
899#define IXGBE_RTTBCNRM 0x04980
900#define IXGBE_RTTQCNRM 0x04980
903#define IXGBE_RTTBCNRS 0x04988
904#define IXGBE_RTTBCNCR 0x08B00
905#define IXGBE_RTTBCNACH 0x08B04
906#define IXGBE_RTTBCNACL 0x08B08
907#define IXGBE_RTTBCNTG 0x04A90
908#define IXGBE_RTTBCNIDX 0x08B0C
909#define IXGBE_RTTBCNCP 0x08B10
910#define IXGBE_RTFRTIMER 0x08B14
911#define IXGBE_RTTBCNRTT 0x05150
912#define IXGBE_RTTBCNRD 0x0498C
916#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
917#define IXGBE_FCPTRL 0x02410
918#define IXGBE_FCPTRH 0x02414
919#define IXGBE_FCBUFF 0x02418
920#define IXGBE_FCDMARW 0x02420
921#define IXGBE_FCBUFF_VALID (1 << 0)
922#define IXGBE_FCBUFF_BUFFSIZE (3 << 3)
923#define IXGBE_FCBUFF_WRCONTX (1 << 7)
924#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00
925#define IXGBE_FCBUFF_OFFSET 0xffff0000
926#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
927#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
928#define IXGBE_FCBUFF_OFFSET_SHIFT 16
929#define IXGBE_FCDMARW_WE (1 << 14)
930#define IXGBE_FCDMARW_RE (1 << 15)
931#define IXGBE_FCDMARW_FCOESEL 0x000001ff
932#define IXGBE_FCDMARW_LASTSIZE 0xffff0000
933#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
935#define IXGBE_TEOFF 0x04A94
936#define IXGBE_TSOFF 0x04A98
937#define IXGBE_REOFF 0x05158
938#define IXGBE_RSOFF 0x051F8
940#define IXGBE_FCD_ID 0x05114
941#define IXGBE_FCSMAC 0x0510C
942#define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT 16
944#define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
945#define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4))
946#define IXGBE_FCFLT 0x05108
947#define IXGBE_FCFLTRW 0x05110
948#define IXGBE_FCPARAM 0x051d8
949#define IXGBE_FCFLT_VALID (1 << 0)
950#define IXGBE_FCFLT_FIRST (1 << 1)
951#define IXGBE_FCFLT_SEQID 0x00ff0000
952#define IXGBE_FCFLT_SEQCNT 0xff000000
953#define IXGBE_FCFLTRW_RVALDT (1 << 13)
954#define IXGBE_FCFLTRW_WE (1 << 14)
955#define IXGBE_FCFLTRW_RE (1 << 15)
957#define IXGBE_FCRXCTRL 0x05100
958#define IXGBE_FCRXCTRL_FCOELLI (1 << 0)
959#define IXGBE_FCRXCTRL_SAVBAD (1 << 1)
960#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2)
961#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)
962#define IXGBE_FCRXCTRL_ALLH (1 << 4)
963#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)
964#define IXGBE_FCRXCTRL_ICRC (1 << 6)
965#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7)
966#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00
967#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
969#define IXGBE_FCRECTL 0x0ED00
970#define IXGBE_FCRETA0 0x0ED10
971#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4))
972#define IXGBE_FCRECTL_ENA 0x1
973#define IXGBE_FCRETASEL_ENA 0x2
974#define IXGBE_FCRETA_SIZE 8
975#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f
976#define IXGBE_FCRETA_SIZE_X550 32
978#define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000
979#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16
982#define IXGBE_CRCERRS 0x04000
983#define IXGBE_ILLERRC 0x04004
984#define IXGBE_ERRBC 0x04008
985#define IXGBE_MSPDC 0x04010
986#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4))
987#define IXGBE_MLFC 0x04034
988#define IXGBE_MRFC 0x04038
989#define IXGBE_RLEC 0x04040
990#define IXGBE_LXONTXC 0x03F60
991#define IXGBE_LXONRXC 0x0CF60
992#define IXGBE_LXOFFTXC 0x03F68
993#define IXGBE_LXOFFRXC 0x0CF68
994#define IXGBE_LXONRXCNT 0x041A4
995#define IXGBE_LXOFFRXCNT 0x041A8
996#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4))
997#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4))
998#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4))
999#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4))
1000#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4))
1001#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4))
1002#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4))
1003#define IXGBE_PRC64 0x0405C
1004#define IXGBE_PRC127 0x04060
1005#define IXGBE_PRC255 0x04064
1006#define IXGBE_PRC511 0x04068
1007#define IXGBE_PRC1023 0x0406C
1008#define IXGBE_PRC1522 0x04070
1009#define IXGBE_GPRC 0x04074
1010#define IXGBE_BPRC 0x04078
1011#define IXGBE_MPRC 0x0407C
1012#define IXGBE_GPTC 0x04080
1013#define IXGBE_GORCL 0x04088
1014#define IXGBE_GORCH 0x0408C
1015#define IXGBE_GOTCL 0x04090
1016#define IXGBE_GOTCH 0x04094
1017#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4))
1018#define IXGBE_RUC 0x040A4
1019#define IXGBE_RFC 0x040A8
1020#define IXGBE_ROC 0x040AC
1021#define IXGBE_RJC 0x040B0
1022#define IXGBE_MNGPRC 0x040B4
1023#define IXGBE_MNGPDC 0x040B8
1024#define IXGBE_MNGPTC 0x0CF90
1025#define IXGBE_TORL 0x040C0
1026#define IXGBE_TORH 0x040C4
1027#define IXGBE_TPR 0x040D0
1028#define IXGBE_TPT 0x040D4
1029#define IXGBE_PTC64 0x040D8
1030#define IXGBE_PTC127 0x040DC
1031#define IXGBE_PTC255 0x040E0
1032#define IXGBE_PTC511 0x040E4
1033#define IXGBE_PTC1023 0x040E8
1034#define IXGBE_PTC1522 0x040EC
1035#define IXGBE_MPTC 0x040F0
1036#define IXGBE_BPTC 0x040F4
1037#define IXGBE_XEC 0x04120
1038#define IXGBE_SSVPC 0x08780
1040#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
1041#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
1042 (0x08600 + ((_i) * 4)))
1043#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
1045#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40))
1046#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40))
1047#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40))
1048#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40))
1049#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40))
1050#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40))
1051#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40))
1052#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8))
1053#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8))
1054#define IXGBE_FCCRC 0x05118
1055#define IXGBE_FCOERPDC 0x0241C
1056#define IXGBE_FCLAST 0x02424
1057#define IXGBE_FCOEPRC 0x02428
1058#define IXGBE_FCOEDWRC 0x0242C
1059#define IXGBE_FCOEPTC 0x08784
1060#define IXGBE_FCOEDWTC 0x08788
1061#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF
1062#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF
1063#define IXGBE_O2BGPTC 0x041C4
1064#define IXGBE_O2BSPC 0x087B0
1065#define IXGBE_B2OSPC 0x041C0
1066#define IXGBE_B2OGPRC 0x02F90
1067#define IXGBE_BUPRC 0x04180
1068#define IXGBE_BMPRC 0x04184
1069#define IXGBE_BBPRC 0x04188
1070#define IXGBE_BUPTC 0x0418C
1071#define IXGBE_BMPTC 0x04190
1072#define IXGBE_BBPTC 0x04194
1073#define IXGBE_BCRCERRS 0x04198
1074#define IXGBE_BXONRXC 0x0419C
1075#define IXGBE_BXOFFRXC 0x041E0
1076#define IXGBE_BXONTXC 0x041E4
1077#define IXGBE_BXOFFTXC 0x041E8
1080#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4))
1081#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4))
1082#define IXGBE_MANC 0x05820
1083#define IXGBE_MFVAL 0x05824
1084#define IXGBE_MANC2H 0x05860
1085#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4))
1086#define IXGBE_MIPAF 0x058B0
1087#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8))
1088#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8))
1089#define IXGBE_FTFT 0x09400
1090#define IXGBE_METF(_i) (0x05190 + ((_i) * 4))
1091#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4))
1092#define IXGBE_LSWFW 0x15F14
1093#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4))
1094#define IXGBE_BMCIPVAL 0x05060
1095#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
1096#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
1099#define IXGBE_MANC_MPROXYE 0x40000000
1100#define IXGBE_MANC_RCV_TCO_EN 0x00020000
1101#define IXGBE_MANC_EN_BMC2OS 0x10000000
1102#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
1105#define IXGBE_FWSM_MODE_MASK 0xE
1106#define IXGBE_FWSM_TS_ENABLED 0x1
1107#define IXGBE_FWSM_FW_MODE_PT 0x4
1108#define IXGBE_FWSM_FW_NVM_RECOVERY_MODE (1 << 5)
1109#define IXGBE_FWSM_EXT_ERR_IND_MASK 0x01F80000
1110#define IXGBE_FWSM_FW_VAL_BIT (1 << 15)
1113#define IXGBE_HICR 0x15F00
1114#define IXGBE_FWSTS 0x15F0C
1115#define IXGBE_HSMC0R 0x15F04
1116#define IXGBE_HSMC1R 0x15F08
1117#define IXGBE_SWSR 0x15F10
1118#define IXGBE_FWRESETCNT 0x15F40
1119#define IXGBE_HFDR 0x15FE8
1120#define IXGBE_FLEX_MNG 0x15800
1121#define IXGBE_FLEX_MNG_PTR(_i) (IXGBE_FLEX_MNG + ((_i) * 4))
1123#define IXGBE_HICR_EN 0x01
1125#define IXGBE_HICR_C 0x02
1126#define IXGBE_HICR_SV 0x04
1127#define IXGBE_HICR_FW_RESET_ENABLE 0x40
1128#define IXGBE_HICR_FW_RESET 0x80
1131#define IXGBE_GCR 0x11000
1132#define IXGBE_GTV 0x11004
1133#define IXGBE_FUNCTAG 0x11008
1134#define IXGBE_GLT 0x1100C
1135#define IXGBE_PCIEPIPEADR 0x11004
1136#define IXGBE_PCIEPIPEDAT 0x11008
1137#define IXGBE_GSCL_1 0x11010
1138#define IXGBE_GSCL_2 0x11014
1139#define IXGBE_GSCL_1_X540 IXGBE_GSCL_1
1140#define IXGBE_GSCL_2_X540 IXGBE_GSCL_2
1141#define IXGBE_GSCL_3 0x11018
1142#define IXGBE_GSCL_4 0x1101C
1143#define IXGBE_GSCN_0 0x11020
1144#define IXGBE_GSCN_1 0x11024
1145#define IXGBE_GSCN_2 0x11028
1146#define IXGBE_GSCN_3 0x1102C
1147#define IXGBE_GSCN_0_X540 IXGBE_GSCN_0
1148#define IXGBE_GSCN_1_X540 IXGBE_GSCN_1
1149#define IXGBE_GSCN_2_X540 IXGBE_GSCN_2
1150#define IXGBE_GSCN_3_X540 IXGBE_GSCN_3
1151#define IXGBE_FACTPS 0x10150
1152#define IXGBE_FACTPS_X540 IXGBE_FACTPS
1153#define IXGBE_GSCL_1_X550 0x11800
1154#define IXGBE_GSCL_2_X550 0x11804
1155#define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550
1156#define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550
1157#define IXGBE_GSCN_0_X550 0x11820
1158#define IXGBE_GSCN_1_X550 0x11824
1159#define IXGBE_GSCN_2_X550 0x11828
1160#define IXGBE_GSCN_3_X550 0x1182C
1161#define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550
1162#define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550
1163#define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550
1164#define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550
1165#define IXGBE_FACTPS_X550 IXGBE_FACTPS
1166#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS
1167#define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550
1168#define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550
1169#define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550
1170#define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550
1171#define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550
1172#define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550
1173#define IXGBE_FACTPS_X550EM_a 0x15FEC
1174#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS)
1176#define IXGBE_PCIEANACTL 0x11040
1177#define IXGBE_SWSM 0x10140
1178#define IXGBE_SWSM_X540 IXGBE_SWSM
1179#define IXGBE_SWSM_X550 IXGBE_SWSM
1180#define IXGBE_SWSM_X550EM_x IXGBE_SWSM
1181#define IXGBE_SWSM_X550EM_a 0x15F70
1182#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM)
1184#define IXGBE_FWSM 0x10148
1185#define IXGBE_FWSM_X540 IXGBE_FWSM
1186#define IXGBE_FWSM_X550 IXGBE_FWSM
1187#define IXGBE_FWSM_X550EM_x IXGBE_FWSM
1188#define IXGBE_FWSM_X550EM_a 0x15F74
1189#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM)
1191#define IXGBE_SWFW_SYNC IXGBE_GSSR
1192#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC
1193#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC
1194#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC
1195#define IXGBE_SWFW_SYNC_X550EM_a 0x15F78
1196#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC)
1198#define IXGBE_GSSR 0x10160
1199#define IXGBE_MREVID 0x11064
1200#define IXGBE_DCA_ID 0x11070
1201#define IXGBE_DCA_CTRL 0x11074
1204#define IXGBE_GCR_EXT 0x11050
1205#define IXGBE_GSCL_5_82599 0x11030
1206#define IXGBE_GSCL_6_82599 0x11034
1207#define IXGBE_GSCL_7_82599 0x11038
1208#define IXGBE_GSCL_8_82599 0x1103C
1209#define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599
1210#define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599
1211#define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599
1212#define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599
1213#define IXGBE_PHYADR_82599 0x11040
1214#define IXGBE_PHYDAT_82599 0x11044
1215#define IXGBE_PHYCTL_82599 0x11048
1216#define IXGBE_PBACLR_82599 0x11068
1217#define IXGBE_CIAA 0x11088
1218#define IXGBE_CIAD 0x1108C
1219#define IXGBE_CIAA_82599 IXGBE_CIAA
1220#define IXGBE_CIAD_82599 IXGBE_CIAD
1221#define IXGBE_CIAA_X540 IXGBE_CIAA
1222#define IXGBE_CIAD_X540 IXGBE_CIAD
1223#define IXGBE_GSCL_5_X550 0x11810
1224#define IXGBE_GSCL_6_X550 0x11814
1225#define IXGBE_GSCL_7_X550 0x11818
1226#define IXGBE_GSCL_8_X550 0x1181C
1227#define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550
1228#define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550
1229#define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550
1230#define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550
1231#define IXGBE_CIAA_X550 0x11508
1232#define IXGBE_CIAD_X550 0x11510
1233#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
1234#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
1235#define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550
1236#define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550
1237#define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550
1238#define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550
1239#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
1240#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550
1241#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA)
1242#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD)
1243#define IXGBE_PICAUSE 0x110B0
1244#define IXGBE_PIENA 0x110B8
1245#define IXGBE_CDQ_MBR_82599 0x110B4
1246#define IXGBE_PCIESPARE 0x110BC
1247#define IXGBE_MISC_REG_82599 0x110F0
1248#define IXGBE_ECC_CTRL_0_82599 0x11100
1249#define IXGBE_ECC_CTRL_1_82599 0x11104
1250#define IXGBE_ECC_STATUS_82599 0x110E0
1251#define IXGBE_BAR_CTRL_82599 0x110F4
1254#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
1255#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
1256#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
1257#define IXGBE_GCR_CAP_VER2 0x00040000
1259#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
1260#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
1261#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
1262#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
1263#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
1264#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
1265 IXGBE_GCR_EXT_VT_MODE_64)
1266#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003
1268#define IXGBE_TSYNCRXCTL 0x05188
1269#define IXGBE_TSYNCTXCTL 0x08C00
1270#define IXGBE_RXSTMPL 0x051E8
1271#define IXGBE_RXSTMPH 0x051A4
1272#define IXGBE_RXSATRL 0x051A0
1273#define IXGBE_RXSATRH 0x051A8
1274#define IXGBE_RXMTRL 0x05120
1275#define IXGBE_TXSTMPL 0x08C04
1276#define IXGBE_TXSTMPH 0x08C08
1277#define IXGBE_SYSTIML 0x08C0C
1278#define IXGBE_SYSTIMH 0x08C10
1279#define IXGBE_SYSTIMR 0x08C58
1280#define IXGBE_TIMINCA 0x08C14
1281#define IXGBE_TIMADJL 0x08C18
1282#define IXGBE_TIMADJH 0x08C1C
1283#define IXGBE_TSAUXC 0x08C20
1284#define IXGBE_TRGTTIML0 0x08C24
1285#define IXGBE_TRGTTIMH0 0x08C28
1286#define IXGBE_TRGTTIML1 0x08C2C
1287#define IXGBE_TRGTTIMH1 0x08C30
1288#define IXGBE_CLKTIML 0x08C34
1289#define IXGBE_CLKTIMH 0x08C38
1290#define IXGBE_FREQOUT0 0x08C34
1291#define IXGBE_FREQOUT1 0x08C38
1292#define IXGBE_AUXSTMPL0 0x08C3C
1293#define IXGBE_AUXSTMPH0 0x08C40
1294#define IXGBE_AUXSTMPL1 0x08C44
1295#define IXGBE_AUXSTMPH1 0x08C48
1296#define IXGBE_TSIM 0x08C68
1297#define IXGBE_TSICR 0x08C60
1298#define IXGBE_TSSDP 0x0003C
1301#define IXGBE_RDSTATCTL 0x02C20
1302#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4))
1303#define IXGBE_RDHMPN 0x02F08
1304#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
1305#define IXGBE_RDPROBE 0x02F20
1306#define IXGBE_RDMAM 0x02F30
1307#define IXGBE_RDMAD 0x02F34
1308#define IXGBE_TDHMPN 0x07F08
1309#define IXGBE_TDHMPN2 0x082FC
1310#define IXGBE_TXDESCIC 0x082CC
1311#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
1312#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1313#define IXGBE_TDPROBE 0x07F20
1314#define IXGBE_TXBUFCTRL 0x0C600
1315#define IXGBE_TXBUFDATA0 0x0C610
1316#define IXGBE_TXBUFDATA1 0x0C614
1317#define IXGBE_TXBUFDATA2 0x0C618
1318#define IXGBE_TXBUFDATA3 0x0C61C
1319#define IXGBE_RXBUFCTRL 0x03600
1320#define IXGBE_RXBUFDATA0 0x03610
1321#define IXGBE_RXBUFDATA1 0x03614
1322#define IXGBE_RXBUFDATA2 0x03618
1323#define IXGBE_RXBUFDATA3 0x0361C
1324#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4))
1325#define IXGBE_RFVAL 0x050A4
1326#define IXGBE_MDFTC1 0x042B8
1327#define IXGBE_MDFTC2 0x042C0
1328#define IXGBE_MDFTFIFO1 0x042C4
1329#define IXGBE_MDFTFIFO2 0x042C8
1330#define IXGBE_MDFTS 0x042CC
1331#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4))
1332#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4))
1333#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4))
1334#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4))
1335#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4))
1336#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4))
1337#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4))
1338#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4))
1339#define IXGBE_PCIEECCCTL 0x1106C
1340#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4))
1341#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4))
1342#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4))
1343#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4))
1344#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4))
1345#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4))
1346#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4))
1347#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4))
1348#define IXGBE_PCIEECCCTL0 0x11100
1349#define IXGBE_PCIEECCCTL1 0x11104
1350#define IXGBE_RXDBUECC 0x03F70
1351#define IXGBE_TXDBUECC 0x0CF70
1352#define IXGBE_RXDBUEST 0x03F74
1353#define IXGBE_TXDBUEST 0x0CF74
1354#define IXGBE_PBTXECC 0x0C300
1355#define IXGBE_PBRXECC 0x03300
1356#define IXGBE_GHECCR 0x110B0
1359#define IXGBE_PCS1GCFIG 0x04200
1360#define IXGBE_PCS1GLCTL 0x04208
1361#define IXGBE_PCS1GLSTA 0x0420C
1362#define IXGBE_PCS1GDBG0 0x04210
1363#define IXGBE_PCS1GDBG1 0x04214
1364#define IXGBE_PCS1GANA 0x04218
1365#define IXGBE_PCS1GANLP 0x0421C
1366#define IXGBE_PCS1GANNP 0x04220
1367#define IXGBE_PCS1GANLPNP 0x04224
1368#define IXGBE_HLREG0 0x04240
1369#define IXGBE_HLREG1 0x04244
1370#define IXGBE_PAP 0x04248
1371#define IXGBE_MACA 0x0424C
1372#define IXGBE_APAE 0x04250
1373#define IXGBE_ARD 0x04254
1374#define IXGBE_AIS 0x04258
1375#define IXGBE_MSCA 0x0425C
1376#define IXGBE_MSRWD 0x04260
1377#define IXGBE_MLADD 0x04264
1378#define IXGBE_MHADD 0x04268
1379#define IXGBE_MAXFRS 0x04268
1380#define IXGBE_TREG 0x0426C
1381#define IXGBE_PCSS1 0x04288
1382#define IXGBE_PCSS2 0x0428C
1383#define IXGBE_XPCSS 0x04290
1384#define IXGBE_MFLCN 0x04294
1385#define IXGBE_SERDESC 0x04298
1386#define IXGBE_MAC_SGMII_BUSY 0x04298
1387#define IXGBE_MACS 0x0429C
1388#define IXGBE_AUTOC 0x042A0
1389#define IXGBE_LINKS 0x042A4
1390#define IXGBE_LINKS2 0x04324
1391#define IXGBE_AUTOC2 0x042A8
1392#define IXGBE_AUTOC3 0x042AC
1393#define IXGBE_ANLP1 0x042B0
1394#define IXGBE_ANLP2 0x042B4
1395#define IXGBE_MACC 0x04330
1396#define IXGBE_ATLASCTL 0x04800
1397#define IXGBE_MMNGC 0x042D0
1398#define IXGBE_ANLPNP1 0x042D4
1399#define IXGBE_ANLPNP2 0x042D8
1400#define IXGBE_KRPCSFC 0x042E0
1401#define IXGBE_KRPCSS 0x042E4
1402#define IXGBE_FECS1 0x042E8
1403#define IXGBE_FECS2 0x042EC
1404#define IXGBE_SMADARCTL 0x14F10
1405#define IXGBE_MPVC 0x04318
1406#define IXGBE_SGMIIC 0x04314
1409#define IXGBE_RXNFGPC 0x041B0
1410#define IXGBE_RXNFGBCL 0x041B4
1411#define IXGBE_RXNFGBCH 0x041B8
1412#define IXGBE_RXDGPC 0x02F50
1413#define IXGBE_RXDGBCL 0x02F54
1414#define IXGBE_RXDGBCH 0x02F58
1415#define IXGBE_RXDDGPC 0x02F5C
1416#define IXGBE_RXDDGBCL 0x02F60
1417#define IXGBE_RXDDGBCH 0x02F64
1418#define IXGBE_RXLPBKGPC 0x02F68
1419#define IXGBE_RXLPBKGBCL 0x02F6C
1420#define IXGBE_RXLPBKGBCH 0x02F70
1421#define IXGBE_RXDLPBKGPC 0x02F74
1422#define IXGBE_RXDLPBKGBCL 0x02F78
1423#define IXGBE_RXDLPBKGBCH 0x02F7C
1424#define IXGBE_TXDGPC 0x087A0
1425#define IXGBE_TXDGBCL 0x087A4
1426#define IXGBE_TXDGBCH 0x087A8
1428#define IXGBE_RXDSTATCTRL 0x02F40
1431#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1434#define IXGBE_CORECTL 0x014F00
1436#define IXGBE_BARCTRL 0x110F4
1437#define IXGBE_BARCTRL_FLSIZE 0x0700
1438#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
1439#define IXGBE_BARCTRL_CSRSIZE 0x2000
1442#define IXGBE_RSCCTL_RSCEN 0x01
1443#define IXGBE_RSCCTL_MAXDESC_1 0x00
1444#define IXGBE_RSCCTL_MAXDESC_4 0x04
1445#define IXGBE_RSCCTL_MAXDESC_8 0x08
1446#define IXGBE_RSCCTL_MAXDESC_16 0x0C
1447#define IXGBE_RSCCTL_TS_DIS 0x02
1450#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1451#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1454#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
1455#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002
1456#define IXGBE_RDRXCTL_PSP 0x00000004
1457#define IXGBE_RDRXCTL_MVMEN 0x00000020
1458#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020
1459#define IXGBE_RDRXCTL_DMAIDONE 0x00000008
1460#define IXGBE_RDRXCTL_RSC_PUSH 0x00000080
1461#define IXGBE_RDRXCTL_AGGDIS 0x00010000
1462#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
1463#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000
1464#define IXGBE_RDRXCTL_RSCACKC 0x02000000
1465#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000
1466#define IXGBE_RDRXCTL_MBINTEN 0x10000000
1467#define IXGBE_RDRXCTL_MDP_EN 0x20000000
1470#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1471#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1472#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1473#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1474#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1475#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1476#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1477#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1478#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1481#define IXGBE_PSRTYPE_RQPL_MASK 0x7
1482#define IXGBE_PSRTYPE_RQPL_SHIFT 29
1485#define IXGBE_CTRL_GIO_DIS 0x00000004
1486#define IXGBE_CTRL_LNK_RST 0x00000008
1487#define IXGBE_CTRL_RST 0x04000000
1488#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1491#define IXGBE_FACTPS_MNGCG 0x20000000
1492#define IXGBE_FACTPS_LFS 0x40000000
1495#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1496#define IXGBE_MHADD_MFS_SHIFT 16
1499#define IXGBE_CTRL_EXT_PFRSTD 0x00004000
1500#define IXGBE_CTRL_EXT_NS_DIS 0x00010000
1501#define IXGBE_CTRL_EXT_RO_DIS 0x00020000
1502#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000
1505#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000
1506#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001
1508#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00
1509#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02
1511#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F
1512#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000
1513#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24
1514#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5)
1515#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6)
1516#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7)
1517#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9)
1518#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13)
1519#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15)
1521#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F
1522#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000
1523#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24
1524#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5)
1525#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9)
1526#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11)
1527#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13)
1528#define IXGBE_DCA_MAX_QUEUES_82598 16
1531#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF
1532#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1533#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000
1534#define IXGBE_MSCA_DEV_TYPE_SHIFT 16
1535#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000
1536#define IXGBE_MSCA_PHY_ADDR_SHIFT 21
1537#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000
1538#define IXGBE_MSCA_OP_CODE_SHIFT 26
1539#define IXGBE_MSCA_ADDR_CYCLE 0x00000000
1540#define IXGBE_MSCA_WRITE 0x04000000
1541#define IXGBE_MSCA_READ 0x0C000000
1542#define IXGBE_MSCA_READ_AUTOINC 0x08000000
1543#define IXGBE_MSCA_ST_CODE_MASK 0x30000000
1544#define IXGBE_MSCA_ST_CODE_SHIFT 28
1545#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000
1546#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000
1547#define IXGBE_MSCA_MDI_COMMAND 0x40000000
1548#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000
1551#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1552#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1553#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1554#define IXGBE_MSRWD_READ_DATA_SHIFT 16
1557#define IXGBE_ATLAS_PDN_LPBK 0x24
1558#define IXGBE_ATLAS_PDN_10G 0xB
1559#define IXGBE_ATLAS_PDN_1G 0xC
1560#define IXGBE_ATLAS_PDN_AN 0xD
1563#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1564#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1565#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1566#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1567#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1570#define IXGBE_CORECTL_WRITE_CMD 0x00010000
1573#define IXGBE_MDIO_ZERO_DEV_TYPE 0x0
1574#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1575#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1576#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1577#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1578#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E
1579#define IXGBE_TWINAX_DEV 1
1581#define IXGBE_MDIO_COMMAND_TIMEOUT 100
1583#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0
1584#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1
1585#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008
1586#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010
1587#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1588#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1590#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0
1591#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1
1592#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800
1593#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00
1594#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01
1595#define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1
1596#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10
1597#define IXGBE_MDIO_AUTO_NEG_LP 0x13
1598#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C
1599#define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8
1600#define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4
1601#define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2
1602#define IXGBE_MDIO_PHY_XS_CONTROL 0x0
1603#define IXGBE_MDIO_PHY_XS_RESET 0x8000
1604#define IXGBE_MDIO_PHY_ID_HIGH 0x2
1605#define IXGBE_MDIO_PHY_ID_LOW 0x3
1606#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4
1607#define IXGBE_MDIO_PHY_SPEED_10G 0x0001
1608#define IXGBE_MDIO_PHY_SPEED_1G 0x0010
1609#define IXGBE_MDIO_PHY_SPEED_100M 0x0020
1610#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB
1611#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004
1612#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020
1613#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080
1614#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800
1615#define IXGBE_AUTO_NEG_LP_STATUS 0xE820
1616#define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000
1617#define IXGBE_AUTO_NEG_LP_10GBASE_CAP 0x0800
1618#define IXGBE_AUTO_NEG_10GBASET_STAT 0x0021
1620#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02
1621#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3
1622#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479
1623#define IXGBE_MDIO_POWER_UP_STALL 0x8000
1624#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00
1625#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00
1626#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01
1627#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01
1628#define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00
1629#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010
1630#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000
1631#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850
1632#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007
1633#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400
1634#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000
1635#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4
1636#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1
1637#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200
1638#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000
1639#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010
1640#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000
1641#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A
1642#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B
1643#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C
1644#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401
1645#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1
1646#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9
1647#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001
1649#define IXGBE_PCRC8ECL 0x0E810
1650#define IXGBE_PCRC8ECH 0x0E811
1651#define IXGBE_PCRC8ECH_MASK 0x1F
1652#define IXGBE_LDPCECL 0x0E820
1653#define IXGBE_LDPCECH 0x0E821
1656#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
1658#define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005
1659#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1
1661#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4
1663#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7
1664#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6
1665#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0
1666#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1
1667#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2
1668#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3
1669#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4
1670#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5
1671#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6
1672#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7
1673#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4
1674#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6
1676#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20
1677#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400
1678#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17
1679#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10
1680#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000
1681#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000
1682#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000
1683#define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400
1684#define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800
1685#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100
1686#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080
1687#define IXGBE_MII_RESTART 0x200
1688#define IXGBE_MII_AUTONEG_COMPLETE 0x20
1689#define IXGBE_MII_AUTONEG_LINK_UP 0x04
1690#define IXGBE_MII_AUTONEG_REG 0x0
1692#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1693#define IXGBE_MAX_PHY_ADDR 32
1696#define TN1010_PHY_ID 0x00A19410
1697#define TNX_FW_REV 0xB
1698#define X540_PHY_ID 0x01540200
1699#define X550_PHY_ID2 0x01540223
1700#define X550_PHY_ID3 0x01540221
1701#define X557_PHY_ID 0x01540240
1702#define X557_PHY_ID2 0x01540250
1703#define AQ_FW_REV 0x20
1704#define QT2022_PHY_ID 0x0043A400
1705#define ATH_PHY_ID 0x03429050
1708#define IXGBE_M88E1500_E_PHY_ID 0x01410DD0
1709#define IXGBE_M88E1543_E_PHY_ID 0x01410EA0
1712#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1713#define IXGBE_PHY_INIT_END_NL 0xFFFF
1714#define IXGBE_CONTROL_MASK_NL 0xF000
1715#define IXGBE_DATA_MASK_NL 0x0FFF
1716#define IXGBE_CONTROL_SHIFT_NL 12
1717#define IXGBE_DELAY_NL 0
1718#define IXGBE_DATA_NL 1
1719#define IXGBE_CONTROL_NL 0x000F
1720#define IXGBE_CONTROL_EOL_NL 0x0FFF
1721#define IXGBE_CONTROL_SOL_NL 0x0000
1724#define IXGBE_SDP0_GPIEN 0x00000001
1725#define IXGBE_SDP1_GPIEN 0x00000002
1726#define IXGBE_SDP2_GPIEN 0x00000004
1727#define IXGBE_SDP0_GPIEN_X540 0x00000002
1728#define IXGBE_SDP1_GPIEN_X540 0x00000004
1729#define IXGBE_SDP2_GPIEN_X540 0x00000008
1730#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
1731#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
1732#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
1733#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
1734#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
1735#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540
1736#define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540
1737#define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540
1738#define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540
1739#define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1740#define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1741#define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1743#define IXGBE_GPIE_MSIX_MODE 0x00000010
1744#define IXGBE_GPIE_OCD 0x00000020
1745#define IXGBE_GPIE_EIMEN 0x00000040
1746#define IXGBE_GPIE_EIAME 0x40000000
1747#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1748#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1749#define IXGBE_GPIE_VTMODE_MASK 0x0000C000
1750#define IXGBE_GPIE_VTMODE_16 0x00004000
1751#define IXGBE_GPIE_VTMODE_32 0x00008000
1752#define IXGBE_GPIE_VTMODE_64 0x0000C000
1755#define IXGBE_MAX_PACKET_BUFFERS 8
1757#define IXGBE_TXPBSIZE_20KB 0x00005000
1758#define IXGBE_TXPBSIZE_40KB 0x0000A000
1759#define IXGBE_RXPBSIZE_48KB 0x0000C000
1760#define IXGBE_RXPBSIZE_64KB 0x00010000
1761#define IXGBE_RXPBSIZE_80KB 0x00014000
1762#define IXGBE_RXPBSIZE_128KB 0x00020000
1763#define IXGBE_RXPBSIZE_MAX 0x00080000
1764#define IXGBE_TXPBSIZE_MAX 0x00028000
1766#define IXGBE_TXPKT_SIZE_MAX 0xA
1767#define IXGBE_MAX_PB 8
1772#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1774#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1778#define IXGBE_TFCS_TXOFF 0x00000001
1779#define IXGBE_TFCS_TXOFF0 0x00000100
1780#define IXGBE_TFCS_TXOFF1 0x00000200
1781#define IXGBE_TFCS_TXOFF2 0x00000400
1782#define IXGBE_TFCS_TXOFF3 0x00000800
1783#define IXGBE_TFCS_TXOFF4 0x00001000
1784#define IXGBE_TFCS_TXOFF5 0x00002000
1785#define IXGBE_TFCS_TXOFF6 0x00004000
1786#define IXGBE_TFCS_TXOFF7 0x00008000
1789#define IXGBE_TCPTIMER_KS 0x00000100
1790#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1791#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1792#define IXGBE_TCPTIMER_LOOP 0x00000800
1793#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1796#define IXGBE_HLREG0_TXCRCEN 0x00000001
1797#define IXGBE_HLREG0_RXCRCSTRP 0x00000002
1798#define IXGBE_HLREG0_JUMBOEN 0x00000004
1799#define IXGBE_HLREG0_TXPADEN 0x00000400
1800#define IXGBE_HLREG0_TXPAUSEEN 0x00001000
1801#define IXGBE_HLREG0_RXPAUSEEN 0x00004000
1802#define IXGBE_HLREG0_LPBK 0x00008000
1803#define IXGBE_HLREG0_MDCSPD 0x00010000
1804#define IXGBE_HLREG0_CONTMDC 0x00020000
1805#define IXGBE_HLREG0_CTRLFLTR 0x00040000
1806#define IXGBE_HLREG0_PREPEND 0x00F00000
1807#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000
1808#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000
1809#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000
1810#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000
1813#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1814#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1817#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000
1818#define IXGBE_VT_CTL_REPLEN 0x40000000
1819#define IXGBE_VT_CTL_VT_ENABLE 0x00000001
1820#define IXGBE_VT_CTL_POOL_SHIFT 7
1821#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1824#define IXGBE_VMOLR_UPE 0x00400000
1825#define IXGBE_VMOLR_VPE 0x00800000
1826#define IXGBE_VMOLR_AUPE 0x01000000
1827#define IXGBE_VMOLR_ROMPE 0x02000000
1828#define IXGBE_VMOLR_ROPE 0x04000000
1829#define IXGBE_VMOLR_BAM 0x08000000
1830#define IXGBE_VMOLR_MPE 0x10000000
1833#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1835#define IXGBE_VF_INIT_TIMEOUT 200
1838#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1839#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1840#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1841#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1842#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1843#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1845#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1846#define IXGBE_RDMAM_DWORD_SHIFT 9
1847#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1848#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1849#define IXGBE_RDMAM_RSC_HEADER_ADDR 3
1850#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1851#define IXGBE_RDMAM_WB_COLL_FIFO 5
1852#define IXGBE_RDMAM_QSC_CNT_RAM 6
1853#define IXGBE_RDMAM_QSC_FCOE_RAM 7
1854#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1855#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1856#define IXGBE_RDMAM_QSC_RSC_RAM 0xB
1857#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1858#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1859#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1860#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1861#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
1862#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
1863#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1864#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1865#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1866#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1867#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1868#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1869#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
1870#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
1871#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1872#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1873#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1874#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1875#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
1876#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
1878#define IXGBE_TXDESCIC_READY 0x80000000
1881#define IXGBE_RXCSUM_IPPCSE 0x00001000
1882#define IXGBE_RXCSUM_PCSD 0x00002000
1885#define IXGBE_FCRTL_XONE 0x80000000
1886#define IXGBE_FCRTH_FCEN 0x80000000
1889#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF
1892#define IXGBE_RMCS_RRM 0x00000002
1894#define IXGBE_RMCS_RAC 0x00000004
1896#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
1897#define IXGBE_RMCS_TFCE_802_3X 0x00000008
1898#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010
1899#define IXGBE_RMCS_ARBDIS 0x00000040
1902#define IXGBE_FCCFG_TFCE_802_3X 0x00000008
1903#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010
1908#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF
1909#define IXGBE_EICR_FLOW_DIR 0x00010000
1910#define IXGBE_EICR_RX_MISS 0x00020000
1911#define IXGBE_EICR_PCI 0x00040000
1912#define IXGBE_EICR_MAILBOX 0x00080000
1913#define IXGBE_EICR_LSC 0x00100000
1914#define IXGBE_EICR_LINKSEC 0x00200000
1915#define IXGBE_EICR_MNG 0x00400000
1916#define IXGBE_EICR_TS 0x00800000
1917#define IXGBE_EICR_TIMESYNC 0x01000000
1918#define IXGBE_EICR_GPI_SDP0 0x01000000
1919#define IXGBE_EICR_GPI_SDP1 0x02000000
1920#define IXGBE_EICR_GPI_SDP2 0x04000000
1921#define IXGBE_EICR_ECC 0x10000000
1922#define IXGBE_EICR_GPI_SDP0_X540 0x02000000
1923#define IXGBE_EICR_GPI_SDP1_X540 0x04000000
1924#define IXGBE_EICR_GPI_SDP2_X540 0x08000000
1925#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
1926#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
1927#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
1928#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
1929#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
1930#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540
1931#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540
1932#define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540
1933#define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540
1934#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1935#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1936#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1938#define IXGBE_EICR_PBUR 0x10000000
1939#define IXGBE_EICR_DHER 0x20000000
1940#define IXGBE_EICR_TCP_TIMER 0x40000000
1941#define IXGBE_EICR_OTHER 0x80000000
1944#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1945#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1946#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS
1947#define IXGBE_EICS_PCI IXGBE_EICR_PCI
1948#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX
1949#define IXGBE_EICS_LSC IXGBE_EICR_LSC
1950#define IXGBE_EICS_MNG IXGBE_EICR_MNG
1951#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC
1952#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0
1953#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1
1954#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2
1955#define IXGBE_EICS_ECC IXGBE_EICR_ECC
1956#define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1957#define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1958#define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1959#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR
1960#define IXGBE_EICS_DHER IXGBE_EICR_DHER
1961#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1962#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER
1965#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1966#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1967#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS
1968#define IXGBE_EIMS_PCI IXGBE_EICR_PCI
1969#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX
1970#define IXGBE_EIMS_LSC IXGBE_EICR_LSC
1971#define IXGBE_EIMS_MNG IXGBE_EICR_MNG
1972#define IXGBE_EIMS_TS IXGBE_EICR_TS
1973#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC
1974#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0
1975#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1
1976#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2
1977#define IXGBE_EIMS_ECC IXGBE_EICR_ECC
1978#define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
1979#define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
1980#define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
1981#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR
1982#define IXGBE_EIMS_DHER IXGBE_EICR_DHER
1983#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1984#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER
1987#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1988#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR
1989#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS
1990#define IXGBE_EIMC_PCI IXGBE_EICR_PCI
1991#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX
1992#define IXGBE_EIMC_LSC IXGBE_EICR_LSC
1993#define IXGBE_EIMC_MNG IXGBE_EICR_MNG
1994#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC
1995#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0
1996#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1
1997#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2
1998#define IXGBE_EIMC_ECC IXGBE_EICR_ECC
1999#define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)
2000#define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)
2001#define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)
2002#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR
2003#define IXGBE_EIMC_DHER IXGBE_EICR_DHER
2004#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER
2005#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER
2007#define IXGBE_EIMS_ENABLE_MASK ( \
2008 IXGBE_EIMS_RTX_QUEUE | \
2010 IXGBE_EIMS_TCP_TIMER | \
2014#define IXGBE_IMIR_PORT_IM_EN 0x00010000
2015#define IXGBE_IMIR_PORT_BP 0x00020000
2016#define IXGBE_IMIREXT_SIZE_BP 0x00001000
2017#define IXGBE_IMIREXT_CTRL_URG 0x00002000
2018#define IXGBE_IMIREXT_CTRL_ACK 0x00004000
2019#define IXGBE_IMIREXT_CTRL_PSH 0x00008000
2020#define IXGBE_IMIREXT_CTRL_RST 0x00010000
2021#define IXGBE_IMIREXT_CTRL_SYN 0x00020000
2022#define IXGBE_IMIREXT_CTRL_FIN 0x00040000
2023#define IXGBE_IMIREXT_CTRL_BP 0x00080000
2024#define IXGBE_IMIR_SIZE_BP_82599 0x00001000
2025#define IXGBE_IMIR_CTRL_URG_82599 0x00002000
2026#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000
2027#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000
2028#define IXGBE_IMIR_CTRL_RST_82599 0x00010000
2029#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000
2030#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000
2031#define IXGBE_IMIR_CTRL_BP_82599 0x00080000
2032#define IXGBE_IMIR_LLI_EN_82599 0x00100000
2033#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F
2034#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21
2035#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007
2036#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008
2038#define IXGBE_MAX_FTQF_FILTERS 128
2039#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
2040#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
2041#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
2042#define IXGBE_FTQF_PROTOCOL_SCTP 2
2043#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
2044#define IXGBE_FTQF_PRIORITY_SHIFT 2
2045#define IXGBE_FTQF_POOL_MASK 0x0000003F
2046#define IXGBE_FTQF_POOL_SHIFT 8
2047#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
2048#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
2049#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
2050#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
2051#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
2052#define IXGBE_FTQF_DEST_PORT_MASK 0x17
2053#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
2054#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
2055#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
2058#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
2061#define IXGBE_IVAR_REG_NUM 25
2062#define IXGBE_IVAR_REG_NUM_82599 64
2063#define IXGBE_IVAR_TXRX_ENTRY 96
2064#define IXGBE_IVAR_RX_ENTRY 64
2065#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
2066#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
2067#define IXGBE_IVAR_TX_ENTRY 32
2069#define IXGBE_IVAR_TCP_TIMER_INDEX 96
2070#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97
2072#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
2074#define IXGBE_IVAR_ALLOC_VAL 0x80
2077#define IXGBE_MAX_ETQF_FILTERS 8
2078#define IXGBE_ETQF_FCOE 0x08000000
2079#define IXGBE_ETQF_BCN 0x10000000
2080#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000
2081#define IXGBE_ETQF_1588 0x40000000
2082#define IXGBE_ETQF_FILTER_EN 0x80000000
2083#define IXGBE_ETQF_POOL_ENABLE (1 << 26)
2084#define IXGBE_ETQF_POOL_SHIFT 20
2086#define IXGBE_ETQS_RX_QUEUE 0x007F0000
2087#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
2088#define IXGBE_ETQS_LLI 0x20000000
2089#define IXGBE_ETQS_QUEUE_EN 0x80000000
2105#define IXGBE_ETQF_FILTER_EAPOL 0
2106#define IXGBE_ETQF_FILTER_FCOE 2
2107#define IXGBE_ETQF_FILTER_1588 3
2108#define IXGBE_ETQF_FILTER_FIP 4
2109#define IXGBE_ETQF_FILTER_LLDP 5
2110#define IXGBE_ETQF_FILTER_LACP 6
2111#define IXGBE_ETQF_FILTER_FC 7
2113#define IXGBE_VLNCTRL_VET 0x0000FFFF
2114#define IXGBE_VLNCTRL_CFI 0x10000000
2115#define IXGBE_VLNCTRL_CFIEN 0x20000000
2116#define IXGBE_VLNCTRL_VFE 0x40000000
2117#define IXGBE_VLNCTRL_VME 0x80000000
2120#define IXGBE_VLVF_VIEN 0x80000000
2121#define IXGBE_VLVF_ENTRIES 64
2122#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
2124#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000
2125#define IXGBE_VMVIR_VLANA_NEVER 0x80000000
2127#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100
2130#define IXGBE_STATUS_LAN_ID 0x0000000C
2131#define IXGBE_STATUS_LAN_ID_SHIFT 2
2132#define IXGBE_STATUS_GIO 0x00080000
2134#define IXGBE_STATUS_LAN_ID_0 0x00000000
2135#define IXGBE_STATUS_LAN_ID_1 0x00000004
2138#define IXGBE_ESDP_SDP0 0x00000001
2139#define IXGBE_ESDP_SDP1 0x00000002
2140#define IXGBE_ESDP_SDP2 0x00000004
2141#define IXGBE_ESDP_SDP3 0x00000008
2142#define IXGBE_ESDP_SDP4 0x00000010
2143#define IXGBE_ESDP_SDP5 0x00000020
2144#define IXGBE_ESDP_SDP6 0x00000040
2145#define IXGBE_ESDP_SDP7 0x00000080
2146#define IXGBE_ESDP_SDP0_DIR 0x00000100
2147#define IXGBE_ESDP_SDP1_DIR 0x00000200
2148#define IXGBE_ESDP_SDP2_DIR 0x00000400
2149#define IXGBE_ESDP_SDP3_DIR 0x00000800
2150#define IXGBE_ESDP_SDP4_DIR 0x00001000
2151#define IXGBE_ESDP_SDP5_DIR 0x00002000
2152#define IXGBE_ESDP_SDP6_DIR 0x00004000
2153#define IXGBE_ESDP_SDP7_DIR 0x00008000
2154#define IXGBE_ESDP_SDP0_NATIVE 0x00010000
2155#define IXGBE_ESDP_SDP1_NATIVE 0x00020000
2159#define IXGBE_LED_IVRT_BASE 0x00000040
2160#define IXGBE_LED_BLINK_BASE 0x00000080
2161#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
2162#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
2163#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
2164#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
2165#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
2166#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
2167#define IXGBE_X557_LED_MANUAL_SET_MASK (1 << 8)
2168#define IXGBE_X557_MAX_LED_INDEX 3
2169#define IXGBE_X557_LED_PROVISIONING 0xC430
2172#define IXGBE_LED_LINK_UP 0x0
2173#define IXGBE_LED_LINK_10G 0x1
2174#define IXGBE_LED_MAC 0x2
2175#define IXGBE_LED_FILTER 0x3
2176#define IXGBE_LED_LINK_ACTIVE 0x4
2177#define IXGBE_LED_LINK_1G 0x5
2178#define IXGBE_LED_ON 0xE
2179#define IXGBE_LED_OFF 0xF
2182#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
2183#define IXGBE_AUTOC_KX4_SUPP 0x80000000
2184#define IXGBE_AUTOC_KX_SUPP 0x40000000
2185#define IXGBE_AUTOC_PAUSE 0x30000000
2186#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
2187#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
2188#define IXGBE_AUTOC_RF 0x08000000
2189#define IXGBE_AUTOC_PD_TMR 0x06000000
2190#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
2191#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
2192#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
2193#define IXGBE_AUTOC_FECA 0x00040000
2194#define IXGBE_AUTOC_FECR 0x00020000
2195#define IXGBE_AUTOC_KR_SUPP 0x00010000
2196#define IXGBE_AUTOC_AN_RESTART 0x00001000
2197#define IXGBE_AUTOC_FLU 0x00000001
2198#define IXGBE_AUTOC_LMS_SHIFT 13
2199#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
2200#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
2201#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
2202#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
2203#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2204#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
2205#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
2206#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
2207#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
2208#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
2209#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
2210#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2212#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
2213#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
2214#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
2215#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
2216#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2217#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2218#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
2219#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2220#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2221#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2222#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
2224#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
2225#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
2226#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
2227#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2228#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2229#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
2230#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
2231#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
2233#define IXGBE_MACC_FLU 0x00000001
2234#define IXGBE_MACC_FSV_10G 0x00030000
2235#define IXGBE_MACC_FS 0x00040000
2236#define IXGBE_MAC_RX2TX_LPBK 0x00000002
2239#define IXGBE_MMNGC_MNG_VETO 0x00000001
2242#define IXGBE_LINKS_KX_AN_COMP 0x80000000
2243#define IXGBE_LINKS_UP 0x40000000
2244#define IXGBE_LINKS_SPEED 0x20000000
2245#define IXGBE_LINKS_MODE 0x18000000
2246#define IXGBE_LINKS_RX_MODE 0x06000000
2247#define IXGBE_LINKS_TX_MODE 0x01800000
2248#define IXGBE_LINKS_XGXS_EN 0x00400000
2249#define IXGBE_LINKS_SGMII_EN 0x02000000
2250#define IXGBE_LINKS_PCS_1G_EN 0x00200000
2251#define IXGBE_LINKS_1G_AN_EN 0x00100000
2252#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
2253#define IXGBE_LINKS_1G_SYNC 0x00040000
2254#define IXGBE_LINKS_10G_ALIGN 0x00020000
2255#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
2256#define IXGBE_LINKS_TL_FAULT 0x00001000
2257#define IXGBE_LINKS_SIGNAL 0x00000F00
2259#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
2260#define IXGBE_LINKS_SPEED_82599 0x30000000
2261#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
2262#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
2263#define IXGBE_LINKS_SPEED_100_82599 0x10000000
2264#define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000
2265#define IXGBE_LINK_UP_TIME 90
2266#define IXGBE_AUTO_NEG_TIME 45
2268#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
2271#define IXGBE_PCS1GLSTA_LINK_OK 1
2272#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
2273#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
2274#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
2275#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
2276#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
2277#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
2279#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
2280#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
2283#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000
2284#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
2285#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
2286#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
2287#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
2288#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
2291#define IXGBE_ANLP1_PAUSE 0x0C00
2292#define IXGBE_ANLP1_SYM_PAUSE 0x0400
2293#define IXGBE_ANLP1_ASM_PAUSE 0x0800
2294#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
2297#define IXGBE_SWSM_SMBI 0x00000001
2298#define IXGBE_SWSM_SWESMBI 0x00000002
2299#define IXGBE_SWSM_WMNG 0x00000004
2300#define IXGBE_SWFW_REGSMP 0x80000000
2303#define IXGBE_GSSR_EEP_SM 0x0001
2304#define IXGBE_GSSR_PHY0_SM 0x0002
2305#define IXGBE_GSSR_PHY1_SM 0x0004
2306#define IXGBE_GSSR_MAC_CSR_SM 0x0008
2307#define IXGBE_GSSR_FLASH_SM 0x0010
2308#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
2309#define IXGBE_GSSR_SW_MNG_SM 0x0400
2310#define IXGBE_GSSR_TOKEN_SM 0x40000000
2311#define IXGBE_GSSR_SHARED_I2C_SM 0x1806
2312#define IXGBE_GSSR_I2C_MASK 0x1800
2313#define IXGBE_GSSR_NVM_PHY_MASK 0xF
2316#define IXGBE_FWSTS_FWRI 0x00000200
2319#define IXGBE_EEC_SK 0x00000001
2320#define IXGBE_EEC_CS 0x00000002
2321#define IXGBE_EEC_DI 0x00000004
2322#define IXGBE_EEC_DO 0x00000008
2323#define IXGBE_EEC_FWE_MASK 0x00000030
2324#define IXGBE_EEC_FWE_DIS 0x00000010
2325#define IXGBE_EEC_FWE_EN 0x00000020
2326#define IXGBE_EEC_FWE_SHIFT 4
2327#define IXGBE_EEC_REQ 0x00000040
2328#define IXGBE_EEC_GNT 0x00000080
2329#define IXGBE_EEC_PRES 0x00000100
2330#define IXGBE_EEC_ARD 0x00000200
2331#define IXGBE_EEC_FLUP 0x00800000
2332#define IXGBE_EEC_SEC1VAL 0x02000000
2333#define IXGBE_EEC_FLUDONE 0x04000000
2335#define IXGBE_EEC_ADDR_SIZE 0x00000400
2336#define IXGBE_EEC_SIZE 0x00007800
2337#define IXGBE_EERD_MAX_ADDR 0x00003FFF
2339#define IXGBE_EEC_SIZE_SHIFT 11
2340#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
2341#define IXGBE_EEPROM_OPCODE_BITS 8
2344#define IXGBE_FLA_LOCKED 0x00000040
2347#define IXGBE_PBANUM_LENGTH 11
2350#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
2351#define IXGBE_EEPROM_CHECKSUM 0x3F
2352#define IXGBE_EEPROM_SUM 0xBABA
2353#define IXGBE_EEPROM_CTRL_4 0x45
2354#define IXGBE_EE_CTRL_4_INST_ID 0x10
2355#define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4
2356#define IXGBE_PCIE_ANALOG_PTR 0x03
2357#define IXGBE_ATLAS0_CONFIG_PTR 0x04
2358#define IXGBE_PHY_PTR 0x04
2359#define IXGBE_ATLAS1_CONFIG_PTR 0x05
2360#define IXGBE_OPTION_ROM_PTR 0x05
2361#define IXGBE_PCIE_GENERAL_PTR 0x06
2362#define IXGBE_PCIE_CONFIG0_PTR 0x07
2363#define IXGBE_PCIE_CONFIG1_PTR 0x08
2364#define IXGBE_CORE0_PTR 0x09
2365#define IXGBE_CORE1_PTR 0x0A
2366#define IXGBE_MAC0_PTR 0x0B
2367#define IXGBE_MAC1_PTR 0x0C
2368#define IXGBE_CSR0_CONFIG_PTR 0x0D
2369#define IXGBE_CSR1_CONFIG_PTR 0x0E
2370#define IXGBE_PCIE_ANALOG_PTR_X550 0x02
2371#define IXGBE_SHADOW_RAM_SIZE_X550 0x4000
2372#define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24
2373#define IXGBE_PCIE_CONFIG_SIZE 0x08
2374#define IXGBE_EEPROM_LAST_WORD 0x41
2375#define IXGBE_FW_PTR 0x0F
2376#define IXGBE_PBANUM0_PTR 0x15
2377#define IXGBE_PBANUM1_PTR 0x16
2378#define IXGBE_ALT_MAC_ADDR_PTR 0x37
2379#define IXGBE_FREE_SPACE_PTR 0X3E
2382#define IXGBE_ETS_CFG 0x26
2383#define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0
2384#define IXGBE_ETS_LTHRES_DELTA_SHIFT 6
2385#define IXGBE_ETS_TYPE_MASK 0x0038
2386#define IXGBE_ETS_TYPE_SHIFT 3
2387#define IXGBE_ETS_TYPE_EMC 0x000
2388#define IXGBE_ETS_NUM_SENSORS_MASK 0x0007
2389#define IXGBE_ETS_DATA_LOC_MASK 0x3C00
2390#define IXGBE_ETS_DATA_LOC_SHIFT 10
2391#define IXGBE_ETS_DATA_INDEX_MASK 0x0300
2392#define IXGBE_ETS_DATA_INDEX_SHIFT 8
2393#define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF
2395#define IXGBE_SAN_MAC_ADDR_PTR 0x28
2396#define IXGBE_DEVICE_CAPS 0x2C
2397#define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11
2398#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04
2400#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
2401#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
2402#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
2403#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
2406#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
2409#define IXGBE_ISCSI_BOOT_CAPS 0x0033
2410#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
2411#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
2414#define IXGBE_EEPROM_MAX_RETRY_SPI 5000
2415#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
2416#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03
2417#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02
2418#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08
2419#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06
2421#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
2422#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05
2423#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01
2424#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20
2425#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8
2426#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB
2429#define IXGBE_EEPROM_RW_REG_DATA 16
2430#define IXGBE_EEPROM_RW_REG_DONE 2
2431#define IXGBE_EEPROM_RW_REG_START 1
2432#define IXGBE_EEPROM_RW_ADDR_SHIFT 2
2433#define IXGBE_NVM_POLL_WRITE 1
2434#define IXGBE_NVM_POLL_READ 0
2436#define NVM_INIT_CTRL_3 0x38
2437#define NVM_INIT_CTRL_3_LPLU 0x8
2438#define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2439#define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2441#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
2443#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
2444#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256
2445#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256
2446#define IXGBE_EEPROM_CTRL_2 1
2447#define IXGBE_EEPROM_CCD_BIT 2
2449#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000
2453#define IXGBE_EERD_EEWR_ATTEMPTS 100000
2456#define IXGBE_FLUDONE_ATTEMPTS 20000
2458#define IXGBE_PCIE_CTRL2 0x5
2459#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8
2460#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2
2461#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1
2463#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
2464#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2465#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2466#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
2467#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7)
2468#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2469#define IXGBE_FW_LESM_STATE_1 0x1
2470#define IXGBE_FW_LESM_STATE_ENABLED 0x8000
2471#define IXGBE_FW_LESM_2_STATES_ENABLED_MASK 0x1F
2472#define IXGBE_FW_LESM_2_STATES_ENABLED 0x12
2473#define IXGBE_FW_LESM_STATE0_10G_ENABLED 0x6FFF
2474#define IXGBE_FW_LESM_STATE1_10G_ENABLED 0x4FFF
2475#define IXGBE_FW_LESM_STATE0_10G_DISABLED 0x0FFF
2476#define IXGBE_FW_LESM_STATE1_10G_DISABLED 0x2FFF
2477#define IXGBE_FW_LESM_PORT0_STATE0_OFFSET 0x2
2478#define IXGBE_FW_LESM_PORT0_STATE1_OFFSET 0x3
2479#define IXGBE_FW_LESM_PORT1_STATE0_OFFSET 0x6
2480#define IXGBE_FW_LESM_PORT1_STATE1_OFFSET 0x7
2481#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2482#define IXGBE_FW_PATCH_VERSION_4 0x7
2483#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33
2484#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20
2485#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17
2486#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0
2487#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1
2488#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27
2489#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0
2490#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1
2491#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4
2492#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7
2493#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8
2494#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0
2495#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1
2498#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2499#define IXGBE_X540_FW_MODULE_MASK 0x7FFF
2501#define IXGBE_X540_FW_MODULE_LENGTH 0x1000
2503#define IXGBE_X540_FW_PATCH_VERSION_2 0x5
2505#define IXGBE_X540_FW_PATCH_VERSION_3 0x6
2507#define IXGBE_X540_FW_PATCH_VERSION_4 0x7
2509#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4
2510#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8
2511#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC
2514#define IXGBE_PCI_DEVICE_STATUS 0xAA
2515#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
2516#define IXGBE_PCI_LINK_STATUS 0xB2
2517#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2518#define IXGBE_PCI_LINK_WIDTH 0x3F0
2519#define IXGBE_PCI_LINK_WIDTH_1 0x10
2520#define IXGBE_PCI_LINK_WIDTH_2 0x20
2521#define IXGBE_PCI_LINK_WIDTH_4 0x40
2522#define IXGBE_PCI_LINK_WIDTH_8 0x80
2523#define IXGBE_PCI_LINK_SPEED 0xF
2524#define IXGBE_PCI_LINK_SPEED_2500 0x1
2525#define IXGBE_PCI_LINK_SPEED_5000 0x2
2526#define IXGBE_PCI_LINK_SPEED_8000 0x3
2527#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
2528#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2529#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
2531#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
2532#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
2533#define IXGBE_PCIDEVCTRL2_50_100us 0x1
2534#define IXGBE_PCIDEVCTRL2_1_2ms 0x2
2535#define IXGBE_PCIDEVCTRL2_16_32ms 0x5
2536#define IXGBE_PCIDEVCTRL2_65_130ms 0x6
2537#define IXGBE_PCIDEVCTRL2_260_520ms 0x9
2538#define IXGBE_PCIDEVCTRL2_1_2s 0xa
2539#define IXGBE_PCIDEVCTRL2_4_8s 0xd
2540#define IXGBE_PCIDEVCTRL2_17_34s 0xe
2543#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
2546#define IXGBE_IS_MULTICAST(Address) \
2547 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
2550#define IXGBE_IS_BROADCAST(Address) \
2551 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
2552 (((u8 *)(Address))[1] == ((u8)0xff)))
2555#define IXGBE_RAH_VIND_MASK 0x003C0000
2556#define IXGBE_RAH_VIND_SHIFT 18
2557#define IXGBE_RAH_AV 0x80000000
2558#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
2561#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
2562#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
2563#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2564#define IXGBE_RFCTL_RSC_DIS 0x00000020
2565#define IXGBE_RFCTL_NFSW_DIS 0x00000040
2566#define IXGBE_RFCTL_NFSR_DIS 0x00000080
2567#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
2568#define IXGBE_RFCTL_NFS_VER_SHIFT 8
2569#define IXGBE_RFCTL_NFS_VER_2 0
2570#define IXGBE_RFCTL_NFS_VER_3 1
2571#define IXGBE_RFCTL_NFS_VER_4 2
2572#define IXGBE_RFCTL_IPV6_DIS 0x00000400
2573#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
2574#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
2575#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
2576#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2579#define IXGBE_TXDCTL_ENABLE 0x02000000
2580#define IXGBE_TXDCTL_SWFLSH 0x04000000
2581#define IXGBE_TXDCTL_WTHRESH_SHIFT 16
2583#define IXGBE_TX_PAD_ENABLE 0x00000400
2584#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004
2586#define IXGBE_MAX_FRAME_SZ 0x40040000
2588#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1
2589#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2
2592#define IXGBE_RXCTRL_RXEN 0x00000001
2593#define IXGBE_RXCTRL_DMBYPS 0x00000002
2594#define IXGBE_RXDCTL_ENABLE 0x02000000
2595#define IXGBE_RXDCTL_SWFLSH 0x04000000
2596#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF
2597#define IXGBE_RXDCTL_RLPML_EN 0x00008000
2598#define IXGBE_RXDCTL_VME 0x40000000
2600#define IXGBE_TSAUXC_EN_CLK 0x00000004
2601#define IXGBE_TSAUXC_SYNCLK 0x00000008
2602#define IXGBE_TSAUXC_SDP0_INT 0x00000040
2603#define IXGBE_TSAUXC_EN_TT0 0x00000001
2604#define IXGBE_TSAUXC_EN_TT1 0x00000002
2605#define IXGBE_TSAUXC_ST0 0x00000010
2606#define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000
2608#define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0
2609#define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080
2610#define IXGBE_TSSDP_TS_SDP0_EN 0x00000100
2612#define IXGBE_TSYNCTXCTL_VALID 0x00000001
2613#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010
2615#define IXGBE_TSYNCRXCTL_VALID 0x00000001
2616#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E
2617#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
2618#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
2619#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
2620#define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08
2621#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
2622#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010
2623#define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000
2624#define IXGBE_TSYNCRXCTL_TSIP_UP_MASK 0xFF000000
2626#define IXGBE_TSIM_SYS_WRAP 0x00000001
2627#define IXGBE_TSIM_TXTS 0x00000002
2628#define IXGBE_TSIM_TADJ 0x00000080
2630#define IXGBE_TSICR_SYS_WRAP IXGBE_TSIM_SYS_WRAP
2631#define IXGBE_TSICR_TXTS IXGBE_TSIM_TXTS
2632#define IXGBE_TSICR_TADJ IXGBE_TSIM_TADJ
2634#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
2635#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
2636#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
2637#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
2638#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
2639#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
2641#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
2642#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
2643#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
2644#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
2645#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
2646#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
2647#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
2648#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2649#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
2650#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00
2651#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
2653#define IXGBE_FCTRL_SBP 0x00000002
2654#define IXGBE_FCTRL_MPE 0x00000100
2655#define IXGBE_FCTRL_UPE 0x00000200
2656#define IXGBE_FCTRL_BAM 0x00000400
2657#define IXGBE_FCTRL_PMCF 0x00001000
2658#define IXGBE_FCTRL_DPF 0x00002000
2660#define IXGBE_FCTRL_RPFCE 0x00004000
2661#define IXGBE_FCTRL_RFCE 0x00008000
2662#define IXGBE_MFLCN_PMCF 0x00000001
2663#define IXGBE_MFLCN_DPF 0x00000002
2664#define IXGBE_MFLCN_RPFCE 0x00000004
2665#define IXGBE_MFLCN_RFCE 0x00000008
2666#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4
2667#define IXGBE_MFLCN_RPFCE_SHIFT 4
2670#define IXGBE_MRQC_RSSEN 0x00000001
2671#define IXGBE_MRQC_MRQE_MASK 0xF
2672#define IXGBE_MRQC_RT8TCEN 0x00000002
2673#define IXGBE_MRQC_RT4TCEN 0x00000003
2674#define IXGBE_MRQC_RTRSS8TCEN 0x00000004
2675#define IXGBE_MRQC_RTRSS4TCEN 0x00000005
2676#define IXGBE_MRQC_VMDQEN 0x00000008
2677#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A
2678#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B
2679#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C
2680#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D
2681#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2682#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2683#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2684#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2685#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2686#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2687#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2688#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2689#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
2690#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
2691#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2692#define IXGBE_MRQC_MULTIPLE_RSS 0x00002000
2693#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2696#define IXGBE_QDE_ENABLE 0x00000001
2697#define IXGBE_QDE_HIDE_VLAN 0x00000002
2698#define IXGBE_QDE_IDX_MASK 0x00007F00
2699#define IXGBE_QDE_IDX_SHIFT 8
2700#define IXGBE_QDE_WRITE 0x00010000
2701#define IXGBE_QDE_READ 0x00020000
2703#define IXGBE_TXD_POPTS_IXSM 0x01
2704#define IXGBE_TXD_POPTS_TXSM 0x02
2705#define IXGBE_TXD_CMD_EOP 0x01000000
2706#define IXGBE_TXD_CMD_IFCS 0x02000000
2707#define IXGBE_TXD_CMD_IC 0x04000000
2708#define IXGBE_TXD_CMD_RS 0x08000000
2709#define IXGBE_TXD_CMD_DEXT 0x20000000
2710#define IXGBE_TXD_CMD_VLE 0x40000000
2711#define IXGBE_TXD_STAT_DD 0x00000001
2713#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
2714#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2715#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2716#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
2717#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
2719#define IXGBE_MTQC_RT_ENA 0x1
2720#define IXGBE_MTQC_VT_ENA 0x2
2721#define IXGBE_MTQC_64Q_1PB 0x0
2722#define IXGBE_MTQC_32VF 0x8
2723#define IXGBE_MTQC_64VF 0x4
2724#define IXGBE_MTQC_4TC_4TQ 0x8
2725#define IXGBE_MTQC_8TC_8TQ 0xC
2728#define IXGBE_RXD_STAT_DD 0x01
2729#define IXGBE_RXD_STAT_EOP 0x02
2730#define IXGBE_RXD_STAT_FLM 0x04
2731#define IXGBE_RXD_STAT_VP 0x08
2732#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0
2733#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
2734#define IXGBE_RXD_STAT_UDPCS 0x10
2735#define IXGBE_RXD_STAT_L4CS 0x20
2736#define IXGBE_RXD_STAT_IPCS 0x40
2737#define IXGBE_RXD_STAT_PIF 0x80
2738#define IXGBE_RXD_STAT_CRCV 0x100
2739#define IXGBE_RXD_STAT_OUTERIPCS 0x100
2740#define IXGBE_RXD_STAT_VEXT 0x200
2741#define IXGBE_RXD_STAT_UDPV 0x400
2742#define IXGBE_RXD_STAT_DYNINT 0x800
2743#define IXGBE_RXD_STAT_LLINT 0x800
2744#define IXGBE_RXD_STAT_TSIP 0x08000
2745#define IXGBE_RXD_STAT_TS 0x10000
2746#define IXGBE_RXD_STAT_SECP 0x20000
2747#define IXGBE_RXD_STAT_LB 0x40000
2748#define IXGBE_RXD_STAT_ACK 0x8000
2749#define IXGBE_RXD_ERR_CE 0x01
2750#define IXGBE_RXD_ERR_LE 0x02
2751#define IXGBE_RXD_ERR_PE 0x08
2752#define IXGBE_RXD_ERR_OSE 0x10
2753#define IXGBE_RXD_ERR_USE 0x20
2754#define IXGBE_RXD_ERR_TCPE 0x40
2755#define IXGBE_RXD_ERR_IPE 0x80
2756#define IXGBE_RXDADV_ERR_MASK 0xfff00000
2757#define IXGBE_RXDADV_ERR_SHIFT 20
2758#define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000
2759#define IXGBE_RXDADV_ERR_RXE 0x20000000
2760#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000
2761#define IXGBE_RXDADV_ERR_FCERR 0x00700000
2762#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000
2763#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000
2764#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000
2765#define IXGBE_RXDADV_ERR_HBO 0x00800000
2766#define IXGBE_RXDADV_ERR_CE 0x01000000
2767#define IXGBE_RXDADV_ERR_LE 0x02000000
2768#define IXGBE_RXDADV_ERR_PE 0x08000000
2769#define IXGBE_RXDADV_ERR_OSE 0x10000000
2770#define IXGBE_RXDADV_ERR_USE 0x20000000
2771#define IXGBE_RXDADV_ERR_TCPE 0x40000000
2772#define IXGBE_RXDADV_ERR_IPE 0x80000000
2773#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF
2774#define IXGBE_RXD_PRI_MASK 0xE000
2775#define IXGBE_RXD_PRI_SHIFT 13
2776#define IXGBE_RXD_CFI_MASK 0x1000
2777#define IXGBE_RXD_CFI_SHIFT 12
2779#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD
2780#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP
2781#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM
2782#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP
2783#define IXGBE_RXDADV_STAT_MASK 0x000fffff
2784#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040
2785#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030
2786#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000
2787#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010
2788#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020
2789#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030
2790#define IXGBE_RXDADV_STAT_TS 0x00010000
2791#define IXGBE_RXDADV_STAT_TSIP 0x00008000
2794#define IXGBE_PSRTYPE_TCPHDR 0x00000010
2795#define IXGBE_PSRTYPE_UDPHDR 0x00000020
2796#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2797#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
2798#define IXGBE_PSRTYPE_L2HDR 0x00001000
2801#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10
2802#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2806#define IXGBE_SRRCTL_RDMTS_SHIFT 22
2807#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2808#define IXGBE_SRRCTL_DROP_EN 0x10000000
2809#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2810#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2811#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
2812#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2813#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2814#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2815#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2816#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
2818#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2819#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2821#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2822#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
2823#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
2824#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
2825#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2826#define IXGBE_RXDADV_RSCCNT_SHIFT 17
2827#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2828#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2829#define IXGBE_RXDADV_SPH 0x8000
2832#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2833#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2834#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2835#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2836#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2837#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2838#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2839#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2840#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2841#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2844#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2845#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010
2846#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020
2847#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040
2848#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080
2849#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100
2850#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200
2851#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400
2852#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800
2853#define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800
2854#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800
2855#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000
2856#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000
2857#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000
2858#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000
2859#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000
2860#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070
2861#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4
2864#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
2865#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
2866#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
2867#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
2868#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
2871#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2872 IXGBE_RXD_ERR_CE | \
2873 IXGBE_RXD_ERR_LE | \
2874 IXGBE_RXD_ERR_PE | \
2875 IXGBE_RXD_ERR_OSE | \
2878#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2879 IXGBE_RXDADV_ERR_CE | \
2880 IXGBE_RXDADV_ERR_LE | \
2881 IXGBE_RXDADV_ERR_PE | \
2882 IXGBE_RXDADV_ERR_OSE | \
2883 IXGBE_RXDADV_ERR_USE)
2885#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE
2888#define IXGBE_MCSTCTRL_MFE 0x4
2891#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2892#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2893#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2896#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF
2897#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000
2898#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D
2899#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2902#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2903#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
2904#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
2905#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
2907#define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P)))
2908#define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P)))
2909#define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P)))
2910#define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P)))
2911#define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P)))
2912#define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P)))
2913#define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P)))
2914#define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P)))
2915#define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P)))
2916#define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P)))
2917#define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P)))
2918#define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P)))
2919#define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \
2920 (0x012300 + (((P) - 24) * 4)))
2921#define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P)))
2922#define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P)))
2923#define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P)))
2924#define IXGBE_VFPBACL(P) (0x110C8 + (4 * (P)))
2925#define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \
2926 : (0x0D000 + (0x40 * ((P) - 64))))
2927#define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \
2928 : (0x0D004 + (0x40 * ((P) - 64))))
2929#define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \
2930 : (0x0D008 + (0x40 * ((P) - 64))))
2931#define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \
2932 : (0x0D010 + (0x40 * ((P) - 64))))
2933#define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \
2934 : (0x0D018 + (0x40 * ((P) - 64))))
2935#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \
2936 : (0x0D028 + (0x40 * ((P) - 64))))
2937#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \
2938 : (0x0D014 + (0x40 * ((P) - 64))))
2939#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P)))
2940#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P)))
2941#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P)))
2942#define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P)))
2943#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2944#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
2945#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
2946#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2947#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2948#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2949 : (0x0D00C + (0x40 * ((P) - 64))))
2950#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P)))
2951#define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x)))
2952#define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x)))
2953#define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x)))
2954#define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x)))
2955#define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x)))
2956#define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x)))
2957#define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x)))
2959#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2960 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2961#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2962 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2964#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \
2965 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2966#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \
2967 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2995#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2996#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2997#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2998#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2999#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
3000#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
3001#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
3002#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
3003#define IXGBE_FDIRCTRL_DROP_Q_MASK 0x00007F00
3004#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
3005#define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000
3006#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
3007#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001
3008#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002
3009#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
3010#define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000
3011#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
3012#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
3013#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
3015#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
3016#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
3017#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
3018#define IXGBE_FDIRM_VLANID 0x00000001
3019#define IXGBE_FDIRM_VLANP 0x00000002
3020#define IXGBE_FDIRM_POOL 0x00000004
3021#define IXGBE_FDIRM_L4P 0x00000008
3022#define IXGBE_FDIRM_FLEX 0x00000010
3023#define IXGBE_FDIRM_DIPv6 0x00000020
3024#define IXGBE_FDIRM_L3P 0x00000040
3026#define IXGBE_FDIRIP6M_INNER_MAC 0x03F0
3027#define IXGBE_FDIRIP6M_TUNNEL_TYPE 0x0800
3028#define IXGBE_FDIRIP6M_TNI_VNI 0xF000
3029#define IXGBE_FDIRIP6M_TNI_VNI_24 0x1000
3030#define IXGBE_FDIRIP6M_ALWAYS_MASK 0x040F
3032#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
3033#define IXGBE_FDIRFREE_FREE_SHIFT 0
3034#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
3035#define IXGBE_FDIRFREE_COLL_SHIFT 16
3036#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
3037#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
3038#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
3039#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
3040#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
3041#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
3042#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
3043#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
3044#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
3045#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
3046#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
3047#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
3048#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
3049#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
3050#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
3051#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
3053#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
3054#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
3055#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
3056#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
3057#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
3058#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
3059#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
3060#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
3061#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
3062#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
3063#define IXGBE_FDIRCMD_IPV6 0x00000080
3064#define IXGBE_FDIRCMD_CLEARHT 0x00000100
3065#define IXGBE_FDIRCMD_DROP 0x00000200
3066#define IXGBE_FDIRCMD_INT 0x00000400
3067#define IXGBE_FDIRCMD_LAST 0x00000800
3068#define IXGBE_FDIRCMD_COLLISION 0x00001000
3069#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
3070#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
3071#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
3072#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT 23
3073#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
3074#define IXGBE_FDIR_INIT_DONE_POLL 10
3075#define IXGBE_FDIRCMD_CMD_POLL 10
3076#define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000
3077#define IXGBE_FDIR_DROP_QUEUE 127
3081#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792
3082#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448
3083#define IXGBE_HI_COMMAND_TIMEOUT 500
3084#define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000
3085#define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000
3086#define IXGBE_HI_FLASH_APPLY_TIMEOUT 0
3087#define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000
3090#define FW_CEM_HDR_LEN 0x4
3091#define FW_CEM_CMD_DRIVER_INFO 0xDD
3092#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
3093#define FW_CEM_CMD_RESERVED 0X0
3094#define FW_CEM_UNUSED_VER 0x0
3095#define FW_CEM_MAX_RETRIES 3
3096#define FW_CEM_RESP_STATUS_SUCCESS 0x1
3097#define FW_CEM_DRIVER_VERSION_SIZE 39
3098#define FW_READ_SHADOW_RAM_CMD 0x31
3099#define FW_READ_SHADOW_RAM_LEN 0x6
3100#define FW_WRITE_SHADOW_RAM_CMD 0x33
3101#define FW_WRITE_SHADOW_RAM_LEN 0xA
3102#define FW_SHADOW_RAM_DUMP_CMD 0x36
3103#define FW_SHADOW_RAM_DUMP_LEN 0
3104#define FW_DEFAULT_CHECKSUM 0xFF
3105#define FW_NVM_DATA_OFFSET 3
3106#define FW_MAX_READ_BUFFER_SIZE 1024
3107#define FW_DISABLE_RXEN_CMD 0xDE
3108#define FW_DISABLE_RXEN_LEN 0x1
3109#define FW_PHY_MGMT_REQ_CMD 0x20
3110#define FW_PHY_TOKEN_REQ_CMD 0xA
3111#define FW_PHY_TOKEN_REQ_LEN 2
3112#define FW_PHY_TOKEN_REQ 0
3113#define FW_PHY_TOKEN_REL 1
3114#define FW_PHY_TOKEN_OK 1
3115#define FW_PHY_TOKEN_RETRY 0x80
3116#define FW_PHY_TOKEN_DELAY 5
3117#define FW_PHY_TOKEN_WAIT 5
3118#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
3119#define FW_INT_PHY_REQ_CMD 0xB
3120#define FW_INT_PHY_REQ_LEN 10
3121#define FW_INT_PHY_REQ_READ 0
3122#define FW_INT_PHY_REQ_WRITE 1
3123#define FW_PHY_ACT_REQ_CMD 5
3124#define FW_PHY_ACT_DATA_COUNT 4
3125#define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT)
3126#define FW_PHY_ACT_INIT_PHY 1
3127#define FW_PHY_ACT_SETUP_LINK 2
3128#define FW_PHY_ACT_LINK_SPEED_10 (1u << 0)
3129#define FW_PHY_ACT_LINK_SPEED_100 (1u << 1)
3130#define FW_PHY_ACT_LINK_SPEED_1G (1u << 2)
3131#define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3)
3132#define FW_PHY_ACT_LINK_SPEED_5G (1u << 4)
3133#define FW_PHY_ACT_LINK_SPEED_10G (1u << 5)
3134#define FW_PHY_ACT_LINK_SPEED_20G (1u << 6)
3135#define FW_PHY_ACT_LINK_SPEED_25G (1u << 7)
3136#define FW_PHY_ACT_LINK_SPEED_40G (1u << 8)
3137#define FW_PHY_ACT_LINK_SPEED_50G (1u << 9)
3138#define FW_PHY_ACT_LINK_SPEED_100G (1u << 10)
3139#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
3140#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \
3141 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
3142#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
3143#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u
3144#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u
3145#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
3146#define FW_PHY_ACT_SETUP_LINK_LP (1u << 18)
3147#define FW_PHY_ACT_SETUP_LINK_HP (1u << 19)
3148#define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20)
3149#define FW_PHY_ACT_SETUP_LINK_AN (1u << 22)
3150#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0)
3151#define FW_PHY_ACT_GET_LINK_INFO 3
3152#define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19)
3153#define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20)
3154#define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21)
3155#define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22)
3156#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24)
3157#define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25)
3158#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28)
3159#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29)
3160#define FW_PHY_ACT_FORCE_LINK_DOWN 4
3161#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0)
3162#define FW_PHY_ACT_PHY_SW_RESET 5
3163#define FW_PHY_ACT_PHY_HW_RESET 6
3164#define FW_PHY_ACT_GET_PHY_INFO 7
3165#define FW_PHY_ACT_UD_2 0x1002
3166#define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6)
3167#define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5)
3168#define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4)
3169#define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3)
3170#define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2)
3171#define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1)
3172#define FW_PHY_ACT_RETRIES 50
3173#define FW_PHY_INFO_SPEED_MASK 0xFFFu
3174#define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u
3175#define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu
3179#pragma pack(push, 1)
3379#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF
3380#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000
3381#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000
3382#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF
3383#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF
3384#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000
3385#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000
3386#define IXGBE_ADVTXD_DTYP_DATA 0x00300000
3387#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP
3388#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS
3389#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS
3390#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000
3391#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT
3392#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE
3393#define IXGBE_ADVTXD_DCMD_TSE 0x80000000
3394#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD
3395#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002
3396#define IXGBE_ADVTXD_STAT_RSV 0x0000000C
3397#define IXGBE_ADVTXD_IDX_SHIFT 4
3398#define IXGBE_ADVTXD_CC 0x00000080
3399#define IXGBE_ADVTXD_POPTS_SHIFT 8
3400#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
3401 IXGBE_ADVTXD_POPTS_SHIFT)
3402#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
3403 IXGBE_ADVTXD_POPTS_SHIFT)
3404#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000
3405#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800
3406#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000
3408#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
3409#define IXGBE_ADVTXD_POPTS_RSV 0x00002000
3410#define IXGBE_ADVTXD_PAYLEN_SHIFT 14
3411#define IXGBE_ADVTXD_MACLEN_SHIFT 9
3412#define IXGBE_ADVTXD_VLAN_SHIFT 16
3413#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400
3414#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000
3415#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000
3416#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800
3417#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000
3418#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800
3419#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000
3420#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400
3421#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000
3422#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
3423#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000
3424#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10)
3425#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10)
3426#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10)
3427#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10)
3428#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10)
3429#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10)
3430#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10)
3431#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10)
3432#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10)
3433#define IXGBE_ADVTXD_L4LEN_SHIFT 8
3434#define IXGBE_ADVTXD_MSS_SHIFT 16
3436#define IXGBE_ADVTXD_OUTER_IPLEN 16
3437#define IXGBE_ADVTXD_TUNNEL_LEN 24
3438#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16
3439#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17
3440#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1
3442#define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26
3447#define IXGBE_LINK_SPEED_UNKNOWN 0
3448#define IXGBE_LINK_SPEED_10_FULL 0x0002
3449#define IXGBE_LINK_SPEED_100_FULL 0x0008
3450#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
3451#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
3452#define IXGBE_LINK_SPEED_5GB_FULL 0x0800
3453#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
3454#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
3455 IXGBE_LINK_SPEED_10GB_FULL)
3456#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
3457 IXGBE_LINK_SPEED_1GB_FULL | \
3458 IXGBE_LINK_SPEED_10GB_FULL)
3462#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
3463#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
3464#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
3465#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
3466#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
3467#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
3468#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
3469#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
3470#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
3471#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
3472#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
3473#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
3474#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
3475#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
3476#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
3477#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
3478#define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
3479#define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
3486#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
3487#define IXGBE_B2BT(BT) (BT * 8)
3490#define IXGBE_PFC_D 672
3493#define IXGBE_CABLE_DC 5556
3494#define IXGBE_CABLE_DO 5000
3497#define IXGBE_PHY_DC 25600
3498#define IXGBE_MAC_DC 8192
3499#define IXGBE_XAUI_DC (2 * 2048)
3501#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
3504#define IXGBE_PHY_D 12800
3505#define IXGBE_MAC_D 4096
3506#define IXGBE_XAUI_D (2 * 1024)
3508#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
3511#define IXGBE_HD 6144
3514#define IXGBE_PCI_DELAY 10000
3517#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3519 (IXGBE_B2BT(_max_frame_link) + \
3521 (2 * IXGBE_CABLE_DC) + \
3522 (2 * IXGBE_ID_X540) + \
3523 IXGBE_HD) / 25 + 1) + \
3524 2 * IXGBE_B2BT(_max_frame_tc))
3527#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3529 (IXGBE_B2BT(_max_frame_link) + \
3531 (2 * IXGBE_CABLE_DC) + \
3533 IXGBE_HD) / 25 + 1) + \
3534 2 * IXGBE_B2BT(_max_frame_tc))
3537#define IXGBE_LOW_DV_X540(_max_frame_tc) \
3538 (2 * IXGBE_B2BT(_max_frame_tc) + \
3539 (36 * IXGBE_PCI_DELAY / 25) + 1)
3540#define IXGBE_LOW_DV(_max_frame_tc) \
3541 (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3544#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
3545#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
3548#define IXGBE_ATR_HASH_MASK 0x7fff
3549#define IXGBE_ATR_L4TYPE_MASK 0x3
3550#define IXGBE_ATR_L4TYPE_UDP 0x1
3551#define IXGBE_ATR_L4TYPE_TCP 0x2
3552#define IXGBE_ATR_L4TYPE_SCTP 0x3
3553#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
3554#define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10
3626#define IXGBE_MVALS_INIT(m) \
3627 IXGBE_CAT(EEC, m), \
3628 IXGBE_CAT(FLA, m), \
3629 IXGBE_CAT(GRC, m), \
3630 IXGBE_CAT(SRAMREL, m), \
3631 IXGBE_CAT(FACTPS, m), \
3632 IXGBE_CAT(SWSM, m), \
3633 IXGBE_CAT(SWFW_SYNC, m), \
3634 IXGBE_CAT(FWSM, m), \
3635 IXGBE_CAT(SDP0_GPIEN, m), \
3636 IXGBE_CAT(SDP1_GPIEN, m), \
3637 IXGBE_CAT(SDP2_GPIEN, m), \
3638 IXGBE_CAT(EICR_GPI_SDP0, m), \
3639 IXGBE_CAT(EICR_GPI_SDP1, m), \
3640 IXGBE_CAT(EICR_GPI_SDP2, m), \
3641 IXGBE_CAT(CIAA, m), \
3642 IXGBE_CAT(CIAD, m), \
3643 IXGBE_CAT(I2C_CLK_IN, m), \
3644 IXGBE_CAT(I2C_CLK_OUT, m), \
3645 IXGBE_CAT(I2C_DATA_IN, m), \
3646 IXGBE_CAT(I2C_DATA_OUT, m), \
3647 IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
3648 IXGBE_CAT(I2C_BB_EN, m), \
3649 IXGBE_CAT(I2C_CLK_OE_N_EN, m), \
3650 IXGBE_CAT(I2CCTL, m)
3777#define IXGBE_SMARTSPEED_MAX_RETRIES 3
3936typedef u8* (*ixgbe_mc_addr_itr) (
struct ixgbe_hw *hw,
u8 **mc_addr_ptr,
4115#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
4126#define IXGBE_MAX_MTA 128
4232#define ixgbe_call_func(hw, func, params, error) \
4233 (func != NULL) ? func params : error
4237#define IXGBE_SUCCESS 0
4238#define IXGBE_ERR_EEPROM -1
4239#define IXGBE_ERR_EEPROM_CHECKSUM -2
4240#define IXGBE_ERR_PHY -3
4241#define IXGBE_ERR_CONFIG -4
4242#define IXGBE_ERR_PARAM -5
4243#define IXGBE_ERR_MAC_TYPE -6
4244#define IXGBE_ERR_UNKNOWN_PHY -7
4245#define IXGBE_ERR_LINK_SETUP -8
4246#define IXGBE_ERR_ADAPTER_STOPPED -9
4247#define IXGBE_ERR_INVALID_MAC_ADDR -10
4248#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
4249#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
4250#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
4251#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
4252#define IXGBE_ERR_RESET_FAILED -15
4253#define IXGBE_ERR_SWFW_SYNC -16
4254#define IXGBE_ERR_PHY_ADDR_INVALID -17
4255#define IXGBE_ERR_I2C -18
4256#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
4257#define IXGBE_ERR_SFP_NOT_PRESENT -20
4258#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
4259#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
4260#define IXGBE_ERR_FDIR_REINIT_FAILED -23
4261#define IXGBE_ERR_EEPROM_VERSION -24
4262#define IXGBE_ERR_NO_SPACE -25
4263#define IXGBE_ERR_OVERTEMP -26
4264#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
4265#define IXGBE_ERR_FC_NOT_SUPPORTED -28
4266#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
4267#define IXGBE_ERR_PBA_SECTION -31
4268#define IXGBE_ERR_INVALID_ARGUMENT -32
4269#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
4270#define IXGBE_ERR_OUT_OF_MEM -34
4271#define IXGBE_BYPASS_FW_WRITE_FAILURE -35
4272#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36
4273#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37
4274#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
4275#define IXGBE_ERR_FW_RESP_INVALID -39
4276#define IXGBE_ERR_TOKEN_RETRY -40
4278#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
4281#define BYPASS_PAGE_CTL0 0x00000000
4282#define BYPASS_PAGE_CTL1 0x40000000
4283#define BYPASS_PAGE_CTL2 0x80000000
4284#define BYPASS_PAGE_M 0xc0000000
4285#define BYPASS_WE 0x20000000
4287#define BYPASS_AUTO 0x0
4288#define BYPASS_NOP 0x0
4289#define BYPASS_NORM 0x1
4290#define BYPASS_BYPASS 0x2
4291#define BYPASS_ISOLATE 0x3
4293#define BYPASS_EVENT_MAIN_ON 0x1
4294#define BYPASS_EVENT_AUX_ON 0x2
4295#define BYPASS_EVENT_MAIN_OFF 0x3
4296#define BYPASS_EVENT_AUX_OFF 0x4
4297#define BYPASS_EVENT_WDT_TO 0x5
4298#define BYPASS_EVENT_USR 0x6
4300#define BYPASS_MODE_OFF_M 0x00000003
4301#define BYPASS_STATUS_OFF_M 0x0000000c
4302#define BYPASS_AUX_ON_M 0x00000030
4303#define BYPASS_MAIN_ON_M 0x000000c0
4304#define BYPASS_MAIN_OFF_M 0x00000300
4305#define BYPASS_AUX_OFF_M 0x00000c00
4306#define BYPASS_WDTIMEOUT_M 0x00003000
4307#define BYPASS_WDT_ENABLE_M 0x00004000
4308#define BYPASS_WDT_VALUE_M 0x00070000
4310#define BYPASS_MODE_OFF_SHIFT 0
4311#define BYPASS_STATUS_OFF_SHIFT 2
4312#define BYPASS_AUX_ON_SHIFT 4
4313#define BYPASS_MAIN_ON_SHIFT 6
4314#define BYPASS_MAIN_OFF_SHIFT 8
4315#define BYPASS_AUX_OFF_SHIFT 10
4316#define BYPASS_WDTIMEOUT_SHIFT 12
4317#define BYPASS_WDT_ENABLE_SHIFT 14
4318#define BYPASS_WDT_TIME_SHIFT 16
4320#define BYPASS_WDT_1 0x0
4321#define BYPASS_WDT_1_5 0x1
4322#define BYPASS_WDT_2 0x2
4323#define BYPASS_WDT_3 0x3
4324#define BYPASS_WDT_4 0x4
4325#define BYPASS_WDT_8 0x5
4326#define BYPASS_WDT_16 0x6
4327#define BYPASS_WDT_32 0x7
4328#define BYPASS_WDT_OFF 0xffff
4330#define BYPASS_CTL1_TIME_M 0x01ffffff
4331#define BYPASS_CTL1_VALID_M 0x02000000
4332#define BYPASS_CTL1_OFFTRST_M 0x04000000
4333#define BYPASS_CTL1_WDT_PET_M 0x08000000
4335#define BYPASS_CTL1_VALID 0x02000000
4336#define BYPASS_CTL1_OFFTRST 0x04000000
4337#define BYPASS_CTL1_WDT_PET 0x08000000
4339#define BYPASS_CTL2_DATA_M 0x000000ff
4340#define BYPASS_CTL2_OFFSET_M 0x0000ff00
4341#define BYPASS_CTL2_RW_M 0x00010000
4342#define BYPASS_CTL2_HEAD_M 0x0ff00000
4344#define BYPASS_CTL2_OFFSET_SHIFT 8
4345#define BYPASS_CTL2_HEAD_SHIFT 20
4347#define BYPASS_CTL2_RW 0x00010000
4355#define BYPASS_MAX_LOGS 43
4356#define BYPASS_LOG_SIZE 5
4357#define BYPASS_LOG_LINE_SIZE 37
4359#define BYPASS_EEPROM_VER_ADD 0x02
4361#define BYPASS_LOG_TIME_M 0x01ffffff
4362#define BYPASS_LOG_TIME_VALID_M 0x02000000
4363#define BYPASS_LOG_HEAD_M 0x04000000
4364#define BYPASS_LOG_CLEAR_M 0x08000000
4365#define BYPASS_LOG_EVENT_M 0xf0000000
4366#define BYPASS_LOG_ACTION_M 0x03
4368#define BYPASS_LOG_EVENT_SHIFT 28
4369#define BYPASS_LOG_CLEAR_SHIFT 24
4371#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
4372#define IXGBE_FUSES0_300MHZ (1 << 5)
4373#define IXGBE_FUSES0_REV_MASK (3 << 6)
4375#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
4376#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)
4377#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
4378#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
4379#define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238)
4380#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)
4381#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918)
4382#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C)
4383#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)
4384#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)
4385#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
4386#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
4387#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
4388#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
4389#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)
4390#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
4391#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
4393#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20)
4394#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20)
4395#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20)
4396#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25)
4397#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26)
4398#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27)
4399#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28)
4400#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28)
4401#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28)
4402#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28)
4403#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28)
4404#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28)
4405#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28)
4406#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31)
4408#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
4409#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
4411#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
4412#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
4413#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
4414#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12)
4415#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13)
4416#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
4417#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
4418#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
4419#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
4420#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
4421#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
4422#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28)
4423#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
4424#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
4426#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
4427#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
4428#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1)
4429#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2)
4430#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2)
4431#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3)
4432#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29)
4433#define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0)
4434#define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1)
4436#define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10)
4437#define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11)
4439#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12)
4440#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19)
4442#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
4443#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
4444#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
4446#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
4447#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
4449#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
4451#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
4452#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
4453#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
4454#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
4456#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
4457#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
4459#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
4460#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
4461#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
4462#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
4463 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
4464#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20
4465#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
4466 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
4467#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
4468#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
4469#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
4470#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
4471#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
4473#define IXGBE_NW_MNG_IF_SEL 0x00011178
4474#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1)
4475#define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2)
4476#define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13)
4477#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17)
4478#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18)
4479#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19)
4480#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20)
4481#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21)
4482#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25)
4483#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)
4484#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
4485#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
4486 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
4489#define IXGBE_HOST_INTERFACE_FLASH_READ_CMD 0x30
4490#define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD 0x31
4491#define IXGBE_HOST_INTERFACE_FLASH_WRITE_CMD 0x32
4492#define IXGBE_HOST_INTERFACE_SHADOW_RAM_WRITE_CMD 0x33
4493#define IXGBE_HOST_INTERFACE_FLASH_MODULE_UPDATE_CMD 0x34
4494#define IXGBE_HOST_INTERFACE_FLASH_BLOCK_EREASE_CMD 0x35
4495#define IXGBE_HOST_INTERFACE_SHADOW_RAM_DUMP_CMD 0x36
4496#define IXGBE_HOST_INTERFACE_FLASH_INFO_CMD 0x37
4497#define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD 0x38
4498#define IXGBE_HOST_INTERFACE_MASK_CMD 0x000000FF
4500#define IXGBE_REQUEST_TASK_MOD 0x01
4501#define IXGBE_REQUEST_TASK_MSF 0x02
4502#define IXGBE_REQUEST_TASK_MBX 0x04
4503#define IXGBE_REQUEST_TASK_FDIR 0x08
4504#define IXGBE_REQUEST_TASK_PHY 0x10
4505#define IXGBE_REQUEST_TASK_LSC 0x20
u32 ixgbe_autoneg_advertised
#define IXGBE_ETH_LENGTH_OF_ADDRESS
@ ixgbe_bus_type_reserved
@ ixgbe_bus_type_pci_express
@ ixgbe_bus_type_internal
#define IXGBE_DCB_MAX_TRAFFIC_CLASS
#define IXGBE_MAX_SENSORS
#define PBA_STRATEGY_WEIGHTED
@ IXGBE_ATR_FLOW_TYPE_SCTPV4
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4
@ IXGBE_ATR_FLOW_TYPE_IPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4
@ IXGBE_ATR_FLOW_TYPE_TCPV4
@ IXGBE_ATR_FLOW_TYPE_TCPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4
@ IXGBE_ATR_FLOW_TYPE_IPV4
@ IXGBE_ATR_FLOW_TYPE_SCTPV6
@ IXGBE_ATR_FLOW_TYPE_UDPV6
@ IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4
@ IXGBE_ATR_FLOW_TYPE_UDPV4
@ ixgbe_bus_speed_reserved
@ ixgbe_bus_speed_unknown
#define FW_CEM_DRIVER_VERSION_SIZE
u8 *(* ixgbe_mc_addr_itr)(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
@ IXGBE_FDIR_PBALLOC_256K
@ IXGBE_FDIR_PBALLOC_NONE
@ IXGBE_FDIR_PBALLOC_128K
@ ixgbe_phy_sfp_ftl_active
@ ixgbe_phy_qsfp_active_unknown
@ ixgbe_phy_sfp_active_unknown
@ ixgbe_phy_sfp_passive_tyco
@ ixgbe_phy_sfp_passive_unknown
@ ixgbe_phy_sfp_unsupported
@ ixgbe_phy_qsfp_passive_unknown
@ ixgbe_eeprom_uninitialized
#define FW_PHY_ACT_DATA_COUNT
@ ixgbe_media_type_unknown
@ ixgbe_media_type_copper
@ ixgbe_media_type_fiber_qsfp
@ ixgbe_media_type_virtual
@ ixgbe_media_type_backplane
@ ixgbe_media_type_fiber_fixed
@ ixgbe_sfp_type_1g_sx_core1
@ ixgbe_sfp_type_da_cu_core1
@ ixgbe_sfp_type_1g_cu_core1
@ ixgbe_sfp_type_da_act_lmt_core1
@ ixgbe_sfp_type_1g_lx_core0
@ ixgbe_sfp_type_srlr_core1
@ ixgbe_sfp_type_da_act_lmt_core0
@ ixgbe_sfp_type_1g_cu_core0
@ ixgbe_sfp_type_da_cu_core0
@ ixgbe_sfp_type_1g_lx_core1
@ ixgbe_sfp_type_not_present
@ ixgbe_sfp_type_1g_sx_core0
@ ixgbe_sfp_type_srlr_core0
#define PBA_STRATEGY_EQUAL
#define IXGBE_MVALS_INIT(m)
@ ixgbe_bus_width_reserved
@ ixgbe_bus_width_unknown
@ ixgbe_bus_width_pcie_x1
@ ixgbe_bus_width_pcie_x8
@ ixgbe_bus_width_pcie_x2
@ ixgbe_bus_width_pcie_x4
@ ixgbe_fcoe_bootstatus_disabled
@ ixgbe_fcoe_bootstatus_unavailable
@ ixgbe_fcoe_bootstatus_enabled
enum ixgbe_bus_width width
enum ixgbe_bus_speed speed
enum ixgbe_eeprom_type type
struct ixgbe_eeprom_operations ops
s32(* read_buffer)(struct ixgbe_hw *, u16, u16, u16 *)
s32(* write_buffer)(struct ixgbe_hw *, u16, u16, u16 *)
s32(* update_checksum)(struct ixgbe_hw *)
s32(* init_params)(struct ixgbe_hw *)
s32(* write)(struct ixgbe_hw *, u16, u16)
s32(* read)(struct ixgbe_hw *, u16, u16 *)
s32(* calc_checksum)(struct ixgbe_hw *)
s32(* validate_checksum)(struct ixgbe_hw *, u16 *)
enum ixgbe_fc_mode current_mode
u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]
u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]
enum ixgbe_fc_mode requested_mode
char driver_string[FW_CEM_DRIVER_VERSION_SIZE]
union ixgbe_hic_hdr::@3 cmd_or_resp
__be32 data[FW_PHY_ACT_DATA_COUNT]
__be32 data[FW_PHY_ACT_DATA_COUNT]
struct ixgbe_mac_info mac
struct ixgbe_addr_filter_info addr_ctrl
struct ixgbe_link_info link
struct ixgbe_bus_info bus
struct ixgbe_mbx_info mbx
bool allow_unsupported_sfp
struct ixgbe_eeprom_info eeprom
struct ixgbe_phy_info phy
union ixgbe_legacy_tx_desc::@5 upper
union ixgbe_legacy_tx_desc::@4 lower
struct ixgbe_legacy_tx_desc::@4::@6 flags
struct ixgbe_legacy_tx_desc::@5::@7 fields
struct ixgbe_link_operations ops
s32(* read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val)
s32(* write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val)
s32(* write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val)
s32(* read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val)
bool orig_link_settings_stored
u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
u32 mta_shadow[IXGBE_MAX_MTA]
bool thermal_sensor_enabled
u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
struct ixgbe_thermal_sensor_data thermal_sensor_data
struct ixgbe_dmac_config dmac_config
u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
struct ixgbe_mac_operations ops
s32(* get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *)
s32(* set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32, bool)
s32(* reset_hw)(struct ixgbe_hw *)
s32(* init_hw)(struct ixgbe_hw *)
s32(* prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *)
s32(* update_xcast_mode)(struct ixgbe_hw *, int)
s32(* dmac_config_tcs)(struct ixgbe_hw *hw)
void(* set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int)
s32(* acquire_swfw_sync)(struct ixgbe_hw *, u32)
s32(* fc_enable)(struct ixgbe_hw *)
s32(* set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, const char *)
s32(* led_off)(struct ixgbe_hw *, u32)
s32(* get_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* set_rlpml)(struct ixgbe_hw *, u16)
s32(* init_rx_addrs)(struct ixgbe_hw *)
s32(* enable_rx_dma)(struct ixgbe_hw *, u32)
s32(* setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool)
s32(* set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32)
s32(* disable_mc)(struct ixgbe_hw *)
void(* release_swfw_sync)(struct ixgbe_hw *, u32)
s32(* read_analog_reg8)(struct ixgbe_hw *, u32, u8 *)
s32(* clear_vmdq)(struct ixgbe_hw *, u32, u32)
s32(* enable_mc)(struct ixgbe_hw *)
s32(* setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool)
void(* set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed)
s32(* clear_vfta)(struct ixgbe_hw *)
s32(* init_thermal_sensor_thresh)(struct ixgbe_hw *hw)
void(* set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int)
void(* enable_rx)(struct ixgbe_hw *hw)
s32(* write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32)
void(* setup_rxpba)(struct ixgbe_hw *, int, u32, int)
s32(* set_vmdq)(struct ixgbe_hw *, u32, u32)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool)
void(* get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map)
s32(* get_thermal_sensor_data)(struct ixgbe_hw *)
s32(* prot_autoc_write)(struct ixgbe_hw *, u32, bool)
s32(* setup_sfp)(struct ixgbe_hw *)
s32(* set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool)
s32(* update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, ixgbe_mc_addr_itr)
bool(* fw_recovery_mode)(struct ixgbe_hw *hw)
s32(* get_link_state)(struct ixgbe_hw *hw, bool *link_state)
s32(* disable_sec_rx_path)(struct ixgbe_hw *)
s32(* enable_sec_rx_path)(struct ixgbe_hw *)
s32(* update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, ixgbe_mc_addr_itr, bool clear)
s32(* init_led_link_act)(struct ixgbe_hw *)
void(* init_swfw_sync)(struct ixgbe_hw *)
s32(* bypass_set)(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action)
void(* enable_mdd)(struct ixgbe_hw *hw)
s32(* get_san_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* set_uc_addr)(struct ixgbe_hw *, u32, u8 *)
s32(* write_analog_reg8)(struct ixgbe_hw *, u32, u8)
s32(* setup_eee)(struct ixgbe_hw *hw, bool enable_eee)
void(* disable_rx)(struct ixgbe_hw *hw)
s32(* init_uta_tables)(struct ixgbe_hw *)
void(* disable_tx_laser)(struct ixgbe_hw *)
s32(* get_device_caps)(struct ixgbe_hw *, u16 *)
void(* fc_autoneg)(struct ixgbe_hw *)
void(* enable_relaxed_ordering)(struct ixgbe_hw *)
s32(* led_on)(struct ixgbe_hw *, u32)
s32(* setup_fc)(struct ixgbe_hw *)
s32(* dmac_config)(struct ixgbe_hw *hw)
s32(* get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
void(* set_lan_id)(struct ixgbe_hw *)
void(* disable_mdd)(struct ixgbe_hw *hw)
s32(* clear_rar)(struct ixgbe_hw *, u32)
s32(* insert_mac_addr)(struct ixgbe_hw *, u8 *, u32)
s32(* blink_led_stop)(struct ixgbe_hw *, u32)
s32(* clear_hw_cntrs)(struct ixgbe_hw *)
s32(* read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *)
void(* enable_tx_laser)(struct ixgbe_hw *)
void(* flap_tx_laser)(struct ixgbe_hw *)
enum ixgbe_media_type(* get_media_type)(struct ixgbe_hw *)
s32(* set_san_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* get_bus_info)(struct ixgbe_hw *)
s32(* get_fcoe_boot_status)(struct ixgbe_hw *, u16 *)
s32(* blink_led_start)(struct ixgbe_hw *, u32)
void(* set_source_address_pruning)(struct ixgbe_hw *, bool, unsigned int)
s32(* start_hw)(struct ixgbe_hw *)
s32(* set_vmdq_san_mac)(struct ixgbe_hw *, u32)
bool(* bypass_valid_rd)(u32 in_reg, u32 out_reg)
void(* set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int)
s32(* stop_adapter)(struct ixgbe_hw *)
s32(* bypass_rd_eep)(struct ixgbe_hw *hw, u32 addr, u8 *value)
void(* restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf)
void(* mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap)
u64(* get_supported_physical_layer)(struct ixgbe_hw *)
s32(* negotiate_api_version)(struct ixgbe_hw *hw, int api)
s32(* dmac_update_tcs)(struct ixgbe_hw *hw)
s32(* bypass_rw)(struct ixgbe_hw *hw, u32 cmd, u32 *status)
struct ixgbe_mbx_stats stats
struct ixgbe_mbx_operations ops
s32(* check_for_ack)(struct ixgbe_hw *, u16)
s32(* read_posted)(struct ixgbe_hw *, u32 *, u16, u16)
s32(* write_posted)(struct ixgbe_hw *, u32 *, u16, u16)
s32(* check_for_msg)(struct ixgbe_hw *, u16)
void(* init_params)(struct ixgbe_hw *hw)
s32(* check_for_rst)(struct ixgbe_hw *, u16)
s32(* read)(struct ixgbe_hw *, u32 *, u16, u16)
s32(* write)(struct ixgbe_hw *, u32 *, u16, u16)
enum ixgbe_media_type media_type
ixgbe_link_speed eee_speeds_advertised
ixgbe_link_speed speeds_supported
ixgbe_autoneg_advertised autoneg_advertised
struct ixgbe_phy_operations ops
ixgbe_link_speed eee_speeds_supported
enum ixgbe_sfp_type sfp_type
enum ixgbe_smart_speed smart_speed
s32(* read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, u8 *value)
s32(* read_i2c_eeprom)(struct ixgbe_hw *, u8, u8 *)
s32(* setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool)
s32(* write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8)
s32(* read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *)
s32(* check_overtemp)(struct ixgbe_hw *)
s32(* init)(struct ixgbe_hw *)
s32(* write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, u8 value)
s32(* get_firmware_version)(struct ixgbe_hw *, u16 *)
s32(* handle_lasi)(struct ixgbe_hw *hw)
s32(* reset)(struct ixgbe_hw *)
s32(* identify)(struct ixgbe_hw *)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
s32(* set_phy_power)(struct ixgbe_hw *, bool on)
s32(* read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *)
void(* i2c_bus_clear)(struct ixgbe_hw *)
s32(* write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16)
s32(* read_reg)(struct ixgbe_hw *, u32, u32, u16 *)
s32(* setup_link)(struct ixgbe_hw *)
s32(* enter_lplu)(struct ixgbe_hw *)
s32(* setup_internal_link)(struct ixgbe_hw *)
s32(* read_i2c_sff8472)(struct ixgbe_hw *, u8, u8 *)
s32(* write_i2c_eeprom)(struct ixgbe_hw *, u8, u8)
s32(* write_reg)(struct ixgbe_hw *, u32, u32, u16)
s32(* identify_sfp)(struct ixgbe_hw *)
struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS]
struct ixgbe_adv_rx_desc::@11::@12 lower
struct ixgbe_adv_rx_desc::@11::@13 upper
struct ixgbe_adv_rx_desc::@10 read
union ixgbe_adv_rx_desc::@11::@12::@15 hi_dword
struct ixgbe_adv_rx_desc::@11::@12::@14::@16 hs_rss
union ixgbe_adv_rx_desc::@11::@12::@14 lo_dword
struct ixgbe_adv_rx_desc::@11::@12::@15::@17 csum_ip
struct ixgbe_adv_rx_desc::@11 wb
struct ixgbe_adv_tx_desc::@9 wb
struct ixgbe_adv_tx_desc::@8 read
struct ixgbe_atr_hash_dword::@20 port
struct ixgbe_atr_hash_dword::@19 formatted
struct ixgbe_hic_hdr2_req req
struct ixgbe_hic_hdr2_rsp rsp