36#ifndef _IXGBE_OSDEP_H_
37#define _IXGBE_OSDEP_H_
41#include <sys/endian.h>
44#include <sys/protosw.h>
45#include <sys/socket.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
49#include <machine/bus.h>
51#include <machine/resource.h>
54#include <machine/clock.h>
55#include <dev/pci/pcivar.h>
56#include <dev/pci/pcireg.h>
58#define ASSERT(x) if(!(x)) panic("IXGBE: x")
59#define EWARN(H, W) printf(W)
71#define usec_delay(x) DELAY(x)
72#define msec_delay(x) DELAY(1000*(x))
75#define MSGOUT(S, A, B) printf(S "\n", A, B)
76#define DEBUGFUNC(F) DEBUGOUT(F);
78 #define DEBUGOUT(S) printf(S "\n")
79 #define DEBUGOUT1(S,A) printf(S "\n",A)
80 #define DEBUGOUT2(S,A,B) printf(S "\n",A,B)
81 #define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C)
82 #define DEBUGOUT4(S,A,B,C,D) printf(S "\n",A,B,C,D)
83 #define DEBUGOUT5(S,A,B,C,D,E) printf(S "\n",A,B,C,D,E)
84 #define DEBUGOUT6(S,A,B,C,D,E,F) printf(S "\n",A,B,C,D,E,F)
85 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G)
86 #define ERROR_REPORT1 ERROR_REPORT
87 #define ERROR_REPORT2 ERROR_REPORT
88 #define ERROR_REPORT3 ERROR_REPORT
89 #define ERROR_REPORT(level, format, arg...) do { \
91 case IXGBE_ERROR_SOFTWARE: \
92 case IXGBE_ERROR_CAUTION: \
93 case IXGBE_ERROR_POLLING: \
94 case IXGBE_ERROR_INVALID_STATE: \
95 case IXGBE_ERROR_UNSUPPORTED: \
96 case IXGBE_ERROR_ARGUMENT: \
97 device_printf(ixgbe_dev_from_hw(hw), format, ## arg); \
105 #define DEBUGOUT1(S,A)
106 #define DEBUGOUT2(S,A,B)
107 #define DEBUGOUT3(S,A,B,C)
108 #define DEBUGOUT4(S,A,B,C,D)
109 #define DEBUGOUT5(S,A,B,C,D,E)
110 #define DEBUGOUT6(S,A,B,C,D,E,F)
111 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
113 #define ERROR_REPORT1(S,A)
114 #define ERROR_REPORT2(S,A,B)
115 #define ERROR_REPORT3(S,A,B,C)
118#define CMD_MEM_WRT_INVALIDATE 0x0010
119#define PCI_COMMAND_REGISTER PCIR_COMMAND
122#define IXGBE_INTEL_VENDOR_ID 0x8086
125#define UNREFERENCED_PARAMETER(_p)
126#define UNREFERENCED_1PARAMETER(_p)
127#define UNREFERENCED_2PARAMETER(_p, _q)
128#define UNREFERENCED_3PARAMETER(_p, _q, _r)
129#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
131#define IXGBE_NTOHL(_i) ntohl(_i)
132#define IXGBE_NTOHS(_i) ntohs(_i)
135#define IXGBE_CPU_TO_LE16 htole16
136#define IXGBE_CPU_TO_LE32 htole32
137#define IXGBE_LE32_TO_CPU le32toh
138#define IXGBE_LE32_TO_CPUS(x)
139#define IXGBE_CPU_TO_BE16 htobe16
140#define IXGBE_CPU_TO_BE32 htobe32
141#define IXGBE_BE32_TO_CPU be32toh
150#ifndef __bool_true_false_are_defined
164#if __FreeBSD_version < 800000
165#if defined(__i386__) || defined(__amd64__)
166#define mb() __asm volatile("mfence" ::: "memory")
167#define wmb() __asm volatile("sfence" ::: "memory")
168#define rmb() __asm volatile("lfence" ::: "memory")
176#if defined(__i386__) || defined(__amd64__)
180 __asm
volatile(
"prefetcht0 %0" ::
"m" (*(
unsigned long *)x));
193 uint64_t *src = _src;
194 uint64_t *dst = _dst;
196 for (; l > 0; l -= 32) {
216#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
219#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
221#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
224#define IXGBE_READ_REG(a, reg) ixgbe_read_reg(a, reg)
227#define IXGBE_WRITE_REG(a, reg, val) ixgbe_write_reg(a, reg, val)
230#define IXGBE_READ_REG_ARRAY(a, reg, offset) \
231 ixgbe_read_reg_array(a, reg, offset)
234#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, val) \
235 ixgbe_write_reg_array(a, reg, offset, val)
u32 ixgbe_read_reg(struct ixgbe_hw *, u32)
u32 ixgbe_read_reg_array(struct ixgbe_hw *, u32, u32)
void ixgbe_write_reg(struct ixgbe_hw *, u32, u32)
u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32)
void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16)
void ixgbe_write_reg_array(struct ixgbe_hw *, u32, u32, u32)
static __inline int ixgbe_bcopy(void *restrict _src, void *restrict _dst, int l)
@ IXGBE_ERROR_INVALID_STATE
@ IXGBE_ERROR_UNSUPPORTED
bus_space_tag_t mem_bus_space_tag
bus_space_handle_t mem_bus_space_handle