35#ifdef AH_NEED_DESC_SWAP
36static void ar5212SwapTxDesc(
struct ath_desc *ds);
51 uint32_t txcfg, curLevel, newLevel;
70 if (newLevel != curLevel)
80 return (newLevel != curLevel);
156 "%s: no available UAPSD tx queue\n", __func__);
166 "%s: no available tx queue\n", __func__);
172 "%s: bad tx queue type %u\n", __func__, type);
211 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__,
268#define TU_TO_USEC(_tu) ((_tu) << 10)
274 const struct ieee80211_channel *chan =
AH_PRIVATE(ah)->ah_curchan;
276 uint32_t cwMin, chanCwMin, qmisc, dmisc;
297 if (chan && IEEE80211_IS_CHAN_B(chan))
302 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
328#ifdef AH_SUPPORT_5311
365 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0;
369 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1;
417 "%s: using tqi_readyTime\n", __func__);
444 "%s: defaulting to rdytime = %d uS\n",
600 for (i = 1000; i != 0; i--) {
608 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
610 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
614 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
627 "%s: Num of pending TX Frames %d on Q %d\n",
632 for (j = 0; j < 2; j++) {
642 "%s: TSF moved while trying to set quiet time "
643 "TSF: 0x%08x\n", __func__, tsfLow);
660 "%s: Failed to stop Tx DMA in %d msec after killing last frame\n",
678#define VALID_PKT_TYPES \
679 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
680 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
681 (1<<HAL_PKT_TYPE_BEACON))
682#define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
683#define VALID_TX_RATES \
684 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
685 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
686 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
687#define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
695 u_int txRate0, u_int txTries0,
700 u_int rtsctsDuration,
705#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
718 if(txPower > 63) txPower=63;
746 "%s: invalid rts/cts rate 0x%x\n",
747 __func__, rtsctsRate);
763 u_int txRate1, u_int txTries1,
764 u_int txRate2, u_int txTries2,
765 u_int txRate3, u_int txTries3)
798#ifdef AH_NEED_DESC_SWAP
807 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int qcuId,
812 uint32_t segLen = segLenList[0];
824 }
else if (lastSeg) {
831#ifdef AH_NEED_DESC_SWAP
845#ifdef AH_NEED_DESC_SWAP
855 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
859#ifdef AH_NEED_DESC_SWAP
862ar5212SwapTxDesc(
struct ath_desc *ds)
883#ifdef AH_NEED_DESC_SWAP
884 if ((ads->ds_txstatus1 & __bswap32(
AR_Done)) == 0)
887 ar5212SwapTxDesc(ds);
889 if ((ads->ds_txstatus1 &
AR_Done) == 0)
HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi)
HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo)
#define HAL_COMP_BUF_MAX_SIZE
@ HAL_TXQ_TXDESCINT_ENABLE
@ HAL_TXQ_ARB_LOCKOUT_GLOBAL
@ HAL_TXQ_TXERRINT_ENABLE
@ HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE
@ HAL_TXQ_TXURNINT_ENABLE
@ HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE
@ HAL_TXQ_TXEOLINT_ENABLE
@ HAL_TXQ_ARB_LOCKOUT_INTRA
@ HAL_TXQ_BACKOFF_DISABLE
#define HAL_TXQ_USEDEFAULT
#define HAL_TXDESC_DURENA
#define HAL_TXDESC_INTREQ
#define HAL_TXKEYIX_INVALID
#define HAL_TXDESC_CTSENA
#define HAL_TXDESC_CLRDMASK
#define HAL_TXDESC_RTSENA
#define OS_REG_SET_BIT(_a, _r, _f)
#define OS_REG_CLR_BIT(_a, _r, _f)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v)
#define HALDEBUG(_ah, __m,...)
#define ath_hal_setInterrupts(_ah, _mask)
#define OS_MEMZERO(_a, _n)
#define OS_REG_WRITE(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg)
#define MIN_TX_FIFO_THRESHOLD
#define AR_ExcessiveRetries
#define AR_AckSigStrength
#define AR_D_MISC_ARB_LOCKOUT_CNTRL
#define AR_D_LCL_IFS_CWMIN
#define AR_Q_CBRCFG_CBR_INTERVAL
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR
#define AR_Q_RDYTIMECFG_INT
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT
#define AR_D_MISC_FRAG_BKOFF_EN
#define AR_D_MISC_SEQ_NUM_INCR_DIS
#define AR_Q_MISC_FSP_CBR
#define AR_Q_MISC_FSP_DBA_GATED
#define AR_D_MISC_BEACON_USE
#define AR_IMR_S1_QCU_TXEOL
#define AR_QRDYTIMECFG(i)
#define AR_D_RETRY_LIMIT_FR_LG
#define AR_Q_MISC_CBR_INCR_DIS1
#define AR_D_MISC_VIR_COL_HANDLING_IGNORE
#define AR_Q_CBRCFG_CBR_OVF_THRESH
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
#define AR_IMR_S0_QCU_TXDESC
#define AR_D_LCL_IFS_CWMAX
#define AR_IMR_S0_QCU_TXOK
#define AR_Q_MISC_RDYTIME_EXP_POLICY
#define AR_SREV_VERSION_OAHU
#define AR_DRETRY_LIMIT(i)
#define AR_D_RETRY_LIMIT_FR_SH
#define AR_Q_MISC_FSP_ASAP
#define AR_D_LCL_IFS_AIFS
#define AR_D_RETRY_LIMIT_STA_SH
#define AR_Q_MISC_CBR_INCR_DIS0
#define AR_D_RETRY_LIMIT_STA_LG
#define AR_Q_MISC_DCU_EARLY_TERM_REQ
#define AR5311_D_MISC_SEQ_NUM_CONTROL
#define AR_D_MISC_POST_FR_BKOFF_DIS
#define AR_IMR_S1_QCU_TXERR
#define AR_Q_MISC_BEACON_USE
#define AR_IMR_S2_QCU_TXURN
HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
void ar5212SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int qcuId, u_int descId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *ds0)
void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, const HAL_TXQ_INFO *qInfo)
HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsctsDuration, u_int compicvLen, u_int compivLen, u_int comp)
HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q)
HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q)
HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
static void setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, struct ath_desc *ds, struct ath_tx_status *ts)
#define isValidPktType(_t)
void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q)
uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q)
HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q)
HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
#define isValidTxRate(_r)
HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
void ar5212GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int txRate1, u_int txTries1, u_int txRate2, u_int txTries2, u_int txRate3, u_int txTries3)
#define AR_XmitDataTries2
#define AR_XmitDataTries1
#define AR5212DESC_CONST(_ds)
#define AR_XmitDataTries3
#define AR_RTSCTSDuration
#define AR_XmitDataTries0
#define AR_Q_MISC_QCU_COMP_EN
#define AR_QUIET1_QUIET_ENABLE
#define AR_QUIET1_NEXT_QUIET
#define AR_Q_RDYTIMECFG_ENA
#define AR_QUIET2_QUIET_DUR
#define AR_D_MISC_VIR_COL_HANDLING
#define AR_DIAG_CHAN_IDLE
#define AR_D_MISC_FRAG_WAIT_EN
#define AR_QUIET2_QUIET_PER
#define AR_Q_STS_PEND_FR_CNT
int ah_additional_swba_backoff
int ah_dma_beacon_response_time
int ah_sw_beacon_response_time
HAL_TX_QUEUE_FLAGS tqi_qflags
uint32_t tqi_cbrOverflowLimit
uint32_t ds_hw[HAL_DESC_HW_SIZE]
uint32_t ah_txUrnInterruptMask
uint32_t ah_txEolInterruptMask
int16_t ah_txPowerIndexOffset
uint32_t ah_txDescInterruptMask
uint32_t ah_txOkInterruptMask
uint32_t ah_txErrInterruptMask
HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]
uint32_t ah_beaconInterval