42 uint32_t curTrigLevel, txcfg;
54 curTrigLevel = curTrigLevel +
176 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__
237 const struct ieee80211_channel *chan =
AH_PRIVATE(ah)->ah_curchan;
239 uint32_t cwMin, chanCwMin, value;
258 if (chan && IEEE80211_IS_CHAN_B(chan))
263 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
485 for (i = 0; i < 10000; i++) {
499#define VALID_PKT_TYPES \
500 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
501 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
502 (1<<HAL_PKT_TYPE_BEACON))
503#define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
504#define VALID_TX_RATES \
505 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
506 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
507 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
508#define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
516 u_int txRate0, u_int txTries0,
521 u_int rtsctsDuration,
530 (void) rtsctsRate; (void) rtsctsDuration;
560 u_int txRate1, u_int txTries1,
561 u_int txRate2, u_int txTries2,
562 u_int txRate3, u_int txTries3)
564 (void) ah; (void) ds;
565 (void) txRate1; (void) txTries1;
566 (void) txRate2; (void) txTries2;
567 (void) txRate3; (void) txTries3;
581 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int qcuId,
586 uint32_t segLen = segLenList[0];
598 }
else if (lastSeg) {
HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi)
HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo)
#define HAL_NUM_TX_QUEUES
@ HAL_TXQ_TXDESCINT_ENABLE
@ HAL_TXQ_TXERRINT_ENABLE
@ HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE
@ HAL_TXQ_TXURNINT_ENABLE
@ HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE
@ HAL_TXQ_TXEOLINT_ENABLE
@ HAL_TXQ_BACKOFF_DISABLE
#define HAL_TXQ_USEDEFAULT
#define HAL_TXDESC_INTREQ
#define HAL_TXKEYIX_INVALID
#define HAL_TXDESC_CLRDMASK
#define HAL_TXDESC_RTSENA
#define OS_REG_RMW_FIELD(_a, _r, _f, _v)
#define HALDEBUG(_ah, __m,...)
#define OS_MEMZERO(_a, _n)
#define OS_REG_WRITE(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg)
#define MIN_TX_FIFO_THRESHOLD
#define MAX_TX_FIFO_THRESHOLD
#define AR_ExcessiveRetries
#define AR_AckSigStrength
#define AR_EncryptKeyValid
#define AR_EncryptKeyIdx_S
HAL_INT ar5211GetInterrupts(struct ath_hal *)
HAL_INT ar5211SetInterrupts(struct ath_hal *, HAL_INT ints)
HAL_BOOL ar5211GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
HAL_BOOL ar5211ResetTxQueue(struct ath_hal *ah, u_int q)
HAL_BOOL ar5211SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
HAL_BOOL ar5211ReleaseTxQueue(struct ath_hal *ah, u_int q)
static void setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
void ar5211GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
#define isValidPktType(_t)
HAL_BOOL ar5211SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int txRate1, u_int txTries1, u_int txRate2, u_int txTries2, u_int txRate3, u_int txTries3)
HAL_BOOL ar5211FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int qcuId, u_int descId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *ds0)
HAL_BOOL ar5211StopTxDma(struct ath_hal *ah, u_int q)
uint32_t ar5211NumTxPending(struct ath_hal *ah, u_int q)
void ar5211GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
int ar5211SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, const HAL_TXQ_INFO *qInfo)
void ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
#define isValidTxRate(_r)
HAL_BOOL ar5211SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsctsDuration, u_int compicvLen, u_int compivLen, u_int comp)
HAL_BOOL ar5211UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
HAL_STATUS ar5211ProcTxDesc(struct ath_hal *ah, struct ath_desc *ds, struct ath_tx_status *ts)
HAL_BOOL ar5211StartTxDma(struct ath_hal *ah, u_int q)
HAL_BOOL ar5211SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
HAL_BOOL ar5211GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
void ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
void ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
uint32_t ar5211GetTxDP(struct ath_hal *ah, u_int q)
#define AR5211DESC_CONST(_ds)
#define AR_D_LCL_IFS_CWMIN
#define AR_Q_CBRCFG_CBR_INTERVAL
#define AR_Q_RDYTIMECFG_INT
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT
#define AR_D_MISC_FRAG_BKOFF_EN
#define AR_Q_MISC_FSP_CBR
#define AR_Q_MISC_FSP_DBA_GATED
#define AR_D_MISC_BEACON_USE
#define AR_IMR_S1_QCU_TXEOL
#define AR_QRDYTIMECFG(i)
#define AR_D_RETRY_LIMIT_FR_LG
#define AR_Q_MISC_CBR_INCR_DIS1
#define AR_Q_CBRCFG_CBR_OVF_THRESH
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
#define AR_IMR_S0_QCU_TXDESC
#define AR_Q_STS_PEND_FR_CNT_M
#define AR_D_LCL_IFS_CWMAX
#define AR_IMR_S0_QCU_TXOK
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S
#define AR_Q_MISC_RDYTIME_EXP_POLICY
#define AR_SREV_VERSION_OAHU
#define AR_DRETRY_LIMIT(i)
#define AR_D_RETRY_LIMIT_FR_SH
#define AR_D_LCL_IFS_AIFS
#define AR_D_RETRY_LIMIT_STA_SH
#define AR_Q_MISC_CBR_INCR_DIS0
#define AR_D_RETRY_LIMIT_STA_LG
#define AR_Q_MISC_DCU_EARLY_TERM_REQ
#define AR5311_D_MISC_SEQ_NUM_CONTROL
#define AR_D_MISC_POST_FR_BKOFF_DIS
#define AR_IMR_S1_QCU_TXERR
#define AR_Q_MISC_BEACON_USE
#define AR_Q_RDYTIMECFG_EN
#define AR_IMR_S2_QCU_TXURN
int ah_additional_swba_backoff
int ah_dma_beacon_response_time
int ah_sw_beacon_response_time
HAL_TX_QUEUE_FLAGS tqi_qflags
uint32_t tqi_cbrOverflowLimit
uint32_t ah_beaconInterval
uint32_t ah_txDescInterruptMask
HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]
uint32_t ah_txEolInterruptMask
uint32_t ah_txUrnInterruptMask
uint32_t ah_txErrInterruptMask
uint32_t ah_txOkInterruptMask