38#define STOP_DMA_TIMEOUT 4000
39#define STOP_DMA_ITER 100
55 "%s: queue %u DMA did not stop in 400 msec\n", __func__, q);
57 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
61 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
73 "%s: Num of pending TX Frames %d on Q %d\n",
78 for (j = 0; j < 2; j++) {
90 "%s: TSF moved while trying to set quiet time "
91 "TSF: 0x%08x\n", __func__, tsfLow);
109 "%s: Failed to stop Tx DMA in %d msec after killing"
118#undef STOP_DMA_TIMEOUT
121#define VALID_KEY_TYPES \
122 ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\
123 (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP))
124#define isValidKeyType(_t) ((1 << (_t)) & VALID_KEY_TYPES)
126#define set11nTries(_series, _index) \
127 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
129#define set11nRate(_series, _index) \
130 (SM((_series)[_index].Rate, AR_XmitRate##_index))
132#define set11nPktDurRTSCTS(_series, _index) \
133 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
134 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\
135 AR_RTSCTSQual##_index : 0))
137#define set11nRateFlags(_series, _index) \
138 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
139 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \
140 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \
141 |SM((_series)[_index].ChSel, AR_ChainSel##_index)
147#define VALID_PKT_TYPES \
148 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
149 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
150 (1<<HAL_PKT_TYPE_BEACON)|(1<<HAL_PKT_TYPE_AMPDU))
151#define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
152#define VALID_TX_RATES \
153 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
154 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
155 (1<<0x1d)|(1<<0x18)|(1<<0x1c)|(1<<0x01)|(1<<0x02)|(1<<0x03)|\
156 (1<<0x04)|(1<<0x05)|(1<<0x06)|(1<<0x07)|(1<<0x00))
158#define isValidTxRate(_r) ((1<<((_r) & 0x7f)) & VALID_TX_RATES)
209 if ((rate & 0x80) && is_ht40) {
211 }
else if (rate & 0x80) {
229 int n_txpower, max_txpower;
230 const int cck_ofdm_delta = 2;
231#define EEP_MINOR(_ah) \
232 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
233#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
240 n_txpower +=
AH5416(ah)->ah_ht40PowerIncForPdadc;
251 int8_t pwr_table_offset = 0;
255 n_txpower -= (pwr_table_offset * 2);
269 if (rate == 0x19 || rate == 0x1a || rate == 0x1b ||
270 rate == (0x19 | 0x04) || rate == (0x1a | 0x04) ||
271 rate == (0x1b | 0x04)) {
272 n_txpower -= cck_ofdm_delta;
283 "rate = 0x%x , is_ht40 = %d\n",
290 n_txpower =
MIN(max_txpower, n_txpower);
306 else if (n_txpower > 63)
319#undef IS_EEP_MINOR_V2
328 u_int txRate0, u_int txTries0,
333 u_int rtsctsDuration,
338#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
350 txPower = (txPower +
AH5212(ah)->ah_txPowerIndexOffset);
358 if (
AH5212(ah)->ah_tpcEnabled) {
402 "%s: invalid rts/cts rate 0x%x\n",
403 __func__, rtsctsRate);
432 u_int txRate1, u_int txTries1,
433 u_int txRate2, u_int txTries2,
434 u_int txRate3, u_int txTries3)
462 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int descId,
467 uint32_t segLen = segLenList[0];
479 }
else if (lastSeg) {
486#ifdef AH_NEED_DESC_SWAP
504#ifdef AH_NEED_DESC_SWAP
527 uint32_t *segLenList,
541 u_int segLen = segLenList[0];
544 uint32_t last_aggr = 0;
586 | (isaggr ? (
AR_IsAggr | last_aggr) : 0);
603 }
else if (lastSeg) {
613 ds_txstatus[0] = ds_txstatus[1] = 0;
614 ds_txstatus[9] &= ~AR_TxDone;
621 u_int aggrLen, u_int flags, u_int txPower,
622 u_int txRate0, u_int txTries0, u_int antMode,
623 u_int rtsctsRate, u_int rtsctsDuration)
625#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
635 if(txPower > 63) txPower=63;
655 ads->ds_ctl6 &= ~(0xffff);
687 ads->ds_ctl6 &= ~AR_PadDelim;
690#ifdef AH_NEED_DESC_SWAP
700#ifdef AH_NEED_DESC_SWAP
703ar5416SwapTxDesc(
struct ath_desc *ds)
725#ifdef AH_NEED_DESC_SWAP
726 if ((ds_txstatus[9] & __bswap32(
AR_TxDone)) == 0)
728 ar5416SwapTxDesc(ds);
854#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
876 u_int durUpdateEn, u_int rtsctsRate,
934 if (
AH5212(ah)->ah_tpcEnabled) {
941 series[0].tx_power_cap,
955 series[1].tx_power_cap,
961 series[2].tx_power_cap,
967 series[3].tx_power_cap,
1021 ads->ds_ctl6 &= ~AR_PadDelim;
1023 ads->ds_ctl6 &= ~AR_AggrLen;
1029 ds_txstatus[9] &= ~AR_TxDone;
1039 ads->ds_ctl6 &= ~AR_PadDelim;
1047 ads->
ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1048 ads->ds_ctl6 &= ~AR_PadDelim;
1049 ads->ds_ctl6 &= ~AR_AggrLen;
1060 ads->
ds_ctl0 &= ~AR_VirtMoreFrag;
1069 u_int burstDuration)
1072 uint32_t burstDur = 0;
1091 ads->ds_ctl2 &= ~AR_BurstDur;
1166 "%s: no available UAPSD tx queue\n", __func__);
1176 "%s: no available tx queue\n", __func__);
1182 "%s: bad tx queue type %u\n", __func__, type);
1221 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__,
1243#define TU_TO_USEC(_tu) ((_tu) << 10)
1249 const struct ieee80211_channel *chan =
AH_PRIVATE(ah)->ah_curchan;
1251 uint32_t cwMin, chanCwMin, qmisc, dmisc;
1272 if (chan && IEEE80211_IS_CHAN_B(chan))
1277 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
1344 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0;
1348 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1;
1397 "%s: using tqi_readyTime\n", __func__);
1428 "%s: defaulting to rdytime = %d uS\n",
#define HAL_COMP_BUF_MAX_SIZE
@ HAL_TXQ_TXDESCINT_ENABLE
@ HAL_TXQ_ARB_LOCKOUT_GLOBAL
@ HAL_TXQ_TXERRINT_ENABLE
@ HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE
@ HAL_TXQ_TXURNINT_ENABLE
@ HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE
@ HAL_TXQ_TXEOLINT_ENABLE
@ HAL_TXQ_ARB_LOCKOUT_INTRA
@ HAL_TXQ_BACKOFF_DISABLE
#define HAL_TXQ_USEDEFAULT
#define HAL_RATESERIES_2040
#define HAL_TXDESC_DURENA
#define HAL_TXERR_TIMER_EXPIRED
#define HAL_TXDESC_INTREQ
#define HAL_TX_DESC_CFG_ERR
#define HAL_TXKEYIX_INVALID
#define HAL_TXDESC_CTSENA
#define HAL_TX_DELIM_UNDERRUN
#define HAL_TX_DATA_UNDERRUN
#define HAL_TXDESC_CLRDMASK
#define HAL_TXDESC_RTSENA
@ AR_EEP_PWR_TABLE_OFFSET
#define AR5416_PWR_TABLE_OFFSET_DB
#define OS_REG_SET_BIT(_a, _r, _f)
#define ath_hal_eepromGet(_ah, _param, _val)
#define OS_REG_CLR_BIT(_a, _r, _f)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v)
#define HALDEBUG(_ah, __m,...)
#define ath_hal_eepromGetFlag(_ah, _param)
void ath_hal_printf(struct ath_hal *, const char *,...)
#define OS_MEMZERO(_a, _n)
#define OS_REG_WRITE(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg)
#define AR_ExcessiveRetries
#define AR_D_MISC_ARB_LOCKOUT_CNTRL
#define AR_D_LCL_IFS_CWMIN
#define AR_D_MISC_BKOFF_PERSISTENCE
#define AR_Q_CBRCFG_CBR_INTERVAL
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR
#define AR_Q_RDYTIMECFG_INT
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT
#define AR_D_MISC_FRAG_BKOFF_EN
#define AR_D_MISC_SEQ_NUM_INCR_DIS
#define AR_Q_MISC_FSP_CBR
#define AR_Q_MISC_FSP_DBA_GATED
#define AR_D_MISC_BEACON_USE
#define AR_IMR_S1_QCU_TXEOL
#define AR_QRDYTIMECFG(i)
#define AR_D_RETRY_LIMIT_FR_LG
#define AR_Q_MISC_CBR_INCR_DIS1
#define AR_D_MISC_VIR_COL_HANDLING_IGNORE
#define AR_Q_CBRCFG_CBR_OVF_THRESH
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
#define AR_IMR_S0_QCU_TXDESC
#define AR_D_LCL_IFS_CWMAX
#define AR_IMR_S0_QCU_TXOK
#define AR_Q_MISC_RDYTIME_EXP_POLICY
#define AR_DRETRY_LIMIT(i)
#define AR_D_RETRY_LIMIT_FR_SH
#define AR_Q_MISC_FSP_ASAP
#define AR_D_LCL_IFS_AIFS
#define AR_D_RETRY_LIMIT_STA_SH
#define AR_Q_MISC_CBR_INCR_DIS0
#define AR_D_RETRY_LIMIT_STA_LG
#define AR_Q_MISC_DCU_EARLY_TERM_REQ
#define AR_D_MISC_POST_FR_BKOFF_DIS
#define AR_IMR_S1_QCU_TXERR
#define AR_Q_MISC_BEACON_USE
#define AR_IMR_S2_QCU_TXURN
HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL IncTrigLevel)
uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q)
#define AR_XmitDataTries2
#define AR_XmitDataTries1
#define AR_XmitDataTries3
#define AR_XmitDataTries0
#define AR_Q_MISC_QCU_COMP_EN
#define AR_Q_RDYTIMECFG_ENA
#define AR_QUIET2_QUIET_DUR
#define AR_D_MISC_VIR_COL_HANDLING
#define AR_DIAG_CHAN_IDLE
#define AR_D_MISC_FRAG_WAIT_EN
void ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, u_int burstDuration)
void ar5416Set11nVirtualMoreFrag(struct ath_hal *ah, struct ath_desc *ds, u_int vmf)
HAL_BOOL ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds, HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int keyIx, HAL_CIPHER cipher, uint8_t delims, HAL_BOOL firstSeg, HAL_BOOL lastSeg, HAL_BOOL lastAggr)
HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, u_int txRate0, u_int txTries0, u_int keyIx, u_int antMode, u_int flags, u_int rtsctsRate, u_int rtsctsDuration, u_int compicvLen, u_int compivLen, u_int comp)
HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu)
static const u_int8_t baDurationDelta[]
HAL_BOOL ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
HAL_BOOL ar5416SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int txRate1, u_int txTries1, u_int txRate2, u_int txTries2, u_int txRate3, u_int txTries3)
#define set11nPktDurRTSCTS(_series, _index)
static void setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
#define isValidPktType(_t)
static uint16_t ar5416GetTxRatePower(struct ath_hal *ah, uint8_t rate, uint8_t tx_chainmask, uint16_t txPower, HAL_BOOL is_ht40)
HAL_BOOL ar5416ResetTxQueue(struct ath_hal *ah, u_int q)
void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, u_int durUpdateEn, u_int rtsctsRate, HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags)
void ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds)
static int ar5416RateToRateTable(struct ath_hal *ah, uint8_t rate, HAL_BOOL is_ht40)
#define set11nRateFlags(_series, _index)
HAL_BOOL ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *ds0)
#define isValidTxRate(_r)
void ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)
void ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, u_int numDelims)
HAL_STATUS ar5416ProcTxDesc(struct ath_hal *ah, struct ath_desc *ds, struct ath_tx_status *ts)
HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q)
void ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds)
HAL_BOOL ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds, const struct ath_desc *ds0)
HAL_BOOL ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, u_int flags, u_int txPower, u_int txRate0, u_int txTries0, u_int antMode, u_int rtsctsRate, u_int rtsctsDuration)
u_int ar5416GetGlobalTxTimeout(struct ath_hal *ah)
int ar5416SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, const HAL_TXQ_INFO *qInfo)
#define set11nTries(_series, _index)
#define set11nRate(_series, _index)
#define AR_TxRSSICombined
#define AR_TxDelimUnderrun
#define AR_BaBitmapHigh(_ptr)
#define AR_TxDataUnderrun
#define AR5416_DESC_TX_CTL_SZ
#define AR_BaBitmapLow(_ptr)
#define AR_TxTimerExpired
#define AR5416_DS_TXSTATUS(_ah, _ads)
#define AR5416DESC_CONST(_ds)
#define AR_SREV_KIWI_10_OR_LATER(_ah)
#define AR_SREV_KITE(_ah)
#define AR_SREV_MERLIN_20_OR_LATER(_ah)
#define AR_SREV_MERLIN_10_OR_LATER(_ah)
#define AR_TIMER_MODE_QUIET
#define AR_GTXTO_TIMEOUT_LIMIT
int ah_additional_swba_backoff
int ah_dma_beacon_response_time
int ah_sw_beacon_response_time
HAL_TX_QUEUE_FLAGS tqi_qflags
uint32_t tqi_cbrOverflowLimit
uint32_t status[AR5416_NUM_TX_STATUS]
uint32_t ds_hw[HAL_DESC_HW_SIZE]
uint32_t ah_txUrnInterruptMask
uint32_t ah_txEolInterruptMask
int16_t ah_txPowerIndexOffset
uint32_t ah_txDescInterruptMask
uint32_t ah_txOkInterruptMask
uint32_t ah_txErrInterruptMask
HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]
uint32_t ah_beaconInterval
uint8_t ah_keytype[AR5416_KEYTABLE_SIZE]