37#include <sys/devmap.h>
39#include <sys/kernel.h>
41#include <sys/malloc.h>
42#include <sys/module.h>
46#include <machine/bus.h>
47#include <machine/intr.h>
48#include <machine/resource.h>
50#include <dev/ofw/ofw_bus.h>
51#include <dev/ofw/ofw_bus_subr.h>
52#include <dev/ofw/ofw_pci.h>
53#include <dev/ofw/ofwpci.h>
63#define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
65#define debugf(fmt, args...)
68#define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val)
69#define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val)
70#define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val)
71#define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg)
72#define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg)
73#define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg)
75#define IATU_UR_WR4(sc, reg, val) \
76 bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val))
77#define IATU_UR_RD4(sc, reg) \
78 bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg))
80#define PCI_BUS_SHIFT 20
81#define PCI_SLOT_SHIFT 15
82#define PCI_FUNC_SHIFT 12
83#define PCI_BUS_MASK 0xFF
84#define PCI_SLOT_MASK 0x1F
85#define PCI_FUNC_MASK 0x07
86#define PCI_REG_MASK 0xFFF
88#define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24)
89#define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19)
90#define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16)
97 sc = device_get_softc(
dev);
108 device_printf(sc->
dev,
"Unsupported width: %d\n",
width);
118 sc = device_get_softc(
dev);
132 device_printf(sc->
dev,
"Unsupported width: %d\n",
width);
144 reg &= ~DBI_RO_WR_EN;
189 for (i = 0; i < num_regions; ++i) {
193 if (
reg != 0x12340000)
205 int num_viewports, i;
212 device_printf(sc->
dev,
213 "Cannot detect number of output iATU regions; read %#x\n",
218 num_viewports =
reg + 1;
224 for (i = 0; i < num_viewports; ++i) {
228 if (
reg != 0x12340000)
248 uint64_t pa, uint64_t pci_addr, uint32_t size)
259 (pa >> 32) & 0xFFFFFFFF);
261 (pa + size - 1) & 0xFFFFFFFF);
263 pci_addr & 0xFFFFFFFF);
265 (pci_addr >> 32) & 0xFFFFFFFF);
272 for (i = 10; i > 0; i--) {
279 device_printf(sc->
dev,
280 "Cannot map outbound region %d in unroll mode iATU\n", idx);
286 uint64_t pa, uint64_t pci_addr, uint32_t size)
304 for (i = 10; i > 0; i--) {
311 device_printf(sc->
dev,
312 "Cannot map outbound region %d in legacy mode iATU\n", idx);
319 uint64_t pa, uint64_t pci_addr, uint32_t size)
373 reg &= ~PORT_LINK_CAPABLE(~0);
394 device_printf(sc->
dev,
395 "'num-lanes' property have invalid value: %d\n",
403 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0);
440 for (i = 0; i < nranges; i++) {
441 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
442 OFW_PCI_PHYS_HI_SPACE_MEM32)
451 for (i = 0; i < nranges; i++) {
452 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
453 OFW_PCI_PHYS_HI_SPACE_IO) {
455 device_printf(sc->
dev,
456 "Duplicated IO range found in DT\n");
462 if (sc->
io_range.size > UINT32_MAX) {
463 device_printf(sc->
dev,
464 "ATU IO window size is too large. "
465 "Up to 4GB windows are supported, "
466 "trimming window size to 4GB\n");
470 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
471 OFW_PCI_PHYS_HI_SPACE_MEM32) {
475 device_printf(sc->
dev,
476 "ATU MEM window size is too large. "
477 "Up to 4GB windows are supported, "
478 "trimming window size to 4GB\n");
488 device_printf(sc->
dev,
489 "Missing required memory range in DT\n");
507 u_int
func, u_int
reg,
int bytes)
510 struct resource *res;
515 sc = device_get_softc(
dev);
518 return (0xFFFFFFFFU);
532 return (0xFFFFFFFFU);
556 u_int
func, u_int
reg, uint32_t
val,
int bytes)
559 struct resource *res;
563 sc = device_get_softc(
dev);
585 bus_write_1(res,
reg,
val);
588 bus_write_2(res,
reg,
val);
591 bus_write_4(res,
reg,
val);
602 phandle_t msi_parent;
605 rv = ofw_bus_msimap(ofw_bus_get_node(
pci), pci_get_rid(
child),
617 phandle_t msi_parent;
620 rv = ofw_bus_msimap(ofw_bus_get_node(
pci), pci_get_rid(
child),
631 phandle_t msi_parent;
634 rv = ofw_bus_msimap(ofw_bus_get_node(
pci), pci_get_rid(
child),
645 phandle_t msi_parent;
648 rv = ofw_bus_msimap(ofw_bus_get_node(
pci), pci_get_rid(
child),
652 return (intr_alloc_msix(
pci,
child, msi_parent,
irq));
658 phandle_t msi_parent;
661 rv = ofw_bus_msimap(ofw_bus_get_node(
pci), pci_get_rid(
child),
665 return (intr_release_msix(
pci,
child, msi_parent,
irq));
680 node = ofw_bus_get_node(
pci);
681 pci_rid = pci_get_rid(
child);
683 rv = ofw_bus_msimap(node, pci_rid, NULL, &
rid);
700 sc = device_get_softc(
dev);
711 sc = device_get_softc(
dev);
713 sc->
node = ofw_bus_get_node(
dev);
715 mtx_init(&sc->
mtx,
"pci_dw_mtx", NULL, MTX_DEF);
734 "invalid number of lanes: %d\n",sc->
num_lanes);
741 rv = ofw_bus_find_string_index(sc->
node,
"reg-names",
"config", &
rid);
743 device_printf(
dev,
"Cannot get config space memory\n");
747 sc->
cfg_res = bus_alloc_resource_any(
dev, SYS_RES_MEMORY, &
rid,
750 device_printf(
dev,
"Cannot allocate config space(rid: %d)\n",
761 device_printf(
dev,
"Bus is%s cache-coherent\n",
763 rv = bus_dma_tag_create(bus_get_dma_tag(
dev),
769 BUS_SPACE_UNRESTRICTED,
771 sc->
coherent ? BUS_DMA_COHERENT : 0,
777 rv = ofw_pcib_init(
dev);
787 device_printf(
dev,
"Using iATU %s mode\n",
788 unroll_mode ?
"unroll" :
"legacy");
791 rv = ofw_bus_find_string_index(sc->
node,
"reg-names",
"atu", &
rid);
794 SYS_RES_MEMORY, &
rid, RF_ACTIVE);
797 "Cannot allocate iATU space (rid: %d)\n",
804 }
else if (rv == ENOENT) {
809 device_printf(
dev,
"Cannot get iATU space memory\n");
820 device_printf(sc->
dev,
"Detected outbound iATU regions: %d\n",
827 device_add_child(
dev,
"pci", -1);
850 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
851 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
852 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
853 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
854 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
static bool pci_dw_check_dev(struct pci_dw_softc *sc, u_int bus, u_int slot, u_int func, u_int reg)
static int pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs)
static int pci_dw_detect_out_atu_regions(struct pci_dw_softc *sc)
static void pci_dw_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int bytes)
static device_method_t pci_dw_methods[]
static int pci_dw_detect_out_atu_regions_legacy(struct pci_dw_softc *sc)
#define IATU_UR_RD4(sc, reg)
static int pci_dw_alloc_msix(device_t pci, device_t child, int *irq)
#define DBI_WR2(sc, reg, val)
static int pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges, int nranges)
#define DBI_WR1(sc, reg, val)
static int pci_dw_setup_hw(struct pci_dw_softc *sc)
static int pci_dw_map_out_atu_unroll(struct pci_dw_softc *sc, int idx, int type, uint64_t pa, uint64_t pci_addr, uint32_t size)
static int pci_dw_map_out_atu(struct pci_dw_softc *sc, int idx, int type, uint64_t pa, uint64_t pci_addr, uint32_t size)
static uint32_t pci_dw_dbi_read(device_t dev, u_int reg, int width)
static int pci_dw_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs)
static void pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect)
static int pci_dw_map_out_atu_legacy(struct pci_dw_softc *sc, int idx, int type, uint64_t pa, uint64_t pci_addr, uint32_t size)
#define IATU_UR_WR4(sc, reg, val)
#define IATU_CFG_FUNC(func)
static int pci_dw_release_msix(device_t pci, device_t child, int irq)
static uint32_t pci_dw_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes)
DEFINE_CLASS_1(pcib, pci_dw_driver, pci_dw_methods, sizeof(struct pci_dw_softc), ofw_pcib_driver)
static bus_dma_tag_t pci_dw_get_dma_tag(device_t dev, device_t child)
static int pci_dw_get_id(device_t pci, device_t child, enum pci_id_type type, uintptr_t *id)
#define IATU_CFG_BUS(bus)
static bool pci_dw_detect_atu_unroll(struct pci_dw_softc *sc)
#define IATU_CFG_SLOT(slot)
#define DBI_WR4(sc, reg, val)
static int pci_dw_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data)
static int pci_dw_detect_out_atu_regions_unroll(struct pci_dw_softc *sc)
static void pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width)
int pci_dw_init(device_t dev)
#define PORT_LINK_CAPABLE_32
#define GEN2_CTRL_NUM_OF_LANES(n)
#define PORT_LINK_CAPABLE(n)
#define PORT_LINK_CAPABLE_8
#define IATU_CTRL1_TYPE_CFG1
#define DW_IATU_LWR_TARGET_ADDR
#define DW_PORT_LINK_CTRL
#define DW_IATU_LIMIT_ADDR
#define DW_MISC_CONTROL_1
#define GEN2_CTRL_NUM_OF_LANES_8
#define IATU_CTRL1_TYPE_IO
#define PORT_LINK_CAPABLE_2
#define GEN2_CTRL_NUM_OF_LANES_16
#define GEN2_CTRL_NUM_OF_LANES_32
#define GEN2_CTRL_NUM_OF_LANES_2
#define PORT_LINK_CAPABLE_1
#define IATU_CTRL1_TYPE(x)
#define DW_IATU_UR_REG(r, n)
#define IATU_CTRL1_TYPE_CFG0
#define DW_DEFAULT_IATU_UR_DBI_SIZE
#define DW_IATU_UPPER_TARGET_ADDR
#define DW_IATU_LWR_BASE_ADDR
#define PORT_LINK_CAPABLE_16
#define GEN2_CTRL_NUM_OF_LANES_1
#define IATU_CTRL2_REGION_EN
#define GEN2_CTRL_NUM_OF_LANES_4
#define IATU_REGION_INDEX(x)
#define DW_IATU_UPPER_BASE_ADDR
#define PORT_LINK_CAPABLE_4
#define IATU_CTRL1_TYPE_MEM
#define DW_DEFAULT_IATU_UR_DBI_OFFSET
#define DIRECT_SPEED_CHANGE
static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
int pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
int pcib_release_msix(device_t pcib, device_t dev, int irq)
int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data)
static void pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
#define PCIM_CMD_BUSMASTEREN
#define PCIM_CMD_SERRESPEN
bus_addr_t iatu_ur_offset
struct resource * dbi_res
struct resource * iatu_ur_res
struct resource * cfg_res
struct ofw_pci_softc ofw_pci
struct ofw_pci_range io_range
struct ofw_pci_range * mem_ranges