38#define DW_PORT_LINK_CTRL 0x710
39#define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16)
40#define PORT_LINK_CAPABLE_1 0x01
41#define PORT_LINK_CAPABLE_2 0x03
42#define PORT_LINK_CAPABLE_4 0x07
43#define PORT_LINK_CAPABLE_8 0x0F
44#define PORT_LINK_CAPABLE_16 0x1F
45#define PORT_LINK_CAPABLE_32 0x3F
47#define DW_GEN2_CTRL 0x80C
48#define DIRECT_SPEED_CHANGE (1 << 17)
49#define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8)
50#define GEN2_CTRL_NUM_OF_LANES_1 0x01
51#define GEN2_CTRL_NUM_OF_LANES_2 0x03
52#define GEN2_CTRL_NUM_OF_LANES_4 0x07
53#define GEN2_CTRL_NUM_OF_LANES_8 0x0F
54#define GEN2_CTRL_NUM_OF_LANES_16 0x1F
55#define GEN2_CTRL_NUM_OF_LANES_32 0x3F
57#define DW_MSI_ADDR_LO 0x820
58#define DW_MSI_ADDR_HI 0x824
59#define DW_MSI_INTR0_ENABLE 0x828
60#define DW_MSI_INTR0_MASK 0x82C
61#define DW_MSI_INTR0_STATUS 0x830
63#define DW_MISC_CONTROL_1 0x8BC
64#define DBI_RO_WR_EN (1 << 0)
67#define DW_IATU_VIEWPORT 0x900
68#define IATU_REGION_INBOUND (1U << 31)
69#define IATU_REGION_INDEX(x) ((x) & 0x7)
70#define DW_IATU_CTRL1 0x904
71#define IATU_CTRL1_TYPE(x) ((x) & 0x1F)
72#define IATU_CTRL1_TYPE_MEM 0x0
73#define IATU_CTRL1_TYPE_IO 0x2
74#define IATU_CTRL1_TYPE_CFG0 0x4
75#define IATU_CTRL1_TYPE_CFG1 0x5
76#define DW_IATU_CTRL2 0x908
77#define IATU_CTRL2_REGION_EN (1U << 31)
78#define DW_IATU_LWR_BASE_ADDR 0x90C
79#define DW_IATU_UPPER_BASE_ADDR 0x910
80#define DW_IATU_LIMIT_ADDR 0x914
81#define DW_IATU_LWR_TARGET_ADDR 0x918
82#define DW_IATU_UPPER_TARGET_ADDR 0x91C
85#define DW_IATU_UR_STEP 0x200
86#define DW_IATU_UR_REG(r, n) (r) * DW_IATU_UR_STEP + IATU_UR_##n
87#define IATU_UR_CTRL1 0x00
88#define IATU_UR_CTRL2 0x04
89#define IATU_UR_LWR_BASE_ADDR 0x08
90#define IATU_UR_UPPER_BASE_ADDR 0x0C
91#define IATU_UR_LIMIT_ADDR 0x10
92#define IATU_UR_LWR_TARGET_ADDR 0x14
93#define IATU_UR_UPPER_TARGET_ADDR 0x18
95#define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000
96#define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000
151static inline uint32_t
154 return (PCI_DW_DBI_READ(
dev,
reg, 4));
157static inline uint16_t
160 return ((uint16_t)PCI_DW_DBI_READ(
dev,
reg, 2));
166 return ((uint8_t)PCI_DW_DBI_READ(
dev,
reg, 1));
static uint16_t pci_dw_dbi_rd2(device_t dev, u_int reg)
static void pci_dw_dbi_wr1(device_t dev, u_int reg, uint8_t val)
DECLARE_CLASS(pci_dw_driver)
static void pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val)
static void pci_dw_dbi_wr2(device_t dev, u_int reg, uint16_t val)
int pci_dw_init(device_t)
static uint32_t pci_dw_dbi_rd4(device_t dev, u_int reg)
static uint8_t pci_dw_dbi_rd1(device_t dev, u_int reg)
bus_addr_t iatu_ur_offset
struct resource * dbi_res
struct resource * iatu_ur_res
struct resource * cfg_res
struct ofw_pci_softc ofw_pci
struct ofw_pci_range io_range
struct ofw_pci_range * mem_ranges