#include "pci_dw_if.h"
Go to the source code of this file.
◆ DBI_RO_WR_EN
#define DBI_RO_WR_EN (1 << 0) |
◆ DIRECT_SPEED_CHANGE
#define DIRECT_SPEED_CHANGE (1 << 17) |
◆ DW_DEFAULT_IATU_UR_DBI_OFFSET
#define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000 |
◆ DW_DEFAULT_IATU_UR_DBI_SIZE
#define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000 |
◆ DW_GEN2_CTRL
#define DW_GEN2_CTRL 0x80C |
◆ DW_IATU_CTRL1
#define DW_IATU_CTRL1 0x904 |
◆ DW_IATU_CTRL2
#define DW_IATU_CTRL2 0x908 |
◆ DW_IATU_LIMIT_ADDR
#define DW_IATU_LIMIT_ADDR 0x914 |
◆ DW_IATU_LWR_BASE_ADDR
#define DW_IATU_LWR_BASE_ADDR 0x90C |
◆ DW_IATU_LWR_TARGET_ADDR
#define DW_IATU_LWR_TARGET_ADDR 0x918 |
◆ DW_IATU_UPPER_BASE_ADDR
#define DW_IATU_UPPER_BASE_ADDR 0x910 |
◆ DW_IATU_UPPER_TARGET_ADDR
#define DW_IATU_UPPER_TARGET_ADDR 0x91C |
◆ DW_IATU_UR_REG
◆ DW_IATU_UR_STEP
#define DW_IATU_UR_STEP 0x200 |
◆ DW_IATU_VIEWPORT
#define DW_IATU_VIEWPORT 0x900 |
◆ DW_MISC_CONTROL_1
#define DW_MISC_CONTROL_1 0x8BC |
◆ DW_MSI_ADDR_HI
#define DW_MSI_ADDR_HI 0x824 |
◆ DW_MSI_ADDR_LO
#define DW_MSI_ADDR_LO 0x820 |
◆ DW_MSI_INTR0_ENABLE
#define DW_MSI_INTR0_ENABLE 0x828 |
◆ DW_MSI_INTR0_MASK
#define DW_MSI_INTR0_MASK 0x82C |
◆ DW_MSI_INTR0_STATUS
#define DW_MSI_INTR0_STATUS 0x830 |
◆ DW_PORT_LINK_CTRL
#define DW_PORT_LINK_CTRL 0x710 |
◆ GEN2_CTRL_NUM_OF_LANES
#define GEN2_CTRL_NUM_OF_LANES |
( |
|
n | ) |
(((n) & 0x3F) << 8) |
◆ GEN2_CTRL_NUM_OF_LANES_1
#define GEN2_CTRL_NUM_OF_LANES_1 0x01 |
◆ GEN2_CTRL_NUM_OF_LANES_16
#define GEN2_CTRL_NUM_OF_LANES_16 0x1F |
◆ GEN2_CTRL_NUM_OF_LANES_2
#define GEN2_CTRL_NUM_OF_LANES_2 0x03 |
◆ GEN2_CTRL_NUM_OF_LANES_32
#define GEN2_CTRL_NUM_OF_LANES_32 0x3F |
◆ GEN2_CTRL_NUM_OF_LANES_4
#define GEN2_CTRL_NUM_OF_LANES_4 0x07 |
◆ GEN2_CTRL_NUM_OF_LANES_8
#define GEN2_CTRL_NUM_OF_LANES_8 0x0F |
◆ IATU_CTRL1_TYPE
#define IATU_CTRL1_TYPE |
( |
|
x | ) |
((x) & 0x1F) |
◆ IATU_CTRL1_TYPE_CFG0
#define IATU_CTRL1_TYPE_CFG0 0x4 |
◆ IATU_CTRL1_TYPE_CFG1
#define IATU_CTRL1_TYPE_CFG1 0x5 |
◆ IATU_CTRL1_TYPE_IO
#define IATU_CTRL1_TYPE_IO 0x2 |
◆ IATU_CTRL1_TYPE_MEM
#define IATU_CTRL1_TYPE_MEM 0x0 |
◆ IATU_CTRL2_REGION_EN
#define IATU_CTRL2_REGION_EN (1U << 31) |
◆ IATU_REGION_INBOUND
#define IATU_REGION_INBOUND (1U << 31) |
◆ IATU_REGION_INDEX
#define IATU_REGION_INDEX |
( |
|
x | ) |
((x) & 0x7) |
◆ IATU_UR_CTRL1
#define IATU_UR_CTRL1 0x00 |
◆ IATU_UR_CTRL2
#define IATU_UR_CTRL2 0x04 |
◆ IATU_UR_LIMIT_ADDR
#define IATU_UR_LIMIT_ADDR 0x10 |
◆ IATU_UR_LWR_BASE_ADDR
#define IATU_UR_LWR_BASE_ADDR 0x08 |
◆ IATU_UR_LWR_TARGET_ADDR
#define IATU_UR_LWR_TARGET_ADDR 0x14 |
◆ IATU_UR_UPPER_BASE_ADDR
#define IATU_UR_UPPER_BASE_ADDR 0x0C |
◆ IATU_UR_UPPER_TARGET_ADDR
#define IATU_UR_UPPER_TARGET_ADDR 0x18 |
◆ PORT_LINK_CAPABLE
#define PORT_LINK_CAPABLE |
( |
|
n | ) |
(((n) & 0x3F) << 16) |
◆ PORT_LINK_CAPABLE_1
#define PORT_LINK_CAPABLE_1 0x01 |
◆ PORT_LINK_CAPABLE_16
#define PORT_LINK_CAPABLE_16 0x1F |
◆ PORT_LINK_CAPABLE_2
#define PORT_LINK_CAPABLE_2 0x03 |
◆ PORT_LINK_CAPABLE_32
#define PORT_LINK_CAPABLE_32 0x3F |
◆ PORT_LINK_CAPABLE_4
#define PORT_LINK_CAPABLE_4 0x07 |
◆ PORT_LINK_CAPABLE_8
#define PORT_LINK_CAPABLE_8 0x0F |
◆ DECLARE_CLASS()
DECLARE_CLASS |
( |
pci_dw_driver |
| ) |
|
◆ pci_dw_dbi_rd1()
static uint8_t pci_dw_dbi_rd1 |
( |
device_t |
dev, |
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u_int |
reg |
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) |
| |
|
inlinestatic |
◆ pci_dw_dbi_rd2()
static uint16_t pci_dw_dbi_rd2 |
( |
device_t |
dev, |
|
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u_int |
reg |
|
) |
| |
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inlinestatic |
◆ pci_dw_dbi_rd4()
static uint32_t pci_dw_dbi_rd4 |
( |
device_t |
dev, |
|
|
u_int |
reg |
|
) |
| |
|
inlinestatic |
◆ pci_dw_dbi_wr1()
static void pci_dw_dbi_wr1 |
( |
device_t |
dev, |
|
|
u_int |
reg, |
|
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uint8_t |
val |
|
) |
| |
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inlinestatic |
◆ pci_dw_dbi_wr2()
static void pci_dw_dbi_wr2 |
( |
device_t |
dev, |
|
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u_int |
reg, |
|
|
uint16_t |
val |
|
) |
| |
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inlinestatic |
◆ pci_dw_dbi_wr4()
static void pci_dw_dbi_wr4 |
( |
device_t |
dev, |
|
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u_int |
reg, |
|
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uint32_t |
val |
|
) |
| |
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inlinestatic |
◆ pci_dw_init()
int pci_dw_init |
( |
device_t |
dev | ) |
|
Definition at line 705 of file pci_dw.c.
References pci_dw_softc::bus_end, pci_dw_softc::bus_start, pci_dw_softc::cfg_pa, pci_dw_softc::cfg_res, pci_dw_softc::cfg_size, pci_dw_softc::coherent, pci_dw_softc::dbi_res, pci_dw_softc::dev, dev, pci_dw_softc::dmat, DW_DEFAULT_IATU_UR_DBI_OFFSET, DW_DEFAULT_IATU_UR_DBI_SIZE, pci_dw_softc::iatu_ur_offset, pci_dw_softc::iatu_ur_res, pci_dw_softc::iatu_ur_size, pci_dw_softc::mtx, pci_dw_softc::node, pci_dw_softc::num_lanes, pci_dw_softc::num_out_regions, pci_dw_softc::ofw_pci, pci_dw_decode_ranges(), pci_dw_detect_atu_unroll(), pci_dw_detect_out_atu_regions(), pci_dw_setup_hw(), rid, pci_dw_softc::root_bus, and pci_dw_softc::sub_bus.
Referenced by pci_mv_attach().