FreeBSD kernel amd64 PCI device code
Macros
pcireg.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define PCI_DOMAINMAX   65535 /* highest supported domain number */
 
#define PCI_BUSMAX   255 /* highest supported bus number */
 
#define PCI_SLOTMAX   31 /* highest supported slot number */
 
#define PCI_FUNCMAX   7 /* highest supported function number */
 
#define PCI_REGMAX   255 /* highest supported config register addr. */
 
#define PCIE_REGMAX   4095 /* highest supported config register addr. */
 
#define PCI_MAXHDRTYPE   2
 
#define PCIE_ARI_SLOTMAX   0
 
#define PCIE_ARI_FUNCMAX   255
 
#define PCI_RID_DOMAIN_SHIFT   16
 
#define PCI_RID_BUS_SHIFT   8
 
#define PCI_RID_SLOT_SHIFT   3
 
#define PCI_RID_FUNC_SHIFT   0
 
#define PCI_RID(bus, slot, func)
 
#define PCI_ARI_RID(bus, func)
 
#define PCI_RID2BUS(rid)   (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX)
 
#define PCI_RID2SLOT(rid)   (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
 
#define PCI_RID2FUNC(rid)   (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
 
#define PCIE_ARI_RID2SLOT(rid)   (0)
 
#define PCIE_ARI_RID2FUNC(rid)    (((rid) >> PCI_RID_FUNC_SHIFT) & PCIE_ARI_FUNCMAX)
 
#define PCIE_ARI_SLOT(func)   (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
 
#define PCIE_ARI_FUNC(func)   (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
 
#define PCIR_DEVVENDOR   0x00
 
#define PCIR_VENDOR   0x00
 
#define PCIR_DEVICE   0x02
 
#define PCIR_COMMAND   0x04
 
#define PCIM_CMD_PORTEN   0x0001
 
#define PCIM_CMD_MEMEN   0x0002
 
#define PCIM_CMD_BUSMASTEREN   0x0004
 
#define PCIM_CMD_SPECIALEN   0x0008
 
#define PCIM_CMD_MWRICEN   0x0010
 
#define PCIM_CMD_PERRESPEN   0x0040
 
#define PCIM_CMD_SERRESPEN   0x0100
 
#define PCIM_CMD_BACKTOBACK   0x0200
 
#define PCIM_CMD_INTxDIS   0x0400
 
#define PCIR_STATUS   0x06
 
#define PCIM_STATUS_INTxSTATE   0x0008
 
#define PCIM_STATUS_CAPPRESENT   0x0010
 
#define PCIM_STATUS_66CAPABLE   0x0020
 
#define PCIM_STATUS_BACKTOBACK   0x0080
 
#define PCIM_STATUS_MDPERR   0x0100
 
#define PCIM_STATUS_SEL_FAST   0x0000
 
#define PCIM_STATUS_SEL_MEDIMUM   0x0200
 
#define PCIM_STATUS_SEL_SLOW   0x0400
 
#define PCIM_STATUS_SEL_MASK   0x0600
 
#define PCIM_STATUS_STABORT   0x0800
 
#define PCIM_STATUS_RTABORT   0x1000
 
#define PCIM_STATUS_RMABORT   0x2000
 
#define PCIM_STATUS_SERR   0x4000
 
#define PCIM_STATUS_PERR   0x8000
 
#define PCIR_REVID   0x08
 
#define PCIR_PROGIF   0x09
 
#define PCIR_SUBCLASS   0x0a
 
#define PCIR_CLASS   0x0b
 
#define PCIR_CACHELNSZ   0x0c
 
#define PCIR_LATTIMER   0x0d
 
#define PCIR_HDRTYPE   0x0e
 
#define PCIM_HDRTYPE   0x7f
 
#define PCIM_HDRTYPE_NORMAL   0x00
 
#define PCIM_HDRTYPE_BRIDGE   0x01
 
#define PCIM_HDRTYPE_CARDBUS   0x02
 
#define PCIM_MFDEV   0x80
 
#define PCIR_BIST   0x0f
 
#define PCIV_INVALID   0xffff
 
#define PCICAP_ID   0x0
 
#define PCICAP_NEXTPTR   0x1
 
#define PCIY_PMG   0x01 /* PCI Power Management */
 
#define PCIY_AGP   0x02 /* AGP */
 
#define PCIY_VPD   0x03 /* Vital Product Data */
 
#define PCIY_SLOTID   0x04 /* Slot Identification */
 
#define PCIY_MSI   0x05 /* Message Signaled Interrupts */
 
#define PCIY_CHSWP   0x06 /* CompactPCI Hot Swap */
 
#define PCIY_PCIX   0x07 /* PCI-X */
 
#define PCIY_HT   0x08 /* HyperTransport */
 
#define PCIY_VENDOR   0x09 /* Vendor Unique */
 
#define PCIY_DEBUG   0x0a /* Debug port */
 
#define PCIY_CRES   0x0b /* CompactPCI central resource control */
 
#define PCIY_HOTPLUG   0x0c /* PCI Hot-Plug */
 
#define PCIY_SUBVENDOR   0x0d /* PCI-PCI bridge subvendor ID */
 
#define PCIY_AGP8X   0x0e /* AGP 8x */
 
#define PCIY_SECDEV   0x0f /* Secure Device */
 
#define PCIY_EXPRESS   0x10 /* PCI Express */
 
#define PCIY_MSIX   0x11 /* MSI-X */
 
#define PCIY_SATA   0x12 /* SATA */
 
#define PCIY_PCIAF   0x13 /* PCI Advanced Features */
 
#define PCIY_EA   0x14 /* PCI Extended Allocation */
 
#define PCIY_FPB   0x15 /* Flattening Portal Bridge */
 
#define PCIR_EXTCAP   0x100
 
#define PCIM_EXTCAP_ID   0x0000ffff
 
#define PCIM_EXTCAP_VER   0x000f0000
 
#define PCIM_EXTCAP_NEXTPTR   0xfff00000
 
#define PCI_EXTCAP_ID(ecap)   ((ecap) & PCIM_EXTCAP_ID)
 
#define PCI_EXTCAP_VER(ecap)   (((ecap) & PCIM_EXTCAP_VER) >> 16)
 
#define PCI_EXTCAP_NEXTPTR(ecap)   (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
 
#define PCIZ_AER   0x0001 /* Advanced Error Reporting */
 
#define PCIZ_VC   0x0002 /* Virtual Channel if MFVC Ext Cap not set */
 
#define PCIZ_SERNUM   0x0003 /* Device Serial Number */
 
#define PCIZ_PWRBDGT   0x0004 /* Power Budgeting */
 
#define PCIZ_RCLINK_DCL   0x0005 /* Root Complex Link Declaration */
 
#define PCIZ_RCLINK_CTL   0x0006 /* Root Complex Internal Link Control */
 
#define PCIZ_RCEC_ASSOC   0x0007 /* Root Complex Event Collector Association */
 
#define PCIZ_MFVC   0x0008 /* Multi-Function Virtual Channel */
 
#define PCIZ_VC2   0x0009 /* Virtual Channel if MFVC Ext Cap set */
 
#define PCIZ_RCRB   0x000a /* RCRB Header */
 
#define PCIZ_VENDOR   0x000b /* Vendor Unique */
 
#define PCIZ_CAC   0x000c /* Configuration Access Correction -- obsolete */
 
#define PCIZ_ACS   0x000d /* Access Control Services */
 
#define PCIZ_ARI   0x000e /* Alternative Routing-ID Interpretation */
 
#define PCIZ_ATS   0x000f /* Address Translation Services */
 
#define PCIZ_SRIOV   0x0010 /* Single Root IO Virtualization */
 
#define PCIZ_MRIOV   0x0011 /* Multiple Root IO Virtualization */
 
#define PCIZ_MULTICAST   0x0012 /* Multicast */
 
#define PCIZ_PAGE_REQ   0x0013 /* Page Request */
 
#define PCIZ_AMD   0x0014 /* Reserved for AMD */
 
#define PCIZ_RESIZE_BAR   0x0015 /* Resizable BAR */
 
#define PCIZ_DPA   0x0016 /* Dynamic Power Allocation */
 
#define PCIZ_TPH_REQ   0x0017 /* TPH Requester */
 
#define PCIZ_LTR   0x0018 /* Latency Tolerance Reporting */
 
#define PCIZ_SEC_PCIE   0x0019 /* Secondary PCI Express */
 
#define PCIZ_PMUX   0x001a /* Protocol Multiplexing */
 
#define PCIZ_PASID   0x001b /* Process Address Space ID */
 
#define PCIZ_LN_REQ   0x001c /* LN Requester */
 
#define PCIZ_DPC   0x001d /* Downstream Port Containment */
 
#define PCIZ_L1PM   0x001e /* L1 PM Substates */
 
#define PCIZ_PTM   0x001f /* Precision Time Measurement */
 
#define PCIZ_M_PCIE   0x0020 /* PCIe over M-PHY */
 
#define PCIZ_FRS   0x0021 /* FRS Queuing */
 
#define PCIZ_RTR   0x0022 /* Readiness Time Reporting */
 
#define PCIZ_DVSEC   0x0023 /* Designated Vendor-Specific */
 
#define PCIZ_VF_REBAR   0x0024 /* VF Resizable BAR */
 
#define PCIZ_DLNK   0x0025 /* Data Link Feature */
 
#define PCIZ_16GT   0x0026 /* Physical Layer 16.0 GT/s */
 
#define PCIZ_LMR   0x0027 /* Lane Margining at Receiver */
 
#define PCIZ_HIER_ID   0x0028 /* Hierarchy ID */
 
#define PCIZ_NPEM   0x0029 /* Native PCIe Enclosure Management */
 
#define PCIZ_PL32   0x002a /* Physical Layer 32.0 GT/s */
 
#define PCIZ_AP   0x002b /* Alternate Protocol */
 
#define PCIZ_SFI   0x002c /* System Firmware Intermediary */
 
#define PCIR_BARS   0x10
 
#define PCIR_BAR(x)   (PCIR_BARS + (x) * 4)
 
#define PCIR_MAX_BAR_0   5
 
#define PCI_RID2BAR(rid)   (((rid) - PCIR_BARS) / 4)
 
#define PCI_BAR_IO(x)   (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
 
#define PCI_BAR_MEM(x)   (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
 
#define PCIM_BAR_SPACE   0x00000001
 
#define PCIM_BAR_MEM_SPACE   0
 
#define PCIM_BAR_IO_SPACE   1
 
#define PCIM_BAR_MEM_TYPE   0x00000006
 
#define PCIM_BAR_MEM_32   0
 
#define PCIM_BAR_MEM_1MB   2 /* Locate below 1MB in PCI <= 2.1 */
 
#define PCIM_BAR_MEM_64   4
 
#define PCIM_BAR_MEM_PREFETCH   0x00000008
 
#define PCIM_BAR_MEM_BASE   0xfffffffffffffff0ULL
 
#define PCIM_BAR_IO_RESERVED   0x00000002
 
#define PCIM_BAR_IO_BASE   0xfffffffc
 
#define PCIR_CIS   0x28
 
#define PCIM_CIS_ASI_MASK   0x00000007
 
#define PCIM_CIS_ASI_CONFIG   0
 
#define PCIM_CIS_ASI_BAR0   1
 
#define PCIM_CIS_ASI_BAR1   2
 
#define PCIM_CIS_ASI_BAR2   3
 
#define PCIM_CIS_ASI_BAR3   4
 
#define PCIM_CIS_ASI_BAR4   5
 
#define PCIM_CIS_ASI_BAR5   6
 
#define PCIM_CIS_ASI_ROM   7
 
#define PCIM_CIS_ADDR_MASK   0x0ffffff8
 
#define PCIM_CIS_ROM_MASK   0xf0000000
 
#define PCIM_CIS_CONFIG_MASK   0xff
 
#define PCIR_SUBVEND_0   0x2c
 
#define PCIR_SUBDEV_0   0x2e
 
#define PCIR_BIOS   0x30
 
#define PCIM_BIOS_ENABLE   0x01
 
#define PCIM_BIOS_ADDR_MASK   0xfffff800
 
#define PCIR_CAP_PTR   0x34
 
#define PCIR_INTLINE   0x3c
 
#define PCIR_INTPIN   0x3d
 
#define PCIR_MINGNT   0x3e
 
#define PCIR_MAXLAT   0x3f
 
#define PCIR_MAX_BAR_1   1
 
#define PCIR_SECSTAT_1   0x1e
 
#define PCIR_PRIBUS_1   0x18
 
#define PCIR_SECBUS_1   0x19
 
#define PCIR_SUBBUS_1   0x1a
 
#define PCIR_SECLAT_1   0x1b
 
#define PCIR_IOBASEL_1   0x1c
 
#define PCIR_IOLIMITL_1   0x1d
 
#define PCIR_IOBASEH_1   0x30
 
#define PCIR_IOLIMITH_1   0x32
 
#define PCIM_BRIO_16   0x0
 
#define PCIM_BRIO_32   0x1
 
#define PCIM_BRIO_MASK   0xf
 
#define PCIR_MEMBASE_1   0x20
 
#define PCIR_MEMLIMIT_1   0x22
 
#define PCIR_PMBASEL_1   0x24
 
#define PCIR_PMLIMITL_1   0x26
 
#define PCIR_PMBASEH_1   0x28
 
#define PCIR_PMLIMITH_1   0x2c
 
#define PCIM_BRPM_32   0x0
 
#define PCIM_BRPM_64   0x1
 
#define PCIM_BRPM_MASK   0xf
 
#define PCIR_BIOS_1   0x38
 
#define PCIR_BRIDGECTL_1   0x3e
 
#define PCI_PPBMEMBASE(h, l)   ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
 
#define PCI_PPBMEMLIMIT(h, l)   ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff)
 
#define PCI_PPBIOBASE(h, l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
 
#define PCI_PPBIOLIMIT(h, l)   ((((h)<<16) + ((l)<<8)) | 0xfff)
 
#define PCIR_MAX_BAR_2   0
 
#define PCIR_CAP_PTR_2   0x14
 
#define PCIR_SECSTAT_2   0x16
 
#define PCIR_PRIBUS_2   0x18
 
#define PCIR_SECBUS_2   0x19
 
#define PCIR_SUBBUS_2   0x1a
 
#define PCIR_SECLAT_2   0x1b
 
#define PCIR_MEMBASE0_2   0x1c
 
#define PCIR_MEMLIMIT0_2   0x20
 
#define PCIR_MEMBASE1_2   0x24
 
#define PCIR_MEMLIMIT1_2   0x28
 
#define PCIR_IOBASE0_2   0x2c
 
#define PCIR_IOLIMIT0_2   0x30
 
#define PCIR_IOBASE1_2   0x34
 
#define PCIR_IOLIMIT1_2   0x38
 
#define PCIM_CBBIO_16   0x0
 
#define PCIM_CBBIO_32   0x1
 
#define PCIM_CBBIO_MASK   0x3
 
#define PCIR_BRIDGECTL_2   0x3e
 
#define PCIR_SUBVEND_2   0x40
 
#define PCIR_SUBDEV_2   0x42
 
#define PCIR_PCCARDIF_2   0x44
 
#define PCI_CBBMEMBASE(l)   ((l) & ~0xfffff)
 
#define PCI_CBBMEMLIMIT(l)   ((l) | 0xfffff)
 
#define PCI_CBBIOBASE(l)   ((l) & ~0x3)
 
#define PCI_CBBIOLIMIT(l)   ((l) | 0x3)
 
#define PCIC_OLD   0x00
 
#define PCIS_OLD_NONVGA   0x00
 
#define PCIS_OLD_VGA   0x01
 
#define PCIC_STORAGE   0x01
 
#define PCIS_STORAGE_SCSI   0x00
 
#define PCIS_STORAGE_IDE   0x01
 
#define PCIP_STORAGE_IDE_MODEPRIM   0x01
 
#define PCIP_STORAGE_IDE_PROGINDPRIM   0x02
 
#define PCIP_STORAGE_IDE_MODESEC   0x04
 
#define PCIP_STORAGE_IDE_PROGINDSEC   0x08
 
#define PCIP_STORAGE_IDE_MASTERDEV   0x80
 
#define PCIS_STORAGE_FLOPPY   0x02
 
#define PCIS_STORAGE_IPI   0x03
 
#define PCIS_STORAGE_RAID   0x04
 
#define PCIS_STORAGE_ATA_ADMA   0x05
 
#define PCIS_STORAGE_SATA   0x06
 
#define PCIP_STORAGE_SATA_AHCI_1_0   0x01
 
#define PCIS_STORAGE_SAS   0x07
 
#define PCIS_STORAGE_NVM   0x08
 
#define PCIP_STORAGE_NVM_NVMHCI_1_0   0x01
 
#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0   0x02
 
#define PCIS_STORAGE_UFS   0x09
 
#define PCIP_STORAGE_UFS_UFSHCI_1_0   0x01
 
#define PCIS_STORAGE_OTHER   0x80
 
#define PCIC_NETWORK   0x02
 
#define PCIS_NETWORK_ETHERNET   0x00
 
#define PCIS_NETWORK_TOKENRING   0x01
 
#define PCIS_NETWORK_FDDI   0x02
 
#define PCIS_NETWORK_ATM   0x03
 
#define PCIS_NETWORK_ISDN   0x04
 
#define PCIS_NETWORK_WORLDFIP   0x05
 
#define PCIS_NETWORK_PICMG   0x06
 
#define PCIS_NETWORK_INFINIBAND   0x07
 
#define PCIS_NETWORK_HFC   0x08
 
#define PCIS_NETWORK_OTHER   0x80
 
#define PCIC_DISPLAY   0x03
 
#define PCIS_DISPLAY_VGA   0x00
 
#define PCIS_DISPLAY_XGA   0x01
 
#define PCIS_DISPLAY_3D   0x02
 
#define PCIS_DISPLAY_OTHER   0x80
 
#define PCIC_MULTIMEDIA   0x04
 
#define PCIS_MULTIMEDIA_VIDEO   0x00
 
#define PCIS_MULTIMEDIA_AUDIO   0x01
 
#define PCIS_MULTIMEDIA_TELE   0x02
 
#define PCIS_MULTIMEDIA_HDA   0x03
 
#define PCIP_MULTIMEDIA_HDA_VENDOR   0x01
 
#define PCIS_MULTIMEDIA_OTHER   0x80
 
#define PCIC_MEMORY   0x05
 
#define PCIS_MEMORY_RAM   0x00
 
#define PCIS_MEMORY_FLASH   0x01
 
#define PCIS_MEMORY_OTHER   0x80
 
#define PCIC_BRIDGE   0x06
 
#define PCIS_BRIDGE_HOST   0x00
 
#define PCIS_BRIDGE_ISA   0x01
 
#define PCIS_BRIDGE_EISA   0x02
 
#define PCIS_BRIDGE_MCA   0x03
 
#define PCIS_BRIDGE_PCI   0x04
 
#define PCIP_BRIDGE_PCI_SUBTRACTIVE   0x01
 
#define PCIS_BRIDGE_PCMCIA   0x05
 
#define PCIS_BRIDGE_NUBUS   0x06
 
#define PCIS_BRIDGE_CARDBUS   0x07
 
#define PCIS_BRIDGE_RACEWAY   0x08
 
#define PCIS_BRIDGE_PCI_TRANSPARENT   0x09
 
#define PCIS_BRIDGE_INFINIBAND   0x0a
 
#define PCIS_BRIDGE_AS_PCI   0x0b
 
#define PCIS_BRIDGE_AS_PCI_ASI_SIG   0x01
 
#define PCIS_BRIDGE_OTHER   0x80
 
#define PCIC_SIMPLECOMM   0x07
 
#define PCIS_SIMPLECOMM_UART   0x00
 
#define PCIP_SIMPLECOMM_UART_8250   0x00
 
#define PCIP_SIMPLECOMM_UART_16450A   0x01
 
#define PCIP_SIMPLECOMM_UART_16550A   0x02
 
#define PCIP_SIMPLECOMM_UART_16650A   0x03
 
#define PCIP_SIMPLECOMM_UART_16750A   0x04
 
#define PCIP_SIMPLECOMM_UART_16850A   0x05
 
#define PCIP_SIMPLECOMM_UART_16950A   0x06
 
#define PCIS_SIMPLECOMM_PAR   0x01
 
#define PCIS_SIMPLECOMM_MULSER   0x02
 
#define PCIS_SIMPLECOMM_MODEM   0x03
 
#define PCIS_SIMPLECOMM_GPIB   0x04
 
#define PCIS_SIMPLECOMM_SMART_CARD   0x05
 
#define PCIS_SIMPLECOMM_OTHER   0x80
 
#define PCIC_BASEPERIPH   0x08
 
#define PCIS_BASEPERIPH_PIC   0x00
 
#define PCIP_BASEPERIPH_PIC_8259A   0x00
 
#define PCIP_BASEPERIPH_PIC_ISA   0x01
 
#define PCIP_BASEPERIPH_PIC_EISA   0x02
 
#define PCIP_BASEPERIPH_PIC_IO_APIC   0x10
 
#define PCIP_BASEPERIPH_PIC_IOX_APIC   0x20
 
#define PCIS_BASEPERIPH_DMA   0x01
 
#define PCIS_BASEPERIPH_TIMER   0x02
 
#define PCIS_BASEPERIPH_RTC   0x03
 
#define PCIS_BASEPERIPH_PCIHOT   0x04
 
#define PCIS_BASEPERIPH_SDHC   0x05
 
#define PCIS_BASEPERIPH_IOMMU   0x06
 
#define PCIS_BASEPERIPH_RCEC   0x07
 
#define PCIS_BASEPERIPH_OTHER   0x80
 
#define PCIC_INPUTDEV   0x09
 
#define PCIS_INPUTDEV_KEYBOARD   0x00
 
#define PCIS_INPUTDEV_DIGITIZER   0x01
 
#define PCIS_INPUTDEV_MOUSE   0x02
 
#define PCIS_INPUTDEV_SCANNER   0x03
 
#define PCIS_INPUTDEV_GAMEPORT   0x04
 
#define PCIS_INPUTDEV_OTHER   0x80
 
#define PCIC_DOCKING   0x0a
 
#define PCIS_DOCKING_GENERIC   0x00
 
#define PCIS_DOCKING_OTHER   0x80
 
#define PCIC_PROCESSOR   0x0b
 
#define PCIS_PROCESSOR_386   0x00
 
#define PCIS_PROCESSOR_486   0x01
 
#define PCIS_PROCESSOR_PENTIUM   0x02
 
#define PCIS_PROCESSOR_ALPHA   0x10
 
#define PCIS_PROCESSOR_POWERPC   0x20
 
#define PCIS_PROCESSOR_MIPS   0x30
 
#define PCIS_PROCESSOR_COPROC   0x40
 
#define PCIC_SERIALBUS   0x0c
 
#define PCIS_SERIALBUS_FW   0x00
 
#define PCIS_SERIALBUS_ACCESS   0x01
 
#define PCIS_SERIALBUS_SSA   0x02
 
#define PCIS_SERIALBUS_USB   0x03
 
#define PCIP_SERIALBUS_USB_UHCI   0x00
 
#define PCIP_SERIALBUS_USB_OHCI   0x10
 
#define PCIP_SERIALBUS_USB_EHCI   0x20
 
#define PCIP_SERIALBUS_USB_XHCI   0x30
 
#define PCIP_SERIALBUS_USB_DEVICE   0xfe
 
#define PCIS_SERIALBUS_FC   0x04
 
#define PCIS_SERIALBUS_SMBUS   0x05
 
#define PCIS_SERIALBUS_INFINIBAND   0x06
 
#define PCIS_SERIALBUS_IPMI   0x07
 
#define PCIP_SERIALBUS_IPMI_SMIC   0x00
 
#define PCIP_SERIALBUS_IPMI_KCS   0x01
 
#define PCIP_SERIALBUS_IPMI_BT   0x02
 
#define PCIS_SERIALBUS_SERCOS   0x08
 
#define PCIS_SERIALBUS_CANBUS   0x09
 
#define PCIS_SERIALBUS_MIPI_I3C   0x0a
 
#define PCIC_WIRELESS   0x0d
 
#define PCIS_WIRELESS_IRDA   0x00
 
#define PCIS_WIRELESS_IR   0x01
 
#define PCIS_WIRELESS_RF   0x10
 
#define PCIS_WIRELESS_BLUETOOTH   0x11
 
#define PCIS_WIRELESS_BROADBAND   0x12
 
#define PCIS_WIRELESS_80211A   0x20
 
#define PCIS_WIRELESS_80211B   0x21
 
#define PCIS_WIRELESS_CELL   0x40
 
#define PCIS_WIRELESS_CELL_E   0x41
 
#define PCIS_WIRELESS_OTHER   0x80
 
#define PCIC_INTELLIIO   0x0e
 
#define PCIS_INTELLIIO_I2O   0x00
 
#define PCIC_SATCOM   0x0f
 
#define PCIS_SATCOM_TV   0x01
 
#define PCIS_SATCOM_AUDIO   0x02
 
#define PCIS_SATCOM_VOICE   0x03
 
#define PCIS_SATCOM_DATA   0x04
 
#define PCIC_CRYPTO   0x10
 
#define PCIS_CRYPTO_NETCOMP   0x00
 
#define PCIS_CRYPTO_ENTERTAIN   0x10
 
#define PCIS_CRYPTO_OTHER   0x80
 
#define PCIC_DASP   0x11
 
#define PCIS_DASP_DPIO   0x00
 
#define PCIS_DASP_PERFCNTRS   0x01
 
#define PCIS_DASP_COMM_SYNC   0x10
 
#define PCIS_DASP_MGMT_CARD   0x20
 
#define PCIS_DASP_OTHER   0x80
 
#define PCIC_ACCEL   0x12
 
#define PCIS_ACCEL_PROCESSING   0x00
 
#define PCIC_INSTRUMENT   0x13
 
#define PCIC_OTHER   0xff
 
#define PCIB_BCR_PERR_ENABLE   0x0001
 
#define PCIB_BCR_SERR_ENABLE   0x0002
 
#define PCIB_BCR_ISA_ENABLE   0x0004
 
#define PCIB_BCR_VGA_ENABLE   0x0008
 
#define PCIB_BCR_MASTER_ABORT_MODE   0x0020
 
#define PCIB_BCR_SECBUS_RESET   0x0040
 
#define PCIB_BCR_SECBUS_BACKTOBACK   0x0080
 
#define PCIB_BCR_PRI_DISCARD_TIMEOUT   0x0100
 
#define PCIB_BCR_SEC_DISCARD_TIMEOUT   0x0200
 
#define PCIB_BCR_DISCARD_TIMER_STATUS   0x0400
 
#define PCIB_BCR_DISCARD_TIMER_SERREN   0x0800
 
#define CBB_BCR_PERR_ENABLE   0x0001
 
#define CBB_BCR_SERR_ENABLE   0x0002
 
#define CBB_BCR_ISA_ENABLE   0x0004
 
#define CBB_BCR_VGA_ENABLE   0x0008
 
#define CBB_BCR_MASTER_ABORT_MODE   0x0020
 
#define CBB_BCR_CARDBUS_RESET   0x0040
 
#define CBB_BCR_IREQ_INT_ENABLE   0x0080
 
#define CBB_BCR_PREFETCH_0_ENABLE   0x0100
 
#define CBB_BCR_PREFETCH_1_ENABLE   0x0200
 
#define CBB_BCR_WRITE_POSTING_ENABLE   0x0400
 
#define PCIR_POWER_CAP   0x2
 
#define PCIM_PCAP_SPEC   0x0007
 
#define PCIM_PCAP_PMEREQCLK   0x0008
 
#define PCIM_PCAP_DEVSPECINIT   0x0020
 
#define PCIM_PCAP_AUXPWR_0   0x0000
 
#define PCIM_PCAP_AUXPWR_55   0x0040
 
#define PCIM_PCAP_AUXPWR_100   0x0080
 
#define PCIM_PCAP_AUXPWR_160   0x00c0
 
#define PCIM_PCAP_AUXPWR_220   0x0100
 
#define PCIM_PCAP_AUXPWR_270   0x0140
 
#define PCIM_PCAP_AUXPWR_320   0x0180
 
#define PCIM_PCAP_AUXPWR_375   0x01c0
 
#define PCIM_PCAP_AUXPWRMASK   0x01c0
 
#define PCIM_PCAP_D1SUPP   0x0200
 
#define PCIM_PCAP_D2SUPP   0x0400
 
#define PCIM_PCAP_D0PME   0x0800
 
#define PCIM_PCAP_D1PME   0x1000
 
#define PCIM_PCAP_D2PME   0x2000
 
#define PCIM_PCAP_D3PME_HOT   0x4000
 
#define PCIM_PCAP_D3PME_COLD   0x8000
 
#define PCIR_POWER_STATUS   0x4
 
#define PCIM_PSTAT_D0   0x0000
 
#define PCIM_PSTAT_D1   0x0001
 
#define PCIM_PSTAT_D2   0x0002
 
#define PCIM_PSTAT_D3   0x0003
 
#define PCIM_PSTAT_DMASK   0x0003
 
#define PCIM_PSTAT_NOSOFTRESET   0x0008
 
#define PCIM_PSTAT_PMEENABLE   0x0100
 
#define PCIM_PSTAT_D0POWER   0x0000
 
#define PCIM_PSTAT_D1POWER   0x0200
 
#define PCIM_PSTAT_D2POWER   0x0400
 
#define PCIM_PSTAT_D3POWER   0x0600
 
#define PCIM_PSTAT_D0HEAT   0x0800
 
#define PCIM_PSTAT_D1HEAT   0x0a00
 
#define PCIM_PSTAT_D2HEAT   0x0c00
 
#define PCIM_PSTAT_D3HEAT   0x0e00
 
#define PCIM_PSTAT_DATASELMASK   0x1e00
 
#define PCIM_PSTAT_DATAUNKN   0x0000
 
#define PCIM_PSTAT_DATADIV10   0x2000
 
#define PCIM_PSTAT_DATADIV100   0x4000
 
#define PCIM_PSTAT_DATADIV1000   0x6000
 
#define PCIM_PSTAT_DATADIVMASK   0x6000
 
#define PCIM_PSTAT_PME   0x8000
 
#define PCIR_POWER_BSE   0x6
 
#define PCIM_PMCSR_BSE_D3B3   0x00
 
#define PCIM_PMCSR_BSE_D3B2   0x40
 
#define PCIM_PMCSR_BSE_BPCCE   0x80
 
#define PCIR_POWER_DATA   0x7
 
#define PCIR_VPD_ADDR   0x2
 
#define PCIR_VPD_DATA   0x4
 
#define PCIR_MSI_CTRL   0x2
 
#define PCIM_MSICTRL_VECTOR   0x0100
 
#define PCIM_MSICTRL_64BIT   0x0080
 
#define PCIM_MSICTRL_MME_MASK   0x0070
 
#define PCIM_MSICTRL_MME_1   0x0000
 
#define PCIM_MSICTRL_MME_2   0x0010
 
#define PCIM_MSICTRL_MME_4   0x0020
 
#define PCIM_MSICTRL_MME_8   0x0030
 
#define PCIM_MSICTRL_MME_16   0x0040
 
#define PCIM_MSICTRL_MME_32   0x0050
 
#define PCIM_MSICTRL_MMC_MASK   0x000E
 
#define PCIM_MSICTRL_MMC_1   0x0000
 
#define PCIM_MSICTRL_MMC_2   0x0002
 
#define PCIM_MSICTRL_MMC_4   0x0004
 
#define PCIM_MSICTRL_MMC_8   0x0006
 
#define PCIM_MSICTRL_MMC_16   0x0008
 
#define PCIM_MSICTRL_MMC_32   0x000A
 
#define PCIM_MSICTRL_MSI_ENABLE   0x0001
 
#define PCIR_MSI_ADDR   0x4
 
#define PCIR_MSI_ADDR_HIGH   0x8
 
#define PCIR_MSI_DATA   0x8
 
#define PCIR_MSI_DATA_64BIT   0xc
 
#define PCIR_MSI_MASK   0x10
 
#define PCIR_MSI_PENDING   0x14
 
#define PCIR_EA_NUM_ENT   2 /* Number of Capability Entries */
 
#define PCIM_EA_NUM_ENT_MASK   0x3f /* Num Entries Mask */
 
#define PCIR_EA_FIRST_ENT   4 /* First EA Entry in List */
 
#define PCIR_EA_FIRST_ENT_BRIDGE   8 /* First EA Entry for Bridges */
 
#define PCIM_EA_ES   0x00000007 /* Entry Size */
 
#define PCIM_EA_BEI   0x000000f0 /* BAR Equivalent Indicator */
 
#define PCIM_EA_BEI_OFFSET   4
 
#define PCIM_EA_BEI_BAR_0   0
 
#define PCIM_EA_BEI_BAR_5   5
 
#define PCIM_EA_BEI_BAR(x)   (((x) >> PCIM_EA_BEI_OFFSET) & 0xf)
 
#define PCIM_EA_BEI_BRIDGE   0x6 /* Resource behind bridge */
 
#define PCIM_EA_BEI_ENI   0x7 /* Equivalent Not Indicated */
 
#define PCIM_EA_BEI_ROM   0x8 /* Expansion ROM */
 
#define PCIM_EA_BEI_VF_BAR_0   9
 
#define PCIM_EA_BEI_VF_BAR_5   14
 
#define PCIM_EA_BEI_RESERVED   0xf /* Reserved - Treat like ENI */
 
#define PCIM_EA_PP   0x0000ff00 /* Primary Properties */
 
#define PCIM_EA_PP_OFFSET   8
 
#define PCIM_EA_SP_OFFSET   16
 
#define PCIM_EA_SP   0x00ff0000 /* Secondary Properties */
 
#define PCIM_EA_P_MEM   0x00 /* Non-Prefetch Memory */
 
#define PCIM_EA_P_MEM_PREFETCH   0x01 /* Prefetchable Memory */
 
#define PCIM_EA_P_IO   0x02 /* I/O Space */
 
#define PCIM_EA_P_VF_MEM_PREFETCH   0x03 /* VF Prefetchable Memory */
 
#define PCIM_EA_P_VF_MEM   0x04 /* VF Non-Prefetch Memory */
 
#define PCIM_EA_P_BRIDGE_MEM   0x05 /* Bridge Non-Prefetch Memory */
 
#define PCIM_EA_P_BRIDGE_MEM_PREFETCH   0x06 /* Bridge Prefetchable Memory */
 
#define PCIM_EA_P_BRIDGE_IO   0x07 /* Bridge I/O Space */
 
#define PCIM_EA_P_MEM_RESERVED   0xfd /* Reserved Memory */
 
#define PCIM_EA_P_IO_RESERVED   0xfe /* Reserved I/O Space */
 
#define PCIM_EA_P_UNAVAILABLE   0xff /* Entry Unavailable */
 
#define PCIM_EA_WRITABLE   0x40000000 /* Writable: 1 = RW, 0 = HwInit */
 
#define PCIM_EA_ENABLE   0x80000000 /* Enable for this entry */
 
#define PCIM_EA_BASE   4 /* Base Address Offset */
 
#define PCIM_EA_MAX_OFFSET   8 /* MaxOffset (resource length) */
 
#define PCIM_EA_IS_64   0x00000002 /* 64-bit field flag */
 
#define PCIM_EA_FIELD_MASK   0xfffffffc /* For Base & Max Offset */
 
#define PCIM_EA_SEC_NR(reg)   ((reg) & 0xff)
 
#define PCIM_EA_SUB_NR(reg)   (((reg) >> 8) & 0xff)
 
#define PCIXR_COMMAND   0x2
 
#define PCIXM_COMMAND_DPERR_E   0x0001 /* Data Parity Error Recovery */
 
#define PCIXM_COMMAND_ERO   0x0002 /* Enable Relaxed Ordering */
 
#define PCIXM_COMMAND_MAX_READ   0x000c /* Maximum Burst Read Count */
 
#define PCIXM_COMMAND_MAX_READ_512   0x0000
 
#define PCIXM_COMMAND_MAX_READ_1024   0x0004
 
#define PCIXM_COMMAND_MAX_READ_2048   0x0008
 
#define PCIXM_COMMAND_MAX_READ_4096   0x000c
 
#define PCIXM_COMMAND_MAX_SPLITS   0x0070 /* Maximum Split Transactions */
 
#define PCIXM_COMMAND_MAX_SPLITS_1   0x0000
 
#define PCIXM_COMMAND_MAX_SPLITS_2   0x0010
 
#define PCIXM_COMMAND_MAX_SPLITS_3   0x0020
 
#define PCIXM_COMMAND_MAX_SPLITS_4   0x0030
 
#define PCIXM_COMMAND_MAX_SPLITS_8   0x0040
 
#define PCIXM_COMMAND_MAX_SPLITS_12   0x0050
 
#define PCIXM_COMMAND_MAX_SPLITS_16   0x0060
 
#define PCIXM_COMMAND_MAX_SPLITS_32   0x0070
 
#define PCIXM_COMMAND_VERSION   0x3000
 
#define PCIXR_STATUS   0x4
 
#define PCIXM_STATUS_DEVFN   0x000000FF
 
#define PCIXM_STATUS_BUS   0x0000FF00
 
#define PCIXM_STATUS_64BIT   0x00010000
 
#define PCIXM_STATUS_133CAP   0x00020000
 
#define PCIXM_STATUS_SC_DISCARDED   0x00040000
 
#define PCIXM_STATUS_UNEXP_SC   0x00080000
 
#define PCIXM_STATUS_COMPLEX_DEV   0x00100000
 
#define PCIXM_STATUS_MAX_READ   0x00600000
 
#define PCIXM_STATUS_MAX_READ_512   0x00000000
 
#define PCIXM_STATUS_MAX_READ_1024   0x00200000
 
#define PCIXM_STATUS_MAX_READ_2048   0x00400000
 
#define PCIXM_STATUS_MAX_READ_4096   0x00600000
 
#define PCIXM_STATUS_MAX_SPLITS   0x03800000
 
#define PCIXM_STATUS_MAX_SPLITS_1   0x00000000
 
#define PCIXM_STATUS_MAX_SPLITS_2   0x00800000
 
#define PCIXM_STATUS_MAX_SPLITS_3   0x01000000
 
#define PCIXM_STATUS_MAX_SPLITS_4   0x01800000
 
#define PCIXM_STATUS_MAX_SPLITS_8   0x02000000
 
#define PCIXM_STATUS_MAX_SPLITS_12   0x02800000
 
#define PCIXM_STATUS_MAX_SPLITS_16   0x03000000
 
#define PCIXM_STATUS_MAX_SPLITS_32   0x03800000
 
#define PCIXM_STATUS_MAX_CUM_READ   0x1C000000
 
#define PCIXM_STATUS_RCVD_SC_ERR   0x20000000
 
#define PCIXM_STATUS_266CAP   0x40000000
 
#define PCIXM_STATUS_533CAP   0x80000000
 
#define PCIXR_SEC_STATUS   0x2
 
#define PCIXM_SEC_STATUS_64BIT   0x0001
 
#define PCIXM_SEC_STATUS_133CAP   0x0002
 
#define PCIXM_SEC_STATUS_SC_DISC   0x0004
 
#define PCIXM_SEC_STATUS_UNEXP_SC   0x0008
 
#define PCIXM_SEC_STATUS_SC_OVERRUN   0x0010
 
#define PCIXM_SEC_STATUS_SR_DELAYED   0x0020
 
#define PCIXM_SEC_STATUS_BUS_MODE   0x03c0
 
#define PCIXM_SEC_STATUS_VERSION   0x3000
 
#define PCIXM_SEC_STATUS_266CAP   0x4000
 
#define PCIXM_SEC_STATUS_533CAP   0x8000
 
#define PCIXR_BRIDGE_STATUS   0x4
 
#define PCIXM_BRIDGE_STATUS_DEVFN   0x000000FF
 
#define PCIXM_BRIDGE_STATUS_BUS   0x0000FF00
 
#define PCIXM_BRIDGE_STATUS_64BIT   0x00010000
 
#define PCIXM_BRIDGE_STATUS_133CAP   0x00020000
 
#define PCIXM_BRIDGE_STATUS_SC_DISCARDED   0x00040000
 
#define PCIXM_BRIDGE_STATUS_UNEXP_SC   0x00080000
 
#define PCIXM_BRIDGE_STATUS_SC_OVERRUN   0x00100000
 
#define PCIXM_BRIDGE_STATUS_SR_DELAYED   0x00200000
 
#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP   0x20000000
 
#define PCIXM_BRIDGE_STATUS_266CAP   0x40000000
 
#define PCIXM_BRIDGE_STATUS_533CAP   0x80000000
 
#define PCIR_HT_COMMAND   0x2
 
#define PCIM_HTCMD_CAP_MASK   0xf800 /* Capability type. */
 
#define PCIM_HTCAP_SLAVE   0x0000 /* 000xx */
 
#define PCIM_HTCAP_HOST   0x2000 /* 001xx */
 
#define PCIM_HTCAP_SWITCH   0x4000 /* 01000 */
 
#define PCIM_HTCAP_INTERRUPT   0x8000 /* 10000 */
 
#define PCIM_HTCAP_REVISION_ID   0x8800 /* 10001 */
 
#define PCIM_HTCAP_UNITID_CLUMPING   0x9000 /* 10010 */
 
#define PCIM_HTCAP_EXT_CONFIG_SPACE   0x9800 /* 10011 */
 
#define PCIM_HTCAP_ADDRESS_MAPPING   0xa000 /* 10100 */
 
#define PCIM_HTCAP_MSI_MAPPING   0xa800 /* 10101 */
 
#define PCIM_HTCAP_DIRECT_ROUTE   0xb000 /* 10110 */
 
#define PCIM_HTCAP_VCSET   0xb800 /* 10111 */
 
#define PCIM_HTCAP_RETRY_MODE   0xc000 /* 11000 */
 
#define PCIM_HTCAP_X86_ENCODING   0xc800 /* 11001 */
 
#define PCIM_HTCAP_GEN3   0xd000 /* 11010 */
 
#define PCIM_HTCAP_FLE   0xd800 /* 11011 */
 
#define PCIM_HTCAP_PM   0xe000 /* 11100 */
 
#define PCIM_HTCAP_HIGH_NODE_COUNT   0xe800 /* 11101 */
 
#define PCIM_HTCMD_MSI_ENABLE   0x0001
 
#define PCIM_HTCMD_MSI_FIXED   0x0002
 
#define PCIR_HTMSI_ADDRESS_LO   0x4
 
#define PCIR_HTMSI_ADDRESS_HI   0x8
 
#define PCIR_VENDOR_LENGTH   0x2
 
#define PCIR_VENDOR_DATA   0x3
 
#define PCIR_DEVICE_LENGTH   0x2
 
#define PCIR_DEBUG_PORT   0x2
 
#define PCIM_DEBUG_PORT_OFFSET   0x1FFF
 
#define PCIM_DEBUG_PORT_BAR   0xe000
 
#define PCIR_SUBVENDCAP_ID   0x4
 
#define PCIER_FLAGS   0x2
 
#define PCIEM_FLAGS_VERSION   0x000F
 
#define PCIEM_FLAGS_TYPE   0x00F0
 
#define PCIEM_TYPE_ENDPOINT   0x0000
 
#define PCIEM_TYPE_LEGACY_ENDPOINT   0x0010
 
#define PCIEM_TYPE_ROOT_PORT   0x0040
 
#define PCIEM_TYPE_UPSTREAM_PORT   0x0050
 
#define PCIEM_TYPE_DOWNSTREAM_PORT   0x0060
 
#define PCIEM_TYPE_PCI_BRIDGE   0x0070
 
#define PCIEM_TYPE_PCIE_BRIDGE   0x0080
 
#define PCIEM_TYPE_ROOT_INT_EP   0x0090
 
#define PCIEM_TYPE_ROOT_EC   0x00a0
 
#define PCIEM_FLAGS_SLOT   0x0100
 
#define PCIEM_FLAGS_IRQ   0x3e00
 
#define PCIER_DEVICE_CAP   0x4
 
#define PCIEM_CAP_MAX_PAYLOAD   0x00000007
 
#define PCIEM_CAP_PHANTHOM_FUNCS   0x00000018
 
#define PCIEM_CAP_EXT_TAG_FIELD   0x00000020
 
#define PCIEM_CAP_L0S_LATENCY   0x000001c0
 
#define PCIEM_CAP_L1_LATENCY   0x00000e00
 
#define PCIEM_CAP_ROLE_ERR_RPT   0x00008000
 
#define PCIEM_CAP_SLOT_PWR_LIM_VAL   0x03fc0000
 
#define PCIEM_CAP_SLOT_PWR_LIM_SCALE   0x0c000000
 
#define PCIEM_CAP_FLR   0x10000000
 
#define PCIER_DEVICE_CTL   0x8
 
#define PCIEM_CTL_COR_ENABLE   0x0001
 
#define PCIEM_CTL_NFER_ENABLE   0x0002
 
#define PCIEM_CTL_FER_ENABLE   0x0004
 
#define PCIEM_CTL_URR_ENABLE   0x0008
 
#define PCIEM_CTL_RELAXED_ORD_ENABLE   0x0010
 
#define PCIEM_CTL_MAX_PAYLOAD   0x00e0
 
#define PCIEM_CTL_EXT_TAG_FIELD   0x0100
 
#define PCIEM_CTL_PHANTHOM_FUNCS   0x0200
 
#define PCIEM_CTL_AUX_POWER_PM   0x0400
 
#define PCIEM_CTL_NOSNOOP_ENABLE   0x0800
 
#define PCIEM_CTL_MAX_READ_REQUEST   0x7000
 
#define PCIEM_CTL_BRDG_CFG_RETRY   0x8000 /* PCI-E - PCI/PCI-X bridges */
 
#define PCIEM_CTL_INITIATE_FLR   0x8000 /* FLR capable endpoints */
 
#define PCIER_DEVICE_STA   0xa
 
#define PCIEM_STA_CORRECTABLE_ERROR   0x0001
 
#define PCIEM_STA_NON_FATAL_ERROR   0x0002
 
#define PCIEM_STA_FATAL_ERROR   0x0004
 
#define PCIEM_STA_UNSUPPORTED_REQ   0x0008
 
#define PCIEM_STA_AUX_POWER   0x0010
 
#define PCIEM_STA_TRANSACTION_PND   0x0020
 
#define PCIER_LINK_CAP   0xc
 
#define PCIEM_LINK_CAP_MAX_SPEED   0x0000000f
 
#define PCIEM_LINK_CAP_MAX_WIDTH   0x000003f0
 
#define PCIEM_LINK_CAP_ASPM   0x00000c00
 
#define PCIEM_LINK_CAP_L0S_EXIT   0x00007000
 
#define PCIEM_LINK_CAP_L1_EXIT   0x00038000
 
#define PCIEM_LINK_CAP_CLOCK_PM   0x00040000
 
#define PCIEM_LINK_CAP_SURPRISE_DOWN   0x00080000
 
#define PCIEM_LINK_CAP_DL_ACTIVE   0x00100000
 
#define PCIEM_LINK_CAP_LINK_BW_NOTIFY   0x00200000
 
#define PCIEM_LINK_CAP_ASPM_COMPLIANCE   0x00400000
 
#define PCIEM_LINK_CAP_PORT   0xff000000
 
#define PCIER_LINK_CTL   0x10
 
#define PCIEM_LINK_CTL_ASPMC_DIS   0x0000
 
#define PCIEM_LINK_CTL_ASPMC_L0S   0x0001
 
#define PCIEM_LINK_CTL_ASPMC_L1   0x0002
 
#define PCIEM_LINK_CTL_ASPMC   0x0003
 
#define PCIEM_LINK_CTL_RCB   0x0008
 
#define PCIEM_LINK_CTL_LINK_DIS   0x0010
 
#define PCIEM_LINK_CTL_RETRAIN_LINK   0x0020
 
#define PCIEM_LINK_CTL_COMMON_CLOCK   0x0040
 
#define PCIEM_LINK_CTL_EXTENDED_SYNC   0x0080
 
#define PCIEM_LINK_CTL_ECPM   0x0100
 
#define PCIEM_LINK_CTL_HAWD   0x0200
 
#define PCIEM_LINK_CTL_LBMIE   0x0400
 
#define PCIEM_LINK_CTL_LABIE   0x0800
 
#define PCIER_LINK_STA   0x12
 
#define PCIEM_LINK_STA_SPEED   0x000f
 
#define PCIEM_LINK_STA_WIDTH   0x03f0
 
#define PCIEM_LINK_STA_TRAINING_ERROR   0x0400
 
#define PCIEM_LINK_STA_TRAINING   0x0800
 
#define PCIEM_LINK_STA_SLOT_CLOCK   0x1000
 
#define PCIEM_LINK_STA_DL_ACTIVE   0x2000
 
#define PCIEM_LINK_STA_LINK_BW_MGMT   0x4000
 
#define PCIEM_LINK_STA_LINK_AUTO_BW   0x8000
 
#define PCIER_SLOT_CAP   0x14
 
#define PCIEM_SLOT_CAP_APB   0x00000001
 
#define PCIEM_SLOT_CAP_PCP   0x00000002
 
#define PCIEM_SLOT_CAP_MRLSP   0x00000004
 
#define PCIEM_SLOT_CAP_AIP   0x00000008
 
#define PCIEM_SLOT_CAP_PIP   0x00000010
 
#define PCIEM_SLOT_CAP_HPS   0x00000020
 
#define PCIEM_SLOT_CAP_HPC   0x00000040
 
#define PCIEM_SLOT_CAP_SPLV   0x00007f80
 
#define PCIEM_SLOT_CAP_SPLS   0x00018000
 
#define PCIEM_SLOT_CAP_EIP   0x00020000
 
#define PCIEM_SLOT_CAP_NCCS   0x00040000
 
#define PCIEM_SLOT_CAP_PSN   0xfff80000
 
#define PCIER_SLOT_CTL   0x18
 
#define PCIEM_SLOT_CTL_ABPE   0x0001
 
#define PCIEM_SLOT_CTL_PFDE   0x0002
 
#define PCIEM_SLOT_CTL_MRLSCE   0x0004
 
#define PCIEM_SLOT_CTL_PDCE   0x0008
 
#define PCIEM_SLOT_CTL_CCIE   0x0010
 
#define PCIEM_SLOT_CTL_HPIE   0x0020
 
#define PCIEM_SLOT_CTL_AIC   0x00c0
 
#define PCIEM_SLOT_CTL_AI_ON   0x0040
 
#define PCIEM_SLOT_CTL_AI_BLINK   0x0080
 
#define PCIEM_SLOT_CTL_AI_OFF   0x00c0
 
#define PCIEM_SLOT_CTL_PIC   0x0300
 
#define PCIEM_SLOT_CTL_PI_ON   0x0100
 
#define PCIEM_SLOT_CTL_PI_BLINK   0x0200
 
#define PCIEM_SLOT_CTL_PI_OFF   0x0300
 
#define PCIEM_SLOT_CTL_PCC   0x0400
 
#define PCIEM_SLOT_CTL_PC_ON   0x0000
 
#define PCIEM_SLOT_CTL_PC_OFF   0x0400
 
#define PCIEM_SLOT_CTL_EIC   0x0800
 
#define PCIEM_SLOT_CTL_DLLSCE   0x1000
 
#define PCIER_SLOT_STA   0x1a
 
#define PCIEM_SLOT_STA_ABP   0x0001
 
#define PCIEM_SLOT_STA_PFD   0x0002
 
#define PCIEM_SLOT_STA_MRLSC   0x0004
 
#define PCIEM_SLOT_STA_PDC   0x0008
 
#define PCIEM_SLOT_STA_CC   0x0010
 
#define PCIEM_SLOT_STA_MRLSS   0x0020
 
#define PCIEM_SLOT_STA_PDS   0x0040
 
#define PCIEM_SLOT_STA_EIS   0x0080
 
#define PCIEM_SLOT_STA_DLLSC   0x0100
 
#define PCIER_ROOT_CTL   0x1c
 
#define PCIEM_ROOT_CTL_SERR_CORR   0x0001
 
#define PCIEM_ROOT_CTL_SERR_NONFATAL   0x0002
 
#define PCIEM_ROOT_CTL_SERR_FATAL   0x0004
 
#define PCIEM_ROOT_CTL_PME   0x0008
 
#define PCIEM_ROOT_CTL_CRS_VIS   0x0010
 
#define PCIER_ROOT_CAP   0x1e
 
#define PCIEM_ROOT_CAP_CRS_VIS   0x0001
 
#define PCIER_ROOT_STA   0x20
 
#define PCIEM_ROOT_STA_PME_REQID_MASK   0x0000ffff
 
#define PCIEM_ROOT_STA_PME_STATUS   0x00010000
 
#define PCIEM_ROOT_STA_PME_PEND   0x00020000
 
#define PCIER_DEVICE_CAP2   0x24
 
#define PCIEM_CAP2_COMP_TIMO_RANGES   0x0000000f
 
#define PCIEM_CAP2_COMP_TIMO_RANGE_A   0x00000001
 
#define PCIEM_CAP2_COMP_TIMO_RANGE_B   0x00000002
 
#define PCIEM_CAP2_COMP_TIMO_RANGE_C   0x00000004
 
#define PCIEM_CAP2_COMP_TIMO_RANGE_D   0x00000008
 
#define PCIEM_CAP2_COMP_TIMO_DISABLE   0x00000010
 
#define PCIEM_CAP2_ARI   0x00000020
 
#define PCIER_DEVICE_CTL2   0x28
 
#define PCIEM_CTL2_COMP_TIMO_VAL   0x000f
 
#define PCIEM_CTL2_COMP_TIMO_50MS   0x0000
 
#define PCIEM_CTL2_COMP_TIMO_100US   0x0001
 
#define PCIEM_CTL2_COMP_TIMO_10MS   0x0002
 
#define PCIEM_CTL2_COMP_TIMO_55MS   0x0005
 
#define PCIEM_CTL2_COMP_TIMO_210MS   0x0006
 
#define PCIEM_CTL2_COMP_TIMO_900MS   0x0009
 
#define PCIEM_CTL2_COMP_TIMO_3500MS   0x000a
 
#define PCIEM_CTL2_COMP_TIMO_13S   0x000d
 
#define PCIEM_CTL2_COMP_TIMO_64S   0x000e
 
#define PCIEM_CTL2_COMP_TIMO_DISABLE   0x0010
 
#define PCIEM_CTL2_ARI   0x0020
 
#define PCIEM_CTL2_ATOMIC_REQ_ENABLE   0x0040
 
#define PCIEM_CTL2_ATOMIC_EGR_BLOCK   0x0080
 
#define PCIEM_CTL2_ID_ORDERED_REQ_EN   0x0100
 
#define PCIEM_CTL2_ID_ORDERED_CMP_EN   0x0200
 
#define PCIEM_CTL2_LTR_ENABLE   0x0400
 
#define PCIEM_CTL2_OBFF   0x6000
 
#define PCIEM_OBFF_DISABLE   0x0000
 
#define PCIEM_OBFF_MSGA_ENABLE   0x2000
 
#define PCIEM_OBFF_MSGB_ENABLE   0x4000
 
#define PCIEM_OBFF_WAKE_ENABLE   0x6000
 
#define PCIEM_CTL2_END2END_TLP   0x8000
 
#define PCIER_DEVICE_STA2   0x2a
 
#define PCIER_LINK_CAP2   0x2c
 
#define PCIER_LINK_CTL2   0x30
 
#define PCIER_LINK_STA2   0x32
 
#define PCIER_SLOT_CAP2   0x34
 
#define PCIER_SLOT_CTL2   0x38
 
#define PCIER_SLOT_STA2   0x3a
 
#define PCIR_MSIX_CTRL   0x2
 
#define PCIM_MSIXCTRL_MSIX_ENABLE   0x8000
 
#define PCIM_MSIXCTRL_FUNCTION_MASK   0x4000
 
#define PCIM_MSIXCTRL_TABLE_SIZE   0x07FF
 
#define PCIR_MSIX_TABLE   0x4
 
#define PCIR_MSIX_PBA   0x8
 
#define PCIM_MSIX_BIR_MASK   0x7
 
#define PCIM_MSIX_BIR_BAR_10   0
 
#define PCIM_MSIX_BIR_BAR_14   1
 
#define PCIM_MSIX_BIR_BAR_18   2
 
#define PCIM_MSIX_BIR_BAR_1C   3
 
#define PCIM_MSIX_BIR_BAR_20   4
 
#define PCIM_MSIX_BIR_BAR_24   5
 
#define PCIM_MSIX_VCTRL_MASK   0x1
 
#define PCIR_PCIAF_CAP   0x3
 
#define PCIM_PCIAFCAP_TP   0x01
 
#define PCIM_PCIAFCAP_FLR   0x02
 
#define PCIR_PCIAF_CTRL   0x4
 
#define PCIR_PCIAFCTRL_FLR   0x01
 
#define PCIR_PCIAF_STATUS   0x5
 
#define PCIR_PCIAFSTATUS_TP   0x01
 
#define PCIR_AER_UC_STATUS   0x04
 
#define PCIM_AER_UC_TRAINING_ERROR   0x00000001
 
#define PCIM_AER_UC_DL_PROTOCOL_ERROR   0x00000010
 
#define PCIM_AER_UC_SURPRISE_LINK_DOWN   0x00000020
 
#define PCIM_AER_UC_POISONED_TLP   0x00001000
 
#define PCIM_AER_UC_FC_PROTOCOL_ERROR   0x00002000
 
#define PCIM_AER_UC_COMPLETION_TIMEOUT   0x00004000
 
#define PCIM_AER_UC_COMPLETER_ABORT   0x00008000
 
#define PCIM_AER_UC_UNEXPECTED_COMPLETION   0x00010000
 
#define PCIM_AER_UC_RECEIVER_OVERFLOW   0x00020000
 
#define PCIM_AER_UC_MALFORMED_TLP   0x00040000
 
#define PCIM_AER_UC_ECRC_ERROR   0x00080000
 
#define PCIM_AER_UC_UNSUPPORTED_REQUEST   0x00100000
 
#define PCIM_AER_UC_ACS_VIOLATION   0x00200000
 
#define PCIM_AER_UC_INTERNAL_ERROR   0x00400000
 
#define PCIM_AER_UC_MC_BLOCKED_TLP   0x00800000
 
#define PCIM_AER_UC_ATOMIC_EGRESS_BLK   0x01000000
 
#define PCIM_AER_UC_TLP_PREFIX_BLOCKED   0x02000000
 
#define PCIR_AER_UC_MASK   0x08 /* Shares bits with UC_STATUS */
 
#define PCIR_AER_UC_SEVERITY   0x0c /* Shares bits with UC_STATUS */
 
#define PCIR_AER_COR_STATUS   0x10
 
#define PCIM_AER_COR_RECEIVER_ERROR   0x00000001
 
#define PCIM_AER_COR_BAD_TLP   0x00000040
 
#define PCIM_AER_COR_BAD_DLLP   0x00000080
 
#define PCIM_AER_COR_REPLAY_ROLLOVER   0x00000100
 
#define PCIM_AER_COR_REPLAY_TIMEOUT   0x00001000
 
#define PCIM_AER_COR_ADVISORY_NF_ERROR   0x00002000
 
#define PCIM_AER_COR_INTERNAL_ERROR   0x00004000
 
#define PCIM_AER_COR_HEADER_LOG_OVFLOW   0x00008000
 
#define PCIR_AER_COR_MASK   0x14 /* Shares bits with COR_STATUS */
 
#define PCIR_AER_CAP_CONTROL   0x18
 
#define PCIM_AER_FIRST_ERROR_PTR   0x0000001f
 
#define PCIM_AER_ECRC_GEN_CAPABLE   0x00000020
 
#define PCIM_AER_ECRC_GEN_ENABLE   0x00000040
 
#define PCIM_AER_ECRC_CHECK_CAPABLE   0x00000080
 
#define PCIM_AER_ECRC_CHECK_ENABLE   0x00000100
 
#define PCIM_AER_MULT_HDR_CAPABLE   0x00000200
 
#define PCIM_AER_MULT_HDR_ENABLE   0x00000400
 
#define PCIM_AER_TLP_PREFIX_LOG_PRESENT   0x00000800
 
#define PCIR_AER_HEADER_LOG   0x1c
 
#define PCIR_AER_ROOTERR_CMD   0x2c /* Only for root complex ports */
 
#define PCIM_AER_ROOTERR_COR_ENABLE   0x00000001
 
#define PCIM_AER_ROOTERR_NF_ENABLE   0x00000002
 
#define PCIM_AER_ROOTERR_F_ENABLE   0x00000004
 
#define PCIR_AER_ROOTERR_STATUS   0x30 /* Only for root complex ports */
 
#define PCIM_AER_ROOTERR_COR_ERR   0x00000001
 
#define PCIM_AER_ROOTERR_MULTI_COR_ERR   0x00000002
 
#define PCIM_AER_ROOTERR_UC_ERR   0x00000004
 
#define PCIM_AER_ROOTERR_MULTI_UC_ERR   0x00000008
 
#define PCIM_AER_ROOTERR_FIRST_UC_FATAL   0x00000010
 
#define PCIM_AER_ROOTERR_NF_ERR   0x00000020
 
#define PCIM_AER_ROOTERR_F_ERR   0x00000040
 
#define PCIM_AER_ROOTERR_INT_MESSAGE   0xf8000000
 
#define PCIR_AER_COR_SOURCE_ID   0x34 /* Only for root complex ports */
 
#define PCIR_AER_ERR_SOURCE_ID   0x36 /* Only for root complex ports */
 
#define PCIR_AER_TLP_PREFIX_LOG   0x38 /* Only for TLP prefix functions */
 
#define PCIR_VC_CAP1   0x04
 
#define PCIM_VC_CAP1_EXT_COUNT   0x00000007
 
#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT   0x00000070
 
#define PCIR_VC_CAP2   0x08
 
#define PCIR_VC_CONTROL   0x0C
 
#define PCIR_VC_STATUS   0x0E
 
#define PCIR_VC_RESOURCE_CAP(n)   (0x10 + (n) * 0x0C)
 
#define PCIR_VC_RESOURCE_CTL(n)   (0x14 + (n) * 0x0C)
 
#define PCIR_VC_RESOURCE_STA(n)   (0x18 + (n) * 0x0C)
 
#define PCIR_SERIAL_LOW   0x04
 
#define PCIR_SERIAL_HIGH   0x08
 
#define PCIR_SRIOV_CTL   0x08
 
#define PCIM_SRIOV_VF_EN   0x01
 
#define PCIM_SRIOV_VF_MSE   0x08 /* Memory space enable. */
 
#define PCIM_SRIOV_ARI_EN   0x10
 
#define PCIR_SRIOV_TOTAL_VFS   0x0E
 
#define PCIR_SRIOV_NUM_VFS   0x10
 
#define PCIR_SRIOV_VF_OFF   0x14
 
#define PCIR_SRIOV_VF_STRIDE   0x16
 
#define PCIR_SRIOV_VF_DID   0x1A
 
#define PCIR_SRIOV_PAGE_CAP   0x1C
 
#define PCIR_SRIOV_PAGE_SIZE   0x20
 
#define PCI_SRIOV_BASE_PAGE_SHIFT   12
 
#define PCIR_SRIOV_BARS   0x24
 
#define PCIR_SRIOV_BAR(x)   (PCIR_SRIOV_BARS + (x) * 4)
 
#define PCIR_VSEC_HEADER   0x04
 
#define PCIR_VSEC_ID(hdr)   ((hdr) & 0xffff)
 
#define PCIR_VSEC_REV(hdr)   (((hdr) & 0xf0000) >> 16)
 
#define PCIR_VSEC_LENGTH(hdr)   (((hdr) & 0xfff00000) >> 20)
 
#define PCIR_VSEC_DATA   0x08
 
#define PCI_OSC_STATUS   0
 
#define PCI_OSC_SUPPORT   1
 
#define PCIM_OSC_SUPPORT_EXT_PCI_CONF   0x01 /* Extended PCI Config Space */
 
#define PCIM_OSC_SUPPORT_ASPM   0x02 /* Active State Power Management */
 
#define PCIM_OSC_SUPPORT_CPMC   0x04 /* Clock Power Management Cap */
 
#define PCIM_OSC_SUPPORT_SEG_GROUP   0x08 /* PCI Segment Groups supported */
 
#define PCIM_OSC_SUPPORT_MSI   0x10 /* MSI signalling supported */
 
#define PCI_OSC_CTL   2
 
#define PCIM_OSC_CTL_PCIE_HP   0x01 /* PCIe Native Hot Plug */
 
#define PCIM_OSC_CTL_SHPC_HP   0x02 /* SHPC Native Hot Plug */
 
#define PCIM_OSC_CTL_PCIE_PME   0x04 /* PCIe Native Power Mgt Events */
 
#define PCIM_OSC_CTL_PCIE_AER   0x08 /* PCIe Advanced Error Reporting */
 
#define PCIM_OSC_CTL_PCIE_CAP_STRUCT   0x10 /* Various Capability Structures */
 

Macro Definition Documentation

◆ CBB_BCR_CARDBUS_RESET

#define CBB_BCR_CARDBUS_RESET   0x0040

Definition at line 536 of file pcireg.h.

◆ CBB_BCR_IREQ_INT_ENABLE

#define CBB_BCR_IREQ_INT_ENABLE   0x0080

Definition at line 537 of file pcireg.h.

◆ CBB_BCR_ISA_ENABLE

#define CBB_BCR_ISA_ENABLE   0x0004

Definition at line 533 of file pcireg.h.

◆ CBB_BCR_MASTER_ABORT_MODE

#define CBB_BCR_MASTER_ABORT_MODE   0x0020

Definition at line 535 of file pcireg.h.

◆ CBB_BCR_PERR_ENABLE

#define CBB_BCR_PERR_ENABLE   0x0001

Definition at line 531 of file pcireg.h.

◆ CBB_BCR_PREFETCH_0_ENABLE

#define CBB_BCR_PREFETCH_0_ENABLE   0x0100

Definition at line 538 of file pcireg.h.

◆ CBB_BCR_PREFETCH_1_ENABLE

#define CBB_BCR_PREFETCH_1_ENABLE   0x0200

Definition at line 539 of file pcireg.h.

◆ CBB_BCR_SERR_ENABLE

#define CBB_BCR_SERR_ENABLE   0x0002

Definition at line 532 of file pcireg.h.

◆ CBB_BCR_VGA_ENABLE

#define CBB_BCR_VGA_ENABLE   0x0008

Definition at line 534 of file pcireg.h.

◆ CBB_BCR_WRITE_POSTING_ENABLE

#define CBB_BCR_WRITE_POSTING_ENABLE   0x0400

Definition at line 540 of file pcireg.h.

◆ PCI_ARI_RID

#define PCI_ARI_RID (   bus,
  func 
)
Value:
((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
(((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
func
u_int func
Definition: pcib_if.m:81
bus
u_int bus
Definition: pcib_if.m:79
PCI_RID_FUNC_SHIFT
#define PCI_RID_FUNC_SHIFT
Definition: pcireg.h:58
PCI_RID_BUS_SHIFT
#define PCI_RID_BUS_SHIFT
Definition: pcireg.h:56
PCI_BUSMAX
#define PCI_BUSMAX
Definition: pcireg.h:45
PCIE_ARI_FUNCMAX
#define PCIE_ARI_FUNCMAX
Definition: pcireg.h:53

Definition at line 65 of file pcireg.h.

◆ PCI_BAR_IO

#define PCI_BAR_IO (   x)    (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)

Definition at line 219 of file pcireg.h.

◆ PCI_BAR_MEM

#define PCI_BAR_MEM (   x)    (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)

Definition at line 220 of file pcireg.h.

◆ PCI_BUSMAX

#define PCI_BUSMAX   255 /* highest supported bus number */

Definition at line 45 of file pcireg.h.

◆ PCI_CBBIOBASE

#define PCI_CBBIOBASE (   l)    ((l) & ~0x3)

Definition at line 325 of file pcireg.h.

◆ PCI_CBBIOLIMIT

#define PCI_CBBIOLIMIT (   l)    ((l) | 0x3)

Definition at line 326 of file pcireg.h.

◆ PCI_CBBMEMBASE

#define PCI_CBBMEMBASE (   l)    ((l) & ~0xfffff)

Definition at line 323 of file pcireg.h.

◆ PCI_CBBMEMLIMIT

#define PCI_CBBMEMLIMIT (   l)    ((l) | 0xfffff)

Definition at line 324 of file pcireg.h.

◆ PCI_DOMAINMAX

#define PCI_DOMAINMAX   65535 /* highest supported domain number */

Definition at line 44 of file pcireg.h.

◆ PCI_EXTCAP_ID

#define PCI_EXTCAP_ID (   ecap)    ((ecap) & PCIM_EXTCAP_ID)

Definition at line 162 of file pcireg.h.

◆ PCI_EXTCAP_NEXTPTR

#define PCI_EXTCAP_NEXTPTR (   ecap)    (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)

Definition at line 164 of file pcireg.h.

◆ PCI_EXTCAP_VER

#define PCI_EXTCAP_VER (   ecap)    (((ecap) & PCIM_EXTCAP_VER) >> 16)

Definition at line 163 of file pcireg.h.

◆ PCI_FUNCMAX

#define PCI_FUNCMAX   7 /* highest supported function number */

Definition at line 47 of file pcireg.h.

◆ PCI_MAXHDRTYPE

#define PCI_MAXHDRTYPE   2

Definition at line 50 of file pcireg.h.

◆ PCI_OSC_CTL

#define PCI_OSC_CTL   2

Definition at line 1095 of file pcireg.h.

◆ PCI_OSC_STATUS

#define PCI_OSC_STATUS   0

Definition at line 1088 of file pcireg.h.

◆ PCI_OSC_SUPPORT

#define PCI_OSC_SUPPORT   1

Definition at line 1089 of file pcireg.h.

◆ PCI_PPBIOBASE

#define PCI_PPBIOBASE (   h,
  l 
)    ((((h)<<16) + ((l)<<8)) & ~0xfff)

Definition at line 290 of file pcireg.h.

◆ PCI_PPBIOLIMIT

#define PCI_PPBIOLIMIT (   h,
  l 
)    ((((h)<<16) + ((l)<<8)) | 0xfff)

Definition at line 291 of file pcireg.h.

◆ PCI_PPBMEMBASE

#define PCI_PPBMEMBASE (   h,
  l 
)    ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff)

Definition at line 288 of file pcireg.h.

◆ PCI_PPBMEMLIMIT

#define PCI_PPBMEMLIMIT (   h,
  l 
)    ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff)

Definition at line 289 of file pcireg.h.

◆ PCI_REGMAX

#define PCI_REGMAX   255 /* highest supported config register addr. */

Definition at line 48 of file pcireg.h.

◆ PCI_RID

#define PCI_RID (   bus,
  slot,
  func 
)
Value:
((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
(((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \
(((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
slot
u_int slot
Definition: pcib_if.m:80
PCI_RID_SLOT_SHIFT
#define PCI_RID_SLOT_SHIFT
Definition: pcireg.h:57
PCI_SLOTMAX
#define PCI_SLOTMAX
Definition: pcireg.h:46
PCI_FUNCMAX
#define PCI_FUNCMAX
Definition: pcireg.h:47

Definition at line 60 of file pcireg.h.

◆ PCI_RID2BAR

#define PCI_RID2BAR (   rid)    (((rid) - PCIR_BARS) / 4)

Definition at line 218 of file pcireg.h.

◆ PCI_RID2BUS

#define PCI_RID2BUS (   rid)    (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX)

Definition at line 69 of file pcireg.h.

◆ PCI_RID2FUNC

#define PCI_RID2FUNC (   rid)    (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)

Definition at line 71 of file pcireg.h.

◆ PCI_RID2SLOT

#define PCI_RID2SLOT (   rid)    (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)

Definition at line 70 of file pcireg.h.

◆ PCI_RID_BUS_SHIFT

#define PCI_RID_BUS_SHIFT   8

Definition at line 56 of file pcireg.h.

◆ PCI_RID_DOMAIN_SHIFT

#define PCI_RID_DOMAIN_SHIFT   16

Definition at line 55 of file pcireg.h.

◆ PCI_RID_FUNC_SHIFT

#define PCI_RID_FUNC_SHIFT   0

Definition at line 58 of file pcireg.h.

◆ PCI_RID_SLOT_SHIFT

#define PCI_RID_SLOT_SHIFT   3

Definition at line 57 of file pcireg.h.

◆ PCI_SLOTMAX

#define PCI_SLOTMAX   31 /* highest supported slot number */

Definition at line 46 of file pcireg.h.

◆ PCI_SRIOV_BASE_PAGE_SHIFT

#define PCI_SRIOV_BASE_PAGE_SHIFT   12

Definition at line 1073 of file pcireg.h.

◆ PCIB_BCR_DISCARD_TIMER_SERREN

#define PCIB_BCR_DISCARD_TIMER_SERREN   0x0800

Definition at line 529 of file pcireg.h.

◆ PCIB_BCR_DISCARD_TIMER_STATUS

#define PCIB_BCR_DISCARD_TIMER_STATUS   0x0400

Definition at line 528 of file pcireg.h.

◆ PCIB_BCR_ISA_ENABLE

#define PCIB_BCR_ISA_ENABLE   0x0004

Definition at line 521 of file pcireg.h.

◆ PCIB_BCR_MASTER_ABORT_MODE

#define PCIB_BCR_MASTER_ABORT_MODE   0x0020

Definition at line 523 of file pcireg.h.

◆ PCIB_BCR_PERR_ENABLE

#define PCIB_BCR_PERR_ENABLE   0x0001

Definition at line 519 of file pcireg.h.

◆ PCIB_BCR_PRI_DISCARD_TIMEOUT

#define PCIB_BCR_PRI_DISCARD_TIMEOUT   0x0100

Definition at line 526 of file pcireg.h.

◆ PCIB_BCR_SEC_DISCARD_TIMEOUT

#define PCIB_BCR_SEC_DISCARD_TIMEOUT   0x0200

Definition at line 527 of file pcireg.h.

◆ PCIB_BCR_SECBUS_BACKTOBACK

#define PCIB_BCR_SECBUS_BACKTOBACK   0x0080

Definition at line 525 of file pcireg.h.

◆ PCIB_BCR_SECBUS_RESET

#define PCIB_BCR_SECBUS_RESET   0x0040

Definition at line 524 of file pcireg.h.

◆ PCIB_BCR_SERR_ENABLE

#define PCIB_BCR_SERR_ENABLE   0x0002

Definition at line 520 of file pcireg.h.

◆ PCIB_BCR_VGA_ENABLE

#define PCIB_BCR_VGA_ENABLE   0x0008

Definition at line 522 of file pcireg.h.

◆ PCIC_ACCEL

#define PCIC_ACCEL   0x12

Definition at line 511 of file pcireg.h.

◆ PCIC_BASEPERIPH

#define PCIC_BASEPERIPH   0x08

Definition at line 420 of file pcireg.h.

◆ PCIC_BRIDGE

#define PCIC_BRIDGE   0x06

Definition at line 387 of file pcireg.h.

◆ PCIC_CRYPTO

#define PCIC_CRYPTO   0x10

Definition at line 499 of file pcireg.h.

◆ PCIC_DASP

#define PCIC_DASP   0x11

Definition at line 504 of file pcireg.h.

◆ PCIC_DISPLAY

#define PCIC_DISPLAY   0x03

Definition at line 368 of file pcireg.h.

◆ PCIC_DOCKING

#define PCIC_DOCKING   0x0a

Definition at line 444 of file pcireg.h.

◆ PCIC_INPUTDEV

#define PCIC_INPUTDEV   0x09

Definition at line 436 of file pcireg.h.

◆ PCIC_INSTRUMENT

#define PCIC_INSTRUMENT   0x13

Definition at line 514 of file pcireg.h.

◆ PCIC_INTELLIIO

#define PCIC_INTELLIIO   0x0e

Definition at line 490 of file pcireg.h.

◆ PCIC_MEMORY

#define PCIC_MEMORY   0x05

Definition at line 382 of file pcireg.h.

◆ PCIC_MULTIMEDIA

#define PCIC_MULTIMEDIA   0x04

Definition at line 374 of file pcireg.h.

◆ PCIC_NETWORK

#define PCIC_NETWORK   0x02

Definition at line 356 of file pcireg.h.

◆ PCIC_OLD

#define PCIC_OLD   0x00

Definition at line 330 of file pcireg.h.

◆ PCIC_OTHER

#define PCIC_OTHER   0xff

Definition at line 516 of file pcireg.h.

◆ PCIC_PROCESSOR

#define PCIC_PROCESSOR   0x0b

Definition at line 448 of file pcireg.h.

◆ PCIC_SATCOM

#define PCIC_SATCOM   0x0f

Definition at line 493 of file pcireg.h.

◆ PCIC_SERIALBUS

#define PCIC_SERIALBUS   0x0c

Definition at line 457 of file pcireg.h.

◆ PCIC_SIMPLECOMM

#define PCIC_SIMPLECOMM   0x07

Definition at line 404 of file pcireg.h.

◆ PCIC_STORAGE

#define PCIC_STORAGE   0x01

Definition at line 334 of file pcireg.h.

◆ PCIC_WIRELESS

#define PCIC_WIRELESS   0x0d

Definition at line 478 of file pcireg.h.

◆ PCICAP_ID

#define PCICAP_ID   0x0

Definition at line 129 of file pcireg.h.

◆ PCICAP_NEXTPTR

#define PCICAP_NEXTPTR   0x1

Definition at line 130 of file pcireg.h.

◆ PCIE_ARI_FUNC

#define PCIE_ARI_FUNC (   func)    (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)

Definition at line 78 of file pcireg.h.

◆ PCIE_ARI_FUNCMAX

#define PCIE_ARI_FUNCMAX   255

Definition at line 53 of file pcireg.h.

◆ PCIE_ARI_RID2FUNC

#define PCIE_ARI_RID2FUNC (   rid)     (((rid) >> PCI_RID_FUNC_SHIFT) & PCIE_ARI_FUNCMAX)

Definition at line 74 of file pcireg.h.

◆ PCIE_ARI_RID2SLOT

#define PCIE_ARI_RID2SLOT (   rid)    (0)

Definition at line 73 of file pcireg.h.

◆ PCIE_ARI_SLOT

#define PCIE_ARI_SLOT (   func)    (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)

Definition at line 77 of file pcireg.h.

◆ PCIE_ARI_SLOTMAX

#define PCIE_ARI_SLOTMAX   0

Definition at line 52 of file pcireg.h.

◆ PCIE_REGMAX

#define PCIE_REGMAX   4095 /* highest supported config register addr. */

Definition at line 49 of file pcireg.h.

◆ PCIEM_CAP2_ARI

#define PCIEM_CAP2_ARI   0x00000020

Definition at line 929 of file pcireg.h.

◆ PCIEM_CAP2_COMP_TIMO_DISABLE

#define PCIEM_CAP2_COMP_TIMO_DISABLE   0x00000010

Definition at line 928 of file pcireg.h.

◆ PCIEM_CAP2_COMP_TIMO_RANGE_A

#define PCIEM_CAP2_COMP_TIMO_RANGE_A   0x00000001

Definition at line 924 of file pcireg.h.

◆ PCIEM_CAP2_COMP_TIMO_RANGE_B

#define PCIEM_CAP2_COMP_TIMO_RANGE_B   0x00000002

Definition at line 925 of file pcireg.h.

◆ PCIEM_CAP2_COMP_TIMO_RANGE_C

#define PCIEM_CAP2_COMP_TIMO_RANGE_C   0x00000004

Definition at line 926 of file pcireg.h.

◆ PCIEM_CAP2_COMP_TIMO_RANGE_D

#define PCIEM_CAP2_COMP_TIMO_RANGE_D   0x00000008

Definition at line 927 of file pcireg.h.

◆ PCIEM_CAP2_COMP_TIMO_RANGES

#define PCIEM_CAP2_COMP_TIMO_RANGES   0x0000000f

Definition at line 923 of file pcireg.h.

◆ PCIEM_CAP_EXT_TAG_FIELD

#define PCIEM_CAP_EXT_TAG_FIELD   0x00000020

Definition at line 804 of file pcireg.h.

◆ PCIEM_CAP_FLR

#define PCIEM_CAP_FLR   0x10000000

Definition at line 810 of file pcireg.h.

◆ PCIEM_CAP_L0S_LATENCY

#define PCIEM_CAP_L0S_LATENCY   0x000001c0

Definition at line 805 of file pcireg.h.

◆ PCIEM_CAP_L1_LATENCY

#define PCIEM_CAP_L1_LATENCY   0x00000e00

Definition at line 806 of file pcireg.h.

◆ PCIEM_CAP_MAX_PAYLOAD

#define PCIEM_CAP_MAX_PAYLOAD   0x00000007

Definition at line 802 of file pcireg.h.

◆ PCIEM_CAP_PHANTHOM_FUNCS

#define PCIEM_CAP_PHANTHOM_FUNCS   0x00000018

Definition at line 803 of file pcireg.h.

◆ PCIEM_CAP_ROLE_ERR_RPT

#define PCIEM_CAP_ROLE_ERR_RPT   0x00008000

Definition at line 807 of file pcireg.h.

◆ PCIEM_CAP_SLOT_PWR_LIM_SCALE

#define PCIEM_CAP_SLOT_PWR_LIM_SCALE   0x0c000000

Definition at line 809 of file pcireg.h.

◆ PCIEM_CAP_SLOT_PWR_LIM_VAL

#define PCIEM_CAP_SLOT_PWR_LIM_VAL   0x03fc0000

Definition at line 808 of file pcireg.h.

◆ PCIEM_CTL2_ARI

#define PCIEM_CTL2_ARI   0x0020

Definition at line 942 of file pcireg.h.

◆ PCIEM_CTL2_ATOMIC_EGR_BLOCK

#define PCIEM_CTL2_ATOMIC_EGR_BLOCK   0x0080

Definition at line 944 of file pcireg.h.

◆ PCIEM_CTL2_ATOMIC_REQ_ENABLE

#define PCIEM_CTL2_ATOMIC_REQ_ENABLE   0x0040

Definition at line 943 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_100US

#define PCIEM_CTL2_COMP_TIMO_100US   0x0001

Definition at line 933 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_10MS

#define PCIEM_CTL2_COMP_TIMO_10MS   0x0002

Definition at line 934 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_13S

#define PCIEM_CTL2_COMP_TIMO_13S   0x000d

Definition at line 939 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_210MS

#define PCIEM_CTL2_COMP_TIMO_210MS   0x0006

Definition at line 936 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_3500MS

#define PCIEM_CTL2_COMP_TIMO_3500MS   0x000a

Definition at line 938 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_50MS

#define PCIEM_CTL2_COMP_TIMO_50MS   0x0000

Definition at line 932 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_55MS

#define PCIEM_CTL2_COMP_TIMO_55MS   0x0005

Definition at line 935 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_64S

#define PCIEM_CTL2_COMP_TIMO_64S   0x000e

Definition at line 940 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_900MS

#define PCIEM_CTL2_COMP_TIMO_900MS   0x0009

Definition at line 937 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_DISABLE

#define PCIEM_CTL2_COMP_TIMO_DISABLE   0x0010

Definition at line 941 of file pcireg.h.

◆ PCIEM_CTL2_COMP_TIMO_VAL

#define PCIEM_CTL2_COMP_TIMO_VAL   0x000f

Definition at line 931 of file pcireg.h.

◆ PCIEM_CTL2_END2END_TLP

#define PCIEM_CTL2_END2END_TLP   0x8000

Definition at line 953 of file pcireg.h.

◆ PCIEM_CTL2_ID_ORDERED_CMP_EN

#define PCIEM_CTL2_ID_ORDERED_CMP_EN   0x0200

Definition at line 946 of file pcireg.h.

◆ PCIEM_CTL2_ID_ORDERED_REQ_EN

#define PCIEM_CTL2_ID_ORDERED_REQ_EN   0x0100

Definition at line 945 of file pcireg.h.

◆ PCIEM_CTL2_LTR_ENABLE

#define PCIEM_CTL2_LTR_ENABLE   0x0400

Definition at line 947 of file pcireg.h.

◆ PCIEM_CTL2_OBFF

#define PCIEM_CTL2_OBFF   0x6000

Definition at line 948 of file pcireg.h.

◆ PCIEM_CTL_AUX_POWER_PM

#define PCIEM_CTL_AUX_POWER_PM   0x0400

Definition at line 820 of file pcireg.h.

◆ PCIEM_CTL_BRDG_CFG_RETRY

#define PCIEM_CTL_BRDG_CFG_RETRY   0x8000 /* PCI-E - PCI/PCI-X bridges */

Definition at line 823 of file pcireg.h.

◆ PCIEM_CTL_COR_ENABLE

#define PCIEM_CTL_COR_ENABLE   0x0001

Definition at line 812 of file pcireg.h.

◆ PCIEM_CTL_EXT_TAG_FIELD

#define PCIEM_CTL_EXT_TAG_FIELD   0x0100

Definition at line 818 of file pcireg.h.

◆ PCIEM_CTL_FER_ENABLE

#define PCIEM_CTL_FER_ENABLE   0x0004

Definition at line 814 of file pcireg.h.

◆ PCIEM_CTL_INITIATE_FLR

#define PCIEM_CTL_INITIATE_FLR   0x8000 /* FLR capable endpoints */

Definition at line 824 of file pcireg.h.

◆ PCIEM_CTL_MAX_PAYLOAD

#define PCIEM_CTL_MAX_PAYLOAD   0x00e0

Definition at line 817 of file pcireg.h.

◆ PCIEM_CTL_MAX_READ_REQUEST

#define PCIEM_CTL_MAX_READ_REQUEST   0x7000

Definition at line 822 of file pcireg.h.

◆ PCIEM_CTL_NFER_ENABLE

#define PCIEM_CTL_NFER_ENABLE   0x0002

Definition at line 813 of file pcireg.h.

◆ PCIEM_CTL_NOSNOOP_ENABLE

#define PCIEM_CTL_NOSNOOP_ENABLE   0x0800

Definition at line 821 of file pcireg.h.

◆ PCIEM_CTL_PHANTHOM_FUNCS

#define PCIEM_CTL_PHANTHOM_FUNCS   0x0200

Definition at line 819 of file pcireg.h.

◆ PCIEM_CTL_RELAXED_ORD_ENABLE

#define PCIEM_CTL_RELAXED_ORD_ENABLE   0x0010

Definition at line 816 of file pcireg.h.

◆ PCIEM_CTL_URR_ENABLE

#define PCIEM_CTL_URR_ENABLE   0x0008

Definition at line 815 of file pcireg.h.

◆ PCIEM_FLAGS_IRQ

#define PCIEM_FLAGS_IRQ   0x3e00

Definition at line 800 of file pcireg.h.

◆ PCIEM_FLAGS_SLOT

#define PCIEM_FLAGS_SLOT   0x0100

Definition at line 799 of file pcireg.h.

◆ PCIEM_FLAGS_TYPE

#define PCIEM_FLAGS_TYPE   0x00F0

Definition at line 789 of file pcireg.h.

◆ PCIEM_FLAGS_VERSION

#define PCIEM_FLAGS_VERSION   0x000F

Definition at line 788 of file pcireg.h.

◆ PCIEM_LINK_CAP_ASPM

#define PCIEM_LINK_CAP_ASPM   0x00000c00

Definition at line 835 of file pcireg.h.

◆ PCIEM_LINK_CAP_ASPM_COMPLIANCE

#define PCIEM_LINK_CAP_ASPM_COMPLIANCE   0x00400000

Definition at line 842 of file pcireg.h.

◆ PCIEM_LINK_CAP_CLOCK_PM

#define PCIEM_LINK_CAP_CLOCK_PM   0x00040000

Definition at line 838 of file pcireg.h.

◆ PCIEM_LINK_CAP_DL_ACTIVE

#define PCIEM_LINK_CAP_DL_ACTIVE   0x00100000

Definition at line 840 of file pcireg.h.

◆ PCIEM_LINK_CAP_L0S_EXIT

#define PCIEM_LINK_CAP_L0S_EXIT   0x00007000

Definition at line 836 of file pcireg.h.

◆ PCIEM_LINK_CAP_L1_EXIT

#define PCIEM_LINK_CAP_L1_EXIT   0x00038000

Definition at line 837 of file pcireg.h.

◆ PCIEM_LINK_CAP_LINK_BW_NOTIFY

#define PCIEM_LINK_CAP_LINK_BW_NOTIFY   0x00200000

Definition at line 841 of file pcireg.h.

◆ PCIEM_LINK_CAP_MAX_SPEED

#define PCIEM_LINK_CAP_MAX_SPEED   0x0000000f

Definition at line 833 of file pcireg.h.

◆ PCIEM_LINK_CAP_MAX_WIDTH

#define PCIEM_LINK_CAP_MAX_WIDTH   0x000003f0

Definition at line 834 of file pcireg.h.

◆ PCIEM_LINK_CAP_PORT

#define PCIEM_LINK_CAP_PORT   0xff000000

Definition at line 843 of file pcireg.h.

◆ PCIEM_LINK_CAP_SURPRISE_DOWN

#define PCIEM_LINK_CAP_SURPRISE_DOWN   0x00080000

Definition at line 839 of file pcireg.h.

◆ PCIEM_LINK_CTL_ASPMC

#define PCIEM_LINK_CTL_ASPMC   0x0003

Definition at line 848 of file pcireg.h.

◆ PCIEM_LINK_CTL_ASPMC_DIS

#define PCIEM_LINK_CTL_ASPMC_DIS   0x0000

Definition at line 845 of file pcireg.h.

◆ PCIEM_LINK_CTL_ASPMC_L0S

#define PCIEM_LINK_CTL_ASPMC_L0S   0x0001

Definition at line 846 of file pcireg.h.

◆ PCIEM_LINK_CTL_ASPMC_L1

#define PCIEM_LINK_CTL_ASPMC_L1   0x0002

Definition at line 847 of file pcireg.h.

◆ PCIEM_LINK_CTL_COMMON_CLOCK

#define PCIEM_LINK_CTL_COMMON_CLOCK   0x0040

Definition at line 852 of file pcireg.h.

◆ PCIEM_LINK_CTL_ECPM

#define PCIEM_LINK_CTL_ECPM   0x0100

Definition at line 854 of file pcireg.h.

◆ PCIEM_LINK_CTL_EXTENDED_SYNC

#define PCIEM_LINK_CTL_EXTENDED_SYNC   0x0080

Definition at line 853 of file pcireg.h.

◆ PCIEM_LINK_CTL_HAWD

#define PCIEM_LINK_CTL_HAWD   0x0200

Definition at line 855 of file pcireg.h.

◆ PCIEM_LINK_CTL_LABIE

#define PCIEM_LINK_CTL_LABIE   0x0800

Definition at line 857 of file pcireg.h.

◆ PCIEM_LINK_CTL_LBMIE

#define PCIEM_LINK_CTL_LBMIE   0x0400

Definition at line 856 of file pcireg.h.

◆ PCIEM_LINK_CTL_LINK_DIS

#define PCIEM_LINK_CTL_LINK_DIS   0x0010

Definition at line 850 of file pcireg.h.

◆ PCIEM_LINK_CTL_RCB

#define PCIEM_LINK_CTL_RCB   0x0008

Definition at line 849 of file pcireg.h.

◆ PCIEM_LINK_CTL_RETRAIN_LINK

#define PCIEM_LINK_CTL_RETRAIN_LINK   0x0020

Definition at line 851 of file pcireg.h.

◆ PCIEM_LINK_STA_DL_ACTIVE

#define PCIEM_LINK_STA_DL_ACTIVE   0x2000

Definition at line 864 of file pcireg.h.

◆ PCIEM_LINK_STA_LINK_AUTO_BW

#define PCIEM_LINK_STA_LINK_AUTO_BW   0x8000

Definition at line 866 of file pcireg.h.

◆ PCIEM_LINK_STA_LINK_BW_MGMT

#define PCIEM_LINK_STA_LINK_BW_MGMT   0x4000

Definition at line 865 of file pcireg.h.

◆ PCIEM_LINK_STA_SLOT_CLOCK

#define PCIEM_LINK_STA_SLOT_CLOCK   0x1000

Definition at line 863 of file pcireg.h.

◆ PCIEM_LINK_STA_SPEED

#define PCIEM_LINK_STA_SPEED   0x000f

Definition at line 859 of file pcireg.h.

◆ PCIEM_LINK_STA_TRAINING

#define PCIEM_LINK_STA_TRAINING   0x0800

Definition at line 862 of file pcireg.h.

◆ PCIEM_LINK_STA_TRAINING_ERROR

#define PCIEM_LINK_STA_TRAINING_ERROR   0x0400

Definition at line 861 of file pcireg.h.

◆ PCIEM_LINK_STA_WIDTH

#define PCIEM_LINK_STA_WIDTH   0x03f0

Definition at line 860 of file pcireg.h.

◆ PCIEM_OBFF_DISABLE

#define PCIEM_OBFF_DISABLE   0x0000

Definition at line 949 of file pcireg.h.

◆ PCIEM_OBFF_MSGA_ENABLE

#define PCIEM_OBFF_MSGA_ENABLE   0x2000

Definition at line 950 of file pcireg.h.

◆ PCIEM_OBFF_MSGB_ENABLE

#define PCIEM_OBFF_MSGB_ENABLE   0x4000

Definition at line 951 of file pcireg.h.

◆ PCIEM_OBFF_WAKE_ENABLE

#define PCIEM_OBFF_WAKE_ENABLE   0x6000

Definition at line 952 of file pcireg.h.

◆ PCIEM_ROOT_CAP_CRS_VIS

#define PCIEM_ROOT_CAP_CRS_VIS   0x0001

Definition at line 917 of file pcireg.h.

◆ PCIEM_ROOT_CTL_CRS_VIS

#define PCIEM_ROOT_CTL_CRS_VIS   0x0010

Definition at line 915 of file pcireg.h.

◆ PCIEM_ROOT_CTL_PME

#define PCIEM_ROOT_CTL_PME   0x0008

Definition at line 914 of file pcireg.h.

◆ PCIEM_ROOT_CTL_SERR_CORR

#define PCIEM_ROOT_CTL_SERR_CORR   0x0001

Definition at line 911 of file pcireg.h.

◆ PCIEM_ROOT_CTL_SERR_FATAL

#define PCIEM_ROOT_CTL_SERR_FATAL   0x0004

Definition at line 913 of file pcireg.h.

◆ PCIEM_ROOT_CTL_SERR_NONFATAL

#define PCIEM_ROOT_CTL_SERR_NONFATAL   0x0002

Definition at line 912 of file pcireg.h.

◆ PCIEM_ROOT_STA_PME_PEND

#define PCIEM_ROOT_STA_PME_PEND   0x00020000

Definition at line 921 of file pcireg.h.

◆ PCIEM_ROOT_STA_PME_REQID_MASK

#define PCIEM_ROOT_STA_PME_REQID_MASK   0x0000ffff

Definition at line 919 of file pcireg.h.

◆ PCIEM_ROOT_STA_PME_STATUS

#define PCIEM_ROOT_STA_PME_STATUS   0x00010000

Definition at line 920 of file pcireg.h.

◆ PCIEM_SLOT_CAP_AIP

#define PCIEM_SLOT_CAP_AIP   0x00000008

Definition at line 871 of file pcireg.h.

◆ PCIEM_SLOT_CAP_APB

#define PCIEM_SLOT_CAP_APB   0x00000001

Definition at line 868 of file pcireg.h.

◆ PCIEM_SLOT_CAP_EIP

#define PCIEM_SLOT_CAP_EIP   0x00020000

Definition at line 877 of file pcireg.h.

◆ PCIEM_SLOT_CAP_HPC

#define PCIEM_SLOT_CAP_HPC   0x00000040

Definition at line 874 of file pcireg.h.

◆ PCIEM_SLOT_CAP_HPS

#define PCIEM_SLOT_CAP_HPS   0x00000020

Definition at line 873 of file pcireg.h.

◆ PCIEM_SLOT_CAP_MRLSP

#define PCIEM_SLOT_CAP_MRLSP   0x00000004

Definition at line 870 of file pcireg.h.

◆ PCIEM_SLOT_CAP_NCCS

#define PCIEM_SLOT_CAP_NCCS   0x00040000

Definition at line 878 of file pcireg.h.

◆ PCIEM_SLOT_CAP_PCP

#define PCIEM_SLOT_CAP_PCP   0x00000002

Definition at line 869 of file pcireg.h.

◆ PCIEM_SLOT_CAP_PIP

#define PCIEM_SLOT_CAP_PIP   0x00000010

Definition at line 872 of file pcireg.h.

◆ PCIEM_SLOT_CAP_PSN

#define PCIEM_SLOT_CAP_PSN   0xfff80000

Definition at line 879 of file pcireg.h.

◆ PCIEM_SLOT_CAP_SPLS

#define PCIEM_SLOT_CAP_SPLS   0x00018000

Definition at line 876 of file pcireg.h.

◆ PCIEM_SLOT_CAP_SPLV

#define PCIEM_SLOT_CAP_SPLV   0x00007f80

Definition at line 875 of file pcireg.h.

◆ PCIEM_SLOT_CTL_ABPE

#define PCIEM_SLOT_CTL_ABPE   0x0001

Definition at line 881 of file pcireg.h.

◆ PCIEM_SLOT_CTL_AI_BLINK

#define PCIEM_SLOT_CTL_AI_BLINK   0x0080

Definition at line 889 of file pcireg.h.

◆ PCIEM_SLOT_CTL_AI_OFF

#define PCIEM_SLOT_CTL_AI_OFF   0x00c0

Definition at line 890 of file pcireg.h.

◆ PCIEM_SLOT_CTL_AI_ON

#define PCIEM_SLOT_CTL_AI_ON   0x0040

Definition at line 888 of file pcireg.h.

◆ PCIEM_SLOT_CTL_AIC

#define PCIEM_SLOT_CTL_AIC   0x00c0

Definition at line 887 of file pcireg.h.

◆ PCIEM_SLOT_CTL_CCIE

#define PCIEM_SLOT_CTL_CCIE   0x0010

Definition at line 885 of file pcireg.h.

◆ PCIEM_SLOT_CTL_DLLSCE

#define PCIEM_SLOT_CTL_DLLSCE   0x1000

Definition at line 899 of file pcireg.h.

◆ PCIEM_SLOT_CTL_EIC

#define PCIEM_SLOT_CTL_EIC   0x0800

Definition at line 898 of file pcireg.h.

◆ PCIEM_SLOT_CTL_HPIE

#define PCIEM_SLOT_CTL_HPIE   0x0020

Definition at line 886 of file pcireg.h.

◆ PCIEM_SLOT_CTL_MRLSCE

#define PCIEM_SLOT_CTL_MRLSCE   0x0004

Definition at line 883 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PC_OFF

#define PCIEM_SLOT_CTL_PC_OFF   0x0400

Definition at line 897 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PC_ON

#define PCIEM_SLOT_CTL_PC_ON   0x0000

Definition at line 896 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PCC

#define PCIEM_SLOT_CTL_PCC   0x0400

Definition at line 895 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PDCE

#define PCIEM_SLOT_CTL_PDCE   0x0008

Definition at line 884 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PFDE

#define PCIEM_SLOT_CTL_PFDE   0x0002

Definition at line 882 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PI_BLINK

#define PCIEM_SLOT_CTL_PI_BLINK   0x0200

Definition at line 893 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PI_OFF

#define PCIEM_SLOT_CTL_PI_OFF   0x0300

Definition at line 894 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PI_ON

#define PCIEM_SLOT_CTL_PI_ON   0x0100

Definition at line 892 of file pcireg.h.

◆ PCIEM_SLOT_CTL_PIC

#define PCIEM_SLOT_CTL_PIC   0x0300

Definition at line 891 of file pcireg.h.

◆ PCIEM_SLOT_STA_ABP

#define PCIEM_SLOT_STA_ABP   0x0001

Definition at line 901 of file pcireg.h.

◆ PCIEM_SLOT_STA_CC

#define PCIEM_SLOT_STA_CC   0x0010

Definition at line 905 of file pcireg.h.

◆ PCIEM_SLOT_STA_DLLSC

#define PCIEM_SLOT_STA_DLLSC   0x0100

Definition at line 909 of file pcireg.h.

◆ PCIEM_SLOT_STA_EIS

#define PCIEM_SLOT_STA_EIS   0x0080

Definition at line 908 of file pcireg.h.

◆ PCIEM_SLOT_STA_MRLSC

#define PCIEM_SLOT_STA_MRLSC   0x0004

Definition at line 903 of file pcireg.h.

◆ PCIEM_SLOT_STA_MRLSS

#define PCIEM_SLOT_STA_MRLSS   0x0020

Definition at line 906 of file pcireg.h.

◆ PCIEM_SLOT_STA_PDC

#define PCIEM_SLOT_STA_PDC   0x0008

Definition at line 904 of file pcireg.h.

◆ PCIEM_SLOT_STA_PDS

#define PCIEM_SLOT_STA_PDS   0x0040

Definition at line 907 of file pcireg.h.

◆ PCIEM_SLOT_STA_PFD

#define PCIEM_SLOT_STA_PFD   0x0002

Definition at line 902 of file pcireg.h.

◆ PCIEM_STA_AUX_POWER

#define PCIEM_STA_AUX_POWER   0x0010

Definition at line 830 of file pcireg.h.

◆ PCIEM_STA_CORRECTABLE_ERROR

#define PCIEM_STA_CORRECTABLE_ERROR   0x0001

Definition at line 826 of file pcireg.h.

◆ PCIEM_STA_FATAL_ERROR

#define PCIEM_STA_FATAL_ERROR   0x0004

Definition at line 828 of file pcireg.h.

◆ PCIEM_STA_NON_FATAL_ERROR

#define PCIEM_STA_NON_FATAL_ERROR   0x0002

Definition at line 827 of file pcireg.h.

◆ PCIEM_STA_TRANSACTION_PND

#define PCIEM_STA_TRANSACTION_PND   0x0020

Definition at line 831 of file pcireg.h.

◆ PCIEM_STA_UNSUPPORTED_REQ

#define PCIEM_STA_UNSUPPORTED_REQ   0x0008

Definition at line 829 of file pcireg.h.

◆ PCIEM_TYPE_DOWNSTREAM_PORT

#define PCIEM_TYPE_DOWNSTREAM_PORT   0x0060

Definition at line 794 of file pcireg.h.

◆ PCIEM_TYPE_ENDPOINT

#define PCIEM_TYPE_ENDPOINT   0x0000

Definition at line 790 of file pcireg.h.

◆ PCIEM_TYPE_LEGACY_ENDPOINT

#define PCIEM_TYPE_LEGACY_ENDPOINT   0x0010

Definition at line 791 of file pcireg.h.

◆ PCIEM_TYPE_PCI_BRIDGE

#define PCIEM_TYPE_PCI_BRIDGE   0x0070

Definition at line 795 of file pcireg.h.

◆ PCIEM_TYPE_PCIE_BRIDGE

#define PCIEM_TYPE_PCIE_BRIDGE   0x0080

Definition at line 796 of file pcireg.h.

◆ PCIEM_TYPE_ROOT_EC

#define PCIEM_TYPE_ROOT_EC   0x00a0

Definition at line 798 of file pcireg.h.

◆ PCIEM_TYPE_ROOT_INT_EP

#define PCIEM_TYPE_ROOT_INT_EP   0x0090

Definition at line 797 of file pcireg.h.

◆ PCIEM_TYPE_ROOT_PORT

#define PCIEM_TYPE_ROOT_PORT   0x0040

Definition at line 792 of file pcireg.h.

◆ PCIEM_TYPE_UPSTREAM_PORT

#define PCIEM_TYPE_UPSTREAM_PORT   0x0050

Definition at line 793 of file pcireg.h.

◆ PCIER_DEVICE_CAP

#define PCIER_DEVICE_CAP   0x4

Definition at line 801 of file pcireg.h.

◆ PCIER_DEVICE_CAP2

#define PCIER_DEVICE_CAP2   0x24

Definition at line 922 of file pcireg.h.

◆ PCIER_DEVICE_CTL

#define PCIER_DEVICE_CTL   0x8

Definition at line 811 of file pcireg.h.

◆ PCIER_DEVICE_CTL2

#define PCIER_DEVICE_CTL2   0x28

Definition at line 930 of file pcireg.h.

◆ PCIER_DEVICE_STA

#define PCIER_DEVICE_STA   0xa

Definition at line 825 of file pcireg.h.

◆ PCIER_DEVICE_STA2

#define PCIER_DEVICE_STA2   0x2a

Definition at line 954 of file pcireg.h.

◆ PCIER_FLAGS

#define PCIER_FLAGS   0x2

Definition at line 787 of file pcireg.h.

◆ PCIER_LINK_CAP

#define PCIER_LINK_CAP   0xc

Definition at line 832 of file pcireg.h.

◆ PCIER_LINK_CAP2

#define PCIER_LINK_CAP2   0x2c

Definition at line 955 of file pcireg.h.

◆ PCIER_LINK_CTL

#define PCIER_LINK_CTL   0x10

Definition at line 844 of file pcireg.h.

◆ PCIER_LINK_CTL2

#define PCIER_LINK_CTL2   0x30

Definition at line 956 of file pcireg.h.

◆ PCIER_LINK_STA

#define PCIER_LINK_STA   0x12

Definition at line 858 of file pcireg.h.

◆ PCIER_LINK_STA2

#define PCIER_LINK_STA2   0x32

Definition at line 957 of file pcireg.h.

◆ PCIER_ROOT_CAP

#define PCIER_ROOT_CAP   0x1e

Definition at line 916 of file pcireg.h.

◆ PCIER_ROOT_CTL

#define PCIER_ROOT_CTL   0x1c

Definition at line 910 of file pcireg.h.

◆ PCIER_ROOT_STA

#define PCIER_ROOT_STA   0x20

Definition at line 918 of file pcireg.h.

◆ PCIER_SLOT_CAP

#define PCIER_SLOT_CAP   0x14

Definition at line 867 of file pcireg.h.

◆ PCIER_SLOT_CAP2

#define PCIER_SLOT_CAP2   0x34

Definition at line 958 of file pcireg.h.

◆ PCIER_SLOT_CTL

#define PCIER_SLOT_CTL   0x18

Definition at line 880 of file pcireg.h.

◆ PCIER_SLOT_CTL2

#define PCIER_SLOT_CTL2   0x38

Definition at line 959 of file pcireg.h.

◆ PCIER_SLOT_STA

#define PCIER_SLOT_STA   0x1a

Definition at line 900 of file pcireg.h.

◆ PCIER_SLOT_STA2

#define PCIER_SLOT_STA2   0x3a

Definition at line 960 of file pcireg.h.

◆ PCIM_AER_COR_ADVISORY_NF_ERROR

#define PCIM_AER_COR_ADVISORY_NF_ERROR   0x00002000

Definition at line 1014 of file pcireg.h.

◆ PCIM_AER_COR_BAD_DLLP

#define PCIM_AER_COR_BAD_DLLP   0x00000080

Definition at line 1011 of file pcireg.h.

◆ PCIM_AER_COR_BAD_TLP

#define PCIM_AER_COR_BAD_TLP   0x00000040

Definition at line 1010 of file pcireg.h.

◆ PCIM_AER_COR_HEADER_LOG_OVFLOW

#define PCIM_AER_COR_HEADER_LOG_OVFLOW   0x00008000

Definition at line 1016 of file pcireg.h.

◆ PCIM_AER_COR_INTERNAL_ERROR

#define PCIM_AER_COR_INTERNAL_ERROR   0x00004000

Definition at line 1015 of file pcireg.h.

◆ PCIM_AER_COR_RECEIVER_ERROR

#define PCIM_AER_COR_RECEIVER_ERROR   0x00000001

Definition at line 1009 of file pcireg.h.

◆ PCIM_AER_COR_REPLAY_ROLLOVER

#define PCIM_AER_COR_REPLAY_ROLLOVER   0x00000100

Definition at line 1012 of file pcireg.h.

◆ PCIM_AER_COR_REPLAY_TIMEOUT

#define PCIM_AER_COR_REPLAY_TIMEOUT   0x00001000

Definition at line 1013 of file pcireg.h.

◆ PCIM_AER_ECRC_CHECK_CAPABLE

#define PCIM_AER_ECRC_CHECK_CAPABLE   0x00000080

Definition at line 1022 of file pcireg.h.

◆ PCIM_AER_ECRC_CHECK_ENABLE

#define PCIM_AER_ECRC_CHECK_ENABLE   0x00000100

Definition at line 1023 of file pcireg.h.

◆ PCIM_AER_ECRC_GEN_CAPABLE

#define PCIM_AER_ECRC_GEN_CAPABLE   0x00000020

Definition at line 1020 of file pcireg.h.

◆ PCIM_AER_ECRC_GEN_ENABLE

#define PCIM_AER_ECRC_GEN_ENABLE   0x00000040

Definition at line 1021 of file pcireg.h.

◆ PCIM_AER_FIRST_ERROR_PTR

#define PCIM_AER_FIRST_ERROR_PTR   0x0000001f

Definition at line 1019 of file pcireg.h.

◆ PCIM_AER_MULT_HDR_CAPABLE

#define PCIM_AER_MULT_HDR_CAPABLE   0x00000200

Definition at line 1024 of file pcireg.h.

◆ PCIM_AER_MULT_HDR_ENABLE

#define PCIM_AER_MULT_HDR_ENABLE   0x00000400

Definition at line 1025 of file pcireg.h.

◆ PCIM_AER_ROOTERR_COR_ENABLE

#define PCIM_AER_ROOTERR_COR_ENABLE   0x00000001

Definition at line 1029 of file pcireg.h.

◆ PCIM_AER_ROOTERR_COR_ERR

#define PCIM_AER_ROOTERR_COR_ERR   0x00000001

Definition at line 1033 of file pcireg.h.

◆ PCIM_AER_ROOTERR_F_ENABLE

#define PCIM_AER_ROOTERR_F_ENABLE   0x00000004

Definition at line 1031 of file pcireg.h.

◆ PCIM_AER_ROOTERR_F_ERR

#define PCIM_AER_ROOTERR_F_ERR   0x00000040

Definition at line 1039 of file pcireg.h.

◆ PCIM_AER_ROOTERR_FIRST_UC_FATAL

#define PCIM_AER_ROOTERR_FIRST_UC_FATAL   0x00000010

Definition at line 1037 of file pcireg.h.

◆ PCIM_AER_ROOTERR_INT_MESSAGE

#define PCIM_AER_ROOTERR_INT_MESSAGE   0xf8000000

Definition at line 1040 of file pcireg.h.

◆ PCIM_AER_ROOTERR_MULTI_COR_ERR

#define PCIM_AER_ROOTERR_MULTI_COR_ERR   0x00000002

Definition at line 1034 of file pcireg.h.

◆ PCIM_AER_ROOTERR_MULTI_UC_ERR

#define PCIM_AER_ROOTERR_MULTI_UC_ERR   0x00000008

Definition at line 1036 of file pcireg.h.

◆ PCIM_AER_ROOTERR_NF_ENABLE

#define PCIM_AER_ROOTERR_NF_ENABLE   0x00000002

Definition at line 1030 of file pcireg.h.

◆ PCIM_AER_ROOTERR_NF_ERR

#define PCIM_AER_ROOTERR_NF_ERR   0x00000020

Definition at line 1038 of file pcireg.h.

◆ PCIM_AER_ROOTERR_UC_ERR

#define PCIM_AER_ROOTERR_UC_ERR   0x00000004

Definition at line 1035 of file pcireg.h.

◆ PCIM_AER_TLP_PREFIX_LOG_PRESENT

#define PCIM_AER_TLP_PREFIX_LOG_PRESENT   0x00000800

Definition at line 1026 of file pcireg.h.

◆ PCIM_AER_UC_ACS_VIOLATION

#define PCIM_AER_UC_ACS_VIOLATION   0x00200000

Definition at line 1001 of file pcireg.h.

◆ PCIM_AER_UC_ATOMIC_EGRESS_BLK

#define PCIM_AER_UC_ATOMIC_EGRESS_BLK   0x01000000

Definition at line 1004 of file pcireg.h.

◆ PCIM_AER_UC_COMPLETER_ABORT

#define PCIM_AER_UC_COMPLETER_ABORT   0x00008000

Definition at line 995 of file pcireg.h.

◆ PCIM_AER_UC_COMPLETION_TIMEOUT

#define PCIM_AER_UC_COMPLETION_TIMEOUT   0x00004000

Definition at line 994 of file pcireg.h.

◆ PCIM_AER_UC_DL_PROTOCOL_ERROR

#define PCIM_AER_UC_DL_PROTOCOL_ERROR   0x00000010

Definition at line 990 of file pcireg.h.

◆ PCIM_AER_UC_ECRC_ERROR

#define PCIM_AER_UC_ECRC_ERROR   0x00080000

Definition at line 999 of file pcireg.h.

◆ PCIM_AER_UC_FC_PROTOCOL_ERROR

#define PCIM_AER_UC_FC_PROTOCOL_ERROR   0x00002000

Definition at line 993 of file pcireg.h.

◆ PCIM_AER_UC_INTERNAL_ERROR

#define PCIM_AER_UC_INTERNAL_ERROR   0x00400000

Definition at line 1002 of file pcireg.h.

◆ PCIM_AER_UC_MALFORMED_TLP

#define PCIM_AER_UC_MALFORMED_TLP   0x00040000

Definition at line 998 of file pcireg.h.

◆ PCIM_AER_UC_MC_BLOCKED_TLP

#define PCIM_AER_UC_MC_BLOCKED_TLP   0x00800000

Definition at line 1003 of file pcireg.h.

◆ PCIM_AER_UC_POISONED_TLP

#define PCIM_AER_UC_POISONED_TLP   0x00001000

Definition at line 992 of file pcireg.h.

◆ PCIM_AER_UC_RECEIVER_OVERFLOW

#define PCIM_AER_UC_RECEIVER_OVERFLOW   0x00020000

Definition at line 997 of file pcireg.h.

◆ PCIM_AER_UC_SURPRISE_LINK_DOWN

#define PCIM_AER_UC_SURPRISE_LINK_DOWN   0x00000020

Definition at line 991 of file pcireg.h.

◆ PCIM_AER_UC_TLP_PREFIX_BLOCKED

#define PCIM_AER_UC_TLP_PREFIX_BLOCKED   0x02000000

Definition at line 1005 of file pcireg.h.

◆ PCIM_AER_UC_TRAINING_ERROR

#define PCIM_AER_UC_TRAINING_ERROR   0x00000001

Definition at line 989 of file pcireg.h.

◆ PCIM_AER_UC_UNEXPECTED_COMPLETION

#define PCIM_AER_UC_UNEXPECTED_COMPLETION   0x00010000

Definition at line 996 of file pcireg.h.

◆ PCIM_AER_UC_UNSUPPORTED_REQUEST

#define PCIM_AER_UC_UNSUPPORTED_REQUEST   0x00100000

Definition at line 1000 of file pcireg.h.

◆ PCIM_BAR_IO_BASE

#define PCIM_BAR_IO_BASE   0xfffffffc

Definition at line 231 of file pcireg.h.

◆ PCIM_BAR_IO_RESERVED

#define PCIM_BAR_IO_RESERVED   0x00000002

Definition at line 230 of file pcireg.h.

◆ PCIM_BAR_IO_SPACE

#define PCIM_BAR_IO_SPACE   1

Definition at line 223 of file pcireg.h.

◆ PCIM_BAR_MEM_1MB

#define PCIM_BAR_MEM_1MB   2 /* Locate below 1MB in PCI <= 2.1 */

Definition at line 226 of file pcireg.h.

◆ PCIM_BAR_MEM_32

#define PCIM_BAR_MEM_32   0

Definition at line 225 of file pcireg.h.

◆ PCIM_BAR_MEM_64

#define PCIM_BAR_MEM_64   4

Definition at line 227 of file pcireg.h.

◆ PCIM_BAR_MEM_BASE

#define PCIM_BAR_MEM_BASE   0xfffffffffffffff0ULL

Definition at line 229 of file pcireg.h.

◆ PCIM_BAR_MEM_PREFETCH

#define PCIM_BAR_MEM_PREFETCH   0x00000008

Definition at line 228 of file pcireg.h.

◆ PCIM_BAR_MEM_SPACE

#define PCIM_BAR_MEM_SPACE   0

Definition at line 222 of file pcireg.h.

◆ PCIM_BAR_MEM_TYPE

#define PCIM_BAR_MEM_TYPE   0x00000006

Definition at line 224 of file pcireg.h.

◆ PCIM_BAR_SPACE

#define PCIM_BAR_SPACE   0x00000001

Definition at line 221 of file pcireg.h.

◆ PCIM_BIOS_ADDR_MASK

#define PCIM_BIOS_ADDR_MASK   0xfffff800

Definition at line 249 of file pcireg.h.

◆ PCIM_BIOS_ENABLE

#define PCIM_BIOS_ENABLE   0x01

Definition at line 248 of file pcireg.h.

◆ PCIM_BRIO_16

#define PCIM_BRIO_16   0x0

Definition at line 270 of file pcireg.h.

◆ PCIM_BRIO_32

#define PCIM_BRIO_32   0x1

Definition at line 271 of file pcireg.h.

◆ PCIM_BRIO_MASK

#define PCIM_BRIO_MASK   0xf

Definition at line 272 of file pcireg.h.

◆ PCIM_BRPM_32

#define PCIM_BRPM_32   0x0

Definition at line 281 of file pcireg.h.

◆ PCIM_BRPM_64

#define PCIM_BRPM_64   0x1

Definition at line 282 of file pcireg.h.

◆ PCIM_BRPM_MASK

#define PCIM_BRPM_MASK   0xf

Definition at line 283 of file pcireg.h.

◆ PCIM_CBBIO_16

#define PCIM_CBBIO_16   0x0

Definition at line 312 of file pcireg.h.

◆ PCIM_CBBIO_32

#define PCIM_CBBIO_32   0x1

Definition at line 313 of file pcireg.h.

◆ PCIM_CBBIO_MASK

#define PCIM_CBBIO_MASK   0x3

Definition at line 314 of file pcireg.h.

◆ PCIM_CIS_ADDR_MASK

#define PCIM_CIS_ADDR_MASK   0x0ffffff8

Definition at line 242 of file pcireg.h.

◆ PCIM_CIS_ASI_BAR0

#define PCIM_CIS_ASI_BAR0   1

Definition at line 235 of file pcireg.h.

◆ PCIM_CIS_ASI_BAR1

#define PCIM_CIS_ASI_BAR1   2

Definition at line 236 of file pcireg.h.

◆ PCIM_CIS_ASI_BAR2

#define PCIM_CIS_ASI_BAR2   3

Definition at line 237 of file pcireg.h.

◆ PCIM_CIS_ASI_BAR3

#define PCIM_CIS_ASI_BAR3   4

Definition at line 238 of file pcireg.h.

◆ PCIM_CIS_ASI_BAR4

#define PCIM_CIS_ASI_BAR4   5

Definition at line 239 of file pcireg.h.

◆ PCIM_CIS_ASI_BAR5

#define PCIM_CIS_ASI_BAR5   6

Definition at line 240 of file pcireg.h.

◆ PCIM_CIS_ASI_CONFIG

#define PCIM_CIS_ASI_CONFIG   0

Definition at line 234 of file pcireg.h.

◆ PCIM_CIS_ASI_MASK

#define PCIM_CIS_ASI_MASK   0x00000007

Definition at line 233 of file pcireg.h.

◆ PCIM_CIS_ASI_ROM

#define PCIM_CIS_ASI_ROM   7

Definition at line 241 of file pcireg.h.

◆ PCIM_CIS_CONFIG_MASK

#define PCIM_CIS_CONFIG_MASK   0xff

Definition at line 244 of file pcireg.h.

◆ PCIM_CIS_ROM_MASK

#define PCIM_CIS_ROM_MASK   0xf0000000

Definition at line 243 of file pcireg.h.

◆ PCIM_CMD_BACKTOBACK

#define PCIM_CMD_BACKTOBACK   0x0200

Definition at line 93 of file pcireg.h.

◆ PCIM_CMD_BUSMASTEREN

#define PCIM_CMD_BUSMASTEREN   0x0004

Definition at line 88 of file pcireg.h.

◆ PCIM_CMD_INTxDIS

#define PCIM_CMD_INTxDIS   0x0400

Definition at line 94 of file pcireg.h.

◆ PCIM_CMD_MEMEN

#define PCIM_CMD_MEMEN   0x0002

Definition at line 87 of file pcireg.h.

◆ PCIM_CMD_MWRICEN

#define PCIM_CMD_MWRICEN   0x0010

Definition at line 90 of file pcireg.h.

◆ PCIM_CMD_PERRESPEN

#define PCIM_CMD_PERRESPEN   0x0040

Definition at line 91 of file pcireg.h.

◆ PCIM_CMD_PORTEN

#define PCIM_CMD_PORTEN   0x0001

Definition at line 86 of file pcireg.h.

◆ PCIM_CMD_SERRESPEN

#define PCIM_CMD_SERRESPEN   0x0100

Definition at line 92 of file pcireg.h.

◆ PCIM_CMD_SPECIALEN

#define PCIM_CMD_SPECIALEN   0x0008

Definition at line 89 of file pcireg.h.

◆ PCIM_DEBUG_PORT_BAR

#define PCIM_DEBUG_PORT_BAR   0xe000

Definition at line 781 of file pcireg.h.

◆ PCIM_DEBUG_PORT_OFFSET

#define PCIM_DEBUG_PORT_OFFSET   0x1FFF

Definition at line 780 of file pcireg.h.

◆ PCIM_EA_BASE

#define PCIM_EA_BASE   4 /* Base Address Offset */

Definition at line 662 of file pcireg.h.

◆ PCIM_EA_BEI

#define PCIM_EA_BEI   0x000000f0 /* BAR Equivalent Indicator */

Definition at line 631 of file pcireg.h.

◆ PCIM_EA_BEI_BAR

#define PCIM_EA_BEI_BAR (   x)    (((x) >> PCIM_EA_BEI_OFFSET) & 0xf)

Definition at line 636 of file pcireg.h.

◆ PCIM_EA_BEI_BAR_0

#define PCIM_EA_BEI_BAR_0   0

Definition at line 634 of file pcireg.h.

◆ PCIM_EA_BEI_BAR_5

#define PCIM_EA_BEI_BAR_5   5

Definition at line 635 of file pcireg.h.

◆ PCIM_EA_BEI_BRIDGE

#define PCIM_EA_BEI_BRIDGE   0x6 /* Resource behind bridge */

Definition at line 637 of file pcireg.h.

◆ PCIM_EA_BEI_ENI

#define PCIM_EA_BEI_ENI   0x7 /* Equivalent Not Indicated */

Definition at line 638 of file pcireg.h.

◆ PCIM_EA_BEI_OFFSET

#define PCIM_EA_BEI_OFFSET   4

Definition at line 632 of file pcireg.h.

◆ PCIM_EA_BEI_RESERVED

#define PCIM_EA_BEI_RESERVED   0xf /* Reserved - Treat like ENI */

Definition at line 643 of file pcireg.h.

◆ PCIM_EA_BEI_ROM

#define PCIM_EA_BEI_ROM   0x8 /* Expansion ROM */

Definition at line 639 of file pcireg.h.

◆ PCIM_EA_BEI_VF_BAR_0

#define PCIM_EA_BEI_VF_BAR_0   9

Definition at line 641 of file pcireg.h.

◆ PCIM_EA_BEI_VF_BAR_5

#define PCIM_EA_BEI_VF_BAR_5   14

Definition at line 642 of file pcireg.h.

◆ PCIM_EA_ENABLE

#define PCIM_EA_ENABLE   0x80000000 /* Enable for this entry */

Definition at line 661 of file pcireg.h.

◆ PCIM_EA_ES

#define PCIM_EA_ES   0x00000007 /* Entry Size */

Definition at line 630 of file pcireg.h.

◆ PCIM_EA_FIELD_MASK

#define PCIM_EA_FIELD_MASK   0xfffffffc /* For Base & Max Offset */

Definition at line 666 of file pcireg.h.

◆ PCIM_EA_IS_64

#define PCIM_EA_IS_64   0x00000002 /* 64-bit field flag */

Definition at line 665 of file pcireg.h.

◆ PCIM_EA_MAX_OFFSET

#define PCIM_EA_MAX_OFFSET   8 /* MaxOffset (resource length) */

Definition at line 663 of file pcireg.h.

◆ PCIM_EA_NUM_ENT_MASK

#define PCIM_EA_NUM_ENT_MASK   0x3f /* Num Entries Mask */

Definition at line 627 of file pcireg.h.

◆ PCIM_EA_P_BRIDGE_IO

#define PCIM_EA_P_BRIDGE_IO   0x07 /* Bridge I/O Space */

Definition at line 655 of file pcireg.h.

◆ PCIM_EA_P_BRIDGE_MEM

#define PCIM_EA_P_BRIDGE_MEM   0x05 /* Bridge Non-Prefetch Memory */

Definition at line 653 of file pcireg.h.

◆ PCIM_EA_P_BRIDGE_MEM_PREFETCH

#define PCIM_EA_P_BRIDGE_MEM_PREFETCH   0x06 /* Bridge Prefetchable Memory */

Definition at line 654 of file pcireg.h.

◆ PCIM_EA_P_IO

#define PCIM_EA_P_IO   0x02 /* I/O Space */

Definition at line 650 of file pcireg.h.

◆ PCIM_EA_P_IO_RESERVED

#define PCIM_EA_P_IO_RESERVED   0xfe /* Reserved I/O Space */

Definition at line 658 of file pcireg.h.

◆ PCIM_EA_P_MEM

#define PCIM_EA_P_MEM   0x00 /* Non-Prefetch Memory */

Definition at line 648 of file pcireg.h.

◆ PCIM_EA_P_MEM_PREFETCH

#define PCIM_EA_P_MEM_PREFETCH   0x01 /* Prefetchable Memory */

Definition at line 649 of file pcireg.h.

◆ PCIM_EA_P_MEM_RESERVED

#define PCIM_EA_P_MEM_RESERVED   0xfd /* Reserved Memory */

Definition at line 657 of file pcireg.h.

◆ PCIM_EA_P_UNAVAILABLE

#define PCIM_EA_P_UNAVAILABLE   0xff /* Entry Unavailable */

Definition at line 659 of file pcireg.h.

◆ PCIM_EA_P_VF_MEM

#define PCIM_EA_P_VF_MEM   0x04 /* VF Non-Prefetch Memory */

Definition at line 652 of file pcireg.h.

◆ PCIM_EA_P_VF_MEM_PREFETCH

#define PCIM_EA_P_VF_MEM_PREFETCH   0x03 /* VF Prefetchable Memory */

Definition at line 651 of file pcireg.h.

◆ PCIM_EA_PP

#define PCIM_EA_PP   0x0000ff00 /* Primary Properties */

Definition at line 644 of file pcireg.h.

◆ PCIM_EA_PP_OFFSET

#define PCIM_EA_PP_OFFSET   8

Definition at line 645 of file pcireg.h.

◆ PCIM_EA_SEC_NR

#define PCIM_EA_SEC_NR (   reg)    ((reg) & 0xff)

Definition at line 668 of file pcireg.h.

◆ PCIM_EA_SP

#define PCIM_EA_SP   0x00ff0000 /* Secondary Properties */

Definition at line 647 of file pcireg.h.

◆ PCIM_EA_SP_OFFSET

#define PCIM_EA_SP_OFFSET   16

Definition at line 646 of file pcireg.h.

◆ PCIM_EA_SUB_NR

#define PCIM_EA_SUB_NR (   reg)    (((reg) >> 8) & 0xff)

Definition at line 669 of file pcireg.h.

◆ PCIM_EA_WRITABLE

#define PCIM_EA_WRITABLE   0x40000000 /* Writable: 1 = RW, 0 = HwInit */

Definition at line 660 of file pcireg.h.

◆ PCIM_EXTCAP_ID

#define PCIM_EXTCAP_ID   0x0000ffff

Definition at line 159 of file pcireg.h.

◆ PCIM_EXTCAP_NEXTPTR

#define PCIM_EXTCAP_NEXTPTR   0xfff00000

Definition at line 161 of file pcireg.h.

◆ PCIM_EXTCAP_VER

#define PCIM_EXTCAP_VER   0x000f0000

Definition at line 160 of file pcireg.h.

◆ PCIM_HDRTYPE

#define PCIM_HDRTYPE   0x7f

Definition at line 117 of file pcireg.h.

◆ PCIM_HDRTYPE_BRIDGE

#define PCIM_HDRTYPE_BRIDGE   0x01

Definition at line 119 of file pcireg.h.

◆ PCIM_HDRTYPE_CARDBUS

#define PCIM_HDRTYPE_CARDBUS   0x02

Definition at line 120 of file pcireg.h.

◆ PCIM_HDRTYPE_NORMAL

#define PCIM_HDRTYPE_NORMAL   0x00

Definition at line 118 of file pcireg.h.

◆ PCIM_HTCAP_ADDRESS_MAPPING

#define PCIM_HTCAP_ADDRESS_MAPPING   0xa000 /* 10100 */

Definition at line 754 of file pcireg.h.

◆ PCIM_HTCAP_DIRECT_ROUTE

#define PCIM_HTCAP_DIRECT_ROUTE   0xb000 /* 10110 */

Definition at line 756 of file pcireg.h.

◆ PCIM_HTCAP_EXT_CONFIG_SPACE

#define PCIM_HTCAP_EXT_CONFIG_SPACE   0x9800 /* 10011 */

Definition at line 753 of file pcireg.h.

◆ PCIM_HTCAP_FLE

#define PCIM_HTCAP_FLE   0xd800 /* 11011 */

Definition at line 761 of file pcireg.h.

◆ PCIM_HTCAP_GEN3

#define PCIM_HTCAP_GEN3   0xd000 /* 11010 */

Definition at line 760 of file pcireg.h.

◆ PCIM_HTCAP_HIGH_NODE_COUNT

#define PCIM_HTCAP_HIGH_NODE_COUNT   0xe800 /* 11101 */

Definition at line 763 of file pcireg.h.

◆ PCIM_HTCAP_HOST

#define PCIM_HTCAP_HOST   0x2000 /* 001xx */

Definition at line 748 of file pcireg.h.

◆ PCIM_HTCAP_INTERRUPT

#define PCIM_HTCAP_INTERRUPT   0x8000 /* 10000 */

Definition at line 750 of file pcireg.h.

◆ PCIM_HTCAP_MSI_MAPPING

#define PCIM_HTCAP_MSI_MAPPING   0xa800 /* 10101 */

Definition at line 755 of file pcireg.h.

◆ PCIM_HTCAP_PM

#define PCIM_HTCAP_PM   0xe000 /* 11100 */

Definition at line 762 of file pcireg.h.

◆ PCIM_HTCAP_RETRY_MODE

#define PCIM_HTCAP_RETRY_MODE   0xc000 /* 11000 */

Definition at line 758 of file pcireg.h.

◆ PCIM_HTCAP_REVISION_ID

#define PCIM_HTCAP_REVISION_ID   0x8800 /* 10001 */

Definition at line 751 of file pcireg.h.

◆ PCIM_HTCAP_SLAVE

#define PCIM_HTCAP_SLAVE   0x0000 /* 000xx */

Definition at line 747 of file pcireg.h.

◆ PCIM_HTCAP_SWITCH

#define PCIM_HTCAP_SWITCH   0x4000 /* 01000 */

Definition at line 749 of file pcireg.h.

◆ PCIM_HTCAP_UNITID_CLUMPING

#define PCIM_HTCAP_UNITID_CLUMPING   0x9000 /* 10010 */

Definition at line 752 of file pcireg.h.

◆ PCIM_HTCAP_VCSET

#define PCIM_HTCAP_VCSET   0xb800 /* 10111 */

Definition at line 757 of file pcireg.h.

◆ PCIM_HTCAP_X86_ENCODING

#define PCIM_HTCAP_X86_ENCODING   0xc800 /* 11001 */

Definition at line 759 of file pcireg.h.

◆ PCIM_HTCMD_CAP_MASK

#define PCIM_HTCMD_CAP_MASK   0xf800 /* Capability type. */

Definition at line 746 of file pcireg.h.

◆ PCIM_HTCMD_MSI_ENABLE

#define PCIM_HTCMD_MSI_ENABLE   0x0001

Definition at line 766 of file pcireg.h.

◆ PCIM_HTCMD_MSI_FIXED

#define PCIM_HTCMD_MSI_FIXED   0x0002

Definition at line 767 of file pcireg.h.

◆ PCIM_MFDEV

#define PCIM_MFDEV   0x80

Definition at line 121 of file pcireg.h.

◆ PCIM_MSICTRL_64BIT

#define PCIM_MSICTRL_64BIT   0x0080

Definition at line 602 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_1

#define PCIM_MSICTRL_MMC_1   0x0000

Definition at line 611 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_16

#define PCIM_MSICTRL_MMC_16   0x0008

Definition at line 615 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_2

#define PCIM_MSICTRL_MMC_2   0x0002

Definition at line 612 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_32

#define PCIM_MSICTRL_MMC_32   0x000A

Definition at line 616 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_4

#define PCIM_MSICTRL_MMC_4   0x0004

Definition at line 613 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_8

#define PCIM_MSICTRL_MMC_8   0x0006

Definition at line 614 of file pcireg.h.

◆ PCIM_MSICTRL_MMC_MASK

#define PCIM_MSICTRL_MMC_MASK   0x000E

Definition at line 610 of file pcireg.h.

◆ PCIM_MSICTRL_MME_1

#define PCIM_MSICTRL_MME_1   0x0000

Definition at line 604 of file pcireg.h.

◆ PCIM_MSICTRL_MME_16

#define PCIM_MSICTRL_MME_16   0x0040

Definition at line 608 of file pcireg.h.

◆ PCIM_MSICTRL_MME_2

#define PCIM_MSICTRL_MME_2   0x0010

Definition at line 605 of file pcireg.h.

◆ PCIM_MSICTRL_MME_32

#define PCIM_MSICTRL_MME_32   0x0050

Definition at line 609 of file pcireg.h.

◆ PCIM_MSICTRL_MME_4

#define PCIM_MSICTRL_MME_4   0x0020

Definition at line 606 of file pcireg.h.

◆ PCIM_MSICTRL_MME_8

#define PCIM_MSICTRL_MME_8   0x0030

Definition at line 607 of file pcireg.h.

◆ PCIM_MSICTRL_MME_MASK

#define PCIM_MSICTRL_MME_MASK   0x0070

Definition at line 603 of file pcireg.h.

◆ PCIM_MSICTRL_MSI_ENABLE

#define PCIM_MSICTRL_MSI_ENABLE   0x0001

Definition at line 617 of file pcireg.h.

◆ PCIM_MSICTRL_VECTOR

#define PCIM_MSICTRL_VECTOR   0x0100

Definition at line 601 of file pcireg.h.

◆ PCIM_MSIX_BIR_BAR_10

#define PCIM_MSIX_BIR_BAR_10   0

Definition at line 970 of file pcireg.h.

◆ PCIM_MSIX_BIR_BAR_14

#define PCIM_MSIX_BIR_BAR_14   1

Definition at line 971 of file pcireg.h.

◆ PCIM_MSIX_BIR_BAR_18

#define PCIM_MSIX_BIR_BAR_18   2

Definition at line 972 of file pcireg.h.

◆ PCIM_MSIX_BIR_BAR_1C

#define PCIM_MSIX_BIR_BAR_1C   3

Definition at line 973 of file pcireg.h.

◆ PCIM_MSIX_BIR_BAR_20

#define PCIM_MSIX_BIR_BAR_20   4

Definition at line 974 of file pcireg.h.

◆ PCIM_MSIX_BIR_BAR_24

#define PCIM_MSIX_BIR_BAR_24   5

Definition at line 975 of file pcireg.h.

◆ PCIM_MSIX_BIR_MASK

#define PCIM_MSIX_BIR_MASK   0x7

Definition at line 969 of file pcireg.h.

◆ PCIM_MSIX_VCTRL_MASK

#define PCIM_MSIX_VCTRL_MASK   0x1

Definition at line 976 of file pcireg.h.

◆ PCIM_MSIXCTRL_FUNCTION_MASK

#define PCIM_MSIXCTRL_FUNCTION_MASK   0x4000

Definition at line 965 of file pcireg.h.

◆ PCIM_MSIXCTRL_MSIX_ENABLE

#define PCIM_MSIXCTRL_MSIX_ENABLE   0x8000

Definition at line 964 of file pcireg.h.

◆ PCIM_MSIXCTRL_TABLE_SIZE

#define PCIM_MSIXCTRL_TABLE_SIZE   0x07FF

Definition at line 966 of file pcireg.h.

◆ PCIM_OSC_CTL_PCIE_AER

#define PCIM_OSC_CTL_PCIE_AER   0x08 /* PCIe Advanced Error Reporting */

Definition at line 1099 of file pcireg.h.

◆ PCIM_OSC_CTL_PCIE_CAP_STRUCT

#define PCIM_OSC_CTL_PCIE_CAP_STRUCT   0x10 /* Various Capability Structures */

Definition at line 1100 of file pcireg.h.

◆ PCIM_OSC_CTL_PCIE_HP

#define PCIM_OSC_CTL_PCIE_HP   0x01 /* PCIe Native Hot Plug */

Definition at line 1096 of file pcireg.h.

◆ PCIM_OSC_CTL_PCIE_PME

#define PCIM_OSC_CTL_PCIE_PME   0x04 /* PCIe Native Power Mgt Events */

Definition at line 1098 of file pcireg.h.

◆ PCIM_OSC_CTL_SHPC_HP

#define PCIM_OSC_CTL_SHPC_HP   0x02 /* SHPC Native Hot Plug */

Definition at line 1097 of file pcireg.h.

◆ PCIM_OSC_SUPPORT_ASPM

#define PCIM_OSC_SUPPORT_ASPM   0x02 /* Active State Power Management */

Definition at line 1091 of file pcireg.h.

◆ PCIM_OSC_SUPPORT_CPMC

#define PCIM_OSC_SUPPORT_CPMC   0x04 /* Clock Power Management Cap */

Definition at line 1092 of file pcireg.h.

◆ PCIM_OSC_SUPPORT_EXT_PCI_CONF

#define PCIM_OSC_SUPPORT_EXT_PCI_CONF   0x01 /* Extended PCI Config Space */

Definition at line 1090 of file pcireg.h.

◆ PCIM_OSC_SUPPORT_MSI

#define PCIM_OSC_SUPPORT_MSI   0x10 /* MSI signalling supported */

Definition at line 1094 of file pcireg.h.

◆ PCIM_OSC_SUPPORT_SEG_GROUP

#define PCIM_OSC_SUPPORT_SEG_GROUP   0x08 /* PCI Segment Groups supported */

Definition at line 1093 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_0

#define PCIM_PCAP_AUXPWR_0   0x0000

Definition at line 547 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_100

#define PCIM_PCAP_AUXPWR_100   0x0080

Definition at line 549 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_160

#define PCIM_PCAP_AUXPWR_160   0x00c0

Definition at line 550 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_220

#define PCIM_PCAP_AUXPWR_220   0x0100

Definition at line 551 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_270

#define PCIM_PCAP_AUXPWR_270   0x0140

Definition at line 552 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_320

#define PCIM_PCAP_AUXPWR_320   0x0180

Definition at line 553 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_375

#define PCIM_PCAP_AUXPWR_375   0x01c0

Definition at line 554 of file pcireg.h.

◆ PCIM_PCAP_AUXPWR_55

#define PCIM_PCAP_AUXPWR_55   0x0040

Definition at line 548 of file pcireg.h.

◆ PCIM_PCAP_AUXPWRMASK

#define PCIM_PCAP_AUXPWRMASK   0x01c0

Definition at line 555 of file pcireg.h.

◆ PCIM_PCAP_D0PME

#define PCIM_PCAP_D0PME   0x0800

Definition at line 558 of file pcireg.h.

◆ PCIM_PCAP_D1PME

#define PCIM_PCAP_D1PME   0x1000

Definition at line 559 of file pcireg.h.

◆ PCIM_PCAP_D1SUPP

#define PCIM_PCAP_D1SUPP   0x0200

Definition at line 556 of file pcireg.h.

◆ PCIM_PCAP_D2PME

#define PCIM_PCAP_D2PME   0x2000

Definition at line 560 of file pcireg.h.

◆ PCIM_PCAP_D2SUPP

#define PCIM_PCAP_D2SUPP   0x0400

Definition at line 557 of file pcireg.h.

◆ PCIM_PCAP_D3PME_COLD

#define PCIM_PCAP_D3PME_COLD   0x8000

Definition at line 562 of file pcireg.h.

◆ PCIM_PCAP_D3PME_HOT

#define PCIM_PCAP_D3PME_HOT   0x4000

Definition at line 561 of file pcireg.h.

◆ PCIM_PCAP_DEVSPECINIT

#define PCIM_PCAP_DEVSPECINIT   0x0020

Definition at line 546 of file pcireg.h.

◆ PCIM_PCAP_PMEREQCLK

#define PCIM_PCAP_PMEREQCLK   0x0008

Definition at line 545 of file pcireg.h.

◆ PCIM_PCAP_SPEC

#define PCIM_PCAP_SPEC   0x0007

Definition at line 544 of file pcireg.h.

◆ PCIM_PCIAFCAP_FLR

#define PCIM_PCIAFCAP_FLR   0x02

Definition at line 981 of file pcireg.h.

◆ PCIM_PCIAFCAP_TP

#define PCIM_PCIAFCAP_TP   0x01

Definition at line 980 of file pcireg.h.

◆ PCIM_PMCSR_BSE_BPCCE

#define PCIM_PMCSR_BSE_BPCCE   0x80

Definition at line 591 of file pcireg.h.

◆ PCIM_PMCSR_BSE_D3B2

#define PCIM_PMCSR_BSE_D3B2   0x40

Definition at line 590 of file pcireg.h.

◆ PCIM_PMCSR_BSE_D3B3

#define PCIM_PMCSR_BSE_D3B3   0x00

Definition at line 589 of file pcireg.h.

◆ PCIM_PSTAT_D0

#define PCIM_PSTAT_D0   0x0000

Definition at line 565 of file pcireg.h.

◆ PCIM_PSTAT_D0HEAT

#define PCIM_PSTAT_D0HEAT   0x0800

Definition at line 576 of file pcireg.h.

◆ PCIM_PSTAT_D0POWER

#define PCIM_PSTAT_D0POWER   0x0000

Definition at line 572 of file pcireg.h.

◆ PCIM_PSTAT_D1

#define PCIM_PSTAT_D1   0x0001

Definition at line 566 of file pcireg.h.

◆ PCIM_PSTAT_D1HEAT

#define PCIM_PSTAT_D1HEAT   0x0a00

Definition at line 577 of file pcireg.h.

◆ PCIM_PSTAT_D1POWER

#define PCIM_PSTAT_D1POWER   0x0200

Definition at line 573 of file pcireg.h.

◆ PCIM_PSTAT_D2

#define PCIM_PSTAT_D2   0x0002

Definition at line 567 of file pcireg.h.

◆ PCIM_PSTAT_D2HEAT

#define PCIM_PSTAT_D2HEAT   0x0c00

Definition at line 578 of file pcireg.h.

◆ PCIM_PSTAT_D2POWER

#define PCIM_PSTAT_D2POWER   0x0400

Definition at line 574 of file pcireg.h.

◆ PCIM_PSTAT_D3

#define PCIM_PSTAT_D3   0x0003

Definition at line 568 of file pcireg.h.

◆ PCIM_PSTAT_D3HEAT

#define PCIM_PSTAT_D3HEAT   0x0e00

Definition at line 579 of file pcireg.h.

◆ PCIM_PSTAT_D3POWER

#define PCIM_PSTAT_D3POWER   0x0600

Definition at line 575 of file pcireg.h.

◆ PCIM_PSTAT_DATADIV10

#define PCIM_PSTAT_DATADIV10   0x2000

Definition at line 582 of file pcireg.h.

◆ PCIM_PSTAT_DATADIV100

#define PCIM_PSTAT_DATADIV100   0x4000

Definition at line 583 of file pcireg.h.

◆ PCIM_PSTAT_DATADIV1000

#define PCIM_PSTAT_DATADIV1000   0x6000

Definition at line 584 of file pcireg.h.

◆ PCIM_PSTAT_DATADIVMASK

#define PCIM_PSTAT_DATADIVMASK   0x6000

Definition at line 585 of file pcireg.h.

◆ PCIM_PSTAT_DATASELMASK

#define PCIM_PSTAT_DATASELMASK   0x1e00

Definition at line 580 of file pcireg.h.

◆ PCIM_PSTAT_DATAUNKN

#define PCIM_PSTAT_DATAUNKN   0x0000

Definition at line 581 of file pcireg.h.

◆ PCIM_PSTAT_DMASK

#define PCIM_PSTAT_DMASK   0x0003

Definition at line 569 of file pcireg.h.

◆ PCIM_PSTAT_NOSOFTRESET

#define PCIM_PSTAT_NOSOFTRESET   0x0008

Definition at line 570 of file pcireg.h.

◆ PCIM_PSTAT_PME

#define PCIM_PSTAT_PME   0x8000

Definition at line 586 of file pcireg.h.

◆ PCIM_PSTAT_PMEENABLE

#define PCIM_PSTAT_PMEENABLE   0x0100

Definition at line 571 of file pcireg.h.

◆ PCIM_SRIOV_ARI_EN

#define PCIM_SRIOV_ARI_EN   0x10

Definition at line 1064 of file pcireg.h.

◆ PCIM_SRIOV_VF_EN

#define PCIM_SRIOV_VF_EN   0x01

Definition at line 1062 of file pcireg.h.

◆ PCIM_SRIOV_VF_MSE

#define PCIM_SRIOV_VF_MSE   0x08 /* Memory space enable. */

Definition at line 1063 of file pcireg.h.

◆ PCIM_STATUS_66CAPABLE

#define PCIM_STATUS_66CAPABLE   0x0020

Definition at line 98 of file pcireg.h.

◆ PCIM_STATUS_BACKTOBACK

#define PCIM_STATUS_BACKTOBACK   0x0080

Definition at line 99 of file pcireg.h.

◆ PCIM_STATUS_CAPPRESENT

#define PCIM_STATUS_CAPPRESENT   0x0010

Definition at line 97 of file pcireg.h.

◆ PCIM_STATUS_INTxSTATE

#define PCIM_STATUS_INTxSTATE   0x0008

Definition at line 96 of file pcireg.h.

◆ PCIM_STATUS_MDPERR

#define PCIM_STATUS_MDPERR   0x0100

Definition at line 100 of file pcireg.h.

◆ PCIM_STATUS_PERR

#define PCIM_STATUS_PERR   0x8000

Definition at line 109 of file pcireg.h.

◆ PCIM_STATUS_RMABORT

#define PCIM_STATUS_RMABORT   0x2000

Definition at line 107 of file pcireg.h.

◆ PCIM_STATUS_RTABORT

#define PCIM_STATUS_RTABORT   0x1000

Definition at line 106 of file pcireg.h.

◆ PCIM_STATUS_SEL_FAST

#define PCIM_STATUS_SEL_FAST   0x0000

Definition at line 101 of file pcireg.h.

◆ PCIM_STATUS_SEL_MASK

#define PCIM_STATUS_SEL_MASK   0x0600

Definition at line 104 of file pcireg.h.

◆ PCIM_STATUS_SEL_MEDIMUM

#define PCIM_STATUS_SEL_MEDIMUM   0x0200

Definition at line 102 of file pcireg.h.

◆ PCIM_STATUS_SEL_SLOW

#define PCIM_STATUS_SEL_SLOW   0x0400

Definition at line 103 of file pcireg.h.

◆ PCIM_STATUS_SERR

#define PCIM_STATUS_SERR   0x4000

Definition at line 108 of file pcireg.h.

◆ PCIM_STATUS_STABORT

#define PCIM_STATUS_STABORT   0x0800

Definition at line 105 of file pcireg.h.

◆ PCIM_VC_CAP1_EXT_COUNT

#define PCIM_VC_CAP1_EXT_COUNT   0x00000007

Definition at line 1047 of file pcireg.h.

◆ PCIM_VC_CAP1_LOWPRI_EXT_COUNT

#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT   0x00000070

Definition at line 1048 of file pcireg.h.

◆ PCIP_BASEPERIPH_PIC_8259A

#define PCIP_BASEPERIPH_PIC_8259A   0x00

Definition at line 422 of file pcireg.h.

◆ PCIP_BASEPERIPH_PIC_EISA

#define PCIP_BASEPERIPH_PIC_EISA   0x02

Definition at line 424 of file pcireg.h.

◆ PCIP_BASEPERIPH_PIC_IO_APIC

#define PCIP_BASEPERIPH_PIC_IO_APIC   0x10

Definition at line 425 of file pcireg.h.

◆ PCIP_BASEPERIPH_PIC_IOX_APIC

#define PCIP_BASEPERIPH_PIC_IOX_APIC   0x20

Definition at line 426 of file pcireg.h.

◆ PCIP_BASEPERIPH_PIC_ISA

#define PCIP_BASEPERIPH_PIC_ISA   0x01

Definition at line 423 of file pcireg.h.

◆ PCIP_BRIDGE_PCI_SUBTRACTIVE

#define PCIP_BRIDGE_PCI_SUBTRACTIVE   0x01

Definition at line 393 of file pcireg.h.

◆ PCIP_MULTIMEDIA_HDA_VENDOR

#define PCIP_MULTIMEDIA_HDA_VENDOR   0x01

Definition at line 379 of file pcireg.h.

◆ PCIP_SERIALBUS_IPMI_BT

#define PCIP_SERIALBUS_IPMI_BT   0x02

Definition at line 473 of file pcireg.h.

◆ PCIP_SERIALBUS_IPMI_KCS

#define PCIP_SERIALBUS_IPMI_KCS   0x01

Definition at line 472 of file pcireg.h.

◆ PCIP_SERIALBUS_IPMI_SMIC

#define PCIP_SERIALBUS_IPMI_SMIC   0x00

Definition at line 471 of file pcireg.h.

◆ PCIP_SERIALBUS_USB_DEVICE

#define PCIP_SERIALBUS_USB_DEVICE   0xfe

Definition at line 466 of file pcireg.h.

◆ PCIP_SERIALBUS_USB_EHCI

#define PCIP_SERIALBUS_USB_EHCI   0x20

Definition at line 464 of file pcireg.h.

◆ PCIP_SERIALBUS_USB_OHCI

#define PCIP_SERIALBUS_USB_OHCI   0x10

Definition at line 463 of file pcireg.h.

◆ PCIP_SERIALBUS_USB_UHCI

#define PCIP_SERIALBUS_USB_UHCI   0x00

Definition at line 462 of file pcireg.h.

◆ PCIP_SERIALBUS_USB_XHCI

#define PCIP_SERIALBUS_USB_XHCI   0x30

Definition at line 465 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_16450A

#define PCIP_SIMPLECOMM_UART_16450A   0x01

Definition at line 407 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_16550A

#define PCIP_SIMPLECOMM_UART_16550A   0x02

Definition at line 408 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_16650A

#define PCIP_SIMPLECOMM_UART_16650A   0x03

Definition at line 409 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_16750A

#define PCIP_SIMPLECOMM_UART_16750A   0x04

Definition at line 410 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_16850A

#define PCIP_SIMPLECOMM_UART_16850A   0x05

Definition at line 411 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_16950A

#define PCIP_SIMPLECOMM_UART_16950A   0x06

Definition at line 412 of file pcireg.h.

◆ PCIP_SIMPLECOMM_UART_8250

#define PCIP_SIMPLECOMM_UART_8250   0x00

Definition at line 406 of file pcireg.h.

◆ PCIP_STORAGE_IDE_MASTERDEV

#define PCIP_STORAGE_IDE_MASTERDEV   0x80

Definition at line 341 of file pcireg.h.

◆ PCIP_STORAGE_IDE_MODEPRIM

#define PCIP_STORAGE_IDE_MODEPRIM   0x01

Definition at line 337 of file pcireg.h.

◆ PCIP_STORAGE_IDE_MODESEC

#define PCIP_STORAGE_IDE_MODESEC   0x04

Definition at line 339 of file pcireg.h.

◆ PCIP_STORAGE_IDE_PROGINDPRIM

#define PCIP_STORAGE_IDE_PROGINDPRIM   0x02

Definition at line 338 of file pcireg.h.

◆ PCIP_STORAGE_IDE_PROGINDSEC

#define PCIP_STORAGE_IDE_PROGINDSEC   0x08

Definition at line 340 of file pcireg.h.

◆ PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0

#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0   0x02

Definition at line 351 of file pcireg.h.

◆ PCIP_STORAGE_NVM_NVMHCI_1_0

#define PCIP_STORAGE_NVM_NVMHCI_1_0   0x01

Definition at line 350 of file pcireg.h.

◆ PCIP_STORAGE_SATA_AHCI_1_0

#define PCIP_STORAGE_SATA_AHCI_1_0   0x01

Definition at line 347 of file pcireg.h.

◆ PCIP_STORAGE_UFS_UFSHCI_1_0

#define PCIP_STORAGE_UFS_UFSHCI_1_0   0x01

Definition at line 353 of file pcireg.h.

◆ PCIR_AER_CAP_CONTROL

#define PCIR_AER_CAP_CONTROL   0x18

Definition at line 1018 of file pcireg.h.

◆ PCIR_AER_COR_MASK

#define PCIR_AER_COR_MASK   0x14 /* Shares bits with COR_STATUS */

Definition at line 1017 of file pcireg.h.

◆ PCIR_AER_COR_SOURCE_ID

#define PCIR_AER_COR_SOURCE_ID   0x34 /* Only for root complex ports */

Definition at line 1041 of file pcireg.h.

◆ PCIR_AER_COR_STATUS

#define PCIR_AER_COR_STATUS   0x10

Definition at line 1008 of file pcireg.h.

◆ PCIR_AER_ERR_SOURCE_ID

#define PCIR_AER_ERR_SOURCE_ID   0x36 /* Only for root complex ports */

Definition at line 1042 of file pcireg.h.

◆ PCIR_AER_HEADER_LOG

#define PCIR_AER_HEADER_LOG   0x1c

Definition at line 1027 of file pcireg.h.

◆ PCIR_AER_ROOTERR_CMD

#define PCIR_AER_ROOTERR_CMD   0x2c /* Only for root complex ports */

Definition at line 1028 of file pcireg.h.

◆ PCIR_AER_ROOTERR_STATUS

#define PCIR_AER_ROOTERR_STATUS   0x30 /* Only for root complex ports */

Definition at line 1032 of file pcireg.h.

◆ PCIR_AER_TLP_PREFIX_LOG

#define PCIR_AER_TLP_PREFIX_LOG   0x38 /* Only for TLP prefix functions */

Definition at line 1043 of file pcireg.h.

◆ PCIR_AER_UC_MASK

#define PCIR_AER_UC_MASK   0x08 /* Shares bits with UC_STATUS */

Definition at line 1006 of file pcireg.h.

◆ PCIR_AER_UC_SEVERITY

#define PCIR_AER_UC_SEVERITY   0x0c /* Shares bits with UC_STATUS */

Definition at line 1007 of file pcireg.h.

◆ PCIR_AER_UC_STATUS

#define PCIR_AER_UC_STATUS   0x04

Definition at line 988 of file pcireg.h.

◆ PCIR_BAR

#define PCIR_BAR (   x)    (PCIR_BARS + (x) * 4)

Definition at line 216 of file pcireg.h.

◆ PCIR_BARS

#define PCIR_BARS   0x10

Definition at line 215 of file pcireg.h.

◆ PCIR_BIOS

#define PCIR_BIOS   0x30

Definition at line 247 of file pcireg.h.

◆ PCIR_BIOS_1

#define PCIR_BIOS_1   0x38

Definition at line 285 of file pcireg.h.

◆ PCIR_BIST

#define PCIR_BIST   0x0f

Definition at line 122 of file pcireg.h.

◆ PCIR_BRIDGECTL_1

#define PCIR_BRIDGECTL_1   0x3e

Definition at line 286 of file pcireg.h.

◆ PCIR_BRIDGECTL_2

#define PCIR_BRIDGECTL_2   0x3e

Definition at line 316 of file pcireg.h.

◆ PCIR_CACHELNSZ

#define PCIR_CACHELNSZ   0x0c

Definition at line 114 of file pcireg.h.

◆ PCIR_CAP_PTR

#define PCIR_CAP_PTR   0x34

Definition at line 250 of file pcireg.h.

◆ PCIR_CAP_PTR_2

#define PCIR_CAP_PTR_2   0x14

Definition at line 296 of file pcireg.h.

◆ PCIR_CIS

#define PCIR_CIS   0x28

Definition at line 232 of file pcireg.h.

◆ PCIR_CLASS

#define PCIR_CLASS   0x0b

Definition at line 113 of file pcireg.h.

◆ PCIR_COMMAND

#define PCIR_COMMAND   0x04

Definition at line 85 of file pcireg.h.

◆ PCIR_DEBUG_PORT

#define PCIR_DEBUG_PORT   0x2

Definition at line 779 of file pcireg.h.

◆ PCIR_DEVICE

#define PCIR_DEVICE   0x02

Definition at line 84 of file pcireg.h.

◆ PCIR_DEVICE_LENGTH

#define PCIR_DEVICE_LENGTH   0x2

Definition at line 776 of file pcireg.h.

◆ PCIR_DEVVENDOR

#define PCIR_DEVVENDOR   0x00

Definition at line 82 of file pcireg.h.

◆ PCIR_EA_FIRST_ENT

#define PCIR_EA_FIRST_ENT   4 /* First EA Entry in List */

Definition at line 628 of file pcireg.h.

◆ PCIR_EA_FIRST_ENT_BRIDGE

#define PCIR_EA_FIRST_ENT_BRIDGE   8 /* First EA Entry for Bridges */

Definition at line 629 of file pcireg.h.

◆ PCIR_EA_NUM_ENT

#define PCIR_EA_NUM_ENT   2 /* Number of Capability Entries */

Definition at line 626 of file pcireg.h.

◆ PCIR_EXTCAP

#define PCIR_EXTCAP   0x100

Definition at line 158 of file pcireg.h.

◆ PCIR_HDRTYPE

#define PCIR_HDRTYPE   0x0e

Definition at line 116 of file pcireg.h.

◆ PCIR_HT_COMMAND

#define PCIR_HT_COMMAND   0x2

Definition at line 745 of file pcireg.h.

◆ PCIR_HTMSI_ADDRESS_HI

#define PCIR_HTMSI_ADDRESS_HI   0x8

Definition at line 769 of file pcireg.h.

◆ PCIR_HTMSI_ADDRESS_LO

#define PCIR_HTMSI_ADDRESS_LO   0x4

Definition at line 768 of file pcireg.h.

◆ PCIR_INTLINE

#define PCIR_INTLINE   0x3c

Definition at line 251 of file pcireg.h.

◆ PCIR_INTPIN

#define PCIR_INTPIN   0x3d

Definition at line 252 of file pcireg.h.

◆ PCIR_IOBASE0_2

#define PCIR_IOBASE0_2   0x2c

Definition at line 308 of file pcireg.h.

◆ PCIR_IOBASE1_2

#define PCIR_IOBASE1_2   0x34

Definition at line 310 of file pcireg.h.

◆ PCIR_IOBASEH_1

#define PCIR_IOBASEH_1   0x30

Definition at line 268 of file pcireg.h.

◆ PCIR_IOBASEL_1

#define PCIR_IOBASEL_1   0x1c

Definition at line 266 of file pcireg.h.

◆ PCIR_IOLIMIT0_2

#define PCIR_IOLIMIT0_2   0x30

Definition at line 309 of file pcireg.h.

◆ PCIR_IOLIMIT1_2

#define PCIR_IOLIMIT1_2   0x38

Definition at line 311 of file pcireg.h.

◆ PCIR_IOLIMITH_1

#define PCIR_IOLIMITH_1   0x32

Definition at line 269 of file pcireg.h.

◆ PCIR_IOLIMITL_1

#define PCIR_IOLIMITL_1   0x1d

Definition at line 267 of file pcireg.h.

◆ PCIR_LATTIMER

#define PCIR_LATTIMER   0x0d

Definition at line 115 of file pcireg.h.

◆ PCIR_MAX_BAR_0

#define PCIR_MAX_BAR_0   5

Definition at line 217 of file pcireg.h.

◆ PCIR_MAX_BAR_1

#define PCIR_MAX_BAR_1   1

Definition at line 258 of file pcireg.h.

◆ PCIR_MAX_BAR_2

#define PCIR_MAX_BAR_2   0

Definition at line 295 of file pcireg.h.

◆ PCIR_MAXLAT

#define PCIR_MAXLAT   0x3f

Definition at line 254 of file pcireg.h.

◆ PCIR_MEMBASE0_2

#define PCIR_MEMBASE0_2   0x1c

Definition at line 304 of file pcireg.h.

◆ PCIR_MEMBASE1_2

#define PCIR_MEMBASE1_2   0x24

Definition at line 306 of file pcireg.h.

◆ PCIR_MEMBASE_1

#define PCIR_MEMBASE_1   0x20

Definition at line 274 of file pcireg.h.

◆ PCIR_MEMLIMIT0_2

#define PCIR_MEMLIMIT0_2   0x20

Definition at line 305 of file pcireg.h.

◆ PCIR_MEMLIMIT1_2

#define PCIR_MEMLIMIT1_2   0x28

Definition at line 307 of file pcireg.h.

◆ PCIR_MEMLIMIT_1

#define PCIR_MEMLIMIT_1   0x22

Definition at line 275 of file pcireg.h.

◆ PCIR_MINGNT

#define PCIR_MINGNT   0x3e

Definition at line 253 of file pcireg.h.

◆ PCIR_MSI_ADDR

#define PCIR_MSI_ADDR   0x4

Definition at line 618 of file pcireg.h.

◆ PCIR_MSI_ADDR_HIGH

#define PCIR_MSI_ADDR_HIGH   0x8

Definition at line 619 of file pcireg.h.

◆ PCIR_MSI_CTRL

#define PCIR_MSI_CTRL   0x2

Definition at line 600 of file pcireg.h.

◆ PCIR_MSI_DATA

#define PCIR_MSI_DATA   0x8

Definition at line 620 of file pcireg.h.

◆ PCIR_MSI_DATA_64BIT

#define PCIR_MSI_DATA_64BIT   0xc

Definition at line 621 of file pcireg.h.

◆ PCIR_MSI_MASK

#define PCIR_MSI_MASK   0x10

Definition at line 622 of file pcireg.h.

◆ PCIR_MSI_PENDING

#define PCIR_MSI_PENDING   0x14

Definition at line 623 of file pcireg.h.

◆ PCIR_MSIX_CTRL

#define PCIR_MSIX_CTRL   0x2

Definition at line 963 of file pcireg.h.

◆ PCIR_MSIX_PBA

#define PCIR_MSIX_PBA   0x8

Definition at line 968 of file pcireg.h.

◆ PCIR_MSIX_TABLE

#define PCIR_MSIX_TABLE   0x4

Definition at line 967 of file pcireg.h.

◆ PCIR_PCCARDIF_2

#define PCIR_PCCARDIF_2   0x44

Definition at line 321 of file pcireg.h.

◆ PCIR_PCIAF_CAP

#define PCIR_PCIAF_CAP   0x3

Definition at line 979 of file pcireg.h.

◆ PCIR_PCIAF_CTRL

#define PCIR_PCIAF_CTRL   0x4

Definition at line 982 of file pcireg.h.

◆ PCIR_PCIAF_STATUS

#define PCIR_PCIAF_STATUS   0x5

Definition at line 984 of file pcireg.h.

◆ PCIR_PCIAFCTRL_FLR

#define PCIR_PCIAFCTRL_FLR   0x01

Definition at line 983 of file pcireg.h.

◆ PCIR_PCIAFSTATUS_TP

#define PCIR_PCIAFSTATUS_TP   0x01

Definition at line 985 of file pcireg.h.

◆ PCIR_PMBASEH_1

#define PCIR_PMBASEH_1   0x28

Definition at line 279 of file pcireg.h.

◆ PCIR_PMBASEL_1

#define PCIR_PMBASEL_1   0x24

Definition at line 277 of file pcireg.h.

◆ PCIR_PMLIMITH_1

#define PCIR_PMLIMITH_1   0x2c

Definition at line 280 of file pcireg.h.

◆ PCIR_PMLIMITL_1

#define PCIR_PMLIMITL_1   0x26

Definition at line 278 of file pcireg.h.

◆ PCIR_POWER_BSE

#define PCIR_POWER_BSE   0x6

Definition at line 588 of file pcireg.h.

◆ PCIR_POWER_CAP

#define PCIR_POWER_CAP   0x2

Definition at line 543 of file pcireg.h.

◆ PCIR_POWER_DATA

#define PCIR_POWER_DATA   0x7

Definition at line 593 of file pcireg.h.

◆ PCIR_POWER_STATUS

#define PCIR_POWER_STATUS   0x4

Definition at line 564 of file pcireg.h.

◆ PCIR_PRIBUS_1

#define PCIR_PRIBUS_1   0x18

Definition at line 261 of file pcireg.h.

◆ PCIR_PRIBUS_2

#define PCIR_PRIBUS_2   0x18

Definition at line 299 of file pcireg.h.

◆ PCIR_PROGIF

#define PCIR_PROGIF   0x09

Definition at line 111 of file pcireg.h.

◆ PCIR_REVID

#define PCIR_REVID   0x08

Definition at line 110 of file pcireg.h.

◆ PCIR_SECBUS_1

#define PCIR_SECBUS_1   0x19

Definition at line 262 of file pcireg.h.

◆ PCIR_SECBUS_2

#define PCIR_SECBUS_2   0x19

Definition at line 300 of file pcireg.h.

◆ PCIR_SECLAT_1

#define PCIR_SECLAT_1   0x1b

Definition at line 264 of file pcireg.h.

◆ PCIR_SECLAT_2

#define PCIR_SECLAT_2   0x1b

Definition at line 302 of file pcireg.h.

◆ PCIR_SECSTAT_1

#define PCIR_SECSTAT_1   0x1e

Definition at line 259 of file pcireg.h.

◆ PCIR_SECSTAT_2

#define PCIR_SECSTAT_2   0x16

Definition at line 297 of file pcireg.h.

◆ PCIR_SERIAL_HIGH

#define PCIR_SERIAL_HIGH   0x08

Definition at line 1058 of file pcireg.h.

◆ PCIR_SERIAL_LOW

#define PCIR_SERIAL_LOW   0x04

Definition at line 1057 of file pcireg.h.

◆ PCIR_SRIOV_BAR

#define PCIR_SRIOV_BAR (   x)    (PCIR_SRIOV_BARS + (x) * 4)

Definition at line 1076 of file pcireg.h.

◆ PCIR_SRIOV_BARS

#define PCIR_SRIOV_BARS   0x24

Definition at line 1075 of file pcireg.h.

◆ PCIR_SRIOV_CTL

#define PCIR_SRIOV_CTL   0x08

Definition at line 1061 of file pcireg.h.

◆ PCIR_SRIOV_NUM_VFS

#define PCIR_SRIOV_NUM_VFS   0x10

Definition at line 1066 of file pcireg.h.

◆ PCIR_SRIOV_PAGE_CAP

#define PCIR_SRIOV_PAGE_CAP   0x1C

Definition at line 1070 of file pcireg.h.

◆ PCIR_SRIOV_PAGE_SIZE

#define PCIR_SRIOV_PAGE_SIZE   0x20

Definition at line 1071 of file pcireg.h.

◆ PCIR_SRIOV_TOTAL_VFS

#define PCIR_SRIOV_TOTAL_VFS   0x0E

Definition at line 1065 of file pcireg.h.

◆ PCIR_SRIOV_VF_DID

#define PCIR_SRIOV_VF_DID   0x1A

Definition at line 1069 of file pcireg.h.

◆ PCIR_SRIOV_VF_OFF

#define PCIR_SRIOV_VF_OFF   0x14

Definition at line 1067 of file pcireg.h.

◆ PCIR_SRIOV_VF_STRIDE

#define PCIR_SRIOV_VF_STRIDE   0x16

Definition at line 1068 of file pcireg.h.

◆ PCIR_STATUS

#define PCIR_STATUS   0x06

Definition at line 95 of file pcireg.h.

◆ PCIR_SUBBUS_1

#define PCIR_SUBBUS_1   0x1a

Definition at line 263 of file pcireg.h.

◆ PCIR_SUBBUS_2

#define PCIR_SUBBUS_2   0x1a

Definition at line 301 of file pcireg.h.

◆ PCIR_SUBCLASS

#define PCIR_SUBCLASS   0x0a

Definition at line 112 of file pcireg.h.

◆ PCIR_SUBDEV_0

#define PCIR_SUBDEV_0   0x2e

Definition at line 246 of file pcireg.h.

◆ PCIR_SUBDEV_2

#define PCIR_SUBDEV_2   0x42

Definition at line 319 of file pcireg.h.

◆ PCIR_SUBVEND_0

#define PCIR_SUBVEND_0   0x2c

Definition at line 245 of file pcireg.h.

◆ PCIR_SUBVEND_2

#define PCIR_SUBVEND_2   0x40

Definition at line 318 of file pcireg.h.

◆ PCIR_SUBVENDCAP_ID

#define PCIR_SUBVENDCAP_ID   0x4

Definition at line 784 of file pcireg.h.

◆ PCIR_VC_CAP1

#define PCIR_VC_CAP1   0x04

Definition at line 1046 of file pcireg.h.

◆ PCIR_VC_CAP2

#define PCIR_VC_CAP2   0x08

Definition at line 1049 of file pcireg.h.

◆ PCIR_VC_CONTROL

#define PCIR_VC_CONTROL   0x0C

Definition at line 1050 of file pcireg.h.

◆ PCIR_VC_RESOURCE_CAP

#define PCIR_VC_RESOURCE_CAP (   n)    (0x10 + (n) * 0x0C)

Definition at line 1052 of file pcireg.h.

◆ PCIR_VC_RESOURCE_CTL

#define PCIR_VC_RESOURCE_CTL (   n)    (0x14 + (n) * 0x0C)

Definition at line 1053 of file pcireg.h.

◆ PCIR_VC_RESOURCE_STA

#define PCIR_VC_RESOURCE_STA (   n)    (0x18 + (n) * 0x0C)

Definition at line 1054 of file pcireg.h.

◆ PCIR_VC_STATUS

#define PCIR_VC_STATUS   0x0E

Definition at line 1051 of file pcireg.h.

◆ PCIR_VENDOR

#define PCIR_VENDOR   0x00

Definition at line 83 of file pcireg.h.

◆ PCIR_VENDOR_DATA

#define PCIR_VENDOR_DATA   0x3

Definition at line 773 of file pcireg.h.

◆ PCIR_VENDOR_LENGTH

#define PCIR_VENDOR_LENGTH   0x2

Definition at line 772 of file pcireg.h.

◆ PCIR_VPD_ADDR

#define PCIR_VPD_ADDR   0x2

Definition at line 596 of file pcireg.h.

◆ PCIR_VPD_DATA

#define PCIR_VPD_DATA   0x4

Definition at line 597 of file pcireg.h.

◆ PCIR_VSEC_DATA

#define PCIR_VSEC_DATA   0x08

Definition at line 1083 of file pcireg.h.

◆ PCIR_VSEC_HEADER

#define PCIR_VSEC_HEADER   0x04

Definition at line 1079 of file pcireg.h.

◆ PCIR_VSEC_ID

#define PCIR_VSEC_ID (   hdr)    ((hdr) & 0xffff)

Definition at line 1080 of file pcireg.h.

◆ PCIR_VSEC_LENGTH

#define PCIR_VSEC_LENGTH (   hdr)    (((hdr) & 0xfff00000) >> 20)

Definition at line 1082 of file pcireg.h.

◆ PCIR_VSEC_REV

#define PCIR_VSEC_REV (   hdr)    (((hdr) & 0xf0000) >> 16)

Definition at line 1081 of file pcireg.h.

◆ PCIS_ACCEL_PROCESSING

#define PCIS_ACCEL_PROCESSING   0x00

Definition at line 512 of file pcireg.h.

◆ PCIS_BASEPERIPH_DMA

#define PCIS_BASEPERIPH_DMA   0x01

Definition at line 427 of file pcireg.h.

◆ PCIS_BASEPERIPH_IOMMU

#define PCIS_BASEPERIPH_IOMMU   0x06

Definition at line 432 of file pcireg.h.

◆ PCIS_BASEPERIPH_OTHER

#define PCIS_BASEPERIPH_OTHER   0x80

Definition at line 434 of file pcireg.h.

◆ PCIS_BASEPERIPH_PCIHOT

#define PCIS_BASEPERIPH_PCIHOT   0x04

Definition at line 430 of file pcireg.h.

◆ PCIS_BASEPERIPH_PIC

#define PCIS_BASEPERIPH_PIC   0x00

Definition at line 421 of file pcireg.h.

◆ PCIS_BASEPERIPH_RCEC

#define PCIS_BASEPERIPH_RCEC   0x07

Definition at line 433 of file pcireg.h.

◆ PCIS_BASEPERIPH_RTC

#define PCIS_BASEPERIPH_RTC   0x03

Definition at line 429 of file pcireg.h.

◆ PCIS_BASEPERIPH_SDHC

#define PCIS_BASEPERIPH_SDHC   0x05

Definition at line 431 of file pcireg.h.

◆ PCIS_BASEPERIPH_TIMER

#define PCIS_BASEPERIPH_TIMER   0x02

Definition at line 428 of file pcireg.h.

◆ PCIS_BRIDGE_AS_PCI

#define PCIS_BRIDGE_AS_PCI   0x0b

Definition at line 400 of file pcireg.h.

◆ PCIS_BRIDGE_AS_PCI_ASI_SIG

#define PCIS_BRIDGE_AS_PCI_ASI_SIG   0x01

Definition at line 401 of file pcireg.h.

◆ PCIS_BRIDGE_CARDBUS

#define PCIS_BRIDGE_CARDBUS   0x07

Definition at line 396 of file pcireg.h.

◆ PCIS_BRIDGE_EISA

#define PCIS_BRIDGE_EISA   0x02

Definition at line 390 of file pcireg.h.

◆ PCIS_BRIDGE_HOST

#define PCIS_BRIDGE_HOST   0x00

Definition at line 388 of file pcireg.h.

◆ PCIS_BRIDGE_INFINIBAND

#define PCIS_BRIDGE_INFINIBAND   0x0a

Definition at line 399 of file pcireg.h.

◆ PCIS_BRIDGE_ISA

#define PCIS_BRIDGE_ISA   0x01

Definition at line 389 of file pcireg.h.

◆ PCIS_BRIDGE_MCA

#define PCIS_BRIDGE_MCA   0x03

Definition at line 391 of file pcireg.h.

◆ PCIS_BRIDGE_NUBUS

#define PCIS_BRIDGE_NUBUS   0x06

Definition at line 395 of file pcireg.h.

◆ PCIS_BRIDGE_OTHER

#define PCIS_BRIDGE_OTHER   0x80

Definition at line 402 of file pcireg.h.

◆ PCIS_BRIDGE_PCI

#define PCIS_BRIDGE_PCI   0x04

Definition at line 392 of file pcireg.h.

◆ PCIS_BRIDGE_PCI_TRANSPARENT

#define PCIS_BRIDGE_PCI_TRANSPARENT   0x09

Definition at line 398 of file pcireg.h.

◆ PCIS_BRIDGE_PCMCIA

#define PCIS_BRIDGE_PCMCIA   0x05

Definition at line 394 of file pcireg.h.

◆ PCIS_BRIDGE_RACEWAY

#define PCIS_BRIDGE_RACEWAY   0x08

Definition at line 397 of file pcireg.h.

◆ PCIS_CRYPTO_ENTERTAIN

#define PCIS_CRYPTO_ENTERTAIN   0x10

Definition at line 501 of file pcireg.h.

◆ PCIS_CRYPTO_NETCOMP

#define PCIS_CRYPTO_NETCOMP   0x00

Definition at line 500 of file pcireg.h.

◆ PCIS_CRYPTO_OTHER

#define PCIS_CRYPTO_OTHER   0x80

Definition at line 502 of file pcireg.h.

◆ PCIS_DASP_COMM_SYNC

#define PCIS_DASP_COMM_SYNC   0x10

Definition at line 507 of file pcireg.h.

◆ PCIS_DASP_DPIO

#define PCIS_DASP_DPIO   0x00

Definition at line 505 of file pcireg.h.

◆ PCIS_DASP_MGMT_CARD

#define PCIS_DASP_MGMT_CARD   0x20

Definition at line 508 of file pcireg.h.

◆ PCIS_DASP_OTHER

#define PCIS_DASP_OTHER   0x80

Definition at line 509 of file pcireg.h.

◆ PCIS_DASP_PERFCNTRS

#define PCIS_DASP_PERFCNTRS   0x01

Definition at line 506 of file pcireg.h.

◆ PCIS_DISPLAY_3D

#define PCIS_DISPLAY_3D   0x02

Definition at line 371 of file pcireg.h.

◆ PCIS_DISPLAY_OTHER

#define PCIS_DISPLAY_OTHER   0x80

Definition at line 372 of file pcireg.h.

◆ PCIS_DISPLAY_VGA

#define PCIS_DISPLAY_VGA   0x00

Definition at line 369 of file pcireg.h.

◆ PCIS_DISPLAY_XGA

#define PCIS_DISPLAY_XGA   0x01

Definition at line 370 of file pcireg.h.

◆ PCIS_DOCKING_GENERIC

#define PCIS_DOCKING_GENERIC   0x00

Definition at line 445 of file pcireg.h.

◆ PCIS_DOCKING_OTHER

#define PCIS_DOCKING_OTHER   0x80

Definition at line 446 of file pcireg.h.

◆ PCIS_INPUTDEV_DIGITIZER

#define PCIS_INPUTDEV_DIGITIZER   0x01

Definition at line 438 of file pcireg.h.

◆ PCIS_INPUTDEV_GAMEPORT

#define PCIS_INPUTDEV_GAMEPORT   0x04

Definition at line 441 of file pcireg.h.

◆ PCIS_INPUTDEV_KEYBOARD

#define PCIS_INPUTDEV_KEYBOARD   0x00

Definition at line 437 of file pcireg.h.

◆ PCIS_INPUTDEV_MOUSE

#define PCIS_INPUTDEV_MOUSE   0x02

Definition at line 439 of file pcireg.h.

◆ PCIS_INPUTDEV_OTHER

#define PCIS_INPUTDEV_OTHER   0x80

Definition at line 442 of file pcireg.h.

◆ PCIS_INPUTDEV_SCANNER

#define PCIS_INPUTDEV_SCANNER   0x03

Definition at line 440 of file pcireg.h.

◆ PCIS_INTELLIIO_I2O

#define PCIS_INTELLIIO_I2O   0x00

Definition at line 491 of file pcireg.h.

◆ PCIS_MEMORY_FLASH

#define PCIS_MEMORY_FLASH   0x01

Definition at line 384 of file pcireg.h.

◆ PCIS_MEMORY_OTHER

#define PCIS_MEMORY_OTHER   0x80

Definition at line 385 of file pcireg.h.

◆ PCIS_MEMORY_RAM

#define PCIS_MEMORY_RAM   0x00

Definition at line 383 of file pcireg.h.

◆ PCIS_MULTIMEDIA_AUDIO

#define PCIS_MULTIMEDIA_AUDIO   0x01

Definition at line 376 of file pcireg.h.

◆ PCIS_MULTIMEDIA_HDA

#define PCIS_MULTIMEDIA_HDA   0x03

Definition at line 378 of file pcireg.h.

◆ PCIS_MULTIMEDIA_OTHER

#define PCIS_MULTIMEDIA_OTHER   0x80

Definition at line 380 of file pcireg.h.

◆ PCIS_MULTIMEDIA_TELE

#define PCIS_MULTIMEDIA_TELE   0x02

Definition at line 377 of file pcireg.h.

◆ PCIS_MULTIMEDIA_VIDEO

#define PCIS_MULTIMEDIA_VIDEO   0x00

Definition at line 375 of file pcireg.h.

◆ PCIS_NETWORK_ATM

#define PCIS_NETWORK_ATM   0x03

Definition at line 360 of file pcireg.h.

◆ PCIS_NETWORK_ETHERNET

#define PCIS_NETWORK_ETHERNET   0x00

Definition at line 357 of file pcireg.h.

◆ PCIS_NETWORK_FDDI

#define PCIS_NETWORK_FDDI   0x02

Definition at line 359 of file pcireg.h.

◆ PCIS_NETWORK_HFC

#define PCIS_NETWORK_HFC   0x08

Definition at line 365 of file pcireg.h.

◆ PCIS_NETWORK_INFINIBAND

#define PCIS_NETWORK_INFINIBAND   0x07

Definition at line 364 of file pcireg.h.

◆ PCIS_NETWORK_ISDN

#define PCIS_NETWORK_ISDN   0x04

Definition at line 361 of file pcireg.h.

◆ PCIS_NETWORK_OTHER

#define PCIS_NETWORK_OTHER   0x80

Definition at line 366 of file pcireg.h.

◆ PCIS_NETWORK_PICMG

#define PCIS_NETWORK_PICMG   0x06

Definition at line 363 of file pcireg.h.

◆ PCIS_NETWORK_TOKENRING

#define PCIS_NETWORK_TOKENRING   0x01

Definition at line 358 of file pcireg.h.

◆ PCIS_NETWORK_WORLDFIP

#define PCIS_NETWORK_WORLDFIP   0x05

Definition at line 362 of file pcireg.h.

◆ PCIS_OLD_NONVGA

#define PCIS_OLD_NONVGA   0x00

Definition at line 331 of file pcireg.h.

◆ PCIS_OLD_VGA

#define PCIS_OLD_VGA   0x01

Definition at line 332 of file pcireg.h.

◆ PCIS_PROCESSOR_386

#define PCIS_PROCESSOR_386   0x00

Definition at line 449 of file pcireg.h.

◆ PCIS_PROCESSOR_486

#define PCIS_PROCESSOR_486   0x01

Definition at line 450 of file pcireg.h.

◆ PCIS_PROCESSOR_ALPHA

#define PCIS_PROCESSOR_ALPHA   0x10

Definition at line 452 of file pcireg.h.

◆ PCIS_PROCESSOR_COPROC

#define PCIS_PROCESSOR_COPROC   0x40

Definition at line 455 of file pcireg.h.

◆ PCIS_PROCESSOR_MIPS

#define PCIS_PROCESSOR_MIPS   0x30

Definition at line 454 of file pcireg.h.

◆ PCIS_PROCESSOR_PENTIUM

#define PCIS_PROCESSOR_PENTIUM   0x02

Definition at line 451 of file pcireg.h.

◆ PCIS_PROCESSOR_POWERPC

#define PCIS_PROCESSOR_POWERPC   0x20

Definition at line 453 of file pcireg.h.

◆ PCIS_SATCOM_AUDIO

#define PCIS_SATCOM_AUDIO   0x02

Definition at line 495 of file pcireg.h.

◆ PCIS_SATCOM_DATA

#define PCIS_SATCOM_DATA   0x04

Definition at line 497 of file pcireg.h.

◆ PCIS_SATCOM_TV

#define PCIS_SATCOM_TV   0x01

Definition at line 494 of file pcireg.h.

◆ PCIS_SATCOM_VOICE

#define PCIS_SATCOM_VOICE   0x03

Definition at line 496 of file pcireg.h.

◆ PCIS_SERIALBUS_ACCESS

#define PCIS_SERIALBUS_ACCESS   0x01

Definition at line 459 of file pcireg.h.

◆ PCIS_SERIALBUS_CANBUS

#define PCIS_SERIALBUS_CANBUS   0x09

Definition at line 475 of file pcireg.h.

◆ PCIS_SERIALBUS_FC

#define PCIS_SERIALBUS_FC   0x04

Definition at line 467 of file pcireg.h.

◆ PCIS_SERIALBUS_FW

#define PCIS_SERIALBUS_FW   0x00

Definition at line 458 of file pcireg.h.

◆ PCIS_SERIALBUS_INFINIBAND

#define PCIS_SERIALBUS_INFINIBAND   0x06

Definition at line 469 of file pcireg.h.

◆ PCIS_SERIALBUS_IPMI

#define PCIS_SERIALBUS_IPMI   0x07

Definition at line 470 of file pcireg.h.

◆ PCIS_SERIALBUS_MIPI_I3C

#define PCIS_SERIALBUS_MIPI_I3C   0x0a

Definition at line 476 of file pcireg.h.

◆ PCIS_SERIALBUS_SERCOS

#define PCIS_SERIALBUS_SERCOS   0x08

Definition at line 474 of file pcireg.h.

◆ PCIS_SERIALBUS_SMBUS

#define PCIS_SERIALBUS_SMBUS   0x05

Definition at line 468 of file pcireg.h.

◆ PCIS_SERIALBUS_SSA

#define PCIS_SERIALBUS_SSA   0x02

Definition at line 460 of file pcireg.h.

◆ PCIS_SERIALBUS_USB

#define PCIS_SERIALBUS_USB   0x03

Definition at line 461 of file pcireg.h.

◆ PCIS_SIMPLECOMM_GPIB

#define PCIS_SIMPLECOMM_GPIB   0x04

Definition at line 416 of file pcireg.h.

◆ PCIS_SIMPLECOMM_MODEM

#define PCIS_SIMPLECOMM_MODEM   0x03

Definition at line 415 of file pcireg.h.

◆ PCIS_SIMPLECOMM_MULSER

#define PCIS_SIMPLECOMM_MULSER   0x02

Definition at line 414 of file pcireg.h.

◆ PCIS_SIMPLECOMM_OTHER

#define PCIS_SIMPLECOMM_OTHER   0x80

Definition at line 418 of file pcireg.h.

◆ PCIS_SIMPLECOMM_PAR

#define PCIS_SIMPLECOMM_PAR   0x01

Definition at line 413 of file pcireg.h.

◆ PCIS_SIMPLECOMM_SMART_CARD

#define PCIS_SIMPLECOMM_SMART_CARD   0x05

Definition at line 417 of file pcireg.h.

◆ PCIS_SIMPLECOMM_UART

#define PCIS_SIMPLECOMM_UART   0x00

Definition at line 405 of file pcireg.h.

◆ PCIS_STORAGE_ATA_ADMA

#define PCIS_STORAGE_ATA_ADMA   0x05

Definition at line 345 of file pcireg.h.

◆ PCIS_STORAGE_FLOPPY

#define PCIS_STORAGE_FLOPPY   0x02

Definition at line 342 of file pcireg.h.

◆ PCIS_STORAGE_IDE

#define PCIS_STORAGE_IDE   0x01

Definition at line 336 of file pcireg.h.

◆ PCIS_STORAGE_IPI

#define PCIS_STORAGE_IPI   0x03

Definition at line 343 of file pcireg.h.

◆ PCIS_STORAGE_NVM

#define PCIS_STORAGE_NVM   0x08

Definition at line 349 of file pcireg.h.

◆ PCIS_STORAGE_OTHER

#define PCIS_STORAGE_OTHER   0x80

Definition at line 354 of file pcireg.h.

◆ PCIS_STORAGE_RAID

#define PCIS_STORAGE_RAID   0x04

Definition at line 344 of file pcireg.h.

◆ PCIS_STORAGE_SAS

#define PCIS_STORAGE_SAS   0x07

Definition at line 348 of file pcireg.h.

◆ PCIS_STORAGE_SATA

#define PCIS_STORAGE_SATA   0x06

Definition at line 346 of file pcireg.h.

◆ PCIS_STORAGE_SCSI

#define PCIS_STORAGE_SCSI   0x00

Definition at line 335 of file pcireg.h.

◆ PCIS_STORAGE_UFS

#define PCIS_STORAGE_UFS   0x09

Definition at line 352 of file pcireg.h.

◆ PCIS_WIRELESS_80211A

#define PCIS_WIRELESS_80211A   0x20

Definition at line 484 of file pcireg.h.

◆ PCIS_WIRELESS_80211B

#define PCIS_WIRELESS_80211B   0x21

Definition at line 485 of file pcireg.h.

◆ PCIS_WIRELESS_BLUETOOTH

#define PCIS_WIRELESS_BLUETOOTH   0x11

Definition at line 482 of file pcireg.h.

◆ PCIS_WIRELESS_BROADBAND

#define PCIS_WIRELESS_BROADBAND   0x12

Definition at line 483 of file pcireg.h.

◆ PCIS_WIRELESS_CELL

#define PCIS_WIRELESS_CELL   0x40

Definition at line 486 of file pcireg.h.

◆ PCIS_WIRELESS_CELL_E

#define PCIS_WIRELESS_CELL_E   0x41

Definition at line 487 of file pcireg.h.

◆ PCIS_WIRELESS_IR

#define PCIS_WIRELESS_IR   0x01

Definition at line 480 of file pcireg.h.

◆ PCIS_WIRELESS_IRDA

#define PCIS_WIRELESS_IRDA   0x00

Definition at line 479 of file pcireg.h.

◆ PCIS_WIRELESS_OTHER

#define PCIS_WIRELESS_OTHER   0x80

Definition at line 488 of file pcireg.h.

◆ PCIS_WIRELESS_RF

#define PCIS_WIRELESS_RF   0x10

Definition at line 481 of file pcireg.h.

◆ PCIV_INVALID

#define PCIV_INVALID   0xffff

Definition at line 125 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_133CAP

#define PCIXM_BRIDGE_STATUS_133CAP   0x00020000

Definition at line 735 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_266CAP

#define PCIXM_BRIDGE_STATUS_266CAP   0x40000000

Definition at line 741 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_533CAP

#define PCIXM_BRIDGE_STATUS_533CAP   0x80000000

Definition at line 742 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_64BIT

#define PCIXM_BRIDGE_STATUS_64BIT   0x00010000

Definition at line 734 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_BUS

#define PCIXM_BRIDGE_STATUS_BUS   0x0000FF00

Definition at line 733 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_DEVFN

#define PCIXM_BRIDGE_STATUS_DEVFN   0x000000FF

Definition at line 732 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_DEVID_MSGCAP

#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP   0x20000000

Definition at line 740 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_SC_DISCARDED

#define PCIXM_BRIDGE_STATUS_SC_DISCARDED   0x00040000

Definition at line 736 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_SC_OVERRUN

#define PCIXM_BRIDGE_STATUS_SC_OVERRUN   0x00100000

Definition at line 738 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_SR_DELAYED

#define PCIXM_BRIDGE_STATUS_SR_DELAYED   0x00200000

Definition at line 739 of file pcireg.h.

◆ PCIXM_BRIDGE_STATUS_UNEXP_SC

#define PCIXM_BRIDGE_STATUS_UNEXP_SC   0x00080000

Definition at line 737 of file pcireg.h.

◆ PCIXM_COMMAND_DPERR_E

#define PCIXM_COMMAND_DPERR_E   0x0001 /* Data Parity Error Recovery */

Definition at line 675 of file pcireg.h.

◆ PCIXM_COMMAND_ERO

#define PCIXM_COMMAND_ERO   0x0002 /* Enable Relaxed Ordering */

Definition at line 676 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_READ

#define PCIXM_COMMAND_MAX_READ   0x000c /* Maximum Burst Read Count */

Definition at line 677 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_READ_1024

#define PCIXM_COMMAND_MAX_READ_1024   0x0004

Definition at line 679 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_READ_2048

#define PCIXM_COMMAND_MAX_READ_2048   0x0008

Definition at line 680 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_READ_4096

#define PCIXM_COMMAND_MAX_READ_4096   0x000c

Definition at line 681 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_READ_512

#define PCIXM_COMMAND_MAX_READ_512   0x0000

Definition at line 678 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS

#define PCIXM_COMMAND_MAX_SPLITS   0x0070 /* Maximum Split Transactions */

Definition at line 682 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_1

#define PCIXM_COMMAND_MAX_SPLITS_1   0x0000

Definition at line 683 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_12

#define PCIXM_COMMAND_MAX_SPLITS_12   0x0050

Definition at line 688 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_16

#define PCIXM_COMMAND_MAX_SPLITS_16   0x0060

Definition at line 689 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_2

#define PCIXM_COMMAND_MAX_SPLITS_2   0x0010

Definition at line 684 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_3

#define PCIXM_COMMAND_MAX_SPLITS_3   0x0020

Definition at line 685 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_32

#define PCIXM_COMMAND_MAX_SPLITS_32   0x0070

Definition at line 690 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_4

#define PCIXM_COMMAND_MAX_SPLITS_4   0x0030

Definition at line 686 of file pcireg.h.

◆ PCIXM_COMMAND_MAX_SPLITS_8

#define PCIXM_COMMAND_MAX_SPLITS_8   0x0040

Definition at line 687 of file pcireg.h.

◆ PCIXM_COMMAND_VERSION

#define PCIXM_COMMAND_VERSION   0x3000

Definition at line 691 of file pcireg.h.

◆ PCIXM_SEC_STATUS_133CAP

#define PCIXM_SEC_STATUS_133CAP   0x0002

Definition at line 722 of file pcireg.h.

◆ PCIXM_SEC_STATUS_266CAP

#define PCIXM_SEC_STATUS_266CAP   0x4000

Definition at line 729 of file pcireg.h.

◆ PCIXM_SEC_STATUS_533CAP

#define PCIXM_SEC_STATUS_533CAP   0x8000

Definition at line 730 of file pcireg.h.

◆ PCIXM_SEC_STATUS_64BIT

#define PCIXM_SEC_STATUS_64BIT   0x0001

Definition at line 721 of file pcireg.h.

◆ PCIXM_SEC_STATUS_BUS_MODE

#define PCIXM_SEC_STATUS_BUS_MODE   0x03c0

Definition at line 727 of file pcireg.h.

◆ PCIXM_SEC_STATUS_SC_DISC

#define PCIXM_SEC_STATUS_SC_DISC   0x0004

Definition at line 723 of file pcireg.h.

◆ PCIXM_SEC_STATUS_SC_OVERRUN

#define PCIXM_SEC_STATUS_SC_OVERRUN   0x0010

Definition at line 725 of file pcireg.h.

◆ PCIXM_SEC_STATUS_SR_DELAYED

#define PCIXM_SEC_STATUS_SR_DELAYED   0x0020

Definition at line 726 of file pcireg.h.

◆ PCIXM_SEC_STATUS_UNEXP_SC

#define PCIXM_SEC_STATUS_UNEXP_SC   0x0008

Definition at line 724 of file pcireg.h.

◆ PCIXM_SEC_STATUS_VERSION

#define PCIXM_SEC_STATUS_VERSION   0x3000

Definition at line 728 of file pcireg.h.

◆ PCIXM_STATUS_133CAP

#define PCIXM_STATUS_133CAP   0x00020000

Definition at line 696 of file pcireg.h.

◆ PCIXM_STATUS_266CAP

#define PCIXM_STATUS_266CAP   0x40000000

Definition at line 716 of file pcireg.h.

◆ PCIXM_STATUS_533CAP

#define PCIXM_STATUS_533CAP   0x80000000

Definition at line 717 of file pcireg.h.

◆ PCIXM_STATUS_64BIT

#define PCIXM_STATUS_64BIT   0x00010000

Definition at line 695 of file pcireg.h.

◆ PCIXM_STATUS_BUS

#define PCIXM_STATUS_BUS   0x0000FF00

Definition at line 694 of file pcireg.h.

◆ PCIXM_STATUS_COMPLEX_DEV

#define PCIXM_STATUS_COMPLEX_DEV   0x00100000

Definition at line 699 of file pcireg.h.

◆ PCIXM_STATUS_DEVFN

#define PCIXM_STATUS_DEVFN   0x000000FF

Definition at line 693 of file pcireg.h.

◆ PCIXM_STATUS_MAX_CUM_READ

#define PCIXM_STATUS_MAX_CUM_READ   0x1C000000

Definition at line 714 of file pcireg.h.

◆ PCIXM_STATUS_MAX_READ

#define PCIXM_STATUS_MAX_READ   0x00600000

Definition at line 700 of file pcireg.h.

◆ PCIXM_STATUS_MAX_READ_1024

#define PCIXM_STATUS_MAX_READ_1024   0x00200000

Definition at line 702 of file pcireg.h.

◆ PCIXM_STATUS_MAX_READ_2048

#define PCIXM_STATUS_MAX_READ_2048   0x00400000

Definition at line 703 of file pcireg.h.

◆ PCIXM_STATUS_MAX_READ_4096

#define PCIXM_STATUS_MAX_READ_4096   0x00600000

Definition at line 704 of file pcireg.h.

◆ PCIXM_STATUS_MAX_READ_512

#define PCIXM_STATUS_MAX_READ_512   0x00000000

Definition at line 701 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS

#define PCIXM_STATUS_MAX_SPLITS   0x03800000

Definition at line 705 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_1

#define PCIXM_STATUS_MAX_SPLITS_1   0x00000000

Definition at line 706 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_12

#define PCIXM_STATUS_MAX_SPLITS_12   0x02800000

Definition at line 711 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_16

#define PCIXM_STATUS_MAX_SPLITS_16   0x03000000

Definition at line 712 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_2

#define PCIXM_STATUS_MAX_SPLITS_2   0x00800000

Definition at line 707 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_3

#define PCIXM_STATUS_MAX_SPLITS_3   0x01000000

Definition at line 708 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_32

#define PCIXM_STATUS_MAX_SPLITS_32   0x03800000

Definition at line 713 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_4

#define PCIXM_STATUS_MAX_SPLITS_4   0x01800000

Definition at line 709 of file pcireg.h.

◆ PCIXM_STATUS_MAX_SPLITS_8

#define PCIXM_STATUS_MAX_SPLITS_8   0x02000000

Definition at line 710 of file pcireg.h.

◆ PCIXM_STATUS_RCVD_SC_ERR

#define PCIXM_STATUS_RCVD_SC_ERR   0x20000000

Definition at line 715 of file pcireg.h.

◆ PCIXM_STATUS_SC_DISCARDED

#define PCIXM_STATUS_SC_DISCARDED   0x00040000

Definition at line 697 of file pcireg.h.

◆ PCIXM_STATUS_UNEXP_SC

#define PCIXM_STATUS_UNEXP_SC   0x00080000

Definition at line 698 of file pcireg.h.

◆ PCIXR_BRIDGE_STATUS

#define PCIXR_BRIDGE_STATUS   0x4

Definition at line 731 of file pcireg.h.

◆ PCIXR_COMMAND

#define PCIXR_COMMAND   0x2

Definition at line 674 of file pcireg.h.

◆ PCIXR_SEC_STATUS

#define PCIXR_SEC_STATUS   0x2

Definition at line 720 of file pcireg.h.

◆ PCIXR_STATUS

#define PCIXR_STATUS   0x4

Definition at line 692 of file pcireg.h.

◆ PCIY_AGP

#define PCIY_AGP   0x02 /* AGP */

Definition at line 135 of file pcireg.h.

◆ PCIY_AGP8X

#define PCIY_AGP8X   0x0e /* AGP 8x */

Definition at line 147 of file pcireg.h.

◆ PCIY_CHSWP

#define PCIY_CHSWP   0x06 /* CompactPCI Hot Swap */

Definition at line 139 of file pcireg.h.

◆ PCIY_CRES

#define PCIY_CRES   0x0b /* CompactPCI central resource control */

Definition at line 144 of file pcireg.h.

◆ PCIY_DEBUG

#define PCIY_DEBUG   0x0a /* Debug port */

Definition at line 143 of file pcireg.h.

◆ PCIY_EA

#define PCIY_EA   0x14 /* PCI Extended Allocation */

Definition at line 153 of file pcireg.h.

◆ PCIY_EXPRESS

#define PCIY_EXPRESS   0x10 /* PCI Express */

Definition at line 149 of file pcireg.h.

◆ PCIY_FPB

#define PCIY_FPB   0x15 /* Flattening Portal Bridge */

Definition at line 154 of file pcireg.h.

◆ PCIY_HOTPLUG

#define PCIY_HOTPLUG   0x0c /* PCI Hot-Plug */

Definition at line 145 of file pcireg.h.

◆ PCIY_HT

#define PCIY_HT   0x08 /* HyperTransport */

Definition at line 141 of file pcireg.h.

◆ PCIY_MSI

#define PCIY_MSI   0x05 /* Message Signaled Interrupts */

Definition at line 138 of file pcireg.h.

◆ PCIY_MSIX

#define PCIY_MSIX   0x11 /* MSI-X */

Definition at line 150 of file pcireg.h.

◆ PCIY_PCIAF

#define PCIY_PCIAF   0x13 /* PCI Advanced Features */

Definition at line 152 of file pcireg.h.

◆ PCIY_PCIX

#define PCIY_PCIX   0x07 /* PCI-X */

Definition at line 140 of file pcireg.h.

◆ PCIY_PMG

#define PCIY_PMG   0x01 /* PCI Power Management */

Definition at line 134 of file pcireg.h.

◆ PCIY_SATA

#define PCIY_SATA   0x12 /* SATA */

Definition at line 151 of file pcireg.h.

◆ PCIY_SECDEV

#define PCIY_SECDEV   0x0f /* Secure Device */

Definition at line 148 of file pcireg.h.

◆ PCIY_SLOTID

#define PCIY_SLOTID   0x04 /* Slot Identification */

Definition at line 137 of file pcireg.h.

◆ PCIY_SUBVENDOR

#define PCIY_SUBVENDOR   0x0d /* PCI-PCI bridge subvendor ID */

Definition at line 146 of file pcireg.h.

◆ PCIY_VENDOR

#define PCIY_VENDOR   0x09 /* Vendor Unique */

Definition at line 142 of file pcireg.h.

◆ PCIY_VPD

#define PCIY_VPD   0x03 /* Vital Product Data */

Definition at line 136 of file pcireg.h.

◆ PCIZ_16GT

#define PCIZ_16GT   0x0026 /* Physical Layer 16.0 GT/s */

Definition at line 205 of file pcireg.h.

◆ PCIZ_ACS

#define PCIZ_ACS   0x000d /* Access Control Services */

Definition at line 180 of file pcireg.h.

◆ PCIZ_AER

#define PCIZ_AER   0x0001 /* Advanced Error Reporting */

Definition at line 168 of file pcireg.h.

◆ PCIZ_AMD

#define PCIZ_AMD   0x0014 /* Reserved for AMD */

Definition at line 187 of file pcireg.h.

◆ PCIZ_AP

#define PCIZ_AP   0x002b /* Alternate Protocol */

Definition at line 210 of file pcireg.h.

◆ PCIZ_ARI

#define PCIZ_ARI   0x000e /* Alternative Routing-ID Interpretation */

Definition at line 181 of file pcireg.h.

◆ PCIZ_ATS

#define PCIZ_ATS   0x000f /* Address Translation Services */

Definition at line 182 of file pcireg.h.

◆ PCIZ_CAC

#define PCIZ_CAC   0x000c /* Configuration Access Correction -- obsolete */

Definition at line 179 of file pcireg.h.

◆ PCIZ_DLNK

#define PCIZ_DLNK   0x0025 /* Data Link Feature */

Definition at line 204 of file pcireg.h.

◆ PCIZ_DPA

#define PCIZ_DPA   0x0016 /* Dynamic Power Allocation */

Definition at line 189 of file pcireg.h.

◆ PCIZ_DPC

#define PCIZ_DPC   0x001d /* Downstream Port Containment */

Definition at line 196 of file pcireg.h.

◆ PCIZ_DVSEC

#define PCIZ_DVSEC   0x0023 /* Designated Vendor-Specific */

Definition at line 202 of file pcireg.h.

◆ PCIZ_FRS

#define PCIZ_FRS   0x0021 /* FRS Queuing */

Definition at line 200 of file pcireg.h.

◆ PCIZ_HIER_ID

#define PCIZ_HIER_ID   0x0028 /* Hierarchy ID */

Definition at line 207 of file pcireg.h.

◆ PCIZ_L1PM

#define PCIZ_L1PM   0x001e /* L1 PM Substates */

Definition at line 197 of file pcireg.h.

◆ PCIZ_LMR

#define PCIZ_LMR   0x0027 /* Lane Margining at Receiver */

Definition at line 206 of file pcireg.h.

◆ PCIZ_LN_REQ

#define PCIZ_LN_REQ   0x001c /* LN Requester */

Definition at line 195 of file pcireg.h.

◆ PCIZ_LTR

#define PCIZ_LTR   0x0018 /* Latency Tolerance Reporting */

Definition at line 191 of file pcireg.h.

◆ PCIZ_M_PCIE

#define PCIZ_M_PCIE   0x0020 /* PCIe over M-PHY */

Definition at line 199 of file pcireg.h.

◆ PCIZ_MFVC

#define PCIZ_MFVC   0x0008 /* Multi-Function Virtual Channel */

Definition at line 175 of file pcireg.h.

◆ PCIZ_MRIOV

#define PCIZ_MRIOV   0x0011 /* Multiple Root IO Virtualization */

Definition at line 184 of file pcireg.h.

◆ PCIZ_MULTICAST

#define PCIZ_MULTICAST   0x0012 /* Multicast */

Definition at line 185 of file pcireg.h.

◆ PCIZ_NPEM

#define PCIZ_NPEM   0x0029 /* Native PCIe Enclosure Management */

Definition at line 208 of file pcireg.h.

◆ PCIZ_PAGE_REQ

#define PCIZ_PAGE_REQ   0x0013 /* Page Request */

Definition at line 186 of file pcireg.h.

◆ PCIZ_PASID

#define PCIZ_PASID   0x001b /* Process Address Space ID */

Definition at line 194 of file pcireg.h.

◆ PCIZ_PL32

#define PCIZ_PL32   0x002a /* Physical Layer 32.0 GT/s */

Definition at line 209 of file pcireg.h.

◆ PCIZ_PMUX

#define PCIZ_PMUX   0x001a /* Protocol Multiplexing */

Definition at line 193 of file pcireg.h.

◆ PCIZ_PTM

#define PCIZ_PTM   0x001f /* Precision Time Measurement */

Definition at line 198 of file pcireg.h.

◆ PCIZ_PWRBDGT

#define PCIZ_PWRBDGT   0x0004 /* Power Budgeting */

Definition at line 171 of file pcireg.h.

◆ PCIZ_RCEC_ASSOC

#define PCIZ_RCEC_ASSOC   0x0007 /* Root Complex Event Collector Association */

Definition at line 174 of file pcireg.h.

◆ PCIZ_RCLINK_CTL

#define PCIZ_RCLINK_CTL   0x0006 /* Root Complex Internal Link Control */

Definition at line 173 of file pcireg.h.

◆ PCIZ_RCLINK_DCL

#define PCIZ_RCLINK_DCL   0x0005 /* Root Complex Link Declaration */

Definition at line 172 of file pcireg.h.

◆ PCIZ_RCRB

#define PCIZ_RCRB   0x000a /* RCRB Header */

Definition at line 177 of file pcireg.h.

◆ PCIZ_RESIZE_BAR

#define PCIZ_RESIZE_BAR   0x0015 /* Resizable BAR */

Definition at line 188 of file pcireg.h.

◆ PCIZ_RTR

#define PCIZ_RTR   0x0022 /* Readiness Time Reporting */

Definition at line 201 of file pcireg.h.

◆ PCIZ_SEC_PCIE

#define PCIZ_SEC_PCIE   0x0019 /* Secondary PCI Express */

Definition at line 192 of file pcireg.h.

◆ PCIZ_SERNUM

#define PCIZ_SERNUM   0x0003 /* Device Serial Number */

Definition at line 170 of file pcireg.h.

◆ PCIZ_SFI

#define PCIZ_SFI   0x002c /* System Firmware Intermediary */

Definition at line 211 of file pcireg.h.

◆ PCIZ_SRIOV

#define PCIZ_SRIOV   0x0010 /* Single Root IO Virtualization */

Definition at line 183 of file pcireg.h.

◆ PCIZ_TPH_REQ

#define PCIZ_TPH_REQ   0x0017 /* TPH Requester */

Definition at line 190 of file pcireg.h.

◆ PCIZ_VC

#define PCIZ_VC   0x0002 /* Virtual Channel if MFVC Ext Cap not set */

Definition at line 169 of file pcireg.h.

◆ PCIZ_VC2

#define PCIZ_VC2   0x0009 /* Virtual Channel if MFVC Ext Cap set */

Definition at line 176 of file pcireg.h.

◆ PCIZ_VENDOR

#define PCIZ_VENDOR   0x000b /* Vendor Unique */

Definition at line 178 of file pcireg.h.

◆ PCIZ_VF_REBAR

#define PCIZ_VF_REBAR   0x0024 /* VF Resizable BAR */

Definition at line 203 of file pcireg.h.