FreeBSD kernel pms device code
saport.c
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1/*******************************************************************************
2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
3*
4*Redistribution and use in source and binary forms, with or without modification, are permitted provided
5*that the following conditions are met:
6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7*following disclaimer.
8*2. Redistributions in binary form must reproduce the above copyright notice,
9*this list of conditions and the following disclaimer in the documentation and/or other materials provided
10*with the distribution.
11*
12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20
21********************************************************************************/
22/*******************************************************************************/
27/******************************************************************************/
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD$");
30#include <dev/pms/config.h>
31
33#ifdef SA_ENABLE_TRACE_FUNCTIONS
34#ifdef siTraceFileID
35#undef siTraceFileID
36#endif
37#define siTraceFileID 'L'
38#endif
39
40
41extern bit32 gFPGA_TEST;
42/******************************************************************************/
59/*******************************************************************************/
61 agsaRoot_t *agRoot,
62 agsaPort_t *pPort,
63 agsaSASIdentify_t sasIdentify,
64 bit32 sasInitiator,
65 bit32 smpTimeout,
66 bit32 itNexusTimeout,
67 bit32 firstBurstSize,
68 bit8 dTypeSRate,
69 bit32 flag
70 )
71{
72 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
73 agsaDeviceDesc_t *pDevice;
74
75 SA_DBG3(("siPortSASDeviceAdd: start\n"));
76
78
79 /* sanity check */
80 SA_ASSERT((agNULL != agRoot), "");
81 SA_ASSERT((agNULL != pPort), "");
82
83 /* Acquire Device Lock */
85
86 /* Try to Allocate from device list */
87 pDevice = (agsaDeviceDesc_t *) saLlistGetHead(&(saRoot->freeDevicesList));
88
89 /* If device handle available */
90 if ( agNULL != pDevice)
91 {
92 int i;
93
94 /* Remove from free device list */
95 saLlistRemove(&(saRoot->freeDevicesList), &(pDevice->linkNode));
96
97 /* Initialize device descriptor */
98 if ( agTRUE == sasInitiator )
99 {
100 pDevice->initiatorDevHandle.sdkData = pDevice;
101 pDevice->targetDevHandle.sdkData = agNULL;
102 }
103 else
104 {
106 pDevice->targetDevHandle.sdkData = pDevice;
107 }
108
110 pDevice->targetDevHandle.osData = agNULL;
111
112 /* setup device type */
113 pDevice->deviceType = (bit8)((dTypeSRate & 0x30) >> SHIFT4);
114 SA_DBG3(("siPortSASDeviceAdd: Device Type 0x%x, Port Context %p\n", pDevice->deviceType, pPort));
115 pDevice->pPort = pPort;
117
118 /* setup sasDeviceInfo */
119 pDevice->devInfo.sasDeviceInfo.commonDevInfo.smpTimeout = (bit16)smpTimeout;
120 pDevice->devInfo.sasDeviceInfo.commonDevInfo.it_NexusTimeout = (bit16)itNexusTimeout;
121 pDevice->devInfo.sasDeviceInfo.commonDevInfo.firstBurstSize = (bit16)firstBurstSize;
123 pDevice->devInfo.sasDeviceInfo.commonDevInfo.flag = flag;
124 for (i = 0; i < 4; i++)
125 {
126 pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressHi[i] = sasIdentify.sasAddressHi[i];
127 pDevice->devInfo.sasDeviceInfo.commonDevInfo.sasAddressLo[i] = sasIdentify.sasAddressLo[i];
128 }
131 pDevice->devInfo.sasDeviceInfo.phyIdentifier = sasIdentify.phyIdentifier;
132
133 /* Add to discoverd device for the port */
134 saLlistAdd(&(pPort->listSASATADevices), &(pDevice->linkNode));
135
136 /* Release Device Lock */
138
139 /* Log Messages */
140 SA_DBG3(("siPortSASDeviceAdd: sasIdentify addrHI 0x%x\n", SA_IDFRM_GET_SAS_ADDRESSHI(&sasIdentify)));
141 SA_DBG3(("siPortSASDeviceAdd: sasIdentify addrLO 0x%x\n", SA_IDFRM_GET_SAS_ADDRESSLO(&sasIdentify)));
142
143 }
144 else
145 {
146 /* Release Device Lock */
148 SA_ASSERT((agNULL != pDevice), "");
149 SA_DBG1(("siPortSASDeviceAdd: device allocation failed\n"));
150 }
151 SA_DBG3(("siPortSASDeviceAdd: end\n"));
152
154 return pDevice;
155}
156
157/******************************************************************************/
168/*******************************************************************************/
170 agsaRoot_t *agRoot,
171 agsaPort_t *pPort,
172 agsaDeviceDesc_t *pDevice,
173 bit32 unmap
174 )
175{
176 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
177 bit32 deviceIdx;
178
180
181 /* sanity check */
182 SA_ASSERT((agNULL != agRoot), "");
183 SA_ASSERT((agNULL != pPort), "");
184 SA_ASSERT((agNULL != pDevice), "");
186
187 /* remove the device from discovered list */
188 SA_DBG3(("siPortDeviceRemove(SAS/SATA): DeviceIndex %d Device Context %p\n", pDevice->DeviceMapIndex, pDevice));
189
191 saLlistRemove(&(pPort->listSASATADevices), &(pDevice->linkNode));
192
193 /* Reset the device data structure */
194 pDevice->pPort = agNULL;
197 pDevice->targetDevHandle.osData = agNULL;
198 pDevice->targetDevHandle.sdkData = agNULL;
199
200 saLlistAdd(&(saRoot->freeDevicesList), &(pDevice->linkNode));
201
202 if(unmap)
203 {
204 /* remove the DeviceMap and MapIndex */
205 deviceIdx = pDevice->DeviceMapIndex & DEVICE_ID_BITS;
206 OS_ASSERT(deviceIdx < MAX_IO_DEVICE_ENTRIES, "deviceIdx MAX_IO_DEVICE_ENTRIES");
207
208 saRoot->DeviceMap[deviceIdx].DeviceIdFromFW = 0;
209 saRoot->DeviceMap[deviceIdx].DeviceHandle = agNULL;
210 pDevice->DeviceMapIndex = 0;
211 }
213
215
216 return;
217}
218
219/******************************************************************************/
237/*******************************************************************************/
239 agsaRoot_t *agRoot,
240 agsaPort_t *pPort,
241 agsaDeviceDesc_t *pSTPBridge,
242 bit8 *pSignature,
243 bit8 pm,
244 bit8 pmField,
245 bit32 smpReqTimeout,
246 bit32 itNexusTimeout,
247 bit32 firstBurstSize,
248 bit8 dTypeSRate,
249 bit32 flag
250 )
251{
252 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
253 agsaDeviceDesc_t *pDevice;
254
256
257 /* sanity check */
258 SA_ASSERT((agNULL != agRoot), "");
259 SA_ASSERT((agNULL != pPort), "");
260
261 /* Acquire Device Lock */
263
264 /* Try to Allocate from device list */
265 pDevice = (agsaDeviceDesc_t *) saLlistGetHead(&(saRoot->freeDevicesList));
266
267 /* If device handle available */
268 if ( agNULL != pDevice)
269 {
270 int i;
271
272 /* Remove from free device list */
273 saLlistRemove(&(saRoot->freeDevicesList), &(pDevice->linkNode));
274
275 /* Initialize the device descriptor */
277 pDevice->targetDevHandle.sdkData = pDevice;
279 pDevice->targetDevHandle.osData = agNULL;
280
281 pDevice->deviceType = (bit8)((dTypeSRate & 0x30) >> SHIFT4);
282 SA_DBG3(("siPortSATADeviceAdd: DeviceType 0x%x Port Context %p\n", pDevice->deviceType, pPort));
283
284 /* setup device common infomation */
285 pDevice->devInfo.sataDeviceInfo.commonDevInfo.smpTimeout = (bit16)smpReqTimeout;
286 pDevice->devInfo.sataDeviceInfo.commonDevInfo.it_NexusTimeout = (bit16)itNexusTimeout;
287 pDevice->devInfo.sataDeviceInfo.commonDevInfo.firstBurstSize = (bit16)firstBurstSize;
290 for (i = 0; i < 4; i++)
291 {
294 }
295 /* setup SATA device information */
296 pDevice->devInfo.sataDeviceInfo.connection = pm;
297 pDevice->devInfo.sataDeviceInfo.portMultiplierField = pmField;
299 pDevice->pPort = pPort;
300
301 /* Add to discoverd device for the port */
302 saLlistAdd(&(pPort->listSASATADevices), &(pDevice->linkNode));
303
304 /* Release Device Lock */
306 }
307 else
308 {
309 /* Release Device Lock */
311 SA_ASSERT((agNULL != pDevice), "");
312 SA_DBG1(("siPortSATADeviceAdd: device allocation failed\n"));
313 }
314 SA_DBG3(("siPortSATADeviceAdd: end\n"));
315
317 return pDevice;
318}
319
320/******************************************************************************/
330/*******************************************************************************/
332 agsaRoot_t *agRoot,
333 agsaPort_t *pPort
334 )
335{
336 agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData);
338
339 /* sanity check */
340 SA_ASSERT((agNULL != agRoot), "");
341 SA_ASSERT((agNULL != pPort), "");
342
343 /* set port's status to invalidating */
344 pPort->status |= PORT_INVALIDATING;
345
346 /* Remove from validPort and add the port back to the free port link list */
348 saLlistRemove(&(saRoot->validPorts), &(pPort->linkNode));
349 saLlistAdd(&(saRoot->freePorts), &(pPort->linkNode));
350 pPort->tobedeleted = agFALSE;
352
354
355 /* return */
356}
357
358/******************************************************************************/
369/*******************************************************************************/
371 agsaRoot_t *agRoot,
372 agsaPort_t *pPort,
373 agsaDeviceDesc_t *pDevice
374 )
375{
376 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
377
379
380 /* sanity check */
381 SA_ASSERT((agNULL != agRoot), "");
382 SA_ASSERT((agNULL != pPort), "");
383 SA_ASSERT((agNULL != pDevice), "");
385
386 /* remove the device from discovered list */
387 SA_DBG3(("siPortDeviceListRemove(SAS/SATA): PortID %d Device Context %p\n", pPort->portId, pDevice));
388
390 saLlistRemove(&(pPort->listSASATADevices), &(pDevice->linkNode));
391
392 /* Reset the device data structure */
393 pDevice->pPort = agNULL;
396 pDevice->targetDevHandle.osData = agNULL;
397 pDevice->targetDevHandle.sdkData = agNULL;
398
399 saLlistAdd(&(saRoot->freeDevicesList), &(pDevice->linkNode));
401
403 return;
404}
405
406/******************************************************************************/
421/*******************************************************************************/
423 agsaRoot_t *agRoot,
424 agsaContext_t *agContext,
425 bit32 queueNum,
426 agsaPortContext_t *agPortContext,
427 bit32 portOperation,
428 bit32 param0,
429 bit32 param1
430 )
431{
432 agsaLLRoot_t *saRoot = (agsaLLRoot_t *) (agRoot->sdkData);
433 agsaIORequestDesc_t *pRequest;
434 agsaPort_t *pPort;
436 bit32 opportId;
437 agsaPortControlCmd_t payload;
438 bit32 using_reserved = agFALSE;
439
440
441 /* sanity check */
442 SA_ASSERT((agNULL !=saRoot ), "");
443 SA_ASSERT((agNULL != agPortContext), "");
444 if(saRoot == agNULL)
445 {
446 SA_DBG1(("saPortControl: saRoot == agNULL\n"));
447 return(AGSA_RC_FAILURE);
448 }
450
451 SA_DBG1(("saPortControl: portContext %p portOperation 0x%x param0 0x%x param1 0x%x\n", agPortContext, portOperation, param0, param1));
452
453 /* Get request from free IORequests */
455 pRequest = (agsaIORequestDesc_t *)saLlistIOGetHead(&(saRoot->freeIORequests));
456 /* If no LL Control request entry available */
457 if ( agNULL == pRequest )
458 {
460 /* If no LL Control request entry available */
461 if(agNULL != pRequest)
462 {
463 using_reserved = agTRUE;
464 SA_DBG2(("saPortControl, using saRoot->freeReservedRequests\n"));
465 }
466 else
467 {
469 SA_DBG1(("saPortControl, No request from free list Not using saRoot->freeReservedRequests\n"));
471 return AGSA_RC_BUSY;
472 }
473 }
474
475 /* If LL Control request entry avaliable */
476 if( using_reserved )
477 {
478 saLlistIORemove(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
479 }
480 else
481 {
482 /* Remove the request from free list */
483 saLlistIORemove(&(saRoot->freeIORequests), &(pRequest->linkNode));
484 }
485 SA_ASSERT((!pRequest->valid), "The pRequest is in use");
486 saRoot->IOMap[pRequest->HTag].Tag = pRequest->HTag;
487 saRoot->IOMap[pRequest->HTag].IORequest = (void *)pRequest;
488 saRoot->IOMap[pRequest->HTag].agContext = agContext;
489 pRequest->valid = agTRUE;
491
492 /* build IOMB command and send to SPC */
493 /* set payload to zeros */
494 si_memset(&payload, 0, sizeof(agsaPortControlCmd_t));
495
496 /* find port id */
497 pPort = (agsaPort_t *) (agPortContext->sdkData);
498 opportId = (pPort->portId & PORTID_MASK) | (portOperation << SHIFT8);
499 /* set tag */
500 OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, tag), pRequest->HTag);
501 OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, portOPPortId), opportId);
502 OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, Param0), param0);
503 OSSA_WRITE_LE_32(agRoot, &payload, OSSA_OFFSET_OF(agsaPortControlCmd_t, Param1), param1);
504
505 SA_DBG1(("saPortControl: portId 0x%x portOperation 0x%x\n", (pPort->portId & PORTID_MASK),portOperation));
506
507 /* build IOMB command and send to SPC */
508 ret = mpiBuildCmd(agRoot, (bit32 *)&payload, MPI_CATEGORY_SAS_SATA, OPC_INB_PORT_CONTROL, IOMB_SIZE64, queueNum);
509 if (AGSA_RC_SUCCESS != ret)
510 {
511 /* remove the request from IOMap */
512 saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF;
513 saRoot->IOMap[pRequest->HTag].IORequest = agNULL;
514 saRoot->IOMap[pRequest->HTag].agContext = agNULL;
515 pRequest->valid = agFALSE;
516 /* return the request to free pool */
519 {
520 SA_DBG1(("saPortControl: saving pRequest (%p) for later use\n", pRequest));
521 saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode));
522 }
523 else
524 {
525 /* return the request to free pool */
526 saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode));
527 }
529 SA_DBG1(("saPortControl, sending IOMB failed\n" ));
530 }
531 else
532 {
533 if (portOperation == AGSA_PORT_HARD_RESET)
534 {
535 SA_DBG1(("saPortControl,0x%x AGSA_PORT_HARD_RESET 0x%x param0 0x%x\n",
536 pPort->portId, param0, param0 & AUTO_HARD_RESET_DEREG_FLAG));
538 }
539 else if (portOperation == AGSA_PORT_CLEAN_UP)
540 {
541 SA_DBG1(("saPortControl, 0x%x AGSA_PORT_CLEAN_UP param0 0x%x %d\n", pPort->portId, param0,((param0 & AUTO_FW_CLEANUP_DEREG_FLAG) ? 0:1)));
542 saRoot->autoDeregDeviceflag[pPort->portId & PORTID_MASK] = ((param0 & AUTO_FW_CLEANUP_DEREG_FLAG) ? 0:1);
543 }
544 SA_DBG1(("saPortControl, sending IOMB SUCCESS, portId 0x%x autoDeregDeviceflag=0x%x\n", pPort->portId,saRoot->autoDeregDeviceflag[pPort->portId & PORTID_MASK]));
545 }
546
548
549 return ret;
550}
551
564 agsaContext_t *agContext,
565 agsaEncryptInfo_t *encryptInfo)
566{
568
570 agContext = agContext; /* Lint*/
571 SA_DBG4(("saEncryptGetMode, encryptInfo %p\n",encryptInfo ));
572 if(smIS_SPCV(agRoot))
573 {
574 bit32 ScratchPad1 =0;
575 bit32 ScratchPad3 =0;
576
577 encryptInfo->status = 0;
578 encryptInfo->encryptionCipherMode = 0;
579 encryptInfo->encryptionSecurityMode = 0;
580 encryptInfo->flag = 0;
581
582 ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register);
583 ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register);
585 {
586 if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK) == SCRATCH_PAD3_V_ENC_READY ) /* 3 */
587 {
588 if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED)
589 {
591 }
592 if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED )
593 {
595 }
597 {
599 }
600 if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED )
601 {
603 }
604 encryptInfo->status = AGSA_RC_SUCCESS;
605 ret = AGSA_RC_SUCCESS;
606 }
607 else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_READY) == SCRATCH_PAD3_V_ENC_DISABLED) /* 0 */
608 {
609 SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_DISABLED 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
610 encryptInfo->status = 0xFFFF;
611 encryptInfo->encryptionCipherMode = 0;
612 encryptInfo->encryptionSecurityMode = 0;
614 }
615 else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_DIS_ERR) /* 1 */
616 {
617 SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_DIS_ERR 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
618 encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16;
619 if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED)
620 {
622 }
623 if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED )
624 {
626 }
628 {
630 }
631 if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED )
632 {
634 }
635 ret = AGSA_RC_FAILURE;
636 }
637 else if((ScratchPad3 & SCRATCH_PAD3_V_ENC_MASK ) == SCRATCH_PAD3_V_ENC_ENA_ERR) /* 2 */
638 {
639
640 SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_ENA_ERR 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
641 encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16;
642 if( ScratchPad3 & SCRATCH_PAD3_V_XTS_ENABLED)
643 {
645 SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_ENA_ERR 2 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
646 }
647 if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMF_ENABLED )
648 {
649 SA_DBG1(("saEncryptGetMode, SCRATCH_PAD3_V_ENC_ENA_ERR 3 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
651 }
653 {
655 }
656 if( (ScratchPad3 & SCRATCH_PAD3_V_SM_MASK ) == SCRATCH_PAD3_V_SMB_ENABLED )
657 {
659 }
660
661 SA_DBG1(("saEncryptGetMode,encryptInfo status 0x%08X CipherMode 0x%X SecurityMode 0x%X\n" ,
662 encryptInfo->status,
663 encryptInfo->encryptionCipherMode,
664 encryptInfo->encryptionSecurityMode));
665
666#ifdef CCFLAGS_SPCV_FPGA_REVB /*The FPGA platform hasn't EEPROM*/
667 ret = AGSA_RC_SUCCESS;
668#else
669 ret = AGSA_RC_FAILURE;
670#endif
671 }
672 }
673 else if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == SCRATCH_PAD1_V_RAAE_ERR)
674 {
675 SA_DBG1(("saEncryptGetMode, SCRATCH_PAD1_V_RAAE_ERR 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
676 ret = AGSA_RC_FAILURE;
677 }
678 else if((ScratchPad1 & SCRATCH_PAD1_V_RAAE_MASK) == 0x0 )
679 {
680 SA_DBG1(("saEncryptGetMode, RAAE not ready AGSA_RC_BUSY 1 0x%08X 3 0x%08X\n",ScratchPad1,ScratchPad3 ));
681 ret = AGSA_RC_BUSY;
682 }
683 if(ScratchPad3 & SCRATCH_PAD3_V_AUT)
684 {
686 }
687 if(ScratchPad3 & SCRATCH_PAD3_V_ARF)
688 {
689 encryptInfo->flag |= ReturnToFactoryMode_ARF;
690 }
691
692 SA_DBG2(("saEncryptGetMode, encryptionCipherMode 0x%x encryptionSecurityMode 0x%x flag 0x%x status 0x%x\n",
693 encryptInfo->encryptionCipherMode,
694 encryptInfo->encryptionSecurityMode,
695 encryptInfo->flag,
696 encryptInfo->status));
697 SA_DBG2(("saEncryptGetMode, ScratchPad3 0x%x returns 0x%x\n",ScratchPad3, ret));
698
699 }
700 else
701 {
702 SA_DBG1(("saEncryptGetMode, SPC AGSA_RC_NOT_SUPPORTED\n"));
703 }
704
706 return ret;
707}
708
709
711 agsaRoot_t *agRoot,
712 agsaContext_t *agContext,
713 bit32 queueNum,
715 )
716
717{
719 agsaSetControllerConfigCmd_t agControllerConfig;
720 agsaSetControllerConfigCmd_t *pagControllerConfig = &agControllerConfig;
721 bit32 smode = 0;
722
723 if(smIS_SPCV(agRoot))
724 {
725 bit32 ScratchPad1 =0;
726
727 ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register);
729 {
730 si_memset(pagControllerConfig,0,sizeof(agsaSetControllerConfigCmd_t));
731
732 SA_DBG2(("saEncryptSetMode, encryptionCipherMode 0x%x encryptionSecurityMode 0x%x status 0x%x\n",
735 mode->status
736 ));
737
738 smode = mode->encryptionSecurityMode;
739
741 {
742 smode |= 1 << SHIFT22;
743 }
744
745
746 pagControllerConfig->pageCode = AGSA_ENCRYPTION_CONTROL_PARM_PAGE | smode;
747 pagControllerConfig->tag =0;
748
749 SA_DBG2(("saEncryptSetMode,tag 0x%x pageCode 0x%x\n",
750 pagControllerConfig->tag,
751 pagControllerConfig->pageCode
752 ));
753
754 SA_DBG2(("saEncryptSetMode, 0x%x 0x%x 0x%x 0x%x\n",
755 pagControllerConfig->configPage[0],
756 pagControllerConfig->configPage[1],
757 pagControllerConfig->configPage[2],
758 pagControllerConfig->configPage[3]
759 ));
760
761 SA_DBG2(("saEncryptSetMode, 0x%x 0x%x 0x%x 0x%x\n",
762 pagControllerConfig->configPage[4],
763 pagControllerConfig->configPage[5],
764 pagControllerConfig->configPage[6],
765 pagControllerConfig->configPage[7]
766 ));
767
768 SA_DBG2(("saEncryptSetMode, 0x%x 0x%x 0x%x 0x%x\n",
769 pagControllerConfig->configPage[8],
770 pagControllerConfig->configPage[9],
771 pagControllerConfig->configPage[10],
772 pagControllerConfig->configPage[11]
773 ));
774
775 ret = mpiSetControllerConfigCmd(agRoot,agContext,pagControllerConfig,queueNum,agTRUE);
776
777 SA_DBG2(("saEncryptSetMode, pageCode 0x%x tag 0x%x status 0x%x\n",
778 pagControllerConfig->pageCode,
779 pagControllerConfig->tag,
780 ret
781 ));
782 }
783 else
784 {
785 SA_DBG2(("saEncryptSetMode,ScratchPad1 not ready %08X\n",ScratchPad1 ));
786 ret = AGSA_RC_BUSY;
787 }
788
789 }
790 return ret;
791}
792
793
794
809 agsaRoot_t *agRoot,
810 agsaContext_t *agContext,
811 bit32 queueNum,
812 bit32 flags,
813 bit32 newKekIndex,
816 agsaEncryptKekBlob_t *encryptKekBlob
817 )
818{
820 bit32 ret, i;
821
823
824 SA_DBG2(("saEncryptKekUpdate, flags 0x%x newKekIndex 0x%x wrapperKekIndex 0x%x encryptKekBlob %p\n",flags,newKekIndex,wrapperKekIndex,encryptKekBlob));
825 SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n",
826 encryptKekBlob->kekBlob[0],encryptKekBlob->kekBlob[1],
827 encryptKekBlob->kekBlob[2],encryptKekBlob->kekBlob[3],
828 encryptKekBlob->kekBlob[4],encryptKekBlob->kekBlob[5],
829 encryptKekBlob->kekBlob[6],encryptKekBlob->kekBlob[7]));
830 SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n",
831 encryptKekBlob->kekBlob[ 8],encryptKekBlob->kekBlob[ 9],
832 encryptKekBlob->kekBlob[10],encryptKekBlob->kekBlob[11],
833 encryptKekBlob->kekBlob[12],encryptKekBlob->kekBlob[13],
834 encryptKekBlob->kekBlob[14],encryptKekBlob->kekBlob[15]));
835 SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n",
836 encryptKekBlob->kekBlob[16],encryptKekBlob->kekBlob[17],
837 encryptKekBlob->kekBlob[18],encryptKekBlob->kekBlob[19],
838 encryptKekBlob->kekBlob[20],encryptKekBlob->kekBlob[21],
839 encryptKekBlob->kekBlob[22],encryptKekBlob->kekBlob[23]));
840 SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n",
841 encryptKekBlob->kekBlob[24],encryptKekBlob->kekBlob[25],
842 encryptKekBlob->kekBlob[26],encryptKekBlob->kekBlob[27],
843 encryptKekBlob->kekBlob[28],encryptKekBlob->kekBlob[29],
844 encryptKekBlob->kekBlob[30],encryptKekBlob->kekBlob[31]));
845 SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n",
846 encryptKekBlob->kekBlob[32],encryptKekBlob->kekBlob[33],
847 encryptKekBlob->kekBlob[34],encryptKekBlob->kekBlob[35],
848 encryptKekBlob->kekBlob[36],encryptKekBlob->kekBlob[37],
849 encryptKekBlob->kekBlob[38],encryptKekBlob->kekBlob[39]));
850 SA_DBG2(("saEncryptKekUpdate, 0x%02X%02X%02X%02X 0x%02X%02X%02X%02X\n",
851 encryptKekBlob->kekBlob[40],encryptKekBlob->kekBlob[41],
852 encryptKekBlob->kekBlob[42],encryptKekBlob->kekBlob[43],
853 encryptKekBlob->kekBlob[44],encryptKekBlob->kekBlob[45],
854 encryptKekBlob->kekBlob[46],encryptKekBlob->kekBlob[47]));
855 /* create payload for IOMB */
856 si_memset(&payload, 0, sizeof(agsaKekManagementCmd_t));
857
858 OSSA_WRITE_LE_32(agRoot,
859 &payload,
860 OSSA_OFFSET_OF(agsaKekManagementCmd_t, NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP),
861 (newKekIndex << SHIFT24) | (wrapperKekIndex << SHIFT16) | blobFormat << SHIFT14 | (flags << SHIFT8) | KEK_MGMT_SUBOP_UPDATE);
862 for (i = 0; i < 12; i++)
863 {
864
865 OSSA_WRITE_LE_32(agRoot,
866 &payload,
868 (bit32)*(bit32*)&encryptKekBlob->kekBlob[i * sizeof(bit32)] );
869
870 }
871
872 ret = mpiKekManagementCmd(agRoot, agContext, &payload, queueNum );
873
875 return ret;
876}
877
878
879#ifdef HIALEAH_ENCRYPTION
880
881GLOBAL bit32 saEncryptHilUpdate(
882 agsaRoot_t *agRoot,
883 agsaContext_t *agContext,
884 bit32 queueNum
885 )
886{
888
889 bit32 ScratchPad1 =0;
890 bit32 ScratchPad3 =0;
891 bit32 ret =0;
892
893 ScratchPad1 = ossaHwRegRead(agRoot,V_Scratchpad_1_Register);
894 ScratchPad3 = ossaHwRegRead(agRoot,V_Scratchpad_3_Register);
895
896
898
899 SA_DBG2(("saEncryptHilUpdate ScratchPad1 0x08%x ScratchPad3 0x08%x\n",ScratchPad1,ScratchPad3));
900 /* create payload for IOMB */
901 si_memset(&payload, 0, sizeof(agsaKekManagementCmd_t));
902
903 OSSA_WRITE_LE_32(agRoot,
904 &payload,
905 OSSA_OFFSET_OF(agsaKekManagementCmd_t, NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP),
906 (1 << SHIFT24) | (1 << SHIFT16) | (1 << SHIFT8) | KEK_MGMT_SUBOP_KEYCARDUPDATE);
907
908
909 ret = mpiKekManagementCmd(agRoot, agContext, &payload, queueNum );
910
911 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "xxx");
912 return ret;
913}
914#endif /* HIALEAH_ENCRYPTION */
915
930 agsaRoot_t *agRoot,
931 agsaContext_t *agContext,
932 bit32 queueNum,
934 )
935{
937 bit32 ret;
938
940
941 SA_DBG2(("saEncryptKekInvalidate, kekIndex 0x%x \n",kekIndex));
942
943
944 /* create payload for IOMB */
945 si_memset(&payload, 0, sizeof(agsaDekManagementCmd_t));
946
947 OSSA_WRITE_LE_32(agRoot,
948 &payload,
949 OSSA_OFFSET_OF(agsaKekManagementCmd_t, NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP),
951
952 ret = mpiKekManagementCmd(agRoot, agContext, &payload, queueNum );
953
955 return ret;
956}
957
974 agsaRoot_t *agRoot,
975 agsaContext_t *agContext,
976 bit32 queueNum,
978 bit32 dekTableSelect,
979 bit32 dekAddrHi,
980 bit32 dekAddrLo,
982 bit32 dekNumberOfEntries,
985 )
986{
988 bit32 ret;
989
991
992 SA_DBG2(("saEncryptDekCacheUpdate, kekIndex 0x%x dekTableSelect 0x%x dekAddrHi 0x%x dekAddrLo 0x%x\n",
993 kekIndex,
994 dekTableSelect,
995 dekAddrHi,
996 dekAddrLo ));
997 SA_DBG2(("saEncryptDekCacheUpdate, dekIndex 0x%x dekNumberOfEntries 0x%x dekBlobFormat 0x%x dekTableKeyEntrySize 0x%x\n",
998 dekIndex,
999 dekNumberOfEntries,
1002
1003 /* create payload for IOMB */
1004 si_memset(&payload, 0, sizeof(agsaDekManagementCmd_t));
1005
1006 OSSA_WRITE_LE_32(agRoot,
1007 &payload,
1008 OSSA_OFFSET_OF(agsaDekManagementCmd_t, KEKIDX_Reserved_TBLS_DSOP),
1009 (kekIndex << SHIFT24) | (dekTableSelect << SHIFT8) | DEK_MGMT_SUBOP_UPDATE);
1010
1011 OSSA_WRITE_LE_32(agRoot,
1012 &payload,
1014 dekIndex);
1015
1016 OSSA_WRITE_LE_32(agRoot,
1017 &payload,
1019 dekAddrLo);
1020
1021 OSSA_WRITE_LE_32(agRoot,
1022 &payload,
1024 dekAddrHi);
1025
1026 OSSA_WRITE_LE_32(agRoot,
1027 &payload,
1029 dekNumberOfEntries);
1030
1031 OSSA_WRITE_LE_32(agRoot,
1032 &payload,
1033 OSSA_OFFSET_OF(agsaDekManagementCmd_t, Reserved_DBF_TBL_SIZE),
1035
1036 ret = mpiDekManagementCmd(agRoot, agContext, &payload, queueNum);
1037
1038 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "32");
1039 return ret;
1040}
1041
1058 agsaRoot_t *agRoot,
1059 agsaContext_t *agContext,
1060 bit32 queueNum,
1063 )
1064{
1065 agsaDekManagementCmd_t payload;
1066 bit32 ret;
1067
1069
1070 SA_DBG2(("saEncryptDekCacheInvalidate,dekTable 0x%x dekIndex 0x%x\n",dekTable,dekIndex));
1071
1072 /* create payload for IOMB */
1073 si_memset(&payload, 0, sizeof(agsaDekManagementCmd_t));
1074
1075 OSSA_WRITE_LE_32(agRoot,
1076 &payload,
1077 OSSA_OFFSET_OF(agsaDekManagementCmd_t, KEKIDX_Reserved_TBLS_DSOP),
1079
1080 OSSA_WRITE_LE_32(agRoot,
1081 &payload,
1083 dekIndex);
1084
1085 /* Assume all DEKs are 80 bytes*/
1086 OSSA_WRITE_LE_32(agRoot,
1087 &payload,
1088 OSSA_OFFSET_OF(agsaDekManagementCmd_t, Reserved_DBF_TBL_SIZE),
1089 4);
1090
1091 ret = mpiDekManagementCmd(agRoot, agContext, &payload, queueNum);
1092
1093 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "33");
1094 return ret;
1095}
1096
1112 agsaRoot_t *agRoot,
1113 agsaContext_t *agContext,
1114 bit32 queueNum,
1115 bit32 op,
1116 agsaDifEncPayload_t *agsaDifEncPayload,
1118{
1119 bit32 ret = AGSA_RC_FAILURE;
1120
1122 SA_DBG1(("saDIFEncryptionOffloadStart: start op=%d, agsaDifEncPayload=%p\n", op, agsaDifEncPayload));
1123
1124 if(smIS_SPCV(agRoot))
1125 {
1126 ret = mpiDIFEncryptionOffloadCmd(agRoot, agContext, queueNum, op, agsaDifEncPayload, agCB);
1127 }
1128 else
1129 {
1130 SA_DBG1(("saDIFEncryptionOffloadStart: spcv only AGSA_RC_FAILURE \n"));
1131 }
1132
1133 SA_DBG1(("saDIFEncryptionOffloadStart: end status 0x%x\n",ret));
1134 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3I");
1135 return ret;
1136}
1137
1152 agsaRoot_t *agRoot,
1153 bit32 queueNum,
1154 bit32 modePage,
1155 bit32 length,
1156 void *buffer,
1157 agsaContext_t *agContext
1158 )
1159{
1160 agsaSetControllerConfigCmd_t agControllerConfig;
1161 bit32 *src;
1162 bit32 i, ret;
1163
1165
1166
1167 if(smIS_SPCV(agRoot))
1168 {
1169
1170 SA_DBG2(("saSetControllerConfig: queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length ));
1171
1172 /* If the page is well known, validate the size of the buffer */
1173 if (((modePage == AGSA_INTERRUPT_CONFIGURATION_PAGE) && (length != sizeof(agsaInterruptConfigPage_t ))) ||
1174 ((modePage == AGSA_ENCRYPTION_DEK_CONFIG_PAGE) && (length != sizeof(agsaEncryptDekConfigPage_t))) ||
1175 ((modePage == AGSA_ENCRYPTION_CONTROL_PARM_PAGE) && (length != sizeof(agsaEncryptControlParamPage_t ))) ||
1176 ((modePage == AGSA_ENCRYPTION_HMAC_CONFIG_PAGE) && (length != sizeof(agsaEncryptHMACConfigPage_t ))) ||
1178 {
1179 SA_DBG1(("saSetControllerConfig: AGSA_RC_FAILURE queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length ));
1180 ret = AGSA_RC_FAILURE;
1181 }
1182 else if(modePage == AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE)
1183 {
1184 SA_DBG1(("saSetControllerConfig: Warning!!!!GENERAL_CONFIG_PAGE cannot be set\n"));
1185 ret = AGSA_RC_FAILURE;
1186 }
1187 else
1188 {
1189 /* Copy the raw mode page data into something that can be wrapped in an IOMB. */
1190 si_memset(&agControllerConfig, 0, sizeof(agsaSetControllerConfigCmd_t));
1191
1192 agControllerConfig.tag = 0; /*HTAG */
1193
1194 src = (bit32 *) buffer;
1195
1196 for (i = 0; i < (length / 4); i++)
1197 {
1198 OSSA_WRITE_LE_32(agRoot,
1199 &agControllerConfig,
1200 OSSA_OFFSET_OF(agsaSetControllerConfigCmd_t, pageCode) + (i * 4),
1201 *src);
1202
1203 src++;
1204 }
1205 ret = mpiSetControllerConfigCmd(agRoot, agContext, &agControllerConfig, queueNum,agFALSE);
1206 if(ret)
1207 {
1208 SA_DBG1(("saSetControllerConfig: AGSA_RC_FAILURE (sending) queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length ));
1209 }
1210
1211 }
1212 }
1213 else
1214 {
1215 SA_DBG1(("saSetControllerConfig: spcv only AGSA_RC_FAILURE queueNum %d modePage 0x%x length %d\n",queueNum,modePage,length ));
1216 ret = AGSA_RC_FAILURE;
1217 }
1218 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "34");
1219 return ret;
1220}
1221
1222
1235 agsaRoot_t *agRoot,
1236 bit32 queueNum,
1237 bit32 modePage,
1238 bit32 flag0,
1239 bit32 flag1,
1240 agsaContext_t *agContext
1241 )
1242{
1243 bit32 ret;
1244 agsaGetControllerConfigCmd_t agControllerConfig;
1245
1247
1248 SA_DBG2(("saGetControllerConfig, modePage 0x%x agContext %p flag0 0x%08x flag1 0x%08x\n",modePage,agContext, flag0, flag1 ));
1249 if(smIS_SPCV(agRoot))
1250 {
1251 si_memset(&agControllerConfig, 0, sizeof(agsaGetControllerConfigCmd_t));
1252
1253 agControllerConfig.pageCode = modePage;
1254 if(modePage == AGSA_INTERRUPT_CONFIGURATION_PAGE)
1255 {
1256 agControllerConfig.INT_VEC_MSK0 = flag0;
1257 agControllerConfig.INT_VEC_MSK1 = flag1;
1258 }
1259 ret = mpiGetControllerConfigCmd(agRoot, agContext, &agControllerConfig, queueNum);
1260 }
1261 else
1262 {
1263 SA_DBG1(("saGetControllerConfig: spcv only AGSA_RC_FAILURE queueNum %d modePage 0x%x flag0 0x%08x flag1 0x%08x\n",queueNum,modePage, flag0, flag1 ));
1264 ret = AGSA_RC_FAILURE;
1265 }
1266
1267 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "35");
1268 return ret;
1269}
1270
1272 agsaRoot_t *agRoot,
1273 agsaContext_t *agContext,
1274 bit32 queueNum,
1275 bit32 type,
1276 bit32 length,
1277 void *TestDescriptor)
1278{
1279 bit32 ret = AGSA_RC_SUCCESS;
1280
1281 agsaEncryptBist_t bist;
1283 si_memset(&bist, 0, (sizeof(agsaEncryptBist_t)));
1284
1285 SA_DBG1(("saEncryptSelftestExecute, enter\n" ));
1286 bist.r_subop = (type & 0xFF);
1287
1288 si_memcpy(&bist.testDiscption,TestDescriptor,length );
1289
1290 /* setup IOMB payload */
1291 ret = mpiEncryptBistCmd( agRoot, queueNum, agContext, &bist );
1292
1293 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2e");
1294
1295 return (ret);
1296}
1298 agsaRoot_t *agRoot,
1299 agsaContext_t *agContext,
1300 bit32 queueNum,
1301 bit32 flag,
1302 bit8 role,
1303 agsaID_t *id,
1304 agsaEncryptKekBlob_t *kblob)
1305{
1306 bit32 ret = AGSA_RC_SUCCESS;
1308
1310
1311 SA_DBG1(("saOperatorManagement, enter\n" ));
1312
1313 si_memset(&opmcmd, 0, sizeof(agsaOperatorMangmentCmd_t));
1314 /*role = ((flag & SA_OPR_MGMNT_FLAG_MASK) >> SA_OPR_MGMNT_FLAG_SHIFT);*/
1315
1316 flag = (flag & ~SA_OPR_MGMNT_FLAG_MASK);
1317
1318 opmcmd.OPRIDX_AUTIDX_R_KBF_PKT_OMO = flag;
1319
1320 opmcmd.IDString_Role[0] = (bit8)role;
1321 SA_DBG1(("saOperatorManagement, role 0x%X flags 0x%08X\n", role, opmcmd.OPRIDX_AUTIDX_R_KBF_PKT_OMO ));
1322
1323 si_memcpy(&opmcmd.IDString_Role[1], id->ID, AGSA_ID_SIZE);
1324 si_memcpy(&opmcmd.Kblob, kblob, sizeof(agsaEncryptKekBlob_t));
1325
1326 /* setup IOMB payload */
1327 ret = mpiOperatorManagementCmd(agRoot, queueNum, agContext, &opmcmd);
1328
1329 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2i");
1330
1331 return (ret);
1332}
1333
1334/*
1335 The command is for an operator to login to/logout from SPCve.
1336 Only when all IOs are quiesced, can an operator logout.
1337
1338 flag:
1339 Access type (ACS) [4 bits]
1340 0x1: login
1341 0x2: logout
1342 Others: reserved
1343 KEYopr pinned in the KEK RAM (PIN) [1 bit]
1344 0: not pinned, operator ID table will be searched during authentication.
1345 1: pinned, OPRIDX is referenced to unwrap the certificate.
1346 KEYopr Index in the KEK RAM (OPRIDX) [8 bits]
1347 If KEYopr is pinned in the KEK RAM, OPRIDX is to reference to the KEK for authentication
1348
1349 cert
1350 Operator Certificate (CERT) [40 bytes]
1351
1352 response calls ossaSetOperatorCB
1353*/
1354
1357 agsaRoot_t *agRoot,
1358 agsaContext_t *agContext,
1359 bit32 queueNum,
1360 bit32 flag,
1361 void *cert
1362 )
1363{
1364 bit32 ret = AGSA_RC_SUCCESS;
1365 agsaSetOperatorCmd_t SetOperatorCmd;
1366
1368 SA_DBG1(("saSetOperator, flag 0x%x cert %p\n",flag, cert));
1369
1370 /* initialize set operator IOMB */
1371 si_memset(&SetOperatorCmd, 0, sizeof(agsaSetOperatorCmd_t));
1372 SetOperatorCmd.OPRIDX_PIN_ACS = flag;
1373 si_memcpy((bit8*)SetOperatorCmd.cert, (bit8*)cert, 40);
1374
1375 /* setup IOMB payload */
1376 ret = mpiSetOperatorCmd(agRoot, queueNum, agContext, &SetOperatorCmd);
1377
1378 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3c");
1379 return (ret);
1380}
1381
1382/*
1383 The command is to get role and ID of either current or all operators from SPCve.
1384 Option
1385 0x1: current operator
1386 0x2: all operators
1387 Others: reserved
1388
1389 OprBufAddr
1390 the host buffer address to store the role and ID of all operators. Valid only when option == 0x2.
1391 Buffer size must be 1KB to store max 32 operators's role and ID.
1392 response calls ossaGetOperatorCB
1393*/
1396 agsaRoot_t *agRoot,
1397 agsaContext_t *agContext,
1398 bit32 queueNum,
1399 bit32 option,
1400 bit32 AddrHi,
1401 bit32 AddrLo
1402 )
1403{
1404 bit32 ret = AGSA_RC_SUCCESS;
1405 agsaGetOperatorCmd_t GetOperatorCmd;
1406
1408 SA_DBG1(("saGetOperator, option 0x%x 0x%08x_%08x\n",option,AddrHi,AddrLo ));
1409
1410 /* initialize get operator IOMB */
1411 si_memset(&GetOperatorCmd, 0, sizeof(agsaGetOperatorCmd_t));
1412 GetOperatorCmd.option = option;
1413 GetOperatorCmd.OprBufAddrLo = AddrLo;
1414 GetOperatorCmd.OprBufAddrHi = AddrHi;
1415
1416 /* setup IOMB payload */
1417 ret = mpiGetOperatorCmd(agRoot, queueNum, agContext, &GetOperatorCmd);
1418
1419 smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "3d");
1420
1421 return (ret);
1422}
1423
bit32 flags
Definition: encrypt_ioctl.h:2
bit32 dekBlobFormat
Definition: encrypt_ioctl.h:3
bit32 dekTableKeyEntrySize
Definition: encrypt_ioctl.h:4
bit32 wrapperKekIndex
Definition: encrypt_ioctl.h:1
bit32 dekTable
Definition: encrypt_ioctl.h:1
bit32 kekIndex
Definition: encrypt_ioctl.h:0
bit32 dekIndex
Definition: encrypt_ioctl.h:2
bit32 blobFormat
Definition: encrypt_ioctl.h:2
@ MPI_CATEGORY_SAS_SATA
Definition: mpi.h:80
#define smTraceFuncEnter(L, I)
Definition: mpidebug.h:238
#define smTraceFuncExit(L, S, I)
Definition: mpidebug.h:239
#define hpDBG_VERY_LOUD
Definition: mpidebug.h:100
#define OS_ASSERT(expr, message)
Definition: osdebug.h:56
unsigned short bit16
Definition: ostypes.h:98
#define agNULL
Definition: ostypes.h:151
#define GLOBAL
Definition: ostypes.h:131
unsigned int bit32
Definition: ostypes.h:99
#define agFALSE
Definition: ostypes.h:150
#define agTRUE
Definition: ostypes.h:149
unsigned char bit8
Definition: ostypes.h:97
#define SA_RESERVED_REQUEST_COUNT
Definition: sa.h:3597
#define AGSA_RC_BUSY
Definition: sa.h:782
#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE
Definition: sa.h:3155
#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE
Definition: sa.h:3158
#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD)
Definition: sa.h:39
#define AGSA_ID_SIZE
Definition: sa.h:3291
#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE
Definition: sa.h:3156
#define AGSA_INTERRUPT_CONFIGURATION_PAGE
Definition: sa.h:3153
#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE
Definition: sa.h:3157
#define OperatorAuthenticationEnable_AUT
Definition: sa.h:3215
#define agsaEncryptSMB
Definition: sa.h:1526
#define AGSA_PORT_CLEAN_UP
Definition: sa.h:1175
#define agsaEncryptCipherModeXTS
Definition: sa.h:1542
#define agsaEncryptSMF
Definition: sa.h:1524
#define agsaEncryptSMA
Definition: sa.h:1525
#define MAX_IO_DEVICE_ENTRIES
Definition: sa.h:3791
#define AGSA_RC_NOT_SUPPORTED
Definition: sa.h:789
#define ReturnToFactoryMode_ARF
Definition: sa.h:3216
#define AGSA_RC_FAILURE
Definition: sa.h:781
void(* ossaDIFEncryptionOffloadStartCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, agsaOffloadDifDetails_t *agsaOffloadDifDetails)
Definition: sa.h:3590
#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE
Definition: sa.h:3152
#define AGSA_PORT_HARD_RESET
Definition: sa.h:1174
#define AGSA_RC_SUCCESS
Definition: sa.h:780
#define SA_IDFRM_GET_SAS_ADDRESSLO(identFrame)
Definition: sa_spec.h:482
#define SA_IDFRM_GET_SAS_ADDRESSHI(identFrame)
Definition: sa_spec.h:485
#define SHIFT4
Definition: sadefs.h:205
#define IOMB_SIZE64
Definition: sadefs.h:60
#define LL_IOREQ_LOCKEQ_LOCK
Definition: sadefs.h:130
#define SHIFT14
Definition: sadefs.h:215
#define MARK_OFF
Definition: sadefs.h:185
#define LL_DEVICE_LOCK
Definition: sadefs.h:127
#define SAS_SATA_UNKNOWN_DEVICE
Definition: sadefs.h:175
#define AUTO_HARD_RESET_DEREG_FLAG
Definition: sadefs.h:272
#define PORTID_MASK
Definition: sadefs.h:75
#define SHIFT8
Definition: sadefs.h:209
#define LL_PORT_LOCK
Definition: sadefs.h:128
#define SHIFT16
Definition: sadefs.h:217
#define SHIFT24
Definition: sadefs.h:225
#define PORT_INVALIDATING
Definition: sadefs.h:165
#define AUTO_FW_CLEANUP_DEREG_FLAG
Definition: sadefs.h:273
#define SHIFT22
Definition: sadefs.h:223
This file defines global types.
#define SCRATCH_PAD1_V_RAAE_ERR
Definition: sahwreg.h:258
#define SCRATCH_PAD3_V_AUT
Definition: sahwreg.h:402
#define SCRATCH_PAD3_V_ENC_DISABLED
Definition: sahwreg.h:396
#define SCRATCH_PAD3_V_SMF_ENABLED
Definition: sahwreg.h:408
#define V_Scratchpad_3_Register
Definition: sahwreg.h:106
#define SCRATCH_PAD3_V_SMB_ENABLED
Definition: sahwreg.h:407
#define SCRATCH_PAD3_V_XTS_ENABLED
Definition: sahwreg.h:405
#define V_Scratchpad_1_Register
Definition: sahwreg.h:104
#define SCRATCH_PAD1_V_RAAE_MASK
Definition: sahwreg.h:257
#define SCRATCH_PAD3_V_ENC_ENA_ERR
Definition: sahwreg.h:398
#define SCRATCH_PAD3_V_ENC_MASK
Definition: sahwreg.h:400
#define SCRATCH_PAD3_V_SMA_ENABLED
Definition: sahwreg.h:406
#define SCRATCH_PAD3_V_ERR_CODE
Definition: sahwreg.h:410
#define SCRATCH_PAD3_V_ENC_READY
Definition: sahwreg.h:399
#define SCRATCH_PAD3_V_ARF
Definition: sahwreg.h:403
#define SCRATCH_PAD3_V_ENC_DIS_ERR
Definition: sahwreg.h:397
#define SCRATCH_PAD3_V_SM_MASK
Definition: sahwreg.h:409
#define saLlistIOAdd(pList, pLink)
Definition: sallist.h:185
#define saLlistIORemove(pList, pLink)
Definition: sallist.h:275
#define saLlistIOGetHead(pList)
Definition: sallist.h:307
#define saLlistAdd(pList, pLink)
saLlistAdd macro
Definition: sallist.h:176
#define saLlistIOGetCount(pList)
Definition: sallist.h:361
#define saLlistRemove(pList, pLink)
saLlistRemove macro
Definition: sallist.h:268
#define saLlistInitialize(pList)
saLlistInitialize macro
Definition: sallist.h:99
#define saLlistGetHead(pList)
saLlistGetHead macro
Definition: sallist.h:305
#define SA_DBG4(format)
Definition: samacro.h:203
#define SA_DBG1(format)
Definition: samacro.h:200
#define SA_DBG2(format)
Definition: samacro.h:201
#define SA_ASSERT
Definition: samacro.h:209
#define SA_DBG3(format)
Definition: samacro.h:202
GLOBAL bit32 mpiDekManagementCmd(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaDekManagementCmd_t *agDekMgmt, bit32 queueNum)
SAS Encryption DEK management command.
Definition: sampicmd.c:2372
GLOBAL bit32 mpiGetOperatorCmd(agsaRoot_t *agRoot, bit32 queueNum, agsaContext_t *agContext, agsaGetOperatorCmd_t *operatorcode)
This command sends get operator command.
Definition: sampicmd.c:2722
GLOBAL bit32 mpiEncryptBistCmd(agsaRoot_t *agRoot, bit32 queueNum, agsaContext_t *agContext, agsaEncryptBist_t *bist)
This command sends encrypt self test command.
Definition: sampicmd.c:2545
GLOBAL bit32 mpiSetOperatorCmd(agsaRoot_t *agRoot, bit32 queueNum, agsaContext_t *agContext, agsaSetOperatorCmd_t *operatorcode)
This command sends set operator command.
Definition: sampicmd.c:2637
GLOBAL bit32 mpiOperatorManagementCmd(agsaRoot_t *agRoot, bit32 queueNum, agsaContext_t *agContext, agsaOperatorMangmentCmd_t *operatorcode)
This command sends operator management command.
Definition: sampicmd.c:2462
GLOBAL bit32 mpiSetControllerConfigCmd(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaSetControllerConfigCmd_t *agControllerConfig, bit32 queueNum, bit8 modePageContext)
SAS Set Controller Configuration Command.
Definition: sampicmd.c:2099
GLOBAL bit32 mpiDIFEncryptionOffloadCmd(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 op, agsaDifEncPayload_t *agDifEncOffload, ossaDIFEncryptionOffloadStartCB_t agCB)
Definition: sampicmd.c:2790
GLOBAL bit32 mpiKekManagementCmd(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaKekManagementCmd_t *agKekMgmt, bit32 queueNum)
SAS Encryption KEK command.
Definition: sampicmd.c:2289
GLOBAL bit32 mpiGetControllerConfigCmd(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaGetControllerConfigCmd_t *agControllerConfig, bit32 queueNum)
SAS Get Controller Configuration Command.
Definition: sampicmd.c:2198
GLOBAL bit32 mpiBuildCmd(agsaRoot_t *agRoot, bit32 *payload, mpiMsgCategory_t category, bit16 opcode, bit16 size, bit32 queueNum)
Build a IOMB command and send to SPC.
Definition: sampicmd.c:94
#define KEK_MGMT_SUBOP_UPDATE
Definition: sampidefs.h:177
#define OPC_INB_PORT_CONTROL
Definition: sampidefs.h:67
#define DEK_MGMT_SUBOP_UPDATE
Definition: sampidefs.h:182
#define KEK_MGMT_SUBOP_INVALIDATE
Definition: sampidefs.h:176
#define KEK_MGMT_SUBOP_KEYCARDUPDATE
Definition: sampidefs.h:179
#define DEVICE_ID_BITS
Definition: sampidefs.h:1086
#define DEK_MGMT_SUBOP_INVALIDATE
Definition: sampidefs.h:181
GLOBAL FORCEINLINE void ossaSingleThreadedEnter(agsaRoot_t *agRoot, bit32 syncLockId)
ossaSingleThreadedEnter
Definition: ossacmnapi.c:3786
GLOBAL FORCEINLINE void ossaSingleThreadedLeave(agsaRoot_t *agRoot, bit32 syncLockId)
ossaSingleThreadedLeave
Definition: ossacmnapi.c:3827
GLOBAL FORCEINLINE bit32 ossaHwRegRead(agsaRoot_t *agRoot, bit32 regOffset)
Definition: ossacmnapi.c:3521
GLOBAL void siPortDeviceListRemove(agsaRoot_t *agRoot, agsaPort_t *pPort, agsaDeviceDesc_t *pDevice)
The function to remove a device descriptor.
Definition: saport.c:370
GLOBAL bit32 saEncryptKekInvalidate(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 kekIndex)
Definition: saport.c:929
bit32 gFPGA_TEST
Definition: sainit.c:56
GLOBAL void siPortDeviceRemove(agsaRoot_t *agRoot, agsaPort_t *pPort, agsaDeviceDesc_t *pDevice, bit32 unmap)
The function to remove a device descriptor.
Definition: saport.c:169
GLOBAL agsaDeviceDesc_t * siPortSATADeviceAdd(agsaRoot_t *agRoot, agsaPort_t *pPort, agsaDeviceDesc_t *pSTPBridge, bit8 *pSignature, bit8 pm, bit8 pmField, bit32 smpReqTimeout, bit32 itNexusTimeout, bit32 firstBurstSize, bit8 dTypeSRate, bit32 flag)
Add a SATA device to the discovery list of the port.
Definition: saport.c:238
GLOBAL agsaDeviceDesc_t * siPortSASDeviceAdd(agsaRoot_t *agRoot, agsaPort_t *pPort, agsaSASIdentify_t sasIdentify, bit32 sasInitiator, bit32 smpTimeout, bit32 itNexusTimeout, bit32 firstBurstSize, bit8 dTypeSRate, bit32 flag)
Add a SAS device to the discovery list of the port.
Definition: saport.c:60
GLOBAL bit32 saEncryptGetMode(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaEncryptInfo_t *encryptInfo)
Definition: saport.c:563
GLOBAL bit32 saEncryptDekCacheInvalidate(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 dekTable, bit32 dekIndex)
Definition: saport.c:1057
GLOBAL bit32 saOperatorManagement(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 flag, bit8 role, agsaID_t *id, agsaEncryptKekBlob_t *kblob)
Definition: saport.c:1297
__FBSDID("$FreeBSD$")
GLOBAL void siPortInvalid(agsaRoot_t *agRoot, agsaPort_t *pPort)
Invalid a port.
Definition: saport.c:331
GLOBAL bit32 saDIFEncryptionOffloadStart(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 op, agsaDifEncPayload_t *agsaDifEncPayload, ossaDIFEncryptionOffloadStartCB_t agCB)
Definition: saport.c:1111
GLOBAL bit32 saEncryptSelftestExecute(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 type, bit32 length, void *TestDescriptor)
Definition: saport.c:1271
GLOBAL bit32 saGetControllerConfig(agsaRoot_t *agRoot, bit32 queueNum, bit32 modePage, bit32 flag0, bit32 flag1, agsaContext_t *agContext)
Definition: saport.c:1234
GLOBAL bit32 saEncryptDekCacheUpdate(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 kekIndex, bit32 dekTableSelect, bit32 dekAddrHi, bit32 dekAddrLo, bit32 dekIndex, bit32 dekNumberOfEntries, bit32 dekBlobFormat, bit32 dekTableKeyEntrySize)
Definition: saport.c:973
GLOBAL bit32 saPortControl(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, agsaPortContext_t *agPortContext, bit32 portOperation, bit32 param0, bit32 param1)
Initiate a Port COntrol IOMB command.
Definition: saport.c:422
GLOBAL bit32 saSetControllerConfig(agsaRoot_t *agRoot, bit32 queueNum, bit32 modePage, bit32 length, void *buffer, agsaContext_t *agContext)
Definition: saport.c:1151
GLOBAL bit32 saGetOperator(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 option, bit32 AddrHi, bit32 AddrLo)
Definition: saport.c:1395
GLOBAL bit32 saSetOperator(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 flag, void *cert)
Definition: saport.c:1356
GLOBAL bit32 saEncryptKekUpdate(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, bit32 flags, bit32 newKekIndex, bit32 wrapperKekIndex, bit32 blobFormat, agsaEncryptKekBlob_t *encryptKekBlob)
Definition: saport.c:808
GLOBAL bit32 saEncryptSetMode(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 queueNum, agsaEncryptInfo_t *mode)
Definition: saport.c:710
GLOBAL FORCEINLINE void * si_memcpy(void *dst, void *src, bit32 count)
memcopy
Definition: sautil.c:76
GLOBAL FORCEINLINE void * si_memset(void *s, int c, bit32 n)
memset
Definition: sautil.c:104
GLOBAL bit32 smIS_SPCV(agsaRoot_t *agRoot)
Definition: sautil.c:502
data structure stores OS specific and LL specific context
Definition: sa.h:1658
void * osData
Definition: sa.h:1659
void * sdkData
Definition: sa.h:1660
the LL defined device descriptor
Definition: satypes.h:112
agsaDevHandle_t targetDevHandle
Definition: satypes.h:115
agsaDevHandle_t initiatorDevHandle
Definition: satypes.h:114
SALINK linkNode
Definition: satypes.h:113
agsaPort_t * pPort
Definition: satypes.h:117
bit32 DeviceMapIndex
Definition: satypes.h:123
agsaSASSATADevInfo_t devInfo
Definition: satypes.h:122
SALINK_LIST pendingIORequests
Definition: satypes.h:116
bit8 sasAddressHi[4]
Definition: sa.h:2580
bit8 devType_S_Rate
Definition: sa.h:2567
bit16 firstBurstSize
Definition: sa.h:2564
bit16 smpTimeout
Definition: sa.h:2562
bit8 sasAddressLo[4]
Definition: sa.h:2581
bit32 flag
Definition: sa.h:2582
bit16 it_NexusTimeout
Definition: sa.h:2563
void * DeviceHandle
Definition: satypes.h:195
bit32 DeviceIdFromFW
Definition: satypes.h:194
bit32 testDiscption[28]
Definition: sampidefs.h:1897
bit32 status
Definition: sa.h:3210
bit32 encryptionSecurityMode
Definition: sa.h:3209
bit32 flag
Definition: sa.h:3211
bit32 encryptionCipherMode
Definition: sa.h:3208
bit8 kekBlob[48]
Definition: sa.h:3278
the data structure of Get Operator Command
Definition: sampidefs.h:1868
Definition: sa.h:3292
bit8 ID[AGSA_ID_SIZE]
Definition: sa.h:3293
agsaIORequestDesc_t * IORequest
Definition: satypes.h:171
bit32 Tag
Definition: satypes.h:170
agsaContext_t * agContext
Definition: satypes.h:172
the LL defined IO request descriptor
Definition: satypes.h:132
the LLRoot
Definition: satypes.h:209
agsaDeviceMap_t DeviceMap[MAX_IO_DEVICE_ENTRIES]
Definition: satypes.h:245
SALINK_LIST freeIORequests
Definition: satypes.h:214
bit32 autoDeregDeviceflag[AGSA_MAX_VALID_PORTS]
Definition: satypes.h:333
SALINK_LIST freeReservedRequests
Definition: satypes.h:215
agsaIOMap_t IOMap[MAX_ACTIVE_IO_REQUESTS]
Definition: satypes.h:246
SALINK_LIST freeDevicesList
Definition: satypes.h:211
SALINK_LIST validPorts
Definition: satypes.h:225
SALINK_LIST freePorts
Definition: satypes.h:224
the data structure of Operator Mangement Command
Definition: sampidefs.h:1815
agsaEncryptKekBlob_t Kblob
Definition: sampidefs.h:1820
the data structure of Port Control Command
Definition: sampidefs.h:734
the port
Definition: satypes.h:64
bit32 status
Definition: satypes.h:69
SALINK_LIST listSASATADevices
Definition: satypes.h:67
bit32 tobedeleted
Definition: satypes.h:70
bit32 portId
Definition: satypes.h:71
SALINK linkNode
Definition: satypes.h:65
agsaDeviceInfo_t commonDevInfo
Definition: sa.h:2683
bit8 phyIdentifier
Definition: sa.h:2698
bit8 target_ssp_stp_smp
Definition: sa.h:2691
bit8 initiator_ssp_stp_smp
Definition: sa.h:2685
describe SAS IDENTIFY address frame
Definition: sa_spec.h:448
bit8 initiator_ssp_stp_smp
Definition: sa_spec.h:456
bit8 sasAddressLo[4]
Definition: sa_spec.h:471
bit8 phyIdentifier
Definition: sa_spec.h:473
bit8 target_ssp_stp_smp
Definition: sa_spec.h:462
bit8 sasAddressHi[4]
Definition: sa_spec.h:470
data structure for SAS protocol timer configuration page.
Definition: sa.h:3373
agsaDeviceInfo_t commonDevInfo
Definition: sa.h:2650
bit8 stpPhyIdentifier
Definition: sa.h:2664
bit8 portMultiplierField
Definition: sa.h:2658
the data structure of Set Operator Command
Definition: sampidefs.h:1844
agsaSATADeviceInfo_t sataDeviceInfo
Definition: satypes.h:103
agsaSASDeviceInfo_t sasDeviceInfo
Definition: satypes.h:102