The file defines the register offset of hardware. More...

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Data Structures
struct	spcv_hda_cmd_s

struct	spcv_hda_rsp_s

Macros
#define	MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */

#define	MSGU_HOST_INT_STATUS 0x08

#define	MSGU_HOST_INT_MASK 0x0C

#define	MSGU_IOPIB_INT_STATUS 0x18

#define	MSGU_IOPIB_INT_MASK 0x1C

#define	MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */

#define	MSGU_MSGU_CONTROL 0x24

#define	MSGU_ODR 0x3C /* RevB */

#define	MSGU_ODCR 0x40 /* RevB */

#define	MSGU_SCRATCH_PAD_0 0x44

#define	MSGU_SCRATCH_PAD_1 0x48

#define	MSGU_SCRATCH_PAD_2 0x4C

#define	MSGU_SCRATCH_PAD_3 0x50

#define	MSGU_HOST_SCRATCH_PAD_0 0x54

#define	MSGU_HOST_SCRATCH_PAD_1 0x58

#define	MSGU_HOST_SCRATCH_PAD_2 0x5C

#define	MSGU_HOST_SCRATCH_PAD_3 0x60

#define	MSGU_HOST_SCRATCH_PAD_4 0x64

#define	MSGU_HOST_SCRATCH_PAD_5 0x68

#define	MSGU_HOST_SCRATCH_PAD_6 0x6C

#define	MSGU_HOST_SCRATCH_PAD_7 0x70

#define	MSGU_ODMR 0x74 /* RevB */

#define	V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound Doorbell Set */

#define	V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound Doorbell Set */

#define	V_Inbound_Doorbell_Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Clear */

#define	V_Inbound_Doorbell_Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Clear */

#define	V_Inbound_Doorbell_Mask_Set_Register 0x10 /* Host RO Local R/W 0x10 MSGU - Inbound Doorbell Mask Set New in SPCv */

#define	V_Inbound_Doorbell_Mask_Set_RegisterU 0x14 /* Host RO Local R/W 0x14 MSGU - Inbound Doorbell Mask Set New in SPCv */

#define	V_Inbound_Doorbell_Mask_Clear_Register 0x18 /* Host RO Local W, R all 0s 0x18 MSGU - Inbound Doorbell Mask Clear New in SPCv */

#define	V_Inbound_Doorbell_Mask_Clear_RegisterU 0x1C /* Host RO Local W, R all 0s 0x1C MSGU - Inbound Doorbell Mask Clear New in SPCv */

#define	V_Outbound_Doorbell_Set_Register 0x20 /* Host RO Local R/W 0x20 MSGU - Outbound Doorbell Set */

#define	V_Outbound_Doorbell_Set_RegisterU 0x24 /* Host RO Local R/W 0x24 MSGU - Outbound Doorbell Set */

#define	V_Outbound_Doorbell_Clear_Register 0x28 /* Host W, R all 0s Local RO 0x28 MSGU - Outbound Doorbell Clear */

#define	V_Outbound_Doorbell_Clear_RegisterU 0x2C /* Host W, R all 0s Local RO 0x2C MSGU - Outbound Doorbell Clear */

#define	V_Outbound_Doorbell_Mask_Set_Register 0x30 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */

#define	V_Outbound_Doorbell_Mask_Set_RegisterU 0x34 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */

#define	V_Outbound_Doorbell_Mask_Clear_Register 0x38 /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */

#define	V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */

#define	V_Scratchpad_0_Register 0x44 /* Host RO Local R/W 0x120 MSGU - Scratchpad 0 */

#define	V_Scratchpad_1_Register 0x48 /* Host RO Local R/W 0x128 MSGU - Scratchpad 1 */

#define	V_Scratchpad_2_Register 0x4C /* Host RO Local R/W 0x130 MSGU - Scratchpad 2 */

#define	V_Scratchpad_3_Register 0x50 /* Host RO Local R/W 0x138 MSGU - Scratchpad 3 */

#define	V_Host_Scratchpad_0_Register 0x54 /* Host RW Local RO 0x140 MSGU - Scratchpad 4 */

#define	V_Host_Scratchpad_1_Register 0x58 /* Host RW Local RO 0x148 MSGU - Scratchpad 5 */

#define	V_Host_Scratchpad_2_Register 0x5C /* Host RW Local RO 0x150 MSGU - Scratchpad 6 */

#define	V_Host_Scratchpad_3_Register 0x60 /* Host RW Local RO 0x158 MSGU - Scratchpad 7 */

#define	V_Host_Scratchpad_4_Register 0x64 /* Host RW Local R/W 0x160 MSGU - Scratchpad 8 */

#define	V_Host_Scratchpad_5_Register 0x68 /* Host RW Local R/W 0x168 MSGU - Scratchpad 9 */

#define	V_Scratchpad_Rsvd_0_Register 0x6C /* Host RW Local R/W 0x170 MSGU - Scratchpad 10 */

#define	V_Scratchpad_Rsvd_1_Register 0x70 /* Host RW Local R/W 0x178 MSGU - Scratchpad 11 */

#define	V_Outbound_Queue_Consumer_Indices_Base 0x100 /* typical value real offset is read from table to 0x1FF Host RW Local RO 0x1F100 � 0x1F1FF In DQ storage area*/

#define	V_Inbound_Queue_Producer_Indices 0x200 /* typical value real offset is read from table to 0x3FF Host RW Local RO 0x1F200 � 0x1F3FF In DQ storage area, also mapped as WSM*/

#define	V_RamEccDbErr 0x00000018

#define	V_SoftResetRegister 0x1000

#define	V_MEMBASE_II_ShiftRegister 0x1010

#define	V_GsmConfigReset 0

#define	V_GsmReadAddrParityCheck 0x38

#define	V_GsmWriteAddrParityCheck 0x40

#define	V_GsmWriteDataParityCheck 0x48

#define	V_GsmReadAddrParityIndic 0x58

#define	V_GsmWriteAddrParityIndic 0x60

#define	V_GsmWriteDataParityIndic 0x68

#define	SPCv_Reset_Reserved 0xFFFFFF3C

#define	SPCv_Reset_Read_Mask 0xC0

#define	SPCv_Reset_Read_NoReset 0x0

#define	SPCv_Reset_Read_NormalResetOccurred 0x40

#define	SPCv_Reset_Read_SoftResetHDAOccurred 0x80

#define	SPCv_Reset_Read_ChipResetOccurred 0xC0

#define	SPCv_Reset_Write_NormalReset 0x1

#define	SPCv_Reset_Write_SoftResetHDA 0x2

#define	SPCv_Reset_Write_ChipReset 0x3

#define	SPC_ODAR 0x00335C

#define	SPC_ICTIMER 0x0033C0

#define	SPC_ICCONTROL 0x0033C4

#define	MSGU_XCBI_IBDB_REG 0x003034 /* PCIE - Message Unit Inbound Doorbell register */

#define	MSGU_XCBI_OBDB_REG 0x003354 /* PCIE - Message Unit Outbound Doorbell Interrupt Register */

#define	MSGU_XCBI_OBDB_MASK 0x003358 /* PCIE - Message Unit Outbound Doorbell Interrupt Mask Register */

#define	MSGU_XCBI_OBDB_CLEAR 0x00303C /* PCIE - Message Unit Outbound Doorbell Interrupt Clear Register */

#define	SPC_RB6_OFFSET 0x80C0

#define	RB6_MAGIC_NUMBER_RST 0x1234 /* Magic number of soft reset for RB6 */

#define	MSGU_READ_IDR siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET)

#define	MSGU_READ_ODMR siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR)

#define	MSGU_READ_ODR siHalRegReadExt(agRoot, GEN_MSGU_ODR, MSGU_ODR)

#define	MSGU_READ_ODCR siHalRegReadExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR)

#define	ODMR_MASK_ALL 0xFFFFFFFF /* mask all interrupt vector */

#define	ODMR_CLEAR_ALL 0 /* clear all interrupt vector */

#define	ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all interrupt vector */

#define	IBDB_IBQ_UNFREEZE 0x08 /* Inbound doorbell bit3 */

#define	IBDB_IBQ_FREEZE 0x04 /* Inbound doorbell bit2 */

#define	IBDB_CFG_TABLE_RESET 0x02 /* Inbound doorbell bit1 */

#define	IBDB_CFG_TABLE_UPDATE 0x01 /* Inbound doorbell bit0 */

#define	IBDB_MPIIU 0x08 /* Inbound doorbell bit3 - Unfreeze */

#define	IBDB_MPIIF 0x04 /* Inbound doorbell bit2 - Freeze */

#define	IBDB_MPICT 0x02 /* Inbound doorbell bit1 - Termination */

#define	IBDB_MPIINI 0x01 /* Inbound doorbell bit0 - Initialization */

#define	SCRATCH_PAD0_BAR_MASK 0xFC000000 /* bit31-26 - mask bar */

#define	SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF /* bit25-0 - offset mask */

#define	SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF /* if AAP error state */

#define	SCRATCH_PAD1_POR 0x00 /* power on reset state */

#define	SCRATCH_PAD1_SFR 0x01 /* soft reset state */

#define	SCRATCH_PAD1_ERR 0x02 /* error state */

#define	SCRATCH_PAD1_RDY 0x03 /* ready state */

#define	SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */

#define	SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */

#define	SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 Mask other bits 31:4, bit1-0 State */

#define	SCRATCH_PAD1_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */

#define	SCRATCH_PAD1_V_RAAE_MASK 0x00000003 /* 0 1 also ready */

#define	SCRATCH_PAD1_V_RAAE_ERR 0x00000002 /* 1 */

#define	SCRATCH_PAD1_V_ILA_MASK 0x0000000C /* 2 3 also ready */

#define	SCRATCH_PAD1_V_ILA_ERR 0x00000008 /* 3 */

#define	SCRATCH_PAD1_V_BOOTSTATE_MASK 0x00000070 /* 456 */

#define	SCRATCH_PAD1_V_BOOTSTATE_SUCESS 0x00000000 /* Load successful */

#define	SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM 0x00000010 /* HDA Mode SEEPROM Setting */

#define	SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP 0x00000020 /* HDA Mode BootStrap Setting */

#define	SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030 /* HDA Mode Soft Reset */

#define	SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR 0x00000040 /* HDA Mode due to critical error */

#define	SCRATCH_PAD1_V_BOOTSTATE_R1 0x00000050 /* Reserved */

#define	SCRATCH_PAD1_V_BOOTSTATE_R2 0x00000060 /* Reserved */

#define	SCRATCH_PAD1_V_BOOTSTATE_FATAL 0x00000070 /* Fatal Error Boot process halted */

#define	SCRATCH_PAD1_V_ILA_IMAGE 0x00000080 /* 7 */

#define	SCRATCH_PAD1_V_FW_IMAGE 0x00000100 /* 8 */

#define	SCRATCH_PAD1_V_BIT9_RESERVED 0x00000200 /* 9 */

#define	SCRATCH_PAD1_V_IOP0_MASK 0x00000C00 /* 10 11 also ready */

#define	SCRATCH_PAD1_V_IOP0_ERR 0x00000800 /* 11 */

#define	SCRATCH_PAD1_V_IOP1_MASK 0x00003000 /* 12 13 also ready */

#define	SCRATCH_PAD1_V_IOP1_ERR 0x00002000 /* 13 */

#define	SCRATCH_PAD1_V_RESERVED 0xFFFFC000 /* 14-31 */

#define	SCRATCH_PAD1_V_READY ( SCRATCH_PAD1_V_RAAE_MASK \| SCRATCH_PAD1_V_ILA_MASK \| SCRATCH_PAD1_V_IOP0_MASK ) /* */

#define	SCRATCH_PAD1_V_ERROR ( SCRATCH_PAD1_V_RAAE_ERR \| SCRATCH_PAD1_V_ILA_ERR \| SCRATCH_PAD1_V_IOP0_ERR \| SCRATCH_PAD1_V_IOP1_ERR ) /* Scratch Pad1 13 11 3 1 */

#define	SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1)

#define	SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1)

#define	SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1)

#define	SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1)

#define	SCRATCH_PAD1_V_ERROR_STATE(ScratchPad1)

#define	SCRATCH_PAD1_V_BOOTLDR_ERROR 0x00000070 /* Scratch Pad1 (6 5 4) */

#define	SCRATCH_PAD1_BDMA_ERR 0x80000000 /* bit31 */

#define	SCRATCH_PAD1_GSM_ERR 0x40000000 /* bit30 */

#define	SCRATCH_PAD1_MBIC1_ERR 0x20000000 /* bit29 */

#define	SCRATCH_PAD1_MBIC1_SET0_ERR 0x10000000 /* bit28 */

#define	SCRATCH_PAD1_MBIC1_SET1_ERR 0x08000000 /* bit27 */

#define	SCRATCH_PAD1_PMIC1_ERR 0x04000000 /* bit26 */

#define	SCRATCH_PAD1_PMIC2_ERR 0x02000000 /* bit25 */

#define	SCRATCH_PAD1_PMIC_EVENT_ERR 0x01000000 /* bit24 */

#define	SCRATCH_PAD1_OSSP_ERR 0x00800000 /* bit23 */

#define	SCRATCH_PAD1_SSPA_ERR 0x00400000 /* bit22 */

#define	SCRATCH_PAD1_SSPL_ERR 0x00200000 /* bit21 */

#define	SCRATCH_PAD1_HSST_ERR 0x00100000 /* bit20 */

#define	SCRATCH_PAD1_PCS_ERR 0x00080000 /* bit19 */

#define	SCRATCH_PAD1_FW_INIT_ERR 0x00008000 /* bit15 */

#define	SCRATCH_PAD1_FW_ASRT_ERR 0x00004000 /* bit14 */

#define	SCRATCH_PAD1_FW_WDG_ERR 0x00002000 /* bit13 */

#define	SCRATCH_PAD1_AAP_ERROR_STATE 0x00000002 /* bit1 */

#define	SCRATCH_PAD1_AAP_READY 0x00000003 /* bit1 & bit0 */

#define	SCRATCH_PAD2_POR 0x00 /* power on state */

#define	SCRATCH_PAD2_SFR 0x01 /* soft reset state */

#define	SCRATCH_PAD2_ERR 0x02 /* error state */

#define	SCRATCH_PAD2_RDY 0x03 /* ready state */

#define	SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset rdy flag */

#define	SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */

#define	SCRATCH_PAD2_STATE_MASK 0xFFFFFFF0 /* ScratchPad 2 Mask for other bits 31:4, bit1-0 State*/

#define	SCRATCH_PAD2_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */

#define	SCRATCH_PAD2_BDMA_ERR 0x80000000 /* bit31 */

#define	SCRATCH_PAD2_GSM_ERR 0x40000000 /* bit30 */

#define	SCRATCH_PAD2_MBIC3_ERR 0x20000000 /* bit29 */

#define	SCRATCH_PAD2_MBIC3_SET0_ERR 0x10000000 /* bit28 */

#define	SCRATCH_PAD2_MBIC3_SET1_ERR 0x08000000 /* bit27 */

#define	SCRATCH_PAD2_PMIC1_ERR 0x04000000 /* bit26 */

#define	SCRATCH_PAD2_PMIC2_ERR 0x02000000 /* bit25 */

#define	SCRATCH_PAD2_PMIC_EVENT_ERR 0x01000000 /* bit24 */

#define	SCRATCH_PAD2_OSSP_ERR 0x00800000 /* bit23 */

#define	SCRATCH_PAD2_SSPA_ERR 0x00400000 /* bit22 */

#define	SCRATCH_PAD2_SSPL_ERR 0x00200000 /* bit21 */

#define	SCRATCH_PAD2_HSST_ERR 0x00100000 /* bit20 */

#define	SCRATCH_PAD2_PCS_ERR 0x00080000 /* bit19 */

#define	SCRATCH_PAD2_FW_BOOT_ROM_ERROR 0x00010000 /* bit16 */

#define	SCRATCH_PAD2_FW_ILA_ERR 0x00008000 /* bit15 */

#define	SCRATCH_PAD2_FW_FLM_ERR 0x00004000 /* bit14 */

#define	SCRATCH_PAD2_FW_FW_ASRT_ERR 0x00002000 /* bit13 */

#define	SCRATCH_PAD2_FW_HW_WDG_ERR 0x00001000 /* bit12 */

#define	SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x00000800 /* bit11 */

#define	SCRATCH_PAD2_FW_UNDTMN_ERR 0x00000400 /* bit10 */

#define	SCRATCH_PAD2_FW_HW_FATAL_ERR 0x00000200 /* bit9 */

#define	SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x00000100 /* bit8 */

#define	SCRATCH_PAD2_FW_HW_MASK 0x000000FF

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x00

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x01

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x02

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x03

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x04

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x05

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x06

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x08

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x0C

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x0E

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x0F

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x10

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x13

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x14

#define	SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF

#define	SCRATCH_PAD_ERROR_MASK 0xFFFFFF00 /* Error mask bits 31:8 */

#define	SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits 1:0 */

#define	SPCV_RAAE_STATE_MASK 0x3

#define	SPCV_IOP0_STATE_MASK ((1 << 10) \| (1 << 11))

#define	SPCV_IOP1_STATE_MASK ((1 << 12) \| (1 << 13))

#define	SPCV_ERROR_VALUE 0x2

#define	SCRATCH_PAD3_FW_IMAGE_MASK 0x0000000F /* SPC 8x6G boots from Image */

#define	SCRATCH_PAD3_FW_IMAGE_FLAG_VALID 0x00000008 /* Image flag is valid */

#define	SCRATCH_PAD3_FW_IMAGE_B_VALID 0x00000004 /* Image B is valid */

#define	SCRATCH_PAD3_FW_IMAGE_A_VALID 0x00000002 /* Image A is valid */

#define	SCRATCH_PAD3_FW_IMAGE_B_ACTIVE 0x00000001 /* Image B is active */

#define	SCRATCH_PAD3_V_ 0x00000001 /* Image B is valid */

#define	SCRATCH_PAD3_V_ENC_DISABLED 0x00000000 /* */

#define	SCRATCH_PAD3_V_ENC_DIS_ERR 0x00000001 /* */

#define	SCRATCH_PAD3_V_ENC_ENA_ERR 0x00000002 /* */

#define	SCRATCH_PAD3_V_ENC_READY 0x00000003 /* */

#define	SCRATCH_PAD3_V_ENC_MASK SCRATCH_PAD3_V_ENC_READY /* */

#define	SCRATCH_PAD3_V_AUT 0x00000008 /* AUT Operator authentication*/

#define	SCRATCH_PAD3_V_ARF 0x00000004 /* ARF factory mode. */

#define	SCRATCH_PAD3_V_XTS_ENABLED (1 << SHIFT14) /* */

#define	SCRATCH_PAD3_V_SMA_ENABLED (1 << SHIFT4 ) /* */

#define	SCRATCH_PAD3_V_SMB_ENABLED (1 << SHIFT5 ) /* */

#define	SCRATCH_PAD3_V_SMF_ENABLED 0 /* */

#define	SCRATCH_PAD3_V_SM_MASK 0x000000F0 /* */

#define	SCRATCH_PAD3_V_ERR_CODE 0x00FF0000 /* */

#define	GSM_CONFIG_RESET 0x00000000

#define	RAM_ECC_DB_ERR 0x00000018

#define	GSM_READ_ADDR_PARITY_INDIC 0x00000058

#define	GSM_WRITE_ADDR_PARITY_INDIC 0x00000060

#define	GSM_WRITE_DATA_PARITY_INDIC 0x00000068

#define	GSM_READ_ADDR_PARITY_CHECK 0x00000038

#define	GSM_WRITE_ADDR_PARITY_CHECK 0x00000040

#define	GSM_WRITE_DATA_PARITY_CHECK 0x00000048

#define	SPC_SOFT_RESET_SIGNATURE 0x252acbcd /* Signature for Soft Reset */

#define	SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7 /* Signature for HDA Soft Reset without PCIe resetting */

#define	SPC_REG_RESET 0x000000 /* reset register */

#define	SPC_REG_DEVICE_LCLK 0x000058 /* Device LCLK generation register */

#define	SPC_READ_RESET_REG siHalRegReadExt(agRoot, GEN_SPC_REG_RESET, SPC_REG_RESET)

#define	SPC_WRITE_RESET_REG(value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value);

#define	MBIC_NMI_ENABLE_VPE0_IOP 0x000418

#define	MBIC_NMI_ENABLE_VPE0_AAP1 0x000418

#define	PCIE_EVENT_INTERRUPT_ENABLE 0x003040

#define	PCIE_EVENT_INTERRUPT 0x003044

#define	PCIE_ERROR_INTERRUPT_ENABLE 0x003048

#define	PCIE_ERROR_INTERRUPT 0x00304C

#define	SPC_REG_MSGU_CONFIG 0x003018

#define	PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010

#define	SPC_REG_RESET_OSSP 0x00000001

#define	SPC_REG_RESET_RAAE 0x00000002

#define	SPC_REG_RESET_PCS_SPBC 0x00000004

#define	SPC_REG_RESET_PCS_IOP_SS 0x00000008

#define	SPC_REG_RESET_PCS_AAP1_SS 0x00000010

#define	SPC_REG_RESET_PCS_AAP2_SS 0x00000020

#define	SPC_REG_RESET_PCS_LM 0x00000040

#define	SPC_REG_RESET_PCS 0x00000080

#define	SPC_REG_RESET_GSM 0x00000100

#define	SPC_REG_RESET_DDR2 0x00010000

#define	SPC_REG_RESET_BDMA_CORE 0x00020000

#define	SPC_REG_RESET_BDMA_SXCBI 0x00040000

#define	SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000

#define	SPC_REG_RESET_PCIE_PWR 0x00100000

#define	SPC_REG_RESET_PCIE_SFT 0x00200000

#define	SPC_REG_RESET_PCS_SXCBI 0x00400000

#define	SPC_REG_RESET_LMS_SXCBI 0x00800000

#define	SPC_REG_RESET_PMIC_SXCBI 0x01000000

#define	SPC_REG_RESET_PMIC_CORE 0x02000000

#define	SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000

#define	SPC_REG_RESET_DEVICE 0x80000000

#define	SPC_REG_DEVICE_REV 0x000024

#define	SPC_REG_DEVICE_REV_MASK 0x0000000F

#define	SPC_REG_TOP_DEVICE_ID 0x20

#define	SPC_TOP_DEVICE_ID 0x8001

#define	SPC_REG_TOP_BOOT_STRAP 0x8

#define	SPC_TOP_BOOT_STRAP 0x02C0A682

#define	COUNT_OFFSET 0x4000

#define	LCLK_CLEAR 0x2

#define	LCLK 0x1

#define	CNTL_OFFSET 0x100

#define	L0_LCLK_CLEAR 0x2

#define	L0_LCLK 0x1

#define	DEVICE_LCLK_CLEAR 0x40

#define	SPC_SSPL_COUNTER_CNTL 0x001030

#define	SPC_INVALID_DW_COUNT 0x001034

#define	SPC_RUN_DISP_ERROR_COUNT 0x001038

#define	SPC_CODE_VIOLATION_COUNT 0x00103C

#define	SPC_LOSS_DW_SYNC_COUNT 0x001040

#define	SPC_PHY_RESET_PROBLEM_COUNT 0x001044

#define	SPC_READ_DEV_REV ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_REV);

#define	SPC_READ_COUNTER_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId))

#define	SPC_WRITE_COUNTER_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId), value)

#define	SPC_READ_INV_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_INVALID_DW_COUNT + (COUNT_OFFSET * phyId))

#define	SPC_READ_DISP_ERR_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_RUN_DISP_ERROR_COUNT + (COUNT_OFFSET * phyId))

#define	SPC_READ_CODE_VIO_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_CODE_VIOLATION_COUNT + (COUNT_OFFSET * phyId))

#define	SPC_READ_LOSS_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_LOSS_DW_SYNC_COUNT + (COUNT_OFFSET * phyId))

#define	SPC_READ_PHY_RESET_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_PHY_RESET_PROBLEM_COUNT + (COUNT_OFFSET * phyId))

#define	SPC_L0_ERR_CNT_CNTL 0x0041B0

#define	SPC_READ_L0ERR_CNT_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId))

#define	SPC_WRITE_L0ERR_CNT_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value)

#define	SPC_IBW_AXI_TRANSLATION_LOW 0x003258

#define	HDA_CMD_OFFSET256K 0x0003FFC0

#define	HDA_RSP_OFFSET256K 0x0003FFE0

#define	HDA_CMD_OFFSET512K 0x0007FFC0

#define	HDA_RSP_OFFSET512K 0x0007FFE0

#define	HDA_CMD_OFFSET768K 0x000BFFC0

#define	HDA_RSP_OFFSET768K 0x000BFFE0

#define	HDA_CMD_OFFSET1MB 0x0000FEC0

#define	HDA_RSP_OFFSET1MB 0x0000FEE0

#define	SPC_V_HDA_COMMAND_OFFSET 0x000042c0

#define	SPC_V_HDA_RESPONSE_OFFSET 0x000042e0

#define	HDA_C_PA_OFFSET 0x1F

#define	HDA_SEQ_ID_OFFSET 0x1E

#define	HDA_PAR_LEN_OFFSET 0x04

#define	HDA_CMD_CODE_OFFSET 0x1C

#define	HDA_RSP_CODE_OFFSET 0x1C

#define	SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET (HDA_RSP_OFFSET1MB + HDA_RSP_CODE_OFFSET)

#define	SPC_V_HDAC_PA 0xCB

#define	SPC_V_HDAC_BUF_INFO 0x0001

#define	SPC_V_HDAC_EXEC 0x0002

#define	SPC_V_HDAC_RESET 0x0003

#define	SPC_V_HDAC_DMA 0x0004

#define	SPC_V_HDAC_PA_MASK 0xFF000000

#define	SPC_V_HDAC_SEQID_MASK 0x00FF0000

#define	SPC_V_HDAC_CMDCODE_MASK 0x0000FFFF

#define	SPC_V_HDAR_PA 0xDB

#define	SPC_V_HDAR_BUF_INFO 0x8001

#define	SPC_V_HDAR_IDLE 0x8002

#define	SPC_V_HDAR_BAD_IMG 0x8003

#define	SPC_V_HDAR_BAD_CMD 0x8004

#define	SPC_V_HDAR_INTL_ERR 0x8005

#define	SPC_V_HDAR_EXEC 0x8006

#define	SPC_V_HDAR_PA_MASK 0xFF000000

#define	SPC_V_HDAR_SEQID_MASK 0x00FF0000

#define	SPC_V_HDAR_RSPCODE_MASK 0x0000FFFF

#define	ILAHDA_RAAE_IMG_GET 0x11

#define	ILAHDA_IOP_IMG_GET 0x10

#define	ILAHDAC_RAAE_IMG_DONE 0x81

#define	HDA_AES_DIF_FUNC 0xFEDFAE1F

#define	PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE 0x00000001

#define	PMIC_MU_CFG_1_BITMSK_MU_IO_WIR 0x0000000C

#define	PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010

#define	PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET 0xFFFFFC00

#define	MU_MEM_OFFSET 0x0

#define	MSGU_MU_IO_WIR 0x8 /* Window 0 */

#define	BOOTTLOADERHDA_IDLE 0x8002

#define	HDAR_BAD_IMG 0x8003

#define	HDAR_BAD_CMD 0x8004

#define	HDAR_EXEC 0x8006

#define	CEILING(X, rem) ((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem))

#define	GSMSM_AXI_LOWERADDR 0x00400000

#define	SHIFT_MASK 0xFFFF0000

#define	OFFSET_MASK 0x0000FFFF

#define	SIZE_64KB 0x00010000

#define	ILA_ISTR_ADDROFFSETHDA 0x0007E000

#define	HDA_STATUS_BITS 0x0000FFFF

#define	ILAHDA_IOP_IMG_GET 0x10

#define	ILAHDA_AAP1_IMG_GET 0x11

#define	ILAHDA_AAP2_IMG_GET 0x12

#define	ILAHDA_EXITGOOD 0x1F

#define	ILAHDAC_IOP_IMG_DONE 0x00000080

#define	ILAHDAC_AAP1_IMG_DONE 0x00000081

#define	ILAHDAC_AAP2_IMG_DONE 0x00000082

#define	ILAHDAC_ISTR_IMG_DONE 0x00000083

#define	ILAHDAC_GOTOHDA 0x000000ff

#define	HDA_ISTR_DONE (bit32)(ILAHDAC_ISTR_IMG_DONE << 24)

#define	HDA_AAP1_DONE (bit32)(ILAHDAC_AAP1_IMG_DONE << 24)

#define	HDA_IOP_DONE (bit32)(ILAHDAC_IOP_IMG_DONE << 24)

#define	RB6_ACCESS_REG 0x6A0000

#define	HDAC_EXEC_CMD 0x0002

#define	HDA_C_PA 0xcb

#define	HDA_SEQ_ID_BITS 0x00ff0000

#define	HDA_GSM_OFFSET_BITS 0x00FFFFFF

#define	MBIC_AAP1_ADDR_BASE 0x060000

#define	MBIC_GSM_SM_BASE 0x04F0000

#define	MBIC_IOP_ADDR_BASE 0x070000

#define	GSM_ADDR_BASE 0x0700000

#define	SPC_TOP_LEVEL_ADDR_BASE 0x000000

#define	GSM_CONFIG_RESET_VALUE 0x00003b00

#define	GPIO_ADDR_BASE 0x00090000

#define	GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c

#define	SA_FATAL_ERROR_SP1_AAP1_ERR_MASK 0x3

#define	SA_FATAL_ERROR_SP2_IOP_ERR_MASK 0x3

#define	SA_FATAL_ERROR_FATAL_ERROR 0x2

#define	PCIE_TRIGGER_ON_REGISTER_READ V_Host_Scratchpad_2_Register /* PCI trigger on this offset */

#define	PCI_TRIGGER_INIT_TEST 1 /* Setting adjustable paramater PciTrigger to match this value */

#define	PCI_TRIGGER_OFFSET_MISMATCH 2 /* Setting adjustable paramater PciTrigger to match this value */

#define	PCI_TRIGGER_COAL_IOMB_ERROR 4 /* Setting adjustable paramater PciTrigger to match this value */

#define	PCI_TRIGGER_COAL_INVALID 8 /* Setting adjustable paramater PciTrigger to match this value */

Typedefs
typedef struct spcv_hda_cmd_s	spcv_hda_cmd_t

typedef struct spcv_hda_rsp_s	spcv_hda_rsp_t

Enumerations
enum	spc_spcv_offsetmap_e { GEN_MSGU_IBDB_SET =0 , GEN_MSGU_ODR , GEN_MSGU_ODCR , GEN_MSGU_SCRATCH_PAD_0 , GEN_MSGU_SCRATCH_PAD_1 , GEN_MSGU_SCRATCH_PAD_2 , GEN_MSGU_SCRATCH_PAD_3 , GEN_MSGU_HOST_SCRATCH_PAD_0 , GEN_MSGU_HOST_SCRATCH_PAD_1 , GEN_MSGU_HOST_SCRATCH_PAD_2 , GEN_MSGU_HOST_SCRATCH_PAD_3 , GEN_MSGU_ODMR , GEN_PCIE_TRIGGER , GEN_SPC_REG_RESET }

Detailed Description

The file defines the register offset of hardware.

Definition in file sahwreg.h.

Macro Definition Documentation

◆ BOOTTLOADERHDA_IDLE

#define BOOTTLOADERHDA_IDLE 0x8002

Definition at line 621 of file sahwreg.h.

◆ CEILING

#define CEILING	(	X,
		rem
	)	((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem))

Definition at line 626 of file sahwreg.h.

◆ CNTL_OFFSET

#define CNTL_OFFSET 0x100

Definition at line 492 of file sahwreg.h.

◆ COUNT_OFFSET

#define COUNT_OFFSET 0x4000

Definition at line 489 of file sahwreg.h.

◆ DEVICE_LCLK_CLEAR

#define DEVICE_LCLK_CLEAR 0x40

Definition at line 495 of file sahwreg.h.

◆ GPIO_ADDR_BASE

#define GPIO_ADDR_BASE 0x00090000

Definition at line 664 of file sahwreg.h.

◆ GPIO_GPIO_0_0UTPUT_CTL_OFFSET

#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c

Definition at line 665 of file sahwreg.h.

◆ GSM_ADDR_BASE

#define GSM_ADDR_BASE 0x0700000

Definition at line 661 of file sahwreg.h.

◆ GSM_CONFIG_RESET

#define GSM_CONFIG_RESET 0x00000000

Definition at line 414 of file sahwreg.h.

◆ GSM_CONFIG_RESET_VALUE

#define GSM_CONFIG_RESET_VALUE 0x00003b00

Definition at line 663 of file sahwreg.h.

◆ GSM_READ_ADDR_PARITY_CHECK

#define GSM_READ_ADDR_PARITY_CHECK 0x00000038

Definition at line 419 of file sahwreg.h.

◆ GSM_READ_ADDR_PARITY_INDIC

#define GSM_READ_ADDR_PARITY_INDIC 0x00000058

Definition at line 416 of file sahwreg.h.

◆ GSM_WRITE_ADDR_PARITY_CHECK

#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040

Definition at line 420 of file sahwreg.h.

◆ GSM_WRITE_ADDR_PARITY_INDIC

#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060

Definition at line 417 of file sahwreg.h.

◆ GSM_WRITE_DATA_PARITY_CHECK

#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048

Definition at line 421 of file sahwreg.h.

◆ GSM_WRITE_DATA_PARITY_INDIC

#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068

Definition at line 418 of file sahwreg.h.

◆ GSMSM_AXI_LOWERADDR

#define GSMSM_AXI_LOWERADDR 0x00400000

Definition at line 628 of file sahwreg.h.

◆ HDA_AAP1_DONE

#define HDA_AAP1_DONE (bit32)(ILAHDAC_AAP1_IMG_DONE << 24)

Definition at line 650 of file sahwreg.h.

◆ HDA_AES_DIF_FUNC

#define HDA_AES_DIF_FUNC 0xFEDFAE1F

Definition at line 608 of file sahwreg.h.

◆ HDA_C_PA

#define HDA_C_PA 0xcb

Definition at line 655 of file sahwreg.h.

◆ HDA_C_PA_OFFSET

#define HDA_C_PA_OFFSET 0x1F

Definition at line 571 of file sahwreg.h.

◆ HDA_CMD_CODE_OFFSET

#define HDA_CMD_CODE_OFFSET 0x1C

Definition at line 574 of file sahwreg.h.

◆ HDA_CMD_OFFSET1MB

#define HDA_CMD_OFFSET1MB 0x0000FEC0

Definition at line 536 of file sahwreg.h.

◆ HDA_CMD_OFFSET256K

#define HDA_CMD_OFFSET256K 0x0003FFC0

Definition at line 524 of file sahwreg.h.

◆ HDA_CMD_OFFSET512K

#define HDA_CMD_OFFSET512K 0x0007FFC0

Definition at line 528 of file sahwreg.h.

◆ HDA_CMD_OFFSET768K

#define HDA_CMD_OFFSET768K 0x000BFFC0

Definition at line 532 of file sahwreg.h.

◆ HDA_GSM_OFFSET_BITS

#define HDA_GSM_OFFSET_BITS 0x00FFFFFF

Definition at line 657 of file sahwreg.h.

◆ HDA_IOP_DONE

#define HDA_IOP_DONE (bit32)(ILAHDAC_IOP_IMG_DONE << 24)

Definition at line 651 of file sahwreg.h.

◆ HDA_ISTR_DONE

#define HDA_ISTR_DONE (bit32)(ILAHDAC_ISTR_IMG_DONE << 24)

Definition at line 649 of file sahwreg.h.

◆ HDA_PAR_LEN_OFFSET

#define HDA_PAR_LEN_OFFSET 0x04

Definition at line 573 of file sahwreg.h.

◆ HDA_RSP_CODE_OFFSET

#define HDA_RSP_CODE_OFFSET 0x1C

Definition at line 575 of file sahwreg.h.

◆ HDA_RSP_OFFSET1MB

#define HDA_RSP_OFFSET1MB 0x0000FEE0

Definition at line 537 of file sahwreg.h.

◆ HDA_RSP_OFFSET256K

#define HDA_RSP_OFFSET256K 0x0003FFE0

Definition at line 525 of file sahwreg.h.

◆ HDA_RSP_OFFSET512K

#define HDA_RSP_OFFSET512K 0x0007FFE0

Definition at line 529 of file sahwreg.h.

◆ HDA_RSP_OFFSET768K

#define HDA_RSP_OFFSET768K 0x000BFFE0

Definition at line 533 of file sahwreg.h.

◆ HDA_SEQ_ID_BITS

#define HDA_SEQ_ID_BITS 0x00ff0000

Definition at line 656 of file sahwreg.h.

◆ HDA_SEQ_ID_OFFSET

#define HDA_SEQ_ID_OFFSET 0x1E

Definition at line 572 of file sahwreg.h.

◆ HDA_STATUS_BITS

#define HDA_STATUS_BITS 0x0000FFFF

Definition at line 633 of file sahwreg.h.

◆ HDAC_EXEC_CMD

#define HDAC_EXEC_CMD 0x0002

Definition at line 654 of file sahwreg.h.

◆ HDAR_BAD_CMD

#define HDAR_BAD_CMD 0x8004

Definition at line 623 of file sahwreg.h.

◆ HDAR_BAD_IMG

#define HDAR_BAD_IMG 0x8003

Definition at line 622 of file sahwreg.h.

◆ HDAR_EXEC

#define HDAR_EXEC 0x8006

Definition at line 624 of file sahwreg.h.

◆ IBDB_CFG_TABLE_RESET

#define IBDB_CFG_TABLE_RESET 0x02 /* Inbound doorbell bit1 */

Definition at line 232 of file sahwreg.h.

◆ IBDB_CFG_TABLE_UPDATE

#define IBDB_CFG_TABLE_UPDATE 0x01 /* Inbound doorbell bit0 */

Definition at line 233 of file sahwreg.h.

◆ IBDB_IBQ_FREEZE

#define IBDB_IBQ_FREEZE 0x04 /* Inbound doorbell bit2 */

Definition at line 231 of file sahwreg.h.

◆ IBDB_IBQ_UNFREEZE

#define IBDB_IBQ_UNFREEZE 0x08 /* Inbound doorbell bit3 */

Definition at line 230 of file sahwreg.h.

◆ IBDB_MPICT

#define IBDB_MPICT 0x02 /* Inbound doorbell bit1 - Termination */

Definition at line 237 of file sahwreg.h.

◆ IBDB_MPIIF

#define IBDB_MPIIF 0x04 /* Inbound doorbell bit2 - Freeze */

Definition at line 236 of file sahwreg.h.

◆ IBDB_MPIINI

#define IBDB_MPIINI 0x01 /* Inbound doorbell bit0 - Initialization */

Definition at line 238 of file sahwreg.h.

◆ IBDB_MPIIU

#define IBDB_MPIIU 0x08 /* Inbound doorbell bit3 - Unfreeze */

Definition at line 235 of file sahwreg.h.

◆ ILA_ISTR_ADDROFFSETHDA

#define ILA_ISTR_ADDROFFSETHDA 0x0007E000

Definition at line 632 of file sahwreg.h.

◆ ILAHDA_AAP1_IMG_GET

#define ILAHDA_AAP1_IMG_GET 0x11

Definition at line 638 of file sahwreg.h.

◆ ILAHDA_AAP2_IMG_GET

#define ILAHDA_AAP2_IMG_GET 0x12

Definition at line 639 of file sahwreg.h.

◆ ILAHDA_EXITGOOD

#define ILAHDA_EXITGOOD 0x1F

Definition at line 640 of file sahwreg.h.

◆ ILAHDA_IOP_IMG_GET [1/2]

#define ILAHDA_IOP_IMG_GET 0x10

Definition at line 637 of file sahwreg.h.

◆ ILAHDA_IOP_IMG_GET [2/2]

#define ILAHDA_IOP_IMG_GET 0x10

Definition at line 637 of file sahwreg.h.

◆ ILAHDA_RAAE_IMG_GET

#define ILAHDA_RAAE_IMG_GET 0x11

Definition at line 602 of file sahwreg.h.

◆ ILAHDAC_AAP1_IMG_DONE

#define ILAHDAC_AAP1_IMG_DONE 0x00000081

Definition at line 644 of file sahwreg.h.

◆ ILAHDAC_AAP2_IMG_DONE

#define ILAHDAC_AAP2_IMG_DONE 0x00000082

Definition at line 645 of file sahwreg.h.

◆ ILAHDAC_GOTOHDA

#define ILAHDAC_GOTOHDA 0x000000ff

Definition at line 647 of file sahwreg.h.

◆ ILAHDAC_IOP_IMG_DONE

#define ILAHDAC_IOP_IMG_DONE 0x00000080

Definition at line 643 of file sahwreg.h.

◆ ILAHDAC_ISTR_IMG_DONE

#define ILAHDAC_ISTR_IMG_DONE 0x00000083

Definition at line 646 of file sahwreg.h.

◆ ILAHDAC_RAAE_IMG_DONE

#define ILAHDAC_RAAE_IMG_DONE 0x81

Definition at line 605 of file sahwreg.h.

◆ L0_LCLK

#define L0_LCLK 0x1

Definition at line 494 of file sahwreg.h.

◆ L0_LCLK_CLEAR

#define L0_LCLK_CLEAR 0x2

Definition at line 493 of file sahwreg.h.

◆ LCLK

#define LCLK 0x1

Definition at line 491 of file sahwreg.h.

◆ LCLK_CLEAR

#define LCLK_CLEAR 0x2

Definition at line 490 of file sahwreg.h.

◆ MBIC_AAP1_ADDR_BASE

#define MBIC_AAP1_ADDR_BASE 0x060000

Definition at line 658 of file sahwreg.h.

◆ MBIC_GSM_SM_BASE

#define MBIC_GSM_SM_BASE 0x04F0000

Definition at line 659 of file sahwreg.h.

◆ MBIC_IOP_ADDR_BASE

#define MBIC_IOP_ADDR_BASE 0x070000

Definition at line 660 of file sahwreg.h.

◆ MBIC_NMI_ENABLE_VPE0_AAP1

#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418

Definition at line 440 of file sahwreg.h.

◆ MBIC_NMI_ENABLE_VPE0_IOP

#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418

Definition at line 439 of file sahwreg.h.

◆ MSGU_HOST_INT_MASK

#define MSGU_HOST_INT_MASK 0x0C

Definition at line 56 of file sahwreg.h.

◆ MSGU_HOST_INT_STATUS

#define MSGU_HOST_INT_STATUS 0x08

Definition at line 55 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_0

#define MSGU_HOST_SCRATCH_PAD_0 0x54

Definition at line 67 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_1

#define MSGU_HOST_SCRATCH_PAD_1 0x58

Definition at line 68 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_2

#define MSGU_HOST_SCRATCH_PAD_2 0x5C

Definition at line 69 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_3

#define MSGU_HOST_SCRATCH_PAD_3 0x60

Definition at line 70 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_4

#define MSGU_HOST_SCRATCH_PAD_4 0x64

Definition at line 71 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_5

#define MSGU_HOST_SCRATCH_PAD_5 0x68

Definition at line 72 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_6

#define MSGU_HOST_SCRATCH_PAD_6 0x6C

Definition at line 73 of file sahwreg.h.

◆ MSGU_HOST_SCRATCH_PAD_7

#define MSGU_HOST_SCRATCH_PAD_7 0x70

Definition at line 74 of file sahwreg.h.

◆ MSGU_IBDB_CLEAR

#define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */

Definition at line 59 of file sahwreg.h.

◆ MSGU_IBDB_SET

#define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */

Definition at line 54 of file sahwreg.h.

◆ MSGU_IOPIB_INT_MASK

#define MSGU_IOPIB_INT_MASK 0x1C

Definition at line 58 of file sahwreg.h.

◆ MSGU_IOPIB_INT_STATUS

#define MSGU_IOPIB_INT_STATUS 0x18

Definition at line 57 of file sahwreg.h.

◆ MSGU_MSGU_CONTROL

#define MSGU_MSGU_CONTROL 0x24

Definition at line 60 of file sahwreg.h.

◆ MSGU_MU_IO_WIR

#define MSGU_MU_IO_WIR 0x8 /* Window 0 */

Definition at line 619 of file sahwreg.h.

◆ MSGU_ODCR

#define MSGU_ODCR 0x40 /* RevB */

Definition at line 62 of file sahwreg.h.

◆ MSGU_ODMR

#define MSGU_ODMR 0x74 /* RevB */

Definition at line 75 of file sahwreg.h.

◆ MSGU_ODR

#define MSGU_ODR 0x3C /* RevB */

Definition at line 61 of file sahwreg.h.

◆ MSGU_READ_IDR

#define MSGU_READ_IDR siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET)

Definition at line 217 of file sahwreg.h.

◆ MSGU_READ_ODCR

#define MSGU_READ_ODCR siHalRegReadExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR)

Definition at line 220 of file sahwreg.h.

◆ MSGU_READ_ODMR

#define MSGU_READ_ODMR siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR)

Definition at line 218 of file sahwreg.h.

◆ MSGU_READ_ODR

#define MSGU_READ_ODR siHalRegReadExt(agRoot, GEN_MSGU_ODR, MSGU_ODR)

Definition at line 219 of file sahwreg.h.

◆ MSGU_SCRATCH_PAD_0

#define MSGU_SCRATCH_PAD_0 0x44

Definition at line 63 of file sahwreg.h.

◆ MSGU_SCRATCH_PAD_1

#define MSGU_SCRATCH_PAD_1 0x48

Definition at line 64 of file sahwreg.h.

◆ MSGU_SCRATCH_PAD_2

#define MSGU_SCRATCH_PAD_2 0x4C

Definition at line 65 of file sahwreg.h.

◆ MSGU_SCRATCH_PAD_3

#define MSGU_SCRATCH_PAD_3 0x50

Definition at line 66 of file sahwreg.h.

◆ MSGU_XCBI_IBDB_REG

#define MSGU_XCBI_IBDB_REG 0x003034 /* PCIE - Message Unit Inbound Doorbell register */

Definition at line 201 of file sahwreg.h.

◆ MSGU_XCBI_OBDB_CLEAR

#define MSGU_XCBI_OBDB_CLEAR 0x00303C /* PCIE - Message Unit Outbound Doorbell Interrupt Clear Register */

Definition at line 204 of file sahwreg.h.

◆ MSGU_XCBI_OBDB_MASK

#define MSGU_XCBI_OBDB_MASK 0x003358 /* PCIE - Message Unit Outbound Doorbell Interrupt Mask Register */

Definition at line 203 of file sahwreg.h.

◆ MSGU_XCBI_OBDB_REG

#define MSGU_XCBI_OBDB_REG 0x003354 /* PCIE - Message Unit Outbound Doorbell Interrupt Register */

Definition at line 202 of file sahwreg.h.

◆ MU_MEM_OFFSET

#define MU_MEM_OFFSET 0x0

Definition at line 618 of file sahwreg.h.

◆ ODCR_CLEAR_ALL

#define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all interrupt vector */

Definition at line 227 of file sahwreg.h.

◆ ODMR_CLEAR_ALL

#define ODMR_CLEAR_ALL 0 /* clear all interrupt vector */

Definition at line 225 of file sahwreg.h.

◆ ODMR_MASK_ALL

#define ODMR_MASK_ALL 0xFFFFFFFF /* mask all interrupt vector */

Definition at line 224 of file sahwreg.h.

◆ OFFSET_MASK

#define OFFSET_MASK 0x0000FFFF

Definition at line 630 of file sahwreg.h.

◆ PCI_TRIGGER_COAL_INVALID

#define PCI_TRIGGER_COAL_INVALID 8 /* Setting adjustable paramater PciTrigger to match this value */

Definition at line 679 of file sahwreg.h.

◆ PCI_TRIGGER_COAL_IOMB_ERROR

#define PCI_TRIGGER_COAL_IOMB_ERROR 4 /* Setting adjustable paramater PciTrigger to match this value */

Definition at line 678 of file sahwreg.h.

◆ PCI_TRIGGER_INIT_TEST

#define PCI_TRIGGER_INIT_TEST 1 /* Setting adjustable paramater PciTrigger to match this value */

Definition at line 676 of file sahwreg.h.

◆ PCI_TRIGGER_OFFSET_MISMATCH

#define PCI_TRIGGER_OFFSET_MISMATCH 2 /* Setting adjustable paramater PciTrigger to match this value */

Definition at line 677 of file sahwreg.h.

◆ PCIE_ERROR_INTERRUPT

#define PCIE_ERROR_INTERRUPT 0x00304C

Definition at line 446 of file sahwreg.h.

◆ PCIE_ERROR_INTERRUPT_ENABLE

#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048

Definition at line 445 of file sahwreg.h.

◆ PCIE_EVENT_INTERRUPT

#define PCIE_EVENT_INTERRUPT 0x003044

Definition at line 444 of file sahwreg.h.

◆ PCIE_EVENT_INTERRUPT_ENABLE

#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040

Definition at line 443 of file sahwreg.h.

◆ PCIE_TRIGGER_ON_REGISTER_READ

#define PCIE_TRIGGER_ON_REGISTER_READ V_Host_Scratchpad_2_Register /* PCI trigger on this offset */

Definition at line 674 of file sahwreg.h.

◆ PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE

#define PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE 0x00000001

Definition at line 612 of file sahwreg.h.

◆ PMIC_MU_CFG_1_BITMSK_MU_IO_WIR

#define PMIC_MU_CFG_1_BITMSK_MU_IO_WIR 0x0000000C

Definition at line 613 of file sahwreg.h.

◆ PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE [1/2]

#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010

Definition at line 614 of file sahwreg.h.

◆ PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE [2/2]

#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010

Definition at line 614 of file sahwreg.h.

◆ PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET

#define PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET 0xFFFFFC00

Definition at line 615 of file sahwreg.h.

◆ RAM_ECC_DB_ERR

#define RAM_ECC_DB_ERR 0x00000018

Definition at line 415 of file sahwreg.h.

◆ RB6_ACCESS_REG

#define RB6_ACCESS_REG 0x6A0000

Definition at line 653 of file sahwreg.h.

◆ RB6_MAGIC_NUMBER_RST

#define RB6_MAGIC_NUMBER_RST 0x1234 /* Magic number of soft reset for RB6 */

Definition at line 209 of file sahwreg.h.

◆ SA_FATAL_ERROR_FATAL_ERROR

#define SA_FATAL_ERROR_FATAL_ERROR 0x2

Definition at line 671 of file sahwreg.h.

◆ SA_FATAL_ERROR_SP1_AAP1_ERR_MASK

#define SA_FATAL_ERROR_SP1_AAP1_ERR_MASK 0x3

Definition at line 669 of file sahwreg.h.

◆ SA_FATAL_ERROR_SP2_IOP_ERR_MASK

#define SA_FATAL_ERROR_SP2_IOP_ERR_MASK 0x3

Definition at line 670 of file sahwreg.h.

◆ SCRATCH_PAD0_AAPERR_MASK

#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF /* if AAP error state */

Definition at line 243 of file sahwreg.h.

◆ SCRATCH_PAD0_BAR_MASK

#define SCRATCH_PAD0_BAR_MASK 0xFC000000 /* bit31-26 - mask bar */

Definition at line 241 of file sahwreg.h.

◆ SCRATCH_PAD0_OFFSET_MASK

#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF /* bit25-0 - offset mask */

Definition at line 242 of file sahwreg.h.

◆ SCRATCH_PAD1_AAP1RDY_RST

#define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */

Definition at line 251 of file sahwreg.h.

◆ SCRATCH_PAD1_AAP_ERROR_STATE

#define SCRATCH_PAD1_AAP_ERROR_STATE 0x00000002 /* bit1 */

Definition at line 321 of file sahwreg.h.

◆ SCRATCH_PAD1_AAP_READY

#define SCRATCH_PAD1_AAP_READY 0x00000003 /* bit1 & bit0 */

Definition at line 322 of file sahwreg.h.

◆ SCRATCH_PAD1_BDMA_ERR

#define SCRATCH_PAD1_BDMA_ERR 0x80000000 /* bit31 */

Definition at line 305 of file sahwreg.h.

◆ SCRATCH_PAD1_ERR

#define SCRATCH_PAD1_ERR 0x02 /* error state */

Definition at line 248 of file sahwreg.h.

◆ SCRATCH_PAD1_FW_ASRT_ERR

#define SCRATCH_PAD1_FW_ASRT_ERR 0x00004000 /* bit14 */

Definition at line 319 of file sahwreg.h.

◆ SCRATCH_PAD1_FW_INIT_ERR

#define SCRATCH_PAD1_FW_INIT_ERR 0x00008000 /* bit15 */

Definition at line 318 of file sahwreg.h.

◆ SCRATCH_PAD1_FW_WDG_ERR

#define SCRATCH_PAD1_FW_WDG_ERR 0x00002000 /* bit13 */

Definition at line 320 of file sahwreg.h.

◆ SCRATCH_PAD1_GSM_ERR

#define SCRATCH_PAD1_GSM_ERR 0x40000000 /* bit30 */

Definition at line 306 of file sahwreg.h.

◆ SCRATCH_PAD1_HSST_ERR

#define SCRATCH_PAD1_HSST_ERR 0x00100000 /* bit20 */

Definition at line 316 of file sahwreg.h.

◆ SCRATCH_PAD1_MBIC1_ERR

#define SCRATCH_PAD1_MBIC1_ERR 0x20000000 /* bit29 */

Definition at line 307 of file sahwreg.h.

◆ SCRATCH_PAD1_MBIC1_SET0_ERR

#define SCRATCH_PAD1_MBIC1_SET0_ERR 0x10000000 /* bit28 */

Definition at line 308 of file sahwreg.h.

◆ SCRATCH_PAD1_MBIC1_SET1_ERR

#define SCRATCH_PAD1_MBIC1_SET1_ERR 0x08000000 /* bit27 */

Definition at line 309 of file sahwreg.h.

◆ SCRATCH_PAD1_OSSP_ERR

#define SCRATCH_PAD1_OSSP_ERR 0x00800000 /* bit23 */

Definition at line 313 of file sahwreg.h.

◆ SCRATCH_PAD1_PCS_ERR

#define SCRATCH_PAD1_PCS_ERR 0x00080000 /* bit19 */

Definition at line 317 of file sahwreg.h.

◆ SCRATCH_PAD1_PMIC1_ERR

#define SCRATCH_PAD1_PMIC1_ERR 0x04000000 /* bit26 */

Definition at line 310 of file sahwreg.h.

◆ SCRATCH_PAD1_PMIC2_ERR

#define SCRATCH_PAD1_PMIC2_ERR 0x02000000 /* bit25 */

Definition at line 311 of file sahwreg.h.

◆ SCRATCH_PAD1_PMIC_EVENT_ERR

#define SCRATCH_PAD1_PMIC_EVENT_ERR 0x01000000 /* bit24 */

Definition at line 312 of file sahwreg.h.

◆ SCRATCH_PAD1_POR

#define SCRATCH_PAD1_POR 0x00 /* power on reset state */

Definition at line 246 of file sahwreg.h.

◆ SCRATCH_PAD1_RDY

#define SCRATCH_PAD1_RDY 0x03 /* ready state */

Definition at line 249 of file sahwreg.h.

◆ SCRATCH_PAD1_RESERVED

#define SCRATCH_PAD1_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */

Definition at line 253 of file sahwreg.h.

◆ SCRATCH_PAD1_RST

#define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */

Definition at line 250 of file sahwreg.h.

◆ SCRATCH_PAD1_SFR

#define SCRATCH_PAD1_SFR 0x01 /* soft reset state */

Definition at line 247 of file sahwreg.h.

◆ SCRATCH_PAD1_SSPA_ERR

#define SCRATCH_PAD1_SSPA_ERR 0x00400000 /* bit22 */

Definition at line 314 of file sahwreg.h.

◆ SCRATCH_PAD1_SSPL_ERR

#define SCRATCH_PAD1_SSPL_ERR 0x00200000 /* bit21 */

Definition at line 315 of file sahwreg.h.

◆ SCRATCH_PAD1_STATE_MASK

#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 Mask other bits 31:4, bit1-0 State */

Definition at line 252 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BIT9_RESERVED

#define SCRATCH_PAD1_V_BIT9_RESERVED 0x00000200 /* 9 */

Definition at line 274 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTLDR_ERROR

#define SCRATCH_PAD1_V_BOOTLDR_ERROR 0x00000070 /* Scratch Pad1 (6 5 4) */

Definition at line 301 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR

#define SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR 0x00000040 /* HDA Mode due to critical error */

Definition at line 266 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_FATAL

#define SCRATCH_PAD1_V_BOOTSTATE_FATAL 0x00000070 /* Fatal Error Boot process halted */

Definition at line 269 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP

#define SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP 0x00000020 /* HDA Mode BootStrap Setting */

Definition at line 264 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM

#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM 0x00000010 /* HDA Mode SEEPROM Setting */

Definition at line 263 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET

#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030 /* HDA Mode Soft Reset */

Definition at line 265 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_MASK

#define SCRATCH_PAD1_V_BOOTSTATE_MASK 0x00000070 /* 456 */

Definition at line 261 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_R1

#define SCRATCH_PAD1_V_BOOTSTATE_R1 0x00000050 /* Reserved */

Definition at line 267 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_R2

#define SCRATCH_PAD1_V_BOOTSTATE_R2 0x00000060 /* Reserved */

Definition at line 268 of file sahwreg.h.

◆ SCRATCH_PAD1_V_BOOTSTATE_SUCESS

#define SCRATCH_PAD1_V_BOOTSTATE_SUCESS 0x00000000 /* Load successful */

Definition at line 262 of file sahwreg.h.

◆ SCRATCH_PAD1_V_ERROR

#define SCRATCH_PAD1_V_ERROR ( SCRATCH_PAD1_V_RAAE_ERR | SCRATCH_PAD1_V_ILA_ERR | SCRATCH_PAD1_V_IOP0_ERR | SCRATCH_PAD1_V_IOP1_ERR ) /* Scratch Pad1 13 11 3 1 */

Definition at line 282 of file sahwreg.h.

◆ SCRATCH_PAD1_V_ERROR_STATE

#define SCRATCH_PAD1_V_ERROR_STATE ( ScratchPad1 )

Value:

                                                  ( SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1)  | \
                                                  SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) | \
                                                  SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) | \
                                                  SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) )

Definition at line 296 of file sahwreg.h.

◆ SCRATCH_PAD1_V_FW_IMAGE

#define SCRATCH_PAD1_V_FW_IMAGE 0x00000100 /* 8 */

Definition at line 273 of file sahwreg.h.

◆ SCRATCH_PAD1_V_ILA_ERR

#define SCRATCH_PAD1_V_ILA_ERR 0x00000008 /* 3 */

Definition at line 260 of file sahwreg.h.

◆ SCRATCH_PAD1_V_ILA_ERROR_STATE

#define SCRATCH_PAD1_V_ILA_ERROR_STATE ( ScratchPad1 )

Value:

((((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_MASK) ? 0: \

(((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_ERR ) ? SCRATCH_PAD1_V_ILA_ERR : 0 )

SCRATCH_PAD1_V_ILA_ERR

#define SCRATCH_PAD1_V_ILA_ERR

Definition: sahwreg.h:260

SCRATCH_PAD1_V_ILA_MASK

#define SCRATCH_PAD1_V_ILA_MASK

Definition: sahwreg.h:259

Definition at line 284 of file sahwreg.h.

◆ SCRATCH_PAD1_V_ILA_IMAGE

#define SCRATCH_PAD1_V_ILA_IMAGE 0x00000080 /* 7 */

Definition at line 272 of file sahwreg.h.

◆ SCRATCH_PAD1_V_ILA_MASK

#define SCRATCH_PAD1_V_ILA_MASK 0x0000000C /* 2 3 also ready */

Definition at line 259 of file sahwreg.h.

◆ SCRATCH_PAD1_V_IOP0_ERR

#define SCRATCH_PAD1_V_IOP0_ERR 0x00000800 /* 11 */

Definition at line 276 of file sahwreg.h.

◆ SCRATCH_PAD1_V_IOP0_ERROR_STATE

#define SCRATCH_PAD1_V_IOP0_ERROR_STATE ( ScratchPad1 )

Value:

((((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_MASK) ? 0: \

(((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_ERR) ? SCRATCH_PAD1_V_IOP0_ERR : 0 )

SCRATCH_PAD1_V_IOP0_MASK

#define SCRATCH_PAD1_V_IOP0_MASK

Definition: sahwreg.h:275

SCRATCH_PAD1_V_IOP0_ERR

#define SCRATCH_PAD1_V_IOP0_ERR

Definition: sahwreg.h:276

Definition at line 290 of file sahwreg.h.

◆ SCRATCH_PAD1_V_IOP0_MASK

#define SCRATCH_PAD1_V_IOP0_MASK 0x00000C00 /* 10 11 also ready */

Definition at line 275 of file sahwreg.h.

◆ SCRATCH_PAD1_V_IOP1_ERR

#define SCRATCH_PAD1_V_IOP1_ERR 0x00002000 /* 13 */

Definition at line 278 of file sahwreg.h.

◆ SCRATCH_PAD1_V_IOP1_ERROR_STATE

#define SCRATCH_PAD1_V_IOP1_ERROR_STATE ( ScratchPad1 )

Value:

((((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_MASK) ? 0: \

(((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_ERR) ? SCRATCH_PAD1_V_IOP1_ERR : 0 )

SCRATCH_PAD1_V_IOP1_ERR

#define SCRATCH_PAD1_V_IOP1_ERR

Definition: sahwreg.h:278

SCRATCH_PAD1_V_IOP1_MASK

#define SCRATCH_PAD1_V_IOP1_MASK

Definition: sahwreg.h:277

Definition at line 293 of file sahwreg.h.

◆ SCRATCH_PAD1_V_IOP1_MASK

#define SCRATCH_PAD1_V_IOP1_MASK 0x00003000 /* 12 13 also ready */

Definition at line 277 of file sahwreg.h.

◆ SCRATCH_PAD1_V_RAAE_ERR

#define SCRATCH_PAD1_V_RAAE_ERR 0x00000002 /* 1 */

Definition at line 258 of file sahwreg.h.

◆ SCRATCH_PAD1_V_RAAE_ERROR_STATE

#define SCRATCH_PAD1_V_RAAE_ERROR_STATE ( ScratchPad1 )

Value:

((((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_MASK) ? 0: \

(((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_ERR) ? SCRATCH_PAD1_V_RAAE_ERR : 0 )

SCRATCH_PAD1_V_RAAE_ERR

#define SCRATCH_PAD1_V_RAAE_ERR

Definition: sahwreg.h:258

SCRATCH_PAD1_V_RAAE_MASK

#define SCRATCH_PAD1_V_RAAE_MASK

Definition: sahwreg.h:257

Definition at line 287 of file sahwreg.h.

◆ SCRATCH_PAD1_V_RAAE_MASK

#define SCRATCH_PAD1_V_RAAE_MASK 0x00000003 /* 0 1 also ready */

Definition at line 257 of file sahwreg.h.

◆ SCRATCH_PAD1_V_READY

#define SCRATCH_PAD1_V_READY ( SCRATCH_PAD1_V_RAAE_MASK | SCRATCH_PAD1_V_ILA_MASK | SCRATCH_PAD1_V_IOP0_MASK ) /* */

Definition at line 281 of file sahwreg.h.

◆ SCRATCH_PAD1_V_RESERVED

#define SCRATCH_PAD1_V_RESERVED 0xFFFFC000 /* 14-31 */

Definition at line 279 of file sahwreg.h.

◆ SCRATCH_PAD2_BDMA_ERR

#define SCRATCH_PAD2_BDMA_ERR 0x80000000 /* bit31 */

Definition at line 336 of file sahwreg.h.

◆ SCRATCH_PAD2_ERR

#define SCRATCH_PAD2_ERR 0x02 /* error state */

Definition at line 328 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_BOOT_ROM_ERROR

#define SCRATCH_PAD2_FW_BOOT_ROM_ERROR 0x00010000 /* bit16 */

Definition at line 350 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_FLM_ERR

#define SCRATCH_PAD2_FW_FLM_ERR 0x00004000 /* bit14 */

Definition at line 352 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_FW_ASRT_ERR

#define SCRATCH_PAD2_FW_FW_ASRT_ERR 0x00002000 /* bit13 */

Definition at line 353 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR

#define SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x00000800 /* bit11 */

Definition at line 355 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_HW_FATAL_ERR

#define SCRATCH_PAD2_FW_HW_FATAL_ERR 0x00000200 /* bit9 */

Definition at line 357 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_HW_MASK

#define SCRATCH_PAD2_FW_HW_MASK 0x000000FF

Definition at line 359 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_HW_NON_FATAL_ERR

#define SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x00000100 /* bit8 */

Definition at line 358 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_HW_WDG_ERR

#define SCRATCH_PAD2_FW_HW_WDG_ERR 0x00001000 /* bit12 */

Definition at line 354 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_ILA_ERR

#define SCRATCH_PAD2_FW_ILA_ERR 0x00008000 /* bit15 */

Definition at line 351 of file sahwreg.h.

◆ SCRATCH_PAD2_FW_UNDTMN_ERR

#define SCRATCH_PAD2_FW_UNDTMN_ERR 0x00000400 /* bit10 */

Definition at line 356 of file sahwreg.h.

◆ SCRATCH_PAD2_FWRDY_RST

#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset rdy flag */

Definition at line 330 of file sahwreg.h.

◆ SCRATCH_PAD2_GSM_ERR

#define SCRATCH_PAD2_GSM_ERR 0x40000000 /* bit30 */

Definition at line 337 of file sahwreg.h.

◆ SCRATCH_PAD2_HSST_ERR

#define SCRATCH_PAD2_HSST_ERR 0x00100000 /* bit20 */

Definition at line 347 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x10

Definition at line 371 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x05

Definition at line 365 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x01

Definition at line 361 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x14

Definition at line 373 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x13

Definition at line 372 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x0E

Definition at line 369 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x02

Definition at line 362 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x03

Definition at line 363 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x04

Definition at line 364 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x0C

Definition at line 368 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x08

Definition at line 367 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x00

Definition at line 360 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x06

Definition at line 366 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x0F

Definition at line 370 of file sahwreg.h.

◆ SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED

#define SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF

Definition at line 374 of file sahwreg.h.

◆ SCRATCH_PAD2_IOPRDY_RST

#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */

Definition at line 331 of file sahwreg.h.

◆ SCRATCH_PAD2_MBIC3_ERR

#define SCRATCH_PAD2_MBIC3_ERR 0x20000000 /* bit29 */

Definition at line 338 of file sahwreg.h.

◆ SCRATCH_PAD2_MBIC3_SET0_ERR

#define SCRATCH_PAD2_MBIC3_SET0_ERR 0x10000000 /* bit28 */

Definition at line 339 of file sahwreg.h.

◆ SCRATCH_PAD2_MBIC3_SET1_ERR

#define SCRATCH_PAD2_MBIC3_SET1_ERR 0x08000000 /* bit27 */

Definition at line 340 of file sahwreg.h.

◆ SCRATCH_PAD2_OSSP_ERR

#define SCRATCH_PAD2_OSSP_ERR 0x00800000 /* bit23 */

Definition at line 344 of file sahwreg.h.

◆ SCRATCH_PAD2_PCS_ERR

#define SCRATCH_PAD2_PCS_ERR 0x00080000 /* bit19 */

Definition at line 348 of file sahwreg.h.

◆ SCRATCH_PAD2_PMIC1_ERR

#define SCRATCH_PAD2_PMIC1_ERR 0x04000000 /* bit26 */

Definition at line 341 of file sahwreg.h.

◆ SCRATCH_PAD2_PMIC2_ERR

#define SCRATCH_PAD2_PMIC2_ERR 0x02000000 /* bit25 */

Definition at line 342 of file sahwreg.h.

◆ SCRATCH_PAD2_PMIC_EVENT_ERR

#define SCRATCH_PAD2_PMIC_EVENT_ERR 0x01000000 /* bit24 */

Definition at line 343 of file sahwreg.h.

◆ SCRATCH_PAD2_POR

#define SCRATCH_PAD2_POR 0x00 /* power on state */

Definition at line 326 of file sahwreg.h.

◆ SCRATCH_PAD2_RDY

#define SCRATCH_PAD2_RDY 0x03 /* ready state */

Definition at line 329 of file sahwreg.h.

◆ SCRATCH_PAD2_RESERVED

#define SCRATCH_PAD2_RESERVED 0x000000F0 /* Scratch Pad1 Reserved bit 4 to 7 */

Definition at line 333 of file sahwreg.h.

◆ SCRATCH_PAD2_SFR

#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */

Definition at line 327 of file sahwreg.h.

◆ SCRATCH_PAD2_SSPA_ERR

#define SCRATCH_PAD2_SSPA_ERR 0x00400000 /* bit22 */

Definition at line 345 of file sahwreg.h.

◆ SCRATCH_PAD2_SSPL_ERR

#define SCRATCH_PAD2_SSPL_ERR 0x00200000 /* bit21 */

Definition at line 346 of file sahwreg.h.

◆ SCRATCH_PAD2_STATE_MASK

#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF0 /* ScratchPad 2 Mask for other bits 31:4, bit1-0 State*/

Definition at line 332 of file sahwreg.h.

◆ SCRATCH_PAD3_FW_IMAGE_A_VALID

#define SCRATCH_PAD3_FW_IMAGE_A_VALID 0x00000002 /* Image A is valid */

Definition at line 390 of file sahwreg.h.

◆ SCRATCH_PAD3_FW_IMAGE_B_ACTIVE

#define SCRATCH_PAD3_FW_IMAGE_B_ACTIVE 0x00000001 /* Image B is active */

Definition at line 391 of file sahwreg.h.

◆ SCRATCH_PAD3_FW_IMAGE_B_VALID

#define SCRATCH_PAD3_FW_IMAGE_B_VALID 0x00000004 /* Image B is valid */

Definition at line 389 of file sahwreg.h.

◆ SCRATCH_PAD3_FW_IMAGE_FLAG_VALID

#define SCRATCH_PAD3_FW_IMAGE_FLAG_VALID 0x00000008 /* Image flag is valid */

Definition at line 388 of file sahwreg.h.

◆ SCRATCH_PAD3_FW_IMAGE_MASK

#define SCRATCH_PAD3_FW_IMAGE_MASK 0x0000000F /* SPC 8x6G boots from Image */

Definition at line 387 of file sahwreg.h.

◆ SCRATCH_PAD3_V_

#define SCRATCH_PAD3_V_ 0x00000001 /* Image B is valid */

Definition at line 394 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ARF

#define SCRATCH_PAD3_V_ARF 0x00000004 /* ARF factory mode. */

Definition at line 403 of file sahwreg.h.

◆ SCRATCH_PAD3_V_AUT

#define SCRATCH_PAD3_V_AUT 0x00000008 /* AUT Operator authentication*/

Definition at line 402 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ENC_DIS_ERR

#define SCRATCH_PAD3_V_ENC_DIS_ERR 0x00000001 /* */

Definition at line 397 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ENC_DISABLED

#define SCRATCH_PAD3_V_ENC_DISABLED 0x00000000 /* */

Definition at line 396 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ENC_ENA_ERR

#define SCRATCH_PAD3_V_ENC_ENA_ERR 0x00000002 /* */

Definition at line 398 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ENC_MASK

#define SCRATCH_PAD3_V_ENC_MASK SCRATCH_PAD3_V_ENC_READY /* */

Definition at line 400 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ENC_READY

#define SCRATCH_PAD3_V_ENC_READY 0x00000003 /* */

Definition at line 399 of file sahwreg.h.

◆ SCRATCH_PAD3_V_ERR_CODE

#define SCRATCH_PAD3_V_ERR_CODE 0x00FF0000 /* */

Definition at line 410 of file sahwreg.h.

◆ SCRATCH_PAD3_V_SM_MASK

#define SCRATCH_PAD3_V_SM_MASK 0x000000F0 /* */

Definition at line 409 of file sahwreg.h.

◆ SCRATCH_PAD3_V_SMA_ENABLED

#define SCRATCH_PAD3_V_SMA_ENABLED (1 << SHIFT4 ) /* */

Definition at line 406 of file sahwreg.h.

◆ SCRATCH_PAD3_V_SMB_ENABLED

#define SCRATCH_PAD3_V_SMB_ENABLED (1 << SHIFT5 ) /* */

Definition at line 407 of file sahwreg.h.

◆ SCRATCH_PAD3_V_SMF_ENABLED

#define SCRATCH_PAD3_V_SMF_ENABLED 0 /* */

Definition at line 408 of file sahwreg.h.

◆ SCRATCH_PAD3_V_XTS_ENABLED

#define SCRATCH_PAD3_V_XTS_ENABLED (1 << SHIFT14) /* */

Definition at line 405 of file sahwreg.h.

◆ SCRATCH_PAD_ERROR_MASK

#define SCRATCH_PAD_ERROR_MASK 0xFFFFFF00 /* Error mask bits 31:8 */

Definition at line 378 of file sahwreg.h.

◆ SCRATCH_PAD_STATE_MASK

#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits 1:0 */

Definition at line 379 of file sahwreg.h.

◆ SHIFT_MASK

#define SHIFT_MASK 0xFFFF0000

Definition at line 629 of file sahwreg.h.

◆ SIZE_64KB

#define SIZE_64KB 0x00010000

Definition at line 631 of file sahwreg.h.

◆ SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET

#define SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET (HDA_RSP_OFFSET1MB + HDA_RSP_CODE_OFFSET)

Definition at line 576 of file sahwreg.h.

◆ SPC_CODE_VIOLATION_COUNT

#define SPC_CODE_VIOLATION_COUNT 0x00103C

Definition at line 502 of file sahwreg.h.

◆ SPC_HDASOFT_RESET_SIGNATURE

#define SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7 /* Signature for HDA Soft Reset without PCIe resetting */

Definition at line 425 of file sahwreg.h.

◆ SPC_IBW_AXI_TRANSLATION_LOW

#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258

Definition at line 520 of file sahwreg.h.

◆ SPC_ICCONTROL

#define SPC_ICCONTROL 0x0033C4

Definition at line 198 of file sahwreg.h.

◆ SPC_ICTIMER

#define SPC_ICTIMER 0x0033C0

Definition at line 197 of file sahwreg.h.

◆ SPC_INVALID_DW_COUNT

#define SPC_INVALID_DW_COUNT 0x001034

Definition at line 500 of file sahwreg.h.

◆ SPC_L0_ERR_CNT_CNTL

#define SPC_L0_ERR_CNT_CNTL 0x0041B0

Definition at line 515 of file sahwreg.h.

◆ SPC_LOSS_DW_SYNC_COUNT

#define SPC_LOSS_DW_SYNC_COUNT 0x001040

Definition at line 503 of file sahwreg.h.

◆ SPC_ODAR

#define SPC_ODAR 0x00335C

Definition at line 196 of file sahwreg.h.

◆ SPC_PHY_RESET_PROBLEM_COUNT

#define SPC_PHY_RESET_PROBLEM_COUNT 0x001044

Definition at line 504 of file sahwreg.h.

◆ SPC_RB6_OFFSET

#define SPC_RB6_OFFSET 0x80C0

Definition at line 207 of file sahwreg.h.

◆ SPC_READ_CODE_VIO_COUNT

#define SPC_READ_CODE_VIO_COUNT ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_CODE_VIOLATION_COUNT + (COUNT_OFFSET * phyId))

Definition at line 511 of file sahwreg.h.

◆ SPC_READ_COUNTER_CNTL

#define SPC_READ_COUNTER_CNTL ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId))

Definition at line 507 of file sahwreg.h.

◆ SPC_READ_DEV_REV

#define SPC_READ_DEV_REV ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_REV);

Definition at line 505 of file sahwreg.h.

◆ SPC_READ_DISP_ERR_COUNT

#define SPC_READ_DISP_ERR_COUNT ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_RUN_DISP_ERROR_COUNT + (COUNT_OFFSET * phyId))

Definition at line 510 of file sahwreg.h.

◆ SPC_READ_INV_DW_COUNT

#define SPC_READ_INV_DW_COUNT ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_INVALID_DW_COUNT + (COUNT_OFFSET * phyId))

Definition at line 509 of file sahwreg.h.

◆ SPC_READ_L0ERR_CNT_CNTL

#define SPC_READ_L0ERR_CNT_CNTL ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId))

Definition at line 516 of file sahwreg.h.

◆ SPC_READ_LOSS_DW_COUNT

#define SPC_READ_LOSS_DW_COUNT ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_LOSS_DW_SYNC_COUNT + (COUNT_OFFSET * phyId))

Definition at line 512 of file sahwreg.h.

◆ SPC_READ_PHY_RESET_COUNT

#define SPC_READ_PHY_RESET_COUNT ( phyId ) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_PHY_RESET_PROBLEM_COUNT + (COUNT_OFFSET * phyId))

Definition at line 513 of file sahwreg.h.

◆ SPC_READ_RESET_REG

#define SPC_READ_RESET_REG siHalRegReadExt(agRoot, GEN_SPC_REG_RESET, SPC_REG_RESET)

Definition at line 433 of file sahwreg.h.

◆ SPC_REG_DEVICE_LCLK

#define SPC_REG_DEVICE_LCLK 0x000058 /* Device LCLK generation register */

Definition at line 431 of file sahwreg.h.

◆ SPC_REG_DEVICE_REV

#define SPC_REG_DEVICE_REV 0x000024

Definition at line 476 of file sahwreg.h.

◆ SPC_REG_DEVICE_REV_MASK

#define SPC_REG_DEVICE_REV_MASK 0x0000000F

Definition at line 477 of file sahwreg.h.

◆ SPC_REG_MSGU_CONFIG

#define SPC_REG_MSGU_CONFIG 0x003018

Definition at line 449 of file sahwreg.h.

◆ SPC_REG_RESET

#define SPC_REG_RESET 0x000000 /* reset register */

Definition at line 430 of file sahwreg.h.

◆ SPC_REG_RESET_BDMA_CORE

#define SPC_REG_RESET_BDMA_CORE 0x00020000

Definition at line 463 of file sahwreg.h.

◆ SPC_REG_RESET_BDMA_SXCBI

#define SPC_REG_RESET_BDMA_SXCBI 0x00040000

Definition at line 464 of file sahwreg.h.

◆ SPC_REG_RESET_DDR2

#define SPC_REG_RESET_DDR2 0x00010000

Definition at line 462 of file sahwreg.h.

◆ SPC_REG_RESET_DEVICE

#define SPC_REG_RESET_DEVICE 0x80000000

Definition at line 473 of file sahwreg.h.

◆ SPC_REG_RESET_GSM

#define SPC_REG_RESET_GSM 0x00000100

Definition at line 461 of file sahwreg.h.

◆ SPC_REG_RESET_LMS_SXCBI

#define SPC_REG_RESET_LMS_SXCBI 0x00800000

Definition at line 469 of file sahwreg.h.

◆ SPC_REG_RESET_OSSP

#define SPC_REG_RESET_OSSP 0x00000001

Definition at line 453 of file sahwreg.h.

◆ SPC_REG_RESET_PCIE_AL_SXCBI

#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000

Definition at line 465 of file sahwreg.h.

◆ SPC_REG_RESET_PCIE_PC_SXCBI

#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000

Definition at line 472 of file sahwreg.h.

◆ SPC_REG_RESET_PCIE_PWR

#define SPC_REG_RESET_PCIE_PWR 0x00100000

Definition at line 466 of file sahwreg.h.

◆ SPC_REG_RESET_PCIE_SFT

#define SPC_REG_RESET_PCIE_SFT 0x00200000

Definition at line 467 of file sahwreg.h.

◆ SPC_REG_RESET_PCS

#define SPC_REG_RESET_PCS 0x00000080

Definition at line 460 of file sahwreg.h.

◆ SPC_REG_RESET_PCS_AAP1_SS

#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010

Definition at line 457 of file sahwreg.h.

◆ SPC_REG_RESET_PCS_AAP2_SS

#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020

Definition at line 458 of file sahwreg.h.

◆ SPC_REG_RESET_PCS_IOP_SS

#define SPC_REG_RESET_PCS_IOP_SS 0x00000008

Definition at line 456 of file sahwreg.h.

◆ SPC_REG_RESET_PCS_LM

#define SPC_REG_RESET_PCS_LM 0x00000040

Definition at line 459 of file sahwreg.h.

◆ SPC_REG_RESET_PCS_SPBC

#define SPC_REG_RESET_PCS_SPBC 0x00000004

Definition at line 455 of file sahwreg.h.

◆ SPC_REG_RESET_PCS_SXCBI

#define SPC_REG_RESET_PCS_SXCBI 0x00400000

Definition at line 468 of file sahwreg.h.

◆ SPC_REG_RESET_PMIC_CORE

#define SPC_REG_RESET_PMIC_CORE 0x02000000

Definition at line 471 of file sahwreg.h.

◆ SPC_REG_RESET_PMIC_SXCBI

#define SPC_REG_RESET_PMIC_SXCBI 0x01000000

Definition at line 470 of file sahwreg.h.

◆ SPC_REG_RESET_RAAE

#define SPC_REG_RESET_RAAE 0x00000002

Definition at line 454 of file sahwreg.h.

◆ SPC_REG_TOP_BOOT_STRAP

#define SPC_REG_TOP_BOOT_STRAP 0x8

Definition at line 484 of file sahwreg.h.

◆ SPC_REG_TOP_DEVICE_ID

#define SPC_REG_TOP_DEVICE_ID 0x20

Definition at line 481 of file sahwreg.h.

◆ SPC_RUN_DISP_ERROR_COUNT

#define SPC_RUN_DISP_ERROR_COUNT 0x001038

Definition at line 501 of file sahwreg.h.

◆ SPC_SOFT_RESET_SIGNATURE

#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd /* Signature for Soft Reset */

Definition at line 424 of file sahwreg.h.

◆ SPC_SSPL_COUNTER_CNTL

#define SPC_SSPL_COUNTER_CNTL 0x001030

Definition at line 499 of file sahwreg.h.

◆ SPC_TOP_BOOT_STRAP

#define SPC_TOP_BOOT_STRAP 0x02C0A682

Definition at line 485 of file sahwreg.h.

◆ SPC_TOP_DEVICE_ID

#define SPC_TOP_DEVICE_ID 0x8001

Definition at line 482 of file sahwreg.h.

◆ SPC_TOP_LEVEL_ADDR_BASE

#define SPC_TOP_LEVEL_ADDR_BASE 0x000000

Definition at line 662 of file sahwreg.h.

◆ SPC_V_HDA_COMMAND_OFFSET

#define SPC_V_HDA_COMMAND_OFFSET 0x000042c0

Definition at line 567 of file sahwreg.h.

◆ SPC_V_HDA_RESPONSE_OFFSET

#define SPC_V_HDA_RESPONSE_OFFSET 0x000042e0

Definition at line 568 of file sahwreg.h.

◆ SPC_V_HDAC_BUF_INFO

#define SPC_V_HDAC_BUF_INFO 0x0001

Definition at line 580 of file sahwreg.h.

◆ SPC_V_HDAC_CMDCODE_MASK

#define SPC_V_HDAC_CMDCODE_MASK 0x0000FFFF

Definition at line 587 of file sahwreg.h.

◆ SPC_V_HDAC_DMA

#define SPC_V_HDAC_DMA 0x0004

Definition at line 583 of file sahwreg.h.

◆ SPC_V_HDAC_EXEC

#define SPC_V_HDAC_EXEC 0x0002

Definition at line 581 of file sahwreg.h.

◆ SPC_V_HDAC_PA

#define SPC_V_HDAC_PA 0xCB

Definition at line 579 of file sahwreg.h.

◆ SPC_V_HDAC_PA_MASK

#define SPC_V_HDAC_PA_MASK 0xFF000000

Definition at line 585 of file sahwreg.h.

◆ SPC_V_HDAC_RESET

#define SPC_V_HDAC_RESET 0x0003

Definition at line 582 of file sahwreg.h.

◆ SPC_V_HDAC_SEQID_MASK

#define SPC_V_HDAC_SEQID_MASK 0x00FF0000

Definition at line 586 of file sahwreg.h.

◆ SPC_V_HDAR_BAD_CMD

#define SPC_V_HDAR_BAD_CMD 0x8004

Definition at line 594 of file sahwreg.h.

◆ SPC_V_HDAR_BAD_IMG

#define SPC_V_HDAR_BAD_IMG 0x8003

Definition at line 593 of file sahwreg.h.

◆ SPC_V_HDAR_BUF_INFO

#define SPC_V_HDAR_BUF_INFO 0x8001

Definition at line 591 of file sahwreg.h.

◆ SPC_V_HDAR_EXEC

#define SPC_V_HDAR_EXEC 0x8006

Definition at line 596 of file sahwreg.h.

◆ SPC_V_HDAR_IDLE

#define SPC_V_HDAR_IDLE 0x8002

Definition at line 592 of file sahwreg.h.

◆ SPC_V_HDAR_INTL_ERR

#define SPC_V_HDAR_INTL_ERR 0x8005

Definition at line 595 of file sahwreg.h.

◆ SPC_V_HDAR_PA

#define SPC_V_HDAR_PA 0xDB

Definition at line 590 of file sahwreg.h.

◆ SPC_V_HDAR_PA_MASK

#define SPC_V_HDAR_PA_MASK 0xFF000000

Definition at line 598 of file sahwreg.h.

◆ SPC_V_HDAR_RSPCODE_MASK

#define SPC_V_HDAR_RSPCODE_MASK 0x0000FFFF

Definition at line 600 of file sahwreg.h.

◆ SPC_V_HDAR_SEQID_MASK

#define SPC_V_HDAR_SEQID_MASK 0x00FF0000

Definition at line 599 of file sahwreg.h.

◆ SPC_WRITE_COUNTER_CNTL

#define SPC_WRITE_COUNTER_CNTL	(	phyId,
		value
	)	ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId), value)

Definition at line 508 of file sahwreg.h.

◆ SPC_WRITE_L0ERR_CNT_CNTL

#define SPC_WRITE_L0ERR_CNT_CNTL	(	phyId,
		value
	)	ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value)

Definition at line 517 of file sahwreg.h.

◆ SPC_WRITE_RESET_REG

#define SPC_WRITE_RESET_REG ( value ) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value);

Definition at line 435 of file sahwreg.h.

◆ SPCV_ERROR_VALUE

#define SPCV_ERROR_VALUE 0x2

Definition at line 384 of file sahwreg.h.

◆ SPCV_IOP0_STATE_MASK

#define SPCV_IOP0_STATE_MASK ((1 << 10) | (1 << 11))

Definition at line 382 of file sahwreg.h.

◆ SPCV_IOP1_STATE_MASK

#define SPCV_IOP1_STATE_MASK ((1 << 12) | (1 << 13))

Definition at line 383 of file sahwreg.h.

◆ SPCV_RAAE_STATE_MASK

#define SPCV_RAAE_STATE_MASK 0x3

Definition at line 381 of file sahwreg.h.

◆ SPCv_Reset_Read_ChipResetOccurred

#define SPCv_Reset_Read_ChipResetOccurred 0xC0

Definition at line 159 of file sahwreg.h.

◆ SPCv_Reset_Read_Mask

#define SPCv_Reset_Read_Mask 0xC0

Definition at line 155 of file sahwreg.h.

◆ SPCv_Reset_Read_NoReset

#define SPCv_Reset_Read_NoReset 0x0

Definition at line 156 of file sahwreg.h.

◆ SPCv_Reset_Read_NormalResetOccurred

#define SPCv_Reset_Read_NormalResetOccurred 0x40

Definition at line 157 of file sahwreg.h.

◆ SPCv_Reset_Read_SoftResetHDAOccurred

#define SPCv_Reset_Read_SoftResetHDAOccurred 0x80

Definition at line 158 of file sahwreg.h.

◆ SPCv_Reset_Reserved

#define SPCv_Reset_Reserved 0xFFFFFF3C

Definition at line 154 of file sahwreg.h.

◆ SPCv_Reset_Write_ChipReset

#define SPCv_Reset_Write_ChipReset 0x3

Definition at line 164 of file sahwreg.h.

◆ SPCv_Reset_Write_NormalReset

#define SPCv_Reset_Write_NormalReset 0x1

Definition at line 162 of file sahwreg.h.

◆ SPCv_Reset_Write_SoftResetHDA

#define SPCv_Reset_Write_SoftResetHDA 0x2

Definition at line 163 of file sahwreg.h.

◆ V_GsmConfigReset

#define V_GsmConfigReset 0

Definition at line 145 of file sahwreg.h.

◆ V_GsmReadAddrParityCheck

#define V_GsmReadAddrParityCheck 0x38

Definition at line 146 of file sahwreg.h.

◆ V_GsmReadAddrParityIndic

#define V_GsmReadAddrParityIndic 0x58

Definition at line 149 of file sahwreg.h.

◆ V_GsmWriteAddrParityCheck

#define V_GsmWriteAddrParityCheck 0x40

Definition at line 147 of file sahwreg.h.

◆ V_GsmWriteAddrParityIndic

#define V_GsmWriteAddrParityIndic 0x60

Definition at line 150 of file sahwreg.h.

◆ V_GsmWriteDataParityCheck

#define V_GsmWriteDataParityCheck 0x48

Definition at line 148 of file sahwreg.h.

◆ V_GsmWriteDataParityIndic

#define V_GsmWriteDataParityIndic 0x68

Definition at line 151 of file sahwreg.h.

◆ V_Host_Scratchpad_0_Register

#define V_Host_Scratchpad_0_Register 0x54 /* Host RW Local RO 0x140 MSGU - Scratchpad 4 */

Definition at line 107 of file sahwreg.h.

◆ V_Host_Scratchpad_1_Register

#define V_Host_Scratchpad_1_Register 0x58 /* Host RW Local RO 0x148 MSGU - Scratchpad 5 */

Definition at line 108 of file sahwreg.h.

◆ V_Host_Scratchpad_2_Register

#define V_Host_Scratchpad_2_Register 0x5C /* Host RW Local RO 0x150 MSGU - Scratchpad 6 */

Definition at line 109 of file sahwreg.h.

◆ V_Host_Scratchpad_3_Register

#define V_Host_Scratchpad_3_Register 0x60 /* Host RW Local RO 0x158 MSGU - Scratchpad 7 */

Definition at line 110 of file sahwreg.h.

◆ V_Host_Scratchpad_4_Register

#define V_Host_Scratchpad_4_Register 0x64 /* Host RW Local R/W 0x160 MSGU - Scratchpad 8 */

Definition at line 111 of file sahwreg.h.

◆ V_Host_Scratchpad_5_Register

#define V_Host_Scratchpad_5_Register 0x68 /* Host RW Local R/W 0x168 MSGU - Scratchpad 9 */

Definition at line 112 of file sahwreg.h.

◆ V_Inbound_Doorbell_Clear_Register

#define V_Inbound_Doorbell_Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Clear */

Definition at line 88 of file sahwreg.h.

◆ V_Inbound_Doorbell_Clear_RegisterU

#define V_Inbound_Doorbell_Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Clear */

Definition at line 89 of file sahwreg.h.

◆ V_Inbound_Doorbell_Mask_Clear_Register

#define V_Inbound_Doorbell_Mask_Clear_Register 0x18 /* Host RO Local W, R all 0s 0x18 MSGU - Inbound Doorbell Mask Clear New in SPCv */

Definition at line 92 of file sahwreg.h.

◆ V_Inbound_Doorbell_Mask_Clear_RegisterU

#define V_Inbound_Doorbell_Mask_Clear_RegisterU 0x1C /* Host RO Local W, R all 0s 0x1C MSGU - Inbound Doorbell Mask Clear New in SPCv */

Definition at line 93 of file sahwreg.h.

◆ V_Inbound_Doorbell_Mask_Set_Register

#define V_Inbound_Doorbell_Mask_Set_Register 0x10 /* Host RO Local R/W 0x10 MSGU - Inbound Doorbell Mask Set New in SPCv */

Definition at line 90 of file sahwreg.h.

◆ V_Inbound_Doorbell_Mask_Set_RegisterU

#define V_Inbound_Doorbell_Mask_Set_RegisterU 0x14 /* Host RO Local R/W 0x14 MSGU - Inbound Doorbell Mask Set New in SPCv */

Definition at line 91 of file sahwreg.h.

◆ V_Inbound_Doorbell_Set_Register

#define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound Doorbell Set */

Definition at line 86 of file sahwreg.h.

◆ V_Inbound_Doorbell_Set_RegisterU

#define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound Doorbell Set */

Definition at line 87 of file sahwreg.h.

◆ V_Inbound_Queue_Producer_Indices

#define V_Inbound_Queue_Producer_Indices 0x200 /* typical value real offset is read from table to 0x3FF Host RW Local RO 0x1F200 � 0x1F3FF In DQ storage area, also mapped as WSM*/

Definition at line 117 of file sahwreg.h.

◆ V_MEMBASE_II_ShiftRegister

#define V_MEMBASE_II_ShiftRegister 0x1010

Definition at line 143 of file sahwreg.h.

◆ V_Outbound_Doorbell_Clear_Register

#define V_Outbound_Doorbell_Clear_Register 0x28 /* Host W, R all 0s Local RO 0x28 MSGU - Outbound Doorbell Clear */

Definition at line 96 of file sahwreg.h.

◆ V_Outbound_Doorbell_Clear_RegisterU

#define V_Outbound_Doorbell_Clear_RegisterU 0x2C /* Host W, R all 0s Local RO 0x2C MSGU - Outbound Doorbell Clear */

Definition at line 97 of file sahwreg.h.

◆ V_Outbound_Doorbell_Mask_Clear_Register

#define V_Outbound_Doorbell_Mask_Clear_Register 0x38 /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */

Definition at line 100 of file sahwreg.h.

◆ V_Outbound_Doorbell_Mask_Clear_RegisterU

#define V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New in SPCv 1's clear */

Definition at line 101 of file sahwreg.h.

◆ V_Outbound_Doorbell_Mask_Set_Register

#define V_Outbound_Doorbell_Mask_Set_Register 0x30 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */

Definition at line 98 of file sahwreg.h.

◆ V_Outbound_Doorbell_Mask_Set_RegisterU

#define V_Outbound_Doorbell_Mask_Set_RegisterU 0x34 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's set */

Definition at line 99 of file sahwreg.h.

◆ V_Outbound_Doorbell_Set_Register

#define V_Outbound_Doorbell_Set_Register 0x20 /* Host RO Local R/W 0x20 MSGU - Outbound Doorbell Set */

Definition at line 94 of file sahwreg.h.

◆ V_Outbound_Doorbell_Set_RegisterU

#define V_Outbound_Doorbell_Set_RegisterU 0x24 /* Host RO Local R/W 0x24 MSGU - Outbound Doorbell Set */

Definition at line 95 of file sahwreg.h.

◆ V_Outbound_Queue_Consumer_Indices_Base

#define V_Outbound_Queue_Consumer_Indices_Base 0x100 /* typical value real offset is read from table to 0x1FF Host RW Local RO 0x1F100 � 0x1F1FF In DQ storage area*/

Definition at line 116 of file sahwreg.h.

◆ V_RamEccDbErr

#define V_RamEccDbErr 0x00000018

Definition at line 141 of file sahwreg.h.

◆ V_Scratchpad_0_Register

#define V_Scratchpad_0_Register 0x44 /* Host RO Local R/W 0x120 MSGU - Scratchpad 0 */

Definition at line 103 of file sahwreg.h.

◆ V_Scratchpad_1_Register

#define V_Scratchpad_1_Register 0x48 /* Host RO Local R/W 0x128 MSGU - Scratchpad 1 */

Definition at line 104 of file sahwreg.h.

◆ V_Scratchpad_2_Register

#define V_Scratchpad_2_Register 0x4C /* Host RO Local R/W 0x130 MSGU - Scratchpad 2 */

Definition at line 105 of file sahwreg.h.

◆ V_Scratchpad_3_Register

#define V_Scratchpad_3_Register 0x50 /* Host RO Local R/W 0x138 MSGU - Scratchpad 3 */

Definition at line 106 of file sahwreg.h.

◆ V_Scratchpad_Rsvd_0_Register

#define V_Scratchpad_Rsvd_0_Register 0x6C /* Host RW Local R/W 0x170 MSGU - Scratchpad 10 */

Definition at line 113 of file sahwreg.h.

◆ V_Scratchpad_Rsvd_1_Register

#define V_Scratchpad_Rsvd_1_Register 0x70 /* Host RW Local R/W 0x178 MSGU - Scratchpad 11 */

Definition at line 114 of file sahwreg.h.

◆ V_SoftResetRegister

#define V_SoftResetRegister 0x1000

Definition at line 142 of file sahwreg.h.

Typedef Documentation

◆ spcv_hda_cmd_t

typedef struct spcv_hda_cmd_s spcv_hda_cmd_t

◆ spcv_hda_rsp_t

typedef struct spcv_hda_rsp_s spcv_hda_rsp_t

Enumeration Type Documentation

◆ spc_spcv_offsetmap_e

enum spc_spcv_offsetmap_e

Enumerator
GEN_MSGU_IBDB_SET
GEN_MSGU_ODR
GEN_MSGU_ODCR
GEN_MSGU_SCRATCH_PAD_0
GEN_MSGU_SCRATCH_PAD_1
GEN_MSGU_SCRATCH_PAD_2
GEN_MSGU_SCRATCH_PAD_3
GEN_MSGU_HOST_SCRATCH_PAD_0
GEN_MSGU_HOST_SCRATCH_PAD_1
GEN_MSGU_HOST_SCRATCH_PAD_2
GEN_MSGU_HOST_SCRATCH_PAD_3
GEN_MSGU_ODMR
GEN_PCIE_TRIGGER
GEN_SPC_REG_RESET

Definition at line 686 of file sahwreg.h.

Data Structures

Macros

Typedefs

Enumerations

Detailed Description

Macro Definition Documentation

◆ BOOTTLOADERHDA_IDLE

◆ CEILING

◆ CNTL_OFFSET

◆ COUNT_OFFSET

◆ DEVICE_LCLK_CLEAR

◆ GPIO_ADDR_BASE

◆ GPIO_GPIO_0_0UTPUT_CTL_OFFSET

◆ GSM_ADDR_BASE

◆ GSM_CONFIG_RESET

◆ GSM_CONFIG_RESET_VALUE

◆ GSM_READ_ADDR_PARITY_CHECK

◆ GSM_READ_ADDR_PARITY_INDIC

◆ GSM_WRITE_ADDR_PARITY_CHECK

◆ GSM_WRITE_ADDR_PARITY_INDIC

◆ GSM_WRITE_DATA_PARITY_CHECK

◆ GSM_WRITE_DATA_PARITY_INDIC

◆ GSMSM_AXI_LOWERADDR

◆ HDA_AAP1_DONE

◆ HDA_AES_DIF_FUNC

◆ HDA_C_PA

◆ HDA_C_PA_OFFSET

◆ HDA_CMD_CODE_OFFSET

◆ HDA_CMD_OFFSET1MB

◆ HDA_CMD_OFFSET256K

◆ HDA_CMD_OFFSET512K

◆ HDA_CMD_OFFSET768K

◆ HDA_GSM_OFFSET_BITS

◆ HDA_IOP_DONE

◆ HDA_ISTR_DONE

◆ HDA_PAR_LEN_OFFSET

◆ HDA_RSP_CODE_OFFSET

◆ HDA_RSP_OFFSET1MB

◆ HDA_RSP_OFFSET256K

◆ HDA_RSP_OFFSET512K

◆ HDA_RSP_OFFSET768K

◆ HDA_SEQ_ID_BITS

◆ HDA_SEQ_ID_OFFSET

◆ HDA_STATUS_BITS

◆ HDAC_EXEC_CMD

◆ HDAR_BAD_CMD

◆ HDAR_BAD_IMG

◆ HDAR_EXEC

◆ IBDB_CFG_TABLE_RESET

◆ IBDB_CFG_TABLE_UPDATE

◆ IBDB_IBQ_FREEZE

◆ IBDB_IBQ_UNFREEZE

◆ IBDB_MPICT

◆ IBDB_MPIIF

◆ IBDB_MPIINI

◆ IBDB_MPIIU

◆ ILA_ISTR_ADDROFFSETHDA

◆ ILAHDA_AAP1_IMG_GET

◆ ILAHDA_AAP2_IMG_GET

◆ ILAHDA_EXITGOOD

◆ ILAHDA_IOP_IMG_GET [1/2]

◆ ILAHDA_IOP_IMG_GET [2/2]

◆ ILAHDA_RAAE_IMG_GET

◆ ILAHDAC_AAP1_IMG_DONE

◆ ILAHDAC_AAP2_IMG_DONE

◆ ILAHDAC_GOTOHDA

◆ ILAHDAC_IOP_IMG_DONE

◆ ILAHDAC_ISTR_IMG_DONE

◆ ILAHDAC_RAAE_IMG_DONE

◆ L0_LCLK

◆ L0_LCLK_CLEAR

◆ LCLK

◆ LCLK_CLEAR

◆ MBIC_AAP1_ADDR_BASE

◆ MBIC_GSM_SM_BASE

◆ MBIC_IOP_ADDR_BASE

◆ MBIC_NMI_ENABLE_VPE0_AAP1

◆ MBIC_NMI_ENABLE_VPE0_IOP

◆ MSGU_HOST_INT_MASK

◆ MSGU_HOST_INT_STATUS