37#define SA_CONFIG_MDFD_REGISTRY
39#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \
40 (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
42#if defined(SA_CPU_LITTLE_ENDIAN)
44#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
45 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
47#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
48 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
50#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
51 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
53#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
54 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
56#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
58 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
60#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
64 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
66#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
67 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
68 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
70#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
71 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
72 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
73 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
74 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
76#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
77 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
80#elif defined(SA_CPU_BIG_ENDIAN)
82#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
84 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
86#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
90 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
92#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
93 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
94 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
96#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
97 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
98 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
99 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
100 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
102#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
103 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
105#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
106 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
108#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
109 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
111#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
112 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
114#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
115 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
119#error (Host CPU endianess undefined!!)
123#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \
124 OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \
125 OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \
126 OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \
127 OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved);
138#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \
139 ((((bit16)(_x))&0xFF00)>>8)))
146#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \
147 ((((bit32)(_x))&0x0000FF00)<<8)| \
148 ((((bit32)(_x))&0x00FF0000)>>8)| \
149 ((((bit32)(_x))&0xFF000000)>>24)))
152#if defined(SA_CPU_LITTLE_ENDIAN)
159#ifndef LEBIT16_TO_BIT16
160#define LEBIT16_TO_BIT16(_x) (_x)
168#ifndef BIT16_TO_LEBIT16
169#define BIT16_TO_LEBIT16(_x) (_x)
177#ifndef BEBIT16_TO_BIT16
178#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
186#ifndef BIT16_TO_BEBIT16
187#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
195#ifndef LEBIT32_TO_BIT32
196#define LEBIT32_TO_BIT32(_x) (_x)
204#ifndef BIT32_TO_LEBIT32
205#define BIT32_TO_LEBIT32(_x) (_x)
213#ifndef BEBIT32_TO_BIT32
214#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
222#ifndef BIT32_TO_BEBIT32
223#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
230#ifndef BIT8_TO_BIT32_B0
231#define BIT8_TO_BIT32_B0(_x) ((bit32)(_x))
234#ifndef BIT8_TO_BIT32_B1
235#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8)
238#ifndef BIT8_TO_BIT32_B2
239#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16)
242#ifndef BIT8_TO_BIT32_B3
243#define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24)
249#ifndef BIT32_B0_TO_BIT8
250#define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
253#ifndef BIT32_B1_TO_BIT8
254#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
257#ifndef BIT32_B2_TO_BIT8
258#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
261#ifndef BIT32_B3_TO_BIT8
262#define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
265#elif defined(SA_CPU_BIG_ENDIAN)
272#ifndef LEBIT16_TO_BIT16
273#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
281#ifndef BIT16_TO_LEBIT16
282#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
290#ifndef BEBIT16_TO_BIT16
291#define BEBIT16_TO_BIT16(_x) (_x)
299#ifndef BIT16_TO_BEBIT16
300#define BIT16_TO_BEBIT16(_x) (_x)
308#ifndef LEBIT32_TO_BIT32
309#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
317#ifndef BIT32_TO_LEBIT32
318#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
326#ifndef BEBIT32_TO_BIT32
327#define BEBIT32_TO_BIT32(_x) (_x)
335#ifndef BIT32_TO_BEBIT32
336#define BIT32_TO_BEBIT32(_x) (_x)
343#ifndef BIT8_TO_BIT32_B0
344#define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24)
347#ifndef BIT8_TO_BIT32_B1
348#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16)
351#ifndef BIT8_TO_BIT32_B2
352#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8)
355#ifndef BIT8_TO_BIT32_B3
356#define BIT8_TO_BIT32_B3(_x) ((bit32)(_x))
362#ifndef BIT32_B0_TO_BIT8
363#define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
366#ifndef BIT32_B1_TO_BIT8
367#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
370#ifndef BIT32_B2_TO_BIT8
371#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
374#ifndef BIT32_B3_TO_BIT8
375#define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
380#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN
385#if defined(SA_DMA_LITTLE_ENDIAN)
390#ifndef DMA_BIT32_TO_BIT32
391#define DMA_BIT32_TO_BIT32(_x) (_x)
394#ifndef DMA_LEBIT32_TO_BIT32
395#define DMA_LEBIT32_TO_BIT32(_x) (_x)
398#ifndef DMA_BEBIT32_TO_BIT32
399#define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
402#ifndef BIT32_TO_DMA_BIT32
403#define BIT32_TO_DMA_BIT32(_x) (_x)
406#ifndef BIT32_TO_DMA_LEBIT32
407#define BIT32_TO_DMA_LEBIT32(_x) (_x)
410#ifndef BIT32_TO_DMA_BEBIT32
411#define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
418#ifndef DMA_BIT16_TO_BIT16
419#define DMA_BIT16_TO_BIT16(_x) (_x)
422#ifndef DMA_LEBIT16_TO_BIT16
423#define DMA_LEBIT16_TO_BIT16(_x) (_x)
426#ifndef DMA_BEBIT16_TO_BIT16
427#define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
430#ifndef BIT16_TO_DMA_BIT16
431#define BIT16_TO_DMA_BIT16(_x) (_x)
434#ifndef BIT16_TO_DMA_LEBIT16
435#define BIT16_TO_DMA_LEBIT16(_x) (_x)
438#ifndef BIT16_TO_DMA_BEBIT16
439#define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
442#if defined(SA_CPU_LITTLE_ENDIAN)
444#ifndef BEBIT32_TO_DMA_BEBIT32
445#define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
448#ifndef LEBIT32_TO_DMA_LEBIT32
449#define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
452#ifndef DMA_LEBIT32_TO_LEBIT32
453#define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
456#ifndef DMA_BEBIT32_TO_BEBIT32
457#define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
463#ifndef BEBIT16_TO_DMA_BEBIT16
464#define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
467#ifndef LEBIT16_TO_DMA_LEBIT16
468#define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
471#ifndef DMA_LEBIT16_TO_LEBIT16
472#define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
475#ifndef DMA_BEBIT16_TO_BEBIT16
476#define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
485#ifndef BEBIT32_TO_DMA_BEBIT32
486#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
489#ifndef LEBIT32_TO_DMA_LEBIT32
490#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
493#ifndef DMA_LEBIT32_TO_LEBIT32
494#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
497#ifndef DMA_BEBIT32_TO_BEBIT32
498#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
504#ifndef BEBIT16_TO_DMA_BEBIT16
505#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
508#ifndef LEBIT16_TO_DMA_LEBIT16
509#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
512#ifndef DMA_LEBIT16_TO_LEBIT16
513#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
516#ifndef DMA_BEBIT16_TO_BEBIT16
517#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
525#ifndef BIT8_TO_DMA_BIT32_B0
526#define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x))
529#ifndef BIT8_TO_DMA_BIT32_B1
530#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8)
533#ifndef BIT8_TO_DMA_BIT32_B2
534#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16)
537#ifndef BIT8_TO_DMA_BIT32_B3
538#define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24)
544#ifndef DMA_BIT32_B0_TO_BIT8
545#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
548#ifndef DMA_BIT32_B1_TO_BIT8
549#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
552#ifndef DMA_BIT32_B2_TO_BIT8
553#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
556#ifndef DMA_BIT32_B3_TO_BIT8
557#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
565#elif defined(SA_DMA_BIG_ENDIAN)
573#ifndef DMA_BEBIT32_TO_BIT32
574#define DMA_BEBIT32_TO_BIT32(_x) (_x)
577#ifndef DMA_LEBIT32_TO_BIT32
578#define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
581#ifndef BIT32_TO_DMA_BIT32
582#define BIT32_TO_DMA_BIT32(_x) (_x)
585#ifndef BIT32_TO_DMA_LEBIT32
586#define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
589#ifndef BIT32_TO_DMA_BEBIT32
590#define BIT32_TO_DMA_BEBIT32(_x) (_x)
594#ifndef DMA_BEBIT16_TO_BIT16
595#define DMA_BEBIT16_TO_BIT16(_x) (_x)
598#ifndef DMA_LEBIT16_TO_BIT16
599#define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
602#ifndef BIT16_TO_DMA_BIT16
603#define BIT16_TO_DMA_BIT16(_x) (_x)
606#ifndef BIT16_TO_DMA_LEBIT16
607#define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
610#ifndef BIT16_TO_DMA_BEBIT16
611#define BIT16_TO_DMA_BEBIT16(_x) (_x)
615#if defined(SA_CPU_LITTLE_ENDIAN)
618#ifndef BEBIT32_TO_DMA_BEBIT32
619#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
622#ifndef LEBIT32_TO_DMA_LEBIT32
623#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
626#ifndef DMA_LEBIT32_TO_LEBIT32
627#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
630#ifndef DMA_BEBIT32_TO_BEBIT32
631#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
635#ifndef BEBIT16_TO_DMA_BEBIT16
636#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
639#ifndef LEBIT16_TO_DMA_LEBIT16
640#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
643#ifndef DMA_LEBIT16_TO_LEBIT16
644#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
647#ifndef DMA_BEBIT16_TO_BEBIT16
648#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
655#ifndef BEBIT32_TO_DMA_BEBIT32
656#define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
659#ifndef LEBIT32_TO_DMA_LEBIT32
660#define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
663#ifndef DMA_LEBIT32_TO_LEBIT32
664#define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
667#ifndef DMA_BEBIT32_TO_BEBIT32
668#define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
672#ifndef BEBIT16_TO_DMA_BEBIT16
673#define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
676#ifndef LEBIT16_TO_DMA_LEBIT16
677#define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
680#ifndef DMA_LEBIT16_TO_LEBIT16
681#define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
684#ifndef DMA_BEBIT16_TO_BEBIT16
685#define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
693#ifndef BIT8_TO_DMA_BIT32_B0
694#define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24)
697#ifndef BIT8_TO_DMA_BIT32_B1
698#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16)
701#ifndef BIT8_TO_DMA_BIT32_B2
702#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8)
705#ifndef BIT8_TO_DMA_BIT32_B3
706#define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x))
712#ifndef DMA_BIT32_B0_TO_BIT8
713#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
716#ifndef DMA_BIT32_B1_TO_BIT8
717#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
720#ifndef DMA_BIT32_B2_TO_BIT8
721#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
724#ifndef DMA_BIT32_B3_TO_BIT8
725#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
734#error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN
753#define FW_THIS_VERSION_SPC12G 0x03060005
755#define FW_THIS_VERSION_SPC6G 0x02092400
756#define FW_THIS_VERSION_SPC 0x01110000
759#define STSDK_LL_INTERFACE_VERSION 0x20A
760#define STSDK_LL_OLD_INTERFACE_VERSION 0x1
761#define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G
762#define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G
763#define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G
764#define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000
766#define STSDK_LL_12G_INTERFACE_VERSION 0x302
767#define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G
768#define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G
769#define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G
770#define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000
772#define STSDK_LL_SPC_VERSION 0x01100000
773#define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC
774#define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502
776#define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00
780#define AGSA_RC_SUCCESS 0x00
781#define AGSA_RC_FAILURE 0x01
782#define AGSA_RC_BUSY 0x02
784#define AGSA_RC_HDA_NO_FW_RUNNING 0x03
785#define AGSA_RC_FW_NOT_IN_READY_STATE 0x04
787#define AGSA_RC_VERSION_INCOMPATIBLE 0x05
788#define AGSA_RC_VERSION_UNTESTED 0x06
789#define AGSA_RC_NOT_SUPPORTED 0x07
790#define AGSA_RC_COMPLETE 0x08
795#define AGSA_CACHED_MEM 0x00
796#define AGSA_DMA_MEM 0x01
797#define AGSA_CACHED_DMA_MEM 0x02
799#ifdef SA_ENABLE_TRACE_FUNCTIONS
801#define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
803#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
807#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
809#define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
817#define AGSA_MAX_VALID_PHYS 16
822#define MAX_ESGL_ENTRIES 10
827#define AGSA_MAX_INBOUND_Q 64
828#define AGSA_MAX_OUTBOUND_Q 64
829#define AGSA_MAX_BEST_INBOUND_Q 16
834#define AGSA_PHY_LINK_RESET 0x01
835#define AGSA_PHY_HARD_RESET 0x02
836#define AGSA_PHY_GET_ERROR_COUNTS 0x03
837#define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04
838#define AGSA_PHY_GET_BW_COUNTS 0x05
839#define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10
840#define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12
841#define AGSA_PHY_COMINIT_OOB 0x20
843#define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01
844#define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02
845#define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03
846#define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
847#define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05
848#define AGSA_PHY_SNW3_PAGE 0x06
849#define AGSA_PHY_RATE_CONTROL_PAGE 0x07
850#define AGSA_SAS_PHY_MISC_PAGE 0x08
851#define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08
856#define AGSA_CHIP_RESET 0x00
857#define AGSA_SOFT_RESET 0x01
862#define AG_SA_DISCOVERY_TYPE_SAS 0x00
863#define AG_SA_DISCOVERY_TYPE_SATA 0x01
868#define AG_SA_DISCOVERY_OPTION_FULL_START 0x00
869#define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01
870#define AG_SA_DISCOVERY_OPTION_ABORT 0x02
885#define AGSA_REQTYPE_MASK 0xF0000000
886#define AGSA_REQ_TYPE_UNKNOWN 0x00000000
887#define AGSA_SSP_REQTYPE 0x80000000
888#define AGSA_SMP_REQTYPE 0x40000000
889#define AGSA_SATA_REQTYPE 0x20000000
891#define AGSA_DIR_MASK 0x00000300
892#define AGSA_AUTO_MASK 0x00000080
893#define AGSA_SATA_ATAP_MASK 0x0000FC00
895#define AGSA_DIR_NONE 0x00000000
896#define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100
897#define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200
900#define AGSA_AUTO_GOOD_RESPONSE 0x00000080
903#define AGSA_SSP_INIT 0x00000001
904#define AGSA_SSP_TGT_MODE 0x00000003
905#define AGSA_SSP_TASK_MGNT 0x00000005
906#define AGSA_SSP_TGT_RSP 0x00000006
907#define AGSA_SMP_INIT 0x00000007
908#define AGSA_SMP_TGT 0x00000008
911#define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT)
914#define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT)
917#define AGSA_MSG 0x00000010
918#define AGSA_SSP_EXT_BIT 0x00000020
919#define AGSA_SSP_INDIRECT_BIT 0x00000040
920#define AGSA_MSG_BIT AGSA_MSG >> 2
923#define AGSA_INDIRECT_CDB_BIT 0x00000008
924#define AGSA_SKIP_MASK_BIT 0x00000010
925#define AGSA_ENCRYPT_BIT 0x00000020
926#define AGSA_DIF_BIT 0x00000040
927#define AGSA_DIF_LA_BIT 0x00000080
928#define AGSA_DIRECTION_BITS 0x00000300
929#define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000
930#define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000
933#define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000
934#define AGSA_SSP_TGT_BITS_ODS 0x00008000
935#define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000
936#define AGSA_SSP_TGT_BITS_DEE 0x00002000
937#define AGSA_SSP_TGT_BITS_R 0x00001000
938#define AGSA_SSP_TGT_BITS_DAD 0x00000600
939#define AGSA_SSP_TGT_BITS_DIR 0x00000300
940#define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100
941#define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200
942#define AGSA_SSP_TGT_BITS_AGR 0x00000080
943#define AGSA_SSP_TGT_BITS_RDF 0x00000040
944#define AGSA_SSP_TGT_BITS_RTE 0x00000030
945#define AGSA_SSP_TGT_BITS_AN 0x00000006
949#define AGSA_DIF_UPDATE_BITS 0xFC000000
950#define AGSA_DIF_VERIFY_BITS 0x03F00000
951#define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000
952#define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040
953#define AGSA_DIF_CRC_SEED_BIT 0x00000020
954#define AGSA_DIF_CRC_INVERT_BIT 0x00000010
955#define AGSA_DIF_CRC_VERIFY_BIT 0x00000008
956#define AGSA_DIF_OP_BITS 0x00000007
958#define AGSA_DIF_OP_INSERT 0x00000000
959#define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001
960#define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002
961#define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003
962#define AGSA_DIF_OP_RESERVED2 0x00000004
963#define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005
964#define AGSA_DIF_OP_RESERVED3 0x00000006
965#define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007
969#define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000
970#define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010
971#define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C
972#define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002
975#define AGSA_ENCRYPT_ECB_Mode 0
976#define AGSA_ENCRYPT_XTS_Mode 0x6
979#define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0
980#define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F
983#define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT)
984#define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT)
985#define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT)
986#define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE)
987#define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE)
988#define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE)
989#define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE)
990#define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE)
991#define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE)
992#define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT)
993#define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP)
994#define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT)
995#define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT)
996#define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG)
997#define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG)
998#define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG)
999#define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT)
1000#define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT)
1002#define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT)
1003#define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT)
1005#define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG)
1006#define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG)
1007#define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG)
1008#define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG)
1010#define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF
1012#define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400
1013#define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800
1014#define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00
1015#define AGSA_SATA_ATAP_NON_DATA 0x00001000
1016#define AGSA_SATA_ATAP_PIO 0x00001400
1017#define AGSA_SATA_ATAP_DMA 0x00001800
1018#define AGSA_SATA_ATAP_NCQ 0x00001C00
1019#define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000
1020#define AGSA_SATA_ATAP_PKT 0x00002400
1022#define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA)
1023#define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO)
1024#define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA)
1025#define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ)
1026#define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO)
1027#define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA)
1028#define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ)
1029#define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET)
1030#define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT)
1031#define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT)
1032#define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT)
1033#define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT)
1034#define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT)
1037#define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG)
1038#define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG)
1039#define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG)
1040#define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG)
1041#define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG)
1042#define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG)
1043#define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG)
1044#define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1045#define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1046#define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1048#define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG)
1052#define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF
1057#define AGSA_IBQ_PRIORITY_NORMAL 0x0
1058#define AGSA_IBQ_PRIORITY_HIGH 0x1
1064#define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F
1065#define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001
1066#define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002
1067#define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004
1068#define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008
1071#define AGSA_PHY_MODE_MASK 0x00000030
1072#define AGSA_PHY_MODE_SAS 0x00000010
1073#define AGSA_PHY_MODE_SATA 0x00000020
1076#define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040
1077#define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040
1078#define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000
1084#define AGSA_DEV_INFO_SASSATA_MASK 0x00000010
1085#define AGSA_DEV_INFO_SASSATA_SAS 0x00000010
1086#define AGSA_DEV_INFO_SASSATA_SATA 0x00000000
1089#define AGSA_DEV_INFO_RATE_MASK 0x0000000F
1090#define AGSA_DEV_INFO_RATE_1_5G 0x00000008
1091#define AGSA_DEV_INFO_RATE_3_0G 0x00000009
1092#define AGSA_DEV_INFO_RATE_6_0G 0x0000000A
1093#define AGSA_DEV_INFO_RATE_12_0G 0x0000000B
1096#define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0
1097#define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020
1098#define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040
1099#define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060
1104#define AGSA_ABORT_TASK 0x01
1105#define AGSA_ABORT_TASK_SET 0x02
1106#define AGSA_CLEAR_TASK_SET 0x04
1107#define AGSA_LOGICAL_UNIT_RESET 0x08
1108#define AGSA_IT_NEXUS_RESET 0x10
1109#define AGSA_CLEAR_ACA 0x40
1110#define AGSA_QUERY_TASK 0x80
1111#define AGSA_QUERY_TASK_SET 0x81
1112#define AGSA_QUERY_UNIT_ATTENTION 0x82
1117#define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
1118#define AGSA_INVALID_FRAME 0x2
1119#define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4
1120#define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
1121#define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
1122#define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9
1124#define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA
1126#define AGSA_SATA_BSY_OVERRIDE 0x00080000
1127#define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000
1129#define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40
1130#define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36
1133#define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001
1134#define AGSA_SATA_ENABLE_ENCRYPTION 0x000004
1135#define AGSA_SATA_ENABLE_DIF 0x000008
1136#define AGSA_SATA_SKIP_QWORD 0xFFFF00
1141#define AGSA_SAS_ENABLE_ENCRYPTION 0x0004
1142#define AGSA_SAS_ENABLE_DIF 0x0008
1144#ifdef SAFLAG_USE_DIF_ENC_IOMB
1145#define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010
1148#define AGSA_SAS_ENABLE_SKIP_MASK 0x0010
1149#define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0
1154#define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1
1155#define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2
1156#define AGSA_PHY_CONTROL_DISABLE 0x3
1157#define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5
1158#define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6
1159#define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7
1164#define AGSA_SAS_DIAG_START 0x1
1165#define AGSA_SAS_DIAG_END 0x0
1170#define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1
1171#define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2
1172#define AGSA_PORT_IO_ABORT 0x3
1173#define AGSA_PORT_SET_PORT_RESET_TIME 0x4
1174#define AGSA_PORT_HARD_RESET 0x5
1175#define AGSA_PORT_CLEAN_UP 0x6
1176#define AGSA_STOP_PORT_RECOVERY_TIMER 0x7
1179#define SA_DS_OPERATIONAL 0x1
1180#define SA_DS_PORT_IN_RESET 0x2
1181#define SA_DS_IN_RECOVERY 0x3
1182#define SA_DS_IN_ERROR 0x4
1183#define SA_DS_NON_OPERATIONAL 0x7
1200#define OSSA_SUCCESS 0x00
1201#define OSSA_FAILURE 0x01
1204#define OSSA_RESET_PENDING 0x03
1205#define OSSA_CHIP_FAILED 0x04
1206#define OSSA_FREEZE_FAILED 0x05
1209#define OSSA_PHY_CONTROL_FAILURE 0x03
1212#define OSSA_FAILURE_OUT_OF_RESOURCE 0x01
1213#define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1214#define OSSA_FAILURE_INVALID_PHY_ID 0x03
1215#define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1216#define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1217#define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06
1218#define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1219#define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020
1220#define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021
1221#define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022
1223#define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027
1225#define OSSA_ERR_PORT_INVALID 0x1041
1226#define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042
1228#define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
1230#define OSSA_ERR_PHY_ID_INVALID 0x1061
1231#define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062
1236#define OSSA_INVALID_HANDLE 0x02
1237#define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023
1238#define OSSA_ERR_DEVICE_BUSY 0x1024
1241#define OSSA_RC_ACCEPT 0x00
1242#define OSSA_RC_REJECT 0x01
1245#define OSSA_INVALID_STATE 0x0001
1246#define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025
1247#define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026
1248#define OSSA_ERR_DEVICE_STATE_INVALID 0x0049
1251#define OSSA_DIAG_SUCCESS 0x00
1252#define OSSA_DIAG_INVALID_COMMAND 0x01
1253#define OSSA_REGISTER_ACCESS_TIMEOUT 0x02
1254#define OSSA_DIAG_FAIL 0x02
1255#define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03
1256#define OSSA_DIAG_INVALID_PHY 0x04
1257#define OSSA_MEMORY_ALLOC_FAILURE 0x05
1261#define OSSA_DIAG_SE_SUCCESS 0x00
1262#define OSSA_DIAG_SE_INVALID_PHY_ID 0x01
1263#define OSSA_DIAG_PHY_NOT_DISABLED 0x02
1264#define OSSA_DIAG_OTHER_FAILURE 0x03
1265#define OSSA_DIAG_OPCODE_INVALID 0x03
1268#define OSSA_PORT_CONTROL_FAILURE 0x03
1270#define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004
1271#define OSSA_MPI_ERR_PORT_INVALID 0x1041
1272#define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043
1273#define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044
1274#define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045
1275#define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047
1278#define GET_GSM_SM_INFO 0x02
1279#define GET_IOST_RB_INFO 0x03
1284#define OSSA_HW_EVENT_RESET_START 0x01
1285#define OSSA_HW_EVENT_RESET_COMPLETE 0x02
1286#define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03
1287#define OSSA_HW_EVENT_SAS_PHY_UP 0x04
1288#define OSSA_HW_EVENT_SATA_PHY_UP 0x05
1289#define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06
1290#define OSSA_HW_EVENT_PHY_DOWN 0x07
1292#define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09
1294#define OSSA_HW_EVENT_PHY_ERROR 0x0A
1295#define OSSA_HW_EVENT_BROADCAST_SES 0x0B
1296#define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C
1297#define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D
1299#define OSSA_HW_EVENT_MALFUNCTION 0x0E
1300#define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1301#define OSSA_HW_EVENT_BROADCAST_EXP 0x10
1303#define OSSA_HW_EVENT_PHY_START_STATUS 0x11
1304#define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12
1305#define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13
1306#define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14
1307#define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15
1308#define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16
1309#define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1310#define OSSA_HW_EVENT_PORT_RECOVER 0x18
1311#define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1312#define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20
1313#define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21
1314#define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22
1316#define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25
1318#define OSSA_HW_EVENT_ENCRYPTION 0x83
1319#define OSSA_HW_EVENT_MODE 0x84
1320#define OSSA_HW_EVENT_SECURITY_MODE 0x85
1324#define OSSA_PORT_NOT_ESTABLISHED 0x00
1325#define OSSA_PORT_VALID 0x01
1326#define OSSA_PORT_LOSTCOMM 0x02
1327#define OSSA_PORT_IN_RESET 0x04
1328#define OSSA_PORT_3RDPARTY_RESET 0x07
1329#define OSSA_PORT_INVALID 0x08
1332#define OSSA_CTL_SUCCESS 0x0000
1333#define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001
1334#define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002
1335#define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1336#define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004
1337#define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005
1339#define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX
1346#define OSSA_INBOUND_V_BIT_NOT_SET 0x01
1347#define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02
1348#define OSSA_INBOUND_IOMB_INVALID_OBID 0x03
1353#define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
1354#define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01
1355#define OSSA_FLASH_UPDATE_HDR_ERR 0x02
1356#define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03
1357#define OSSA_FLASH_UPDATE_CRC_ERR 0x04
1358#define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05
1359#define OSSA_FLASH_UPDATE_HW_ERR 0x06
1360#define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E
1362#define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
1363#define OSSA_FLASH_UPDATE_DISABLED 0x11
1364#define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12
1369#define OSSA_DISCOVER_STARTED 0x00
1370#define OSSA_DISCOVER_FOUND_DEVICE 0x01
1371#define OSSA_DISCOVER_REMOVED_DEVICE 0x02
1372#define OSSA_DISCOVER_COMPLETE 0x03
1373#define OSSA_DISCOVER_ABORT 0x04
1374#define OSSA_DISCOVER_ABORT_ERROR_1 0x05
1375#define OSSA_DISCOVER_ABORT_ERROR_2 0x06
1376#define OSSA_DISCOVER_ABORT_ERROR_3 0x07
1377#define OSSA_DISCOVER_ABORT_ERROR_4 0x08
1378#define OSSA_DISCOVER_ABORT_ERROR_5 0x09
1379#define OSSA_DISCOVER_ABORT_ERROR_6 0x0A
1380#define OSSA_DISCOVER_ABORT_ERROR_7 0x0B
1381#define OSSA_DISCOVER_ABORT_ERROR_8 0x0C
1382#define OSSA_DISCOVER_ABORT_ERROR_9 0x0D
1387#define OSSA_DEBUG_LEVEL_0 0x00
1388#define OSSA_DEBUG_LEVEL_1 0x01
1389#define OSSA_DEBUG_LEVEL_2 0x02
1390#define OSSA_DEBUG_LEVEL_3 0x03
1391#define OSSA_DEBUG_LEVEL_4 0x04
1393#define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF
1395#define OSSA_FRAME_TYPE_SSP_CMD 0x06
1396#define OSSA_FRAME_TYPE_SSP_TASK 0x16
1399#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00
1400#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01
1403#define OSSA_DEV_INFO_INVALID_HANDLE 0x01
1404#define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02
1405#define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03
1406#define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04
1409#define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00
1410#define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01
1411#define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02
1412#define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03
1413#define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04
1414#define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05
1417#define AGSA_CMD_DESC_PRBS 0x00
1418#define AGSA_CMD_DESC_CJTPAT 0x01
1419#define AGSA_CMD_DESC_USR_PATTERNS 0x02
1420#define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08
1421#define AGSA_CMD_DESC_PRBS_INVERT 0x09
1422#define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A
1423#define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B
1424#define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C
1425#define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E
1426#define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10
1427#define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11
1428#define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12
1431#define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00
1432#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01
1433#define AGSA_CMD_DESC_DISP_ERR_CNT 0x02
1434#define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05
1435#define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06
1436#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09
1437#define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A
1438#define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B
1439#define AGSA_CMD_DESC_PHY_RST_CNT 0x0C
1440#define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E
1442#define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19
1443#define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A
1444#define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B
1445#define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C
1446#define AGSA_CMD_DESC_ALL 0x1F
1449#define AGSA_NVMD_TWI_DEVICES 0x00
1450#define AGSA_NVMD_CONFIG_SEEPROM 0x01
1451#define AGSA_NVMD_VPD_FLASH 0x04
1452#define AGSA_NVMD_AAP1_REG_FLASH 0x05
1453#define AGSA_NVMD_IOP_REG_FLASH 0x06
1454#define AGSA_NVMD_EXPANSION_ROM 0x07
1455#define AGSA_NVMD_REG_FLASH 0x05
1459#define OSSA_NVMD_SUCCESS 0x0000
1460#define OSSA_NVMD_MODE_ERROR 0x0001
1461#define OSSA_NVMD_LENGTH_ERROR 0x0002
1462#define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005
1463#define OSSA_NVMD_TWI_NACK_ERROR 0x2001
1464#define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002
1465#define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021
1466#define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081
1467#define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082
1468#define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF
1469#define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001
1470#define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002
1471#define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003
1472#define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004
1473#define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005
1474#define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006
1475#define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007
1476#define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008
1477#define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009
1478#define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A
1479#define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B
1480#define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C
1481#define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D
1482#define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E
1487#define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000
1488#define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001
1489#define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002
1490#define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003
1491#define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004
1492#define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005
1493#define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006
1494#define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007
1495#define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008
1502#define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1503#define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000
1504#define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000
1505#define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001
1506#define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002
1507#define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021
1508#define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022
1509#define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023
1512#define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1513#define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1514#define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1515#define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1516#define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1519#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005
1520#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B
1524#define agsaEncryptSMF 0x00000000
1525#define agsaEncryptSMA 0x00000100
1526#define agsaEncryptSMB 0x00000200
1527#define agsaEncryptReturnSMF (1 << 12)
1528#define agsaEncryptAuthorize (1 << 13)
1535#define agsaEncryptAcmMask 0x00ff0000
1536#define agsaEncryptEnableAES_ECB (1 << 16)
1537#define agsaEncryptEnableAES_XTS (1 << 22)
1541#define agsaEncryptCipherModeECB 0x00000001
1542#define agsaEncryptCipherModeXTS 0x00000002
1546#define agsaEncryptStatusNoNVRAM 0x00000001
1547#define agsaEncryptStatusNVRAMErr 0x00000002
1566#define agsaEncryptSectorSize512 0
1568#define agsaEncryptSectorSize4096 2
1569#define agsaEncryptSectorSize4160 3
1570#define agsaEncryptSectorSize4224 4
1572#define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18)
1573#define agsaEncryptDIFSectorSize528 ( 0x19)
1574#define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18)
1575#define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18)
1576#define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18)
1579#define AGSA_ENCRYPT_STORE_NVRAM 1
1584#define agsaModePageGet 1
1585#define agsaModePageSet 2
1590#define AGSA_READ_SGPIO_REGISTER 0x02
1591#define AGSA_WRITE_SGPIO_REGISTER 0x82
1593#define AGSA_SGPIO_CONFIG_REG 0x0
1594#define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1
1595#define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2
1596#define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3
1597#define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4
1602#define OSSA_SGPIO_COMMAND_SUCCESS 0x00
1603#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01
1604#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02
1605#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03
1606#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04
1607#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05
1608#define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06
1609#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19
1610#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81
1611#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A
1612#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82
1613#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83
1614#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D
1615#define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D
1617#define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D
1618#define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C
1623#define OSSA_DFE_MPI_IO_SUCCESS 0x0000
1624#define OSSA_DFE_DATA_OVERFLOW 0x0002
1625#define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004
1626#define OSSA_DFE_CHANNEL_DOWN 0x100E
1627#define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F
1628#define OSSA_DFE_CHANNEL_INVALID 0x1010
1629#define OSSA_DFE_DMA_FAILURE 0x1011
1881#define TYPE_GSM_SPACE 1
1884#define TYPE_NON_FATAL 4
1885#define TYPE_INBOUND_QUEUE 5
1886#define TYPE_OUTBOUND_QUEUE 6
1889#define BAR_SHIFT_GSM_OFFSET 0x400000
1891#define ONE_MEGABYTE 0x100000
1892#define SIXTYFOURKBYTE (1024 * 64)
1896#define TYPE_INBOUND 1
1897#define TYPE_OUTBOUND 2
1955#define OSSA_PCIE_DIAG_SUCCESS 0x0000
1956#define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001
1957#define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002
1958#define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006
1959#define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007
1960#define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008
1961#define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009
1962#define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A
1963#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000
1964#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1965#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1966#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1967#define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042
1968#define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1969#define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005
2341#ifdef SA_CONFIG_MDFD_REGISTRY
2359#if defined(SALLSDK_DEBUG)
2360 bit32 sallDebugLevel;
2363#ifdef SA_ENABLE_PCI_TRIGGER
2367#ifdef SA_ENABLE_TRACE_FUNCTIONS
2368 bit32 TraceDestination;
2369 bit32 TraceBufferSize;
2444#define OQ_SHARE_PATH_BIT 0x00000001
2492#define DISABLE_LOGGING 0x0
2493#define CRITICAL_ERROR 0x1
2496#define INFORMATION 0x4
2497#define DEBUGGING 0x5
2614#define DEV_INFO_MASK 0xFF
2615#define DEV_INFO_MCN_SHIFT 16
2616#define DEV_INFO_IR_SHIFT 20
2618#define RETRY_DEVICE_FLAG (1 << SHIFT0)
2619#define AWT_DEVICE_FLAG (1 << SHIFT1)
2620#define SSP_DEVICE_FLAG (1 << SHIFT20)
2621#define ATAPI_DEVICE_FLAG 0x200000
2622#define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22)
2625#define DEV_LINK_RATE 0x3F
2627#define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \
2628 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo)
2630#define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \
2631 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi)
2633#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \
2634 (((devInfo)->devType_S_Rate & 0xC0) >> 5)
2636#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \
2637 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
2639#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \
2640 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
2703#define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT
2704#define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT
2705#define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT
2706#define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT
2708#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \
2709 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2711#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \
2712 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2714#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \
2715 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2717#define SA_SASDEV_IS_SSP_TARGET(sasDev) \
2718 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2720#define SA_SASDEV_IS_STP_TARGET(sasDev) \
2721 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2723#define SA_SASDEV_IS_SMP_TARGET(sasDev) \
2724 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2726#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \
2727 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT)
2789#define MAX_CDB_LEN 32
2800#define DIF_UDT_SIZE 6
2803#define AGSA_DIF_INSERT 0
2804#define AGSA_DIF_VERIFY_FORWARD 1
2805#define AGSA_DIF_VERIFY_DELETE 2
2806#define AGSA_DIF_VERIFY_REPLACE 3
2807#define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5
2808#define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7
2810#define agsaDIFSectorSize512 0
2811#define agsaDIFSectorSize520 1
2812#define agsaDIFSectorSize4096 2
2813#define agsaDIFSectorSize4160 3
2833#define DIF_FLAG_BITS_ACTION 0x00000007
2834#define DIF_FLAG_BITS_CRC_VER 0x00000008
2835#define DIF_FLAG_BITS_CRC_INV 0x00000010
2836#define DIF_FLAG_BITS_CRC_SEED 0x00000020
2837#define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040
2838#define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080
2839#define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100
2840#define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200
2841#define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00
2842#define DIF_FLAG_BITS_EPRC 0x00001000
2843#define DIF_FLAG_BITS_Reserved 0x0000E000
2844#define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000
2845#define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16
2846#define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000
2847#define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000
2848#define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000
2849#define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000
2850#define DIF_FLAG_BITS_UDTVMASK 0x03F00000
2851#define DIF_FLAG_BITS_UDTV_SHIFT 20
2852#define DIF_FLAG_BITS_UDTUPMASK 0xF6000000
2853#define DIF_FLAG_BITS_UDTUPSHIFT 26
2905#ifdef SA_TESTBASE_EXTRA
2997#define SSP_OPTION_BITS 0x3F
2998#define SSP_OPTION_ODS 0x8000
3000#define SSP_OPTION_OTHR_NO_RETRY 0
3001#define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1
3002#define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2
3003#define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
3005#define SSP_OPTION_DATA_NO_RETRY 0
3006#define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1
3007#define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2
3008#define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
3010#define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4)
3011#define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5)
3012#define SSP_OPTION_ENCRYPT (1 << SHIFT6)
3013#define SSP_OPTION_DIF (1 << SHIFT7)
3014#define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15)
3044#define RESP_OPTION_BITS 0x3
3045#define RESP_OPTION_ODS 0x8000
3094#define smpFrameFlagDirectResponse 0
3095#define smpFrameFlagIndirectResponse 1
3096#define smpFrameFlagDirectPayload 0
3097#define smpFrameFlagIndirectPayload 2
3144#ifdef SA_TESTBASE_EXTRA
3152#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
3153#define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05
3154#define AGSA_IO_GENERAL_CONFIG_PAGE 0x06
3155#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20
3156#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21
3157#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22
3158#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23
3160#ifdef HIALEAH_ENCRYPTION
3162 bit32 numberOfKeksPageCode;
3163 bit32 KeyCardIdKekIndex;
3166 bit32 KeyCardId11_8;
3175#define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
3176#define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8
3191#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
3192#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28
3193#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000
3194#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24
3215#define OperatorAuthenticationEnable_AUT 1
3216#define ReturnToFactoryMode_ARF 2
3267#define AGSA_BIST_TEST 0x1
3268#define AGSA_HMAC_TEST 0x2
3269#define AGSA_SHA_TEST 0x3
3291#define AGSA_ID_SIZE 31
3297#define SA_OPR_MGMNT_FLAG_MASK 0x00003000
3298#define SA_OPR_MGMNT_FLAG_SHIFT 12
3439#define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1
3440#define AGSA_MPI_GENERAL_STATUS_TABLE 2
3441#define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3
3442#define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4
3443#define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5
3444#define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6
3445#define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7
3446#define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8
3453#ifdef SPC_ENABLE_PROFILE
3454typedef struct agsaFwProfile_s
3597#define SA_RESERVED_REQUEST_COUNT 16
3599#ifdef SA_FW_TIMER_READS_STATUS
3600#define SA_FW_TIMER_READS_STATUS_INTERVAL 20
3738typedef struct agsaIOCountInfo_s
3740 bit32 numSSPStarted;
3741 bit32 numSSPAborted;
3742 bit32 numSSPAbortedCB;
3743 bit32 numSSPCompleted;
3744 bit32 numSMPStarted;
3745 bit32 numSMPAborted;
3746 bit32 numSMPAbortedCB;
3747 bit32 numSMPCompleted;
3748 bit32 numSataStarted;
3749 bit32 numSataAborted;
3750 bit32 numSataAbortedCB;
3751 bit32 numSataCompleted;
3754 bit32 numUNKNWRespIOMB;
3755 bit32 numOurIntCount;
3756 bit32 numSpuriousInt;
3762#define LL_COUNTERS 17
3764#define COUNTER_SSP_START 0x000001
3765#define COUNTER_SSP_ABORT 0x000002
3766#define COUNTER_SSPABORT_CB 0x000004
3767#define COUNTER_SSP_COMPLETEED 0x000008
3768#define COUNTER_SMP_START 0x000010
3769#define COUNTER_SMP_ABORT 0x000020
3770#define COUNTER_SMPABORT_CB 0x000040
3771#define COUNTER_SMP_COMPLETEED 0x000080
3772#define COUNTER_SATA_START 0x000100
3773#define COUNTER_SATA_ABORT 0x000200
3774#define COUNTER_SATAABORT_CB 0x000400
3775#define COUNTER_SATA_COMPLETEED 0x000800
3776#define COUNTER_ECHO_SENT 0x001000
3777#define COUNTER_ECHO_CB 0x002000
3778#define COUNTER_UNKWN_IOMB 0x004000
3779#define COUNTER_OUR_INT 0x008000
3780#define COUNTER_SPUR_INT 0x010000
3781#define ALL_COUNTERS 0xFFFFFF
3783typedef union agsaLLCountInfo_s
3785 agsaIOCountInfo_t IOCounter;
3786 bit32 arrayIOCounter[LL_COUNTERS];
3791#define MAX_IO_DEVICE_ENTRIES 4096
3794#ifdef SA_ENABLE_POISION_TLP
3795#define SA_PTNFE_POISION_TLP 1
3797#define SA_PTNFE_POISION_TLP 0
3800#ifdef SA_DISABLE_MDFD
3801#define SA_MDFD_MULTI_DATA_FETCH 1
3803#define SA_MDFD_MULTI_DATA_FETCH 0
3806#ifdef SA_ENABLE_ARBTE
3812#ifdef SA_DISABLE_OB_COAL
3813#define SA_OUTBOUND_COALESCE 0
3815#define SA_OUTBOUND_COALESCE 1
3839typedef struct agsaFastCBBuf_s
3846 void *oneDeviceData;
3849typedef struct agsaFastCommand_s
3857 bit32 extDataLength;
3858 bit8 additionalCdbLen;
3864 bit32 agRequestType;
3866 agsaFastCBBuf_t *safb;
3874#define EnableFPGA_TEST_ICCcontrol 0x01
3875#define EnableFPGA_TEST_ReadDEV 0x02
3876#define EnableFPGA_TEST_WriteCALAll 0x04
3877#define EnableFPGA_TEST_ReconfigSASParams 0x08
3878#define EnableFPGA_TEST_LocalPhyControl 0x10
3879#define EnableFPGA_TEST_PortControl 0x20
3898#define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000
3899#define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01
3900#define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02
3901#define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03
3902#define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04
3903#define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05
3904#define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20
3905#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21
3906#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22
3907#define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23
3908#define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24
3909#define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40
3910#define OSSA_ENCRYPT_AES_BIST_ERR 0x41
3911#define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42
3931#define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000
3933#define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1
3934#define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2
3935#define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4
3936#define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8
3938#define SA_ROLE_CAPABILITIES_CSP 0x001
3939#define SA_ROLE_CAPABILITIES_OPR 0x002
3940#define SA_ROLE_CAPABILITIES_SCO 0x004
3941#define SA_ROLE_CAPABILITIES_STS 0x008
3942#define SA_ROLE_CAPABILITIES_TST 0x010
3943#define SA_ROLE_CAPABILITIES_KEK 0x020
3944#define SA_ROLE_CAPABILITIES_DEK 0x040
3945#define SA_ROLE_CAPABILITIES_IOS 0x080
3946#define SA_ROLE_CAPABILITIES_FWU 0x100
3947#define SA_ROLE_CAPABILITIES_PRM 0x200
struct agsaInterruptConfigPage_s agsaInterruptConfigPage_t
struct agsaHwConfig_s agsaHwConfig_t
structure describe hardware configuration
struct agsaFatalErrorInfo_s agsaFatalErrorInfo_t
describe a fatal error information for a Controller in the SAS/SATA hardware
void(* ossaSMPCompletedCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 agIOStatus, bit32 agIOInfoLen, agsaFrameHandle_t agFrameHandle)
Callback definition for.
struct agsaHWEventMode_s agsaHWEventMode_t
struct agsaQueueInbound_s agsaQueueInbound_t
struct agsaEsgl_s agsaEsgl_t
data structure is used to pass information about the extended scatter-gather list (ESGL) to the LL La...
struct agsaEncryptDek_s agsaEncryptDek_t
void * agsaFrameHandle_t
handle to access frame
struct agsaEncrypt_s agsaEncrypt_t
union agsaSASRequestBody_u agsaSASRequestBody_t
union data structure specifies a request
void(* ossaDeviceRegistrationCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, agsaDevHandle_t *agDevHandle, bit32 deviceID)
Callback definition for .ossaDeviceRegistration.
struct agsaPhyRateControlPage_s agsaPhyRateControlPage_t
describe a Phy Rate Control 4.56 agsaPhyRateControlPage_t Description This profile page is used to re...
struct agsaPhyErrCounters_s agsaPhyErrCounters_t
structure describe error counters of a PHY in the SAS/SATA
struct agsaIOErrorEventStats_s agsaIOErrorEventStats_t
struct _SASG_DESCRIPTOR * PSASG_DESCRIPTOR
struct agsaGpioWriteSetupInfo_s agsaGpioWriteSetupInfo_t
describe a serial GPIO operation in the SAS/SATA hardware
struct agsaDifEncPayload_s agsaDifEncPayload_t
void(* ossaDeregisterDeviceHandleCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaDevHandle_t *agDevHandle, bit32 status)
Callback definition for.
struct agsaFwImg_s agsaFwImg_t
struct agsaEncryptDekConfigPage_s agsaEncryptDekConfigPage_t
struct agsaContext_s agsaContext_t
data structure stores OS specific and LL specific context
struct agsaSASPhyGeneralStatusPage_s agsaSASPhyGeneralStatusPage_t
for the SAS/SATA LL Layer
struct agsaSGpioCfg0 agsaSGpioCfg0_t
describe a serial GPIO operation response in the SAS/SATA hardware
struct agsaPhyConfig_s agsaPhyConfig_t
describe a configuration for a PHY in the SAS/SATA hardware
struct agsaPCIeDiagExecute_s agsaPCIeDiagExecute_t
struct agsaSASDiagExecute_s agsaSASDiagExecute_t
specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer
struct agsaSMPFrame_s agsaSMPFrame_t
data structure describes a SMP request or response frame to be sent on the SAS port
void(* ossaGenericCB_t)(void)
Callback definition for.
struct agsaDeviceInfo_s agsaDeviceInfo_t
data structure provides some information about a SATA device
struct agsaControllerStatus_s agsaControllerStatus_t
describe a status for a Controller in the SAS/SATA hardware
void(* ossaGenericAbortCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 flag, bit32 status)
Callback definition for abort SMP SSP SATA callback.
#define AGSA_MAX_VALID_PHYS
struct agsaGpioEventSetupInfo_s agsaGpioEventSetupInfo_t
describe a GPIO Event Setup Infomation in the SAS/SATA hardware
struct agsaSSPInitiatorRequest_s agsaSSPInitiatorRequest_t
data structure describes a SAS SSP command request to be sent to the target device
struct agsaEncryptSelfTestStatusBitMap_s agsaEncryptSelfTestStatusBitMap_t
struct agsaDif_s agsaDif_t
struct agsaSSPCmdInfoUnitExt_s agsaSSPCmdInfoUnitExt_t
struct agsaEncryptSelfTestBitMap_s agsaEncryptSelfTestBitMap_t
struct agsaQueueOutbound_s agsaQueueOutbound_t
#define AGSA_MAX_OUTBOUND_Q
agsaContext_t agsaDevHandle_t
holds the pointers to the device data structure used by the LL and OS Layers
struct agsaDifDetails_s agsaDifDetails_t
struct agsaEncryptSHATestDescriptor_s agsaEncryptSHATestDescriptor_t
struct agsaSATAInitiatorRequest_s agsaSATAInitiatorRequest_t
data structure describes an STP or direct connect SATA command
struct agsaNVMDData_s agsaNVMDData_t
describe a NVMData for a Controller in the SAS/SATA hardware
void(* ossaSSPCompletedCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 agIOStatus, bit32 agIOInfoLen, void *agParam, bit16 sspTag, bit32 agOtherInfo)
Callback definition for.
struct agsaHWEventEncrypt_s agsaHWEventEncrypt_t
struct agsaEncryptKekBlob_s agsaEncryptKekBlob_t
struct agsaIoGeneralPage_s agsaIoGeneralPage_t
struct agsaEncryptControlParamPage_s agsaEncryptControlParamPage_t
struct agsaUpdateFwFlash_s agsaUpdateFwFlash_t
data structure for firmware flash update saFwFlashUpdate().
void(* ossaSATACompletedCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 agIOStatus, void *agFirstDword, bit32 agIOInfoLen, void *agParam)
Callback definition for.
struct agsaMPIContext_s agsaMPIContext_t
data structure for set fields in MPI table. The agsaMPIContext_t data structure is used to set fields...
struct agsaPhyErrCountersPage_s agsaPhyErrCountersPage_t
used in saGetPhyProfile
#define AGSA_MAX_INBOUND_Q
struct agsaSASAddressID_s agsaSASAddressID_t
describe a SAS address and PHY Identifier
#define MAX_CDB_LEN
data structure describes an SSP Command INFORMATION UNIT
struct agsaEncryptHMACConfigPage_s agsaEncryptHMACConfigPage_t
struct agsaPhyAnalogSettingsPage_s agsaPhyAnalogSettingsPage_t
describe a Phy Analog Setting
struct agsaFlashExtResponse_s agsaFlashExtResponse_t
data structure for firmware flash update saFwFlashUpdate().
struct agsaBarOffset_s agsaBarOffset_t
describe an element of SPC-SPCV converter
struct agsaEncryptDekBlob_s agsaEncryptDekBlob_t
struct agsaSGpioCfg1 agsaSGpioCfg1_t
SGPIO configuration register 1.
struct agsaEncryptHMACTestDescriptor_s agsaEncryptHMACTestDescriptor_t
struct agsaEncryptGeneralPage_s agsaEncryptGeneralPage_t
struct agsaSASReconfig_s agsaSASReconfig_t
describe a SAS ReCofiguration structure in the SAS/SATA hardware
struct agsaEncryptInfo_s agsaEncryptInfo_t
#define OSSA_SGPIO_MAX_READ_DATA_COUNT
struct agsaSgl_s agsaSgl_t
data structure used to pass information about the scatter-gather list to the LL Layer
struct agsaGpioPinSetupInfo_t agsaGpioPinSetupInfo_t
describe a GPIO Pin Setup Infomation in the SAS/SATA hardware
struct agsaPhyAnalogSetupTable_s agsaPhyAnalogSetupTable_t
void(* ossaLocalPhyControlCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 phyId, bit32 phyOperation, bit32 status, void *parm)
struct agsaSSPTargetRequest_s agsaSSPTargetRequest_t
data structure describes a SAS SSP target read and write request
struct agsaControllerInfo_s agsaControllerInfo_t
describe a information for a Controller in the SAS/SATA hardware
struct agsaSASDeviceInfo_s agsaSASDeviceInfo_t
data structure provides some information about a SAS device
struct agsaOffloadDifDetails_s agsaOffloadDifDetails_t
void(* ossaVhistCaptureCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, bit32 len)
struct agsaSASPhyMiscPage_s agsaSASPhyMiscPage_t
struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s agsaSASPhyOpenRejectRetryBackOffThresholdPage_t
describe a Open reject retry backoff threshold page
struct agsaFlashExtExecute_s agsaFlashExtExecute_t
data structure for extended firmware flash update saFwFlashExtUpdate().
agsaContext_t agsaRoot_t
hold points to global data structures used by the LL and OS Layers
struct agsaSATADeviceInfo_s agsaSATADeviceInfo_t
data structure provides some information about a SATA device
struct agsaControllerEventLog_s agsaControllerEventLog_t
specify the controller Event Log for the SAS/SATA LL Layer
agsaContext_t agsaPortContext_t
holds the pointers to the port data structure used by the LL and OS Layers
struct agsaPhyBWCountersPage_s agsaPhyBWCountersPage_t
structure describes bandwidth counters of a PHY in the SAS/SATA
struct agsaEventSource_s agsaEventSource_t
describe a information for a Event in the SAS/SATA hardware
struct agsaSSPTargetResponse_s agsaSSPTargetResponse_t
data structure describes a SAS SSP target response to be issued on the port
void(* ossaDIFEncryptionOffloadStartCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, agsaOffloadDifDetails_t *agsaOffloadDifDetails)
struct agsaSGpioReqResponse_s agsaSGpioReqResponse_t
describe a serial GPIO request and response in the SAS/SATA hardware
agsaContext_t agsaIORequest_t
data structure pointer to IO request structure
struct agsaPhyCalibrationTbl_s agsaPhyCalibrationTbl_t
struct agsaPhyAnalogSetupRegisters_s agsaPhyAnalogSetupRegisters_t
describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware
struct agsaEncryptSHATestResult_s agsaEncryptSHATestResult_t
struct _SASG_DESCRIPTOR SASG_DESCRIPTOR
the data structure describe SG list
struct agsaQueueConfig_s agsaQueueConfig_t
struct agsaSSPInitiatorRequestExt_s agsaSSPInitiatorRequestExt_t
data structure describes a SAS SSP command request Ext to be sent to the target device
struct agsaMem_s agsaMem_t
generic memory descriptor
struct agsaEncryptHMACTestResult_s agsaEncryptHMACTestResult_t
struct agsaSASProtocolTimerConfigurationPage_s agsaSASProtocolTimerConfigurationPage_t
data structure for SAS protocol timer configuration page.
struct agsaPhySNW3Page_s agsaPhySNW3Page_t
Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter.
struct agsaMemoryRequirement_s agsaMemoryRequirement_t
specify the memory allocation requirement for the SAS/SATA LL Layer
#define AGSA_NUM_MEM_CHUNKS
struct agsaGpioReadInfo_s agsaGpioReadInfo_t
describe a GPIO Read Infomation in the SAS/SATA hardware
void(* ossaSetDeviceInfoCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaDevHandle_t *agDevHandle, bit32 status, bit32 option, bit32 param)
Callback definition for.
struct agsaSSPInitiatorRequestIndirect_s agsaSSPInitiatorRequestIndirect_t
struct agsaRegDumpInfo_s agsaRegDumpInfo_t
describe a Register Dump information for a Controller in the SAS/SATA hardware
struct agsaPCIeDiagResponse_s agsaPCIeDiagResponse_t
agsaPCIeDiagResponse_t
union agsabit32bit64_U agsabit32bit64
struct agsaSwConfig_s agsaSwConfig_t
structure describe software configuration
The file defines the error code constants, defined by LL API.
The file defines the constants defined by sas spec.
The file defines the declaration of tSDK APIs.
The file defines the declaration of OS APIs.
the data structure describe SG list
data structure stores OS specific and LL specific context
data structure for set fields in MPI table. The agsaMPIContext_t data structure is used to set fields...
describe a Phy Analog Setting
structure describes bandwidth counters of a PHY in the SAS/SATA
bit32 runningDisparityError
describe a Phy Rate Control 4.56 agsaPhyRateControlPage_t Description This profile page is used to re...
Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter.
for the SAS/SATA LL Layer
describe a Open reject retry backoff threshold page
data structure for SAS protocol timer configuration page.
bit32 Data_Cmd_OPNRJT_RTRY_TMO
bit32 Data_Cmd_OPNRJT_RTRY_THR
bit8 efb_tp_taskAttribute
data structure describes a SAS SSP command request Ext to be sent to the target device
agsaSSPCmdInfoUnitExt_t sspCmdIUExt
union data structure specifies a request
agsaSSPTargetResponse_t sspTargetResponse
agsaSSPInitiatorRequest_t sspInitiatorReq
agsaSSPInitiatorRequestExt_t sspInitiatorReqExt
agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect
agsaSSPTargetRequest_t sspTargetReq
agsaSSPScsiTaskMgntReq_t sspTaskMgntReq
union data structure specifies a FIS from host software