FreeBSD kernel CXGBE device code
t4_hw.c
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1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include "opt_inet.h"
33
34#include <sys/param.h>
35#include <sys/eventhandler.h>
36
37#include "common.h"
38#include "t4_regs.h"
39#include "t4_regs_values.h"
40#include "firmware/t4fw_interface.h"
41
42#undef msleep
43#define msleep(x) do { \
44 if (cold) \
45 DELAY((x) * 1000); \
46 else \
47 pause("t4hw", (x) * hz / 1000); \
48} while (0)
49
65static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
66 int polarity, int attempts, int delay, u32 *valp)
67{
68 while (1) {
69 u32 val = t4_read_reg(adapter, reg);
70
71 if (!!(val & mask) == polarity) {
72 if (valp)
73 *valp = val;
74 return 0;
75 }
76 if (--attempts == 0)
77 return -EAGAIN;
78 if (delay)
79 udelay(delay);
80 }
81}
82
83static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
84 int polarity, int attempts, int delay)
85{
86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
87 delay, NULL);
88}
89
100void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
101 u32 val)
102{
103 u32 v = t4_read_reg(adapter, addr) & ~mask;
104
105 t4_write_reg(adapter, addr, v | val);
106 (void) t4_read_reg(adapter, addr); /* flush */
107}
108
121void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
122 unsigned int data_reg, u32 *vals,
123 unsigned int nregs, unsigned int start_idx)
124{
125 while (nregs--) {
126 t4_write_reg(adap, addr_reg, start_idx);
127 *vals++ = t4_read_reg(adap, data_reg);
128 start_idx++;
129 }
130}
131
144void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
145 unsigned int data_reg, const u32 *vals,
146 unsigned int nregs, unsigned int start_idx)
147{
148 while (nregs--) {
149 t4_write_reg(adap, addr_reg, start_idx++);
150 t4_write_reg(adap, data_reg, *vals++);
151 }
152}
153
154/*
155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
156 * mechanism. This guarantees that we get the real value even if we're
157 * operating within a Virtual Machine and the Hypervisor is trapping our
158 * Configuration Space accesses.
159 *
160 * N.B. This routine should only be used as a last resort: the firmware uses
161 * the backdoor registers on a regular basis and we can end up
162 * conflicting with it's uses!
163 */
164u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
165{
166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
167 u32 val;
168
169 if (chip_id(adap) <= CHELSIO_T5)
170 req |= F_ENABLE;
171 else
172 req |= F_T6_ENABLE;
173
174 if (is_t4(adap))
175 req |= F_LOCALCFG;
176
177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
179
180 /*
181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
182 * Configuration Space read. (None of the other fields matter when
183 * F_ENABLE is 0 so a simple register write is easier than a
184 * read-modify-write via t4_set_reg_field().)
185 */
186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
187
188 return val;
189}
190
191/*
192 * t4_report_fw_error - report firmware error
193 * @adap: the adapter
194 *
195 * The adapter firmware can indicate error conditions to the host.
196 * If the firmware has indicated an error, print out the reason for
197 * the firmware error.
198 */
199void t4_report_fw_error(struct adapter *adap)
200{
201 static const char *const reason[] = {
202 "Crash", /* PCIE_FW_EVAL_CRASH */
203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
209 "Reserved", /* reserved */
210 };
211 u32 pcie_fw;
212
213 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
214 if (pcie_fw & F_PCIE_FW_ERR) {
215 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
216 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
217 }
218}
219
220/*
221 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
222 */
223static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
224 u32 mbox_addr)
225{
226 for ( ; nflit; nflit--, mbox_addr += 8)
227 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
228}
229
230/*
231 * Handle a FW assertion reported in a mailbox.
232 */
233static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
234{
235 CH_ALERT(adap,
236 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
237 asrt->u.assert.filename_0_7,
238 be32_to_cpu(asrt->u.assert.line),
239 be32_to_cpu(asrt->u.assert.x),
240 be32_to_cpu(asrt->u.assert.y));
241}
242
243struct port_tx_state {
244 uint64_t rx_pause;
245 uint64_t tx_frames;
246};
247
248static void
249read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
250{
251 uint32_t rx_pause_reg, tx_frames_reg;
252
253 if (is_t4(sc)) {
254 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
255 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
256 } else {
257 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
258 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
259 }
260
261 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
262 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
263}
264
265static void
266read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
267{
268 int i;
269
270 for_each_port(sc, i)
271 read_tx_state_one(sc, i, &tx_state[i]);
272}
273
274static void
275check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
276{
277 uint32_t port_ctl_reg;
278 uint64_t tx_frames, rx_pause;
279 int i;
280
281 for_each_port(sc, i) {
282 rx_pause = tx_state[i].rx_pause;
283 tx_frames = tx_state[i].tx_frames;
284 read_tx_state_one(sc, i, &tx_state[i]); /* update */
285
286 if (is_t4(sc))
287 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL);
288 else
289 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL);
290 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
291 rx_pause != tx_state[i].rx_pause &&
292 tx_frames == tx_state[i].tx_frames) {
293 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
294 mdelay(1);
295 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
296 }
297 }
298}
299
300#define X_CIM_PF_NOACCESS 0xeeeeeeee
328int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
329 int size, void *rpl, bool sleep_ok, int timeout)
330{
331 /*
332 * We delay in small increments at first in an effort to maintain
333 * responsiveness for simple, fast executing commands but then back
334 * off to larger delays to a maximum retry delay.
335 */
336 static const int delay[] = {
337 1, 1, 3, 5, 10, 10, 20, 50, 100
338 };
339 u32 v;
340 u64 res;
341 int i, ms, delay_idx, ret, next_tx_check;
342 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
343 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
344 u32 ctl;
345 __be64 cmd_rpl[MBOX_LEN/8];
346 u32 pcie_fw;
347 struct port_tx_state tx_state[MAX_NPORTS];
348
349 if (adap->flags & CHK_MBOX_ACCESS)
350 ASSERT_SYNCHRONIZED_OP(adap);
351
352 if (size <= 0 || (size & 15) || size > MBOX_LEN)
353 return -EINVAL;
354
355 if (adap->flags & IS_VF) {
356 if (is_t6(adap))
357 data_reg = FW_T6VF_MBDATA_BASE_ADDR;
358 else
359 data_reg = FW_T4VF_MBDATA_BASE_ADDR;
360 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
361 }
362
363 /*
364 * If we have a negative timeout, that implies that we can't sleep.
365 */
366 if (timeout < 0) {
367 sleep_ok = false;
368 timeout = -timeout;
369 }
370
371 /*
372 * Attempt to gain access to the mailbox.
373 */
374 pcie_fw = 0;
375 if (!(adap->flags & IS_VF)) {
376 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
377 if (pcie_fw & F_PCIE_FW_ERR)
378 goto failed;
379 }
380 for (i = 0; i < 4; i++) {
381 ctl = t4_read_reg(adap, ctl_reg);
382 v = G_MBOWNER(ctl);
383 if (v != X_MBOWNER_NONE)
384 break;
385 }
386
387 /*
388 * If we were unable to gain access, report the error to our caller.
389 */
390 if (v != X_MBOWNER_PL) {
391 if (!(adap->flags & IS_VF)) {
392 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
393 if (pcie_fw & F_PCIE_FW_ERR)
394 goto failed;
395 }
396 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
397 return ret;
398 }
399
400 /*
401 * If we gain ownership of the mailbox and there's a "valid" message
402 * in it, this is likely an asynchronous error message from the
403 * firmware. So we'll report that and then proceed on with attempting
404 * to issue our own command ... which may well fail if the error
405 * presaged the firmware crashing ...
406 */
407 if (ctl & F_MBMSGVALID) {
408 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
409 }
410
411 /*
412 * Copy in the new mailbox command and send it on its way ...
413 */
414 memset(cmd_rpl, 0, sizeof(cmd_rpl));
415 memcpy(cmd_rpl, cmd, size);
416 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
417 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
418 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
419
420 if (adap->flags & IS_VF) {
421 /*
422 * For the VFs, the Mailbox Data "registers" are
423 * actually backed by T4's "MA" interface rather than
424 * PL Registers (as is the case for the PFs). Because
425 * these are in different coherency domains, the write
426 * to the VF's PL-register-backed Mailbox Control can
427 * race in front of the writes to the MA-backed VF
428 * Mailbox Data "registers". So we need to do a
429 * read-back on at least one byte of the VF Mailbox
430 * Data registers before doing the write to the VF
431 * Mailbox Control register.
432 */
433 t4_read_reg(adap, data_reg);
434 }
435
436 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
437 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */
438 next_tx_check = 1000;
439 delay_idx = 0;
440 ms = delay[0];
441
442 /*
443 * Loop waiting for the reply; bail out if we time out or the firmware
444 * reports an error.
445 */
446 for (i = 0; i < timeout; i += ms) {
447 if (!(adap->flags & IS_VF)) {
448 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
449 if (pcie_fw & F_PCIE_FW_ERR)
450 break;
451 }
452
453 if (i >= next_tx_check) {
454 check_tx_state(adap, &tx_state[0]);
455 next_tx_check = i + 1000;
456 }
457
458 if (sleep_ok) {
459 ms = delay[delay_idx]; /* last element may repeat */
460 if (delay_idx < ARRAY_SIZE(delay) - 1)
461 delay_idx++;
462 msleep(ms);
463 } else {
464 mdelay(ms);
465 }
466
467 v = t4_read_reg(adap, ctl_reg);
468 if (v == X_CIM_PF_NOACCESS)
469 continue;
470 if (G_MBOWNER(v) == X_MBOWNER_PL) {
471 if (!(v & F_MBMSGVALID)) {
472 t4_write_reg(adap, ctl_reg,
473 V_MBOWNER(X_MBOWNER_NONE));
474 continue;
475 }
476
477 /*
478 * Retrieve the command reply and release the mailbox.
479 */
480 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
481 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
482 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
483
484 res = be64_to_cpu(cmd_rpl[0]);
485 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
486 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
487 res = V_FW_CMD_RETVAL(EIO);
488 } else if (rpl)
489 memcpy(rpl, cmd_rpl, size);
490 return -G_FW_CMD_RETVAL((int)res);
491 }
492 }
493
494 /*
495 * We timed out waiting for a reply to our mailbox command. Report
496 * the error and also check to see if the firmware reported any
497 * errors ...
498 */
499 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
500 *(const u8 *)cmd, mbox, pcie_fw);
501 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
502 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
503failed:
504 adap->flags &= ~FW_OK;
505 ret = pcie_fw & F_PCIE_FW_ERR ? -ENXIO : -ETIMEDOUT;
506 t4_fatal_err(adap, true);
507 return ret;
508}
509
510int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
511 void *rpl, bool sleep_ok)
512{
513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
514 sleep_ok, FW_CMD_MAX_TIMEOUT);
515
516}
517
518static int t4_edc_err_read(struct adapter *adap, int idx)
519{
520 u32 edc_ecc_err_addr_reg;
521 u32 edc_bist_status_rdata_reg;
522
523 if (is_t4(adap)) {
524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
525 return 0;
526 }
527 if (idx != MEM_EDC0 && idx != MEM_EDC1) {
528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
529 return 0;
530 }
531
532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
534
535 CH_WARN(adap,
536 "edc%d err addr 0x%x: 0x%x.\n",
537 idx, edc_ecc_err_addr_reg,
538 t4_read_reg(adap, edc_ecc_err_addr_reg));
539 CH_WARN(adap,
540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
541 edc_bist_status_rdata_reg,
542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
551
552 return 0;
553}
554
567int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
568{
569 int i;
570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
572
573 if (is_t4(adap)) {
574 mc_bist_cmd_reg = A_MC_BIST_CMD;
575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
579 } else {
580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
584 idx);
585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
586 idx);
587 }
588
589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
590 return -EBUSY;
591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
595 F_START_BIST | V_BIST_CMD_GAP(1));
596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
597 if (i)
598 return i;
599
600#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
601
602 for (i = 15; i >= 0; i--)
603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
604 if (ecc)
605 *ecc = t4_read_reg64(adap, MC_DATA(16));
606#undef MC_DATA
607 return 0;
608}
609
622int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
623{
624 int i;
625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
627
628 if (is_t4(adap)) {
629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
633 idx);
634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
635 idx);
636 } else {
637/*
638 * These macro are missing in t4_regs.h file.
639 * Added temporarily for testing.
640 */
641#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
642#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
647 idx);
648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
649 idx);
650#undef EDC_REG_T5
651#undef EDC_STRIDE_T5
652 }
653
654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
655 return -EBUSY;
656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
659 t4_write_reg(adap, edc_bist_cmd_reg,
660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
662 if (i)
663 return i;
664
665#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
666
667 for (i = 15; i >= 0; i--)
668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
669 if (ecc)
670 *ecc = t4_read_reg64(adap, EDC_DATA(16));
671#undef EDC_DATA
672 return 0;
673}
674
690int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
691 __be32 *buf)
692{
693 u32 pos, start, end, offset;
694 int ret;
695
696 /*
697 * Argument sanity checks ...
698 */
699 if ((addr & 0x3) || (len & 0x3))
700 return -EINVAL;
701
702 /*
703 * The underlaying EDC/MC read routines read 64 bytes at a time so we
704 * need to round down the start and round up the end. We'll start
705 * copying out of the first line at (addr - start) a word at a time.
706 */
707 start = rounddown2(addr, 64);
708 end = roundup2(addr + len, 64);
709 offset = (addr - start)/sizeof(__be32);
710
711 for (pos = start; pos < end; pos += 64, offset = 0) {
712 __be32 data[16];
713
714 /*
715 * Read the chip's memory block and bail if there's an error.
716 */
717 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
719 else
720 ret = t4_edc_read(adap, mtype, pos, data, NULL);
721 if (ret)
722 return ret;
723
724 /*
725 * Copy the data into the caller's memory buffer.
726 */
727 while (offset < 16 && len > 0) {
728 *buf++ = data[offset++];
729 len -= sizeof(__be32);
730 }
731 }
732
733 return 0;
734}
735
736/*
737 * Return the specified PCI-E Configuration Space register from our Physical
738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0)
739 * since we prefer to let the firmware own all of these registers, but if that
740 * fails we go for it directly ourselves.
741 */
742u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
743{
744
745 /*
746 * If fw_attach != 0, construct and send the Firmware LDST Command to
747 * retrieve the specified PCI-E Configuration Space register.
748 */
749 if (drv_fw_attach != 0) {
750 struct fw_ldst_cmd ldst_cmd;
751 int ret;
752
753 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
754 ldst_cmd.op_to_addrspace =
755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
756 F_FW_CMD_REQUEST |
757 F_FW_CMD_READ |
758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
761 ldst_cmd.u.pcie.ctrl_to_fn =
762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
763 ldst_cmd.u.pcie.r = reg;
764
765 /*
766 * If the LDST Command succeeds, return the result, otherwise
767 * fall through to reading it directly ourselves ...
768 */
769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
770 &ldst_cmd);
771 if (ret == 0)
772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
773
774 CH_WARN(adap, "Firmware failed to return "
775 "Configuration Space register %d, err = %d\n",
776 reg, -ret);
777 }
778
779 /*
780 * Read the desired Configuration Space register via the PCI-E
781 * Backdoor mechanism.
782 */
783 return t4_hw_pci_read_cfg4(adap, reg);
784}
785
792unsigned int t4_get_regs_len(struct adapter *adapter)
793{
794 unsigned int chip_version = chip_id(adapter);
795
796 switch (chip_version) {
797 case CHELSIO_T4:
798 if (adapter->flags & IS_VF)
799 return FW_T4VF_REGMAP_SIZE;
800 return T4_REGMAP_SIZE;
801
802 case CHELSIO_T5:
803 case CHELSIO_T6:
804 if (adapter->flags & IS_VF)
805 return FW_T4VF_REGMAP_SIZE;
806 return T5_REGMAP_SIZE;
807 }
808
809 CH_ERR(adapter,
810 "Unsupported chip version %d\n", chip_version);
811 return 0;
812}
813
824void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
825{
826 static const unsigned int t4_reg_ranges[] = {
827 0x1008, 0x1108,
828 0x1180, 0x1184,
829 0x1190, 0x1194,
830 0x11a0, 0x11a4,
831 0x11b0, 0x11b4,
832 0x11fc, 0x123c,
833 0x1300, 0x173c,
834 0x1800, 0x18fc,
835 0x3000, 0x30d8,
836 0x30e0, 0x30e4,
837 0x30ec, 0x5910,
838 0x5920, 0x5924,
839 0x5960, 0x5960,
840 0x5968, 0x5968,
841 0x5970, 0x5970,
842 0x5978, 0x5978,
843 0x5980, 0x5980,
844 0x5988, 0x5988,
845 0x5990, 0x5990,
846 0x5998, 0x5998,
847 0x59a0, 0x59d4,
848 0x5a00, 0x5ae0,
849 0x5ae8, 0x5ae8,
850 0x5af0, 0x5af0,
851 0x5af8, 0x5af8,
852 0x6000, 0x6098,
853 0x6100, 0x6150,
854 0x6200, 0x6208,
855 0x6240, 0x6248,
856 0x6280, 0x62b0,
857 0x62c0, 0x6338,
858 0x6370, 0x638c,
859 0x6400, 0x643c,
860 0x6500, 0x6524,
861 0x6a00, 0x6a04,
862 0x6a14, 0x6a38,
863 0x6a60, 0x6a70,
864 0x6a78, 0x6a78,
865 0x6b00, 0x6b0c,
866 0x6b1c, 0x6b84,
867 0x6bf0, 0x6bf8,
868 0x6c00, 0x6c0c,
869 0x6c1c, 0x6c84,
870 0x6cf0, 0x6cf8,
871 0x6d00, 0x6d0c,
872 0x6d1c, 0x6d84,
873 0x6df0, 0x6df8,
874 0x6e00, 0x6e0c,
875 0x6e1c, 0x6e84,
876 0x6ef0, 0x6ef8,
877 0x6f00, 0x6f0c,
878 0x6f1c, 0x6f84,
879 0x6ff0, 0x6ff8,
880 0x7000, 0x700c,
881 0x701c, 0x7084,
882 0x70f0, 0x70f8,
883 0x7100, 0x710c,
884 0x711c, 0x7184,
885 0x71f0, 0x71f8,
886 0x7200, 0x720c,
887 0x721c, 0x7284,
888 0x72f0, 0x72f8,
889 0x7300, 0x730c,
890 0x731c, 0x7384,
891 0x73f0, 0x73f8,
892 0x7400, 0x7450,
893 0x7500, 0x7530,
894 0x7600, 0x760c,
895 0x7614, 0x761c,
896 0x7680, 0x76cc,
897 0x7700, 0x7798,
898 0x77c0, 0x77fc,
899 0x7900, 0x79fc,
900 0x7b00, 0x7b58,
901 0x7b60, 0x7b84,
902 0x7b8c, 0x7c38,
903 0x7d00, 0x7d38,
904 0x7d40, 0x7d80,
905 0x7d8c, 0x7ddc,
906 0x7de4, 0x7e04,
907 0x7e10, 0x7e1c,
908 0x7e24, 0x7e38,
909 0x7e40, 0x7e44,
910 0x7e4c, 0x7e78,
911 0x7e80, 0x7ea4,
912 0x7eac, 0x7edc,
913 0x7ee8, 0x7efc,
914 0x8dc0, 0x8e04,
915 0x8e10, 0x8e1c,
916 0x8e30, 0x8e78,
917 0x8ea0, 0x8eb8,
918 0x8ec0, 0x8f6c,
919 0x8fc0, 0x9008,
920 0x9010, 0x9058,
921 0x9060, 0x9060,
922 0x9068, 0x9074,
923 0x90fc, 0x90fc,
924 0x9400, 0x9408,
925 0x9410, 0x9458,
926 0x9600, 0x9600,
927 0x9608, 0x9638,
928 0x9640, 0x96bc,
929 0x9800, 0x9808,
930 0x9820, 0x983c,
931 0x9850, 0x9864,
932 0x9c00, 0x9c6c,
933 0x9c80, 0x9cec,
934 0x9d00, 0x9d6c,
935 0x9d80, 0x9dec,
936 0x9e00, 0x9e6c,
937 0x9e80, 0x9eec,
938 0x9f00, 0x9f6c,
939 0x9f80, 0x9fec,
940 0xd004, 0xd004,
941 0xd010, 0xd03c,
942 0xdfc0, 0xdfe0,
943 0xe000, 0xea7c,
944 0xf000, 0x11110,
945 0x11118, 0x11190,
946 0x19040, 0x1906c,
947 0x19078, 0x19080,
948 0x1908c, 0x190e4,
949 0x190f0, 0x190f8,
950 0x19100, 0x19110,
951 0x19120, 0x19124,
952 0x19150, 0x19194,
953 0x1919c, 0x191b0,
954 0x191d0, 0x191e8,
955 0x19238, 0x1924c,
956 0x193f8, 0x1943c,
957 0x1944c, 0x19474,
958 0x19490, 0x194e0,
959 0x194f0, 0x194f8,
960 0x19800, 0x19c08,
961 0x19c10, 0x19c90,
962 0x19ca0, 0x19ce4,
963 0x19cf0, 0x19d40,
964 0x19d50, 0x19d94,
965 0x19da0, 0x19de8,
966 0x19df0, 0x19e40,
967 0x19e50, 0x19e90,
968 0x19ea0, 0x19f4c,
969 0x1a000, 0x1a004,
970 0x1a010, 0x1a06c,
971 0x1a0b0, 0x1a0e4,
972 0x1a0ec, 0x1a0f4,
973 0x1a100, 0x1a108,
974 0x1a114, 0x1a120,
975 0x1a128, 0x1a130,
976 0x1a138, 0x1a138,
977 0x1a190, 0x1a1c4,
978 0x1a1fc, 0x1a1fc,
979 0x1e040, 0x1e04c,
980 0x1e284, 0x1e28c,
981 0x1e2c0, 0x1e2c0,
982 0x1e2e0, 0x1e2e0,
983 0x1e300, 0x1e384,
984 0x1e3c0, 0x1e3c8,
985 0x1e440, 0x1e44c,
986 0x1e684, 0x1e68c,
987 0x1e6c0, 0x1e6c0,
988 0x1e6e0, 0x1e6e0,
989 0x1e700, 0x1e784,
990 0x1e7c0, 0x1e7c8,
991 0x1e840, 0x1e84c,
992 0x1ea84, 0x1ea8c,
993 0x1eac0, 0x1eac0,
994 0x1eae0, 0x1eae0,
995 0x1eb00, 0x1eb84,
996 0x1ebc0, 0x1ebc8,
997 0x1ec40, 0x1ec4c,
998 0x1ee84, 0x1ee8c,
999 0x1eec0, 0x1eec0,
1000 0x1eee0, 0x1eee0,
1001 0x1ef00, 0x1ef84,
1002 0x1efc0, 0x1efc8,
1003 0x1f040, 0x1f04c,
1004 0x1f284, 0x1f28c,
1005 0x1f2c0, 0x1f2c0,
1006 0x1f2e0, 0x1f2e0,
1007 0x1f300, 0x1f384,
1008 0x1f3c0, 0x1f3c8,
1009 0x1f440, 0x1f44c,
1010 0x1f684, 0x1f68c,
1011 0x1f6c0, 0x1f6c0,
1012 0x1f6e0, 0x1f6e0,
1013 0x1f700, 0x1f784,
1014 0x1f7c0, 0x1f7c8,
1015 0x1f840, 0x1f84c,
1016 0x1fa84, 0x1fa8c,
1017 0x1fac0, 0x1fac0,
1018 0x1fae0, 0x1fae0,
1019 0x1fb00, 0x1fb84,
1020 0x1fbc0, 0x1fbc8,
1021 0x1fc40, 0x1fc4c,
1022 0x1fe84, 0x1fe8c,
1023 0x1fec0, 0x1fec0,
1024 0x1fee0, 0x1fee0,
1025 0x1ff00, 0x1ff84,
1026 0x1ffc0, 0x1ffc8,
1027 0x20000, 0x2002c,
1028 0x20100, 0x2013c,
1029 0x20190, 0x201a0,
1030 0x201a8, 0x201b8,
1031 0x201c4, 0x201c8,
1032 0x20200, 0x20318,
1033 0x20400, 0x204b4,
1034 0x204c0, 0x20528,
1035 0x20540, 0x20614,
1036 0x21000, 0x21040,
1037 0x2104c, 0x21060,
1038 0x210c0, 0x210ec,
1039 0x21200, 0x21268,
1040 0x21270, 0x21284,
1041 0x212fc, 0x21388,
1042 0x21400, 0x21404,
1043 0x21500, 0x21500,
1044 0x21510, 0x21518,
1045 0x2152c, 0x21530,
1046 0x2153c, 0x2153c,
1047 0x21550, 0x21554,
1048 0x21600, 0x21600,
1049 0x21608, 0x2161c,
1050 0x21624, 0x21628,
1051 0x21630, 0x21634,
1052 0x2163c, 0x2163c,
1053 0x21700, 0x2171c,
1054 0x21780, 0x2178c,
1055 0x21800, 0x21818,
1056 0x21820, 0x21828,
1057 0x21830, 0x21848,
1058 0x21850, 0x21854,
1059 0x21860, 0x21868,
1060 0x21870, 0x21870,
1061 0x21878, 0x21898,
1062 0x218a0, 0x218a8,
1063 0x218b0, 0x218c8,
1064 0x218d0, 0x218d4,
1065 0x218e0, 0x218e8,
1066 0x218f0, 0x218f0,
1067 0x218f8, 0x21a18,
1068 0x21a20, 0x21a28,
1069 0x21a30, 0x21a48,
1070 0x21a50, 0x21a54,
1071 0x21a60, 0x21a68,
1072 0x21a70, 0x21a70,
1073 0x21a78, 0x21a98,
1074 0x21aa0, 0x21aa8,
1075 0x21ab0, 0x21ac8,
1076 0x21ad0, 0x21ad4,
1077 0x21ae0, 0x21ae8,
1078 0x21af0, 0x21af0,
1079 0x21af8, 0x21c18,
1080 0x21c20, 0x21c20,
1081 0x21c28, 0x21c30,
1082 0x21c38, 0x21c38,
1083 0x21c80, 0x21c98,
1084 0x21ca0, 0x21ca8,
1085 0x21cb0, 0x21cc8,
1086 0x21cd0, 0x21cd4,
1087 0x21ce0, 0x21ce8,
1088 0x21cf0, 0x21cf0,
1089 0x21cf8, 0x21d7c,
1090 0x21e00, 0x21e04,
1091 0x22000, 0x2202c,
1092 0x22100, 0x2213c,
1093 0x22190, 0x221a0,
1094 0x221a8, 0x221b8,
1095 0x221c4, 0x221c8,
1096 0x22200, 0x22318,
1097 0x22400, 0x224b4,
1098 0x224c0, 0x22528,
1099 0x22540, 0x22614,
1100 0x23000, 0x23040,
1101 0x2304c, 0x23060,
1102 0x230c0, 0x230ec,
1103 0x23200, 0x23268,
1104 0x23270, 0x23284,
1105 0x232fc, 0x23388,
1106 0x23400, 0x23404,
1107 0x23500, 0x23500,
1108 0x23510, 0x23518,
1109 0x2352c, 0x23530,
1110 0x2353c, 0x2353c,
1111 0x23550, 0x23554,
1112 0x23600, 0x23600,
1113 0x23608, 0x2361c,
1114 0x23624, 0x23628,
1115 0x23630, 0x23634,
1116 0x2363c, 0x2363c,
1117 0x23700, 0x2371c,
1118 0x23780, 0x2378c,
1119 0x23800, 0x23818,
1120 0x23820, 0x23828,
1121 0x23830, 0x23848,
1122 0x23850, 0x23854,
1123 0x23860, 0x23868,
1124 0x23870, 0x23870,
1125 0x23878, 0x23898,
1126 0x238a0, 0x238a8,
1127 0x238b0, 0x238c8,
1128 0x238d0, 0x238d4,
1129 0x238e0, 0x238e8,
1130 0x238f0, 0x238f0,
1131 0x238f8, 0x23a18,
1132 0x23a20, 0x23a28,
1133 0x23a30, 0x23a48,
1134 0x23a50, 0x23a54,
1135 0x23a60, 0x23a68,
1136 0x23a70, 0x23a70,
1137 0x23a78, 0x23a98,
1138 0x23aa0, 0x23aa8,
1139 0x23ab0, 0x23ac8,
1140 0x23ad0, 0x23ad4,
1141 0x23ae0, 0x23ae8,
1142 0x23af0, 0x23af0,
1143 0x23af8, 0x23c18,
1144 0x23c20, 0x23c20,
1145 0x23c28, 0x23c30,
1146 0x23c38, 0x23c38,
1147 0x23c80, 0x23c98,
1148 0x23ca0, 0x23ca8,
1149 0x23cb0, 0x23cc8,
1150 0x23cd0, 0x23cd4,
1151 0x23ce0, 0x23ce8,
1152 0x23cf0, 0x23cf0,
1153 0x23cf8, 0x23d7c,
1154 0x23e00, 0x23e04,
1155 0x24000, 0x2402c,
1156 0x24100, 0x2413c,
1157 0x24190, 0x241a0,
1158 0x241a8, 0x241b8,
1159 0x241c4, 0x241c8,
1160 0x24200, 0x24318,
1161 0x24400, 0x244b4,
1162 0x244c0, 0x24528,
1163 0x24540, 0x24614,
1164 0x25000, 0x25040,
1165 0x2504c, 0x25060,
1166 0x250c0, 0x250ec,
1167 0x25200, 0x25268,
1168 0x25270, 0x25284,
1169 0x252fc, 0x25388,
1170 0x25400, 0x25404,
1171 0x25500, 0x25500,
1172 0x25510, 0x25518,
1173 0x2552c, 0x25530,
1174 0x2553c, 0x2553c,
1175 0x25550, 0x25554,
1176 0x25600, 0x25600,
1177 0x25608, 0x2561c,
1178 0x25624, 0x25628,
1179 0x25630, 0x25634,
1180 0x2563c, 0x2563c,
1181 0x25700, 0x2571c,
1182 0x25780, 0x2578c,
1183 0x25800, 0x25818,
1184 0x25820, 0x25828,
1185 0x25830, 0x25848,
1186 0x25850, 0x25854,
1187 0x25860, 0x25868,
1188 0x25870, 0x25870,
1189 0x25878, 0x25898,
1190 0x258a0, 0x258a8,
1191 0x258b0, 0x258c8,
1192 0x258d0, 0x258d4,
1193 0x258e0, 0x258e8,
1194 0x258f0, 0x258f0,
1195 0x258f8, 0x25a18,
1196 0x25a20, 0x25a28,
1197 0x25a30, 0x25a48,
1198 0x25a50, 0x25a54,
1199 0x25a60, 0x25a68,
1200 0x25a70, 0x25a70,
1201 0x25a78, 0x25a98,
1202 0x25aa0, 0x25aa8,
1203 0x25ab0, 0x25ac8,
1204 0x25ad0, 0x25ad4,
1205 0x25ae0, 0x25ae8,
1206 0x25af0, 0x25af0,
1207 0x25af8, 0x25c18,
1208 0x25c20, 0x25c20,
1209 0x25c28, 0x25c30,
1210 0x25c38, 0x25c38,
1211 0x25c80, 0x25c98,
1212 0x25ca0, 0x25ca8,
1213 0x25cb0, 0x25cc8,
1214 0x25cd0, 0x25cd4,
1215 0x25ce0, 0x25ce8,
1216 0x25cf0, 0x25cf0,
1217 0x25cf8, 0x25d7c,
1218 0x25e00, 0x25e04,
1219 0x26000, 0x2602c,
1220 0x26100, 0x2613c,
1221 0x26190, 0x261a0,
1222 0x261a8, 0x261b8,
1223 0x261c4, 0x261c8,
1224 0x26200, 0x26318,
1225 0x26400, 0x264b4,
1226 0x264c0, 0x26528,
1227 0x26540, 0x26614,
1228 0x27000, 0x27040,
1229 0x2704c, 0x27060,
1230 0x270c0, 0x270ec,
1231 0x27200, 0x27268,
1232 0x27270, 0x27284,
1233 0x272fc, 0x27388,
1234 0x27400, 0x27404,
1235 0x27500, 0x27500,
1236 0x27510, 0x27518,
1237 0x2752c, 0x27530,
1238 0x2753c, 0x2753c,
1239 0x27550, 0x27554,
1240 0x27600, 0x27600,
1241 0x27608, 0x2761c,
1242 0x27624, 0x27628,
1243 0x27630, 0x27634,
1244 0x2763c, 0x2763c,
1245 0x27700, 0x2771c,
1246 0x27780, 0x2778c,
1247 0x27800, 0x27818,
1248 0x27820, 0x27828,
1249 0x27830, 0x27848,
1250 0x27850, 0x27854,
1251 0x27860, 0x27868,
1252 0x27870, 0x27870,
1253 0x27878, 0x27898,
1254 0x278a0, 0x278a8,
1255 0x278b0, 0x278c8,
1256 0x278d0, 0x278d4,
1257 0x278e0, 0x278e8,
1258 0x278f0, 0x278f0,
1259 0x278f8, 0x27a18,
1260 0x27a20, 0x27a28,
1261 0x27a30, 0x27a48,
1262 0x27a50, 0x27a54,
1263 0x27a60, 0x27a68,
1264 0x27a70, 0x27a70,
1265 0x27a78, 0x27a98,
1266 0x27aa0, 0x27aa8,
1267 0x27ab0, 0x27ac8,
1268 0x27ad0, 0x27ad4,
1269 0x27ae0, 0x27ae8,
1270 0x27af0, 0x27af0,
1271 0x27af8, 0x27c18,
1272 0x27c20, 0x27c20,
1273 0x27c28, 0x27c30,
1274 0x27c38, 0x27c38,
1275 0x27c80, 0x27c98,
1276 0x27ca0, 0x27ca8,
1277 0x27cb0, 0x27cc8,
1278 0x27cd0, 0x27cd4,
1279 0x27ce0, 0x27ce8,
1280 0x27cf0, 0x27cf0,
1281 0x27cf8, 0x27d7c,
1282 0x27e00, 0x27e04,
1283 };
1284
1285 static const unsigned int t4vf_reg_ranges[] = {
1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1287 VF_MPS_REG(A_MPS_VF_CTL),
1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1292 FW_T4VF_MBDATA_BASE_ADDR,
1293 FW_T4VF_MBDATA_BASE_ADDR +
1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1295 };
1296
1297 static const unsigned int t5_reg_ranges[] = {
1298 0x1008, 0x10c0,
1299 0x10cc, 0x10f8,
1300 0x1100, 0x1100,
1301 0x110c, 0x1148,
1302 0x1180, 0x1184,
1303 0x1190, 0x1194,
1304 0x11a0, 0x11a4,
1305 0x11b0, 0x11b4,
1306 0x11fc, 0x123c,
1307 0x1280, 0x173c,
1308 0x1800, 0x18fc,
1309 0x3000, 0x3028,
1310 0x3060, 0x30b0,
1311 0x30b8, 0x30d8,
1312 0x30e0, 0x30fc,
1313 0x3140, 0x357c,
1314 0x35a8, 0x35cc,
1315 0x35ec, 0x35ec,
1316 0x3600, 0x5624,
1317 0x56cc, 0x56ec,
1318 0x56f4, 0x5720,
1319 0x5728, 0x575c,
1320 0x580c, 0x5814,
1321 0x5890, 0x589c,
1322 0x58a4, 0x58ac,
1323 0x58b8, 0x58bc,
1324 0x5940, 0x59c8,
1325 0x59d0, 0x59dc,
1326 0x59fc, 0x5a18,
1327 0x5a60, 0x5a70,
1328 0x5a80, 0x5a9c,
1329 0x5b94, 0x5bfc,
1330 0x6000, 0x6020,
1331 0x6028, 0x6040,
1332 0x6058, 0x609c,
1333 0x60a8, 0x614c,
1334 0x7700, 0x7798,
1335 0x77c0, 0x78fc,
1336 0x7b00, 0x7b58,
1337 0x7b60, 0x7b84,
1338 0x7b8c, 0x7c54,
1339 0x7d00, 0x7d38,
1340 0x7d40, 0x7d80,
1341 0x7d8c, 0x7ddc,
1342 0x7de4, 0x7e04,
1343 0x7e10, 0x7e1c,
1344 0x7e24, 0x7e38,
1345 0x7e40, 0x7e44,
1346 0x7e4c, 0x7e78,
1347 0x7e80, 0x7edc,
1348 0x7ee8, 0x7efc,
1349 0x8dc0, 0x8de0,
1350 0x8df8, 0x8e04,
1351 0x8e10, 0x8e84,
1352 0x8ea0, 0x8f84,
1353 0x8fc0, 0x9058,
1354 0x9060, 0x9060,
1355 0x9068, 0x90f8,
1356 0x9400, 0x9408,
1357 0x9410, 0x9470,
1358 0x9600, 0x9600,
1359 0x9608, 0x9638,
1360 0x9640, 0x96f4,
1361 0x9800, 0x9808,
1362 0x9810, 0x9864,
1363 0x9c00, 0x9c6c,
1364 0x9c80, 0x9cec,
1365 0x9d00, 0x9d6c,
1366 0x9d80, 0x9dec,
1367 0x9e00, 0x9e6c,
1368 0x9e80, 0x9eec,
1369 0x9f00, 0x9f6c,
1370 0x9f80, 0xa020,
1371 0xd000, 0xd004,
1372 0xd010, 0xd03c,
1373 0xdfc0, 0xdfe0,
1374 0xe000, 0x1106c,
1375 0x11074, 0x11088,
1376 0x1109c, 0x11110,
1377 0x11118, 0x1117c,
1378 0x11190, 0x11204,
1379 0x19040, 0x1906c,
1380 0x19078, 0x19080,
1381 0x1908c, 0x190e8,
1382 0x190f0, 0x190f8,
1383 0x19100, 0x19110,
1384 0x19120, 0x19124,
1385 0x19150, 0x19194,
1386 0x1919c, 0x191b0,
1387 0x191d0, 0x191e8,
1388 0x19238, 0x19290,
1389 0x193f8, 0x19428,
1390 0x19430, 0x19444,
1391 0x1944c, 0x1946c,
1392 0x19474, 0x19474,
1393 0x19490, 0x194cc,
1394 0x194f0, 0x194f8,
1395 0x19c00, 0x19c08,
1396 0x19c10, 0x19c60,
1397 0x19c94, 0x19ce4,
1398 0x19cf0, 0x19d40,
1399 0x19d50, 0x19d94,
1400 0x19da0, 0x19de8,
1401 0x19df0, 0x19e10,
1402 0x19e50, 0x19e90,
1403 0x19ea0, 0x19f24,
1404 0x19f34, 0x19f34,
1405 0x19f40, 0x19f50,
1406 0x19f90, 0x19fb4,
1407 0x19fc4, 0x19fe4,
1408 0x1a000, 0x1a004,
1409 0x1a010, 0x1a06c,
1410 0x1a0b0, 0x1a0e4,
1411 0x1a0ec, 0x1a0f8,
1412 0x1a100, 0x1a108,
1413 0x1a114, 0x1a130,
1414 0x1a138, 0x1a1c4,
1415 0x1a1fc, 0x1a1fc,
1416 0x1e008, 0x1e00c,
1417 0x1e040, 0x1e044,
1418 0x1e04c, 0x1e04c,
1419 0x1e284, 0x1e290,
1420 0x1e2c0, 0x1e2c0,
1421 0x1e2e0, 0x1e2e0,
1422 0x1e300, 0x1e384,
1423 0x1e3c0, 0x1e3c8,
1424 0x1e408, 0x1e40c,
1425 0x1e440, 0x1e444,
1426 0x1e44c, 0x1e44c,
1427 0x1e684, 0x1e690,
1428 0x1e6c0, 0x1e6c0,
1429 0x1e6e0, 0x1e6e0,
1430 0x1e700, 0x1e784,
1431 0x1e7c0, 0x1e7c8,
1432 0x1e808, 0x1e80c,
1433 0x1e840, 0x1e844,
1434 0x1e84c, 0x1e84c,
1435 0x1ea84, 0x1ea90,
1436 0x1eac0, 0x1eac0,
1437 0x1eae0, 0x1eae0,
1438 0x1eb00, 0x1eb84,
1439 0x1ebc0, 0x1ebc8,
1440 0x1ec08, 0x1ec0c,
1441 0x1ec40, 0x1ec44,
1442 0x1ec4c, 0x1ec4c,
1443 0x1ee84, 0x1ee90,
1444 0x1eec0, 0x1eec0,
1445 0x1eee0, 0x1eee0,
1446 0x1ef00, 0x1ef84,
1447 0x1efc0, 0x1efc8,
1448 0x1f008, 0x1f00c,
1449 0x1f040, 0x1f044,
1450 0x1f04c, 0x1f04c,
1451 0x1f284, 0x1f290,
1452 0x1f2c0, 0x1f2c0,
1453 0x1f2e0, 0x1f2e0,
1454 0x1f300, 0x1f384,
1455 0x1f3c0, 0x1f3c8,
1456 0x1f408, 0x1f40c,
1457 0x1f440, 0x1f444,
1458 0x1f44c, 0x1f44c,
1459 0x1f684, 0x1f690,
1460 0x1f6c0, 0x1f6c0,
1461 0x1f6e0, 0x1f6e0,
1462 0x1f700, 0x1f784,
1463 0x1f7c0, 0x1f7c8,
1464 0x1f808, 0x1f80c,
1465 0x1f840, 0x1f844,
1466 0x1f84c, 0x1f84c,
1467 0x1fa84, 0x1fa90,
1468 0x1fac0, 0x1fac0,
1469 0x1fae0, 0x1fae0,
1470 0x1fb00, 0x1fb84,
1471 0x1fbc0, 0x1fbc8,
1472 0x1fc08, 0x1fc0c,
1473 0x1fc40, 0x1fc44,
1474 0x1fc4c, 0x1fc4c,
1475 0x1fe84, 0x1fe90,
1476 0x1fec0, 0x1fec0,
1477 0x1fee0, 0x1fee0,
1478 0x1ff00, 0x1ff84,
1479 0x1ffc0, 0x1ffc8,
1480 0x30000, 0x30030,
1481 0x30100, 0x30144,
1482 0x30190, 0x301a0,
1483 0x301a8, 0x301b8,
1484 0x301c4, 0x301c8,
1485 0x301d0, 0x301d0,
1486 0x30200, 0x30318,
1487 0x30400, 0x304b4,
1488 0x304c0, 0x3052c,
1489 0x30540, 0x3061c,
1490 0x30800, 0x30828,
1491 0x30834, 0x30834,
1492 0x308c0, 0x30908,
1493 0x30910, 0x309ac,
1494 0x30a00, 0x30a14,
1495 0x30a1c, 0x30a2c,
1496 0x30a44, 0x30a50,
1497 0x30a74, 0x30a74,
1498 0x30a7c, 0x30afc,
1499 0x30b08, 0x30c24,
1500 0x30d00, 0x30d00,
1501 0x30d08, 0x30d14,
1502 0x30d1c, 0x30d20,
1503 0x30d3c, 0x30d3c,
1504 0x30d48, 0x30d50,
1505 0x31200, 0x3120c,
1506 0x31220, 0x31220,
1507 0x31240, 0x31240,
1508 0x31600, 0x3160c,
1509 0x31a00, 0x31a1c,
1510 0x31e00, 0x31e20,
1511 0x31e38, 0x31e3c,
1512 0x31e80, 0x31e80,
1513 0x31e88, 0x31ea8,
1514 0x31eb0, 0x31eb4,
1515 0x31ec8, 0x31ed4,
1516 0x31fb8, 0x32004,
1517 0x32200, 0x32200,
1518 0x32208, 0x32240,
1519 0x32248, 0x32280,
1520 0x32288, 0x322c0,
1521 0x322c8, 0x322fc,
1522 0x32600, 0x32630,
1523 0x32a00, 0x32abc,
1524 0x32b00, 0x32b10,
1525 0x32b20, 0x32b30,
1526 0x32b40, 0x32b50,
1527 0x32b60, 0x32b70,
1528 0x33000, 0x33028,
1529 0x33030, 0x33048,
1530 0x33060, 0x33068,
1531 0x33070, 0x3309c,
1532 0x330f0, 0x33128,
1533 0x33130, 0x33148,
1534 0x33160, 0x33168,
1535 0x33170, 0x3319c,
1536 0x331f0, 0x33238,
1537 0x33240, 0x33240,
1538 0x33248, 0x33250,
1539 0x3325c, 0x33264,
1540 0x33270, 0x332b8,
1541 0x332c0, 0x332e4,
1542 0x332f8, 0x33338,
1543 0x33340, 0x33340,
1544 0x33348, 0x33350,
1545 0x3335c, 0x33364,
1546 0x33370, 0x333b8,
1547 0x333c0, 0x333e4,
1548 0x333f8, 0x33428,
1549 0x33430, 0x33448,
1550 0x33460, 0x33468,
1551 0x33470, 0x3349c,
1552 0x334f0, 0x33528,
1553 0x33530, 0x33548,
1554 0x33560, 0x33568,
1555 0x33570, 0x3359c,
1556 0x335f0, 0x33638,
1557 0x33640, 0x33640,
1558 0x33648, 0x33650,
1559 0x3365c, 0x33664,
1560 0x33670, 0x336b8,
1561 0x336c0, 0x336e4,
1562 0x336f8, 0x33738,
1563 0x33740, 0x33740,
1564 0x33748, 0x33750,
1565 0x3375c, 0x33764,
1566 0x33770, 0x337b8,
1567 0x337c0, 0x337e4,
1568 0x337f8, 0x337fc,
1569 0x33814, 0x33814,
1570 0x3382c, 0x3382c,
1571 0x33880, 0x3388c,
1572 0x338e8, 0x338ec,
1573 0x33900, 0x33928,
1574 0x33930, 0x33948,
1575 0x33960, 0x33968,
1576 0x33970, 0x3399c,
1577 0x339f0, 0x33a38,
1578 0x33a40, 0x33a40,
1579 0x33a48, 0x33a50,
1580 0x33a5c, 0x33a64,
1581 0x33a70, 0x33ab8,
1582 0x33ac0, 0x33ae4,
1583 0x33af8, 0x33b10,
1584 0x33b28, 0x33b28,
1585 0x33b3c, 0x33b50,
1586 0x33bf0, 0x33c10,
1587 0x33c28, 0x33c28,
1588 0x33c3c, 0x33c50,
1589 0x33cf0, 0x33cfc,
1590 0x34000, 0x34030,
1591 0x34100, 0x34144,
1592 0x34190, 0x341a0,
1593 0x341a8, 0x341b8,
1594 0x341c4, 0x341c8,
1595 0x341d0, 0x341d0,
1596 0x34200, 0x34318,
1597 0x34400, 0x344b4,
1598 0x344c0, 0x3452c,
1599 0x34540, 0x3461c,
1600 0x34800, 0x34828,
1601 0x34834, 0x34834,
1602 0x348c0, 0x34908,
1603 0x34910, 0x349ac,
1604 0x34a00, 0x34a14,
1605 0x34a1c, 0x34a2c,
1606 0x34a44, 0x34a50,
1607 0x34a74, 0x34a74,
1608 0x34a7c, 0x34afc,
1609 0x34b08, 0x34c24,
1610 0x34d00, 0x34d00,
1611 0x34d08, 0x34d14,
1612 0x34d1c, 0x34d20,
1613 0x34d3c, 0x34d3c,
1614 0x34d48, 0x34d50,
1615 0x35200, 0x3520c,
1616 0x35220, 0x35220,
1617 0x35240, 0x35240,
1618 0x35600, 0x3560c,
1619 0x35a00, 0x35a1c,
1620 0x35e00, 0x35e20,
1621 0x35e38, 0x35e3c,
1622 0x35e80, 0x35e80,
1623 0x35e88, 0x35ea8,
1624 0x35eb0, 0x35eb4,
1625 0x35ec8, 0x35ed4,
1626 0x35fb8, 0x36004,
1627 0x36200, 0x36200,
1628 0x36208, 0x36240,
1629 0x36248, 0x36280,
1630 0x36288, 0x362c0,
1631 0x362c8, 0x362fc,
1632 0x36600, 0x36630,
1633 0x36a00, 0x36abc,
1634 0x36b00, 0x36b10,
1635 0x36b20, 0x36b30,
1636 0x36b40, 0x36b50,
1637 0x36b60, 0x36b70,
1638 0x37000, 0x37028,
1639 0x37030, 0x37048,
1640 0x37060, 0x37068,
1641 0x37070, 0x3709c,
1642 0x370f0, 0x37128,
1643 0x37130, 0x37148,
1644 0x37160, 0x37168,
1645 0x37170, 0x3719c,
1646 0x371f0, 0x37238,
1647 0x37240, 0x37240,
1648 0x37248, 0x37250,
1649 0x3725c, 0x37264,
1650 0x37270, 0x372b8,
1651 0x372c0, 0x372e4,
1652 0x372f8, 0x37338,
1653 0x37340, 0x37340,
1654 0x37348, 0x37350,
1655 0x3735c, 0x37364,
1656 0x37370, 0x373b8,
1657 0x373c0, 0x373e4,
1658 0x373f8, 0x37428,
1659 0x37430, 0x37448,
1660 0x37460, 0x37468,
1661 0x37470, 0x3749c,
1662 0x374f0, 0x37528,
1663 0x37530, 0x37548,
1664 0x37560, 0x37568,
1665 0x37570, 0x3759c,
1666 0x375f0, 0x37638,
1667 0x37640, 0x37640,
1668 0x37648, 0x37650,
1669 0x3765c, 0x37664,
1670 0x37670, 0x376b8,
1671 0x376c0, 0x376e4,
1672 0x376f8, 0x37738,
1673 0x37740, 0x37740,
1674 0x37748, 0x37750,
1675 0x3775c, 0x37764,
1676 0x37770, 0x377b8,
1677 0x377c0, 0x377e4,
1678 0x377f8, 0x377fc,
1679 0x37814, 0x37814,
1680 0x3782c, 0x3782c,
1681 0x37880, 0x3788c,
1682 0x378e8, 0x378ec,
1683 0x37900, 0x37928,
1684 0x37930, 0x37948,
1685 0x37960, 0x37968,
1686 0x37970, 0x3799c,
1687 0x379f0, 0x37a38,
1688 0x37a40, 0x37a40,
1689 0x37a48, 0x37a50,
1690 0x37a5c, 0x37a64,
1691 0x37a70, 0x37ab8,
1692 0x37ac0, 0x37ae4,
1693 0x37af8, 0x37b10,
1694 0x37b28, 0x37b28,
1695 0x37b3c, 0x37b50,
1696 0x37bf0, 0x37c10,
1697 0x37c28, 0x37c28,
1698 0x37c3c, 0x37c50,
1699 0x37cf0, 0x37cfc,
1700 0x38000, 0x38030,
1701 0x38100, 0x38144,
1702 0x38190, 0x381a0,
1703 0x381a8, 0x381b8,
1704 0x381c4, 0x381c8,
1705 0x381d0, 0x381d0,
1706 0x38200, 0x38318,
1707 0x38400, 0x384b4,
1708 0x384c0, 0x3852c,
1709 0x38540, 0x3861c,
1710 0x38800, 0x38828,
1711 0x38834, 0x38834,
1712 0x388c0, 0x38908,
1713 0x38910, 0x389ac,
1714 0x38a00, 0x38a14,
1715 0x38a1c, 0x38a2c,
1716 0x38a44, 0x38a50,
1717 0x38a74, 0x38a74,
1718 0x38a7c, 0x38afc,
1719 0x38b08, 0x38c24,
1720 0x38d00, 0x38d00,
1721 0x38d08, 0x38d14,
1722 0x38d1c, 0x38d20,
1723 0x38d3c, 0x38d3c,
1724 0x38d48, 0x38d50,
1725 0x39200, 0x3920c,
1726 0x39220, 0x39220,
1727 0x39240, 0x39240,
1728 0x39600, 0x3960c,
1729 0x39a00, 0x39a1c,
1730 0x39e00, 0x39e20,
1731 0x39e38, 0x39e3c,
1732 0x39e80, 0x39e80,
1733 0x39e88, 0x39ea8,
1734 0x39eb0, 0x39eb4,
1735 0x39ec8, 0x39ed4,
1736 0x39fb8, 0x3a004,
1737 0x3a200, 0x3a200,
1738 0x3a208, 0x3a240,
1739 0x3a248, 0x3a280,
1740 0x3a288, 0x3a2c0,
1741 0x3a2c8, 0x3a2fc,
1742 0x3a600, 0x3a630,
1743 0x3aa00, 0x3aabc,
1744 0x3ab00, 0x3ab10,
1745 0x3ab20, 0x3ab30,
1746 0x3ab40, 0x3ab50,
1747 0x3ab60, 0x3ab70,
1748 0x3b000, 0x3b028,
1749 0x3b030, 0x3b048,
1750 0x3b060, 0x3b068,
1751 0x3b070, 0x3b09c,
1752 0x3b0f0, 0x3b128,
1753 0x3b130, 0x3b148,
1754 0x3b160, 0x3b168,
1755 0x3b170, 0x3b19c,
1756 0x3b1f0, 0x3b238,
1757 0x3b240, 0x3b240,
1758 0x3b248, 0x3b250,
1759 0x3b25c, 0x3b264,
1760 0x3b270, 0x3b2b8,
1761 0x3b2c0, 0x3b2e4,
1762 0x3b2f8, 0x3b338,
1763 0x3b340, 0x3b340,
1764 0x3b348, 0x3b350,
1765 0x3b35c, 0x3b364,
1766 0x3b370, 0x3b3b8,
1767 0x3b3c0, 0x3b3e4,
1768 0x3b3f8, 0x3b428,
1769 0x3b430, 0x3b448,
1770 0x3b460, 0x3b468,
1771 0x3b470, 0x3b49c,
1772 0x3b4f0, 0x3b528,
1773 0x3b530, 0x3b548,
1774 0x3b560, 0x3b568,
1775 0x3b570, 0x3b59c,
1776 0x3b5f0, 0x3b638,
1777 0x3b640, 0x3b640,
1778 0x3b648, 0x3b650,
1779 0x3b65c, 0x3b664,
1780 0x3b670, 0x3b6b8,
1781 0x3b6c0, 0x3b6e4,
1782 0x3b6f8, 0x3b738,
1783 0x3b740, 0x3b740,
1784 0x3b748, 0x3b750,
1785 0x3b75c, 0x3b764,
1786 0x3b770, 0x3b7b8,
1787 0x3b7c0, 0x3b7e4,
1788 0x3b7f8, 0x3b7fc,
1789 0x3b814, 0x3b814,
1790 0x3b82c, 0x3b82c,
1791 0x3b880, 0x3b88c,
1792 0x3b8e8, 0x3b8ec,
1793 0x3b900, 0x3b928,
1794 0x3b930, 0x3b948,
1795 0x3b960, 0x3b968,
1796 0x3b970, 0x3b99c,
1797 0x3b9f0, 0x3ba38,
1798 0x3ba40, 0x3ba40,
1799 0x3ba48, 0x3ba50,
1800 0x3ba5c, 0x3ba64,
1801 0x3ba70, 0x3bab8,
1802 0x3bac0, 0x3bae4,
1803 0x3baf8, 0x3bb10,
1804 0x3bb28, 0x3bb28,
1805 0x3bb3c, 0x3bb50,
1806 0x3bbf0, 0x3bc10,
1807 0x3bc28, 0x3bc28,
1808 0x3bc3c, 0x3bc50,
1809 0x3bcf0, 0x3bcfc,
1810 0x3c000, 0x3c030,
1811 0x3c100, 0x3c144,
1812 0x3c190, 0x3c1a0,
1813 0x3c1a8, 0x3c1b8,
1814 0x3c1c4, 0x3c1c8,
1815 0x3c1d0, 0x3c1d0,
1816 0x3c200, 0x3c318,
1817 0x3c400, 0x3c4b4,
1818 0x3c4c0, 0x3c52c,
1819 0x3c540, 0x3c61c,
1820 0x3c800, 0x3c828,
1821 0x3c834, 0x3c834,
1822 0x3c8c0, 0x3c908,
1823 0x3c910, 0x3c9ac,
1824 0x3ca00, 0x3ca14,
1825 0x3ca1c, 0x3ca2c,
1826 0x3ca44, 0x3ca50,
1827 0x3ca74, 0x3ca74,
1828 0x3ca7c, 0x3cafc,
1829 0x3cb08, 0x3cc24,
1830 0x3cd00, 0x3cd00,
1831 0x3cd08, 0x3cd14,
1832 0x3cd1c, 0x3cd20,
1833 0x3cd3c, 0x3cd3c,
1834 0x3cd48, 0x3cd50,
1835 0x3d200, 0x3d20c,
1836 0x3d220, 0x3d220,
1837 0x3d240, 0x3d240,
1838 0x3d600, 0x3d60c,
1839 0x3da00, 0x3da1c,
1840 0x3de00, 0x3de20,
1841 0x3de38, 0x3de3c,
1842 0x3de80, 0x3de80,
1843 0x3de88, 0x3dea8,
1844 0x3deb0, 0x3deb4,
1845 0x3dec8, 0x3ded4,
1846 0x3dfb8, 0x3e004,
1847 0x3e200, 0x3e200,
1848 0x3e208, 0x3e240,
1849 0x3e248, 0x3e280,
1850 0x3e288, 0x3e2c0,
1851 0x3e2c8, 0x3e2fc,
1852 0x3e600, 0x3e630,
1853 0x3ea00, 0x3eabc,
1854 0x3eb00, 0x3eb10,
1855 0x3eb20, 0x3eb30,
1856 0x3eb40, 0x3eb50,
1857 0x3eb60, 0x3eb70,
1858 0x3f000, 0x3f028,
1859 0x3f030, 0x3f048,
1860 0x3f060, 0x3f068,
1861 0x3f070, 0x3f09c,
1862 0x3f0f0, 0x3f128,
1863 0x3f130, 0x3f148,
1864 0x3f160, 0x3f168,
1865 0x3f170, 0x3f19c,
1866 0x3f1f0, 0x3f238,
1867 0x3f240, 0x3f240,
1868 0x3f248, 0x3f250,
1869 0x3f25c, 0x3f264,
1870 0x3f270, 0x3f2b8,
1871 0x3f2c0, 0x3f2e4,
1872 0x3f2f8, 0x3f338,
1873 0x3f340, 0x3f340,
1874 0x3f348, 0x3f350,
1875 0x3f35c, 0x3f364,
1876 0x3f370, 0x3f3b8,
1877 0x3f3c0, 0x3f3e4,
1878 0x3f3f8, 0x3f428,
1879 0x3f430, 0x3f448,
1880 0x3f460, 0x3f468,
1881 0x3f470, 0x3f49c,
1882 0x3f4f0, 0x3f528,
1883 0x3f530, 0x3f548,
1884 0x3f560, 0x3f568,
1885 0x3f570, 0x3f59c,
1886 0x3f5f0, 0x3f638,
1887 0x3f640, 0x3f640,
1888 0x3f648, 0x3f650,
1889 0x3f65c, 0x3f664,
1890 0x3f670, 0x3f6b8,
1891 0x3f6c0, 0x3f6e4,
1892 0x3f6f8, 0x3f738,
1893 0x3f740, 0x3f740,
1894 0x3f748, 0x3f750,
1895 0x3f75c, 0x3f764,
1896 0x3f770, 0x3f7b8,
1897 0x3f7c0, 0x3f7e4,
1898 0x3f7f8, 0x3f7fc,
1899 0x3f814, 0x3f814,
1900 0x3f82c, 0x3f82c,
1901 0x3f880, 0x3f88c,
1902 0x3f8e8, 0x3f8ec,
1903 0x3f900, 0x3f928,
1904 0x3f930, 0x3f948,
1905 0x3f960, 0x3f968,
1906 0x3f970, 0x3f99c,
1907 0x3f9f0, 0x3fa38,
1908 0x3fa40, 0x3fa40,
1909 0x3fa48, 0x3fa50,
1910 0x3fa5c, 0x3fa64,
1911 0x3fa70, 0x3fab8,
1912 0x3fac0, 0x3fae4,
1913 0x3faf8, 0x3fb10,
1914 0x3fb28, 0x3fb28,
1915 0x3fb3c, 0x3fb50,
1916 0x3fbf0, 0x3fc10,
1917 0x3fc28, 0x3fc28,
1918 0x3fc3c, 0x3fc50,
1919 0x3fcf0, 0x3fcfc,
1920 0x40000, 0x4000c,
1921 0x40040, 0x40050,
1922 0x40060, 0x40068,
1923 0x4007c, 0x4008c,
1924 0x40094, 0x400b0,
1925 0x400c0, 0x40144,
1926 0x40180, 0x4018c,
1927 0x40200, 0x40254,
1928 0x40260, 0x40264,
1929 0x40270, 0x40288,
1930 0x40290, 0x40298,
1931 0x402ac, 0x402c8,
1932 0x402d0, 0x402e0,
1933 0x402f0, 0x402f0,
1934 0x40300, 0x4033c,
1935 0x403f8, 0x403fc,
1936 0x41304, 0x413c4,
1937 0x41400, 0x4140c,
1938 0x41414, 0x4141c,
1939 0x41480, 0x414d0,
1940 0x44000, 0x44054,
1941 0x4405c, 0x44078,
1942 0x440c0, 0x44174,
1943 0x44180, 0x441ac,
1944 0x441b4, 0x441b8,
1945 0x441c0, 0x44254,
1946 0x4425c, 0x44278,
1947 0x442c0, 0x44374,
1948 0x44380, 0x443ac,
1949 0x443b4, 0x443b8,
1950 0x443c0, 0x44454,
1951 0x4445c, 0x44478,
1952 0x444c0, 0x44574,
1953 0x44580, 0x445ac,
1954 0x445b4, 0x445b8,
1955 0x445c0, 0x44654,
1956 0x4465c, 0x44678,
1957 0x446c0, 0x44774,
1958 0x44780, 0x447ac,
1959 0x447b4, 0x447b8,
1960 0x447c0, 0x44854,
1961 0x4485c, 0x44878,
1962 0x448c0, 0x44974,
1963 0x44980, 0x449ac,
1964 0x449b4, 0x449b8,
1965 0x449c0, 0x449fc,
1966 0x45000, 0x45004,
1967 0x45010, 0x45030,
1968 0x45040, 0x45060,
1969 0x45068, 0x45068,
1970 0x45080, 0x45084,
1971 0x450a0, 0x450b0,
1972 0x45200, 0x45204,
1973 0x45210, 0x45230,
1974 0x45240, 0x45260,
1975 0x45268, 0x45268,
1976 0x45280, 0x45284,
1977 0x452a0, 0x452b0,
1978 0x460c0, 0x460e4,
1979 0x47000, 0x4703c,
1980 0x47044, 0x4708c,
1981 0x47200, 0x47250,
1982 0x47400, 0x47408,
1983 0x47414, 0x47420,
1984 0x47600, 0x47618,
1985 0x47800, 0x47814,
1986 0x48000, 0x4800c,
1987 0x48040, 0x48050,
1988 0x48060, 0x48068,
1989 0x4807c, 0x4808c,
1990 0x48094, 0x480b0,
1991 0x480c0, 0x48144,
1992 0x48180, 0x4818c,
1993 0x48200, 0x48254,
1994 0x48260, 0x48264,
1995 0x48270, 0x48288,
1996 0x48290, 0x48298,
1997 0x482ac, 0x482c8,
1998 0x482d0, 0x482e0,
1999 0x482f0, 0x482f0,
2000 0x48300, 0x4833c,
2001 0x483f8, 0x483fc,
2002 0x49304, 0x493c4,
2003 0x49400, 0x4940c,
2004 0x49414, 0x4941c,
2005 0x49480, 0x494d0,
2006 0x4c000, 0x4c054,
2007 0x4c05c, 0x4c078,
2008 0x4c0c0, 0x4c174,
2009 0x4c180, 0x4c1ac,
2010 0x4c1b4, 0x4c1b8,
2011 0x4c1c0, 0x4c254,
2012 0x4c25c, 0x4c278,
2013 0x4c2c0, 0x4c374,
2014 0x4c380, 0x4c3ac,
2015 0x4c3b4, 0x4c3b8,
2016 0x4c3c0, 0x4c454,
2017 0x4c45c, 0x4c478,
2018 0x4c4c0, 0x4c574,
2019 0x4c580, 0x4c5ac,
2020 0x4c5b4, 0x4c5b8,
2021 0x4c5c0, 0x4c654,
2022 0x4c65c, 0x4c678,
2023 0x4c6c0, 0x4c774,
2024 0x4c780, 0x4c7ac,
2025 0x4c7b4, 0x4c7b8,
2026 0x4c7c0, 0x4c854,
2027 0x4c85c, 0x4c878,
2028 0x4c8c0, 0x4c974,
2029 0x4c980, 0x4c9ac,
2030 0x4c9b4, 0x4c9b8,
2031 0x4c9c0, 0x4c9fc,
2032 0x4d000, 0x4d004,
2033 0x4d010, 0x4d030,
2034 0x4d040, 0x4d060,
2035 0x4d068, 0x4d068,
2036 0x4d080, 0x4d084,
2037 0x4d0a0, 0x4d0b0,
2038 0x4d200, 0x4d204,
2039 0x4d210, 0x4d230,
2040 0x4d240, 0x4d260,
2041 0x4d268, 0x4d268,
2042 0x4d280, 0x4d284,
2043 0x4d2a0, 0x4d2b0,
2044 0x4e0c0, 0x4e0e4,
2045 0x4f000, 0x4f03c,
2046 0x4f044, 0x4f08c,
2047 0x4f200, 0x4f250,
2048 0x4f400, 0x4f408,
2049 0x4f414, 0x4f420,
2050 0x4f600, 0x4f618,
2051 0x4f800, 0x4f814,
2052 0x50000, 0x50084,
2053 0x50090, 0x500cc,
2054 0x50400, 0x50400,
2055 0x50800, 0x50884,
2056 0x50890, 0x508cc,
2057 0x50c00, 0x50c00,
2058 0x51000, 0x5101c,
2059 0x51300, 0x51308,
2060 };
2061
2062 static const unsigned int t5vf_reg_ranges[] = {
2063 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2064 VF_MPS_REG(A_MPS_VF_CTL),
2065 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2066 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2068 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2069 FW_T4VF_MBDATA_BASE_ADDR,
2070 FW_T4VF_MBDATA_BASE_ADDR +
2071 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2072 };
2073
2074 static const unsigned int t6_reg_ranges[] = {
2075 0x1008, 0x101c,
2076 0x1024, 0x10a8,
2077 0x10b4, 0x10f8,
2078 0x1100, 0x1114,
2079 0x111c, 0x112c,
2080 0x1138, 0x113c,
2081 0x1144, 0x114c,
2082 0x1180, 0x1184,
2083 0x1190, 0x1194,
2084 0x11a0, 0x11a4,
2085 0x11b0, 0x11c4,
2086 0x11fc, 0x123c,
2087 0x1254, 0x1274,
2088 0x1280, 0x133c,
2089 0x1800, 0x18fc,
2090 0x3000, 0x302c,
2091 0x3060, 0x30b0,
2092 0x30b8, 0x30d8,
2093 0x30e0, 0x30fc,
2094 0x3140, 0x357c,
2095 0x35a8, 0x35cc,
2096 0x35ec, 0x35ec,
2097 0x3600, 0x5624,
2098 0x56cc, 0x56ec,
2099 0x56f4, 0x5720,
2100 0x5728, 0x575c,
2101 0x580c, 0x5814,
2102 0x5890, 0x589c,
2103 0x58a4, 0x58ac,
2104 0x58b8, 0x58bc,
2105 0x5940, 0x595c,
2106 0x5980, 0x598c,
2107 0x59b0, 0x59c8,
2108 0x59d0, 0x59dc,
2109 0x59fc, 0x5a18,
2110 0x5a60, 0x5a6c,
2111 0x5a80, 0x5a8c,
2112 0x5a94, 0x5a9c,
2113 0x5b94, 0x5bfc,
2114 0x5c10, 0x5e48,
2115 0x5e50, 0x5e94,
2116 0x5ea0, 0x5eb0,
2117 0x5ec0, 0x5ec0,
2118 0x5ec8, 0x5ed0,
2119 0x5ee0, 0x5ee0,
2120 0x5ef0, 0x5ef0,
2121 0x5f00, 0x5f00,
2122 0x6000, 0x6020,
2123 0x6028, 0x6040,
2124 0x6058, 0x609c,
2125 0x60a8, 0x619c,
2126 0x7700, 0x7798,
2127 0x77c0, 0x7880,
2128 0x78cc, 0x78fc,
2129 0x7b00, 0x7b58,
2130 0x7b60, 0x7b84,
2131 0x7b8c, 0x7c54,
2132 0x7d00, 0x7d38,
2133 0x7d40, 0x7d84,
2134 0x7d8c, 0x7ddc,
2135 0x7de4, 0x7e04,
2136 0x7e10, 0x7e1c,
2137 0x7e24, 0x7e38,
2138 0x7e40, 0x7e44,
2139 0x7e4c, 0x7e78,
2140 0x7e80, 0x7edc,
2141 0x7ee8, 0x7efc,
2142 0x8dc0, 0x8de0,
2143 0x8df8, 0x8e04,
2144 0x8e10, 0x8e84,
2145 0x8ea0, 0x8f88,
2146 0x8fb8, 0x9058,
2147 0x9060, 0x9060,
2148 0x9068, 0x90f8,
2149 0x9100, 0x9124,
2150 0x9400, 0x9470,
2151 0x9600, 0x9600,
2152 0x9608, 0x9638,
2153 0x9640, 0x9704,
2154 0x9710, 0x971c,
2155 0x9800, 0x9808,
2156 0x9810, 0x9864,
2157 0x9c00, 0x9c6c,
2158 0x9c80, 0x9cec,
2159 0x9d00, 0x9d6c,
2160 0x9d80, 0x9dec,
2161 0x9e00, 0x9e6c,
2162 0x9e80, 0x9eec,
2163 0x9f00, 0x9f6c,
2164 0x9f80, 0xa020,
2165 0xd000, 0xd03c,
2166 0xd100, 0xd118,
2167 0xd200, 0xd214,
2168 0xd220, 0xd234,
2169 0xd240, 0xd254,
2170 0xd260, 0xd274,
2171 0xd280, 0xd294,
2172 0xd2a0, 0xd2b4,
2173 0xd2c0, 0xd2d4,
2174 0xd2e0, 0xd2f4,
2175 0xd300, 0xd31c,
2176 0xdfc0, 0xdfe0,
2177 0xe000, 0xf008,
2178 0xf010, 0xf018,
2179 0xf020, 0xf028,
2180 0x11000, 0x11014,
2181 0x11048, 0x1106c,
2182 0x11074, 0x11088,
2183 0x11098, 0x11120,
2184 0x1112c, 0x1117c,
2185 0x11190, 0x112e0,
2186 0x11300, 0x1130c,
2187 0x12000, 0x1206c,
2188 0x19040, 0x1906c,
2189 0x19078, 0x19080,
2190 0x1908c, 0x190e8,
2191 0x190f0, 0x190f8,
2192 0x19100, 0x19110,
2193 0x19120, 0x19124,
2194 0x19150, 0x19194,
2195 0x1919c, 0x191b0,
2196 0x191d0, 0x191e8,
2197 0x19238, 0x19290,
2198 0x192a4, 0x192b0,
2199 0x19348, 0x1934c,
2200 0x193f8, 0x19418,
2201 0x19420, 0x19428,
2202 0x19430, 0x19444,
2203 0x1944c, 0x1946c,
2204 0x19474, 0x19474,
2205 0x19490, 0x194cc,
2206 0x194f0, 0x194f8,
2207 0x19c00, 0x19c48,
2208 0x19c50, 0x19c80,
2209 0x19c94, 0x19c98,
2210 0x19ca0, 0x19cbc,
2211 0x19ce4, 0x19ce4,
2212 0x19cf0, 0x19cf8,
2213 0x19d00, 0x19d28,
2214 0x19d50, 0x19d78,
2215 0x19d94, 0x19d98,
2216 0x19da0, 0x19de0,
2217 0x19df0, 0x19e10,
2218 0x19e50, 0x19e6c,
2219 0x19ea0, 0x19ebc,
2220 0x19ec4, 0x19ef4,
2221 0x19f04, 0x19f2c,
2222 0x19f34, 0x19f34,
2223 0x19f40, 0x19f50,
2224 0x19f90, 0x19fac,
2225 0x19fc4, 0x19fc8,
2226 0x19fd0, 0x19fe4,
2227 0x1a000, 0x1a004,
2228 0x1a010, 0x1a06c,
2229 0x1a0b0, 0x1a0e4,
2230 0x1a0ec, 0x1a0f8,
2231 0x1a100, 0x1a108,
2232 0x1a114, 0x1a130,
2233 0x1a138, 0x1a1c4,
2234 0x1a1fc, 0x1a1fc,
2235 0x1e008, 0x1e00c,
2236 0x1e040, 0x1e044,
2237 0x1e04c, 0x1e04c,
2238 0x1e284, 0x1e290,
2239 0x1e2c0, 0x1e2c0,
2240 0x1e2e0, 0x1e2e0,
2241 0x1e300, 0x1e384,
2242 0x1e3c0, 0x1e3c8,
2243 0x1e408, 0x1e40c,
2244 0x1e440, 0x1e444,
2245 0x1e44c, 0x1e44c,
2246 0x1e684, 0x1e690,
2247 0x1e6c0, 0x1e6c0,
2248 0x1e6e0, 0x1e6e0,
2249 0x1e700, 0x1e784,
2250 0x1e7c0, 0x1e7c8,
2251 0x1e808, 0x1e80c,
2252 0x1e840, 0x1e844,
2253 0x1e84c, 0x1e84c,
2254 0x1ea84, 0x1ea90,
2255 0x1eac0, 0x1eac0,
2256 0x1eae0, 0x1eae0,
2257 0x1eb00, 0x1eb84,
2258 0x1ebc0, 0x1ebc8,
2259 0x1ec08, 0x1ec0c,
2260 0x1ec40, 0x1ec44,
2261 0x1ec4c, 0x1ec4c,
2262 0x1ee84, 0x1ee90,
2263 0x1eec0, 0x1eec0,
2264 0x1eee0, 0x1eee0,
2265 0x1ef00, 0x1ef84,
2266 0x1efc0, 0x1efc8,
2267 0x1f008, 0x1f00c,
2268 0x1f040, 0x1f044,
2269 0x1f04c, 0x1f04c,
2270 0x1f284, 0x1f290,
2271 0x1f2c0, 0x1f2c0,
2272 0x1f2e0, 0x1f2e0,
2273 0x1f300, 0x1f384,
2274 0x1f3c0, 0x1f3c8,
2275 0x1f408, 0x1f40c,
2276 0x1f440, 0x1f444,
2277 0x1f44c, 0x1f44c,
2278 0x1f684, 0x1f690,
2279 0x1f6c0, 0x1f6c0,
2280 0x1f6e0, 0x1f6e0,
2281 0x1f700, 0x1f784,
2282 0x1f7c0, 0x1f7c8,
2283 0x1f808, 0x1f80c,
2284 0x1f840, 0x1f844,
2285 0x1f84c, 0x1f84c,
2286 0x1fa84, 0x1fa90,
2287 0x1fac0, 0x1fac0,
2288 0x1fae0, 0x1fae0,
2289 0x1fb00, 0x1fb84,
2290 0x1fbc0, 0x1fbc8,
2291 0x1fc08, 0x1fc0c,
2292 0x1fc40, 0x1fc44,
2293 0x1fc4c, 0x1fc4c,
2294 0x1fe84, 0x1fe90,
2295 0x1fec0, 0x1fec0,
2296 0x1fee0, 0x1fee0,
2297 0x1ff00, 0x1ff84,
2298 0x1ffc0, 0x1ffc8,
2299 0x30000, 0x30030,
2300 0x30100, 0x30168,
2301 0x30190, 0x301a0,
2302 0x301a8, 0x301b8,
2303 0x301c4, 0x301c8,
2304 0x301d0, 0x301d0,
2305 0x30200, 0x30320,
2306 0x30400, 0x304b4,
2307 0x304c0, 0x3052c,
2308 0x30540, 0x3061c,
2309 0x30800, 0x308a0,
2310 0x308c0, 0x30908,
2311 0x30910, 0x309b8,
2312 0x30a00, 0x30a04,
2313 0x30a0c, 0x30a14,
2314 0x30a1c, 0x30a2c,
2315 0x30a44, 0x30a50,
2316 0x30a74, 0x30a74,
2317 0x30a7c, 0x30afc,
2318 0x30b08, 0x30c24,
2319 0x30d00, 0x30d14,
2320 0x30d1c, 0x30d3c,
2321 0x30d44, 0x30d4c,
2322 0x30d54, 0x30d74,
2323 0x30d7c, 0x30d7c,
2324 0x30de0, 0x30de0,
2325 0x30e00, 0x30ed4,
2326 0x30f00, 0x30fa4,
2327 0x30fc0, 0x30fc4,
2328 0x31000, 0x31004,
2329 0x31080, 0x310fc,
2330 0x31208, 0x31220,
2331 0x3123c, 0x31254,
2332 0x31300, 0x31300,
2333 0x31308, 0x3131c,
2334 0x31338, 0x3133c,
2335 0x31380, 0x31380,
2336 0x31388, 0x313a8,
2337 0x313b4, 0x313b4,
2338 0x31400, 0x31420,
2339 0x31438, 0x3143c,
2340 0x31480, 0x31480,
2341 0x314a8, 0x314a8,
2342 0x314b0, 0x314b4,
2343 0x314c8, 0x314d4,
2344 0x31a40, 0x31a4c,
2345 0x31af0, 0x31b20,
2346 0x31b38, 0x31b3c,
2347 0x31b80, 0x31b80,
2348 0x31ba8, 0x31ba8,
2349 0x31bb0, 0x31bb4,
2350 0x31bc8, 0x31bd4,
2351 0x32140, 0x3218c,
2352 0x321f0, 0x321f4,
2353 0x32200, 0x32200,
2354 0x32218, 0x32218,
2355 0x32400, 0x32400,
2356 0x32408, 0x3241c,
2357 0x32618, 0x32620,
2358 0x32664, 0x32664,
2359 0x326a8, 0x326a8,
2360 0x326ec, 0x326ec,
2361 0x32a00, 0x32abc,
2362 0x32b00, 0x32b18,
2363 0x32b20, 0x32b38,
2364 0x32b40, 0x32b58,
2365 0x32b60, 0x32b78,
2366 0x32c00, 0x32c00,
2367 0x32c08, 0x32c3c,
2368 0x33000, 0x3302c,
2369 0x33034, 0x33050,
2370 0x33058, 0x33058,
2371 0x33060, 0x3308c,
2372 0x3309c, 0x330ac,
2373 0x330c0, 0x330c0,
2374 0x330c8, 0x330d0,
2375 0x330d8, 0x330e0,
2376 0x330ec, 0x3312c,
2377 0x33134, 0x33150,
2378 0x33158, 0x33158,
2379 0x33160, 0x3318c,
2380 0x3319c, 0x331ac,
2381 0x331c0, 0x331c0,
2382 0x331c8, 0x331d0,
2383 0x331d8, 0x331e0,
2384 0x331ec, 0x33290,
2385 0x33298, 0x332c4,
2386 0x332e4, 0x33390,
2387 0x33398, 0x333c4,
2388 0x333e4, 0x3342c,
2389 0x33434, 0x33450,
2390 0x33458, 0x33458,
2391 0x33460, 0x3348c,
2392 0x3349c, 0x334ac,
2393 0x334c0, 0x334c0,
2394 0x334c8, 0x334d0,
2395 0x334d8, 0x334e0,
2396 0x334ec, 0x3352c,
2397 0x33534, 0x33550,
2398 0x33558, 0x33558,
2399 0x33560, 0x3358c,
2400 0x3359c, 0x335ac,
2401 0x335c0, 0x335c0,
2402 0x335c8, 0x335d0,
2403 0x335d8, 0x335e0,
2404 0x335ec, 0x33690,
2405 0x33698, 0x336c4,
2406 0x336e4, 0x33790,
2407 0x33798, 0x337c4,
2408 0x337e4, 0x337fc,
2409 0x33814, 0x33814,
2410 0x33854, 0x33868,
2411 0x33880, 0x3388c,
2412 0x338c0, 0x338d0,
2413 0x338e8, 0x338ec,
2414 0x33900, 0x3392c,
2415 0x33934, 0x33950,
2416 0x33958, 0x33958,
2417 0x33960, 0x3398c,
2418 0x3399c, 0x339ac,
2419 0x339c0, 0x339c0,
2420 0x339c8, 0x339d0,
2421 0x339d8, 0x339e0,
2422 0x339ec, 0x33a90,
2423 0x33a98, 0x33ac4,
2424 0x33ae4, 0x33b10,
2425 0x33b24, 0x33b28,
2426 0x33b38, 0x33b50,
2427 0x33bf0, 0x33c10,
2428 0x33c24, 0x33c28,
2429 0x33c38, 0x33c50,
2430 0x33cf0, 0x33cfc,
2431 0x34000, 0x34030,
2432 0x34100, 0x34168,
2433 0x34190, 0x341a0,
2434 0x341a8, 0x341b8,
2435 0x341c4, 0x341c8,
2436 0x341d0, 0x341d0,
2437 0x34200, 0x34320,
2438 0x34400, 0x344b4,
2439 0x344c0, 0x3452c,
2440 0x34540, 0x3461c,
2441 0x34800, 0x348a0,
2442 0x348c0, 0x34908,
2443 0x34910, 0x349b8,
2444 0x34a00, 0x34a04,
2445 0x34a0c, 0x34a14,
2446 0x34a1c, 0x34a2c,
2447 0x34a44, 0x34a50,
2448 0x34a74, 0x34a74,
2449 0x34a7c, 0x34afc,
2450 0x34b08, 0x34c24,
2451 0x34d00, 0x34d14,
2452 0x34d1c, 0x34d3c,
2453 0x34d44, 0x34d4c,
2454 0x34d54, 0x34d74,
2455 0x34d7c, 0x34d7c,
2456 0x34de0, 0x34de0,
2457 0x34e00, 0x34ed4,
2458 0x34f00, 0x34fa4,
2459 0x34fc0, 0x34fc4,
2460 0x35000, 0x35004,
2461 0x35080, 0x350fc,
2462 0x35208, 0x35220,
2463 0x3523c, 0x35254,
2464 0x35300, 0x35300,
2465 0x35308, 0x3531c,
2466 0x35338, 0x3533c,
2467 0x35380, 0x35380,
2468 0x35388, 0x353a8,
2469 0x353b4, 0x353b4,
2470 0x35400, 0x35420,
2471 0x35438, 0x3543c,
2472 0x35480, 0x35480,
2473 0x354a8, 0x354a8,
2474 0x354b0, 0x354b4,
2475 0x354c8, 0x354d4,
2476 0x35a40, 0x35a4c,
2477 0x35af0, 0x35b20,
2478 0x35b38, 0x35b3c,
2479 0x35b80, 0x35b80,
2480 0x35ba8, 0x35ba8,
2481 0x35bb0, 0x35bb4,
2482 0x35bc8, 0x35bd4,
2483 0x36140, 0x3618c,
2484 0x361f0, 0x361f4,
2485 0x36200, 0x36200,
2486 0x36218, 0x36218,
2487 0x36400, 0x36400,
2488 0x36408, 0x3641c,
2489 0x36618, 0x36620,
2490 0x36664, 0x36664,
2491 0x366a8, 0x366a8,
2492 0x366ec, 0x366ec,
2493 0x36a00, 0x36abc,
2494 0x36b00, 0x36b18,
2495 0x36b20, 0x36b38,
2496 0x36b40, 0x36b58,
2497 0x36b60, 0x36b78,
2498 0x36c00, 0x36c00,
2499 0x36c08, 0x36c3c,
2500 0x37000, 0x3702c,
2501 0x37034, 0x37050,
2502 0x37058, 0x37058,
2503 0x37060, 0x3708c,
2504 0x3709c, 0x370ac,
2505 0x370c0, 0x370c0,
2506 0x370c8, 0x370d0,
2507 0x370d8, 0x370e0,
2508 0x370ec, 0x3712c,
2509 0x37134, 0x37150,
2510 0x37158, 0x37158,
2511 0x37160, 0x3718c,
2512 0x3719c, 0x371ac,
2513 0x371c0, 0x371c0,
2514 0x371c8, 0x371d0,
2515 0x371d8, 0x371e0,
2516 0x371ec, 0x37290,
2517 0x37298, 0x372c4,
2518 0x372e4, 0x37390,
2519 0x37398, 0x373c4,
2520 0x373e4, 0x3742c,
2521 0x37434, 0x37450,
2522 0x37458, 0x37458,
2523 0x37460, 0x3748c,
2524 0x3749c, 0x374ac,
2525 0x374c0, 0x374c0,
2526 0x374c8, 0x374d0,
2527 0x374d8, 0x374e0,
2528 0x374ec, 0x3752c,
2529 0x37534, 0x37550,
2530 0x37558, 0x37558,
2531 0x37560, 0x3758c,
2532 0x3759c, 0x375ac,
2533 0x375c0, 0x375c0,
2534 0x375c8, 0x375d0,
2535 0x375d8, 0x375e0,
2536 0x375ec, 0x37690,
2537 0x37698, 0x376c4,
2538 0x376e4, 0x37790,
2539 0x37798, 0x377c4,
2540 0x377e4, 0x377fc,
2541 0x37814, 0x37814,
2542 0x37854, 0x37868,
2543 0x37880, 0x3788c,
2544 0x378c0, 0x378d0,
2545 0x378e8, 0x378ec,
2546 0x37900, 0x3792c,
2547 0x37934, 0x37950,
2548 0x37958, 0x37958,
2549 0x37960, 0x3798c,
2550 0x3799c, 0x379ac,
2551 0x379c0, 0x379c0,
2552 0x379c8, 0x379d0,
2553 0x379d8, 0x379e0,
2554 0x379ec, 0x37a90,
2555 0x37a98, 0x37ac4,
2556 0x37ae4, 0x37b10,
2557 0x37b24, 0x37b28,
2558 0x37b38, 0x37b50,
2559 0x37bf0, 0x37c10,
2560 0x37c24, 0x37c28,
2561 0x37c38, 0x37c50,
2562 0x37cf0, 0x37cfc,
2563 0x40040, 0x40040,
2564 0x40080, 0x40084,
2565 0x40100, 0x40100,
2566 0x40140, 0x401bc,
2567 0x40200, 0x40214,
2568 0x40228, 0x40228,
2569 0x40240, 0x40258,
2570 0x40280, 0x40280,
2571 0x40304, 0x40304,
2572 0x40330, 0x4033c,
2573 0x41304, 0x413c8,
2574 0x413d0, 0x413dc,
2575 0x413f0, 0x413f0,
2576 0x41400, 0x4140c,
2577 0x41414, 0x4141c,
2578 0x41480, 0x414d0,
2579 0x44000, 0x4407c,
2580 0x440c0, 0x441ac,
2581 0x441b4, 0x4427c,
2582 0x442c0, 0x443ac,
2583 0x443b4, 0x4447c,
2584 0x444c0, 0x445ac,
2585 0x445b4, 0x4467c,
2586 0x446c0, 0x447ac,
2587 0x447b4, 0x4487c,
2588 0x448c0, 0x449ac,
2589 0x449b4, 0x44a7c,
2590 0x44ac0, 0x44bac,
2591 0x44bb4, 0x44c7c,
2592 0x44cc0, 0x44dac,
2593 0x44db4, 0x44e7c,
2594 0x44ec0, 0x44fac,
2595 0x44fb4, 0x4507c,
2596 0x450c0, 0x451ac,
2597 0x451b4, 0x451fc,
2598 0x45800, 0x45804,
2599 0x45810, 0x45830,
2600 0x45840, 0x45860,
2601 0x45868, 0x45868,
2602 0x45880, 0x45884,
2603 0x458a0, 0x458b0,
2604 0x45a00, 0x45a04,
2605 0x45a10, 0x45a30,
2606 0x45a40, 0x45a60,
2607 0x45a68, 0x45a68,
2608 0x45a80, 0x45a84,
2609 0x45aa0, 0x45ab0,
2610 0x460c0, 0x460e4,
2611 0x47000, 0x4703c,
2612 0x47044, 0x4708c,
2613 0x47200, 0x47250,
2614 0x47400, 0x47408,
2615 0x47414, 0x47420,
2616 0x47600, 0x47618,
2617 0x47800, 0x47814,
2618 0x47820, 0x4782c,
2619 0x50000, 0x50084,
2620 0x50090, 0x500cc,
2621 0x50300, 0x50384,
2622 0x50400, 0x50400,
2623 0x50800, 0x50884,
2624 0x50890, 0x508cc,
2625 0x50b00, 0x50b84,
2626 0x50c00, 0x50c00,
2627 0x51000, 0x51020,
2628 0x51028, 0x510b0,
2629 0x51300, 0x51324,
2630 };
2631
2632 static const unsigned int t6vf_reg_ranges[] = {
2633 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2634 VF_MPS_REG(A_MPS_VF_CTL),
2635 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2636 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2637 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2638 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2639 FW_T6VF_MBDATA_BASE_ADDR,
2640 FW_T6VF_MBDATA_BASE_ADDR +
2641 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2642 };
2643
2644 u32 *buf_end = (u32 *)(buf + buf_size);
2645 const unsigned int *reg_ranges;
2646 int reg_ranges_size, range;
2647 unsigned int chip_version = chip_id(adap);
2648
2649 /*
2650 * Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2652 */
2653 switch (chip_version) {
2654 case CHELSIO_T4:
2655 if (adap->flags & IS_VF) {
2656 reg_ranges = t4vf_reg_ranges;
2657 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2658 } else {
2659 reg_ranges = t4_reg_ranges;
2660 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2661 }
2662 break;
2663
2664 case CHELSIO_T5:
2665 if (adap->flags & IS_VF) {
2666 reg_ranges = t5vf_reg_ranges;
2667 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2668 } else {
2669 reg_ranges = t5_reg_ranges;
2670 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2671 }
2672 break;
2673
2674 case CHELSIO_T6:
2675 if (adap->flags & IS_VF) {
2676 reg_ranges = t6vf_reg_ranges;
2677 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2678 } else {
2679 reg_ranges = t6_reg_ranges;
2680 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2681 }
2682 break;
2683
2684 default:
2685 CH_ERR(adap,
2686 "Unsupported chip version %d\n", chip_version);
2687 return;
2688 }
2689
2690 /*
2691 * Clear the register buffer and insert the appropriate register
2692 * values selected by the above register ranges.
2693 */
2694 memset(buf, 0, buf_size);
2695 for (range = 0; range < reg_ranges_size; range += 2) {
2696 unsigned int reg = reg_ranges[range];
2697 unsigned int last_reg = reg_ranges[range + 1];
2698 u32 *bufp = (u32 *)(buf + reg);
2699
2700 /*
2701 * Iterate across the register range filling in the register
2702 * buffer but don't write past the end of the register buffer.
2703 */
2704 while (reg <= last_reg && bufp < buf_end) {
2705 *bufp++ = t4_read_reg(adap, reg);
2706 reg += sizeof(u32);
2707 }
2708 }
2709}
2710
2711/*
2712 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID
2713 * header followed by one or more VPD-R sections, each with its own header.
2714 */
2715struct t4_vpd_hdr {
2716 u8 id_tag;
2717 u8 id_len[2];
2718 u8 id_data[ID_LEN];
2719};
2720
2721struct t4_vpdr_hdr {
2722 u8 vpdr_tag;
2723 u8 vpdr_len[2];
2724};
2725
2726/*
2727 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2728 */
2729#define EEPROM_DELAY 10 /* 10us per poll spin */
2730#define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
2731
2732#define EEPROM_STAT_ADDR 0x7bfc
2733#define VPD_SIZE 0x800
2734#define VPD_BASE 0x400
2735#define VPD_BASE_OLD 0
2736#define VPD_LEN 1024
2737#define VPD_INFO_FLD_HDR_SIZE 3
2738#define CHELSIO_VPD_UNIQUE_ID 0x82
2739
2740/*
2741 * Small utility function to wait till any outstanding VPD Access is complete.
2742 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2743 * VPD Access in flight. This allows us to handle the problem of having a
2744 * previous VPD Access time out and prevent an attempt to inject a new VPD
2745 * Request before any in-flight VPD reguest has completed.
2746 */
2747static int t4_seeprom_wait(struct adapter *adapter)
2748{
2749 unsigned int base = adapter->params.pci.vpd_cap_addr;
2750 int max_poll;
2751
2752 /*
2753 * If no VPD Access is in flight, we can just return success right
2754 * away.
2755 */
2756 if (!adapter->vpd_busy)
2757 return 0;
2758
2759 /*
2760 * Poll the VPD Capability Address/Flag register waiting for it
2761 * to indicate that the operation is complete.
2762 */
2763 max_poll = EEPROM_MAX_POLL;
2764 do {
2765 u16 val;
2766
2767 udelay(EEPROM_DELAY);
2768 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2769
2770 /*
2771 * If the operation is complete, mark the VPD as no longer
2772 * busy and return success.
2773 */
2774 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2775 adapter->vpd_busy = 0;
2776 return 0;
2777 }
2778 } while (--max_poll);
2779
2780 /*
2781 * Failure! Note that we leave the VPD Busy status set in order to
2782 * avoid pushing a new VPD Access request into the VPD Capability till
2783 * the current operation eventually succeeds. It's a bug to issue a
2784 * new request when an existing request is in flight and will result
2785 * in corrupt hardware state.
2786 */
2787 return -ETIMEDOUT;
2788}
2789
2800int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2801{
2802 unsigned int base = adapter->params.pci.vpd_cap_addr;
2803 int ret;
2804
2805 /*
2806 * VPD Accesses must alway be 4-byte aligned!
2807 */
2808 if (addr >= EEPROMVSIZE || (addr & 3))
2809 return -EINVAL;
2810
2811 /*
2812 * Wait for any previous operation which may still be in flight to
2813 * complete.
2814 */
2815 ret = t4_seeprom_wait(adapter);
2816 if (ret) {
2817 CH_ERR(adapter, "VPD still busy from previous operation\n");
2818 return ret;
2819 }
2820
2821 /*
2822 * Issue our new VPD Read request, mark the VPD as being busy and wait
2823 * for our request to complete. If it doesn't complete, note the
2824 * error and return it to our caller. Note that we do not reset the
2825 * VPD Busy status!
2826 */
2827 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2828 adapter->vpd_busy = 1;
2829 adapter->vpd_flag = PCI_VPD_ADDR_F;
2830 ret = t4_seeprom_wait(adapter);
2831 if (ret) {
2832 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2833 return ret;
2834 }
2835
2836 /*
2837 * Grab the returned data, swizzle it into our endianness and
2838 * return success.
2839 */
2840 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2841 *data = le32_to_cpu(*data);
2842 return 0;
2843}
2844
2855int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2856{
2857 unsigned int base = adapter->params.pci.vpd_cap_addr;
2858 int ret;
2859 u32 stats_reg;
2860 int max_poll;
2861
2862 /*
2863 * VPD Accesses must alway be 4-byte aligned!
2864 */
2865 if (addr >= EEPROMVSIZE || (addr & 3))
2866 return -EINVAL;
2867
2868 /*
2869 * Wait for any previous operation which may still be in flight to
2870 * complete.
2871 */
2872 ret = t4_seeprom_wait(adapter);
2873 if (ret) {
2874 CH_ERR(adapter, "VPD still busy from previous operation\n");
2875 return ret;
2876 }
2877
2878 /*
2879 * Issue our new VPD Read request, mark the VPD as being busy and wait
2880 * for our request to complete. If it doesn't complete, note the
2881 * error and return it to our caller. Note that we do not reset the
2882 * VPD Busy status!
2883 */
2884 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2885 cpu_to_le32(data));
2886 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2887 (u16)addr | PCI_VPD_ADDR_F);
2888 adapter->vpd_busy = 1;
2889 adapter->vpd_flag = 0;
2890 ret = t4_seeprom_wait(adapter);
2891 if (ret) {
2892 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2893 return ret;
2894 }
2895
2896 /*
2897 * Reset PCI_VPD_DATA register after a transaction and wait for our
2898 * request to complete. If it doesn't complete, return error.
2899 */
2900 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2901 max_poll = EEPROM_MAX_POLL;
2902 do {
2903 udelay(EEPROM_DELAY);
2904 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2905 } while ((stats_reg & 0x1) && --max_poll);
2906 if (!max_poll)
2907 return -ETIMEDOUT;
2908
2909 /* Return success! */
2910 return 0;
2911}
2912
2930int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2931{
2932 fn *= sz;
2933 if (phys_addr < 1024)
2934 return phys_addr + (31 << 10);
2935 if (phys_addr < 1024 + fn)
2936 return EEPROMSIZE - fn + phys_addr - 1024;
2937 if (phys_addr < EEPROMSIZE)
2938 return phys_addr - 1024 - fn;
2939 return -EINVAL;
2940}
2941
2949int t4_seeprom_wp(struct adapter *adapter, int enable)
2950{
2951 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2952}
2953
2963static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
2964{
2965 int i, tag;
2966 unsigned int offset, len;
2967 const struct t4_vpdr_hdr *vpdr;
2968
2969 offset = sizeof(struct t4_vpd_hdr);
2970 vpdr = (const void *)(vpd + offset);
2971 tag = vpdr->vpdr_tag;
2972 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2973 while (region--) {
2974 offset += sizeof(struct t4_vpdr_hdr) + len;
2975 vpdr = (const void *)(vpd + offset);
2976 if (++tag != vpdr->vpdr_tag)
2977 return -ENOENT;
2978 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2979 }
2980 offset += sizeof(struct t4_vpdr_hdr);
2981
2982 if (offset + len > VPD_LEN) {
2983 return -ENOENT;
2984 }
2985
2986 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2987 if (memcmp(vpd + i , kw , 2) == 0){
2988 i += VPD_INFO_FLD_HDR_SIZE;
2989 return i;
2990 }
2991
2992 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
2993 }
2994
2995 return -ENOENT;
2996}
2997
2998
3007static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3008 uint16_t device_id, u32 *buf)
3009{
3010 int i, ret, addr;
3011 int ec, sn, pn, na, md;
3012 u8 csum;
3013 const u8 *vpd = (const u8 *)buf;
3014
3015 /*
3016 * Card information normally starts at VPD_BASE but early cards had
3017 * it at 0.
3018 */
3019 ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3020 if (ret)
3021 return (ret);
3022
3023 /*
3024 * The VPD shall have a unique identifier specified by the PCI SIG.
3025 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3026 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3027 * is expected to automatically put this entry at the
3028 * beginning of the VPD.
3029 */
3030 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3031
3032 for (i = 0; i < VPD_LEN; i += 4) {
3033 ret = t4_seeprom_read(adapter, addr + i, buf++);
3034 if (ret)
3035 return ret;
3036 }
3037
3038#define FIND_VPD_KW(var,name) do { \
3039 var = get_vpd_keyword_val(vpd, name, 0); \
3040 if (var < 0) { \
3041 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3042 return -EINVAL; \
3043 } \
3044} while (0)
3045
3046 FIND_VPD_KW(i, "RV");
3047 for (csum = 0; i >= 0; i--)
3048 csum += vpd[i];
3049
3050 if (csum) {
3051 CH_ERR(adapter,
3052 "corrupted VPD EEPROM, actual csum %u\n", csum);
3053 return -EINVAL;
3054 }
3055
3056 FIND_VPD_KW(ec, "EC");
3057 FIND_VPD_KW(sn, "SN");
3058 FIND_VPD_KW(pn, "PN");
3059 FIND_VPD_KW(na, "NA");
3060#undef FIND_VPD_KW
3061
3062 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3063 strstrip(p->id);
3064 memcpy(p->ec, vpd + ec, EC_LEN);
3065 strstrip(p->ec);
3066 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3067 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3068 strstrip(p->sn);
3069 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3070 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3071 strstrip((char *)p->pn);
3072 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3073 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3074 strstrip((char *)p->na);
3075
3076 if (device_id & 0x80)
3077 return 0; /* Custom card */
3078
3079 md = get_vpd_keyword_val(vpd, "VF", 1);
3080 if (md < 0) {
3081 snprintf(p->md, sizeof(p->md), "unknown");
3082 } else {
3083 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3084 memcpy(p->md, vpd + md, min(i, MD_LEN));
3085 strstrip((char *)p->md);
3086 }
3087
3088 return 0;
3089}
3090
3091/* serial flash and firmware constants and flash config file constants */
3092enum {
3093 SF_ATTEMPTS = 10, /* max retries for SF operations */
3094
3095 /* flash command opcodes */
3096 SF_PROG_PAGE = 2, /* program 256B page */
3097 SF_WR_DISABLE = 4, /* disable writes */
3098 SF_RD_STATUS = 5, /* read status register */
3099 SF_WR_ENABLE = 6, /* enable writes */
3100 SF_RD_DATA_FAST = 0xb, /* read flash */
3101 SF_RD_ID = 0x9f, /* read ID */
3102 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */
3103};
3104
3117static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3118 int lock, u32 *valp)
3119{
3120 int ret;
3121
3122 if (!byte_cnt || byte_cnt > 4)
3123 return -EINVAL;
3124 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3125 return -EBUSY;
3126 t4_write_reg(adapter, A_SF_OP,
3127 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3128 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3129 if (!ret)
3130 *valp = t4_read_reg(adapter, A_SF_DATA);
3131 return ret;
3132}
3133
3146static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3147 int lock, u32 val)
3148{
3149 if (!byte_cnt || byte_cnt > 4)
3150 return -EINVAL;
3151 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3152 return -EBUSY;
3153 t4_write_reg(adapter, A_SF_DATA, val);
3154 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3155 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3156 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3157}
3158
3167static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3168{
3169 int ret;
3170 u32 status;
3171
3172 while (1) {
3173 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3174 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3175 return ret;
3176 if (!(status & 1))
3177 return 0;
3178 if (--attempts == 0)
3179 return -EAGAIN;
3180 if (delay)
3181 msleep(delay);
3182 }
3183}
3184
3198int t4_read_flash(struct adapter *adapter, unsigned int addr,
3199 unsigned int nwords, u32 *data, int byte_oriented)
3200{
3201 int ret;
3202
3203 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3204 return -EINVAL;
3205
3206 addr = swab32(addr) | SF_RD_DATA_FAST;
3207
3208 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3209 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3210 return ret;
3211
3212 for ( ; nwords; nwords--, data++) {
3213 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3214 if (nwords == 1)
3215 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3216 if (ret)
3217 return ret;
3218 if (byte_oriented)
3219 *data = (__force __u32)(cpu_to_be32(*data));
3220 }
3221 return 0;
3222}
3223
3237int t4_write_flash(struct adapter *adapter, unsigned int addr,
3238 unsigned int n, const u8 *data, int byte_oriented)
3239{
3240 int ret;
3241 u32 buf[SF_PAGE_SIZE / 4];
3242 unsigned int i, c, left, val, offset = addr & 0xff;
3243
3244 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3245 return -EINVAL;
3246
3247 val = swab32(addr) | SF_PROG_PAGE;
3248
3249 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3250 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3251 goto unlock;
3252
3253 for (left = n; left; left -= c) {
3254 c = min(left, 4U);
3255 for (val = 0, i = 0; i < c; ++i)
3256 val = (val << 8) + *data++;
3257
3258 if (!byte_oriented)
3259 val = cpu_to_be32(val);
3260
3261 ret = sf1_write(adapter, c, c != left, 1, val);
3262 if (ret)
3263 goto unlock;
3264 }
3265 ret = flash_wait_op(adapter, 8, 1);
3266 if (ret)
3267 goto unlock;
3268
3269 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3270
3271 /* Read the page to verify the write succeeded */
3272 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3273 byte_oriented);
3274 if (ret)
3275 return ret;
3276
3277 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3278 CH_ERR(adapter,
3279 "failed to correctly write the flash page at %#x\n",
3280 addr);
3281 return -EIO;
3282 }
3283 return 0;
3284
3285unlock:
3286 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3287 return ret;
3288}
3289
3297int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3298{
3299 return t4_read_flash(adapter, FLASH_FW_START +
3300 offsetof(struct fw_hdr, fw_ver), 1,
3301 vers, 0);
3302}
3303
3311int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
3312{
3313 return t4_read_flash(adapter, FLASH_FW_START,
3314 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
3315}
3316
3324int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3325{
3326 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3327 offsetof(struct fw_hdr, fw_ver), 1,
3328 vers, 0);
3329}
3330
3338int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3339{
3340 return t4_read_flash(adapter, FLASH_FW_START +
3341 offsetof(struct fw_hdr, tp_microcode_ver),
3342 1, vers, 0);
3343}
3344
3355int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
3356{
3357 struct exprom_header {
3358 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3359 unsigned char hdr_ver[4]; /* Expansion ROM version */
3360 } *hdr;
3361 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3362 sizeof(u32))];
3363 int ret;
3364
3365 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
3366 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3367 0);
3368 if (ret)
3369 return ret;
3370
3371 hdr = (struct exprom_header *)exprom_header_buf;
3372 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3373 return -ENOENT;
3374
3375 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3376 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3377 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3378 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3379 return 0;
3380}
3381
3405int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3406{
3407 u32 scfgrev_param;
3408 int ret;
3409
3410 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3412 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3413 1, &scfgrev_param, vers);
3414 if (ret)
3415 *vers = 0;
3416 return ret;
3417}
3418
3440int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3441{
3442 u32 vpdrev_param;
3443 int ret;
3444
3445 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3446 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3447 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3448 1, &vpdrev_param, vers);
3449 if (ret)
3450 *vers = 0;
3451 return ret;
3452}
3453
3463int t4_get_version_info(struct adapter *adapter)
3464{
3465 int ret = 0;
3466
3467 #define FIRST_RET(__getvinfo) \
3468 do { \
3469 int __ret = __getvinfo; \
3470 if (__ret && !ret) \
3471 ret = __ret; \
3472 } while (0)
3473
3474 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3475 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3476 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3477 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3478 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3479 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3480
3481 #undef FIRST_RET
3482
3483 return ret;
3484}
3485
3494int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3495{
3496 int ret = 0;
3497
3498 if (end >= adapter->params.sf_nsec)
3499 return -EINVAL;
3500
3501 while (start <= end) {
3502 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3503 (ret = sf1_write(adapter, 4, 0, 1,
3504 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3505 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3506 CH_ERR(adapter,
3507 "erase of flash sector %d failed, error %d\n",
3508 start, ret);
3509 break;
3510 }
3511 start++;
3512 }
3513 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3514 return ret;
3515}
3516
3525int t4_flash_cfg_addr(struct adapter *adapter)
3526{
3527 /*
3528 * If the device FLASH isn't large enough to hold a Firmware
3529 * Configuration File, return an error.
3530 */
3531 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3532 return -ENOSPC;
3533
3534 return FLASH_CFG_START;
3535}
3536
3537/*
3538 * Return TRUE if the specified firmware matches the adapter. I.e. T4
3539 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3540 * and emit an error message for mismatched firmware to save our caller the
3541 * effort ...
3542 */
3543static int t4_fw_matches_chip(struct adapter *adap,
3544 const struct fw_hdr *hdr)
3545{
3546 /*
3547 * The expression below will return FALSE for any unsupported adapter
3548 * which will keep us "honest" in the future ...
3549 */
3550 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3551 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3552 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3553 return 1;
3554
3555 CH_ERR(adap,
3556 "FW image (%d) is not suitable for this adapter (%d)\n",
3557 hdr->chip, chip_id(adap));
3558 return 0;
3559}
3560
3569int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3570{
3571 u32 csum;
3572 int ret, addr;
3573 unsigned int i;
3574 u8 first_page[SF_PAGE_SIZE];
3575 const u32 *p = (const u32 *)fw_data;
3576 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3578 unsigned int fw_start_sec;
3579 unsigned int fw_start;
3580 unsigned int fw_size;
3581
3582 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3583 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3584 fw_start = FLASH_FWBOOTSTRAP_START;
3585 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3586 } else {
3587 fw_start_sec = FLASH_FW_START_SEC;
3588 fw_start = FLASH_FW_START;
3589 fw_size = FLASH_FW_MAX_SIZE;
3590 }
3591
3592 if (!size) {
3593 CH_ERR(adap, "FW image has no data\n");
3594 return -EINVAL;
3595 }
3596 if (size & 511) {
3597 CH_ERR(adap,
3598 "FW image size not multiple of 512 bytes\n");
3599 return -EINVAL;
3600 }
3601 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3602 CH_ERR(adap,
3603 "FW image size differs from size in FW header\n");
3604 return -EINVAL;
3605 }
3606 if (size > fw_size) {
3607 CH_ERR(adap, "FW image too large, max is %u bytes\n",
3608 fw_size);
3609 return -EFBIG;
3610 }
3611 if (!t4_fw_matches_chip(adap, hdr))
3612 return -EINVAL;
3613
3614 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3615 csum += be32_to_cpu(p[i]);
3616
3617 if (csum != 0xffffffff) {
3618 CH_ERR(adap,
3619 "corrupted firmware image, checksum %#x\n", csum);
3620 return -EINVAL;
3621 }
3622
3623 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3624 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3625 if (ret)
3626 goto out;
3627
3628 /*
3629 * We write the correct version at the end so the driver can see a bad
3630 * version if the FW write fails. Start by writing a copy of the
3631 * first page with a bad version.
3632 */
3633 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3634 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3635 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3636 if (ret)
3637 goto out;
3638
3639 addr = fw_start;
3640 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3641 addr += SF_PAGE_SIZE;
3642 fw_data += SF_PAGE_SIZE;
3643 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3644 if (ret)
3645 goto out;
3646 }
3647
3648 ret = t4_write_flash(adap,
3649 fw_start + offsetof(struct fw_hdr, fw_ver),
3650 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3651out:
3652 if (ret)
3653 CH_ERR(adap, "firmware download failed, error %d\n",
3654 ret);
3655 return ret;
3656}
3657
3663int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3664{
3665 struct fw_params_cmd c;
3666
3667 memset(&c, 0, sizeof(c));
3668 c.op_to_vfn =
3669 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3670 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3671 V_FW_PARAMS_CMD_PFN(adap->pf) |
3672 V_FW_PARAMS_CMD_VFN(0));
3673 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3674 c.param[0].mnem =
3675 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3677 c.param[0].val = (__force __be32)op;
3678
3679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3680}
3681
3682void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3683 unsigned int *pif_req_wrptr,
3684 unsigned int *pif_rsp_wrptr)
3685{
3686 int i, j;
3687 u32 cfg, val, req, rsp;
3688
3689 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3690 if (cfg & F_LADBGEN)
3691 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3692
3693 val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3694 req = G_POLADBGWRPTR(val);
3695 rsp = G_PILADBGWRPTR(val);
3696 if (pif_req_wrptr)
3697 *pif_req_wrptr = req;
3698 if (pif_rsp_wrptr)
3699 *pif_rsp_wrptr = rsp;
3700
3701 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3702 for (j = 0; j < 6; j++) {
3703 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3704 V_PILADBGRDPTR(rsp));
3705 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3706 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3707 req++;
3708 rsp++;
3709 }
3710 req = (req + 2) & M_POLADBGRDPTR;
3711 rsp = (rsp + 2) & M_PILADBGRDPTR;
3712 }
3713 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3714}
3715
3716void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3717{
3718 u32 cfg;
3719 int i, j, idx;
3720
3721 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3722 if (cfg & F_LADBGEN)
3723 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3724
3725 for (i = 0; i < CIM_MALA_SIZE; i++) {
3726 for (j = 0; j < 5; j++) {
3727 idx = 8 * i + j;
3728 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3729 V_PILADBGRDPTR(idx));
3730 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3731 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3732 }
3733 }
3734 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3735}
3736
3737void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3738{
3739 unsigned int i, j;
3740
3741 for (i = 0; i < 8; i++) {
3742 u32 *p = la_buf + i;
3743
3744 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3745 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3746 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3748 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3749 }
3750}
3751
3758static uint32_t fwcaps16_to_caps32(uint16_t caps16)
3759{
3760 uint32_t caps32 = 0;
3761
3762 #define CAP16_TO_CAP32(__cap) \
3763 do { \
3764 if (caps16 & FW_PORT_CAP_##__cap) \
3765 caps32 |= FW_PORT_CAP32_##__cap; \
3766 } while (0)
3767
3768 CAP16_TO_CAP32(SPEED_100M);
3769 CAP16_TO_CAP32(SPEED_1G);
3770 CAP16_TO_CAP32(SPEED_25G);
3771 CAP16_TO_CAP32(SPEED_10G);
3772 CAP16_TO_CAP32(SPEED_40G);
3773 CAP16_TO_CAP32(SPEED_100G);
3774 CAP16_TO_CAP32(FC_RX);
3775 CAP16_TO_CAP32(FC_TX);
3776 CAP16_TO_CAP32(ANEG);
3777 CAP16_TO_CAP32(FORCE_PAUSE);
3778 CAP16_TO_CAP32(MDIAUTO);
3779 CAP16_TO_CAP32(MDISTRAIGHT);
3780 CAP16_TO_CAP32(FEC_RS);
3781 CAP16_TO_CAP32(FEC_BASER_RS);
3782 CAP16_TO_CAP32(802_3_PAUSE);
3783 CAP16_TO_CAP32(802_3_ASM_DIR);
3784
3785 #undef CAP16_TO_CAP32
3786
3787 return caps32;
3788}
3789
3798static uint16_t fwcaps32_to_caps16(uint32_t caps32)
3799{
3800 uint16_t caps16 = 0;
3801
3802 #define CAP32_TO_CAP16(__cap) \
3803 do { \
3804 if (caps32 & FW_PORT_CAP32_##__cap) \
3805 caps16 |= FW_PORT_CAP_##__cap; \
3806 } while (0)
3807
3808 CAP32_TO_CAP16(SPEED_100M);
3809 CAP32_TO_CAP16(SPEED_1G);
3810 CAP32_TO_CAP16(SPEED_10G);
3811 CAP32_TO_CAP16(SPEED_25G);
3812 CAP32_TO_CAP16(SPEED_40G);
3813 CAP32_TO_CAP16(SPEED_100G);
3814 CAP32_TO_CAP16(FC_RX);
3815 CAP32_TO_CAP16(FC_TX);
3816 CAP32_TO_CAP16(802_3_PAUSE);
3817 CAP32_TO_CAP16(802_3_ASM_DIR);
3818 CAP32_TO_CAP16(ANEG);
3819 CAP32_TO_CAP16(FORCE_PAUSE);
3820 CAP32_TO_CAP16(MDIAUTO);
3821 CAP32_TO_CAP16(MDISTRAIGHT);
3822 CAP32_TO_CAP16(FEC_RS);
3823 CAP32_TO_CAP16(FEC_BASER_RS);
3824
3825 #undef CAP32_TO_CAP16
3826
3827 return caps16;
3828}
3829
3830static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none)
3831{
3832 int8_t fec = 0;
3833
3834 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0)
3835 return (unset_means_none ? FEC_NONE : 0);
3836
3837 if (caps & FW_PORT_CAP32_FEC_RS)
3838 fec |= FEC_RS;
3839 if (caps & FW_PORT_CAP32_FEC_BASER_RS)
3840 fec |= FEC_BASER_RS;
3841 if (caps & FW_PORT_CAP32_FEC_NO_FEC)
3842 fec |= FEC_NONE;
3843
3844 return (fec);
3845}
3846
3847/*
3848 * Note that 0 is not translated to NO_FEC.
3849 */
3850static uint32_t fec_to_fwcap(int8_t fec)
3851{
3852 uint32_t caps = 0;
3853
3854 /* Only real FECs allowed. */
3855 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0);
3856
3857 if (fec & FEC_RS)
3858 caps |= FW_PORT_CAP32_FEC_RS;
3859 if (fec & FEC_BASER_RS)
3860 caps |= FW_PORT_CAP32_FEC_BASER_RS;
3861 if (fec & FEC_NONE)
3862 caps |= FW_PORT_CAP32_FEC_NO_FEC;
3863
3864 return (caps);
3865}
3866
3880int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3881 struct link_config *lc)
3882{
3883 struct fw_port_cmd c;
3884 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
3885 unsigned int aneg, fc, fec, speed, rcap;
3886
3887 fc = 0;
3888 if (lc->requested_fc & PAUSE_RX)
3889 fc |= FW_PORT_CAP32_FC_RX;
3890 if (lc->requested_fc & PAUSE_TX)
3891 fc |= FW_PORT_CAP32_FC_TX;
3892 if (!(lc->requested_fc & PAUSE_AUTONEG))
3893 fc |= FW_PORT_CAP32_FORCE_PAUSE;
3894
3895 if (lc->requested_aneg == AUTONEG_DISABLE)
3896 aneg = 0;
3897 else if (lc->requested_aneg == AUTONEG_ENABLE)
3898 aneg = FW_PORT_CAP32_ANEG;
3899 else
3900 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3901
3902 if (aneg) {
3903 speed = lc->pcaps &
3904 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
3905 } else if (lc->requested_speed != 0)
3906 speed = speed_to_fwcap(lc->requested_speed);
3907 else
3908 speed = fwcap_top_speed(lc->pcaps);
3909
3910 fec = 0;
3911#ifdef INVARIANTS
3912 if (lc->force_fec != 0)
3913 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_FEC);
3914#endif
3915 if (fec_supported(speed)) {
3916 if (lc->requested_fec == FEC_AUTO) {
3917 if (lc->force_fec > 0) {
3918 /*
3919 * Must use FORCE_FEC even though requested FEC
3920 * is AUTO. Set all the FEC bits valid for the
3921 * speed and let the firmware pick one.
3922 */
3923 fec |= FW_PORT_CAP32_FORCE_FEC;
3924 if (speed & FW_PORT_CAP32_SPEED_100G) {
3925 fec |= FW_PORT_CAP32_FEC_RS;
3926 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3927 } else if (speed & FW_PORT_CAP32_SPEED_50G) {
3928 fec |= FW_PORT_CAP32_FEC_BASER_RS;
3929 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3930 } else {
3931 fec |= FW_PORT_CAP32_FEC_RS;
3932 fec |= FW_PORT_CAP32_FEC_BASER_RS;
3933 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3934 }
3935 } else {
3936 /*
3937 * Set only 1b. Old firmwares can't deal with
3938 * multiple bits and new firmwares are free to
3939 * ignore this and try whatever FECs they want
3940 * because we aren't setting FORCE_FEC here.
3941 */
3942 fec |= fec_to_fwcap(lc->fec_hint);
3943 MPASS(powerof2(fec));
3944
3945 /*
3946 * Override the hint if the FEC is not valid for
3947 * the potential top speed. Request the best
3948 * FEC at that speed instead.
3949 */
3950 if (speed & FW_PORT_CAP32_SPEED_100G) {
3951 if (fec == FW_PORT_CAP32_FEC_BASER_RS)
3952 fec = FW_PORT_CAP32_FEC_RS;
3953 } else if (speed & FW_PORT_CAP32_SPEED_50G) {
3954 if (fec == FW_PORT_CAP32_FEC_RS)
3955 fec = FW_PORT_CAP32_FEC_BASER_RS;
3956 }
3957 }
3958 } else {
3959 /*
3960 * User has explicitly requested some FEC(s). Set
3961 * FORCE_FEC unless prohibited from using it.
3962 */
3963 if (lc->force_fec != 0)
3964 fec |= FW_PORT_CAP32_FORCE_FEC;
3965 fec |= fec_to_fwcap(lc->requested_fec &
3966 M_FW_PORT_CAP32_FEC);
3967 if (lc->requested_fec & FEC_MODULE)
3968 fec |= fec_to_fwcap(lc->fec_hint);
3969 }
3970
3971 /*
3972 * This is for compatibility with old firmwares. The original
3973 * way to request NO_FEC was to not set any of the FEC bits. New
3974 * firmwares understand this too.
3975 */
3976 if (fec == FW_PORT_CAP32_FEC_NO_FEC)
3977 fec = 0;
3978 }
3979
3980 /* Force AN on for BT cards. */
3981 if (isset(&adap->bt_map, port))
3982 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3983
3984 rcap = aneg | speed | fc | fec;
3985 if ((rcap | lc->pcaps) != lc->pcaps) {
3986#ifdef INVARIANTS
3987 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap,
3988 lc->pcaps, rcap & (rcap ^ lc->pcaps));
3989#endif
3990 rcap &= lc->pcaps;
3991 }
3992 rcap |= mdi;
3993
3994 memset(&c, 0, sizeof(c));
3995 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3996 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3997 V_FW_PORT_CMD_PORTID(port));
3998 if (adap->params.port_caps32) {
3999 c.action_to_len16 =
4000 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
4001 FW_LEN16(c));
4002 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4003 } else {
4004 c.action_to_len16 =
4005 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4006 FW_LEN16(c));
4007 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4008 }
4009
4010 lc->requested_caps = rcap;
4011 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4012}
4013
4022int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4023{
4024 struct fw_port_cmd c;
4025
4026 memset(&c, 0, sizeof(c));
4027 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4028 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4029 V_FW_PORT_CMD_PORTID(port));
4030 c.action_to_len16 =
4031 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4032 FW_LEN16(c));
4033 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4034 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4035}
4036
4037struct intr_details {
4038 u32 mask;
4039 const char *msg;
4040};
4041
4042struct intr_action {
4043 u32 mask;
4044 int arg;
4045 bool (*action)(struct adapter *, int, bool);
4046};
4047
4048#define NONFATAL_IF_DISABLED 1
4049struct intr_info {
4050 const char *name; /* name of the INT_CAUSE register */
4051 int cause_reg; /* INT_CAUSE register */
4052 int enable_reg; /* INT_ENABLE register */
4053 u32 fatal; /* bits that are fatal */
4054 int flags; /* hints */
4055 const struct intr_details *details;
4056 const struct intr_action *actions;
4057};
4058
4059static inline char
4060intr_alert_char(u32 cause, u32 enable, u32 fatal)
4061{
4062
4063 if (cause & fatal)
4064 return ('!');
4065 if (cause & enable)
4066 return ('*');
4067 return ('-');
4068}
4069
4070static void
4071t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
4072{
4073 u32 enable, fatal, leftover;
4074 const struct intr_details *details;
4075 char alert;
4076
4077 enable = t4_read_reg(adap, ii->enable_reg);
4078 if (ii->flags & NONFATAL_IF_DISABLED)
4079 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
4080 else
4081 fatal = ii->fatal;
4082 alert = intr_alert_char(cause, enable, fatal);
4083 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
4084 alert, ii->name, ii->cause_reg, cause, enable, fatal);
4085
4086 leftover = cause;
4087 for (details = ii->details; details && details->mask != 0; details++) {
4088 u32 msgbits = details->mask & cause;
4089 if (msgbits == 0)
4090 continue;
4091 alert = intr_alert_char(msgbits, enable, ii->fatal);
4092 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits,
4093 details->msg);
4094 leftover &= ~msgbits;
4095 }
4096 if (leftover != 0 && leftover != cause)
4097 CH_ALERT(adap, " ? [0x%08x]\n", leftover);
4098}
4099
4100/*
4101 * Returns true for fatal error.
4102 */
4103static bool
4104t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
4105 u32 additional_cause, bool verbose)
4106{
4107 u32 cause, fatal;
4108 bool rc;
4109 const struct intr_action *action;
4110
4111 /*
4112 * Read and display cause. Note that the top level PL_INT_CAUSE is a
4113 * bit special and we need to completely ignore the bits that are not in
4114 * PL_INT_ENABLE.
4115 */
4116 cause = t4_read_reg(adap, ii->cause_reg);
4117 if (ii->cause_reg == A_PL_INT_CAUSE)
4118 cause &= t4_read_reg(adap, ii->enable_reg);
4119 if (verbose || cause != 0)
4120 t4_show_intr_info(adap, ii, cause);
4121 fatal = cause & ii->fatal;
4122 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
4123 fatal &= t4_read_reg(adap, ii->enable_reg);
4124 cause |= additional_cause;
4125 if (cause == 0)
4126 return (false);
4127
4128 rc = fatal != 0;
4129 for (action = ii->actions; action && action->mask != 0; action++) {
4130 if (!(action->mask & cause))
4131 continue;
4132 rc |= (action->action)(adap, action->arg, verbose);
4133 }
4134
4135 /* clear */
4136 t4_write_reg(adap, ii->cause_reg, cause);
4137 (void)t4_read_reg(adap, ii->cause_reg);
4138
4139 return (rc);
4140}
4141
4142/*
4143 * Interrupt handler for the PCIE module.
4144 */
4145static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
4146{
4147 static const struct intr_details sysbus_intr_details[] = {
4148 { F_RNPP, "RXNP array parity error" },
4149 { F_RPCP, "RXPC array parity error" },
4150 { F_RCIP, "RXCIF array parity error" },
4151 { F_RCCP, "Rx completions control array parity error" },
4152 { F_RFTP, "RXFT array parity error" },
4153 { 0 }
4154 };
4155 static const struct intr_info sysbus_intr_info = {
4156 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4157 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4158 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4159 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4160 .flags = 0,
4161 .details = sysbus_intr_details,
4162 .actions = NULL,
4163 };
4164 static const struct intr_details pcie_port_intr_details[] = {
4165 { F_TPCP, "TXPC array parity error" },
4166 { F_TNPP, "TXNP array parity error" },
4167 { F_TFTP, "TXFT array parity error" },
4168 { F_TCAP, "TXCA array parity error" },
4169 { F_TCIP, "TXCIF array parity error" },
4170 { F_RCAP, "RXCA array parity error" },
4171 { F_OTDD, "outbound request TLP discarded" },
4172 { F_RDPE, "Rx data parity error" },
4173 { F_TDUE, "Tx uncorrectable data error" },
4174 { 0 }
4175 };
4176 static const struct intr_info pcie_port_intr_info = {
4177 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4178 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4179 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4180 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4181 F_OTDD | F_RDPE | F_TDUE,
4182 .flags = 0,
4183 .details = pcie_port_intr_details,
4184 .actions = NULL,
4185 };
4186 static const struct intr_details pcie_intr_details[] = {
4187 { F_MSIADDRLPERR, "MSI AddrL parity error" },
4188 { F_MSIADDRHPERR, "MSI AddrH parity error" },
4189 { F_MSIDATAPERR, "MSI data parity error" },
4190 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4191 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4192 { F_MSIXDATAPERR, "MSI-X data parity error" },
4193 { F_MSIXDIPERR, "MSI-X DI parity error" },
4194 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4195 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4196 { F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4197 { F_CCNTPERR, "PCIe CMD channel count parity error" },
4198 { F_CREQPERR, "PCIe CMD channel request parity error" },
4199 { F_CRSPPERR, "PCIe CMD channel response parity error" },
4200 { F_DCNTPERR, "PCIe DMA channel count parity error" },
4201 { F_DREQPERR, "PCIe DMA channel request parity error" },
4202 { F_DRSPPERR, "PCIe DMA channel response parity error" },
4203 { F_HCNTPERR, "PCIe HMA channel count parity error" },
4204 { F_HREQPERR, "PCIe HMA channel request parity error" },
4205 { F_HRSPPERR, "PCIe HMA channel response parity error" },
4206 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4207 { F_FIDPERR, "PCIe FID parity error" },
4208 { F_INTXCLRPERR, "PCIe INTx clear parity error" },
4209 { F_MATAGPERR, "PCIe MA tag parity error" },
4210 { F_PIOTAGPERR, "PCIe PIO tag parity error" },
4211 { F_RXCPLPERR, "PCIe Rx completion parity error" },
4212 { F_RXWRPERR, "PCIe Rx write parity error" },
4213 { F_RPLPERR, "PCIe replay buffer parity error" },
4214 { F_PCIESINT, "PCIe core secondary fault" },
4215 { F_PCIEPINT, "PCIe core primary fault" },
4216 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4217 { 0 }
4218 };
4219 static const struct intr_details t5_pcie_intr_details[] = {
4220 { F_IPGRPPERR, "Parity errors observed by IP" },
4221 { F_NONFATALERR, "PCIe non-fatal error" },
4222 { F_READRSPERR, "Outbound read error" },
4223 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4224 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4225 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4226 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4227 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4228 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4229 { F_MAGRPPERR, "MA group FIFO parity error" },
4230 { F_VFIDPERR, "VFID SRAM parity error" },
4231 { F_FIDPERR, "FID SRAM parity error" },
4232 { F_CFGSNPPERR, "config snoop FIFO parity error" },
4233 { F_HRSPPERR, "HMA channel response data SRAM parity error" },
4234 { F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4235 { F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4236 { F_DRSPPERR, "DMA channel response data SRAM parity error" },
4237 { F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4238 { F_CRSPPERR, "CMD channel response data SRAM parity error" },
4239 { F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4240 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4241 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4242 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4243 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4244 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4245 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4246 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4247 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4248 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4249 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4250 { F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4251 { 0 }
4252 };
4253 struct intr_info pcie_intr_info = {
4254 .name = "PCIE_INT_CAUSE",
4255 .cause_reg = A_PCIE_INT_CAUSE,
4256 .enable_reg = A_PCIE_INT_ENABLE,
4257 .fatal = 0xffffffff,
4258 .flags = NONFATAL_IF_DISABLED,
4259 .details = NULL,
4260 .actions = NULL,
4261 };
4262 bool fatal = false;
4263
4264 if (is_t4(adap)) {
4265 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
4266 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
4267
4268 pcie_intr_info.details = pcie_intr_details;
4269 } else {
4270 pcie_intr_info.details = t5_pcie_intr_details;
4271 }
4272 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
4273
4274 return (fatal);
4275}
4276
4277/*
4278 * TP interrupt handler.
4279 */
4280static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
4281{
4282 static const struct intr_details tp_intr_details[] = {
4283 { 0x3fffffff, "TP parity error" },
4284 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
4285 { 0 }
4286 };
4287 static const struct intr_info tp_intr_info = {
4288 .name = "TP_INT_CAUSE",
4289 .cause_reg = A_TP_INT_CAUSE,
4290 .enable_reg = A_TP_INT_ENABLE,
4291 .fatal = 0x7fffffff,
4292 .flags = NONFATAL_IF_DISABLED,
4293 .details = tp_intr_details,
4294 .actions = NULL,
4295 };
4296
4297 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
4298}
4299
4300/*
4301 * SGE interrupt handler.
4302 */
4303static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
4304{
4305 static const struct intr_info sge_int1_info = {
4306 .name = "SGE_INT_CAUSE1",
4307 .cause_reg = A_SGE_INT_CAUSE1,
4308 .enable_reg = A_SGE_INT_ENABLE1,
4309 .fatal = 0xffffffff,
4310 .flags = NONFATAL_IF_DISABLED,
4311 .details = NULL,
4312 .actions = NULL,
4313 };
4314 static const struct intr_info sge_int2_info = {
4315 .name = "SGE_INT_CAUSE2",
4316 .cause_reg = A_SGE_INT_CAUSE2,
4317 .enable_reg = A_SGE_INT_ENABLE2,
4318 .fatal = 0xffffffff,
4319 .flags = NONFATAL_IF_DISABLED,
4320 .details = NULL,
4321 .actions = NULL,
4322 };
4323 static const struct intr_details sge_int3_details[] = {
4324 { F_ERR_FLM_DBP,
4325 "DBP pointer delivery for invalid context or QID" },
4326 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4327 "Invalid QID or header request by IDMA" },
4328 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4329 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4330 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4331 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4332 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4333 { F_ERR_TIMER_ABOVE_MAX_QID,
4334 "SGE GTS with timer 0-5 for IQID > 1023" },
4335 { F_ERR_CPL_EXCEED_IQE_SIZE,
4336 "SGE received CPL exceeding IQE size" },
4337 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4338 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4339 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4340 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4341 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4342 "SGE IQID > 1023 received CPL for FL" },
4343 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4344 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4345 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4346 { F_ERR_ING_CTXT_PRIO,
4347 "Ingress context manager priority user error" },
4348 { F_ERR_EGR_CTXT_PRIO,
4349 "Egress context manager priority user error" },
4350 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
4351 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
4352 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4353 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4354 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4355 { 0x0000000f, "SGE context access for invalid queue" },
4356 { 0 }
4357 };
4358 static const struct intr_details t6_sge_int3_details[] = {
4359 { F_ERR_FLM_DBP,
4360 "DBP pointer delivery for invalid context or QID" },
4361 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4362 "Invalid QID or header request by IDMA" },
4363 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4364 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4365 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4366 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4367 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4368 { F_ERR_TIMER_ABOVE_MAX_QID,
4369 "SGE GTS with timer 0-5 for IQID > 1023" },
4370 { F_ERR_CPL_EXCEED_IQE_SIZE,
4371 "SGE received CPL exceeding IQE size" },
4372 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4373 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4374 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4375 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4376 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4377 "SGE IQID > 1023 received CPL for FL" },
4378 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4379 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4380 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4381 { F_ERR_ING_CTXT_PRIO,
4382 "Ingress context manager priority user error" },
4383 { F_ERR_EGR_CTXT_PRIO,
4384 "Egress context manager priority user error" },
4385 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
4386 { F_FATAL_WRE_LEN,
4387 "SGE WRE packet less than advertized length" },
4388 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4389 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4390 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4391 { 0x0000000f, "SGE context access for invalid queue" },
4392 { 0 }
4393 };
4394 struct intr_info sge_int3_info = {
4395 .name = "SGE_INT_CAUSE3",
4396 .cause_reg = A_SGE_INT_CAUSE3,
4397 .enable_reg = A_SGE_INT_ENABLE3,
4398 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
4399 .flags = 0,
4400 .details = NULL,
4401 .actions = NULL,
4402 };
4403 static const struct intr_info sge_int4_info = {
4404 .name = "SGE_INT_CAUSE4",
4405 .cause_reg = A_SGE_INT_CAUSE4,
4406 .enable_reg = A_SGE_INT_ENABLE4,
4407 .fatal = 0,
4408 .flags = 0,
4409 .details = NULL,
4410 .actions = NULL,
4411 };
4412 static const struct intr_info sge_int5_info = {
4413 .name = "SGE_INT_CAUSE5",
4414 .cause_reg = A_SGE_INT_CAUSE5,
4415 .enable_reg = A_SGE_INT_ENABLE5,
4416 .fatal = 0xffffffff,
4417 .flags = NONFATAL_IF_DISABLED,
4418 .details = NULL,
4419 .actions = NULL,
4420 };
4421 static const struct intr_info sge_int6_info = {
4422 .name = "SGE_INT_CAUSE6",
4423 .cause_reg = A_SGE_INT_CAUSE6,
4424 .enable_reg = A_SGE_INT_ENABLE6,
4425 .fatal = 0,
4426 .flags = 0,
4427 .details = NULL,
4428 .actions = NULL,
4429 };
4430
4431 bool fatal;
4432 u32 v;
4433
4434 if (chip_id(adap) <= CHELSIO_T5) {
4435 sge_int3_info.details = sge_int3_details;
4436 } else {
4437 sge_int3_info.details = t6_sge_int3_details;
4438 }
4439
4440 fatal = false;
4441 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
4442 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
4443 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
4444 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
4445 if (chip_id(adap) >= CHELSIO_T5)
4446 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
4447 if (chip_id(adap) >= CHELSIO_T6)
4448 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
4449
4450 v = t4_read_reg(adap, A_SGE_ERROR_STATS);
4451 if (v & F_ERROR_QID_VALID) {
4452 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
4453 if (v & F_UNCAPTURED_ERROR)
4454 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
4455 t4_write_reg(adap, A_SGE_ERROR_STATS,
4456 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
4457 }
4458
4459 return (fatal);
4460}
4461
4462/*
4463 * CIM interrupt handler.
4464 */
4465static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
4466{
4467 static const struct intr_details cim_host_intr_details[] = {
4468 /* T6+ */
4469 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
4470
4471 /* T5+ */
4472 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
4473 { F_PLCIM_MSTRSPDATAPARERR,
4474 "PL2CIM master response data parity error" },
4475 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
4476 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
4477 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
4478 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
4479 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
4480 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
4481
4482 /* T4+ */
4483 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
4484 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
4485 { F_MBHOSTPARERR, "CIM mailbox host read parity error" },
4486 { F_MBUPPARERR, "CIM mailbox uP parity error" },
4487 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
4488 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
4489 { F_IBQULPPARERR, "CIM IBQ ULP parity error" },
4490 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
4491 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */
4492 "CIM IBQ PCIe/SGE_HI parity error" },
4493 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
4494 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
4495 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
4496 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
4497 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
4498 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
4499 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
4500 { F_TIMER1INT, "CIM TIMER0 interrupt" },
4501 { F_TIMER0INT, "CIM TIMER0 interrupt" },
4502 { F_PREFDROPINT, "CIM control register prefetch drop" },
4503 { 0}
4504 };
4505 static const struct intr_info cim_host_intr_info = {
4506 .name = "CIM_HOST_INT_CAUSE",
4507 .cause_reg = A_CIM_HOST_INT_CAUSE,
4508 .enable_reg = A_CIM_HOST_INT_ENABLE,
4509 .fatal = 0x007fffe6,
4510 .flags = NONFATAL_IF_DISABLED,
4511 .details = cim_host_intr_details,
4512 .actions = NULL,
4513 };
4514 static const struct intr_details cim_host_upacc_intr_details[] = {
4515 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
4516 { F_TIMEOUTMAINT, "CIM PIF MA timeout" },
4517 { F_TIMEOUTINT, "CIM PIF timeout" },
4518 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
4519 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
4520 { F_BLKWRPLINT, "CIM block write to PL space" },
4521 { F_BLKRDPLINT, "CIM block read from PL space" },
4522 { F_SGLWRPLINT,
4523 "CIM single write to PL space with illegal BEs" },
4524 { F_SGLRDPLINT,
4525 "CIM single read from PL space with illegal BEs" },
4526 { F_BLKWRCTLINT, "CIM block write to CTL space" },
4527 { F_BLKRDCTLINT, "CIM block read from CTL space" },
4528 { F_SGLWRCTLINT,
4529 "CIM single write to CTL space with illegal BEs" },
4530 { F_SGLRDCTLINT,
4531 "CIM single read from CTL space with illegal BEs" },
4532 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
4533 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
4534 { F_SGLWREEPROMINT,
4535 "CIM single write to EEPROM space with illegal BEs" },
4536 { F_SGLRDEEPROMINT,
4537 "CIM single read from EEPROM space with illegal BEs" },
4538 { F_BLKWRFLASHINT, "CIM block write to flash space" },
4539 { F_BLKRDFLASHINT, "CIM block read from flash space" },
4540 { F_SGLWRFLASHINT, "CIM single write to flash space" },
4541 { F_SGLRDFLASHINT,
4542 "CIM single read from flash space with illegal BEs" },
4543 { F_BLKWRBOOTINT, "CIM block write to boot space" },
4544 { F_BLKRDBOOTINT, "CIM block read from boot space" },
4545 { F_SGLWRBOOTINT, "CIM single write to boot space" },
4546 { F_SGLRDBOOTINT,
4547 "CIM single read from boot space with illegal BEs" },
4548 { F_ILLWRBEINT, "CIM illegal write BEs" },
4549 { F_ILLRDBEINT, "CIM illegal read BEs" },
4550 { F_ILLRDINT, "CIM illegal read" },
4551 { F_ILLWRINT, "CIM illegal write" },
4552 { F_ILLTRANSINT, "CIM illegal transaction" },
4553 { F_RSVDSPACEINT, "CIM reserved space access" },
4554 {0}
4555 };
4556 static const struct intr_info cim_host_upacc_intr_info = {
4557 .name = "CIM_HOST_UPACC_INT_CAUSE",
4558 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4559 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
4560 .fatal = 0x3fffeeff,
4561 .flags = NONFATAL_IF_DISABLED,
4562 .details = cim_host_upacc_intr_details,
4563 .actions = NULL,
4564 };
4565 static const struct intr_info cim_pf_host_intr_info = {
4566 .name = "CIM_PF_HOST_INT_CAUSE",
4567 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4568 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
4569 .fatal = 0,
4570 .flags = 0,
4571 .details = NULL,
4572 .actions = NULL,
4573 };
4574 u32 val, fw_err;
4575 bool fatal;
4576
4577 /*
4578 * When the Firmware detects an internal error which normally wouldn't
4579 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4580 * to make sure the Host sees the Firmware Crash. So if we have a
4581 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4582 * interrupt.
4583 */
4584 fw_err = t4_read_reg(adap, A_PCIE_FW);
4585 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
4586 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
4587 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
4588 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
4589 }
4590
4591 fatal = (fw_err & F_PCIE_FW_ERR) != 0;
4592 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
4593 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
4594 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
4595 if (fatal)
4596 t4_os_cim_err(adap);
4597
4598 return (fatal);
4599}
4600
4601/*
4602 * ULP RX interrupt handler.
4603 */
4604static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
4605{
4606 static const struct intr_details ulprx_intr_details[] = {
4607 /* T5+ */
4608 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4609 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4610
4611 /* T4+ */
4612 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4613 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4614 { 0x007fffff, "ULPRX parity error" },
4615 { 0 }
4616 };
4617 static const struct intr_info ulprx_intr_info = {
4618 .name = "ULP_RX_INT_CAUSE",
4619 .cause_reg = A_ULP_RX_INT_CAUSE,
4620 .enable_reg = A_ULP_RX_INT_ENABLE,
4621 .fatal = 0x07ffffff,
4622 .flags = NONFATAL_IF_DISABLED,
4623 .details = ulprx_intr_details,
4624 .actions = NULL,
4625 };
4626 static const struct intr_info ulprx_intr2_info = {
4627 .name = "ULP_RX_INT_CAUSE_2",
4628 .cause_reg = A_ULP_RX_INT_CAUSE_2,
4629 .enable_reg = A_ULP_RX_INT_ENABLE_2,
4630 .fatal = 0,
4631 .flags = 0,
4632 .details = NULL,
4633 .actions = NULL,
4634 };
4635 bool fatal = false;
4636
4637 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
4638 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
4639
4640 return (fatal);
4641}
4642
4643/*
4644 * ULP TX interrupt handler.
4645 */
4646static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
4647{
4648 static const struct intr_details ulptx_intr_details[] = {
4649 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4650 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4651 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4652 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4653 { 0x0fffffff, "ULPTX parity error" },
4654 { 0 }
4655 };
4656 static const struct intr_info ulptx_intr_info = {
4657 .name = "ULP_TX_INT_CAUSE",
4658 .cause_reg = A_ULP_TX_INT_CAUSE,
4659 .enable_reg = A_ULP_TX_INT_ENABLE,
4660 .fatal = 0x0fffffff,
4661 .flags = NONFATAL_IF_DISABLED,
4662 .details = ulptx_intr_details,
4663 .actions = NULL,
4664 };
4665 static const struct intr_info ulptx_intr2_info = {
4666 .name = "ULP_TX_INT_CAUSE_2",
4667 .cause_reg = A_ULP_TX_INT_CAUSE_2,
4668 .enable_reg = A_ULP_TX_INT_ENABLE_2,
4669 .fatal = 0xf0,
4670 .flags = NONFATAL_IF_DISABLED,
4671 .details = NULL,
4672 .actions = NULL,
4673 };
4674 bool fatal = false;
4675
4676 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
4677 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
4678
4679 return (fatal);
4680}
4681
4682static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
4683{
4684 int i;
4685 u32 data[17];
4686
4687 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
4688 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
4689 for (i = 0; i < ARRAY_SIZE(data); i++) {
4690 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
4691 A_PM_TX_DBG_STAT0 + i, data[i]);
4692 }
4693
4694 return (false);
4695}
4696
4697/*
4698 * PM TX interrupt handler.
4699 */
4700static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
4701{
4702 static const struct intr_action pmtx_intr_actions[] = {
4703 { 0xffffffff, 0, pmtx_dump_dbg_stats },
4704 { 0 },
4705 };
4706 static const struct intr_details pmtx_intr_details[] = {
4707 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4708 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4709 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
4710 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
4711 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
4712 { 0x00f00000, "PMTX icspi FIFO Rx framing error" },
4713 { 0x000f0000, "PMTX icspi FIFO Tx framing error" },
4714 { 0x0000f000, "PMTX oespi FIFO Rx framing error" },
4715 { 0x00000f00, "PMTX oespi FIFO Tx framing error" },
4716 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
4717 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
4718 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
4719 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
4720 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
4721 { 0 }
4722 };
4723 static const struct intr_info pmtx_intr_info = {
4724 .name = "PM_TX_INT_CAUSE",
4725 .cause_reg = A_PM_TX_INT_CAUSE,
4726 .enable_reg = A_PM_TX_INT_ENABLE,
4727 .fatal = 0xffffffff,
4728 .flags = 0,
4729 .details = pmtx_intr_details,
4730 .actions = pmtx_intr_actions,
4731 };
4732
4733 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
4734}
4735
4736/*
4737 * PM RX interrupt handler.
4738 */
4739static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
4740{
4741 static const struct intr_details pmrx_intr_details[] = {
4742 /* T6+ */
4743 { 0x18000000, "PMRX ospi overflow" },
4744 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
4745 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
4746 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
4747 { F_SDC_ERR, "PMRX SDC error" },
4748
4749 /* T4+ */
4750 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
4751 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
4752 { 0x0003c000, "PMRX iespi Rx framing error" },
4753 { 0x00003c00, "PMRX iespi Tx framing error" },
4754 { 0x00000300, "PMRX ocspi Rx framing error" },
4755 { 0x000000c0, "PMRX ocspi Tx framing error" },
4756 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
4757 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
4758 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
4759 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
4760 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
4761 { 0 }
4762 };
4763 static const struct intr_info pmrx_intr_info = {
4764 .name = "PM_RX_INT_CAUSE",
4765 .cause_reg = A_PM_RX_INT_CAUSE,
4766 .enable_reg = A_PM_RX_INT_ENABLE,
4767 .fatal = 0x1fffffff,
4768 .flags = NONFATAL_IF_DISABLED,
4769 .details = pmrx_intr_details,
4770 .actions = NULL,
4771 };
4772
4773 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
4774}
4775
4776/*
4777 * CPL switch interrupt handler.
4778 */
4779static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
4780{
4781 static const struct intr_details cplsw_intr_details[] = {
4782 /* T5+ */
4783 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
4784 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
4785
4786 /* T4+ */
4787 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
4788 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
4789 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
4790 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
4791 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
4792 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
4793 { 0 }
4794 };
4795 static const struct intr_info cplsw_intr_info = {
4796 .name = "CPL_INTR_CAUSE",
4797 .cause_reg = A_CPL_INTR_CAUSE,
4798 .enable_reg = A_CPL_INTR_ENABLE,
4799 .fatal = 0xff,
4800 .flags = NONFATAL_IF_DISABLED,
4801 .details = cplsw_intr_details,
4802 .actions = NULL,
4803 };
4804
4805 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
4806}
4807
4808#define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
4809#define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
4810#define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
4811 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
4812 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
4813 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
4814#define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
4815 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
4816 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
4817
4818/*
4819 * LE interrupt handler.
4820 */
4821static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
4822{
4823 static const struct intr_details le_intr_details[] = {
4824 { F_REQQPARERR, "LE request queue parity error" },
4825 { F_UNKNOWNCMD, "LE unknown command" },
4826 { F_ACTRGNFULL, "LE active region full" },
4827 { F_PARITYERR, "LE parity error" },
4828 { F_LIPMISS, "LE LIP miss" },
4829 { F_LIP0, "LE 0 LIP error" },
4830 { 0 }
4831 };
4832 static const struct intr_details t6_le_intr_details[] = {
4833 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
4834 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
4835 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
4836 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
4837 { F_TOTCNTERR, "LE total active < TCAM count" },
4838 { F_CMDPRSRINTERR, "LE internal error in parser" },
4839 { F_CMDTIDERR, "Incorrect tid in LE command" },
4840 { F_T6_ACTRGNFULL, "LE active region full" },
4841 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
4842 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
4843 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
4844 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
4845 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
4846 { F_TCAMACCFAIL, "LE TCAM access failure" },
4847 { F_T6_UNKNOWNCMD, "LE unknown command" },
4848 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
4849 { F_T6_LIPMISS, "LE CLIP lookup miss" },
4850 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
4851 { 0 }
4852 };
4853 struct intr_info le_intr_info = {
4854 .name = "LE_DB_INT_CAUSE",
4855 .cause_reg = A_LE_DB_INT_CAUSE,
4856 .enable_reg = A_LE_DB_INT_ENABLE,
4857 .fatal = 0,
4858 .flags = NONFATAL_IF_DISABLED,
4859 .details = NULL,
4860 .actions = NULL,
4861 };
4862
4863 if (chip_id(adap) <= CHELSIO_T5) {
4864 le_intr_info.details = le_intr_details;
4865 le_intr_info.fatal = T5_LE_FATAL_MASK;
4866 } else {
4867 le_intr_info.details = t6_le_intr_details;
4868 le_intr_info.fatal = T6_LE_FATAL_MASK;
4869 }
4870
4871 return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
4872}
4873
4874/*
4875 * MPS interrupt handler.
4876 */
4877static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
4878{
4879 static const struct intr_details mps_rx_perr_intr_details[] = {
4880 { 0xffffffff, "MPS Rx parity error" },
4881 { 0 }
4882 };
4883 static const struct intr_info mps_rx_perr_intr_info = {
4884 .name = "MPS_RX_PERR_INT_CAUSE",
4885 .cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4886 .enable_reg = A_MPS_RX_PERR_INT_ENABLE,
4887 .fatal = 0xffffffff,
4888 .flags = NONFATAL_IF_DISABLED,
4889 .details = mps_rx_perr_intr_details,
4890 .actions = NULL,
4891 };
4892 static const struct intr_details mps_tx_intr_details[] = {
4893 { F_PORTERR, "MPS Tx destination port is disabled" },
4894 { F_FRMERR, "MPS Tx framing error" },
4895 { F_SECNTERR, "MPS Tx SOP/EOP error" },
4896 { F_BUBBLE, "MPS Tx underflow" },
4897 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
4898 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
4899 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
4900 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
4901 { 0 }
4902 };
4903 static const struct intr_info mps_tx_intr_info = {
4904 .name = "MPS_TX_INT_CAUSE",
4905 .cause_reg = A_MPS_TX_INT_CAUSE,
4906 .enable_reg = A_MPS_TX_INT_ENABLE,
4907 .fatal = 0x1ffff,
4908 .flags = NONFATAL_IF_DISABLED,
4909 .details = mps_tx_intr_details,
4910 .actions = NULL,
4911 };
4912 static const struct intr_details mps_trc_intr_details[] = {
4913 { F_MISCPERR, "MPS TRC misc parity error" },
4914 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
4915 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
4916 { 0 }
4917 };
4918 static const struct intr_info mps_trc_intr_info = {
4919 .name = "MPS_TRC_INT_CAUSE",
4920 .cause_reg = A_MPS_TRC_INT_CAUSE,
4921 .enable_reg = A_MPS_TRC_INT_ENABLE,
4922 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
4923 .flags = 0,
4924 .details = mps_trc_intr_details,
4925 .actions = NULL,
4926 };
4927 static const struct intr_details mps_stat_sram_intr_details[] = {
4928 { 0xffffffff, "MPS statistics SRAM parity error" },
4929 { 0 }
4930 };
4931 static const struct intr_info mps_stat_sram_intr_info = {
4932 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
4933 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4934 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
4935 .fatal = 0x1fffffff,
4936 .flags = NONFATAL_IF_DISABLED,
4937 .details = mps_stat_sram_intr_details,
4938 .actions = NULL,
4939 };
4940 static const struct intr_details mps_stat_tx_intr_details[] = {
4941 { 0xffffff, "MPS statistics Tx FIFO parity error" },
4942 { 0 }
4943 };
4944 static const struct intr_info mps_stat_tx_intr_info = {
4945 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
4946 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4947 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
4948 .fatal = 0xffffff,
4949 .flags = NONFATAL_IF_DISABLED,
4950 .details = mps_stat_tx_intr_details,
4951 .actions = NULL,
4952 };
4953 static const struct intr_details mps_stat_rx_intr_details[] = {
4954 { 0xffffff, "MPS statistics Rx FIFO parity error" },
4955 { 0 }
4956 };
4957 static const struct intr_info mps_stat_rx_intr_info = {
4958 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
4959 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4960 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
4961 .fatal = 0xffffff,
4962 .flags = 0,
4963 .details = mps_stat_rx_intr_details,
4964 .actions = NULL,
4965 };
4966 static const struct intr_details mps_cls_intr_details[] = {
4967 { F_HASHSRAM, "MPS hash SRAM parity error" },
4968 { F_MATCHTCAM, "MPS match TCAM parity error" },
4969 { F_MATCHSRAM, "MPS match SRAM parity error" },
4970 { 0 }
4971 };
4972 static const struct intr_info mps_cls_intr_info = {
4973 .name = "MPS_CLS_INT_CAUSE",
4974 .cause_reg = A_MPS_CLS_INT_CAUSE,
4975 .enable_reg = A_MPS_CLS_INT_ENABLE,
4976 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
4977 .flags = 0,
4978 .details = mps_cls_intr_details,
4979 .actions = NULL,
4980 };
4981 static const struct intr_details mps_stat_sram1_intr_details[] = {
4982 { 0xff, "MPS statistics SRAM1 parity error" },
4983 { 0 }
4984 };
4985 static const struct intr_info mps_stat_sram1_intr_info = {
4986 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
4987 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4988 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
4989 .fatal = 0xff,
4990 .flags = 0,
4991 .details = mps_stat_sram1_intr_details,
4992 .actions = NULL,
4993 };
4994
4995 bool fatal;
4996
4997 fatal = false;
4998 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
4999 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
5000 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
5001 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
5002 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
5003 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
5004 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
5005 if (chip_id(adap) > CHELSIO_T4) {
5006 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
5007 verbose);
5008 }
5009
5010 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5011 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */
5012
5013 return (fatal);
5014
5015}
5016
5017/*
5018 * EDC/MC interrupt handler.
5019 */
5020static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
5021{
5022 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
5023 unsigned int count_reg, v;
5024 static const struct intr_details mem_intr_details[] = {
5025 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
5026 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
5027 { F_PERR_INT_CAUSE, "FIFO parity error" },
5028 { 0 }
5029 };
5030 struct intr_info ii = {
5031 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
5032 .details = mem_intr_details,
5033 .flags = 0,
5034 .actions = NULL,
5035 };
5036 bool fatal;
5037
5038 switch (idx) {
5039 case MEM_EDC0:
5040 ii.name = "EDC0_INT_CAUSE";
5041 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
5042 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);
5043 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0);
5044 break;
5045 case MEM_EDC1:
5046 ii.name = "EDC1_INT_CAUSE";
5047 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
5048 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);
5049 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1);
5050 break;
5051 case MEM_MC0:
5052 ii.name = "MC0_INT_CAUSE";
5053 if (is_t4(adap)) {
5054 ii.cause_reg = A_MC_INT_CAUSE;
5055 ii.enable_reg = A_MC_INT_ENABLE;
5056 count_reg = A_MC_ECC_STATUS;
5057 } else {
5058 ii.cause_reg = A_MC_P_INT_CAUSE;
5059 ii.enable_reg = A_MC_P_INT_ENABLE;
5060 count_reg = A_MC_P_ECC_STATUS;
5061 }
5062 break;
5063 case MEM_MC1:
5064 ii.name = "MC1_INT_CAUSE";
5065 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
5066 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);
5067 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1);
5068 break;
5069 }
5070
5071 fatal = t4_handle_intr(adap, &ii, 0, verbose);
5072
5073 v = t4_read_reg(adap, count_reg);
5074 if (v != 0) {
5075 if (G_ECC_UECNT(v) != 0) {
5076 CH_ALERT(adap,
5077 "%s: %u uncorrectable ECC data error(s)\n",
5078 name[idx], G_ECC_UECNT(v));
5079 }
5080 if (G_ECC_CECNT(v) != 0) {
5081 if (idx <= MEM_EDC1)
5082 t4_edc_err_read(adap, idx);
5083 CH_WARN_RATELIMIT(adap,
5084 "%s: %u correctable ECC data error(s)\n",
5085 name[idx], G_ECC_CECNT(v));
5086 }
5087 t4_write_reg(adap, count_reg, 0xffffffff);
5088 }
5089
5090 return (fatal);
5091}
5092
5093static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
5094{
5095 u32 v;
5096
5097 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
5098 CH_ALERT(adap,
5099 "MA address wrap-around error by client %u to address %#x\n",
5100 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
5101 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
5102
5103 return (false);
5104}
5105
5106
5107/*
5108 * MA interrupt handler.
5109 */
5110static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
5111{
5112 static const struct intr_action ma_intr_actions[] = {
5113 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
5114 { 0 },
5115 };
5116 static const struct intr_info ma_intr_info = {
5117 .name = "MA_INT_CAUSE",
5118 .cause_reg = A_MA_INT_CAUSE,
5119 .enable_reg = A_MA_INT_ENABLE,
5120 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
5121 .flags = NONFATAL_IF_DISABLED,
5122 .details = NULL,
5123 .actions = ma_intr_actions,
5124 };
5125 static const struct intr_info ma_perr_status1 = {
5126 .name = "MA_PARITY_ERROR_STATUS1",
5127 .cause_reg = A_MA_PARITY_ERROR_STATUS1,
5128 .enable_reg = A_MA_PARITY_ERROR_ENABLE1,
5129 .fatal = 0xffffffff,
5130 .flags = 0,
5131 .details = NULL,
5132 .actions = NULL,
5133 };
5134 static const struct intr_info ma_perr_status2 = {
5135 .name = "MA_PARITY_ERROR_STATUS2",
5136 .cause_reg = A_MA_PARITY_ERROR_STATUS2,
5137 .enable_reg = A_MA_PARITY_ERROR_ENABLE2,
5138 .fatal = 0xffffffff,
5139 .flags = 0,
5140 .details = NULL,
5141 .actions = NULL,
5142 };
5143 bool fatal;
5144
5145 fatal = false;
5146 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
5147 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
5148 if (chip_id(adap) > CHELSIO_T4)
5149 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
5150
5151 return (fatal);
5152}
5153
5154/*
5155 * SMB interrupt handler.
5156 */
5157static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
5158{
5159 static const struct intr_details smb_intr_details[] = {
5160 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
5161 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
5162 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
5163 { 0 }
5164 };
5165 static const struct intr_info smb_intr_info = {
5166 .name = "SMB_INT_CAUSE",
5167 .cause_reg = A_SMB_INT_CAUSE,
5168 .enable_reg = A_SMB_INT_ENABLE,
5169 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
5170 .flags = 0,
5171 .details = smb_intr_details,
5172 .actions = NULL,
5173 };
5174
5175 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose));
5176}
5177
5178/*
5179 * NC-SI interrupt handler.
5180 */
5181static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
5182{
5183 static const struct intr_details ncsi_intr_details[] = {
5184 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
5185 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
5186 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
5187 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
5188 { 0 }
5189 };
5190 static const struct intr_info ncsi_intr_info = {
5191 .name = "NCSI_INT_CAUSE",
5192 .cause_reg = A_NCSI_INT_CAUSE,
5193 .enable_reg = A_NCSI_INT_ENABLE,
5194 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
5195 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
5196 .flags = 0,
5197 .details = ncsi_intr_details,
5198 .actions = NULL,
5199 };
5200
5201 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose));
5202}
5203
5204/*
5205 * MAC interrupt handler.
5206 */
5207static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
5208{
5209 static const struct intr_details mac_intr_details[] = {
5210 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
5211 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
5212 { 0 }
5213 };
5214 char name[32];
5215 struct intr_info ii;
5216 bool fatal = false;
5217
5218 if (is_t4(adap)) {
5219 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
5220 ii.name = &name[0];
5221 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5222 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
5223 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5224 ii.flags = 0;
5225 ii.details = mac_intr_details;
5226 ii.actions = NULL;
5227 } else {
5228 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
5229 ii.name = &name[0];
5230 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5231 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
5232 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5233 ii.flags = 0;
5234 ii.details = mac_intr_details;
5235 ii.actions = NULL;
5236 }
5237 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5238
5239 if (chip_id(adap) >= CHELSIO_T5) {
5240 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
5241 ii.name = &name[0];
5242 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5243 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
5244 ii.fatal = 0;
5245 ii.flags = 0;
5246 ii.details = NULL;
5247 ii.actions = NULL;
5248 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5249 }
5250
5251 if (chip_id(adap) >= CHELSIO_T6) {
5252 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
5253 ii.name = &name[0];
5254 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5255 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
5256 ii.fatal = 0;
5257 ii.flags = 0;
5258 ii.details = NULL;
5259 ii.actions = NULL;
5260 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5261 }
5262
5263 return (fatal);
5264}
5265
5266static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
5267{
5268 static const struct intr_details plpl_intr_details[] = {
5269 { F_FATALPERR, "Fatal parity error" },
5270 { F_PERRVFID, "VFID_MAP parity error" },
5271 { 0 }
5272 };
5273 static const struct intr_info plpl_intr_info = {
5274 .name = "PL_PL_INT_CAUSE",
5275 .cause_reg = A_PL_PL_INT_CAUSE,
5276 .enable_reg = A_PL_PL_INT_ENABLE,
5277 .fatal = F_FATALPERR | F_PERRVFID,
5278 .flags = NONFATAL_IF_DISABLED,
5279 .details = plpl_intr_details,
5280 .actions = NULL,
5281 };
5282
5283 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose));
5284}
5285
5295bool t4_slow_intr_handler(struct adapter *adap, bool verbose)
5296{
5297 static const struct intr_details pl_intr_details[] = {
5298 { F_MC1, "MC1" },
5299 { F_UART, "UART" },
5300 { F_ULP_TX, "ULP TX" },
5301 { F_SGE, "SGE" },
5302 { F_HMA, "HMA" },
5303 { F_CPL_SWITCH, "CPL Switch" },
5304 { F_ULP_RX, "ULP RX" },
5305 { F_PM_RX, "PM RX" },
5306 { F_PM_TX, "PM TX" },
5307 { F_MA, "MA" },
5308 { F_TP, "TP" },
5309 { F_LE, "LE" },
5310 { F_EDC1, "EDC1" },
5311 { F_EDC0, "EDC0" },
5312 { F_MC, "MC0" },
5313 { F_PCIE, "PCIE" },
5314 { F_PMU, "PMU" },
5315 { F_MAC3, "MAC3" },
5316 { F_MAC2, "MAC2" },
5317 { F_MAC1, "MAC1" },
5318 { F_MAC0, "MAC0" },
5319 { F_SMB, "SMB" },
5320 { F_SF, "SF" },
5321 { F_PL, "PL" },
5322 { F_NCSI, "NC-SI" },
5323 { F_MPS, "MPS" },
5324 { F_MI, "MI" },
5325 { F_DBG, "DBG" },
5326 { F_I2CM, "I2CM" },
5327 { F_CIM, "CIM" },
5328 { 0 }
5329 };
5330 static const struct intr_info pl_perr_cause = {
5331 .name = "PL_PERR_CAUSE",
5332 .cause_reg = A_PL_PERR_CAUSE,
5333 .enable_reg = A_PL_PERR_ENABLE,
5334 .fatal = 0xffffffff,
5335 .flags = 0,
5336 .details = pl_intr_details,
5337 .actions = NULL,
5338 };
5339 static const struct intr_action pl_intr_action[] = {
5340 { F_MC1, MEM_MC1, mem_intr_handler },
5341 { F_ULP_TX, -1, ulptx_intr_handler },
5342 { F_SGE, -1, sge_intr_handler },
5343 { F_CPL_SWITCH, -1, cplsw_intr_handler },
5344 { F_ULP_RX, -1, ulprx_intr_handler },
5345 { F_PM_RX, -1, pmrx_intr_handler},
5346 { F_PM_TX, -1, pmtx_intr_handler},
5347 { F_MA, -1, ma_intr_handler },
5348 { F_TP, -1, tp_intr_handler },
5349 { F_LE, -1, le_intr_handler },
5350 { F_EDC1, MEM_EDC1, mem_intr_handler },
5351 { F_EDC0, MEM_EDC0, mem_intr_handler },
5352 { F_MC0, MEM_MC0, mem_intr_handler },
5353 { F_PCIE, -1, pcie_intr_handler },
5354 { F_MAC3, 3, mac_intr_handler},
5355 { F_MAC2, 2, mac_intr_handler},
5356 { F_MAC1, 1, mac_intr_handler},
5357 { F_MAC0, 0, mac_intr_handler},
5358 { F_SMB, -1, smb_intr_handler},
5359 { F_PL, -1, plpl_intr_handler },
5360 { F_NCSI, -1, ncsi_intr_handler},
5361 { F_MPS, -1, mps_intr_handler },
5362 { F_CIM, -1, cim_intr_handler },
5363 { 0 }
5364 };
5365 static const struct intr_info pl_intr_info = {
5366 .name = "PL_INT_CAUSE",
5367 .cause_reg = A_PL_INT_CAUSE,
5368 .enable_reg = A_PL_INT_ENABLE,
5369 .fatal = 0,
5370 .flags = 0,
5371 .details = pl_intr_details,
5372 .actions = pl_intr_action,
5373 };
5374 u32 perr;
5375
5376 perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5377 if (verbose || perr != 0) {
5378 t4_show_intr_info(adap, &pl_perr_cause, perr);
5379 if (perr != 0)
5380 t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5381 if (verbose)
5382 perr |= t4_read_reg(adap, pl_intr_info.enable_reg);
5383 }
5384
5385 return (t4_handle_intr(adap, &pl_intr_info, perr, verbose));
5386}
5387
5388#define PF_INTR_MASK (F_PFSW | F_PFCIM)
5389
5403void t4_intr_enable(struct adapter *adap)
5404{
5405 u32 val = 0;
5406
5407 if (chip_id(adap) <= CHELSIO_T5)
5408 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
5409 else
5410 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
5411 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
5412 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
5413 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
5414 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5415 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
5416 F_EGRESS_SIZE_ERR;
5417 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
5418 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
5419 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
5420 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
5421}
5422
5431void t4_intr_disable(struct adapter *adap)
5432{
5433
5434 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
5435 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
5436}
5437
5445void t4_intr_clear(struct adapter *adap)
5446{
5447 static const u32 cause_reg[] = {
5448 A_CIM_HOST_INT_CAUSE,
5449 A_CIM_HOST_UPACC_INT_CAUSE,
5450 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
5451 A_CPL_INTR_CAUSE,
5452 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1),
5453 A_LE_DB_INT_CAUSE,
5454 A_MA_INT_WRAP_STATUS,
5455 A_MA_PARITY_ERROR_STATUS1,
5456 A_MA_INT_CAUSE,
5457 A_MPS_CLS_INT_CAUSE,
5458 A_MPS_RX_PERR_INT_CAUSE,
5459 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
5460 A_MPS_STAT_PERR_INT_CAUSE_SRAM,
5461 A_MPS_TRC_INT_CAUSE,
5462 A_MPS_TX_INT_CAUSE,
5463 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
5464 A_NCSI_INT_CAUSE,
5465 A_PCIE_INT_CAUSE,
5466 A_PCIE_NONFAT_ERR,
5467 A_PL_PL_INT_CAUSE,
5468 A_PM_RX_INT_CAUSE,
5469 A_PM_TX_INT_CAUSE,
5470 A_SGE_INT_CAUSE1,
5471 A_SGE_INT_CAUSE2,
5472 A_SGE_INT_CAUSE3,
5473 A_SGE_INT_CAUSE4,
5474 A_SMB_INT_CAUSE,
5475 A_TP_INT_CAUSE,
5476 A_ULP_RX_INT_CAUSE,
5477 A_ULP_RX_INT_CAUSE_2,
5478 A_ULP_TX_INT_CAUSE,
5479 A_ULP_TX_INT_CAUSE_2,
5480
5481 MYPF_REG(A_PL_PF_INT_CAUSE),
5482 };
5483 int i;
5484 const int nchan = adap->chip_params->nchan;
5485
5486 for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
5487 t4_write_reg(adap, cause_reg[i], 0xffffffff);
5488
5489 if (is_t4(adap)) {
5490 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
5491 0xffffffff);
5492 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
5493 0xffffffff);
5494 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff);
5495 for (i = 0; i < nchan; i++) {
5496 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE),
5497 0xffffffff);
5498 }
5499 }
5500 if (chip_id(adap) >= CHELSIO_T5) {
5501 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
5502 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff);
5503 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff);
5504 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff);
5505 if (is_t5(adap)) {
5506 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1),
5507 0xffffffff);
5508 }
5509 for (i = 0; i < nchan; i++) {
5510 t4_write_reg(adap, T5_PORT_REG(i,
5511 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff);
5512 if (chip_id(adap) > CHELSIO_T5) {
5513 t4_write_reg(adap, T5_PORT_REG(i,
5514 A_MAC_PORT_PERR_INT_CAUSE_100G),
5515 0xffffffff);
5516 }
5517 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE),
5518 0xffffffff);
5519 }
5520 }
5521 if (chip_id(adap) >= CHELSIO_T6) {
5522 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff);
5523 }
5524
5525 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5526 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff);
5527 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff);
5528 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */
5529}
5530
5538static int hash_mac_addr(const u8 *addr)
5539{
5540 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
5541 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
5542 a ^= b;
5543 a ^= (a >> 12);
5544 a ^= (a >> 6);
5545 return a & 0x3f;
5546}
5547
5565int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5566 int start, int n, const u16 *rspq, unsigned int nrspq)
5567{
5568 int ret;
5569 const u16 *rsp = rspq;
5570 const u16 *rsp_end = rspq + nrspq;
5571 struct fw_rss_ind_tbl_cmd cmd;
5572
5573 memset(&cmd, 0, sizeof(cmd));
5574 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
5575 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5576 V_FW_RSS_IND_TBL_CMD_VIID(viid));
5577 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5578
5579 /*
5580 * Each firmware RSS command can accommodate up to 32 RSS Ingress
5581 * Queue Identifiers. These Ingress Queue IDs are packed three to
5582 * a 32-bit word as 10-bit values with the upper remaining 2 bits
5583 * reserved.
5584 */
5585 while (n > 0) {
5586 int nq = min(n, 32);
5587 int nq_packed = 0;
5588 __be32 *qp = &cmd.iq0_to_iq2;
5589
5590 /*
5591 * Set up the firmware RSS command header to send the next
5592 * "nq" Ingress Queue IDs to the firmware.
5593 */
5594 cmd.niqid = cpu_to_be16(nq);
5595 cmd.startidx = cpu_to_be16(start);
5596
5597 /*
5598 * "nq" more done for the start of the next loop.
5599 */
5600 start += nq;
5601 n -= nq;
5602
5603 /*
5604 * While there are still Ingress Queue IDs to stuff into the
5605 * current firmware RSS command, retrieve them from the
5606 * Ingress Queue ID array and insert them into the command.
5607 */
5608 while (nq > 0) {
5609 /*
5610 * Grab up to the next 3 Ingress Queue IDs (wrapping
5611 * around the Ingress Queue ID array if necessary) and
5612 * insert them into the firmware RSS command at the
5613 * current 3-tuple position within the commad.
5614 */
5615 u16 qbuf[3];
5616 u16 *qbp = qbuf;
5617 int nqbuf = min(3, nq);
5618
5619 nq -= nqbuf;
5620 qbuf[0] = qbuf[1] = qbuf[2] = 0;
5621 while (nqbuf && nq_packed < 32) {
5622 nqbuf--;
5623 nq_packed++;
5624 *qbp++ = *rsp++;
5625 if (rsp >= rsp_end)
5626 rsp = rspq;
5627 }
5628 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
5629 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
5630 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
5631 }
5632
5633 /*
5634 * Send this portion of the RRS table update to the firmware;
5635 * bail out on any errors.
5636 */
5637 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5638 if (ret)
5639 return ret;
5640 }
5641 return 0;
5642}
5643
5653int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5654 unsigned int flags)
5655{
5656 struct fw_rss_glb_config_cmd c;
5657
5658 memset(&c, 0, sizeof(c));
5659 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
5660 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5661 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5662 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5663 c.u.manual.mode_pkd =
5664 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5665 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5666 c.u.basicvirtual.mode_keymode =
5667 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5668 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5669 } else
5670 return -EINVAL;
5671 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5672}
5673
5686int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5687 unsigned int flags, unsigned int defq, unsigned int skeyidx,
5688 unsigned int skey)
5689{
5690 struct fw_rss_vi_config_cmd c;
5691
5692 memset(&c, 0, sizeof(c));
5693 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5694 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5695 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
5696 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5697 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5698 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
5699 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
5700 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
5701 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
5702
5703 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5704}
5705
5706/* Read an RSS table row */
5707static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5708{
5709 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
5710 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
5711 5, 0, val);
5712}
5713
5721int t4_read_rss(struct adapter *adapter, u16 *map)
5722{
5723 u32 val;
5724 int i, ret;
5725 int rss_nentries = adapter->chip_params->rss_nentries;
5726
5727 for (i = 0; i < rss_nentries / 2; ++i) {
5728 ret = rd_rss_row(adapter, i, &val);
5729 if (ret)
5730 return ret;
5731 *map++ = G_LKPTBLQUEUE0(val);
5732 *map++ = G_LKPTBLQUEUE1(val);
5733 }
5734 return 0;
5735}
5736
5749static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5750 unsigned int nregs, unsigned int start_index,
5751 unsigned int rw, bool sleep_ok)
5752{
5753 int ret = 0;
5754 unsigned int i;
5755 struct fw_ldst_cmd c;
5756
5757 for (i = 0; i < nregs; i++) {
5758 memset(&c, 0, sizeof(c));
5759 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5760 F_FW_CMD_REQUEST |
5761 (rw ? F_FW_CMD_READ :
5762 F_FW_CMD_WRITE) |
5763 V_FW_LDST_CMD_ADDRSPACE(cmd));
5764 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5765
5766 c.u.addrval.addr = cpu_to_be32(start_index + i);
5767 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5768 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5769 sleep_ok);
5770 if (ret)
5771 return ret;
5772
5773 if (rw)
5774 vals[i] = be32_to_cpu(c.u.addrval.val);
5775 }
5776 return 0;
5777}
5778
5793static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5794 u32 *buff, u32 nregs, u32 start_index, int rw,
5795 bool sleep_ok)
5796{
5797 int rc = -EINVAL;
5798 int cmd;
5799
5800 switch (reg_addr) {
5801 case A_TP_PIO_ADDR:
5802 cmd = FW_LDST_ADDRSPC_TP_PIO;
5803 break;
5804 case A_TP_TM_PIO_ADDR:
5805 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5806 break;
5807 case A_TP_MIB_INDEX:
5808 cmd = FW_LDST_ADDRSPC_TP_MIB;
5809 break;
5810 default:
5811 goto indirect_access;
5812 }
5813
5814 if (t4_use_ldst(adap))
5815 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5816 sleep_ok);
5817
5818indirect_access:
5819
5820 if (rc) {
5821 if (rw)
5822 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5823 start_index);
5824 else
5825 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5826 start_index);
5827 }
5828}
5829
5840void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5841 u32 start_index, bool sleep_ok)
5842{
5843 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
5844 start_index, 1, sleep_ok);
5845}
5846
5857void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
5858 u32 start_index, bool sleep_ok)
5859{
5860 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5861 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
5862}
5863
5874void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5875 u32 start_index, bool sleep_ok)
5876{
5877 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
5878 nregs, start_index, 1, sleep_ok);
5879}
5880
5891void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5892 bool sleep_ok)
5893{
5894 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5895 start_index, 1, sleep_ok);
5896}
5897
5906void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5907{
5908 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5909}
5910
5922void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5923 bool sleep_ok)
5924{
5925 u8 rss_key_addr_cnt = 16;
5926 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5927
5928 /*
5929 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5930 * allows access to key addresses 16-63 by using KeyWrAddrX
5931 * as index[5:4](upper 2) into key table
5932 */
5933 if ((chip_id(adap) > CHELSIO_T5) &&
5934 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5935 rss_key_addr_cnt = 32;
5936
5937 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5938
5939 if (idx >= 0 && idx < rss_key_addr_cnt) {
5940 if (rss_key_addr_cnt > 16)
5941 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5942 vrt | V_KEYWRADDRX(idx >> 4) |
5943 V_T6_VFWRADDR(idx) | F_KEYWREN);
5944 else
5945 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5946 vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5947 }
5948}
5949
5960void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5961 u32 *valp, bool sleep_ok)
5962{
5963 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5964}
5965
5976void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5977 u32 val, bool sleep_ok)
5978{
5979 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5980 sleep_ok);
5981}
5982
5994void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5995 u32 *vfl, u32 *vfh, bool sleep_ok)
5996{
5997 u32 vrt, mask, data;
5998
5999 if (chip_id(adapter) <= CHELSIO_T5) {
6000 mask = V_VFWRADDR(M_VFWRADDR);
6001 data = V_VFWRADDR(index);
6002 } else {
6003 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
6004 data = V_T6_VFWRADDR(index);
6005 }
6006 /*
6007 * Request that the index'th VF Table values be read into VFL/VFH.
6008 */
6009 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
6010 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
6011 vrt |= data | F_VFRDEN;
6012 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
6013
6014 /*
6015 * Grab the VFL/VFH values ...
6016 */
6017 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
6018 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
6019}
6020
6032void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
6033 u32 vfl, u32 vfh, bool sleep_ok)
6034{
6035 u32 vrt, mask, data;
6036
6037 if (chip_id(adapter) <= CHELSIO_T5) {
6038 mask = V_VFWRADDR(M_VFWRADDR);
6039 data = V_VFWRADDR(index);
6040 } else {
6041 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
6042 data = V_T6_VFWRADDR(index);
6043 }
6044
6045 /*
6046 * Load up VFL/VFH with the values to be written ...
6047 */
6048 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
6049 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
6050
6051 /*
6052 * Write the VFL/VFH into the VF Table at index'th location.
6053 */
6054 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
6055 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
6056 vrt |= data | F_VFRDEN;
6057 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
6058}
6059
6067u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
6068{
6069 u32 pfmap;
6070
6071 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6072
6073 return pfmap;
6074}
6075
6083void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
6084{
6085 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6086}
6087
6095u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
6096{
6097 u32 pfmask;
6098
6099 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6100
6101 return pfmask;
6102}
6103
6111void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
6112{
6113 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6114}
6115
6126void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
6127 struct tp_tcp_stats *v6, bool sleep_ok)
6128{
6129 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
6130
6131#define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
6132#define STAT(x) val[STAT_IDX(x)]
6133#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
6134
6135 if (v4) {
6136 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6137 A_TP_MIB_TCP_OUT_RST, sleep_ok);
6138 v4->tcp_out_rsts = STAT(OUT_RST);
6139 v4->tcp_in_segs = STAT64(IN_SEG);
6140 v4->tcp_out_segs = STAT64(OUT_SEG);
6141 v4->tcp_retrans_segs = STAT64(RXT_SEG);
6142 }
6143 if (v6) {
6144 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6145 A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
6146 v6->tcp_out_rsts = STAT(OUT_RST);
6147 v6->tcp_in_segs = STAT64(IN_SEG);
6148 v6->tcp_out_segs = STAT64(OUT_SEG);
6149 v6->tcp_retrans_segs = STAT64(RXT_SEG);
6150 }
6151#undef STAT64
6152#undef STAT
6153#undef STAT_IDX
6154}
6155
6164void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
6165 bool sleep_ok)
6166{
6167 int nchan = adap->chip_params->nchan;
6168
6169 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
6170 sleep_ok);
6171
6172 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
6173 sleep_ok);
6174
6175 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
6176 sleep_ok);
6177
6178 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
6179 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
6180
6181 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
6182 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
6183
6184 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
6185 sleep_ok);
6186
6187 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
6188 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
6189
6190 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
6191 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
6192
6193 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
6194 sleep_ok);
6195}
6196
6205void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st,
6206 bool sleep_ok)
6207{
6208 int nchan = adap->chip_params->nchan;
6209
6210 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0,
6211 sleep_ok);
6212 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0,
6213 sleep_ok);
6214}
6215
6223void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
6224 bool sleep_ok)
6225{
6226 int nchan = adap->chip_params->nchan;
6227
6228 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
6229}
6230
6239void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
6240 bool sleep_ok)
6241{
6242 int nchan = adap->chip_params->nchan;
6243
6244 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
6245
6246 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
6247}
6248
6256void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
6257 bool sleep_ok)
6258{
6259 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
6260 sleep_ok);
6261}
6262
6272void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
6273 struct tp_fcoe_stats *st, bool sleep_ok)
6274{
6275 u32 val[2];
6276
6277 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
6278 sleep_ok);
6279
6280 t4_tp_mib_read(adap, &st->frames_drop, 1,
6281 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
6282
6283 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
6284 sleep_ok);
6285
6286 st->octets_ddp = ((u64)val[0] << 32) | val[1];
6287}
6288
6297void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
6298 bool sleep_ok)
6299{
6300 u32 val[4];
6301
6302 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
6303
6304 st->frames = val[0];
6305 st->drops = val[1];
6306 st->octets = ((u64)val[2] << 32) | val[3];
6307}
6308
6317void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st,
6318 bool sleep_ok)
6319{
6320
6321 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok);
6322}
6323
6332void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
6333{
6334 u32 v;
6335 int i;
6336
6337 for (i = 0; i < NMTUS; ++i) {
6338 t4_write_reg(adap, A_TP_MTU_TABLE,
6339 V_MTUINDEX(0xff) | V_MTUVALUE(i));
6340 v = t4_read_reg(adap, A_TP_MTU_TABLE);
6341 mtus[i] = G_MTUVALUE(v);
6342 if (mtu_log)
6343 mtu_log[i] = G_MTUWIDTH(v);
6344 }
6345}
6346
6355void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
6356{
6357 unsigned int mtu, w;
6358
6359 for (mtu = 0; mtu < NMTUS; ++mtu)
6360 for (w = 0; w < NCCTRL_WIN; ++w) {
6361 t4_write_reg(adap, A_TP_CCTRL_TABLE,
6362 V_ROWINDEX(0xffff) | (mtu << 5) | w);
6363 incr[mtu][w] = (u16)t4_read_reg(adap,
6364 A_TP_CCTRL_TABLE) & 0x1fff;
6365 }
6366}
6367
6377void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
6378 unsigned int mask, unsigned int val)
6379{
6380 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
6381 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
6382 t4_write_reg(adap, A_TP_PIO_DATA, val);
6383}
6384
6392static void init_cong_ctrl(unsigned short *a, unsigned short *b)
6393{
6394 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
6395 a[9] = 2;
6396 a[10] = 3;
6397 a[11] = 4;
6398 a[12] = 5;
6399 a[13] = 6;
6400 a[14] = 7;
6401 a[15] = 8;
6402 a[16] = 9;
6403 a[17] = 10;
6404 a[18] = 14;
6405 a[19] = 17;
6406 a[20] = 21;
6407 a[21] = 25;
6408 a[22] = 30;
6409 a[23] = 35;
6410 a[24] = 45;
6411 a[25] = 60;
6412 a[26] = 80;
6413 a[27] = 100;
6414 a[28] = 200;
6415 a[29] = 300;
6416 a[30] = 400;
6417 a[31] = 500;
6418
6419 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
6420 b[9] = b[10] = 1;
6421 b[11] = b[12] = 2;
6422 b[13] = b[14] = b[15] = b[16] = 3;
6423 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
6424 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
6425 b[28] = b[29] = 6;
6426 b[30] = b[31] = 7;
6427}
6428
6429/* The minimum additive increment value for the congestion control table */
6430#define CC_MIN_INCR 2U
6431
6444void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
6445 const unsigned short *alpha, const unsigned short *beta)
6446{
6447 static const unsigned int avg_pkts[NCCTRL_WIN] = {
6448 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
6449 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
6450 28672, 40960, 57344, 81920, 114688, 163840, 229376
6451 };
6452
6453 unsigned int i, w;
6454
6455 for (i = 0; i < NMTUS; ++i) {
6456 unsigned int mtu = mtus[i];
6457 unsigned int log2 = fls(mtu);
6458
6459 if (!(mtu & ((1 << log2) >> 2))) /* round */
6460 log2--;
6461 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
6462 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
6463
6464 for (w = 0; w < NCCTRL_WIN; ++w) {
6465 unsigned int inc;
6466
6467 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
6468 CC_MIN_INCR);
6469
6470 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
6471 (w << 16) | (beta[w] << 13) | inc);
6472 }
6473 }
6474}
6475
6485int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
6486 unsigned int start, unsigned int n)
6487{
6488 unsigned int vals[NTX_SCHED], i;
6489 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
6490
6491 if (n > NTX_SCHED)
6492 return -ERANGE;
6493
6494 /* convert values from us to dack ticks, rounding to closest value */
6495 for (i = 0; i < n; i++, pace_vals++) {
6496 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
6497 if (vals[i] > 0x7ff)
6498 return -ERANGE;
6499 if (*pace_vals && vals[i] == 0)
6500 return -ERANGE;
6501 }
6502 for (i = 0; i < n; i++, start++)
6503 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
6504 return 0;
6505}
6506
6515int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
6516{
6517 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
6518 unsigned int clk = adap->params.vpd.cclk * 1000;
6519 unsigned int selected_cpt = 0, selected_bpt = 0;
6520
6521 if (kbps > 0) {
6522 kbps *= 125; /* -> bytes */
6523 for (cpt = 1; cpt <= 255; cpt++) {
6524 tps = clk / cpt;
6525 bpt = (kbps + tps / 2) / tps;
6526 if (bpt > 0 && bpt <= 255) {
6527 v = bpt * tps;
6528 delta = v >= kbps ? v - kbps : kbps - v;
6529 if (delta < mindelta) {
6530 mindelta = delta;
6531 selected_cpt = cpt;
6532 selected_bpt = bpt;
6533 }
6534 } else if (selected_cpt)
6535 break;
6536 }
6537 if (!selected_cpt)
6538 return -EINVAL;
6539 }
6540 t4_write_reg(adap, A_TP_TM_PIO_ADDR,
6541 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
6542 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6543 if (sched & 1)
6544 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
6545 else
6546 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
6547 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6548 return 0;
6549}
6550
6559int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
6560{
6561 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
6562
6563 /* convert ipg to nearest number of core clocks */
6564 ipg *= core_ticks_per_usec(adap);
6565 ipg = (ipg + 5000) / 10000;
6566 if (ipg > M_TXTIMERSEPQ0)
6567 return -EINVAL;
6568
6569 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
6570 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6571 if (sched & 1)
6572 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
6573 else
6574 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
6575 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6576 t4_read_reg(adap, A_TP_TM_PIO_DATA);
6577 return 0;
6578}
6579
6580/*
6581 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6582 * clocks. The formula is
6583 *
6584 * bytes/s = bytes256 * 256 * ClkFreq / 4096
6585 *
6586 * which is equivalent to
6587 *
6588 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
6589 */
6590static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
6591{
6592 u64 v = (u64)bytes256 * adap->params.vpd.cclk;
6593
6594 return v * 62 + v / 2;
6595}
6596
6606void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
6607{
6608 u32 v;
6609
6610 v = t4_read_reg(adap, A_TP_TX_TRATE);
6611 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
6612 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
6613 if (adap->chip_params->nchan > 2) {
6614 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
6615 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
6616 }
6617
6618 v = t4_read_reg(adap, A_TP_TX_ORATE);
6619 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
6620 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
6621 if (adap->chip_params->nchan > 2) {
6622 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
6623 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
6624 }
6625}
6626
6638int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
6639 int idx, int enable)
6640{
6641 int i, ofst = idx * 4;
6642 u32 data_reg, mask_reg, cfg;
6643 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
6644
6645 if (idx < 0 || idx >= NTRACE)
6646 return -EINVAL;
6647
6648 if (tp == NULL || !enable) {
6649 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
6650 enable ? en : 0);
6651 return 0;
6652 }
6653
6654 /*
6655 * TODO - After T4 data book is updated, specify the exact
6656 * section below.
6657 *
6658 * See T4 data book - MPS section for a complete description
6659 * of the below if..else handling of A_MPS_TRC_CFG register
6660 * value.
6661 */
6662 cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
6663 if (cfg & F_TRCMULTIFILTER) {
6664 /*
6665 * If multiple tracers are enabled, then maximum
6666 * capture size is 2.5KB (FIFO size of a single channel)
6667 * minus 2 flits for CPL_TRACE_PKT header.
6668 */
6669 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
6670 return -EINVAL;
6671 } else {
6672 /*
6673 * If multiple tracers are disabled, to avoid deadlocks
6674 * maximum packet capture size of 9600 bytes is recommended.
6675 * Also in this mode, only trace0 can be enabled and running.
6676 */
6677 if (tp->snap_len > 9600 || idx)
6678 return -EINVAL;
6679 }
6680
6681 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
6682 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
6683 tp->min_len > M_TFMINPKTSIZE)
6684 return -EINVAL;
6685
6686 /* stop the tracer we'll be changing */
6687 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
6688
6689 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
6690 data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
6691 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
6692
6693 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6694 t4_write_reg(adap, data_reg, tp->data[i]);
6695 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6696 }
6697 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
6698 V_TFCAPTUREMAX(tp->snap_len) |
6699 V_TFMINPKTSIZE(tp->min_len));
6700 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
6701 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
6702 (is_t4(adap) ?
6703 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
6704 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
6705
6706 return 0;
6707}
6708
6718void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6719 int *enabled)
6720{
6721 u32 ctla, ctlb;
6722 int i, ofst = idx * 4;
6723 u32 data_reg, mask_reg;
6724
6725 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
6726 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
6727
6728 if (is_t4(adap)) {
6729 *enabled = !!(ctla & F_TFEN);
6730 tp->port = G_TFPORT(ctla);
6731 tp->invert = !!(ctla & F_TFINVERTMATCH);
6732 } else {
6733 *enabled = !!(ctla & F_T5_TFEN);
6734 tp->port = G_T5_TFPORT(ctla);
6735 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
6736 }
6737 tp->snap_len = G_TFCAPTUREMAX(ctlb);
6738 tp->min_len = G_TFMINPKTSIZE(ctlb);
6739 tp->skip_ofst = G_TFOFFSET(ctla);
6740 tp->skip_len = G_TFLENGTH(ctla);
6741
6742 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
6743 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
6744 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
6745
6746 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6747 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6748 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6749 }
6750}
6751
6760void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6761{
6762 int i;
6763 u32 data[2];
6764
6765 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6766 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
6767 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
6768 if (is_t4(adap))
6769 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
6770 else {
6771 t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
6772 A_PM_TX_DBG_DATA, data, 2,
6773 A_PM_TX_DBG_STAT_MSB);
6774 cycles[i] = (((u64)data[0] << 32) | data[1]);
6775 }
6776 }
6777}
6778
6787void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6788{
6789 int i;
6790 u32 data[2];
6791
6792 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6793 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
6794 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
6795 if (is_t4(adap)) {
6796 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
6797 } else {
6798 t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
6799 A_PM_RX_DBG_DATA, data, 2,
6800 A_PM_RX_DBG_STAT_MSB);
6801 cycles[i] = (((u64)data[0] << 32) | data[1]);
6802 }
6803 }
6804}
6805
6815static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
6816{
6817 u32 n;
6818
6819 if (adap->params.mps_bg_map)
6820 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
6821
6822 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6823 if (n == 0)
6824 return idx == 0 ? 0xf : 0;
6825 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6826 return idx < 2 ? (3 << (2 * idx)) : 0;
6827 return 1 << idx;
6828}
6829
6830/*
6831 * TP RX e-channels associated with the port.
6832 */
6833static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
6834{
6835 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6836 const u32 all_chan = (1 << adap->chip_params->nchan) - 1;
6837
6838 if (n == 0)
6839 return idx == 0 ? all_chan : 0;
6840 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6841 return idx < 2 ? (3 << (2 * idx)) : 0;
6842 return 1 << idx;
6843}
6844
6845/*
6846 * TP RX c-channel associated with the port.
6847 */
6848static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx)
6849{
6850 u32 param, val;
6851 int ret;
6852
6853 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6854 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP));
6855 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
6856 if (!ret)
6857 return (val >> (8 * idx)) & 0xff;
6858
6859 return 0;
6860}
6861
6866const char *t4_get_port_type_description(enum fw_port_type port_type)
6867{
6868 static const char *const port_type_description[] = {
6869 "Fiber_XFI",
6870 "Fiber_XAUI",
6871 "BT_SGMII",
6872 "BT_XFI",
6873 "BT_XAUI",
6874 "KX4",
6875 "CX4",
6876 "KX",
6877 "KR",
6878 "SFP",
6879 "BP_AP",
6880 "BP4_AP",
6881 "QSFP_10G",
6882 "QSA",
6883 "QSFP",
6884 "BP40_BA",
6885 "KR4_100G",
6886 "CR4_QSFP",
6887 "CR_QSFP",
6888 "CR2_QSFP",
6889 "SFP28",
6890 "KR_SFP28",
6891 };
6892
6893 if (port_type < ARRAY_SIZE(port_type_description))
6894 return port_type_description[port_type];
6895 return "UNKNOWN";
6896}
6897
6906void t4_get_port_stats_offset(struct adapter *adap, int idx,
6907 struct port_stats *stats,
6908 struct port_stats *offset)
6909{
6910 u64 *s, *o;
6911 int i;
6912
6913 t4_get_port_stats(adap, idx, stats);
6914 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
6915 i < (sizeof(struct port_stats)/sizeof(u64)) ;
6916 i++, s++, o++)
6917 *s -= *o;
6918}
6919
6928void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6929{
6930 struct port_info *pi = adap->port[idx];
6931 u32 bgmap = pi->mps_bg_map;
6932 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
6933
6934#define GET_STAT(name) \
6935 t4_read_reg64(adap, \
6936 (is_t4(adap) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L) : \
6937 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L)))
6938#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6939
6940 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6941 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6942 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6943 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6944 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6945 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6946 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6947 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6948 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6949 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6950 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6951 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6952 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6953 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6954 p->tx_drop = GET_STAT(TX_PORT_DROP);
6955 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6956 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6957 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6958 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6959 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6960 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6961 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6962 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6963
6964 if (chip_id(adap) >= CHELSIO_T5) {
6965 if (stat_ctl & F_COUNTPAUSESTATTX) {
6966 p->tx_frames -= p->tx_pause;
6967 p->tx_octets -= p->tx_pause * 64;
6968 }
6969 if (stat_ctl & F_COUNTPAUSEMCTX)
6970 p->tx_mcast_frames -= p->tx_pause;
6971 }
6972
6973 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6974 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6975 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6976 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6977 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6978 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6979 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6980 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6981 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6982 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6983 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6984 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6985 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6986 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6987 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6988 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6989 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6990 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6991 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6992 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6993 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6994 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6995 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6996 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6997 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6998 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6999
7000 if (pi->fcs_reg != -1)
7001 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base;
7002
7003 if (chip_id(adap) >= CHELSIO_T5) {
7004 if (stat_ctl & F_COUNTPAUSESTATRX) {
7005 p->rx_frames -= p->rx_pause;
7006 p->rx_octets -= p->rx_pause * 64;
7007 }
7008 if (stat_ctl & F_COUNTPAUSEMCRX)
7009 p->rx_mcast_frames -= p->rx_pause;
7010 }
7011
7012 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
7013 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
7014 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
7015 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
7016 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
7017 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
7018 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
7019 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
7020
7021#undef GET_STAT
7022#undef GET_STAT_COM
7023}
7024
7033void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
7034{
7035
7036#define GET_STAT(name) \
7037 t4_read_reg64(adap, \
7038 (is_t4(adap) ? \
7039 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
7040 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
7041#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
7042
7043 p->octets = GET_STAT(BYTES);
7044 p->frames = GET_STAT(FRAMES);
7045 p->bcast_frames = GET_STAT(BCAST);
7046 p->mcast_frames = GET_STAT(MCAST);
7047 p->ucast_frames = GET_STAT(UCAST);
7048 p->error_frames = GET_STAT(ERROR);
7049
7050 p->frames_64 = GET_STAT(64B);
7051 p->frames_65_127 = GET_STAT(65B_127B);
7052 p->frames_128_255 = GET_STAT(128B_255B);
7053 p->frames_256_511 = GET_STAT(256B_511B);
7054 p->frames_512_1023 = GET_STAT(512B_1023B);
7055 p->frames_1024_1518 = GET_STAT(1024B_1518B);
7056 p->frames_1519_max = GET_STAT(1519B_MAX);
7057 p->drop = GET_STAT(DROP_FRAMES);
7058
7059 if (idx < adap->params.nports) {
7060 u32 bg = adap2pinfo(adap, idx)->mps_bg_map;
7061
7062 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
7063 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
7064 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
7065 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
7066 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
7067 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
7068 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
7069 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
7070 }
7071
7072#undef GET_STAT
7073#undef GET_STAT_COM
7074}
7075
7084void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
7085 const u8 *addr)
7086{
7087 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
7088
7089 if (is_t4(adap)) {
7090 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
7091 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
7092 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7093 } else {
7094 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
7095 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
7096 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7097 }
7098
7099 if (addr) {
7100 t4_write_reg(adap, mag_id_reg_l,
7101 (addr[2] << 24) | (addr[3] << 16) |
7102 (addr[4] << 8) | addr[5]);
7103 t4_write_reg(adap, mag_id_reg_h,
7104 (addr[0] << 8) | addr[1]);
7105 }
7106 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
7107 V_MAGICEN(addr != NULL));
7108}
7109
7125int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
7126 u64 mask0, u64 mask1, unsigned int crc, bool enable)
7127{
7128 int i;
7129 u32 port_cfg_reg;
7130
7131 if (is_t4(adap))
7132 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7133 else
7134 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7135
7136 if (!enable) {
7137 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
7138 return 0;
7139 }
7140 if (map > 0xff)
7141 return -EINVAL;
7142
7143#define EPIO_REG(name) \
7144 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
7145 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
7146
7147 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
7148 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
7149 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
7150
7151 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
7152 if (!(map & 1))
7153 continue;
7154
7155 /* write byte masks */
7156 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
7157 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
7158 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7159 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7160 return -ETIMEDOUT;
7161
7162 /* write CRC */
7163 t4_write_reg(adap, EPIO_REG(DATA0), crc);
7164 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
7165 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7166 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7167 return -ETIMEDOUT;
7168 }
7169#undef EPIO_REG
7170
7171 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
7172 return 0;
7173}
7174
7175/* t4_mk_filtdelwr - create a delete filter WR
7176 * @ftid: the filter ID
7177 * @wr: the filter work request to populate
7178 * @qid: ingress queue to receive the delete notification
7179 *
7180 * Creates a filter work request to delete the supplied filter. If @qid is
7181 * negative the delete notification is suppressed.
7182 */
7183void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
7184{
7185 memset(wr, 0, sizeof(*wr));
7186 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
7187 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
7188 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
7189 V_FW_FILTER_WR_NOREPLY(qid < 0));
7190 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
7191 if (qid >= 0)
7192 wr->rx_chan_rx_rpl_iq =
7193 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
7194}
7195
7196#define INIT_CMD(var, cmd, rd_wr) do { \
7197 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
7198 F_FW_CMD_REQUEST | \
7199 F_FW_CMD_##rd_wr); \
7200 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
7201} while (0)
7202
7203int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
7204 u32 addr, u32 val)
7205{
7206 u32 ldst_addrspace;
7207 struct fw_ldst_cmd c;
7208
7209 memset(&c, 0, sizeof(c));
7210 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
7211 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7212 F_FW_CMD_REQUEST |
7213 F_FW_CMD_WRITE |
7214 ldst_addrspace);
7215 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7216 c.u.addrval.addr = cpu_to_be32(addr);
7217 c.u.addrval.val = cpu_to_be32(val);
7218
7219 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7220}
7221
7233int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7234 unsigned int mmd, unsigned int reg, unsigned int *valp)
7235{
7236 int ret;
7237 u32 ldst_addrspace;
7238 struct fw_ldst_cmd c;
7239
7240 memset(&c, 0, sizeof(c));
7241 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7242 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7243 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7244 ldst_addrspace);
7245 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7246 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7247 V_FW_LDST_CMD_MMD(mmd));
7248 c.u.mdio.raddr = cpu_to_be16(reg);
7249
7250 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7251 if (ret == 0)
7252 *valp = be16_to_cpu(c.u.mdio.rval);
7253 return ret;
7254}
7255
7267int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7268 unsigned int mmd, unsigned int reg, unsigned int val)
7269{
7270 u32 ldst_addrspace;
7271 struct fw_ldst_cmd c;
7272
7273 memset(&c, 0, sizeof(c));
7274 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7275 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7276 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7277 ldst_addrspace);
7278 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7279 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7280 V_FW_LDST_CMD_MMD(mmd));
7281 c.u.mdio.raddr = cpu_to_be16(reg);
7282 c.u.mdio.rval = cpu_to_be16(val);
7283
7284 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7285}
7286
7293void t4_sge_decode_idma_state(struct adapter *adapter, int state)
7294{
7295 static const char * const t4_decode[] = {
7296 "IDMA_IDLE",
7297 "IDMA_PUSH_MORE_CPL_FIFO",
7298 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7299 "Not used",
7300 "IDMA_PHYSADDR_SEND_PCIEHDR",
7301 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7302 "IDMA_PHYSADDR_SEND_PAYLOAD",
7303 "IDMA_SEND_FIFO_TO_IMSG",
7304 "IDMA_FL_REQ_DATA_FL_PREP",
7305 "IDMA_FL_REQ_DATA_FL",
7306 "IDMA_FL_DROP",
7307 "IDMA_FL_H_REQ_HEADER_FL",
7308 "IDMA_FL_H_SEND_PCIEHDR",
7309 "IDMA_FL_H_PUSH_CPL_FIFO",
7310 "IDMA_FL_H_SEND_CPL",
7311 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7312 "IDMA_FL_H_SEND_IP_HDR",
7313 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7314 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7315 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7316 "IDMA_FL_D_SEND_PCIEHDR",
7317 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7318 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7319 "IDMA_FL_SEND_PCIEHDR",
7320 "IDMA_FL_PUSH_CPL_FIFO",
7321 "IDMA_FL_SEND_CPL",
7322 "IDMA_FL_SEND_PAYLOAD_FIRST",
7323 "IDMA_FL_SEND_PAYLOAD",
7324 "IDMA_FL_REQ_NEXT_DATA_FL",
7325 "IDMA_FL_SEND_NEXT_PCIEHDR",
7326 "IDMA_FL_SEND_PADDING",
7327 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7328 "IDMA_FL_SEND_FIFO_TO_IMSG",
7329 "IDMA_FL_REQ_DATAFL_DONE",
7330 "IDMA_FL_REQ_HEADERFL_DONE",
7331 };
7332 static const char * const t5_decode[] = {
7333 "IDMA_IDLE",
7334 "IDMA_ALMOST_IDLE",
7335 "IDMA_PUSH_MORE_CPL_FIFO",
7336 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7337 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7338 "IDMA_PHYSADDR_SEND_PCIEHDR",
7339 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7340 "IDMA_PHYSADDR_SEND_PAYLOAD",
7341 "IDMA_SEND_FIFO_TO_IMSG",
7342 "IDMA_FL_REQ_DATA_FL",
7343 "IDMA_FL_DROP",
7344 "IDMA_FL_DROP_SEND_INC",
7345 "IDMA_FL_H_REQ_HEADER_FL",
7346 "IDMA_FL_H_SEND_PCIEHDR",
7347 "IDMA_FL_H_PUSH_CPL_FIFO",
7348 "IDMA_FL_H_SEND_CPL",
7349 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7350 "IDMA_FL_H_SEND_IP_HDR",
7351 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7352 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7353 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7354 "IDMA_FL_D_SEND_PCIEHDR",
7355 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7356 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7357 "IDMA_FL_SEND_PCIEHDR",
7358 "IDMA_FL_PUSH_CPL_FIFO",
7359 "IDMA_FL_SEND_CPL",
7360 "IDMA_FL_SEND_PAYLOAD_FIRST",
7361 "IDMA_FL_SEND_PAYLOAD",
7362 "IDMA_FL_REQ_NEXT_DATA_FL",
7363 "IDMA_FL_SEND_NEXT_PCIEHDR",
7364 "IDMA_FL_SEND_PADDING",
7365 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7366 };
7367 static const char * const t6_decode[] = {
7368 "IDMA_IDLE",
7369 "IDMA_PUSH_MORE_CPL_FIFO",
7370 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7371 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7372 "IDMA_PHYSADDR_SEND_PCIEHDR",
7373 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7374 "IDMA_PHYSADDR_SEND_PAYLOAD",
7375 "IDMA_FL_REQ_DATA_FL",
7376 "IDMA_FL_DROP",
7377 "IDMA_FL_DROP_SEND_INC",
7378 "IDMA_FL_H_REQ_HEADER_FL",
7379 "IDMA_FL_H_SEND_PCIEHDR",
7380 "IDMA_FL_H_PUSH_CPL_FIFO",
7381 "IDMA_FL_H_SEND_CPL",
7382 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7383 "IDMA_FL_H_SEND_IP_HDR",
7384 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7385 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7386 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7387 "IDMA_FL_D_SEND_PCIEHDR",
7388 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7389 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7390 "IDMA_FL_SEND_PCIEHDR",
7391 "IDMA_FL_PUSH_CPL_FIFO",
7392 "IDMA_FL_SEND_CPL",
7393 "IDMA_FL_SEND_PAYLOAD_FIRST",
7394 "IDMA_FL_SEND_PAYLOAD",
7395 "IDMA_FL_REQ_NEXT_DATA_FL",
7396 "IDMA_FL_SEND_NEXT_PCIEHDR",
7397 "IDMA_FL_SEND_PADDING",
7398 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7399 };
7400 static const u32 sge_regs[] = {
7401 A_SGE_DEBUG_DATA_LOW_INDEX_2,
7402 A_SGE_DEBUG_DATA_LOW_INDEX_3,
7403 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
7404 };
7405 const char * const *sge_idma_decode;
7406 int sge_idma_decode_nstates;
7407 int i;
7408 unsigned int chip_version = chip_id(adapter);
7409
7410 /* Select the right set of decode strings to dump depending on the
7411 * adapter chip type.
7412 */
7413 switch (chip_version) {
7414 case CHELSIO_T4:
7415 sge_idma_decode = (const char * const *)t4_decode;
7416 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
7417 break;
7418
7419 case CHELSIO_T5:
7420 sge_idma_decode = (const char * const *)t5_decode;
7421 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
7422 break;
7423
7424 case CHELSIO_T6:
7425 sge_idma_decode = (const char * const *)t6_decode;
7426 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
7427 break;
7428
7429 default:
7430 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
7431 return;
7432 }
7433
7434 if (state < sge_idma_decode_nstates)
7435 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
7436 else
7437 CH_WARN(adapter, "idma state %d unknown\n", state);
7438
7439 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
7440 CH_WARN(adapter, "SGE register %#x value %#x\n",
7441 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
7442}
7443
7452int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
7453{
7454 int ret;
7455 u32 ldst_addrspace;
7456 struct fw_ldst_cmd c;
7457
7458 memset(&c, 0, sizeof(c));
7459 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ?
7460 FW_LDST_ADDRSPC_SGE_EGRC :
7461 FW_LDST_ADDRSPC_SGE_INGC);
7462 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7463 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7464 ldst_addrspace);
7465 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7466 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
7467
7468 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7469 return ret;
7470}
7471
7483int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
7484 enum dev_master master, enum dev_state *state)
7485{
7486 int ret;
7487 struct fw_hello_cmd c;
7488 u32 v;
7489 unsigned int master_mbox;
7490 int retries = FW_CMD_HELLO_RETRIES;
7491
7492retry:
7493 memset(&c, 0, sizeof(c));
7494 INIT_CMD(c, HELLO, WRITE);
7495 c.err_to_clearinit = cpu_to_be32(
7496 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
7497 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
7498 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
7499 mbox : M_FW_HELLO_CMD_MBMASTER) |
7500 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
7501 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
7502 F_FW_HELLO_CMD_CLEARINIT);
7503
7504 /*
7505 * Issue the HELLO command to the firmware. If it's not successful
7506 * but indicates that we got a "busy" or "timeout" condition, retry
7507 * the HELLO until we exhaust our retry limit. If we do exceed our
7508 * retry limit, check to see if the firmware left us any error
7509 * information and report that if so ...
7510 */
7511 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7512 if (ret != FW_SUCCESS) {
7513 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
7514 goto retry;
7515 return ret;
7516 }
7517
7518 v = be32_to_cpu(c.err_to_clearinit);
7519 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
7520 if (state) {
7521 if (v & F_FW_HELLO_CMD_ERR)
7522 *state = DEV_STATE_ERR;
7523 else if (v & F_FW_HELLO_CMD_INIT)
7524 *state = DEV_STATE_INIT;
7525 else
7526 *state = DEV_STATE_UNINIT;
7527 }
7528
7529 /*
7530 * If we're not the Master PF then we need to wait around for the
7531 * Master PF Driver to finish setting up the adapter.
7532 *
7533 * Note that we also do this wait if we're a non-Master-capable PF and
7534 * there is no current Master PF; a Master PF may show up momentarily
7535 * and we wouldn't want to fail pointlessly. (This can happen when an
7536 * OS loads lots of different drivers rapidly at the same time). In
7537 * this case, the Master PF returned by the firmware will be
7538 * M_PCIE_FW_MASTER so the test below will work ...
7539 */
7540 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
7541 master_mbox != mbox) {
7542 int waiting = FW_CMD_HELLO_TIMEOUT;
7543
7544 /*
7545 * Wait for the firmware to either indicate an error or
7546 * initialized state. If we see either of these we bail out
7547 * and report the issue to the caller. If we exhaust the
7548 * "hello timeout" and we haven't exhausted our retries, try
7549 * again. Otherwise bail with a timeout error.
7550 */
7551 for (;;) {
7552 u32 pcie_fw;
7553
7554 msleep(50);
7555 waiting -= 50;
7556
7557 /*
7558 * If neither Error nor Initialialized are indicated
7559 * by the firmware keep waiting till we exhaust our
7560 * timeout ... and then retry if we haven't exhausted
7561 * our retries ...
7562 */
7563 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
7564 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
7565 if (waiting <= 0) {
7566 if (retries-- > 0)
7567 goto retry;
7568
7569 return -ETIMEDOUT;
7570 }
7571 continue;
7572 }
7573
7574 /*
7575 * We either have an Error or Initialized condition
7576 * report errors preferentially.
7577 */
7578 if (state) {
7579 if (pcie_fw & F_PCIE_FW_ERR)
7580 *state = DEV_STATE_ERR;
7581 else if (pcie_fw & F_PCIE_FW_INIT)
7582 *state = DEV_STATE_INIT;
7583 }
7584
7585 /*
7586 * If we arrived before a Master PF was selected and
7587 * there's not a valid Master PF, grab its identity
7588 * for our caller.
7589 */
7590 if (master_mbox == M_PCIE_FW_MASTER &&
7591 (pcie_fw & F_PCIE_FW_MASTER_VLD))
7592 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
7593 break;
7594 }
7595 }
7596
7597 return master_mbox;
7598}
7599
7607int t4_fw_bye(struct adapter *adap, unsigned int mbox)
7608{
7609 struct fw_bye_cmd c;
7610
7611 memset(&c, 0, sizeof(c));
7612 INIT_CMD(c, BYE, WRITE);
7613 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7614}
7615
7624int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7625{
7626 struct fw_reset_cmd c;
7627
7628 memset(&c, 0, sizeof(c));
7629 INIT_CMD(c, RESET, WRITE);
7630 c.val = cpu_to_be32(reset);
7631 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7632}
7633
7650int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7651{
7652 int ret = 0;
7653
7654 /*
7655 * If a legitimate mailbox is provided, issue a RESET command
7656 * with a HALT indication.
7657 */
7658 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
7659 struct fw_reset_cmd c;
7660
7661 memset(&c, 0, sizeof(c));
7662 INIT_CMD(c, RESET, WRITE);
7663 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
7664 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
7665 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7666 }
7667
7668 /*
7669 * Normally we won't complete the operation if the firmware RESET
7670 * command fails but if our caller insists we'll go ahead and put the
7671 * uP into RESET. This can be useful if the firmware is hung or even
7672 * missing ... We'll have to take the risk of putting the uP into
7673 * RESET without the cooperation of firmware in that case.
7674 *
7675 * We also force the firmware's HALT flag to be on in case we bypassed
7676 * the firmware RESET command above or we're dealing with old firmware
7677 * which doesn't have the HALT capability. This will serve as a flag
7678 * for the incoming firmware to know that it's coming out of a HALT
7679 * rather than a RESET ... if it's new enough to understand that ...
7680 */
7681 if (ret == 0 || force) {
7682 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
7683 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
7684 F_PCIE_FW_HALT);
7685 }
7686
7687 /*
7688 * And we always return the result of the firmware RESET command
7689 * even when we force the uP into RESET ...
7690 */
7691 return ret;
7692}
7693
7702int t4_fw_restart(struct adapter *adap, unsigned int mbox)
7703{
7704 int ms;
7705
7706 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
7707 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7708 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
7709 return FW_SUCCESS;
7710 msleep(100);
7711 ms += 100;
7712 }
7713
7714 return -ETIMEDOUT;
7715}
7716
7738int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7739 const u8 *fw_data, unsigned int size, int force)
7740{
7741 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7742 unsigned int bootstrap =
7743 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
7744 int ret;
7745
7746 if (!t4_fw_matches_chip(adap, fw_hdr))
7747 return -EINVAL;
7748
7749 if (!bootstrap) {
7750 ret = t4_fw_halt(adap, mbox, force);
7751 if (ret < 0 && !force)
7752 return ret;
7753 }
7754
7755 ret = t4_load_fw(adap, fw_data, size);
7756 if (ret < 0 || bootstrap)
7757 return ret;
7758
7759 return t4_fw_restart(adap, mbox);
7760}
7761
7770int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7771{
7772 struct fw_initialize_cmd c;
7773
7774 memset(&c, 0, sizeof(c));
7775 INIT_CMD(c, INITIALIZE, WRITE);
7776 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7777}
7778
7793int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7794 unsigned int vf, unsigned int nparams, const u32 *params,
7795 u32 *val, int rw)
7796{
7797 int i, ret;
7798 struct fw_params_cmd c;
7799 __be32 *p = &c.param[0].mnem;
7800
7801 if (nparams > 7)
7802 return -EINVAL;
7803
7804 memset(&c, 0, sizeof(c));
7805 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7806 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7807 V_FW_PARAMS_CMD_PFN(pf) |
7808 V_FW_PARAMS_CMD_VFN(vf));
7809 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7810
7811 for (i = 0; i < nparams; i++) {
7812 *p++ = cpu_to_be32(*params++);
7813 if (rw)
7814 *p = cpu_to_be32(*(val + i));
7815 p++;
7816 }
7817
7818 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7819 if (ret == 0)
7820 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7821 *val++ = be32_to_cpu(*p);
7822 return ret;
7823}
7824
7825int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7826 unsigned int vf, unsigned int nparams, const u32 *params,
7827 u32 *val)
7828{
7829 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
7830}
7831
7846int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7847 unsigned int pf, unsigned int vf,
7848 unsigned int nparams, const u32 *params,
7849 const u32 *val, int timeout)
7850{
7851 struct fw_params_cmd c;
7852 __be32 *p = &c.param[0].mnem;
7853
7854 if (nparams > 7)
7855 return -EINVAL;
7856
7857 memset(&c, 0, sizeof(c));
7858 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7859 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7860 V_FW_PARAMS_CMD_PFN(pf) |
7861 V_FW_PARAMS_CMD_VFN(vf));
7862 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7863
7864 while (nparams--) {
7865 *p++ = cpu_to_be32(*params++);
7866 *p++ = cpu_to_be32(*val++);
7867 }
7868
7869 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7870}
7871
7885int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7886 unsigned int vf, unsigned int nparams, const u32 *params,
7887 const u32 *val)
7888{
7889 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7890 FW_CMD_MAX_TIMEOUT);
7891}
7892
7914int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7915 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7916 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7917 unsigned int vi, unsigned int cmask, unsigned int pmask,
7918 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7919{
7920 struct fw_pfvf_cmd c;
7921
7922 memset(&c, 0, sizeof(c));
7923 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7924 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7925 V_FW_PFVF_CMD_VFN(vf));
7926 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7927 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7928 V_FW_PFVF_CMD_NIQ(rxq));
7929 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7930 V_FW_PFVF_CMD_PMASK(pmask) |
7931 V_FW_PFVF_CMD_NEQ(txq));
7932 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7933 V_FW_PFVF_CMD_NVI(vi) |
7934 V_FW_PFVF_CMD_NEXACTF(nexact));
7935 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7936 V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7937 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7938 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7939}
7940
7961int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7962 unsigned int port, unsigned int pf, unsigned int vf,
7963 unsigned int nmac, u8 *mac, u16 *rss_size,
7964 uint8_t *vfvld, uint16_t *vin,
7965 unsigned int portfunc, unsigned int idstype)
7966{
7967 int ret;
7968 struct fw_vi_cmd c;
7969
7970 memset(&c, 0, sizeof(c));
7971 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7972 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7973 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7974 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7975 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7976 V_FW_VI_CMD_FUNC(portfunc));
7977 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7978 c.nmac = nmac - 1;
7979 if(!rss_size)
7980 c.norss_rsssize = F_FW_VI_CMD_NORSS;
7981
7982 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7983 if (ret)
7984 return ret;
7985 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7986
7987 if (mac) {
7988 memcpy(mac, c.mac, sizeof(c.mac));
7989 switch (nmac) {
7990 case 5:
7991 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7992 case 4:
7993 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7994 case 3:
7995 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7996 case 2:
7997 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7998 }
7999 }
8000 if (rss_size)
8001 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
8002 if (vfvld) {
8003 *vfvld = adap->params.viid_smt_extn_support ?
8004 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
8005 G_FW_VIID_VIVLD(ret);
8006 }
8007 if (vin) {
8008 *vin = adap->params.viid_smt_extn_support ?
8009 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
8010 G_FW_VIID_VIN(ret);
8011 }
8012
8013 return ret;
8014}
8015
8031int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
8032 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
8033 u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
8034{
8035 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
8036 vfvld, vin, FW_VI_FUNC_ETH, 0);
8037}
8038
8049int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
8050 unsigned int vf, unsigned int viid)
8051{
8052 struct fw_vi_cmd c;
8053
8054 memset(&c, 0, sizeof(c));
8055 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
8056 F_FW_CMD_REQUEST |
8057 F_FW_CMD_EXEC |
8058 V_FW_VI_CMD_PFN(pf) |
8059 V_FW_VI_CMD_VFN(vf));
8060 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
8061 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
8062
8063 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8064}
8065
8080int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
8081 int mtu, int promisc, int all_multi, int bcast, int vlanex,
8082 bool sleep_ok)
8083{
8084 struct fw_vi_rxmode_cmd c;
8085
8086 /* convert to FW values */
8087 if (mtu < 0)
8088 mtu = M_FW_VI_RXMODE_CMD_MTU;
8089 if (promisc < 0)
8090 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
8091 if (all_multi < 0)
8092 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
8093 if (bcast < 0)
8094 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
8095 if (vlanex < 0)
8096 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
8097
8098 memset(&c, 0, sizeof(c));
8099 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
8100 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8101 V_FW_VI_RXMODE_CMD_VIID(viid));
8102 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
8103 c.mtu_to_vlanexen =
8104 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
8105 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
8106 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
8107 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
8108 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
8109 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8110}
8111
8128int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
8129 const u8 *addr, const u8 *mask, unsigned int vni,
8130 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
8131 bool sleep_ok)
8132{
8133 struct fw_vi_mac_cmd c;
8134 struct fw_vi_mac_vni *p = c.u.exact_vni;
8135 int ret = 0;
8136 u32 val;
8137
8138 memset(&c, 0, sizeof(c));
8139 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8140 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8141 V_FW_VI_MAC_CMD_VIID(viid));
8142 val = V_FW_CMD_LEN16(1) |
8143 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI);
8144 c.freemacs_to_len16 = cpu_to_be32(val);
8145 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8146 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8147 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8148 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
8149
8150 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) |
8151 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) |
8152 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type));
8153 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask));
8154
8155 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8156 if (ret == 0)
8157 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8158 return ret;
8159}
8160
8176int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
8177 const u8 *addr, const u8 *mask, unsigned int idx,
8178 u8 lookup_type, u8 port_id, bool sleep_ok)
8179{
8180 int ret = 0;
8181 struct fw_vi_mac_cmd c;
8182 struct fw_vi_mac_raw *p = &c.u.raw;
8183 u32 val;
8184
8185 memset(&c, 0, sizeof(c));
8186 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8187 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8188 V_FW_VI_MAC_CMD_VIID(viid));
8189 val = V_FW_CMD_LEN16(1) |
8190 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
8191 c.freemacs_to_len16 = cpu_to_be32(val);
8192
8193 /* Specify that this is an inner mac address */
8194 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx));
8195
8196 /* Lookup Type. Outer header: 0, Inner header: 1 */
8197 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
8198 V_DATAPORTNUM(port_id));
8199 /* Lookup mask and port mask */
8200 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
8201 V_DATAPORTNUM(M_DATAPORTNUM));
8202
8203 /* Copy the address and the mask */
8204 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
8205 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
8206
8207 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8208 if (ret == 0) {
8209 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd));
8210 if (ret != idx)
8211 ret = -ENOMEM;
8212 }
8213
8214 return ret;
8215}
8216
8239int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8240 unsigned int viid, bool free, unsigned int naddr,
8241 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8242{
8243 int offset, ret = 0;
8244 struct fw_vi_mac_cmd c;
8245 unsigned int nfilters = 0;
8246 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8247 unsigned int rem = naddr;
8248
8249 if (naddr > max_naddr)
8250 return -EINVAL;
8251
8252 for (offset = 0; offset < naddr ; ) {
8253 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8254 ? rem
8255 : ARRAY_SIZE(c.u.exact));
8256 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8257 u.exact[fw_naddr]), 16);
8258 struct fw_vi_mac_exact *p;
8259 int i;
8260
8261 memset(&c, 0, sizeof(c));
8262 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8263 F_FW_CMD_REQUEST |
8264 F_FW_CMD_WRITE |
8265 V_FW_CMD_EXEC(free) |
8266 V_FW_VI_MAC_CMD_VIID(viid));
8267 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
8268 V_FW_CMD_LEN16(len16));
8269
8270 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8271 p->valid_to_idx =
8272 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8273 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8274 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8275 }
8276
8277 /*
8278 * It's okay if we run out of space in our MAC address arena.
8279 * Some of the addresses we submit may get stored so we need
8280 * to run through the reply to see what the results were ...
8281 */
8282 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8283 if (ret && ret != -FW_ENOMEM)
8284 break;
8285
8286 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8287 u16 index = G_FW_VI_MAC_CMD_IDX(
8288 be16_to_cpu(p->valid_to_idx));
8289
8290 if (idx)
8291 idx[offset+i] = (index >= max_naddr
8292 ? 0xffff
8293 : index);
8294 if (index < max_naddr)
8295 nfilters++;
8296 else if (hash)
8297 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
8298 }
8299
8300 free = false;
8301 offset += fw_naddr;
8302 rem -= fw_naddr;
8303 }
8304
8305 if (ret == 0 || ret == -FW_ENOMEM)
8306 ret = nfilters;
8307 return ret;
8308}
8309
8321int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
8322 int idx, bool sleep_ok)
8323{
8324 struct fw_vi_mac_exact *p;
8325 struct fw_vi_mac_cmd c;
8326 u8 addr[] = {0,0,0,0,0,0};
8327 int ret = 0;
8328 u32 exact;
8329
8330 memset(&c, 0, sizeof(c));
8331 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8332 F_FW_CMD_REQUEST |
8333 F_FW_CMD_WRITE |
8334 V_FW_CMD_EXEC(0) |
8335 V_FW_VI_MAC_CMD_VIID(viid));
8336 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC);
8337 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8338 exact |
8339 V_FW_CMD_LEN16(1));
8340 p = c.u.exact;
8341 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8342 V_FW_VI_MAC_CMD_IDX(idx));
8343 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8344
8345 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8346 return ret;
8347}
8348
8364int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
8365 const u8 *addr, const u8 *mask, unsigned int idx,
8366 u8 lookup_type, u8 port_id, bool sleep_ok)
8367{
8368 struct fw_vi_mac_cmd c;
8369 struct fw_vi_mac_raw *p = &c.u.raw;
8370 u32 raw;
8371
8372 memset(&c, 0, sizeof(c));
8373 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8374 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8375 V_FW_CMD_EXEC(0) |
8376 V_FW_VI_MAC_CMD_VIID(viid));
8377 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
8378 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8379 raw |
8380 V_FW_CMD_LEN16(1));
8381
8382 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) |
8383 FW_VI_MAC_ID_BASED_FREE);
8384
8385 /* Lookup Type. Outer header: 0, Inner header: 1 */
8386 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
8387 V_DATAPORTNUM(port_id));
8388 /* Lookup mask and port mask */
8389 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
8390 V_DATAPORTNUM(M_DATAPORTNUM));
8391
8392 /* Copy the address and the mask */
8393 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
8394 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
8395
8396 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8397}
8398
8412int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8413 unsigned int viid, unsigned int naddr,
8414 const u8 **addr, bool sleep_ok)
8415{
8416 int offset, ret = 0;
8417 struct fw_vi_mac_cmd c;
8418 unsigned int nfilters = 0;
8419 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8420 unsigned int rem = naddr;
8421
8422 if (naddr > max_naddr)
8423 return -EINVAL;
8424
8425 for (offset = 0; offset < (int)naddr ; ) {
8426 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8427 ? rem
8428 : ARRAY_SIZE(c.u.exact));
8429 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8430 u.exact[fw_naddr]), 16);
8431 struct fw_vi_mac_exact *p;
8432 int i;
8433
8434 memset(&c, 0, sizeof(c));
8435 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8436 F_FW_CMD_REQUEST |
8437 F_FW_CMD_WRITE |
8438 V_FW_CMD_EXEC(0) |
8439 V_FW_VI_MAC_CMD_VIID(viid));
8440 c.freemacs_to_len16 =
8441 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8442 V_FW_CMD_LEN16(len16));
8443
8444 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8445 p->valid_to_idx = cpu_to_be16(
8446 F_FW_VI_MAC_CMD_VALID |
8447 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
8448 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8449 }
8450
8451 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8452 if (ret)
8453 break;
8454
8455 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8456 u16 index = G_FW_VI_MAC_CMD_IDX(
8457 be16_to_cpu(p->valid_to_idx));
8458
8459 if (index < max_naddr)
8460 nfilters++;
8461 }
8462
8463 offset += fw_naddr;
8464 rem -= fw_naddr;
8465 }
8466
8467 if (ret == 0)
8468 ret = nfilters;
8469 return ret;
8470}
8471
8494int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8495 int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
8496{
8497 int ret, mode;
8498 struct fw_vi_mac_cmd c;
8499 struct fw_vi_mac_exact *p = c.u.exact;
8500 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
8501
8502 if (idx < 0) /* new allocation */
8503 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8504 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8505
8506 memset(&c, 0, sizeof(c));
8507 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8508 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8509 V_FW_VI_MAC_CMD_VIID(viid));
8510 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
8511 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8512 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
8513 V_FW_VI_MAC_CMD_IDX(idx));
8514 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8515
8516 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8517 if (ret == 0) {
8518 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8519 if (ret >= max_mac_addr)
8520 ret = -ENOMEM;
8521 if (smt_idx) {
8522 if (adap->params.viid_smt_extn_support)
8523 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
8524 else {
8525 if (chip_id(adap) <= CHELSIO_T5)
8526 *smt_idx = (viid & M_FW_VIID_VIN) << 1;
8527 else
8528 *smt_idx = viid & M_FW_VIID_VIN;
8529 }
8530 }
8531 }
8532 return ret;
8533}
8534
8546int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8547 bool ucast, u64 vec, bool sleep_ok)
8548{
8549 struct fw_vi_mac_cmd c;
8550 u32 val;
8551
8552 memset(&c, 0, sizeof(c));
8553 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8554 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8555 V_FW_VI_ENABLE_CMD_VIID(viid));
8556 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
8557 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
8558 c.freemacs_to_len16 = cpu_to_be32(val);
8559 c.u.hash.hashvec = cpu_to_be64(vec);
8560 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8561}
8562
8575int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8576 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8577{
8578 struct fw_vi_enable_cmd c;
8579
8580 memset(&c, 0, sizeof(c));
8581 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8582 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8583 V_FW_VI_ENABLE_CMD_VIID(viid));
8584 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
8585 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
8586 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
8587 FW_LEN16(c));
8588 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8589}
8590
8602int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8603 bool rx_en, bool tx_en)
8604{
8605 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8606}
8607
8617int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8618 unsigned int nblinks)
8619{
8620 struct fw_vi_enable_cmd c;
8621
8622 memset(&c, 0, sizeof(c));
8623 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8624 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8625 V_FW_VI_ENABLE_CMD_VIID(viid));
8626 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
8627 c.blinkdur = cpu_to_be16(nblinks);
8628 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8629}
8630
8646int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8647 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8648 unsigned int fl0id, unsigned int fl1id)
8649{
8650 struct fw_iq_cmd c;
8651
8652 memset(&c, 0, sizeof(c));
8653 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8654 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8655 V_FW_IQ_CMD_VFN(vf));
8656 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
8657 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8658 c.iqid = cpu_to_be16(iqid);
8659 c.fl0id = cpu_to_be16(fl0id);
8660 c.fl1id = cpu_to_be16(fl1id);
8661 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8662}
8663
8677int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8678 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8679 unsigned int fl0id, unsigned int fl1id)
8680{
8681 struct fw_iq_cmd c;
8682
8683 memset(&c, 0, sizeof(c));
8684 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8685 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8686 V_FW_IQ_CMD_VFN(vf));
8687 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
8688 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8689 c.iqid = cpu_to_be16(iqid);
8690 c.fl0id = cpu_to_be16(fl0id);
8691 c.fl1id = cpu_to_be16(fl1id);
8692 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8693}
8694
8706int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8707 unsigned int vf, unsigned int eqid)
8708{
8709 struct fw_eq_eth_cmd c;
8710
8711 memset(&c, 0, sizeof(c));
8712 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8713 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8714 V_FW_EQ_ETH_CMD_PFN(pf) |
8715 V_FW_EQ_ETH_CMD_VFN(vf));
8716 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c));
8717 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8718 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8719}
8720
8731int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8732 unsigned int vf, unsigned int eqid)
8733{
8734 struct fw_eq_eth_cmd c;
8735
8736 memset(&c, 0, sizeof(c));
8737 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8738 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8739 V_FW_EQ_ETH_CMD_PFN(pf) |
8740 V_FW_EQ_ETH_CMD_VFN(vf));
8741 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
8742 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8743 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8744}
8745
8756int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8757 unsigned int vf, unsigned int eqid)
8758{
8759 struct fw_eq_ctrl_cmd c;
8760
8761 memset(&c, 0, sizeof(c));
8762 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
8763 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8764 V_FW_EQ_CTRL_CMD_PFN(pf) |
8765 V_FW_EQ_CTRL_CMD_VFN(vf));
8766 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
8767 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
8768 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8769}
8770
8781int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8782 unsigned int vf, unsigned int eqid)
8783{
8784 struct fw_eq_ofld_cmd c;
8785
8786 memset(&c, 0, sizeof(c));
8787 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
8788 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8789 V_FW_EQ_OFLD_CMD_PFN(pf) |
8790 V_FW_EQ_OFLD_CMD_VFN(vf));
8791 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
8792 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
8793 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8794}
8795
8802const char *t4_link_down_rc_str(unsigned char link_down_rc)
8803{
8804 static const char *reason[] = {
8805 "Link Down",
8806 "Remote Fault",
8807 "Auto-negotiation Failure",
8808 "Reserved3",
8809 "Insufficient Airflow",
8810 "Unable To Determine Reason",
8811 "No RX Signal Detected",
8812 "Reserved7",
8813 };
8814
8815 if (link_down_rc >= ARRAY_SIZE(reason))
8816 return "Bad Reason Code";
8817
8818 return reason[link_down_rc];
8819}
8820
8821/*
8822 * Return the highest speed set in the port capabilities, in Mb/s.
8823 */
8824unsigned int fwcap_to_speed(uint32_t caps)
8825{
8826 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8827 do { \
8828 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8829 return __speed; \
8830 } while (0)
8831
8832 TEST_SPEED_RETURN(400G, 400000);
8833 TEST_SPEED_RETURN(200G, 200000);
8834 TEST_SPEED_RETURN(100G, 100000);
8835 TEST_SPEED_RETURN(50G, 50000);
8836 TEST_SPEED_RETURN(40G, 40000);
8837 TEST_SPEED_RETURN(25G, 25000);
8838 TEST_SPEED_RETURN(10G, 10000);
8839 TEST_SPEED_RETURN(1G, 1000);
8840 TEST_SPEED_RETURN(100M, 100);
8841
8842 #undef TEST_SPEED_RETURN
8843
8844 return 0;
8845}
8846
8847/*
8848 * Return the port capabilities bit for the given speed, which is in Mb/s.
8849 */
8850uint32_t speed_to_fwcap(unsigned int speed)
8851{
8852 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8853 do { \
8854 if (speed == __speed) \
8855 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8856 } while (0)
8857
8858 TEST_SPEED_RETURN(400G, 400000);
8859 TEST_SPEED_RETURN(200G, 200000);
8860 TEST_SPEED_RETURN(100G, 100000);
8861 TEST_SPEED_RETURN(50G, 50000);
8862 TEST_SPEED_RETURN(40G, 40000);
8863 TEST_SPEED_RETURN(25G, 25000);
8864 TEST_SPEED_RETURN(10G, 10000);
8865 TEST_SPEED_RETURN(1G, 1000);
8866 TEST_SPEED_RETURN(100M, 100);
8867
8868 #undef TEST_SPEED_RETURN
8869
8870 return 0;
8871}
8872
8873/*
8874 * Return the port capabilities bit for the highest speed in the capabilities.
8875 */
8876uint32_t fwcap_top_speed(uint32_t caps)
8877{
8878 #define TEST_SPEED_RETURN(__caps_speed) \
8879 do { \
8880 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8881 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8882 } while (0)
8883
8884 TEST_SPEED_RETURN(400G);
8885 TEST_SPEED_RETURN(200G);
8886 TEST_SPEED_RETURN(100G);
8887 TEST_SPEED_RETURN(50G);
8888 TEST_SPEED_RETURN(40G);
8889 TEST_SPEED_RETURN(25G);
8890 TEST_SPEED_RETURN(10G);
8891 TEST_SPEED_RETURN(1G);
8892 TEST_SPEED_RETURN(100M);
8893
8894 #undef TEST_SPEED_RETURN
8895
8896 return 0;
8897}
8898
8906static uint32_t lstatus_to_fwcap(u32 lstatus)
8907{
8908 uint32_t linkattr = 0;
8909
8910 /*
8911 * Unfortunately the format of the Link Status in the old
8912 * 16-bit Port Information message isn't the same as the
8913 * 16-bit Port Capabilities bitfield used everywhere else ...
8914 */
8915 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
8916 linkattr |= FW_PORT_CAP32_FC_RX;
8917 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
8918 linkattr |= FW_PORT_CAP32_FC_TX;
8919 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
8920 linkattr |= FW_PORT_CAP32_SPEED_100M;
8921 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
8922 linkattr |= FW_PORT_CAP32_SPEED_1G;
8923 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
8924 linkattr |= FW_PORT_CAP32_SPEED_10G;
8925 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
8926 linkattr |= FW_PORT_CAP32_SPEED_25G;
8927 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
8928 linkattr |= FW_PORT_CAP32_SPEED_40G;
8929 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
8930 linkattr |= FW_PORT_CAP32_SPEED_100G;
8931
8932 return linkattr;
8933}
8934
8935/*
8936 * Updates all fields owned by the common code in port_info and link_config
8937 * based on information provided by the firmware. Does not touch any
8938 * requested_* field.
8939 */
8940static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
8941 enum fw_port_action action, bool *mod_changed, bool *link_changed)
8942{
8943 struct link_config old_lc, *lc = &pi->link_cfg;
8944 unsigned char fc;
8945 u32 stat, linkattr;
8946 int old_ptype, old_mtype;
8947
8948 old_ptype = pi->port_type;
8949 old_mtype = pi->mod_type;
8950 old_lc = *lc;
8951 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8952 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
8953
8954 pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
8955 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
8956 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
8957 G_FW_PORT_CMD_MDIOADDR(stat) : -1;
8958
8959 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
8960 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
8961 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
8962 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
8963 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
8964
8965 linkattr = lstatus_to_fwcap(stat);
8966 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
8967 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
8968
8969 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
8970 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
8971 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
8972 G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
8973
8974 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32);
8975 lc->acaps = be32_to_cpu(p->u.info32.acaps32);
8976 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32);
8977 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
8978 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
8979
8980 linkattr = be32_to_cpu(p->u.info32.linkattr32);
8981 } else {
8982 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
8983 return;
8984 }
8985
8986 lc->speed = fwcap_to_speed(linkattr);
8987 lc->fec = fwcap_to_fec(linkattr, true);
8988
8989 fc = 0;
8990 if (linkattr & FW_PORT_CAP32_FC_RX)
8991 fc |= PAUSE_RX;
8992 if (linkattr & FW_PORT_CAP32_FC_TX)
8993 fc |= PAUSE_TX;
8994 lc->fc = fc;
8995
8996 if (mod_changed != NULL)
8997 *mod_changed = false;
8998 if (link_changed != NULL)
8999 *link_changed = false;
9000 if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
9001 old_lc.pcaps != lc->pcaps) {
9002 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE)
9003 lc->fec_hint = fwcap_to_fec(lc->acaps, true);
9004 if (mod_changed != NULL)
9005 *mod_changed = true;
9006 }
9007 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
9008 old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
9009 if (link_changed != NULL)
9010 *link_changed = true;
9011 }
9012}
9013
9022 int t4_update_port_info(struct port_info *pi)
9023 {
9024 struct adapter *sc = pi->adapter;
9025 struct fw_port_cmd cmd;
9026 enum fw_port_action action;
9027 int ret;
9028
9029 memset(&cmd, 0, sizeof(cmd));
9030 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
9031 F_FW_CMD_REQUEST | F_FW_CMD_READ |
9032 V_FW_PORT_CMD_PORTID(pi->tx_chan));
9033 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
9034 FW_PORT_ACTION_GET_PORT_INFO;
9035 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
9036 FW_LEN16(cmd));
9037 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
9038 if (ret)
9039 return ret;
9040
9041 handle_port_info(pi, &cmd, action, NULL, NULL);
9042 return 0;
9043}
9044
9052int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
9053{
9054 u8 opcode = *(const u8 *)rpl;
9055 const struct fw_port_cmd *p = (const void *)rpl;
9056 enum fw_port_action action =
9057 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
9058 bool mod_changed, link_changed;
9059
9060 if (opcode == FW_PORT_CMD &&
9061 (action == FW_PORT_ACTION_GET_PORT_INFO ||
9062 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
9063 /* link/module state change message */
9064 int i;
9065 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
9066 struct port_info *pi = NULL;
9067
9068 for_each_port(adap, i) {
9069 pi = adap2pinfo(adap, i);
9070 if (pi->tx_chan == chan)
9071 break;
9072 }
9073
9074 PORT_LOCK(pi);
9075 handle_port_info(pi, p, action, &mod_changed, &link_changed);
9076 PORT_UNLOCK(pi);
9077 if (mod_changed)
9078 t4_os_portmod_changed(pi);
9079 if (link_changed) {
9080 PORT_LOCK(pi);
9081 t4_os_link_changed(pi);
9082 PORT_UNLOCK(pi);
9083 }
9084 } else {
9085 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
9086 return -EINVAL;
9087 }
9088 return 0;
9089}
9090
9099static void get_pci_mode(struct adapter *adapter,
9100 struct pci_params *p)
9101{
9102 u16 val;
9103 u32 pcie_cap;
9104
9105 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
9106 if (pcie_cap) {
9107 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
9108 p->speed = val & PCI_EXP_LNKSTA_CLS;
9109 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
9110 }
9111}
9112
9113struct flash_desc {
9114 u32 vendor_and_model_id;
9115 u32 size_mb;
9116};
9117
9118int t4_get_flash_params(struct adapter *adapter)
9119{
9120 /*
9121 * Table for non-standard supported Flash parts. Note, all Flash
9122 * parts must have 64KB sectors.
9123 */
9124 static struct flash_desc supported_flash[] = {
9125 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
9126 };
9127
9128 int ret;
9129 u32 flashid = 0;
9130 unsigned int part, manufacturer;
9131 unsigned int density, size = 0;
9132
9133
9134 /*
9135 * Issue a Read ID Command to the Flash part. We decode supported
9136 * Flash parts and their sizes from this. There's a newer Query
9137 * Command which can retrieve detailed geometry information but many
9138 * Flash parts don't support it.
9139 */
9140 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
9141 if (!ret)
9142 ret = sf1_read(adapter, 3, 0, 1, &flashid);
9143 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
9144 if (ret < 0)
9145 return ret;
9146
9147 /*
9148 * Check to see if it's one of our non-standard supported Flash parts.
9149 */
9150 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9151 if (supported_flash[part].vendor_and_model_id == flashid) {
9152 adapter->params.sf_size =
9153 supported_flash[part].size_mb;
9154 adapter->params.sf_nsec =
9155 adapter->params.sf_size / SF_SEC_SIZE;
9156 goto found;
9157 }
9158
9159 /*
9160 * Decode Flash part size. The code below looks repetative with
9161 * common encodings, but that's not guaranteed in the JEDEC
9162 * specification for the Read JADEC ID command. The only thing that
9163 * we're guaranteed by the JADEC specification is where the
9164 * Manufacturer ID is in the returned result. After that each
9165 * Manufacturer ~could~ encode things completely differently.
9166 * Note, all Flash parts must have 64KB sectors.
9167 */
9168 manufacturer = flashid & 0xff;
9169 switch (manufacturer) {
9170 case 0x20: /* Micron/Numonix */
9171 /*
9172 * This Density -> Size decoding table is taken from Micron
9173 * Data Sheets.
9174 */
9175 density = (flashid >> 16) & 0xff;
9176 switch (density) {
9177 case 0x14: size = 1 << 20; break; /* 1MB */
9178 case 0x15: size = 1 << 21; break; /* 2MB */
9179 case 0x16: size = 1 << 22; break; /* 4MB */
9180 case 0x17: size = 1 << 23; break; /* 8MB */
9181 case 0x18: size = 1 << 24; break; /* 16MB */
9182 case 0x19: size = 1 << 25; break; /* 32MB */
9183 case 0x20: size = 1 << 26; break; /* 64MB */
9184 case 0x21: size = 1 << 27; break; /* 128MB */
9185 case 0x22: size = 1 << 28; break; /* 256MB */
9186 }
9187 break;
9188
9189 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
9190 /*
9191 * This Density -> Size decoding table is taken from ISSI
9192 * Data Sheets.
9193 */
9194 density = (flashid >> 16) & 0xff;
9195 switch (density) {
9196 case 0x16: size = 1 << 25; break; /* 32MB */
9197 case 0x17: size = 1 << 26; break; /* 64MB */
9198 }
9199 break;
9200
9201 case 0xc2: /* Macronix */
9202 /*
9203 * This Density -> Size decoding table is taken from Macronix
9204 * Data Sheets.
9205 */
9206 density = (flashid >> 16) & 0xff;
9207 switch (density) {
9208 case 0x17: size = 1 << 23; break; /* 8MB */
9209 case 0x18: size = 1 << 24; break; /* 16MB */
9210 }
9211 break;
9212
9213 case 0xef: /* Winbond */
9214 /*
9215 * This Density -> Size decoding table is taken from Winbond
9216 * Data Sheets.
9217 */
9218 density = (flashid >> 16) & 0xff;
9219 switch (density) {
9220 case 0x17: size = 1 << 23; break; /* 8MB */
9221 case 0x18: size = 1 << 24; break; /* 16MB */
9222 }
9223 break;
9224 }
9225
9226 /* If we didn't recognize the FLASH part, that's no real issue: the
9227 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9228 * use a FLASH part which is at least 4MB in size and has 64KB
9229 * sectors. The unrecognized FLASH part is likely to be much larger
9230 * than 4MB, but that's all we really need.
9231 */
9232 if (size == 0) {
9233 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
9234 size = 1 << 22;
9235 }
9236
9237 /*
9238 * Store decoded Flash size and fall through into vetting code.
9239 */
9240 adapter->params.sf_size = size;
9241 adapter->params.sf_nsec = size / SF_SEC_SIZE;
9242
9243 found:
9244 /*
9245 * We should ~probably~ reject adapters with FLASHes which are too
9246 * small but we have some legacy FPGAs with small FLASHes that we'd
9247 * still like to use. So instead we emit a scary message ...
9248 */
9249 if (adapter->params.sf_size < FLASH_MIN_SIZE)
9250 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9251 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
9252
9253 return 0;
9254}
9255
9256static void set_pcie_completion_timeout(struct adapter *adapter,
9257 u8 range)
9258{
9259 u16 val;
9260 u32 pcie_cap;
9261
9262 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
9263 if (pcie_cap) {
9264 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
9265 val &= 0xfff0;
9266 val |= range ;
9267 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
9268 }
9269}
9270
9271const struct chip_params *t4_get_chip_params(int chipid)
9272{
9273 static const struct chip_params chip_params[] = {
9274 {
9275 /* T4 */
9276 .nchan = NCHAN,
9277 .pm_stats_cnt = PM_NSTATS,
9278 .cng_ch_bits_log = 2,
9279 .nsched_cls = 15,
9280 .cim_num_obq = CIM_NUM_OBQ,
9281 .filter_opt_len = FILTER_OPT_LEN,
9282 .mps_rplc_size = 128,
9283 .vfcount = 128,
9284 .sge_fl_db = F_DBPRIO,
9285 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
9286 .rss_nentries = RSS_NENTRIES,
9287 },
9288 {
9289 /* T5 */
9290 .nchan = NCHAN,
9291 .pm_stats_cnt = PM_NSTATS,
9292 .cng_ch_bits_log = 2,
9293 .nsched_cls = 16,
9294 .cim_num_obq = CIM_NUM_OBQ_T5,
9295 .filter_opt_len = T5_FILTER_OPT_LEN,
9296 .mps_rplc_size = 128,
9297 .vfcount = 128,
9298 .sge_fl_db = F_DBPRIO | F_DBTYPE,
9299 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
9300 .rss_nentries = RSS_NENTRIES,
9301 },
9302 {
9303 /* T6 */
9304 .nchan = T6_NCHAN,
9305 .pm_stats_cnt = T6_PM_NSTATS,
9306 .cng_ch_bits_log = 3,
9307 .nsched_cls = 16,
9308 .cim_num_obq = CIM_NUM_OBQ_T5,
9309 .filter_opt_len = T5_FILTER_OPT_LEN,
9310 .mps_rplc_size = 256,
9311 .vfcount = 256,
9312 .sge_fl_db = 0,
9313 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
9314 .rss_nentries = T6_RSS_NENTRIES,
9315 },
9316 };
9317
9318 chipid -= CHELSIO_T4;
9319 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
9320 return NULL;
9321
9322 return &chip_params[chipid];
9323}
9324
9334int t4_prep_adapter(struct adapter *adapter, u32 *buf)
9335{
9336 int ret;
9337 uint16_t device_id;
9338 uint32_t pl_rev;
9339
9340 get_pci_mode(adapter, &adapter->params.pci);
9341
9342 pl_rev = t4_read_reg(adapter, A_PL_REV);
9343 adapter->params.chipid = G_CHIPID(pl_rev);
9344 adapter->params.rev = G_REV(pl_rev);
9345 if (adapter->params.chipid == 0) {
9346 /* T4 did not have chipid in PL_REV (T5 onwards do) */
9347 adapter->params.chipid = CHELSIO_T4;
9348
9349 /* T4A1 chip is not supported */
9350 if (adapter->params.rev == 1) {
9351 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
9352 return -EINVAL;
9353 }
9354 }
9355
9356 adapter->chip_params = t4_get_chip_params(chip_id(adapter));
9357 if (adapter->chip_params == NULL)
9358 return -EINVAL;
9359
9360 adapter->params.pci.vpd_cap_addr =
9361 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
9362
9363 ret = t4_get_flash_params(adapter);
9364 if (ret < 0)
9365 return ret;
9366
9367 /* Cards with real ASICs have the chipid in the PCIe device id */
9368 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
9369 if (device_id >> 12 == chip_id(adapter))
9370 adapter->params.cim_la_size = CIMLA_SIZE;
9371 else {
9372 /* FPGA */
9373 adapter->params.fpga = 1;
9374 adapter->params.cim_la_size = 2 * CIMLA_SIZE;
9375 }
9376
9377 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
9378 if (ret < 0)
9379 return ret;
9380
9381 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9382
9383 /*
9384 * Default port and clock for debugging in case we can't reach FW.
9385 */
9386 adapter->params.nports = 1;
9387 adapter->params.portvec = 1;
9388 adapter->params.vpd.cclk = 50000;
9389
9390 /* Set pci completion timeout value to 4 seconds. */
9391 set_pcie_completion_timeout(adapter, 0xd);
9392 return 0;
9393}
9394
9407int t4_shutdown_adapter(struct adapter *adapter)
9408{
9409 int port;
9410 const bool bt = adapter->bt_map != 0;
9411
9412 t4_intr_disable(adapter);
9413 if (bt)
9414 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000);
9415 for_each_port(adapter, port) {
9416 u32 a_port_cfg = is_t4(adapter) ?
9417 PORT_REG(port, A_XGMAC_PORT_CFG) :
9418 T5_PORT_REG(port, A_MAC_PORT_CFG);
9419
9420 t4_write_reg(adapter, a_port_cfg,
9421 t4_read_reg(adapter, a_port_cfg)
9422 & ~V_SIGNAL_DET(1));
9423 if (!bt) {
9424 u32 hss_cfg0 = is_t4(adapter) ?
9425 PORT_REG(port, A_XGMAC_PORT_HSS_CFG0) :
9426 T5_PORT_REG(port, A_MAC_PORT_HSS_CFG0);
9427 t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB |
9428 F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA,
9429 F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB |
9430 F_HSSPLLBYPA);
9431 }
9432 }
9433 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
9434
9435 return 0;
9436}
9437
9464int t4_bar2_sge_qregs(struct adapter *adapter,
9465 unsigned int qid,
9466 enum t4_bar2_qtype qtype,
9467 int user,
9468 u64 *pbar2_qoffset,
9469 unsigned int *pbar2_qid)
9470{
9471 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9472 u64 bar2_page_offset, bar2_qoffset;
9473 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9474
9475 /* T4 doesn't support BAR2 SGE Queue registers for kernel
9476 * mode queues.
9477 */
9478 if (!user && is_t4(adapter))
9479 return -EINVAL;
9480
9481 /* Get our SGE Page Size parameters.
9482 */
9483 page_shift = adapter->params.sge.page_shift;
9484 page_size = 1 << page_shift;
9485
9486 /* Get the right Queues per Page parameters for our Queue.
9487 */
9488 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9489 ? adapter->params.sge.eq_s_qpp
9490 : adapter->params.sge.iq_s_qpp);
9491 qpp_mask = (1 << qpp_shift) - 1;
9492
9493 /* Calculate the basics of the BAR2 SGE Queue register area:
9494 * o The BAR2 page the Queue registers will be in.
9495 * o The BAR2 Queue ID.
9496 * o The BAR2 Queue ID Offset into the BAR2 page.
9497 */
9498 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9499 bar2_qid = qid & qpp_mask;
9500 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9501
9502 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9503 * hardware will infer the Absolute Queue ID simply from the writes to
9504 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9505 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9506 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9507 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9508 * from the BAR2 Page and BAR2 Queue ID.
9509 *
9510 * One important censequence of this is that some BAR2 SGE registers
9511 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9512 * there. But other registers synthesize the SGE Queue ID purely
9513 * from the writes to the registers -- the Write Combined Doorbell
9514 * Buffer is a good example. These BAR2 SGE Registers are only
9515 * available for those BAR2 SGE Register areas where the SGE Absolute
9516 * Queue ID can be inferred from simple writes.
9517 */
9518 bar2_qoffset = bar2_page_offset;
9519 bar2_qinferred = (bar2_qid_offset < page_size);
9520 if (bar2_qinferred) {
9521 bar2_qoffset += bar2_qid_offset;
9522 bar2_qid = 0;
9523 }
9524
9525 *pbar2_qoffset = bar2_qoffset;
9526 *pbar2_qid = bar2_qid;
9527 return 0;
9528}
9529
9538int t4_init_devlog_params(struct adapter *adap, int fw_attach)
9539{
9540 struct devlog_params *dparams = &adap->params.devlog;
9541 u32 pf_dparams;
9542 unsigned int devlog_meminfo;
9543 struct fw_devlog_cmd devlog_cmd;
9544 int ret;
9545
9546 /* If we're dealing with newer firmware, the Device Log Paramerters
9547 * are stored in a designated register which allows us to access the
9548 * Device Log even if we can't talk to the firmware.
9549 */
9550 pf_dparams =
9551 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
9552 if (pf_dparams) {
9553 unsigned int nentries, nentries128;
9554
9555 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
9556 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
9557
9558 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
9559 nentries = (nentries128 + 1) * 128;
9560 dparams->size = nentries * sizeof(struct fw_devlog_e);
9561
9562 return 0;
9563 }
9564
9565 /*
9566 * For any failing returns ...
9567 */
9568 memset(dparams, 0, sizeof *dparams);
9569
9570 /*
9571 * If we can't talk to the firmware, there's really nothing we can do
9572 * at this point.
9573 */
9574 if (!fw_attach)
9575 return -ENXIO;
9576
9577 /* Otherwise, ask the firmware for it's Device Log Parameters.
9578 */
9579 memset(&devlog_cmd, 0, sizeof devlog_cmd);
9580 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9581 F_FW_CMD_REQUEST | F_FW_CMD_READ);
9582 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9583 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9584 &devlog_cmd);
9585 if (ret)
9586 return ret;
9587
9588 devlog_meminfo =
9589 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9590 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
9591 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
9592 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9593
9594 return 0;
9595}
9596
9603int t4_init_sge_params(struct adapter *adapter)
9604{
9605 u32 r;
9606 struct sge_params *sp = &adapter->params.sge;
9607 unsigned i, tscale = 1;
9608
9609 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
9610 sp->counter_val[0] = G_THRESHOLD_0(r);
9611 sp->counter_val[1] = G_THRESHOLD_1(r);
9612 sp->counter_val[2] = G_THRESHOLD_2(r);
9613 sp->counter_val[3] = G_THRESHOLD_3(r);
9614
9615 if (chip_id(adapter) >= CHELSIO_T6) {
9616 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
9617 tscale = G_TSCALE(r);
9618 if (tscale == 0)
9619 tscale = 1;
9620 else
9621 tscale += 2;
9622 }
9623
9624 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
9625 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
9626 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
9627 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
9628 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
9629 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
9630 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
9631 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
9632 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
9633
9634 r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
9635 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
9636 if (is_t4(adapter))
9637 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
9638 else if (is_t5(adapter))
9639 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
9640 else
9641 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
9642
9643 /* egress queues: log2 of # of doorbells per BAR2 page */
9644 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
9645 r >>= S_QUEUESPERPAGEPF0 +
9646 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9647 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
9648
9649 /* ingress queues: log2 of # of doorbells per BAR2 page */
9650 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
9651 r >>= S_QUEUESPERPAGEPF0 +
9652 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9653 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
9654
9655 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
9656 r >>= S_HOSTPAGESIZEPF0 +
9657 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
9658 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
9659
9660 r = t4_read_reg(adapter, A_SGE_CONTROL);
9661 sp->sge_control = r;
9662 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
9663 sp->fl_pktshift = G_PKTSHIFT(r);
9664 if (chip_id(adapter) <= CHELSIO_T5) {
9665 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9666 X_INGPADBOUNDARY_SHIFT);
9667 } else {
9668 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9669 X_T6_INGPADBOUNDARY_SHIFT);
9670 }
9671 if (is_t4(adapter))
9672 sp->pack_boundary = sp->pad_boundary;
9673 else {
9674 r = t4_read_reg(adapter, A_SGE_CONTROL2);
9675 if (G_INGPACKBOUNDARY(r) == 0)
9676 sp->pack_boundary = 16;
9677 else
9678 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
9679 }
9680 for (i = 0; i < SGE_FLBUF_SIZES; i++)
9681 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
9682 A_SGE_FL_BUFFER_SIZE0 + (4 * i));
9683
9684 return 0;
9685}
9686
9687/* Convert the LE's hardware hash mask to a shorter filter mask. */
9688static inline uint16_t
9689hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode)
9690{
9691 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1};
9692 int i;
9693 uint16_t filter_mask;
9694 uint64_t mask; /* field mask */
9695
9696 filter_mask = 0;
9697 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
9698 if ((filter_mode & (1 << i)) == 0)
9699 continue;
9700 mask = (1 << width[i]) - 1;
9701 if ((hashmask & mask) == mask)
9702 filter_mask |= 1 << i;
9703 hashmask >>= width[i];
9704 }
9705
9706 return (filter_mask);
9707}
9708
9709/*
9710 * Read and cache the adapter's compressed filter mode and ingress config.
9711 */
9712static void
9713read_filter_mode_and_ingress_config(struct adapter *adap)
9714{
9715 int rc;
9716 uint32_t v, param[2], val[2];
9717 struct tp_params *tpp = &adap->params.tp;
9718 uint64_t hash_mask;
9719
9720 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9721 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
9722 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
9723 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9724 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
9725 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
9726 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val);
9727 if (rc == 0) {
9728 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]);
9729 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]);
9730 tpp->vnic_mode = val[1];
9731 } else {
9732 /*
9733 * Old firmware. Read filter mode/mask and ingress config
9734 * straight from the hardware.
9735 */
9736 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true);
9737 tpp->filter_mode = v & 0xffff;
9738
9739 hash_mask = 0;
9740 if (chip_id(adap) > CHELSIO_T4) {
9741 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
9742 hash_mask = v;
9743 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
9744 hash_mask |= (u64)v << 32;
9745 }
9746 tpp->filter_mask = hashmask_to_filtermask(hash_mask,
9747 tpp->filter_mode);
9748
9749 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true);
9750 if (v & F_VNIC)
9751 tpp->vnic_mode = FW_VNIC_MODE_PF_VF;
9752 else
9753 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN;
9754 }
9755
9756 /*
9757 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9758 * shift positions of several elements of the Compressed Filter Tuple
9759 * for this adapter which we need frequently ...
9760 */
9761 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
9762 tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
9763 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
9764 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
9765 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
9766 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
9767 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
9768 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
9769 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
9770 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
9771}
9772
9779int t4_init_tp_params(struct adapter *adap)
9780{
9781 int chan;
9782 u32 tx_len, rx_len, r, v;
9783 struct tp_params *tpp = &adap->params.tp;
9784
9785 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
9786 tpp->tre = G_TIMERRESOLUTION(v);
9787 tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
9788
9789 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9790 for (chan = 0; chan < MAX_NCHAN; chan++)
9791 tpp->tx_modq[chan] = chan;
9792
9793 read_filter_mode_and_ingress_config(adap);
9794
9795 if (chip_id(adap) > CHELSIO_T5) {
9796 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
9797 tpp->rx_pkt_encap = v & F_CRXPKTENC;
9798 } else
9799 tpp->rx_pkt_encap = false;
9800
9801 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE);
9802 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE);
9803
9804 r = t4_read_reg(adap, A_TP_PARA_REG2);
9805 rx_len = min(rx_len, G_MAXRXDATA(r));
9806 tx_len = min(tx_len, G_MAXRXDATA(r));
9807
9808 r = t4_read_reg(adap, A_TP_PARA_REG7);
9809 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r));
9810 rx_len = min(rx_len, v);
9811 tx_len = min(tx_len, v);
9812
9813 tpp->max_tx_pdu = tx_len;
9814 tpp->max_rx_pdu = rx_len;
9815
9816 return 0;
9817}
9818
9828int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9829{
9830 const unsigned int filter_mode = adap->params.tp.filter_mode;
9831 unsigned int sel;
9832 int field_shift;
9833
9834 if ((filter_mode & filter_sel) == 0)
9835 return -1;
9836
9837 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9838 switch (filter_mode & sel) {
9839 case F_FCOE:
9840 field_shift += W_FT_FCOE;
9841 break;
9842 case F_PORT:
9843 field_shift += W_FT_PORT;
9844 break;
9845 case F_VNIC_ID:
9846 field_shift += W_FT_VNIC_ID;
9847 break;
9848 case F_VLAN:
9849 field_shift += W_FT_VLAN;
9850 break;
9851 case F_TOS:
9852 field_shift += W_FT_TOS;
9853 break;
9854 case F_PROTOCOL:
9855 field_shift += W_FT_PROTOCOL;
9856 break;
9857 case F_ETHERTYPE:
9858 field_shift += W_FT_ETHERTYPE;
9859 break;
9860 case F_MACMATCH:
9861 field_shift += W_FT_MACMATCH;
9862 break;
9863 case F_MPSHITTYPE:
9864 field_shift += W_FT_MPSHITTYPE;
9865 break;
9866 case F_FRAGMENTATION:
9867 field_shift += W_FT_FRAGMENTATION;
9868 break;
9869 }
9870 }
9871 return field_shift;
9872}
9873
9874int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
9875{
9876 u8 addr[6];
9877 int ret, i, j;
9878 struct port_info *p = adap2pinfo(adap, port_id);
9879 u32 param, val;
9880 struct vi_info *vi = &p->vi[0];
9881
9882 for (i = 0, j = -1; i <= p->port_id; i++) {
9883 do {
9884 j++;
9885 } while ((adap->params.portvec & (1 << j)) == 0);
9886 }
9887
9888 p->tx_chan = j;
9889 p->mps_bg_map = t4_get_mps_bg_map(adap, j);
9890 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
9891 p->rx_c_chan = t4_get_rx_c_chan(adap, j);
9892 p->lport = j;
9893
9894 if (!(adap->flags & IS_VF) ||
9895 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
9896 t4_update_port_info(p);
9897 }
9898
9899 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
9900 &vi->vfvld, &vi->vin);
9901 if (ret < 0)
9902 return ret;
9903
9904 vi->viid = ret;
9905 t4_os_set_hw_addr(p, addr);
9906
9907 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9908 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
9909 V_FW_PARAMS_PARAM_YZ(vi->viid);
9910 ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
9911 if (ret)
9912 vi->rss_base = 0xffff;
9913 else {
9914 /* MPASS((val >> 16) == rss_size); */
9915 vi->rss_base = val & 0xffff;
9916 }
9917
9918 return 0;
9919}
9920
9931void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9932{
9933 unsigned int i, v;
9934 int cim_num_obq = adap->chip_params->cim_num_obq;
9935
9936 for (i = 0; i < CIM_NUM_IBQ; i++) {
9937 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
9938 V_QUENUMSELECT(i));
9939 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9940 /* value is in 256-byte units */
9941 *base++ = G_CIMQBASE(v) * 256;
9942 *size++ = G_CIMQSIZE(v) * 256;
9943 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
9944 }
9945 for (i = 0; i < cim_num_obq; i++) {
9946 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9947 V_QUENUMSELECT(i));
9948 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9949 /* value is in 256-byte units */
9950 *base++ = G_CIMQBASE(v) * 256;
9951 *size++ = G_CIMQSIZE(v) * 256;
9952 }
9953}
9954
9966int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9967{
9968 int i, err, attempts;
9969 unsigned int addr;
9970 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9971
9972 if (qid > 5 || (n & 3))
9973 return -EINVAL;
9974
9975 addr = qid * nwords;
9976 if (n > nwords)
9977 n = nwords;
9978
9979 /* It might take 3-10ms before the IBQ debug read access is allowed.
9980 * Wait for 1 Sec with a delay of 1 usec.
9981 */
9982 attempts = 1000000;
9983
9984 for (i = 0; i < n; i++, addr++) {
9985 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
9986 F_IBQDBGEN);
9987 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
9988 attempts, 1);
9989 if (err)
9990 return err;
9991 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
9992 }
9993 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
9994 return i;
9995}
9996
10008int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
10009{
10010 int i, err;
10011 unsigned int addr, v, nwords;
10012 int cim_num_obq = adap->chip_params->cim_num_obq;
10013
10014 if ((qid > (cim_num_obq - 1)) || (n & 3))
10015 return -EINVAL;
10016
10017 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
10018 V_QUENUMSELECT(qid));
10019 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
10020
10021 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */
10022 nwords = G_CIMQSIZE(v) * 64; /* same */
10023 if (n > nwords)
10024 n = nwords;
10025
10026 for (i = 0; i < n; i++, addr++) {
10027 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
10028 F_OBQDBGEN);
10029 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
10030 2, 1);
10031 if (err)
10032 return err;
10033 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
10034 }
10035 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
10036 return i;
10037}
10038
10039enum {
10040 CIM_QCTL_BASE = 0,
10041 CIM_CTL_BASE = 0x2000,
10042 CIM_PBT_ADDR_BASE = 0x2800,
10043 CIM_PBT_LRF_BASE = 0x3000,
10044 CIM_PBT_DATA_BASE = 0x3800
10045};
10046
10056int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
10057 unsigned int *valp)
10058{
10059 int ret = 0;
10060
10061 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
10062 return -EBUSY;
10063
10064 for ( ; !ret && n--; addr += 4) {
10065 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
10066 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
10067 0, 5, 2);
10068 if (!ret)
10069 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
10070 }
10071 return ret;
10072}
10073
10083int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
10084 const unsigned int *valp)
10085{
10086 int ret = 0;
10087
10088 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
10089 return -EBUSY;
10090
10091 for ( ; !ret && n--; addr += 4) {
10092 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
10093 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
10094 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
10095 0, 5, 2);
10096 }
10097 return ret;
10098}
10099
10100static int t4_cim_write1(struct adapter *adap, unsigned int addr,
10101 unsigned int val)
10102{
10103 return t4_cim_write(adap, addr, 1, &val);
10104}
10105
10115int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
10116 unsigned int *valp)
10117{
10118 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
10119}
10120
10131int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
10132{
10133 int i, ret;
10134 unsigned int cfg, val, idx;
10135
10136 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
10137 if (ret)
10138 return ret;
10139
10140 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */
10141 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
10142 if (ret)
10143 return ret;
10144 }
10145
10146 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
10147 if (ret)
10148 goto restart;
10149
10150 idx = G_UPDBGLAWRPTR(val);
10151 if (wrptr)
10152 *wrptr = idx;
10153
10154 for (i = 0; i < adap->params.cim_la_size; i++) {
10155 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
10156 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
10157 if (ret)
10158 break;
10159 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
10160 if (ret)
10161 break;
10162 if (val & F_UPDBGLARDEN) {
10163 ret = -ETIMEDOUT;
10164 break;
10165 }
10166 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
10167 if (ret)
10168 break;
10169
10170 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
10171 * identify the 32-bit portion of the full 312-bit data
10172 */
10173 if (is_t6(adap) && (idx & 0xf) >= 9)
10174 idx = (idx & 0xff0) + 0x10;
10175 else
10176 idx++;
10177 /* address can't exceed 0xfff */
10178 idx &= M_UPDBGLARDPTR;
10179 }
10180restart:
10181 if (cfg & F_UPDBGLAEN) {
10182 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
10183 cfg & ~F_UPDBGLARDEN);
10184 if (!ret)
10185 ret = r;
10186 }
10187 return ret;
10188}
10189
10200void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10201{
10202 bool last_incomplete;
10203 unsigned int i, cfg, val, idx;
10204
10205 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
10206 if (cfg & F_DBGLAENABLE) /* freeze LA */
10207 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
10208 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
10209
10210 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
10211 idx = G_DBGLAWPTR(val);
10212 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
10213 if (last_incomplete)
10214 idx = (idx + 1) & M_DBGLARPTR;
10215 if (wrptr)
10216 *wrptr = idx;
10217
10218 val &= 0xffff;
10219 val &= ~V_DBGLARPTR(M_DBGLARPTR);
10220 val |= adap->params.tp.la_mask;
10221
10222 for (i = 0; i < TPLA_SIZE; i++) {
10223 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
10224 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
10225 idx = (idx + 1) & M_DBGLARPTR;
10226 }
10227
10228 /* Wipe out last entry if it isn't valid */
10229 if (last_incomplete)
10230 la_buf[TPLA_SIZE - 1] = ~0ULL;
10231
10232 if (cfg & F_DBGLAENABLE) /* restore running state */
10233 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
10234 cfg | adap->params.tp.la_mask);
10235}
10236
10237/*
10238 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10239 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10240 * state for more than the Warning Threshold then we'll issue a warning about
10241 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10242 * appears to be hung every Warning Repeat second till the situation clears.
10243 * If the situation clears, we'll note that as well.
10244 */
10245#define SGE_IDMA_WARN_THRESH 1
10246#define SGE_IDMA_WARN_REPEAT 300
10247
10255void t4_idma_monitor_init(struct adapter *adapter,
10256 struct sge_idma_monitor_state *idma)
10257{
10258 /* Initialize the state variables for detecting an SGE Ingress DMA
10259 * hang. The SGE has internal counters which count up on each clock
10260 * tick whenever the SGE finds its Ingress DMA State Engines in the
10261 * same state they were on the previous clock tick. The clock used is
10262 * the Core Clock so we have a limit on the maximum "time" they can
10263 * record; typically a very small number of seconds. For instance,
10264 * with a 600MHz Core Clock, we can only count up to a bit more than
10265 * 7s. So we'll synthesize a larger counter in order to not run the
10266 * risk of having the "timers" overflow and give us the flexibility to
10267 * maintain a Hung SGE State Machine of our own which operates across
10268 * a longer time frame.
10269 */
10270 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10271 idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
10272}
10273
10281void t4_idma_monitor(struct adapter *adapter,
10282 struct sge_idma_monitor_state *idma,
10283 int hz, int ticks)
10284{
10285 int i, idma_same_state_cnt[2];
10286
10287 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10288 * are counters inside the SGE which count up on each clock when the
10289 * SGE finds its Ingress DMA State Engines in the same states they
10290 * were in the previous clock. The counters will peg out at
10291 * 0xffffffff without wrapping around so once they pass the 1s
10292 * threshold they'll stay above that till the IDMA state changes.
10293 */
10294 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
10295 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
10296 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10297
10298 for (i = 0; i < 2; i++) {
10299 u32 debug0, debug11;
10300
10301 /* If the Ingress DMA Same State Counter ("timer") is less
10302 * than 1s, then we can reset our synthesized Stall Timer and
10303 * continue. If we have previously emitted warnings about a
10304 * potential stalled Ingress Queue, issue a note indicating
10305 * that the Ingress Queue has resumed forward progress.
10306 */
10307 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10308 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
10309 CH_WARN(adapter, "SGE idma%d, queue %u, "
10310 "resumed after %d seconds\n",
10311 i, idma->idma_qid[i],
10312 idma->idma_stalled[i]/hz);
10313 idma->idma_stalled[i] = 0;
10314 continue;
10315 }
10316
10317 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10318 * domain. The first time we get here it'll be because we
10319 * passed the 1s Threshold; each additional time it'll be
10320 * because the RX Timer Callback is being fired on its regular
10321 * schedule.
10322 *
10323 * If the stall is below our Potential Hung Ingress Queue
10324 * Warning Threshold, continue.
10325 */
10326 if (idma->idma_stalled[i] == 0) {
10327 idma->idma_stalled[i] = hz;
10328 idma->idma_warn[i] = 0;
10329 } else {
10330 idma->idma_stalled[i] += ticks;
10331 idma->idma_warn[i] -= ticks;
10332 }
10333
10334 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
10335 continue;
10336
10337 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10338 */
10339 if (idma->idma_warn[i] > 0)
10340 continue;
10341 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
10342
10343 /* Read and save the SGE IDMA State and Queue ID information.
10344 * We do this every time in case it changes across time ...
10345 * can't be too careful ...
10346 */
10347 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
10348 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10349 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10350
10351 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
10352 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10353 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10354
10355 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
10356 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10357 i, idma->idma_qid[i], idma->idma_state[i],
10358 idma->idma_stalled[i]/hz,
10359 debug0, debug11);
10360 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10361 }
10362}
10363
10372int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf,
10373 unsigned int naddr, u8 *addr)
10374{
10375 struct fw_acl_mac_cmd cmd;
10376
10377 memset(&cmd, 0, sizeof(cmd));
10378 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) |
10379 F_FW_CMD_REQUEST |
10380 F_FW_CMD_WRITE |
10381 V_FW_ACL_MAC_CMD_PFN(pf) |
10382 V_FW_ACL_MAC_CMD_VFN(vf));
10383
10384 /* Note: Do not enable the ACL */
10385 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10386 cmd.nmac = naddr;
10387
10388 switch (pf) {
10389 case 3:
10390 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10391 break;
10392 case 2:
10393 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10394 break;
10395 case 1:
10396 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10397 break;
10398 case 0:
10399 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10400 break;
10401 }
10402
10403 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10404}
10405
10413void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10414{
10415 unsigned int i, v;
10416
10417 for (i = 0; i < NTX_SCHED; i++) {
10418 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
10419 v = t4_read_reg(adap, A_TP_PACE_TABLE);
10420 pace_vals[i] = dack_ticks_to_usec(adap, v);
10421 }
10422}
10423
10433void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
10434 unsigned int *ipg, bool sleep_ok)
10435{
10436 unsigned int v, addr, bpt, cpt;
10437
10438 if (kbps) {
10439 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
10440 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10441 if (sched & 1)
10442 v >>= 16;
10443 bpt = (v >> 8) & 0xff;
10444 cpt = v & 0xff;
10445 if (!cpt)
10446 *kbps = 0; /* scheduler disabled */
10447 else {
10448 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10449 *kbps = (v * bpt) / 125;
10450 }
10451 }
10452 if (ipg) {
10453 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
10454 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10455 if (sched & 1)
10456 v >>= 16;
10457 v &= 0xffff;
10458 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10459 }
10460}
10461
10470int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10471{
10472 int ret, i, n, cfg_addr;
10473 unsigned int addr;
10474 unsigned int flash_cfg_start_sec;
10475 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10476
10477 cfg_addr = t4_flash_cfg_addr(adap);
10478 if (cfg_addr < 0)
10479 return cfg_addr;
10480
10481 addr = cfg_addr;
10482 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10483
10484 if (size > FLASH_CFG_MAX_SIZE) {
10485 CH_ERR(adap, "cfg file too large, max is %u bytes\n",
10486 FLASH_CFG_MAX_SIZE);
10487 return -EFBIG;
10488 }
10489
10490 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10491 sf_sec_size);
10492 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10493 flash_cfg_start_sec + i - 1);
10494 /*
10495 * If size == 0 then we're simply erasing the FLASH sectors associated
10496 * with the on-adapter Firmware Configuration File.
10497 */
10498 if (ret || size == 0)
10499 goto out;
10500
10501 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10502 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10503 if ( (size - i) < SF_PAGE_SIZE)
10504 n = size - i;
10505 else
10506 n = SF_PAGE_SIZE;
10507 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
10508 if (ret)
10509 goto out;
10510
10511 addr += SF_PAGE_SIZE;
10512 cfg_data += SF_PAGE_SIZE;
10513 }
10514
10515out:
10516 if (ret)
10517 CH_ERR(adap, "config file %s failed %d\n",
10518 (size == 0 ? "clear" : "download"), ret);
10519 return ret;
10520}
10521
10528int t5_fw_init_extern_mem(struct adapter *adap)
10529{
10530 u32 params[1], val[1];
10531 int ret;
10532
10533 if (!is_t5(adap))
10534 return 0;
10535
10536 val[0] = 0xff; /* Initialize all MCs */
10537 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10538 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
10539 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
10540 FW_CMD_MAX_TIMEOUT);
10541
10542 return ret;
10543}
10544
10545/* BIOS boot headers */
10546typedef struct pci_expansion_rom_header {
10547 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10548 u8 reserved[22]; /* Reserved per processor Architecture data */
10549 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10550} pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
10551
10552/* Legacy PCI Expansion ROM Header */
10553typedef struct legacy_pci_expansion_rom_header {
10554 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10555 u8 size512; /* Current Image Size in units of 512 bytes */
10556 u8 initentry_point[4];
10557 u8 cksum; /* Checksum computed on the entire Image */
10558 u8 reserved[16]; /* Reserved */
10559 u8 pcir_offset[2]; /* Offset to PCI Data Struture */
10560} legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
10561
10562/* EFI PCI Expansion ROM Header */
10563typedef struct efi_pci_expansion_rom_header {
10564 u8 signature[2]; // ROM signature. The value 0xaa55
10565 u8 initialization_size[2]; /* Units 512. Includes this header */
10566 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10567 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */
10568 u8 efi_machine_type[2]; /* Machine type from EFI image header */
10569 u8 compression_type[2]; /* Compression type. */
10570 /*
10571 * Compression type definition
10572 * 0x0: uncompressed
10573 * 0x1: Compressed
10574 * 0x2-0xFFFF: Reserved
10575 */
10576 u8 reserved[8]; /* Reserved */
10577 u8 efi_image_header_offset[2]; /* Offset to EFI Image */
10578 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10579} efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
10580
10581/* PCI Data Structure Format */
10582typedef struct pcir_data_structure { /* PCI Data Structure */
10583 u8 signature[4]; /* Signature. The string "PCIR" */
10584 u8 vendor_id[2]; /* Vendor Identification */
10585 u8 device_id[2]; /* Device Identification */
10586 u8 vital_product[2]; /* Pointer to Vital Product Data */
10587 u8 length[2]; /* PCIR Data Structure Length */
10588 u8 revision; /* PCIR Data Structure Revision */
10589 u8 class_code[3]; /* Class Code */
10590 u8 image_length[2]; /* Image Length. Multiple of 512B */
10591 u8 code_revision[2]; /* Revision Level of Code/Data */
10592 u8 code_type; /* Code Type. */
10593 /*
10594 * PCI Expansion ROM Code Types
10595 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10596 * 0x01: Open Firmware standard for PCI. FCODE
10597 * 0x02: Hewlett-Packard PA RISC. HP reserved
10598 * 0x03: EFI Image. EFI
10599 * 0x04-0xFF: Reserved.
10600 */
10601 u8 indicator; /* Indicator. Identifies the last image in the ROM */
10602 u8 reserved[2]; /* Reserved */
10603} pcir_data_t; /* PCI__DATA_STRUCTURE */
10604
10605/* BOOT constants */
10606enum {
10607 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10608 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
10609 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
10610 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
10611 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */
10612 VENDOR_ID = 0x1425, /* Vendor ID */
10613 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10614};
10615
10616/*
10617 * modify_device_id - Modifies the device ID of the Boot BIOS image
10618 * @adatper: the device ID to write.
10619 * @boot_data: the boot image to modify.
10620 *
10621 * Write the supplied device ID to the boot BIOS image.
10622 */
10623static void modify_device_id(int device_id, u8 *boot_data)
10624{
10625 legacy_pci_exp_rom_header_t *header;
10626 pcir_data_t *pcir_header;
10627 u32 cur_header = 0;
10628
10629 /*
10630 * Loop through all chained images and change the device ID's
10631 */
10632 while (1) {
10633 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
10634 pcir_header = (pcir_data_t *) &boot_data[cur_header +
10635 le16_to_cpu(*(u16*)header->pcir_offset)];
10636
10637 /*
10638 * Only modify the Device ID if code type is Legacy or HP.
10639 * 0x00: Okay to modify
10640 * 0x01: FCODE. Do not be modify
10641 * 0x03: Okay to modify
10642 * 0x04-0xFF: Do not modify
10643 */
10644 if (pcir_header->code_type == 0x00) {
10645 u8 csum = 0;
10646 int i;
10647
10648 /*
10649 * Modify Device ID to match current adatper
10650 */
10651 *(u16*) pcir_header->device_id = device_id;
10652
10653 /*
10654 * Set checksum temporarily to 0.
10655 * We will recalculate it later.
10656 */
10657 header->cksum = 0x0;
10658
10659 /*
10660 * Calculate and update checksum
10661 */
10662 for (i = 0; i < (header->size512 * 512); i++)
10663 csum += (u8)boot_data[cur_header + i];
10664
10665 /*
10666 * Invert summed value to create the checksum
10667 * Writing new checksum value directly to the boot data
10668 */
10669 boot_data[cur_header + 7] = -csum;
10670
10671 } else if (pcir_header->code_type == 0x03) {
10672
10673 /*
10674 * Modify Device ID to match current adatper
10675 */
10676 *(u16*) pcir_header->device_id = device_id;
10677
10678 }
10679
10680
10681 /*
10682 * Check indicator element to identify if this is the last
10683 * image in the ROM.
10684 */
10685 if (pcir_header->indicator & 0x80)
10686 break;
10687
10688 /*
10689 * Move header pointer up to the next image in the ROM.
10690 */
10691 cur_header += header->size512 * 512;
10692 }
10693}
10694
10695/*
10696 * t4_load_boot - download boot flash
10697 * @adapter: the adapter
10698 * @boot_data: the boot image to write
10699 * @boot_addr: offset in flash to write boot_data
10700 * @size: image size
10701 *
10702 * Write the supplied boot image to the card's serial flash.
10703 * The boot image has the following sections: a 28-byte header and the
10704 * boot image.
10705 */
10706int t4_load_boot(struct adapter *adap, u8 *boot_data,
10707 unsigned int boot_addr, unsigned int size)
10708{
10709 pci_exp_rom_header_t *header;
10710 int pcir_offset ;
10711 pcir_data_t *pcir_header;
10712 int ret, addr;
10713 uint16_t device_id;
10714 unsigned int i;
10715 unsigned int boot_sector = (boot_addr * 1024 );
10716 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10717
10718 /*
10719 * Make sure the boot image does not encroach on the firmware region
10720 */
10721 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10722 CH_ERR(adap, "boot image encroaching on firmware region\n");
10723 return -EFBIG;
10724 }
10725
10726 /*
10727 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10728 * and Boot configuration data sections. These 3 boot sections span
10729 * sectors 0 to 7 in flash and live right before the FW image location.
10730 */
10731 i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
10732 sf_sec_size);
10733 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10734 (boot_sector >> 16) + i - 1);
10735
10736 /*
10737 * If size == 0 then we're simply erasing the FLASH sectors associated
10738 * with the on-adapter option ROM file
10739 */
10740 if (ret || (size == 0))
10741 goto out;
10742
10743 /* Get boot header */
10744 header = (pci_exp_rom_header_t *)boot_data;
10745 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
10746 /* PCIR Data Structure */
10747 pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
10748
10749 /*
10750 * Perform some primitive sanity testing to avoid accidentally
10751 * writing garbage over the boot sectors. We ought to check for
10752 * more but it's not worth it for now ...
10753 */
10754 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10755 CH_ERR(adap, "boot image too small/large\n");
10756 return -EFBIG;
10757 }
10758
10759#ifndef CHELSIO_T4_DIAGS
10760 /*
10761 * Check BOOT ROM header signature
10762 */
10763 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
10764 CH_ERR(adap, "Boot image missing signature\n");
10765 return -EINVAL;
10766 }
10767
10768 /*
10769 * Check PCI header signature
10770 */
10771 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
10772 CH_ERR(adap, "PCI header missing signature\n");
10773 return -EINVAL;
10774 }
10775
10776 /*
10777 * Check Vendor ID matches Chelsio ID
10778 */
10779 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
10780 CH_ERR(adap, "Vendor ID missing signature\n");
10781 return -EINVAL;
10782 }
10783#endif
10784
10785 /*
10786 * Retrieve adapter's device ID
10787 */
10788 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
10789 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10790 device_id = device_id & 0xf0ff;
10791
10792 /*
10793 * Check PCIE Device ID
10794 */
10795 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
10796 /*
10797 * Change the device ID in the Boot BIOS image to match
10798 * the Device ID of the current adapter.
10799 */
10800 modify_device_id(device_id, boot_data);
10801 }
10802
10803 /*
10804 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10805 * we finish copying the rest of the boot image. This will ensure
10806 * that the BIOS boot header will only be written if the boot image
10807 * was written in full.
10808 */
10809 addr = boot_sector;
10810 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10811 addr += SF_PAGE_SIZE;
10812 boot_data += SF_PAGE_SIZE;
10813 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
10814 if (ret)
10815 goto out;
10816 }
10817
10818 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10819 (const u8 *)header, 0);
10820
10821out:
10822 if (ret)
10823 CH_ERR(adap, "boot image download failed, error %d\n", ret);
10824 return ret;
10825}
10826
10827/*
10828 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10829 * @adapter: the adapter
10830 *
10831 * Return the address within the flash where the OptionROM Configuration
10832 * is stored, or an error if the device FLASH is too small to contain
10833 * a OptionROM Configuration.
10834 */
10835static int t4_flash_bootcfg_addr(struct adapter *adapter)
10836{
10837 /*
10838 * If the device FLASH isn't large enough to hold a Firmware
10839 * Configuration File, return an error.
10840 */
10841 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10842 return -ENOSPC;
10843
10844 return FLASH_BOOTCFG_START;
10845}
10846
10847int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
10848{
10849 int ret, i, n, cfg_addr;
10850 unsigned int addr;
10851 unsigned int flash_cfg_start_sec;
10852 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10853
10854 cfg_addr = t4_flash_bootcfg_addr(adap);
10855 if (cfg_addr < 0)
10856 return cfg_addr;
10857
10858 addr = cfg_addr;
10859 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10860
10861 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10862 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
10863 FLASH_BOOTCFG_MAX_SIZE);
10864 return -EFBIG;
10865 }
10866
10867 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
10868 sf_sec_size);
10869 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10870 flash_cfg_start_sec + i - 1);
10871
10872 /*
10873 * If size == 0 then we're simply erasing the FLASH sectors associated
10874 * with the on-adapter OptionROM Configuration File.
10875 */
10876 if (ret || size == 0)
10877 goto out;
10878
10879 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10880 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10881 if ( (size - i) < SF_PAGE_SIZE)
10882 n = size - i;
10883 else
10884 n = SF_PAGE_SIZE;
10885 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
10886 if (ret)
10887 goto out;
10888
10889 addr += SF_PAGE_SIZE;
10890 cfg_data += SF_PAGE_SIZE;
10891 }
10892
10893out:
10894 if (ret)
10895 CH_ERR(adap, "boot config data %s failed %d\n",
10896 (size == 0 ? "clear" : "download"), ret);
10897 return ret;
10898}
10899
10912int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
10913{
10914 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1};
10915 int i, nbits, rc;
10916 uint32_t param, val;
10917 uint16_t fmode, fmask;
10918 const int maxbits = adap->chip_params->filter_opt_len;
10919
10920 if (mode != -1 || mask != -1) {
10921 if (mode != -1) {
10922 fmode = mode;
10923 nbits = 0;
10924 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
10925 if (fmode & (1 << i))
10926 nbits += width[i];
10927 }
10928 if (nbits > maxbits) {
10929 CH_ERR(adap, "optional fields in the filter "
10930 "mode (0x%x) add up to %d bits "
10931 "(must be <= %db). Remove some fields and "
10932 "try again.\n", fmode, nbits, maxbits);
10933 return -E2BIG;
10934 }
10935
10936 /*
10937 * Hardware wants the bits to be maxed out. Keep
10938 * setting them until there's no room for more.
10939 */
10940 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
10941 if (fmode & (1 << i))
10942 continue;
10943 if (nbits + width[i] <= maxbits) {
10944 fmode |= 1 << i;
10945 nbits += width[i];
10946 if (nbits == maxbits)
10947 break;
10948 }
10949 }
10950
10951 fmask = fmode & adap->params.tp.filter_mask;
10952 if (fmask != adap->params.tp.filter_mask) {
10953 CH_WARN(adap,
10954 "filter mask will be changed from 0x%x to "
10955 "0x%x to comply with the filter mode (0x%x).\n",
10956 adap->params.tp.filter_mask, fmask, fmode);
10957 }
10958 } else {
10959 fmode = adap->params.tp.filter_mode;
10960 fmask = mask;
10961 if ((fmode | fmask) != fmode) {
10962 CH_ERR(adap,
10963 "filter mask (0x%x) must be a subset of "
10964 "the filter mode (0x%x).\n", fmask, fmode);
10965 return -EINVAL;
10966 }
10967 }
10968
10969 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10970 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
10971 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
10972 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) |
10973 V_FW_PARAMS_PARAM_FILTER_MASK(fmask);
10974 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param,
10975 &val);
10976 if (rc < 0)
10977 return rc;
10978 }
10979
10980 if (vnic_mode != -1) {
10981 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10982 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
10983 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
10984 val = vnic_mode;
10985 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param,
10986 &val);
10987 if (rc < 0)
10988 return rc;
10989 }
10990
10991 /* Refresh. */
10992 read_filter_mode_and_ingress_config(adap);
10993
10994 return 0;
10995}
10996
11004void t4_clr_port_stats(struct adapter *adap, int idx)
11005{
11006 unsigned int i;
11007 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
11008 u32 port_base_addr;
11009
11010 if (is_t4(adap))
11011 port_base_addr = PORT_BASE(idx);
11012 else
11013 port_base_addr = T5_PORT_BASE(idx);
11014
11015 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
11016 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
11017 t4_write_reg(adap, port_base_addr + i, 0);
11018 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
11019 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
11020 t4_write_reg(adap, port_base_addr + i, 0);
11021 for (i = 0; i < 4; i++)
11022 if (bgmap & (1 << i)) {
11023 t4_write_reg(adap,
11024 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
11025 t4_write_reg(adap,
11026 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
11027 }
11028}
11029
11042int t4_i2c_io(struct adapter *adap, unsigned int mbox,
11043 int port, unsigned int devid,
11044 unsigned int offset, unsigned int len,
11045 u8 *buf, bool write)
11046{
11047 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
11048 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
11049 int ret = 0;
11050
11051 if (len > I2C_PAGE_SIZE)
11052 return -EINVAL;
11053
11054 /* Dont allow reads that spans multiple pages */
11055 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
11056 return -EINVAL;
11057
11058 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
11059 ldst_cmd.op_to_addrspace =
11060 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
11061 F_FW_CMD_REQUEST |
11062 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) |
11063 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C));
11064 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
11065 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
11066 ldst_cmd.u.i2c.did = devid;
11067
11068 while (len > 0) {
11069 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
11070
11071 ldst_cmd.u.i2c.boffset = offset;
11072 ldst_cmd.u.i2c.blen = i2c_len;
11073
11074 if (write)
11075 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len);
11076
11077 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
11078 write ? NULL : &ldst_rpl);
11079 if (ret)
11080 break;
11081
11082 if (!write)
11083 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
11084 offset += i2c_len;
11085 buf += i2c_len;
11086 len -= i2c_len;
11087 }
11088
11089 return ret;
11090}
11091
11092int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
11093 int port, unsigned int devid,
11094 unsigned int offset, unsigned int len,
11095 u8 *buf)
11096{
11097 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false);
11098}
11099
11100int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
11101 int port, unsigned int devid,
11102 unsigned int offset, unsigned int len,
11103 u8 *buf)
11104{
11105 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true);
11106}
11107
11118int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
11119 enum ctxt_type ctype, u32 *data)
11120{
11121 int ret;
11122 struct fw_ldst_cmd c;
11123
11124 if (ctype == CTXT_EGRESS)
11125 ret = FW_LDST_ADDRSPC_SGE_EGRC;
11126 else if (ctype == CTXT_INGRESS)
11127 ret = FW_LDST_ADDRSPC_SGE_INGC;
11128 else if (ctype == CTXT_FLM)
11129 ret = FW_LDST_ADDRSPC_SGE_FLMC;
11130 else
11131 ret = FW_LDST_ADDRSPC_SGE_CONMC;
11132
11133 memset(&c, 0, sizeof(c));
11134 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
11135 F_FW_CMD_REQUEST | F_FW_CMD_READ |
11136 V_FW_LDST_CMD_ADDRSPACE(ret));
11137 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
11138 c.u.idctxt.physid = cpu_to_be32(cid);
11139
11140 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11141 if (ret == 0) {
11142 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
11143 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
11144 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
11145 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
11146 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
11147 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
11148 }
11149 return ret;
11150}
11151
11162int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
11163 u32 *data)
11164{
11165 int i, ret;
11166
11167 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
11168 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
11169 if (!ret)
11170 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
11171 *data++ = t4_read_reg(adap, i);
11172 return ret;
11173}
11174
11175int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
11176 int sleep_ok)
11177{
11178 struct fw_sched_cmd cmd;
11179
11180 memset(&cmd, 0, sizeof(cmd));
11181 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11182 F_FW_CMD_REQUEST |
11183 F_FW_CMD_WRITE);
11184 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11185
11186 cmd.u.config.sc = FW_SCHED_SC_CONFIG;
11187 cmd.u.config.type = type;
11188 cmd.u.config.minmaxen = minmaxen;
11189
11190 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11191 NULL, sleep_ok);
11192}
11193
11194int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
11195 int rateunit, int ratemode, int channel, int cl,
11196 int minrate, int maxrate, int weight, int pktsize,
11197 int burstsize, int sleep_ok)
11198{
11199 struct fw_sched_cmd cmd;
11200
11201 memset(&cmd, 0, sizeof(cmd));
11202 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11203 F_FW_CMD_REQUEST |
11204 F_FW_CMD_WRITE);
11205 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11206
11207 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11208 cmd.u.params.type = type;
11209 cmd.u.params.level = level;
11210 cmd.u.params.mode = mode;
11211 cmd.u.params.ch = channel;
11212 cmd.u.params.cl = cl;
11213 cmd.u.params.unit = rateunit;
11214 cmd.u.params.rate = ratemode;
11215 cmd.u.params.min = cpu_to_be32(minrate);
11216 cmd.u.params.max = cpu_to_be32(maxrate);
11217 cmd.u.params.weight = cpu_to_be16(weight);
11218 cmd.u.params.pktsize = cpu_to_be16(pktsize);
11219 cmd.u.params.burstsize = cpu_to_be16(burstsize);
11220
11221 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11222 NULL, sleep_ok);
11223}
11224
11225int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
11226 unsigned int maxrate, int sleep_ok)
11227{
11228 struct fw_sched_cmd cmd;
11229
11230 memset(&cmd, 0, sizeof(cmd));
11231 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11232 F_FW_CMD_REQUEST |
11233 F_FW_CMD_WRITE);
11234 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11235
11236 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11237 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11238 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
11239 cmd.u.params.ch = channel;
11240 cmd.u.params.rate = ratemode; /* REL or ABS */
11241 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */
11242
11243 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11244 NULL, sleep_ok);
11245}
11246
11247int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
11248 int weight, int sleep_ok)
11249{
11250 struct fw_sched_cmd cmd;
11251
11252 if (weight < 0 || weight > 100)
11253 return -EINVAL;
11254
11255 memset(&cmd, 0, sizeof(cmd));
11256 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11257 F_FW_CMD_REQUEST |
11258 F_FW_CMD_WRITE);
11259 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11260
11261 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11262 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11263 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
11264 cmd.u.params.ch = channel;
11265 cmd.u.params.cl = cl;
11266 cmd.u.params.weight = cpu_to_be16(weight);
11267
11268 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11269 NULL, sleep_ok);
11270}
11271
11272int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
11273 int mode, unsigned int maxrate, int pktsize, int sleep_ok)
11274{
11275 struct fw_sched_cmd cmd;
11276
11277 memset(&cmd, 0, sizeof(cmd));
11278 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11279 F_FW_CMD_REQUEST |
11280 F_FW_CMD_WRITE);
11281 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11282
11283 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11284 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11285 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
11286 cmd.u.params.mode = mode;
11287 cmd.u.params.ch = channel;
11288 cmd.u.params.cl = cl;
11289 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
11290 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
11291 cmd.u.params.max = cpu_to_be32(maxrate);
11292 cmd.u.params.pktsize = cpu_to_be16(pktsize);
11293
11294 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11295 NULL, sleep_ok);
11296}
11297
11298/*
11299 * t4_config_watchdog - configure (enable/disable) a watchdog timer
11300 * @adapter: the adapter
11301 * @mbox: mailbox to use for the FW command
11302 * @pf: the PF owning the queue
11303 * @vf: the VF owning the queue
11304 * @timeout: watchdog timeout in ms
11305 * @action: watchdog timer / action
11306 *
11307 * There are separate watchdog timers for each possible watchdog
11308 * action. Configure one of the watchdog timers by setting a non-zero
11309 * timeout. Disable a watchdog timer by using a timeout of zero.
11310 */
11311int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
11312 unsigned int pf, unsigned int vf,
11313 unsigned int timeout, unsigned int action)
11314{
11315 struct fw_watchdog_cmd wdog;
11316 unsigned int ticks;
11317
11318 /*
11319 * The watchdog command expects a timeout in units of 10ms so we need
11320 * to convert it here (via rounding) and force a minimum of one 10ms
11321 * "tick" if the timeout is non-zero but the conversion results in 0
11322 * ticks.
11323 */
11324 ticks = (timeout + 5)/10;
11325 if (timeout && !ticks)
11326 ticks = 1;
11327
11328 memset(&wdog, 0, sizeof wdog);
11329 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
11330 F_FW_CMD_REQUEST |
11331 F_FW_CMD_WRITE |
11332 V_FW_PARAMS_CMD_PFN(pf) |
11333 V_FW_PARAMS_CMD_VFN(vf));
11334 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
11335 wdog.timeout = cpu_to_be32(ticks);
11336 wdog.action = cpu_to_be32(action);
11337
11338 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
11339}
11340
11341int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
11342{
11343 struct fw_devlog_cmd devlog_cmd;
11344 int ret;
11345
11346 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
11347 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11348 F_FW_CMD_REQUEST | F_FW_CMD_READ);
11349 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11350 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
11351 sizeof(devlog_cmd), &devlog_cmd);
11352 if (ret)
11353 return ret;
11354
11355 *level = devlog_cmd.level;
11356 return 0;
11357}
11358
11359int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
11360{
11361 struct fw_devlog_cmd devlog_cmd;
11362
11363 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
11364 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11365 F_FW_CMD_REQUEST |
11366 F_FW_CMD_WRITE);
11367 devlog_cmd.level = level;
11368 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11369 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
11370 sizeof(devlog_cmd), &devlog_cmd);
11371}
11372
11373int t4_configure_add_smac(struct adapter *adap)
11374{
11375 unsigned int param, val;
11376 int ret = 0;
11377
11378 adap->params.smac_add_support = 0;
11379 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11380 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC));
11381 /* Query FW to check if FW supports adding source mac address
11382 * to TCAM feature or not.
11383 * If FW returns 1, driver can use this feature and driver need to send
11384 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to
11385 * enable adding smac to TCAM.
11386 */
11387 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
11388 if (ret)
11389 return ret;
11390
11391 if (val == 1) {
11392 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
11393 &param, &val);
11394 if (!ret)
11395 /* Firmware allows adding explicit TCAM entries.
11396 * Save this internally.
11397 */
11398 adap->params.smac_add_support = 1;
11399 }
11400
11401 return ret;
11402}
11403
11404int t4_configure_ringbb(struct adapter *adap)
11405{
11406 unsigned int param, val;
11407 int ret = 0;
11408
11409 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11410 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE));
11411 /* Query FW to check if FW supports ring switch feature or not.
11412 * If FW returns 1, driver can use this feature and driver need to send
11413 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to
11414 * enable the ring backbone configuration.
11415 */
11416 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
11417 if (ret < 0) {
11418 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n",
11419 ret);
11420 goto out;
11421 }
11422
11423 if (val != 1) {
11424 CH_ERR(adap, "FW doesnot support ringbackbone features\n");
11425 goto out;
11426 }
11427
11428 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
11429 if (ret < 0) {
11430 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n",
11431 ret);
11432 goto out;
11433 }
11434
11435out:
11436 return ret;
11437}
11438
11439/*
11440 * t4_set_vlan_acl - Set a VLAN id for the specified VF
11441 * @adapter: the adapter
11442 * @mbox: mailbox to use for the FW command
11443 * @vf: one of the VFs instantiated by the specified PF
11444 * @vlan: The vlanid to be set
11445 *
11446 */
11447int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
11448 u16 vlan)
11449{
11450 struct fw_acl_vlan_cmd vlan_cmd;
11451 unsigned int enable;
11452
11453 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0);
11454 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
11455 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) |
11456 F_FW_CMD_REQUEST |
11457 F_FW_CMD_WRITE |
11458 F_FW_CMD_EXEC |
11459 V_FW_ACL_VLAN_CMD_PFN(adap->pf) |
11460 V_FW_ACL_VLAN_CMD_VFN(vf));
11461 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
11462 /* Drop all packets that donot match vlan id */
11463 vlan_cmd.dropnovlan_fm = (enable
11464 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN |
11465 F_FW_ACL_VLAN_CMD_FM)
11466 : 0);
11467 if (enable != 0) {
11468 vlan_cmd.nvlan = 1;
11469 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
11470 }
11471
11472 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
11473}
11474
11490int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
11491 const u8 *addr, bool smac)
11492{
11493 int ret;
11494 struct fw_vi_mac_cmd c;
11495 struct fw_vi_mac_exact *p = c.u.exact;
11496 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
11497
11498 memset(&c, 0, sizeof(c));
11499 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
11500 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
11501 V_FW_VI_MAC_CMD_VIID(viid));
11502 c.freemacs_to_len16 = cpu_to_be32(
11503 V_FW_CMD_LEN16(1) |
11504 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
11505
11506 memcpy(p->macaddr, addr, sizeof(p->macaddr));
11507 p->valid_to_idx = cpu_to_be16(
11508 F_FW_VI_MAC_CMD_VALID |
11509 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
11510
11511 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11512 if (ret == 0) {
11513 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
11514 if (ret < max_mac_addr)
11515 return -ENOMEM;
11516 }
11517
11518 return ret;
11519}
11520
11539int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
11540 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac)
11541{
11542 int ret, mode;
11543 struct fw_vi_mac_cmd c;
11544 struct fw_vi_mac_exact *p = c.u.exact;
11545 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
11546
11547 if (idx < 0) /* new allocation */
11548 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
11549 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
11550
11551 memset(&c, 0, sizeof(c));
11552 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
11553 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
11554 V_FW_VI_MAC_CMD_VIID(viid));
11555 c.freemacs_to_len16 = cpu_to_be32(
11556 V_FW_CMD_LEN16(1) |
11557 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
11558 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
11559 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
11560 V_FW_VI_MAC_CMD_IDX(idx));
11561 memcpy(p->macaddr, addr, sizeof(p->macaddr));
11562
11563 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11564 if (ret == 0) {
11565 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
11566 if (ret >= max_mac_addr)
11567 return -ENOMEM;
11568 if (smt_idx) {
11569 /* Does fw supports returning smt_idx? */
11570 if (adap->params.viid_smt_extn_support)
11571 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
11572 else {
11573 /* In T4/T5, SMT contains 256 SMAC entries
11574 * organized in 128 rows of 2 entries each.
11575 * In T6, SMT contains 256 SMAC entries in
11576 * 256 rows.
11577 */
11578 if (chip_id(adap) <= CHELSIO_T5)
11579 *smt_idx = ((viid & M_FW_VIID_VIN) << 1);
11580 else
11581 *smt_idx = (viid & M_FW_VIID_VIN);
11582 }
11583 }
11584 }
11585
11586 return ret;
11587}
t4_os_pci_read_cfg4
static void t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
Definition: adapter.h:1180
PORT_LOCK
#define PORT_LOCK(pi)
Definition: adapter.h:1025
t4_read_reg
static uint32_t t4_read_reg(struct adapter *sc, uint32_t reg)
Definition: adapter.h:1104
CH_DUMP_MBOX
static void CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, const char *msg, const __be64 *const p, const bool err)
Definition: adapter.h:1229
t4_os_portmod_changed
void t4_os_portmod_changed(struct port_info *)
Definition: t4_main.c:12104
adap2pinfo
static struct port_info * adap2pinfo(struct adapter *sc, int idx)
Definition: adapter.h:1196
tag
void * tag
Definition: adapter.h:2
res
struct resource * res
Definition: adapter.h:0
rxq
struct sge_rxq * rxq
Definition: adapter.h:3
PORT_UNLOCK
#define PORT_UNLOCK(pi)
Definition: adapter.h:1026
t4_write_reg64
static void t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
Definition: adapter.h:1134
r
struct mp_ring * r
Definition: adapter.h:3
t4_write_reg
static void t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
Definition: adapter.h:1112
t4_use_ldst
static int t4_use_ldst(struct adapter *sc)
Definition: adapter.h:1218
t4_os_pci_read_cfg2
static void t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
Definition: adapter.h:1163
t4_os_set_hw_addr
static void t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
Definition: adapter.h:1203
ASSERT_SYNCHRONIZED_OP
#define ASSERT_SYNCHRONIZED_OP(sc)
Definition: adapter.h:1020
t4_os_find_pci_capability
int t4_os_find_pci_capability(struct adapter *, int)
Definition: t4_main.c:12070
t4_os_pci_write_cfg4
static void t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
Definition: adapter.h:1188
t4_os_pci_write_cfg2
static void t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
Definition: adapter.h:1172
t4_os_link_changed
void t4_os_link_changed(struct port_info *)
Definition: t4_main.c:12145
FW_OK
@ FW_OK
Definition: adapter.h:159
CHK_MBOX_ACCESS
@ CHK_MBOX_ACCESS
Definition: adapter.h:160
IS_VF
@ IS_VF
Definition: adapter.h:163
t4_os_cim_err
void t4_os_cim_err(struct adapter *)
Definition: t4_main.c:9026
t4_read_reg64
static uint64_t t4_read_reg64(struct adapter *sc, uint32_t reg)
Definition: adapter.h:1120
T4_REGMAP_SIZE
@ T4_REGMAP_SIZE
Definition: common.h:48
T5_REGMAP_SIZE
@ T5_REGMAP_SIZE
Definition: common.h:49
MEM_MC1
@ MEM_MC1
Definition: common.h:52
MEM_MC
@ MEM_MC
Definition: common.h:52
MEM_EDC0
@ MEM_EDC0
Definition: common.h:52
MEM_MC0
@ MEM_MC0
Definition: common.h:52
MEM_EDC1
@ MEM_EDC1
Definition: common.h:52
CHELSIO_T5
#define CHELSIO_T5
Definition: common.h:415
t4_wr_mbox_timeout
static int t4_wr_mbox_timeout(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, int timeout)
Definition: common.h:587
t4_bar2_qtype
t4_bar2_qtype
Definition: common.h:82
T4_BAR2_QTYPE_EGRESS
@ T4_BAR2_QTYPE_EGRESS
Definition: common.h:82
dack_ticks_to_usec
static unsigned int dack_ticks_to_usec(const struct adapter *adap, unsigned int ticks)
Definition: common.h:561
t4_wr_mbox
static int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl)
Definition: common.h:595
is_t6
static int is_t6(struct adapter *adap)
Definition: common.h:532
CHELSIO_T4
#define CHELSIO_T4
Definition: common.h:414
core_ticks_to_us
static unsigned int core_ticks_to_us(const struct adapter *adapter, unsigned int ticks)
Definition: common.h:553
CHELSIO_T6
#define CHELSIO_T6
Definition: common.h:416
t4_fatal_err
void t4_fatal_err(struct adapter *adapter, bool fw_error)
Definition: t4_main.c:3554
chip_id
static int chip_id(struct adapter *adap)
Definition: common.h:512
for_each_port
#define for_each_port(adapter, iter)
Definition: common.h:468
is_t4
static int is_t4(struct adapter *adap)
Definition: common.h:522
FEC_AUTO
@ FEC_AUTO
Definition: common.h:78
FEC_BASER_RS
@ FEC_BASER_RS
Definition: common.h:70
FEC_MODULE
@ FEC_MODULE
Definition: common.h:79
FEC_RS
@ FEC_RS
Definition: common.h:69
FEC_NONE
@ FEC_NONE
Definition: common.h:71
PAUSE_AUTONEG
@ PAUSE_AUTONEG
Definition: common.h:61
PAUSE_TX
@ PAUSE_TX
Definition: common.h:60
PAUSE_RX
@ PAUSE_RX
Definition: common.h:59
core_ticks_per_usec
static unsigned int core_ticks_per_usec(const struct adapter *adap)
Definition: common.h:542
MACADDR_LEN
@ MACADDR_LEN
Definition: common.h:44
ID_LEN
@ ID_LEN
Definition: common.h:41
MAX_NPORTS
@ MAX_NPORTS
Definition: common.h:38
EC_LEN
@ EC_LEN
Definition: common.h:40
PN_LEN
@ PN_LEN
Definition: common.h:42
SERNUM_LEN
@ SERNUM_LEN
Definition: common.h:39
MD_LEN
@ MD_LEN
Definition: common.h:43
dev_state
dev_state
Definition: common.h:56
DEV_STATE_UNINIT
@ DEV_STATE_UNINIT
Definition: common.h:56
DEV_STATE_ERR
@ DEV_STATE_ERR
Definition: common.h:56
DEV_STATE_INIT
@ DEV_STATE_INIT
Definition: common.h:56
is_t5
static int is_t5(struct adapter *adap)
Definition: common.h:527
dev_master
dev_master
Definition: common.h:54
MASTER_MUST
@ MASTER_MUST
Definition: common.h:54
MASTER_CANT
@ MASTER_CANT
Definition: common.h:54
t4_wr_mbox_ns
static int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl)
Definition: common.h:601
region
static const char *const region[]
Definition: cudbg_entity.h:305
ARRAY_SIZE
#define ARRAY_SIZE(_a)
Definition: cudbg_entity.h:106
bool
boolean_t bool
Definition: osdep.h:81
cpu_to_le32
#define cpu_to_le32(x)
Definition: osdep.h:104
__be32
uint32_t __be32
Definition: osdep.h:69
AUTONEG_DISABLE
#define AUTONEG_DISABLE
Definition: osdep.h:116
PCI_VPD_ADDR
#define PCI_VPD_ADDR
Definition: osdep.h:121
AUTONEG_ENABLE
#define AUTONEG_ENABLE
Definition: osdep.h:117
__u32
uint32_t __u32
Definition: osdep.h:65
u64
uint64_t u64
Definition: osdep.h:62
PCI_VPD_ADDR_F
#define PCI_VPD_ADDR_F
Definition: osdep.h:122
be16_to_cpu
#define be16_to_cpu(x)
Definition: osdep.h:106
le32_to_cpu
#define le32_to_cpu(x)
Definition: osdep.h:101
strstrip
static char * strstrip(char *s)
Definition: osdep.h:144
PCI_VPD_DATA
#define PCI_VPD_DATA
Definition: osdep.h:123
__be64
uint64_t __be64
Definition: osdep.h:70
swab32
#define swab32(x)
Definition: osdep.h:98
cpu_to_be64
#define cpu_to_be64(x)
Definition: osdep.h:111
be32_to_cpu
#define be32_to_cpu(x)
Definition: osdep.h:107
le16_to_cpu
#define le16_to_cpu(x)
Definition: osdep.h:100
udelay
#define udelay(x)
Definition: osdep.h:89
u8
uint8_t u8
Definition: osdep.h:59
be64_to_cpu
#define be64_to_cpu(x)
Definition: osdep.h:108
PCI_CAP_ID_EXP
#define PCI_CAP_ID_EXP
Definition: osdep.h:125
PCI_EXP_LNKSTA
#define PCI_EXP_LNKSTA
Definition: osdep.h:130
PCI_EXP_DEVCTL2
#define PCI_EXP_DEVCTL2
Definition: osdep.h:133
mdelay
#define mdelay(x)
Definition: osdep.h:88
__force
#define __force
Definition: osdep.h:86
CH_WARN
#define CH_WARN(adap, fmt,...)
Definition: osdep.h:47
CH_ERR
#define CH_ERR(adap, fmt,...)
Definition: osdep.h:45
CH_WARN_RATELIMIT
#define CH_WARN_RATELIMIT(adap, fmt,...)
Definition: osdep.h:51
u16
uint16_t u16
Definition: osdep.h:60
PCI_DEVICE_ID
#define PCI_DEVICE_ID
Definition: osdep.h:119
CH_ALERT
#define CH_ALERT(adap, fmt,...)
Definition: osdep.h:49
PCI_EXP_LNKSTA_CLS
#define PCI_EXP_LNKSTA_CLS
Definition: osdep.h:131
PCI_CAP_ID_VPD
#define PCI_CAP_ID_VPD
Definition: osdep.h:120
cpu_to_be16
#define cpu_to_be16(x)
Definition: osdep.h:109
PCI_EXP_LNKSTA_NLW
#define PCI_EXP_LNKSTA_NLW
Definition: osdep.h:132
u32
uint32_t u32
Definition: osdep.h:61
cpu_to_be32
#define cpu_to_be32(x)
Definition: osdep.h:110
DIV_ROUND_UP
#define DIV_ROUND_UP(x, y)
Definition: osdep.h:92
adapter_params::scfg_vers
unsigned int scfg_vers
Definition: common.h:375
adapter_params::rev
unsigned int rev
Definition: common.h:387
adapter_params::devlog
struct devlog_params devlog
Definition: common.h:363
adapter_params::a_wnd
unsigned short a_wnd[NCCTRL_WIN]
Definition: common.h:379
adapter_params::mps_bg_map
uint32_t mps_bg_map
Definition: common.h:404
adapter_params::tp
struct tp_params tp
Definition: common.h:360
adapter_params::smac_add_support
unsigned int smac_add_support
Definition: common.h:396
adapter_params::fpga
unsigned int fpga
Definition: common.h:388
adapter_params::fw_vers
unsigned int fw_vers
Definition: common.h:371
adapter_params::sf_size
unsigned int sf_size
Definition: common.h:368
adapter_params::portvec
uint8_t portvec
Definition: common.h:385
adapter_params::pci
struct pci_params pci
Definition: common.h:362
adapter_params::viid_smt_extn_support
bool viid_smt_extn_support
Definition: common.h:409
adapter_params::tp_vers
unsigned int tp_vers
Definition: common.h:373
adapter_params::port_caps32
unsigned int port_caps32
Definition: common.h:395
adapter_params::cim_la_size
unsigned int cim_la_size
Definition: common.h:382
adapter_params::sge
struct sge_params sge
Definition: common.h:359
adapter_params::bs_vers
unsigned int bs_vers
Definition: common.h:372
adapter_params::vfres
struct vf_resources vfres
Definition: common.h:365
adapter_params::chipid
unsigned int chipid
Definition: common.h:386
adapter_params::er_vers
unsigned int er_vers
Definition: common.h:374
adapter_params::sf_nsec
unsigned int sf_nsec
Definition: common.h:369
adapter_params::vpd
struct vpd_params vpd
Definition: common.h:361
adapter_params::nports
uint8_t nports
Definition: common.h:384
adapter_params::vpd_vers
unsigned int vpd_vers
Definition: common.h:376
adapter_params::b_wnd
unsigned short b_wnd[NCCTRL_WIN]
Definition: common.h:380
adapter::mbox
unsigned int mbox
Definition: adapter.h:883
adapter::bt_map
int bt_map
Definition: adapter.h:938
adapter::vpd_busy
unsigned int vpd_busy
Definition: adapter.h:884
adapter::pf
unsigned int pf
Definition: adapter.h:882
adapter::flags
int flags
Definition: adapter.h:940
adapter::chip_params
const struct chip_params * chip_params
Definition: adapter.h:959
adapter::params
struct adapter_params params
Definition: adapter.h:958
adapter::port
struct port_info * port[MAX_NPORTS]
Definition: adapter.h:912
adapter::vpd_flag
unsigned int vpd_flag
Definition: adapter.h:885
chip_params
Definition: common.h:306
chip_params::mps_tcam_size
u16 mps_tcam_size
Definition: common.h:316
chip_params::rss_nentries
u16 rss_nentries
Definition: common.h:317
chip_params::cim_num_obq
u8 cim_num_obq
Definition: common.h:311
chip_params::pm_stats_cnt
u8 pm_stats_cnt
Definition: common.h:308
chip_params::nchan
u8 nchan
Definition: common.h:307
chip_params::filter_opt_len
u8 filter_opt_len
Definition: common.h:312
devlog_params
Definition: common.h:298
devlog_params::memtype
u32 memtype
Definition: common.h:299
devlog_params::size
u32 size
Definition: common.h:301
devlog_params::start
u32 start
Definition: common.h:300
efi_pci_expansion_rom_header
Definition: t4_hw.c:10563
efi_pci_expansion_rom_header::efi_image_header_offset
u8 efi_image_header_offset[2]
Definition: t4_hw.c:10577
efi_pci_expansion_rom_header::efi_machine_type
u8 efi_machine_type[2]
Definition: t4_hw.c:10568
efi_pci_expansion_rom_header::efi_signature
u8 efi_signature[4]
Definition: t4_hw.c:10566
efi_pci_expansion_rom_header::pcir_offset
u8 pcir_offset[2]
Definition: t4_hw.c:10578
efi_pci_expansion_rom_header::compression_type
u8 compression_type[2]
Definition: t4_hw.c:10569
efi_pci_expansion_rom_header::efi_subsystem
u8 efi_subsystem[2]
Definition: t4_hw.c:10567
efi_pci_expansion_rom_header::signature
u8 signature[2]
Definition: t4_hw.c:10564
efi_pci_expansion_rom_header::initialization_size
u8 initialization_size[2]
Definition: t4_hw.c:10565
efi_pci_expansion_rom_header::reserved
u8 reserved[8]
Definition: t4_hw.c:10576
flash_desc
Definition: t4_hw.c:9113
flash_desc::size_mb
u32 size_mb
Definition: t4_hw.c:9115
flash_desc::vendor_and_model_id
u32 vendor_and_model_id
Definition: t4_hw.c:9114
fw_acl_mac_cmd
Definition: t4fw_interface.h:7038
fw_acl_mac_cmd::macaddr1
__u8 macaddr1[6]
Definition: t4fw_interface.h:7046
fw_acl_mac_cmd::macaddr2
__u8 macaddr2[6]
Definition: t4fw_interface.h:7048
fw_acl_mac_cmd::macaddr0
__u8 macaddr0[6]
Definition: t4fw_interface.h:7044
fw_acl_mac_cmd::nmac
__u8 nmac
Definition: t4fw_interface.h:7041
fw_acl_mac_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:7039
fw_acl_mac_cmd::en_to_len16
__be32 en_to_len16
Definition: t4fw_interface.h:7040
fw_acl_mac_cmd::macaddr3
__u8 macaddr3[6]
Definition: t4fw_interface.h:7050
fw_acl_vlan_cmd
Definition: t4fw_interface.h:7072
fw_acl_vlan_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:7073
fw_acl_vlan_cmd::en_to_len16
__be32 en_to_len16
Definition: t4fw_interface.h:7074
fw_acl_vlan_cmd::vlanid
__be16 vlanid[16]
Definition: t4fw_interface.h:7078
fw_acl_vlan_cmd::nvlan
__u8 nvlan
Definition: t4fw_interface.h:7075
fw_acl_vlan_cmd::dropnovlan_fm
__u8 dropnovlan_fm
Definition: t4fw_interface.h:7076
fw_bye_cmd
Definition: t4fw_interface.h:4581
fw_debug_cmd::fw_debug::fw_debug_assert::y
__be32 y
Definition: t4fw_interface.h:9642
fw_debug_cmd::fw_debug::fw_debug_assert::line
__be32 line
Definition: t4fw_interface.h:9640
fw_debug_cmd::fw_debug::fw_debug_assert::filename_0_7
__u8 filename_0_7[8]
Definition: t4fw_interface.h:9643
fw_debug_cmd::fw_debug::fw_debug_assert::x
__be32 x
Definition: t4fw_interface.h:9641
fw_debug_cmd
Definition: t4fw_interface.h:9634
fw_debug_cmd::u
union fw_debug_cmd::fw_debug u
fw_devlog_cmd
Definition: t4fw_interface.h:8858
fw_devlog_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8860
fw_devlog_cmd::memtype_devlog_memaddr16_devlog
__be32 memtype_devlog_memaddr16_devlog
Definition: t4fw_interface.h:8863
fw_devlog_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8859
fw_devlog_cmd::level
__u8 level
Definition: t4fw_interface.h:8861
fw_devlog_cmd::memsize_devlog
__be32 memsize_devlog
Definition: t4fw_interface.h:8864
fw_devlog_e
Definition: t4fw_interface.h:8847
fw_eq_ctrl_cmd
Definition: t4fw_interface.h:6138
fw_eq_ctrl_cmd::cmpliqid_eqid
__be32 cmpliqid_eqid
Definition: t4fw_interface.h:6141
fw_eq_ctrl_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:6140
fw_eq_ctrl_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:6139
fw_eq_eth_cmd
Definition: t4fw_interface.h:5922
fw_eq_eth_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5923
fw_eq_eth_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:5924
fw_eq_eth_cmd::eqid_pkd
__be32 eqid_pkd
Definition: t4fw_interface.h:5925
fw_eq_ofld_cmd
Definition: t4fw_interface.h:6325
fw_eq_ofld_cmd::eqid_pkd
__be32 eqid_pkd
Definition: t4fw_interface.h:6328
fw_eq_ofld_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:6326
fw_eq_ofld_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:6327
fw_filter_wr
Definition: t4fw_interface.h:322
fw_filter_wr::tid_to_iq
__be32 tid_to_iq
Definition: t4fw_interface.h:326
fw_filter_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:324
fw_filter_wr::rx_chan_rx_rpl_iq
__be16 rx_chan_rx_rpl_iq
Definition: t4fw_interface.h:332
fw_filter_wr::del_filter_to_l2tix
__be32 del_filter_to_l2tix
Definition: t4fw_interface.h:327
fw_filter_wr::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:323
fw_hdr
Definition: t4fw_interface.h:9945
fw_hdr::chip
__u8 chip
Definition: t4fw_interface.h:9947
fw_hdr::fw_ver
__be32 fw_ver
Definition: t4fw_interface.h:9949
fw_hdr::magic
__be32 magic
Definition: t4fw_interface.h:9961
fw_hdr::len512
__be16 len512
Definition: t4fw_interface.h:9948
fw_hello_cmd
Definition: t4fw_interface.h:4514
fw_hello_cmd::err_to_clearinit
__be32 err_to_clearinit
Definition: t4fw_interface.h:4517
fw_initialize_cmd
Definition: t4fw_interface.h:4587
fw_iq_cmd
Definition: t4fw_interface.h:5213
fw_iq_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:5215
fw_iq_cmd::fl0id
__be16 fl0id
Definition: t4fw_interface.h:5218
fw_iq_cmd::iqid
__be16 iqid
Definition: t4fw_interface.h:5217
fw_iq_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5214
fw_iq_cmd::type_to_iqandstindex
__be32 type_to_iqandstindex
Definition: t4fw_interface.h:5220
fw_iq_cmd::fl1id
__be16 fl1id
Definition: t4fw_interface.h:5219
fw_ldst_cmd::fw_ldst::fw_ldst_addrval::val
__be32 val
Definition: t4fw_interface.h:4288
fw_ldst_cmd::fw_ldst::fw_ldst_addrval::addr
__be32 addr
Definition: t4fw_interface.h:4287
fw_ldst_cmd::fw_ldst::fw_ldst_i2c::boffset
__u8 boffset
Definition: t4fw_interface.h:4365
fw_ldst_cmd::fw_ldst::fw_ldst_i2c::blen
__u8 blen
Definition: t4fw_interface.h:4366
fw_ldst_cmd::fw_ldst::fw_ldst_i2c::pid
__u8 pid
Definition: t4fw_interface.h:4363
fw_ldst_cmd::fw_ldst::fw_ldst_i2c::data
__u8 data[48]
Definition: t4fw_interface.h:4368
fw_ldst_cmd::fw_ldst::fw_ldst_i2c::did
__u8 did
Definition: t4fw_interface.h:4364
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data3
__be32 ctxt_data3
Definition: t4fw_interface.h:4297
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data1
__be32 ctxt_data1
Definition: t4fw_interface.h:4299
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data5
__be32 ctxt_data5
Definition: t4fw_interface.h:4295
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data0
__be32 ctxt_data0
Definition: t4fw_interface.h:4300
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data2
__be32 ctxt_data2
Definition: t4fw_interface.h:4298
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::physid
__be32 physid
Definition: t4fw_interface.h:4291
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data4
__be32 ctxt_data4
Definition: t4fw_interface.h:4296
fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::msg_ctxtflush
__be32 msg_ctxtflush
Definition: t4fw_interface.h:4292
fw_ldst_cmd::fw_ldst::fw_ldst_mdio::paddr_mmd
__be16 paddr_mmd
Definition: t4fw_interface.h:4303
fw_ldst_cmd::fw_ldst::fw_ldst_mdio::rval
__be16 rval
Definition: t4fw_interface.h:4306
fw_ldst_cmd::fw_ldst::fw_ldst_mdio::raddr
__be16 raddr
Definition: t4fw_interface.h:4304
fw_ldst_cmd::fw_ldst::fw_ldst_pcie::data
__be32 data[12]
Definition: t4fw_interface.h:4353
fw_ldst_cmd::fw_ldst::fw_ldst_pcie::select_naccess
__u8 select_naccess
Definition: t4fw_interface.h:4350
fw_ldst_cmd::fw_ldst::fw_ldst_pcie::ctrl_to_fn
__u8 ctrl_to_fn
Definition: t4fw_interface.h:4346
fw_ldst_cmd::fw_ldst::fw_ldst_pcie::r
__u8 r
Definition: t4fw_interface.h:4348
fw_ldst_cmd
Definition: t4fw_interface.h:4282
fw_ldst_cmd::u
union fw_ldst_cmd::fw_ldst u
fw_ldst_cmd::op_to_addrspace
__be32 op_to_addrspace
Definition: t4fw_interface.h:4283
fw_ldst_cmd::cycles_to_len16
__be32 cycles_to_len16
Definition: t4fw_interface.h:4284
fw_params_cmd::fw_params_param::val
__be32 val
Definition: t4fw_interface.h:5083
fw_params_cmd::fw_params_param::mnem
__be32 mnem
Definition: t4fw_interface.h:5082
fw_params_cmd
Definition: t4fw_interface.h:5078
fw_params_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:5080
fw_params_cmd::param
struct fw_params_cmd::fw_params_param param[7]
fw_params_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5079
fw_pfvf_cmd
Definition: t4fw_interface.h:5099
fw_pfvf_cmd::r_caps_to_nethctrl
__be32 r_caps_to_nethctrl
Definition: t4fw_interface.h:5105
fw_pfvf_cmd::niqflint_niq
__be32 niqflint_niq
Definition: t4fw_interface.h:5102
fw_pfvf_cmd::tc_to_nexactf
__be32 tc_to_nexactf
Definition: t4fw_interface.h:5104
fw_pfvf_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5100
fw_pfvf_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:5101
fw_pfvf_cmd::type_to_neq
__be32 type_to_neq
Definition: t4fw_interface.h:5103
fw_port_cmd::fw_port::fw_port_info32::lstatus32_to_cbllen32
__be32 lstatus32_to_cbllen32
Definition: t4fw_interface.h:7475
fw_port_cmd::fw_port::fw_port_info32::pcaps32
__be32 pcaps32
Definition: t4fw_interface.h:7478
fw_port_cmd::fw_port::fw_port_info32::lpacaps32
__be32 lpacaps32
Definition: t4fw_interface.h:7480
fw_port_cmd::fw_port::fw_port_info32::linkattr32
__be32 linkattr32
Definition: t4fw_interface.h:7477
fw_port_cmd::fw_port::fw_port_info32::acaps32
__be32 acaps32
Definition: t4fw_interface.h:7479
fw_port_cmd::fw_port::fw_port_info::pcap
__be16 pcap
Definition: t4fw_interface.h:7407
fw_port_cmd::fw_port::fw_port_info::lstatus_to_modtype
__be32 lstatus_to_modtype
Definition: t4fw_interface.h:7406
fw_port_cmd::fw_port::fw_port_info::lpacap
__be16 lpacap
Definition: t4fw_interface.h:7414
fw_port_cmd::fw_port::fw_port_info::acap
__be16 acap
Definition: t4fw_interface.h:7408
fw_port_cmd::fw_port::fw_port_l1cfg32::rcap32
__be32 rcap32
Definition: t4fw_interface.h:7471
fw_port_cmd::fw_port::fw_port_l1cfg::rcap
__be32 rcap
Definition: t4fw_interface.h:7387
fw_port_cmd
Definition: t4fw_interface.h:7382
fw_port_cmd::u
union fw_port_cmd::fw_port u
fw_port_cmd::action_to_len16
__be32 action_to_len16
Definition: t4fw_interface.h:7384
fw_port_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:7383
fw_reset_cmd
Definition: t4fw_interface.h:4493
fw_reset_cmd::halt_pkd
__be32 halt_pkd
Definition: t4fw_interface.h:4497
fw_reset_cmd::val
__be32 val
Definition: t4fw_interface.h:4496
fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual::synmapen_to_hashtoeplitz
__be32 synmapen_to_hashtoeplitz
Definition: t4fw_interface.h:8521
fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual::mode_keymode
__be32 mode_keymode
Definition: t4fw_interface.h:8520
fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual::mode_pkd
__be32 mode_pkd
Definition: t4fw_interface.h:8514
fw_rss_glb_config_cmd
Definition: t4fw_interface.h:8509
fw_rss_glb_config_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8510
fw_rss_glb_config_cmd::u
union fw_rss_glb_config_cmd::fw_rss_glb_config u
fw_rss_glb_config_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8511
fw_rss_ind_tbl_cmd
Definition: t4fw_interface.h:8291
fw_rss_ind_tbl_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:8292
fw_rss_ind_tbl_cmd::niqid
__be16 niqid
Definition: t4fw_interface.h:8294
fw_rss_ind_tbl_cmd::iq0_to_iq2
__be32 iq0_to_iq2
Definition: t4fw_interface.h:8297
fw_rss_ind_tbl_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8293
fw_rss_ind_tbl_cmd::startidx
__be16 startidx
Definition: t4fw_interface.h:8295
fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::secretkeyxor
__be32 secretkeyxor
Definition: t4fw_interface.h:8651
fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::defaultq_to_udpen
__be32 defaultq_to_udpen
Definition: t4fw_interface.h:8649
fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::secretkeyidx_pkd
__be32 secretkeyidx_pkd
Definition: t4fw_interface.h:8650
fw_rss_vi_config_cmd
Definition: t4fw_interface.h:8638
fw_rss_vi_config_cmd::u
union fw_rss_vi_config_cmd::fw_rss_vi_config u
fw_rss_vi_config_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:8639
fw_rss_vi_config_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8640
fw_sched_cmd::fw_sched::fw_sched_config::sc
__u8 sc
Definition: t4fw_interface.h:8762
fw_sched_cmd::fw_sched::fw_sched_config::type
__u8 type
Definition: t4fw_interface.h:8763
fw_sched_cmd::fw_sched::fw_sched_config::minmaxen
__u8 minmaxen
Definition: t4fw_interface.h:8764
fw_sched_cmd::fw_sched::fw_sched_params::max
__be32 max
Definition: t4fw_interface.h:8779
fw_sched_cmd::fw_sched::fw_sched_params::unit
__u8 unit
Definition: t4fw_interface.h:8774
fw_sched_cmd::fw_sched::fw_sched_params::weight
__be16 weight
Definition: t4fw_interface.h:8780
fw_sched_cmd::fw_sched::fw_sched_params::ch
__u8 ch
Definition: t4fw_interface.h:8776
fw_sched_cmd::fw_sched::fw_sched_params::type
__u8 type
Definition: t4fw_interface.h:8771
fw_sched_cmd::fw_sched::fw_sched_params::rate
__u8 rate
Definition: t4fw_interface.h:8775
fw_sched_cmd::fw_sched::fw_sched_params::min
__be32 min
Definition: t4fw_interface.h:8778
fw_sched_cmd::fw_sched::fw_sched_params::burstsize
__be16 burstsize
Definition: t4fw_interface.h:8782
fw_sched_cmd::fw_sched::fw_sched_params::cl
__u8 cl
Definition: t4fw_interface.h:8777
fw_sched_cmd::fw_sched::fw_sched_params::pktsize
__be16 pktsize
Definition: t4fw_interface.h:8781
fw_sched_cmd::fw_sched::fw_sched_params::mode
__u8 mode
Definition: t4fw_interface.h:8773
fw_sched_cmd::fw_sched::fw_sched_params::sc
__u8 sc
Definition: t4fw_interface.h:8770
fw_sched_cmd::fw_sched::fw_sched_params::level
__u8 level
Definition: t4fw_interface.h:8772
fw_sched_cmd
Definition: t4fw_interface.h:8757
fw_sched_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8758
fw_sched_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8759
fw_sched_cmd::u
union fw_sched_cmd::fw_sched u
fw_vi_cmd
Definition: t4fw_interface.h:6553
fw_vi_cmd::mac
__u8 mac[6]
Definition: t4fw_interface.h:6557
fw_vi_cmd::nmac1
__u8 nmac1[6]
Definition: t4fw_interface.h:6562
fw_vi_cmd::nmac0
__u8 nmac0[6]
Definition: t4fw_interface.h:6560
fw_vi_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:6554
fw_vi_cmd::nmac3
__u8 nmac3[6]
Definition: t4fw_interface.h:6566
fw_vi_cmd::portid_pkd
__u8 portid_pkd
Definition: t4fw_interface.h:6558
fw_vi_cmd::nmac2
__u8 nmac2[6]
Definition: t4fw_interface.h:6564
fw_vi_cmd::type_to_viid
__be16 type_to_viid
Definition: t4fw_interface.h:6556
fw_vi_cmd::nmac
__u8 nmac
Definition: t4fw_interface.h:6559
fw_vi_cmd::norss_rsssize
__be16 norss_rsssize
Definition: t4fw_interface.h:6561
fw_vi_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:6555
fw_vi_enable_cmd
Definition: t4fw_interface.h:6880
fw_vi_enable_cmd::ien_to_len16
__be32 ien_to_len16
Definition: t4fw_interface.h:6882
fw_vi_enable_cmd::blinkdur
__be16 blinkdur
Definition: t4fw_interface.h:6883
fw_vi_enable_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6881
fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_exact::valid_to_idx
__be16 valid_to_idx
Definition: t4fw_interface.h:6692
fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_hash::hashvec
__be64 hashvec
Definition: t4fw_interface.h:6696
fw_vi_mac_cmd
Definition: t4fw_interface.h:6687
fw_vi_mac_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6688
fw_vi_mac_cmd::freemacs_to_len16
__be32 freemacs_to_len16
Definition: t4fw_interface.h:6689
fw_vi_mac_cmd::u
union fw_vi_mac_cmd::fw_vi_mac u
fw_vi_rxmode_cmd
Definition: t4fw_interface.h:6835
fw_vi_rxmode_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:6837
fw_vi_rxmode_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6836
fw_vi_rxmode_cmd::mtu_to_vlanexen
__be32 mtu_to_vlanexen
Definition: t4fw_interface.h:6838
fw_watchdog_cmd
Definition: t4fw_interface.h:8895
fw_watchdog_cmd::action
__be32 action
Definition: t4fw_interface.h:8899
fw_watchdog_cmd::timeout
__be32 timeout
Definition: t4fw_interface.h:8898
fw_watchdog_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8897
fw_watchdog_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:8896
intr_action
Definition: t4_hw.c:4042
intr_action::mask
u32 mask
Definition: t4_hw.c:4043
intr_action::action
bool(* action)(struct adapter *, int, bool)
Definition: t4_hw.c:4045
intr_action::arg
int arg
Definition: t4_hw.c:4044
intr_details
Definition: t4_hw.c:4037
intr_details::msg
const char * msg
Definition: t4_hw.c:4039
intr_details::mask
u32 mask
Definition: t4_hw.c:4038
intr_info
Definition: t4_hw.c:4049
intr_info::details
const struct intr_details * details
Definition: t4_hw.c:4055
intr_info::flags
int flags
Definition: t4_hw.c:4054
intr_info::cause_reg
int cause_reg
Definition: t4_hw.c:4051
intr_info::fatal
u32 fatal
Definition: t4_hw.c:4053
intr_info::name
const char * name
Definition: t4_hw.c:4050
intr_info::actions
const struct intr_action * actions
Definition: t4_hw.c:4056
intr_info::enable_reg
int enable_reg
Definition: t4_hw.c:4052
lb_port_stats
Definition: common.h:151
lb_port_stats::frames_64
u64 frames_64
Definition: common.h:159
lb_port_stats::ucast_frames
u64 ucast_frames
Definition: common.h:156
lb_port_stats::trunc3
u64 trunc3
Definition: common.h:176
lb_port_stats::frames
u64 frames
Definition: common.h:153
lb_port_stats::trunc1
u64 trunc1
Definition: common.h:174
lb_port_stats::trunc2
u64 trunc2
Definition: common.h:175
lb_port_stats::frames_128_255
u64 frames_128_255
Definition: common.h:161
lb_port_stats::frames_1519_max
u64 frames_1519_max
Definition: common.h:165
lb_port_stats::ovflow0
u64 ovflow0
Definition: common.h:169
lb_port_stats::frames_1024_1518
u64 frames_1024_1518
Definition: common.h:164
lb_port_stats::mcast_frames
u64 mcast_frames
Definition: common.h:155
lb_port_stats::bcast_frames
u64 bcast_frames
Definition: common.h:154
lb_port_stats::frames_512_1023
u64 frames_512_1023
Definition: common.h:163
lb_port_stats::octets
u64 octets
Definition: common.h:152
lb_port_stats::frames_65_127
u64 frames_65_127
Definition: common.h:160
lb_port_stats::frames_256_511
u64 frames_256_511
Definition: common.h:162
lb_port_stats::ovflow2
u64 ovflow2
Definition: common.h:171
lb_port_stats::drop
u64 drop
Definition: common.h:167
lb_port_stats::error_frames
u64 error_frames
Definition: common.h:157
lb_port_stats::ovflow1
u64 ovflow1
Definition: common.h:170
lb_port_stats::trunc0
u64 trunc0
Definition: common.h:173
lb_port_stats::ovflow3
u64 ovflow3
Definition: common.h:172
legacy_pci_expansion_rom_header
Definition: t4_hw.c:10553
legacy_pci_expansion_rom_header::initentry_point
u8 initentry_point[4]
Definition: t4_hw.c:10556
legacy_pci_expansion_rom_header::pcir_offset
u8 pcir_offset[2]
Definition: t4_hw.c:10559
legacy_pci_expansion_rom_header::size512
u8 size512
Definition: t4_hw.c:10555
legacy_pci_expansion_rom_header::signature
u8 signature[2]
Definition: t4_hw.c:10554
legacy_pci_expansion_rom_header::reserved
u8 reserved[16]
Definition: t4_hw.c:10558
legacy_pci_expansion_rom_header::cksum
u8 cksum
Definition: t4_hw.c:10557
link_config
Definition: common.h:441
link_config::fec
int8_t fec
Definition: common.h:457
link_config::fc
int8_t fc
Definition: common.h:455
link_config::requested_fec
int8_t requested_fec
Definition: common.h:445
link_config::pcaps
uint32_t pcaps
Definition: common.h:451
link_config::acaps
uint32_t acaps
Definition: common.h:452
link_config::link_ok
bool link_ok
Definition: common.h:458
link_config::link_down_rc
uint8_t link_down_rc
Definition: common.h:459
link_config::force_fec
int8_t force_fec
Definition: common.h:446
link_config::speed
u_int speed
Definition: common.h:454
link_config::requested_aneg
int8_t requested_aneg
Definition: common.h:443
link_config::lpacaps
uint32_t lpacaps
Definition: common.h:453
link_config::requested_fc
int8_t requested_fc
Definition: common.h:444
link_config::fec_hint
int8_t fec_hint
Definition: common.h:456
link_config::requested_caps
uint32_t requested_caps
Definition: common.h:448
link_config::requested_speed
u_int requested_speed
Definition: common.h:447
pci_expansion_rom_header
Definition: t4_hw.c:10546
pci_expansion_rom_header::reserved
u8 reserved[22]
Definition: t4_hw.c:10548
pci_expansion_rom_header::pcir_offset
u8 pcir_offset[2]
Definition: t4_hw.c:10549
pci_expansion_rom_header::signature
u8 signature[2]
Definition: t4_hw.c:10547
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Definition: common.h:288
pci_params::vpd_cap_addr
unsigned int vpd_cap_addr
Definition: common.h:289
pci_params::width
unsigned short width
Definition: common.h:292
pci_params::speed
unsigned short speed
Definition: common.h:291
pcir_data_structure
Definition: t4_hw.c:10582
pcir_data_structure::length
u8 length[2]
Definition: t4_hw.c:10587
pcir_data_structure::code_type
u8 code_type
Definition: t4_hw.c:10592
pcir_data_structure::vendor_id
u8 vendor_id[2]
Definition: t4_hw.c:10584
pcir_data_structure::reserved
u8 reserved[2]
Definition: t4_hw.c:10602
pcir_data_structure::vital_product
u8 vital_product[2]
Definition: t4_hw.c:10586
pcir_data_structure::device_id
u8 device_id[2]
Definition: t4_hw.c:10585
pcir_data_structure::indicator
u8 indicator
Definition: t4_hw.c:10601
pcir_data_structure::code_revision
u8 code_revision[2]
Definition: t4_hw.c:10591
pcir_data_structure::signature
u8 signature[4]
Definition: t4_hw.c:10583
pcir_data_structure::class_code
u8 class_code[3]
Definition: t4_hw.c:10589
pcir_data_structure::revision
u8 revision
Definition: t4_hw.c:10588
pcir_data_structure::image_length
u8 image_length[2]
Definition: t4_hw.c:10590
port_info
Definition: adapter.h:304
port_info::rx_c_chan
uint8_t rx_c_chan
Definition: adapter.h:328
port_info::port_type
uint8_t port_type
Definition: adapter.h:322
port_info::fcs_base
uint64_t fcs_base
Definition: adapter.h:337
port_info::lport
uint8_t lport
Definition: adapter.h:320
port_info::fcs_reg
int fcs_reg
Definition: adapter.h:336
port_info::link_cfg
struct link_config link_cfg
Definition: adapter.h:330
port_info::tx_chan
uint8_t tx_chan
Definition: adapter.h:325
port_info::mod_type
uint8_t mod_type
Definition: adapter.h:323
port_info::adapter
struct adapter * adapter
Definition: adapter.h:306
port_info::mps_bg_map
uint8_t mps_bg_map
Definition: adapter.h:326
port_info::vi
struct vi_info * vi
Definition: adapter.h:308
port_info::rx_e_chan_map
uint8_t rx_e_chan_map
Definition: adapter.h:327
port_info::port_id
uint8_t port_id
Definition: adapter.h:324
port_info::mdio_addr
int8_t mdio_addr
Definition: adapter.h:321
port_stats
Definition: common.h:84
port_stats::rx_frames
u64 rx_frames
Definition: common.h:112
port_stats::tx_frames_1519_max
u64 tx_frames_1519_max
Definition: common.h:98
port_stats::tx_frames
u64 tx_frames
Definition: common.h:86
port_stats::tx_frames_128_255
u64 tx_frames_128_255
Definition: common.h:94
port_stats::rx_ovflow1
u64 rx_ovflow1
Definition: common.h:142
port_stats::rx_ovflow3
u64 rx_ovflow3
Definition: common.h:144
port_stats::rx_frames_64
u64 rx_frames_64
Definition: common.h:123
port_stats::rx_ppp4
u64 rx_ppp4
Definition: common.h:136
port_stats::tx_frames_512_1023
u64 tx_frames_512_1023
Definition: common.h:96
port_stats::tx_frames_256_511
u64 tx_frames_256_511
Definition: common.h:95
port_stats::tx_mcast_frames
u64 tx_mcast_frames
Definition: common.h:88
port_stats::rx_ppp7
u64 rx_ppp7
Definition: common.h:139
port_stats::rx_ovflow0
u64 rx_ovflow0
Definition: common.h:141
port_stats::tx_frames_64
u64 tx_frames_64
Definition: common.h:92
port_stats::tx_ucast_frames
u64 tx_ucast_frames
Definition: common.h:89
port_stats::rx_frames_512_1023
u64 rx_frames_512_1023
Definition: common.h:127
port_stats::rx_ppp1
u64 rx_ppp1
Definition: common.h:133
port_stats::tx_octets
u64 tx_octets
Definition: common.h:85
port_stats::rx_ppp5
u64 rx_ppp5
Definition: common.h:137
port_stats::rx_frames_1024_1518
u64 rx_frames_1024_1518
Definition: common.h:128
port_stats::tx_ppp5
u64 tx_ppp5
Definition: common.h:107
port_stats::rx_octets
u64 rx_octets
Definition: common.h:111
port_stats::rx_jabber
u64 rx_jabber
Definition: common.h:117
port_stats::rx_frames_65_127
u64 rx_frames_65_127
Definition: common.h:124
port_stats::rx_too_long
u64 rx_too_long
Definition: common.h:116
port_stats::tx_ppp7
u64 tx_ppp7
Definition: common.h:109
port_stats::rx_mcast_frames
u64 rx_mcast_frames
Definition: common.h:114
port_stats::rx_ovflow2
u64 rx_ovflow2
Definition: common.h:143
port_stats::tx_ppp2
u64 tx_ppp2
Definition: common.h:104
port_stats::rx_trunc2
u64 rx_trunc2
Definition: common.h:147
port_stats::rx_fcs_err
u64 rx_fcs_err
Definition: common.h:118
port_stats::rx_bcast_frames
u64 rx_bcast_frames
Definition: common.h:113
port_stats::rx_frames_128_255
u64 rx_frames_128_255
Definition: common.h:125
port_stats::rx_len_err
u64 rx_len_err
Definition: common.h:119
port_stats::rx_trunc1
u64 rx_trunc1
Definition: common.h:146
port_stats::tx_drop
u64 tx_drop
Definition: common.h:100
port_stats::tx_ppp1
u64 tx_ppp1
Definition: common.h:103
port_stats::tx_ppp0
u64 tx_ppp0
Definition: common.h:102
port_stats::rx_symbol_err
u64 rx_symbol_err
Definition: common.h:120
port_stats::tx_ppp3
u64 tx_ppp3
Definition: common.h:105
port_stats::tx_ppp4
u64 tx_ppp4
Definition: common.h:106
port_stats::rx_ppp2
u64 rx_ppp2
Definition: common.h:134
port_stats::rx_ucast_frames
u64 rx_ucast_frames
Definition: common.h:115
port_stats::rx_trunc0
u64 rx_trunc0
Definition: common.h:145
port_stats::tx_pause
u64 tx_pause
Definition: common.h:101
port_stats::rx_ppp3
u64 rx_ppp3
Definition: common.h:135
port_stats::rx_runt
u64 rx_runt
Definition: common.h:121
port_stats::tx_frames_1024_1518
u64 tx_frames_1024_1518
Definition: common.h:97
port_stats::rx_frames_256_511
u64 rx_frames_256_511
Definition: common.h:126
port_stats::tx_error_frames
u64 tx_error_frames
Definition: common.h:90
port_stats::rx_pause
u64 rx_pause
Definition: common.h:131
port_stats::rx_ppp0
u64 rx_ppp0
Definition: common.h:132
port_stats::tx_ppp6
u64 tx_ppp6
Definition: common.h:108
port_stats::rx_ppp6
u64 rx_ppp6
Definition: common.h:138
port_stats::tx_frames_65_127
u64 tx_frames_65_127
Definition: common.h:93
port_stats::rx_trunc3
u64 rx_trunc3
Definition: common.h:148
port_stats::rx_frames_1519_max
u64 rx_frames_1519_max
Definition: common.h:129
port_stats::tx_bcast_frames
u64 tx_bcast_frames
Definition: common.h:87
port_tx_state
Definition: t4_hw.c:243
port_tx_state::rx_pause
uint64_t rx_pause
Definition: t4_hw.c:244
port_tx_state::tx_frames
uint64_t tx_frames
Definition: t4_hw.c:245
sge_idma_monitor_state
Definition: common.h:422
sge_idma_monitor_state::idma_stalled
unsigned int idma_stalled[2]
Definition: common.h:424
sge_idma_monitor_state::idma_qid
unsigned int idma_qid[2]
Definition: common.h:426
sge_idma_monitor_state::idma_state
unsigned int idma_state[2]
Definition: common.h:425
sge_idma_monitor_state::idma_warn
unsigned int idma_warn[2]
Definition: common.h:427
sge_idma_monitor_state::idma_1s_thresh
unsigned int idma_1s_thresh
Definition: common.h:423
sge_params
Definition: common.h:237
sge_params::counter_val
int counter_val[SGE_NCOUNTERS]
Definition: common.h:239
sge_params::pad_boundary
int pad_boundary
Definition: common.h:246
sge_params::iq_s_qpp
int iq_s_qpp
Definition: common.h:244
sge_params::fl_starve_threshold2
int fl_starve_threshold2
Definition: common.h:241
sge_params::sge_control
u32 sge_control
Definition: common.h:249
sge_params::fl_starve_threshold
int fl_starve_threshold
Definition: common.h:240
sge_params::page_shift
int page_shift
Definition: common.h:242
sge_params::eq_s_qpp
int eq_s_qpp
Definition: common.h:243
sge_params::timer_val
int timer_val[SGE_NTIMERS]
Definition: common.h:238
sge_params::pack_boundary
int pack_boundary
Definition: common.h:247
sge_params::spg_len
int spg_len
Definition: common.h:245
sge_params::fl_pktshift
int fl_pktshift
Definition: common.h:248
t4_vpd_hdr
Definition: t4_hw.c:2715
t4_vpd_hdr::id_len
u8 id_len[2]
Definition: t4_hw.c:2717
t4_vpd_hdr::id_tag
u8 id_tag
Definition: t4_hw.c:2716
t4_vpd_hdr::id_data
u8 id_data[ID_LEN]
Definition: t4_hw.c:2718
t4_vpdr_hdr
Definition: t4_hw.c:2721
t4_vpdr_hdr::vpdr_tag
u8 vpdr_tag
Definition: t4_hw.c:2722
t4_vpdr_hdr::vpdr_len
u8 vpdr_len[2]
Definition: t4_hw.c:2723
tp_cpl_stats
Definition: common.h:227
tp_cpl_stats::req
u32 req[MAX_NCHAN]
Definition: common.h:228
tp_cpl_stats::rsp
u32 rsp[MAX_NCHAN]
Definition: common.h:229
tp_err_stats
Definition: common.h:205
tp_err_stats::tcp6_in_errs
u32 tcp6_in_errs[MAX_NCHAN]
Definition: common.h:213
tp_err_stats::tnl_tx_drops
u32 tnl_tx_drops[MAX_NCHAN]
Definition: common.h:211
tp_err_stats::mac_in_errs
u32 mac_in_errs[MAX_NCHAN]
Definition: common.h:206
tp_err_stats::tnl_cong_drops
u32 tnl_cong_drops[MAX_NCHAN]
Definition: common.h:209
tp_err_stats::ofld_no_neigh
u32 ofld_no_neigh
Definition: common.h:214
tp_err_stats::ofld_vlan_drops
u32 ofld_vlan_drops[MAX_NCHAN]
Definition: common.h:212
tp_err_stats::tcp_in_errs
u32 tcp_in_errs[MAX_NCHAN]
Definition: common.h:208
tp_err_stats::hdr_in_errs
u32 hdr_in_errs[MAX_NCHAN]
Definition: common.h:207
tp_err_stats::ofld_chan_drops
u32 ofld_chan_drops[MAX_NCHAN]
Definition: common.h:210
tp_fcoe_stats
Definition: common.h:199
tp_fcoe_stats::frames_ddp
u32 frames_ddp
Definition: common.h:200
tp_fcoe_stats::octets_ddp
u64 octets_ddp
Definition: common.h:202
tp_fcoe_stats::frames_drop
u32 frames_drop
Definition: common.h:201
tp_params
Definition: common.h:253
tp_params::filter_mode
uint16_t filter_mode
Definition: common.h:259
tp_params::max_rx_pdu
uint32_t max_rx_pdu
Definition: common.h:262
tp_params::protocol_shift
int8_t protocol_shift
Definition: common.h:271
tp_params::max_tx_pdu
uint32_t max_tx_pdu
Definition: common.h:263
tp_params::la_mask
unsigned int la_mask
Definition: common.h:256
tp_params::vnic_shift
int8_t vnic_shift
Definition: common.h:268
tp_params::matchtype_shift
int8_t matchtype_shift
Definition: common.h:274
tp_params::fcoe_shift
int8_t fcoe_shift
Definition: common.h:266
tp_params::macmatch_shift
int8_t macmatch_shift
Definition: common.h:273
tp_params::dack_re
unsigned int dack_re
Definition: common.h:255
tp_params::tre
unsigned int tre
Definition: common.h:254
tp_params::filter_mask
uint16_t filter_mask
Definition: common.h:260
tp_params::vnic_mode
int vnic_mode
Definition: common.h:261
tp_params::frag_shift
int8_t frag_shift
Definition: common.h:275
tp_params::vlan_shift
int8_t vlan_shift
Definition: common.h:269
tp_params::tx_modq
unsigned short tx_modq[MAX_NCHAN]
Definition: common.h:257
tp_params::port_shift
int8_t port_shift
Definition: common.h:267
tp_params::rx_pkt_encap
bool rx_pkt_encap
Definition: common.h:264
tp_params::tos_shift
int8_t tos_shift
Definition: common.h:270
tp_params::ethertype_shift
int8_t ethertype_shift
Definition: common.h:272
tp_proxy_stats
Definition: common.h:223
tp_proxy_stats::proxy
u32 proxy[MAX_NCHAN]
Definition: common.h:224
tp_rdma_stats
Definition: common.h:232
tp_rdma_stats::rqe_dfr_pkt
u32 rqe_dfr_pkt
Definition: common.h:233
tp_tcp_stats
Definition: common.h:179
tp_tcp_stats::tcp_out_segs
u64 tcp_out_segs
Definition: common.h:182
tp_tcp_stats::tcp_out_rsts
u32 tcp_out_rsts
Definition: common.h:180
tp_tcp_stats::tcp_retrans_segs
u64 tcp_retrans_segs
Definition: common.h:183
tp_tcp_stats::tcp_in_segs
u64 tcp_in_segs
Definition: common.h:181
tp_tid_stats
Definition: common.h:192
tp_tid_stats::del
u32 del
Definition: common.h:193
tp_tnl_stats
Definition: common.h:218
tp_tnl_stats::out_pkt
u32 out_pkt[MAX_NCHAN]
Definition: common.h:219
tp_tnl_stats::in_pkt
u32 in_pkt[MAX_NCHAN]
Definition: common.h:220
tp_usm_stats
Definition: common.h:186
tp_usm_stats::drops
u32 drops
Definition: common.h:188
tp_usm_stats::frames
u32 frames
Definition: common.h:187
tp_usm_stats::octets
u64 octets
Definition: common.h:189
trace_params
Definition: common.h:430
trace_params::invert
unsigned char invert
Definition: common.h:437
trace_params::port
unsigned char port
Definition: common.h:438
trace_params::skip_ofst
unsigned char skip_ofst
Definition: common.h:435
trace_params::snap_len
unsigned short snap_len
Definition: common.h:433
trace_params::mask
u32 mask[TRACE_LEN/4]
Definition: common.h:432
trace_params::skip_len
unsigned char skip_len
Definition: common.h:436
trace_params::data
u32 data[TRACE_LEN/4]
Definition: common.h:431
trace_params::min_len
unsigned short min_len
Definition: common.h:434
vf_resources::r_caps
unsigned int r_caps
Definition: common.h:354
vi_info
Definition: adapter.h:198
vi_info::viid
uint16_t viid
Definition: adapter.h:210
vi_info::vfvld
uint8_t vfvld
Definition: adapter.h:213
vi_info::rss_base
uint16_t rss_base
Definition: adapter.h:216
vi_info::rss_size
uint16_t rss_size
Definition: adapter.h:215
vi_info::vin
uint16_t vin
Definition: adapter.h:212
vpd_params
Definition: common.h:278
vpd_params::sn
u8 sn[SERNUM_LEN+1]
Definition: common.h:281
vpd_params::id
u8 id[ID_LEN+1]
Definition: common.h:282
vpd_params::ec
u8 ec[EC_LEN+1]
Definition: common.h:280
vpd_params::md
u8 md[MD_LEN+1]
Definition: common.h:285
vpd_params::na
u8 na[MACADDR_LEN+1]
Definition: common.h:284
vpd_params::cclk
unsigned int cclk
Definition: common.h:279
vpd_params::pn
u8 pn[PN_LEN+1]
Definition: common.h:283
t4_read_rss_vf_config
void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, u32 *vfl, u32 *vfh, bool sleep_ok)
Definition: t4_hw.c:5994
GET_STAT_COM
#define GET_STAT_COM(name)
t4_sched_params_cl_wrr
int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, int weight, int sleep_ok)
Definition: t4_hw.c:11247
speed_to_fwcap
uint32_t speed_to_fwcap(unsigned int speed)
Definition: t4_hw.c:8850
t4_set_reg_field
void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, u32 val)
Definition: t4_hw.c:100
t4_sched_params_cl_rl_kbps
int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, int mode, unsigned int maxrate, int pktsize, int sleep_ok)
Definition: t4_hw.c:11272
t4_shutdown_adapter
int t4_shutdown_adapter(struct adapter *adapter)
Definition: t4_hw.c:9407
t4_wol_magic_enable
void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr)
Definition: t4_hw.c:7084
t4_sge_ctxt_rd_bd
int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, u32 *data)
Definition: t4_hw.c:11162
t4_get_regs
void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
Definition: t4_hw.c:824
t4_tp_get_tnl_stats
void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, bool sleep_ok)
Definition: t4_hw.c:6205
t4_get_rx_e_chan_map
static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
Definition: t4_hw.c:6833
t4_set_sched_bps
int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
Definition: t4_hw.c:6515
t4_show_intr_info
static void t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
Definition: t4_hw.c:4071
t4_config_rss_range
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, int start, int n, const u16 *rspq, unsigned int nrspq)
Definition: t4_hw.c:5565
fw_asrt
static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
Definition: t4_hw.c:233
t4_fw_upgrade
int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, const u8 *fw_data, unsigned int size, int force)
Definition: t4_hw.c:7738
t4_free_vi
int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int viid)
Definition: t4_hw.c:8049
fwcaps32_to_caps16
static uint16_t fwcaps32_to_caps16(uint32_t caps32)
Definition: t4_hw.c:3798
set_pcie_completion_timeout
static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
Definition: t4_hw.c:9256
t4_fwaddrspace_write
int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val)
Definition: t4_hw.c:7203
t4_read_cong_tbl
void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
Definition: t4_hw.c:6355
pcir_data_t
struct pcir_data_structure pcir_data_t
fwcaps16_to_caps32
static uint32_t fwcaps16_to_caps32(uint16_t caps16)
Definition: t4_hw.c:3758
t4_read_pcie_cfg4
u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
Definition: t4_hw.c:742
t4_free_mac_filt
int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, unsigned int naddr, const u8 **addr, bool sleep_ok)
Definition: t4_hw.c:8412
get_pci_mode
static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
Definition: t4_hw.c:9099
sf1_write
static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, int lock, u32 val)
Definition: t4_hw.c:3146
legacy_pci_exp_rom_header_t
struct legacy_pci_expansion_rom_header legacy_pci_exp_rom_header_t
t4_get_vpd_version
int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
Definition: t4_hw.c:3440
t4_wr_mbox_meat_timeout
int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, bool sleep_ok, int timeout)
Definition: t4_hw.c:328
t4_wait_op_done_val
static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity, int attempts, int delay, u32 *valp)
Definition: t4_hw.c:65
mem_intr_handler
static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
Definition: t4_hw.c:5020
t4_write_rss_pf_mask
void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
Definition: t4_hw.c:6111
t4_mc_read
int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
Definition: t4_hw.c:567
t4_alloc_raw_mac_filt
int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, const u8 *addr, const u8 *mask, unsigned int idx, u8 lookup_type, u8 port_id, bool sleep_ok)
Definition: t4_hw.c:8176
ma_intr_handler
static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:5110
t4_get_flash_params
int t4_get_flash_params(struct adapter *adapter)
Definition: t4_hw.c:9118
t4_fw_matches_chip
static int t4_fw_matches_chip(struct adapter *adap, const struct fw_hdr *hdr)
Definition: t4_hw.c:3543
le_intr_handler
static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4821
modify_device_id
static void modify_device_id(int device_id, u8 *boot_data)
Definition: t4_hw.c:10623
hashmask_to_filtermask
static uint16_t hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode)
Definition: t4_hw.c:9689
cplsw_intr_handler
static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4779
t4_write_flash
int t4_write_flash(struct adapter *adapter, unsigned int addr, unsigned int n, const u8 *data, int byte_oriented)
Definition: t4_hw.c:3237
t4_get_mps_bg_map
static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
Definition: t4_hw.c:6815
t4_cim_read_ma_la
void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
Definition: t4_hw.c:3716
t4_pmtx_get_stats
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
Definition: t4_hw.c:6760
t4_set_trace_filter
int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, int idx, int enable)
Definition: t4_hw.c:6638
fwcap_top_speed
uint32_t fwcap_top_speed(uint32_t caps)
Definition: t4_hw.c:8876
t4_tp_tm_pio_read
void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, bool sleep_ok)
Definition: t4_hw.c:5874
rd_rss_row
static int rd_rss_row(struct adapter *adap, int row, u32 *val)
Definition: t4_hw.c:5707
t4_seeprom_wp
int t4_seeprom_wp(struct adapter *adapter, int enable)
Definition: t4_hw.c:2949
t4_mem_read
int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, __be32 *buf)
Definition: t4_hw.c:690
t4_set_filter_cfg
int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
Definition: t4_hw.c:10912
t4_iq_free
int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int iqtype, unsigned int iqid, unsigned int fl0id, unsigned int fl1id)
Definition: t4_hw.c:8677
t4_tp_get_tcp_stats
void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, struct tp_tcp_stats *v6, bool sleep_ok)
Definition: t4_hw.c:6126
t4_cim_write
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, const unsigned int *valp)
Definition: t4_hw.c:10083
pmrx_intr_handler
static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4739
t4_idma_monitor_init
void t4_idma_monitor_init(struct adapter *adapter, struct sge_idma_monitor_state *idma)
Definition: t4_hw.c:10255
EDC_REG_T5
#define EDC_REG_T5(reg, idx)
t4_sched_config
int t4_sched_config(struct adapter *adapter, int type, int minmaxen, int sleep_ok)
Definition: t4_hw.c:11175
t4_query_params
int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, u32 *val)
Definition: t4_hw.c:7825
ma_wrap_status
static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:5093
t4_eth_eq_stop
int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid)
Definition: t4_hw.c:8706
t4_tp_fw_ldst_rw
static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, unsigned int nregs, unsigned int start_index, unsigned int rw, bool sleep_ok)
Definition: t4_hw.c:5749
t4_read_indirect
void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, u32 *vals, unsigned int nregs, unsigned int start_idx)
Definition: t4_hw.c:121
t4_sge_decode_idma_state
void t4_sge_decode_idma_state(struct adapter *adapter, int state)
Definition: t4_hw.c:7293
t4_load_fw
int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
Definition: t4_hw.c:3569
t4_get_tx_sched
void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
Definition: t4_hw.c:10433
t4_flash_erase_sectors
int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
Definition: t4_hw.c:3494
SGE_IDMA_WARN_REPEAT
#define SGE_IDMA_WARN_REPEAT
Definition: t4_hw.c:10246
t4_cim_ctl_read
int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp)
Definition: t4_hw.c:10115
t4_query_params_rw
int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, u32 *val, int rw)
Definition: t4_hw.c:7793
t4_get_tp_version
int t4_get_tp_version(struct adapter *adapter, u32 *vers)
Definition: t4_hw.c:3338
t4_read_rss
int t4_read_rss(struct adapter *adapter, u16 *map)
Definition: t4_hw.c:5721
get_mbox_rpl
static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, u32 mbox_addr)
Definition: t4_hw.c:223
t4_get_chip_params
const struct chip_params * t4_get_chip_params(int chipid)
Definition: t4_hw.c:9271
t4_set_sched_ipg
int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
Definition: t4_hw.c:6559
t4_get_rx_c_chan
static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx)
Definition: t4_hw.c:6848
t4_get_fcoe_stats
void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, struct tp_fcoe_stats *st, bool sleep_ok)
Definition: t4_hw.c:6272
FIND_VPD_KW
#define FIND_VPD_KW(var, name)
NONFATAL_IF_DISABLED
#define NONFATAL_IF_DISABLED
Definition: t4_hw.c:4048
t4_read_flash
int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented)
Definition: t4_hw.c:3198
t4_get_port_type_description
const char * t4_get_port_type_description(enum fw_port_type port_type)
Definition: t4_hw.c:6866
t4_fwcache
int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
Definition: t4_hw.c:3663
t4_write_rss_pf_map
void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
Definition: t4_hw.c:6083
t4_fw_initialize
int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
Definition: t4_hw.c:7770
handle_port_info
static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, enum fw_port_action action, bool *mod_changed, bool *link_changed)
Definition: t4_hw.c:8940
pmtx_intr_handler
static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4700
t4_read_mtu_tbl
void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
Definition: t4_hw.c:6332
sf1_read
static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, int lock, u32 *valp)
Definition: t4_hw.c:3117
read_tx_state_one
static void read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
Definition: t4_hw.c:249
t4_idma_monitor
void t4_idma_monitor(struct adapter *adapter, struct sge_idma_monitor_state *idma, int hz, int ticks)
Definition: t4_hw.c:10281
intr_alert_char
static char intr_alert_char(u32 cause, u32 enable, u32 fatal)
Definition: t4_hw.c:4060
t4_read_rss_pf_config
void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp, bool sleep_ok)
Definition: t4_hw.c:5960
t4_wr_mbox_meat
int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, bool sleep_ok)
Definition: t4_hw.c:510
t4_bar2_sge_qregs
int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset, unsigned int *pbar2_qid)
Definition: t4_hw.c:9464
get_vpd_keyword_val
static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
Definition: t4_hw.c:2963
t4_sge_ctxt_rd
int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, enum ctxt_type ctype, u32 *data)
Definition: t4_hw.c:11118
t4_tp_get_proxy_stats
void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, bool sleep_ok)
Definition: t4_hw.c:6223
pcie_intr_handler
static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4145
t4_fw_reset
int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
Definition: t4_hw.c:7624
t4_get_bs_version
int t4_get_bs_version(struct adapter *adapter, u32 *vers)
Definition: t4_hw.c:3324
t4_config_glbl_rss
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, unsigned int flags)
Definition: t4_hw.c:5653
t4_fw_bye
int t4_fw_bye(struct adapter *adap, unsigned int mbox)
Definition: t4_hw.c:7607
t4_cim_write1
static int t4_cim_write1(struct adapter *adap, unsigned int addr, unsigned int val)
Definition: t4_hw.c:10100
ulprx_intr_handler
static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4604
CAP32_TO_CAP16
#define CAP32_TO_CAP16(__cap)
t4_i2c_io
int t4_i2c_io(struct adapter *adap, unsigned int mbox, int port, unsigned int devid, unsigned int offset, unsigned int len, u8 *buf, bool write)
Definition: t4_hw.c:11042
t4_alloc_vi_func
int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, u16 *rss_size, uint8_t *vfvld, uint16_t *vin, unsigned int portfunc, unsigned int idstype)
Definition: t4_hw.c:7961
EEPROM_STAT_ADDR
#define EEPROM_STAT_ADDR
Definition: t4_hw.c:2732
T6_LE_FATAL_MASK
#define T6_LE_FATAL_MASK
Definition: t4_hw.c:4814
t4_set_params_timeout
int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, const u32 *val, int timeout)
Definition: t4_hw.c:7846
t4_mdio_rd
int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, unsigned int mmd, unsigned int reg, unsigned int *valp)
Definition: t4_hw.c:7233
t4_ctrl_eq_free
int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid)
Definition: t4_hw.c:8756
plpl_intr_handler
static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:5266
SGE_IDMA_WARN_THRESH
#define SGE_IDMA_WARN_THRESH
Definition: t4_hw.c:10245
t4_i2c_rd
int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, unsigned int devid, unsigned int offset, unsigned int len, u8 *buf)
Definition: t4_hw.c:11092
t4_ulprx_read_la
void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
Definition: t4_hw.c:3737
t4_get_version_info
int t4_get_version_info(struct adapter *adapter)
Definition: t4_hw.c:3463
t4_i2c_wr
int t4_i2c_wr(struct adapter *adap, unsigned int mbox, int port, unsigned int devid, unsigned int offset, unsigned int len, u8 *buf)
Definition: t4_hw.c:11100
t4_read_rss_key
void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
Definition: t4_hw.c:5906
t4_get_chan_txrate
void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
Definition: t4_hw.c:6606
t4_load_bootcfg
int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
Definition: t4_hw.c:10847
t4_load_mtus
void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, const unsigned short *alpha, const unsigned short *beta)
Definition: t4_hw.c:6444
t4_load_boot
int t4_load_boot(struct adapter *adap, u8 *boot_data, unsigned int boot_addr, unsigned int size)
Definition: t4_hw.c:10706
t4_get_regs_len
unsigned int t4_get_regs_len(struct adapter *adapter)
Definition: t4_hw.c:792
t4_get_scfg_version
int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
Definition: t4_hw.c:3405
mps_intr_handler
static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4877
t4_slow_intr_handler
bool t4_slow_intr_handler(struct adapter *adap, bool verbose)
Definition: t4_hw.c:5295
t4_set_addr_hash
int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, bool ucast, u64 vec, bool sleep_ok)
Definition: t4_hw.c:8546
t4_write_rss_pf_config
void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val, bool sleep_ok)
Definition: t4_hw.c:5976
t4_prep_adapter
int t4_prep_adapter(struct adapter *adapter, u32 *buf)
Definition: t4_hw.c:9334
t4_hw_pci_read_cfg4
u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
Definition: t4_hw.c:164
t4_read_rss_pf_map
u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
Definition: t4_hw.c:6067
STAT64
#define STAT64(x)
t4_edc_err_read
static int t4_edc_err_read(struct adapter *adap, int idx)
Definition: t4_hw.c:518
t4_cim_read
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp)
Definition: t4_hw.c:10056
t4_eeprom_ptov
int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
Definition: t4_hw.c:2930
t4_set_pace_tbl
int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, unsigned int start, unsigned int n)
Definition: t4_hw.c:6485
t4_filter_field_shift
int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
Definition: t4_hw.c:9828
T5_LE_FATAL_MASK
#define T5_LE_FATAL_MASK
Definition: t4_hw.c:4809
t4_alloc_vi
int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
Definition: t4_hw.c:8031
t4_handle_fw_rpl
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
Definition: t4_hw.c:9052
get_vpd_params
static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, uint16_t device_id, u32 *buf)
Definition: t4_hw.c:3007
EPIO_REG
#define EPIO_REG(name)
t4_clr_port_stats
void t4_clr_port_stats(struct adapter *adap, int idx)
Definition: t4_hw.c:11004
t5_fw_init_extern_mem
int t5_fw_init_extern_mem(struct adapter *adap)
Definition: t4_hw.c:10528
t4_update_port_info
int t4_update_port_info(struct port_info *pi)
Definition: t4_hw.c:9022
t4_config_vi_rss
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, unsigned int flags, unsigned int defq, unsigned int skeyidx, unsigned int skey)
Definition: t4_hw.c:5686
t4_mdio_wr
int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, unsigned int mmd, unsigned int reg, unsigned int val)
Definition: t4_hw.c:7267
t4_flash_bootcfg_addr
static int t4_flash_bootcfg_addr(struct adapter *adapter)
Definition: t4_hw.c:10835
t4_tp_indirect_rw
static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, u32 *buff, u32 nregs, u32 start_index, int rw, bool sleep_ok)
Definition: t4_hw.c:5793
hash_mac_addr
static int hash_mac_addr(const u8 *addr)
Definition: t4_hw.c:5538
INIT_CMD
#define INIT_CMD(var, cmd, rd_wr)
Definition: t4_hw.c:7196
t4_intr_disable
void t4_intr_disable(struct adapter *adap)
Definition: t4_hw.c:5431
t4_iq_stop
int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int iqtype, unsigned int iqid, unsigned int fl0id, unsigned int fl1id)
Definition: t4_hw.c:8646
__FBSDID
__FBSDID("$FreeBSD$")
CC_MIN_INCR
#define CC_MIN_INCR
Definition: t4_hw.c:6430
t4_edc_read
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
Definition: t4_hw.c:622
tp_intr_handler
static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4280
t4_tp_get_err_stats
void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, bool sleep_ok)
Definition: t4_hw.c:6164
MC_DATA
#define MC_DATA(i)
t4_free_raw_mac_filt
int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, const u8 *addr, const u8 *mask, unsigned int idx, u8 lookup_type, u8 port_id, bool sleep_ok)
Definition: t4_hw.c:8364
t4_configure_add_smac
int t4_configure_add_smac(struct adapter *adap)
Definition: t4_hw.c:11373
t4_config_watchdog
int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int timeout, unsigned int action)
Definition: t4_hw.c:11311
t4_seeprom_write
int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
Definition: t4_hw.c:2855
t4_read_rss_pf_mask
u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
Definition: t4_hw.c:6095
VPD_LEN
#define VPD_LEN
Definition: t4_hw.c:2736
t4_get_usm_stats
void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, bool sleep_ok)
Definition: t4_hw.c:6297
pmtx_dump_dbg_stats
static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4682
t4_load_cfg
int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
Definition: t4_hw.c:10470
t4_sched_params_ch_rl
int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, unsigned int maxrate, int sleep_ok)
Definition: t4_hw.c:11225
t4_fw_restart
int t4_fw_restart(struct adapter *adap, unsigned int mbox)
Definition: t4_hw.c:7702
t4_set_params
int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, const u32 *val)
Definition: t4_hw.c:7885
flash_wait_op
static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
Definition: t4_hw.c:3167
t4_del_mac
int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, const u8 *addr, bool smac)
Definition: t4_hw.c:11490
t4_cfg_pfvf
int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, unsigned int rxqi, unsigned int rxq, unsigned int tc, unsigned int vi, unsigned int cmask, unsigned int pmask, unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
Definition: t4_hw.c:7914
t4_enable_vi
int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, bool rx_en, bool tx_en)
Definition: t4_hw.c:8602
t4_free_encap_mac_filt
int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, bool sleep_ok)
Definition: t4_hw.c:8321
VPD_INFO_FLD_HDR_SIZE
#define VPD_INFO_FLD_HDR_SIZE
Definition: t4_hw.c:2737
lstatus_to_fwcap
static uint32_t lstatus_to_fwcap(u32 lstatus)
Definition: t4_hw.c:8906
t4_write_rss_key
void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, bool sleep_ok)
Definition: t4_hw.c:5922
FIRST_RET
#define FIRST_RET(__getvinfo)
CAP16_TO_CAP32
#define CAP16_TO_CAP32(__cap)
mac_intr_handler
static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
Definition: t4_hw.c:5207
t4_tp_pio_write
void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, u32 start_index, bool sleep_ok)
Definition: t4_hw.c:5857
sge_intr_handler
static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4303
t4_sge_ctxt_flush
int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
Definition: t4_hw.c:7452
t4_tp_get_tid_stats
void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, bool sleep_ok)
Definition: t4_hw.c:6317
CHELSIO_VPD_UNIQUE_ID
#define CHELSIO_VPD_UNIQUE_ID
Definition: t4_hw.c:2738
t4_sched_params
int t4_sched_params(struct adapter *adapter, int type, int level, int mode, int rateunit, int ratemode, int channel, int cl, int minrate, int maxrate, int weight, int pktsize, int burstsize, int sleep_ok)
Definition: t4_hw.c:11194
t4_configure_ringbb
int t4_configure_ringbb(struct adapter *adap)
Definition: t4_hw.c:11404
t4_set_devlog_level
int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
Definition: t4_hw.c:11359
BOOT_MIN_SIZE
@ BOOT_MIN_SIZE
Definition: t4_hw.c:10610
BOOT_MAX_SIZE
@ BOOT_MAX_SIZE
Definition: t4_hw.c:10611
PCIR_SIGNATURE
@ PCIR_SIGNATURE
Definition: t4_hw.c:10613
BOOT_SIZE_INC
@ BOOT_SIZE_INC
Definition: t4_hw.c:10609
VENDOR_ID
@ VENDOR_ID
Definition: t4_hw.c:10612
BOOT_FLASH_BOOT_ADDR
@ BOOT_FLASH_BOOT_ADDR
Definition: t4_hw.c:10607
BOOT_SIGNATURE
@ BOOT_SIGNATURE
Definition: t4_hw.c:10608
fec_to_fwcap
static uint32_t fec_to_fwcap(int8_t fec)
Definition: t4_hw.c:3850
PF_INTR_MASK
#define PF_INTR_MASK
Definition: t4_hw.c:5388
t4_init_devlog_params
int t4_init_devlog_params(struct adapter *adap, int fw_attach)
Definition: t4_hw.c:9538
STAT
#define STAT(x)
EEPROM_MAX_POLL
#define EEPROM_MAX_POLL
Definition: t4_hw.c:2730
t4_report_fw_error
void t4_report_fw_error(struct adapter *adap)
Definition: t4_hw.c:199
X_CIM_PF_NOACCESS
#define X_CIM_PF_NOACCESS
Definition: t4_hw.c:300
read_filter_mode_and_ingress_config
static void read_filter_mode_and_ingress_config(struct adapter *adap)
Definition: t4_hw.c:9713
t4_read_cimq_cfg
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
Definition: t4_hw.c:9931
t4_add_mac
int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac)
Definition: t4_hw.c:11539
t4_fw_hello
int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, enum dev_master master, enum dev_state *state)
Definition: t4_hw.c:7483
t4_tp_get_rdma_stats
void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, bool sleep_ok)
Definition: t4_hw.c:6256
t4_link_l1cfg
int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, struct link_config *lc)
Definition: t4_hw.c:3880
ncsi_intr_handler
static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:5181
t4_eth_eq_free
int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid)
Definition: t4_hw.c:8731
t4_alloc_mac_filt
int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, bool free, unsigned int naddr, const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
Definition: t4_hw.c:8239
t4_wol_pat_enable
int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, u64 mask0, u64 mask1, unsigned int crc, bool enable)
Definition: t4_hw.c:7125
t4_cim_read_la
int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
Definition: t4_hw.c:10131
t4_get_port_stats
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
Definition: t4_hw.c:6928
smb_intr_handler
static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:5157
t4_write_rss_vf_config
void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, u32 vfl, u32 vfh, bool sleep_ok)
Definition: t4_hw.c:6032
ulptx_intr_handler
static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4646
GET_STAT
#define GET_STAT(name)
t4_pmrx_get_stats
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
Definition: t4_hw.c:6787
VPD_BASE_OLD
#define VPD_BASE_OLD
Definition: t4_hw.c:2735
t4_change_mac
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
Definition: t4_hw.c:8494
t4_tp_pio_read
void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, bool sleep_ok)
Definition: t4_hw.c:5840
efi_pci_exp_rom_header_t
struct efi_pci_expansion_rom_header efi_pci_exp_rom_header_t
cim_intr_handler
static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
Definition: t4_hw.c:4465
chan_rate
static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
Definition: t4_hw.c:6590
t4_get_fw_version
int t4_get_fw_version(struct adapter *adapter, u32 *vers)
Definition: t4_hw.c:3297
t4_restart_aneg
int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
Definition: t4_hw.c:4022
t4_enable_vi_params
int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
Definition: t4_hw.c:8575
TEST_SPEED_RETURN
#define TEST_SPEED_RETURN(__caps_speed, __speed)
t4_get_lb_stats
void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
Definition: t4_hw.c:7033
CIM_PBT_ADDR_BASE
@ CIM_PBT_ADDR_BASE
Definition: t4_hw.c:10042
CIM_QCTL_BASE
@ CIM_QCTL_BASE
Definition: t4_hw.c:10040
CIM_PBT_LRF_BASE
@ CIM_PBT_LRF_BASE
Definition: t4_hw.c:10043
CIM_CTL_BASE
@ CIM_CTL_BASE
Definition: t4_hw.c:10041
CIM_PBT_DATA_BASE
@ CIM_PBT_DATA_BASE
Definition: t4_hw.c:10044
t4_seeprom_read
int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
Definition: t4_hw.c:2800
t4_fw_halt
int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
Definition: t4_hw.c:7650
t4_read_pace_tbl
void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
Definition: t4_hw.c:10413
t4_get_devlog_level
int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
Definition: t4_hw.c:11341
t4_seeprom_wait
static int t4_seeprom_wait(struct adapter *adapter)
Definition: t4_hw.c:2747
t4_tp_read_la
void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
Definition: t4_hw.c:10200
t4_tp_wr_bits_indirect
void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, unsigned int mask, unsigned int val)
Definition: t4_hw.c:6377
t4_cim_read_pif_la
void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr)
Definition: t4_hw.c:3682
t4_write_indirect
void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, const u32 *vals, unsigned int nregs, unsigned int start_idx)
Definition: t4_hw.c:144
check_tx_state
static void check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
Definition: t4_hw.c:275
t4_tp_mib_read
void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, bool sleep_ok)
Definition: t4_hw.c:5891
t4_set_rxmode
int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, int mtu, int promisc, int all_multi, int bcast, int vlanex, bool sleep_ok)
Definition: t4_hw.c:8080
fwcap_to_speed
unsigned int fwcap_to_speed(uint32_t caps)
Definition: t4_hw.c:8824
pci_exp_rom_header_t
struct pci_expansion_rom_header pci_exp_rom_header_t
t4_port_init
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
Definition: t4_hw.c:9874
t4_handle_intr
static bool t4_handle_intr(struct adapter *adap, const struct intr_info *ii, u32 additional_cause, bool verbose)
Definition: t4_hw.c:4104
EDC_DATA
#define EDC_DATA(i)
t4_get_port_stats_offset
void t4_get_port_stats_offset(struct adapter *adap, int idx, struct port_stats *stats, struct port_stats *offset)
Definition: t4_hw.c:6906
t4_init_tp_params
int t4_init_tp_params(struct adapter *adap)
Definition: t4_hw.c:9779
t4_init_sge_params
int t4_init_sge_params(struct adapter *adapter)
Definition: t4_hw.c:9603
t4_link_down_rc_str
const char * t4_link_down_rc_str(unsigned char link_down_rc)
Definition: t4_hw.c:8802
t4_intr_enable
void t4_intr_enable(struct adapter *adap)
Definition: t4_hw.c:5403
t4_intr_clear
void t4_intr_clear(struct adapter *adap)
Definition: t4_hw.c:5445
read_tx_state
static void read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
Definition: t4_hw.c:266
init_cong_ctrl
static void init_cong_ctrl(unsigned short *a, unsigned short *b)
Definition: t4_hw.c:6392
t4_get_fw_hdr
int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
Definition: t4_hw.c:3311
t4_wait_op_done
static int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, int polarity, int attempts, int delay)
Definition: t4_hw.c:83
t4_read_cim_obq
int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
Definition: t4_hw.c:10008
t4_get_exprom_version
int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
Definition: t4_hw.c:3355
t4_ofld_eq_free
int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid)
Definition: t4_hw.c:8781
t4_set_vf_mac
int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, unsigned int naddr, u8 *addr)
Definition: t4_hw.c:10372
t4_read_cim_ibq
int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
Definition: t4_hw.c:9966
t4_mk_filtdelwr
void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
Definition: t4_hw.c:7183
t4_set_vlan_acl
int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, u16 vlan)
Definition: t4_hw.c:11447
fwcap_to_fec
static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none)
Definition: t4_hw.c:3830
SF_WR_ENABLE
@ SF_WR_ENABLE
Definition: t4_hw.c:3099
SF_PROG_PAGE
@ SF_PROG_PAGE
Definition: t4_hw.c:3096
SF_RD_DATA_FAST
@ SF_RD_DATA_FAST
Definition: t4_hw.c:3100
SF_RD_STATUS
@ SF_RD_STATUS
Definition: t4_hw.c:3098
SF_ATTEMPTS
@ SF_ATTEMPTS
Definition: t4_hw.c:3093
SF_RD_ID
@ SF_RD_ID
Definition: t4_hw.c:3101
SF_WR_DISABLE
@ SF_WR_DISABLE
Definition: t4_hw.c:3097
SF_ERASE_SECTOR
@ SF_ERASE_SECTOR
Definition: t4_hw.c:3102
t4_flash_cfg_addr
int t4_flash_cfg_addr(struct adapter *adapter)
Definition: t4_hw.c:3525
T6_LE_PERRCRC_MASK
#define T6_LE_PERRCRC_MASK
Definition: t4_hw.c:4810
t4_identify_port
int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, unsigned int nblinks)
Definition: t4_hw.c:8617
t4_get_trace_filter
void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, int *enabled)
Definition: t4_hw.c:6718
VPD_BASE
#define VPD_BASE
Definition: t4_hw.c:2734
msleep
#define msleep(x)
Definition: t4_hw.c:43
EEPROM_DELAY
#define EEPROM_DELAY
Definition: t4_hw.c:2729
t4_alloc_encap_mac_filt
int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, const u8 *addr, const u8 *mask, unsigned int vni, unsigned int vni_mask, u8 dip_hit, u8 lookup_type, bool sleep_ok)
Definition: t4_hw.c:8128
t4_tp_get_cpl_stats
void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, bool sleep_ok)
Definition: t4_hw.c:6239
I2C_PAGE_SIZE
#define I2C_PAGE_SIZE
Definition: t4_hw.h:307
MBOX_LEN
@ MBOX_LEN
Definition: t4_hw.h:54
EEPROMSIZE
@ EEPROMSIZE
Definition: t4_hw.h:42
TRACE_LEN
@ TRACE_LEN
Definition: t4_hw.h:56
FILTER_OPT_LEN
@ FILTER_OPT_LEN
Definition: t4_hw.h:57
NCCTRL_WIN
@ NCCTRL_WIN
Definition: t4_hw.h:49
T6_RSS_NENTRIES
@ T6_RSS_NENTRIES
Definition: t4_hw.h:46
MAX_NCHAN
@ MAX_NCHAN
Definition: t4_hw.h:40
EEPROMVSIZE
@ EEPROMVSIZE
Definition: t4_hw.h:43
T5_FILTER_OPT_LEN
@ T5_FILTER_OPT_LEN
Definition: t4_hw.h:58
NCHAN
@ NCHAN
Definition: t4_hw.h:38
NMTUS
@ NMTUS
Definition: t4_hw.h:48
T6_NCHAN
@ T6_NCHAN
Definition: t4_hw.h:39
RSS_NENTRIES
@ RSS_NENTRIES
Definition: t4_hw.h:45
NTRACE
@ NTRACE
Definition: t4_hw.h:55
T6_PM_NSTATS
@ T6_PM_NSTATS
Definition: t4_hw.h:52
PM_NSTATS
@ PM_NSTATS
Definition: t4_hw.h:51
NTX_SCHED
@ NTX_SCHED
Definition: t4_hw.h:50
FLASH_MIN_SIZE
@ FLASH_MIN_SIZE
Definition: t4_hw.h:281
FLASH_FW_START
@ FLASH_FW_START
Definition: t4_hw.h:242
FLASH_BOOTCFG_START
@ FLASH_BOOTCFG_START
Definition: t4_hw.h:234
FLASH_FWBOOTSTRAP_MAX_SIZE
@ FLASH_FWBOOTSTRAP_MAX_SIZE
Definition: t4_hw.h:251
FLASH_CFG_START
@ FLASH_CFG_START
Definition: t4_hw.h:274
FLASH_CFG_MAX_SIZE
@ FLASH_CFG_MAX_SIZE
Definition: t4_hw.h:275
FLASH_EXP_ROM_START
@ FLASH_EXP_ROM_START
Definition: t4_hw.h:217
FLASH_FW_MAX_SIZE
@ FLASH_FW_MAX_SIZE
Definition: t4_hw.h:243
FLASH_FWBOOTSTRAP_START
@ FLASH_FWBOOTSTRAP_START
Definition: t4_hw.h:250
FLASH_FWBOOTSTRAP_START_SEC
@ FLASH_FWBOOTSTRAP_START_SEC
Definition: t4_hw.h:248
FLASH_BOOTCFG_MAX_SIZE
@ FLASH_BOOTCFG_MAX_SIZE
Definition: t4_hw.h:235
FLASH_FW_START_SEC
@ FLASH_FW_START_SEC
Definition: t4_hw.h:240
SF_PAGE_SIZE
@ SF_PAGE_SIZE
Definition: t4_hw.h:81
SF_SEC_SIZE
@ SF_SEC_SIZE
Definition: t4_hw.h:82
SGE_FLBUF_SIZES
@ SGE_FLBUF_SIZES
Definition: t4_hw.h:99
CIM_NUM_OBQ
@ CIM_NUM_OBQ
Definition: t4_hw.h:69
CIM_NUM_OBQ_T5
@ CIM_NUM_OBQ_T5
Definition: t4_hw.h:70
CIMLA_SIZE
@ CIMLA_SIZE
Definition: t4_hw.h:71
CIM_NUM_IBQ
@ CIM_NUM_IBQ
Definition: t4_hw.h:68
CIM_PIFLA_SIZE
@ CIM_PIFLA_SIZE
Definition: t4_hw.h:72
ULPRX_LA_SIZE
@ ULPRX_LA_SIZE
Definition: t4_hw.h:77
TPLA_SIZE
@ TPLA_SIZE
Definition: t4_hw.h:76
CIM_IBQ_SIZE
@ CIM_IBQ_SIZE
Definition: t4_hw.h:74
CIM_MALA_SIZE
@ CIM_MALA_SIZE
Definition: t4_hw.h:73
ctxt_type
ctxt_type
Definition: t4_hw.h:86
CTXT_INGRESS
@ CTXT_INGRESS
Definition: t4_hw.h:86
CTXT_EGRESS
@ CTXT_EGRESS
Definition: t4_hw.h:86
CTXT_FLM
@ CTXT_FLM
Definition: t4_hw.h:86
port
int port
Definition: t4_if.m:63
BCAST
@ BCAST
Definition: t4_ioctl.h:154
t4_regs.h
A_TP_VLAN_PRI_MAP
#define A_TP_VLAN_PRI_MAP
Definition: t4_regs.h:26787
G_INGPACKBOUNDARY
#define G_INGPACKBOUNDARY(x)
Definition: t4_regs.h:2313
S_QUEUESPERPAGEPF1
#define S_QUEUESPERPAGEPF1
Definition: t4_regs.h:716
A_SGE_DEBUG_DATA_LOW
#define A_SGE_DEBUG_DATA_LOW
Definition: t4_regs.h:1849
F_ERR_DATA_CPL_ON_HIGH_QID1
#define F_ERR_DATA_CPL_ON_HIGH_QID1
Definition: t4_regs.h:1172
F_TFTP
#define F_TFTP
Definition: t4_regs.h:6670
G_PMMAXXFERLEN1
#define G_PMMAXXFERLEN1(x)
Definition: t4_regs.h:22726
A_PCIE_CFG_SPACE_REQ
#define A_PCIE_CFG_SPACE_REQ
Definition: t4_regs.h:4828
A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE
#define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE
Definition: t4_regs.h:6198
M_TXDESCFIFO
#define M_TXDESCFIFO
Definition: t4_regs.h:32738
F_IBQTP1PARERR
#define F_IBQTP1PARERR
Definition: t4_regs.h:20504
A_PCIE_FW_PF
#define A_PCIE_FW_PF
Definition: t4_regs.h:5006
T5_PORT_REG
#define T5_PORT_REG(idx, reg)
Definition: t4_regs.h:288
F_TXFIFO_PRTY_ERR
#define F_TXFIFO_PRTY_ERR
Definition: t4_regs.h:39990
F_NCSI2CIMINTFPARERR
#define F_NCSI2CIMINTFPARERR
Definition: t4_regs.h:20568
A_MPS_PORT_STAT_RX_PORT_BYTES_L
#define A_MPS_PORT_STAT_RX_PORT_BYTES_L
Definition: t4_regs.h:32342
G_TFLENGTH
#define G_TFLENGTH(x)
Definition: t4_regs.h:33858
F_MAC0
#define F_MAC0
Definition: t4_regs.h:38067
V_CTXTTYPE
#define V_CTXTTYPE(x)
Definition: t4_regs.h:2638
A_TP_MIB_TCP_IN_ERR_0
#define A_TP_MIB_TCP_IN_ERR_0
Definition: t4_regs.h:28678
F_CLIPSUBERR
#define F_CLIPSUBERR
Definition: t4_regs.h:38932
V_TPFIFO
#define V_TPFIFO(x)
Definition: t4_regs.h:32753
G_TIMERVALUE4
#define G_TIMERVALUE4(x)
Definition: t4_regs.h:1730
F_PROTOCOL
#define F_PROTOCOL
Definition: t4_regs.h:26807
F_MPS_DM_PRTY_ERR
#define F_MPS_DM_PRTY_ERR
Definition: t4_regs.h:39966
F_MA_CIM_INTFPERR
#define F_MA_CIM_INTFPERR
Definition: t4_regs.h:20560
F_ERR_DROPPED_DB
#define F_ERR_DROPPED_DB
Definition: t4_regs.h:1168
F_IBQDBGBUSY
#define F_IBQDBGBUSY
Definition: t4_regs.h:20971
F_MSIXDATAPERR
#define F_MSIXDATAPERR
Definition: t4_regs.h:4189
F_KEYEXTEND
#define F_KEYEXTEND
Definition: t4_regs.h:23498
F_BUNDLE_LEN_PARERR
#define F_BUNDLE_LEN_PARERR
Definition: t4_regs.h:29838
A_PCIE_NONFAT_ERR
#define A_PCIE_NONFAT_ERR
Definition: t4_regs.h:4312
A_SGE_INT_CAUSE4
#define A_SGE_INT_CAUSE4
Definition: t4_regs.h:1851
F_ECC_UE_INT_CAUSE
#define F_ECC_UE_INT_CAUSE
Definition: t4_regs.h:15916
A_PCIE_FW
#define A_PCIE_FW
Definition: t4_regs.h:5005
A_MC_INT_CAUSE
#define A_MC_INT_CAUSE
Definition: t4_regs.h:15912
F_PIORST
#define F_PIORST
Definition: t4_regs.h:38162
V_PILADBGRDPTR
#define V_PILADBGRDPTR(x)
Definition: t4_regs.h:21007
A_SGE_INGRESS_QUEUES_PER_PAGE_PF
#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF
Definition: t4_regs.h:2053
A_TP_RSS_PF0_CONFIG
#define A_TP_RSS_PF0_CONFIG
Definition: t4_regs.h:24913
F_ECC_CE_INT_CAUSE
#define F_ECC_CE_INT_CAUSE
Definition: t4_regs.h:15920
A_MAC_PORT_INT_CAUSE
#define A_MAC_PORT_INT_CAUSE
Definition: t4_regs.h:46386
F_T6_LIP0
#define F_T6_LIP0
Definition: t4_regs.h:39078
A_SGE_DEBUG_DATA_HIGH_INDEX_10
#define A_SGE_DEBUG_DATA_HIGH_INDEX_10
Definition: t4_regs.h:3286
A_PL_PF_INT_ENABLE
#define A_PL_PF_INT_ENABLE
Definition: t4_regs.h:37889
G_CHIPID
#define G_CHIPID(x)
Definition: t4_regs.h:37868
A_SGE_CTXT_CMD
#define A_SGE_CTXT_CMD
Definition: t4_regs.h:2625
A_SGE_CONM_CTRL
#define A_SGE_CONM_CTRL
Definition: t4_regs.h:1431
F_RXWRPERR
#define F_RXWRPERR
Definition: t4_regs.h:4109
M_PILADBGRDPTR
#define M_PILADBGRDPTR
Definition: t4_regs.h:21006
A_MAC_PORT_CFG
#define A_MAC_PORT_CFG
Definition: t4_regs.h:45127
A_TP_TX_TRATE
#define A_TP_TX_TRATE
Definition: t4_regs.h:24260
A_CIM_HOST_INT_CAUSE
#define A_CIM_HOST_INT_CAUSE
Definition: t4_regs.h:20598
F_PERR_INT_CAUSE
#define F_PERR_INT_CAUSE
Definition: t4_regs.h:15924
A_CIM_HOST_INT_ENABLE
#define A_CIM_HOST_INT_ENABLE
Definition: t4_regs.h:20480
A_MAC_PORT_MAGIC_MACID_LO
#define A_MAC_PORT_MAGIC_MACID_LO
Definition: t4_regs.h:45482
A_TP_RSS_SECRET_KEY0
#define A_TP_RSS_SECRET_KEY0
Definition: t4_regs.h:25155
A_MPS_PORT_STAT_RX_PORT_LESS_64B_H
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H
Definition: t4_regs.h:32395
F_LIP0
#define F_LIP0
Definition: t4_regs.h:38888
A_SGE_INT_ENABLE1
#define A_SGE_INT_ENABLE1
Definition: t4_regs.h:946
A_EDC_H_BIST_STATUS_RDATA
#define A_EDC_H_BIST_STATUS_RDATA
Definition: t4_regs.h:61865
G_PKTSHIFT
#define G_PKTSHIFT(x)
Definition: t4_regs.h:621
F_CREQPERR
#define F_CREQPERR
Definition: t4_regs.h:4165
F_INGRESS_SIZE_ERR
#define F_INGRESS_SIZE_ERR
Definition: t4_regs.h:1220
F_PERRVFID
#define F_PERRVFID
Definition: t4_regs.h:38202
V_DBGLARPTR
#define V_DBGLARPTR(x)
Definition: t4_regs.h:24313
A_MC_P_BIST_CMD_ADDR
#define A_MC_P_BIST_CMD_ADDR
Definition: t4_regs.h:58482
A_MPS_TRC_INT_ENABLE
#define A_MPS_TRC_INT_ENABLE
Definition: t4_regs.h:33944
F_TOS
#define F_TOS
Definition: t4_regs.h:26811
G_MTUVALUE
#define G_MTUVALUE(x)
Definition: t4_regs.h:23116
G_POLADBGWRPTR
#define G_POLADBGWRPTR(x)
Definition: t4_regs.h:21045
V_ROWINDEX
#define V_ROWINDEX(x)
Definition: t4_regs.h:23093
A_PM_RX_INT_ENABLE
#define A_PM_RX_INT_ENABLE
Definition: t4_regs.h:29730
A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR
#define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR
Definition: t4_regs.h:24389
F_BLKWREEPROMINT
#define F_BLKWREEPROMINT
Definition: t4_regs.h:20806
F_ERR_PCIE_ERROR3
#define F_ERR_PCIE_ERROR3
Definition: t4_regs.h:1132
A_SGE_INT_CAUSE5
#define A_SGE_INT_CAUSE5
Definition: t4_regs.h:2118
A_TP_CCTRL_TABLE
#define A_TP_CCTRL_TABLE
Definition: t4_regs.h:23089
F_BUNDLE_LEN_OVFL
#define F_BUNDLE_LEN_OVFL
Definition: t4_regs.h:29842
F_DBG
#define F_DBG
Definition: t4_regs.h:38020
F_PERR_CPL_128TO128_1
#define F_PERR_CPL_128TO128_1
Definition: t4_regs.h:35984
A_SGE_ITP_CONTROL
#define A_SGE_ITP_CONTROL
Definition: t4_regs.h:1680
F_TRGT1GRPPERR
#define F_TRGT1GRPPERR
Definition: t4_regs.h:4221
A_TP_MIB_TCP_RXT_SEG_LO
#define A_TP_MIB_TCP_RXT_SEG_LO
Definition: t4_regs.h:28688
F_MI
#define F_MI
Definition: t4_regs.h:38016
A_PM_TX_STAT_LSB
#define A_PM_TX_STAT_LSB
Definition: t4_regs.h:30482
F_T6_ACTRGNFULL
#define F_T6_ACTRGNFULL
Definition: t4_regs.h:39054
G_TNLRATE3
#define G_TNLRATE3(x)
Definition: t4_regs.h:24265
G_OFDRATE1
#define G_OFDRATE1(x)
Definition: t4_regs.h:24249
G_REV
#define G_REV(x)
Definition: t4_regs.h:38215
V_TFOFFSET
#define V_TFOFFSET(x)
Definition: t4_regs.h:33862
F_ERR_DATA_CPL_ON_HIGH_QID0
#define F_ERR_DATA_CPL_ON_HIGH_QID0
Definition: t4_regs.h:1176
F_UART
#define F_UART
Definition: t4_regs.h:37916
F_RNPP
#define F_RNPP
Definition: t4_regs.h:6154
A_EDC_BIST_CMD_LEN
#define A_EDC_BIST_CMD_LEN
Definition: t4_regs.h:20292
F_MEM_TO_INT_CAUSE
#define F_MEM_TO_INT_CAUSE
Definition: t4_regs.h:16321
F_ERR_ING_PCIE_CHAN
#define F_ERR_ING_PCIE_CHAN
Definition: t4_regs.h:1196
G_MTUWIDTH
#define G_MTUWIDTH(x)
Definition: t4_regs.h:23111
V_TFLENGTH
#define V_TFLENGTH(x)
Definition: t4_regs.h:33857
NUM_MPS_T5_CLS_SRAM_L_INSTANCES
#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES
Definition: t4_regs.h:318
V_DATALKPTYPE
#define V_DATALKPTYPE(x)
Definition: t4_regs.h:34637
F_SE_CNT_MISMATCH_1
#define F_SE_CNT_MISMATCH_1
Definition: t4_regs.h:36970
V_MAGICEN
#define V_MAGICEN(x)
Definition: t4_regs.h:40764
F_TIMEOUTMAINT
#define F_TIMEOUTMAINT
Definition: t4_regs.h:20758
A_CIM_PF_HOST_INT_ENABLE
#define A_CIM_PF_HOST_INT_ENABLE
Definition: t4_regs.h:20376
A_CIM_QUEUE_CONFIG_REF
#define A_CIM_QUEUE_CONFIG_REF
Definition: t4_regs.h:20890
PCIE_FW_REG
#define PCIE_FW_REG(reg_addr, idx)
Definition: t4_regs.h:124
F_FATALPERR
#define F_FATALPERR
Definition: t4_regs.h:38186
A_MA_INT_WRAP_STATUS
#define A_MA_INT_WRAP_STATUS
Definition: t4_regs.h:16323
M_TXTIMERSEPQ1
#define M_TXTIMERSEPQ1
Definition: t4_regs.h:24392
F_SGLRDEEPROMINT
#define F_SGLRDEEPROMINT
Definition: t4_regs.h:20818
F_IBQULPPARERR
#define F_IBQULPPARERR
Definition: t4_regs.h:20508
G_TFOFFSET
#define G_TFOFFSET(x)
Definition: t4_regs.h:33863
A_PL_REV
#define A_PL_REV
Definition: t4_regs.h:38210
A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L
#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L
Definition: t4_regs.h:33689
F_LOCALCFG
#define F_LOCALCFG
Definition: t4_regs.h:4840
A_TP_MIB_HDR_IN_ERR_0
#define A_TP_MIB_HDR_IN_ERR_0
Definition: t4_regs.h:28674
A_MPS_TX_INT_ENABLE
#define A_MPS_TX_INT_ENABLE
Definition: t4_regs.h:32719
G_OFDRATE0
#define G_OFDRATE0(x)
Definition: t4_regs.h:24254
A_CIM_DEBUGCFG
#define A_CIM_DEBUGCFG
Definition: t4_regs.h:20998
F_MATCHSRAM
#define F_MATCHSRAM
Definition: t4_regs.h:34249
F_SECNTERR
#define F_SECNTERR
Definition: t4_regs.h:32731
G_TNLRATE2
#define G_TNLRATE2(x)
Definition: t4_regs.h:24270
G_THRESHOLD_1
#define G_THRESHOLD_1(x)
Definition: t4_regs.h:1489
A_EDC_INT_ENABLE
#define A_EDC_INT_ENABLE
Definition: t4_regs.h:20310
V_BIST_CMD_GAP
#define V_BIST_CMD_GAP(x)
Definition: t4_regs.h:16000
F_ILLWRINT
#define F_ILLWRINT
Definition: t4_regs.h:20866
V_OP
#define V_OP(x)
Definition: t4_regs.h:36601
A_TP_RSS_CONFIG_VRT
#define A_TP_RSS_CONFIG_VRT
Definition: t4_regs.h:23429
F_ULP_RX
#define F_ULP_RX
Definition: t4_regs.h:37936
F_TCAP
#define F_TCAP
Definition: t4_regs.h:6674
F_DCNTPERR
#define F_DCNTPERR
Definition: t4_regs.h:4157
F_OTDD
#define F_OTDD
Definition: t4_regs.h:6694
A_UP_UP_DBG_LA_DATA
#define A_UP_UP_DBG_LA_DATA
Definition: t4_regs.h:44307
A_CIM_PO_LA_DEBUGDATA
#define A_CIM_PO_LA_DEBUGDATA
Definition: t4_regs.h:21052
M_DATALKPTYPE
#define M_DATALKPTYPE
Definition: t4_regs.h:34636
A_MC_P_ECC_STATUS
#define A_MC_P_ECC_STATUS
Definition: t4_regs.h:58380
F_MEM_PERR_INT_CAUSE
#define F_MEM_PERR_INT_CAUSE
Definition: t4_regs.h:16313
PORT_REG
#define PORT_REG(idx, reg)
Definition: t4_regs.h:101
G_UPDBGLAWRPTR
#define G_UPDBGLAWRPTR(x)
Definition: t4_regs.h:44288
A_MPS_TRC_CFG
#define A_MPS_TRC_CFG
Definition: t4_regs.h:33787
A_CIM_PF_MAILBOX_CTRL
#define A_CIM_PF_MAILBOX_CTRL
Definition: t4_regs.h:20350
A_TP_MIB_USM_PKTS
#define A_TP_MIB_USM_PKTS
Definition: t4_regs.h:28754
F_VFRDEN
#define F_VFRDEN
Definition: t4_regs.h:23437
A_ULP_TX_INT_CAUSE_2
#define A_ULP_TX_INT_CAUSE_2
Definition: t4_regs.h:29388
F_EPIOWR
#define F_EPIOWR
Definition: t4_regs.h:40946
A_MPS_INT_CAUSE
#define A_MPS_INT_CAUSE
Definition: t4_regs.h:32456
V_TFMINPKTSIZE
#define V_TFMINPKTSIZE(x)
Definition: t4_regs.h:33894
F_ETHERTYPE
#define F_ETHERTYPE
Definition: t4_regs.h:26803
F_ILLRDINT
#define F_ILLRDINT
Definition: t4_regs.h:20862
A_MPS_TX_INT_CAUSE
#define A_MPS_TX_INT_CAUSE
Definition: t4_regs.h:32756
A_PL_INT_CAUSE
#define A_PL_INT_CAUSE
Definition: t4_regs.h:38043
F_ZERO_E_CMD_ERROR
#define F_ZERO_E_CMD_ERROR
Definition: t4_regs.h:29734
F_HREQRDPERR
#define F_HREQRDPERR
Definition: t4_regs.h:4253
F_BLKWRCTLINT
#define F_BLKWRCTLINT
Definition: t4_regs.h:20790
F_ZERO_SWITCH_ERROR
#define F_ZERO_SWITCH_ERROR
Definition: t4_regs.h:35980
V_REGISTER
#define V_REGISTER(x)
Definition: t4_regs.h:4864
F_PARITYERR
#define F_PARITYERR
Definition: t4_regs.h:38880
A_ULP_TX_INT_ENABLE
#define A_ULP_TX_INT_ENABLE
Definition: t4_regs.h:28859
F_SGE
#define F_SGE
Definition: t4_regs.h:37924
A_TP_RSS_PF_MAP
#define A_TP_RSS_PF_MAP
Definition: t4_regs.h:25012
A_PCIE_INT_ENABLE
#define A_PCIE_INT_ENABLE
Definition: t4_regs.h:4085
A_SGE_DEBUG_INDEX
#define A_SGE_DEBUG_INDEX
Definition: t4_regs.h:1847
F_DRSPPERR
#define F_DRSPPERR
Definition: t4_regs.h:4149
M_PKTFIFO
#define M_PKTFIFO
Definition: t4_regs.h:33935
F_OBQSGERX1PARERR
#define F_OBQSGERX1PARERR
Definition: t4_regs.h:20584
F_T5_TFINVERTMATCH
#define F_T5_TFINVERTMATCH
Definition: t4_regs.h:33875
F_CAUSE_CTX_1
#define F_CAUSE_CTX_1
Definition: t4_regs.h:36980
F_OBQULP1PARERR
#define F_OBQULP1PARERR
Definition: t4_regs.h:20528
V_TXTIMERSEPQ0
#define V_TXTIMERSEPQ0(x)
Definition: t4_regs.h:24398
F_SDC_ERR
#define F_SDC_ERR
Definition: t4_regs.h:29846
F_RSVDSPACEINT
#define F_RSVDSPACEINT
Definition: t4_regs.h:20874
F_ERR_FLM_DBP
#define F_ERR_FLM_DBP
Definition: t4_regs.h:1116
F_RXFIFO_PRTY_ERR
#define F_RXFIFO_PRTY_ERR
Definition: t4_regs.h:39994
A_SGE_CONTROL2
#define A_SGE_CONTROL2
Definition: t4_regs.h:2296
F_IPGRPPERR
#define F_IPGRPPERR
Definition: t4_regs.h:4213
A_TP_PARA_REG7
#define A_TP_PARA_REG7
Definition: t4_regs.h:22721
NUM_MPS_CLS_SRAM_L_INSTANCES
#define NUM_MPS_CLS_SRAM_L_INSTANCES
Definition: t4_regs.h:191
F_SGLRDCTLINT
#define F_SGLRDCTLINT
Definition: t4_regs.h:20802
A_PL_PF_INT_CAUSE
#define A_PL_PF_INT_CAUSE
Definition: t4_regs.h:37871
F_ERR_BAD_DB_PIDX3
#define F_ERR_BAD_DB_PIDX3
Definition: t4_regs.h:1180
F_OBQULP0PARERR
#define F_OBQULP0PARERR
Definition: t4_regs.h:20524
F_UPDBGLAEN
#define F_UPDBGLAEN
Definition: t4_regs.h:44301
A_CIM_OBQ_DBG_CFG
#define A_CIM_OBQ_DBG_CFG
Definition: t4_regs.h:20977
F_BLKWRPLINT
#define F_BLKWRPLINT
Definition: t4_regs.h:20774
M_DBGLARPTR
#define M_DBGLARPTR
Definition: t4_regs.h:24312
F_PIORSTMODE
#define F_PIORSTMODE
Definition: t4_regs.h:38166
M_POLADBGRDPTR
#define M_POLADBGRDPTR
Definition: t4_regs.h:21001
A_MPS_STAT_PERR_INT_CAUSE_SRAM
#define A_MPS_STAT_PERR_INT_CAUSE_SRAM
Definition: t4_regs.h:33610
F_MISCPERR
#define F_MISCPERR
Definition: t4_regs.h:33932
A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L
#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L
Definition: t4_regs.h:33705
F_CFGSNPPERR
#define F_CFGSNPPERR
Definition: t4_regs.h:4133
F_PORTTXEN
#define F_PORTTXEN
Definition: t4_regs.h:31358
F_REG_ADDRESS_ERR
#define F_REG_ADDRESS_ERR
Definition: t4_regs.h:1216
F_RCCP
#define F_RCCP
Definition: t4_regs.h:6166
F_ERR_PCIE_ERROR1
#define F_ERR_PCIE_ERROR1
Definition: t4_regs.h:1140
A_MAC_PORT_CFG2
#define A_MAC_PORT_CFG2
Definition: t4_regs.h:45423
S_QUEUESPERPAGEPF0
#define S_QUEUESPERPAGEPF0
Definition: t4_regs.h:721
F_SMB
#define F_SMB
Definition: t4_regs.h:37996
A_MPS_PORT_STAT_TX_PORT_PPP7_H
#define A_MPS_PORT_STAT_TX_PORT_PPP7_H
Definition: t4_regs.h:32312
F_FLMTXFLSTEMPTY
#define F_FLMTXFLSTEMPTY
Definition: t4_regs.h:23762
F_SGLWRCTLINT
#define F_SGLWRCTLINT
Definition: t4_regs.h:20798
F_BLKWRBOOTINT
#define F_BLKWRBOOTINT
Definition: t4_regs.h:20838
F_T6_LIPMISS
#define F_T6_LIPMISS
Definition: t4_regs.h:39082
M_VFWRADDR
#define M_VFWRADDR
Definition: t4_regs.h:23461
A_PM_TX_INT_CAUSE
#define A_PM_TX_INT_CAUSE
Definition: t4_regs.h:30618
F_OBQNCSIPARERR
#define F_OBQNCSIPARERR
Definition: t4_regs.h:20544
A_SF_OP
#define A_SF_OP
Definition: t4_regs.h:37805
M_TFOFFSET
#define M_TFOFFSET
Definition: t4_regs.h:33861
A_SGE_CTXT_DATA5
#define A_SGE_CTXT_DATA5
Definition: t4_regs.h:2651
A_MC_P_BIST_DATA_PATTERN
#define A_MC_P_BIST_DATA_PATTERN
Definition: t4_regs.h:58484
G_PMMAXXFERLEN0
#define G_PMMAXXFERLEN0(x)
Definition: t4_regs.h:22731
A_PM_RX_INT_CAUSE
#define A_PM_RX_INT_CAUSE
Definition: t4_regs.h:29848
F_T6_ENABLE
#define F_T6_ENABLE
Definition: t4_regs.h:4892
F_TNPP
#define F_TNPP
Definition: t4_regs.h:6666
F_RXCPLPERR
#define F_RXCPLPERR
Definition: t4_regs.h:4113
G_THRESHOLD_2
#define G_THRESHOLD_2(x)
Definition: t4_regs.h:1494
A_PM_TX_INT_ENABLE
#define A_PM_TX_INT_ENABLE
Definition: t4_regs.h:30492
A_TP_INT_ENABLE
#define A_TP_INT_ENABLE
Definition: t4_regs.h:23758
S_HOSTPAGESIZEPF0
#define S_HOSTPAGESIZEPF0
Definition: t4_regs.h:679
A_SGE_INT_CAUSE3
#define A_SGE_INT_CAUSE3
Definition: t4_regs.h:1112
F_HSSPLLBYPB
#define F_HSSPLLBYPB
Definition: t4_regs.h:46684
F_VFIDPERR
#define F_VFIDPERR
Definition: t4_regs.h:4249
F_MA_INTF_SDC_ERR
#define F_MA_INTF_SDC_ERR
Definition: t4_regs.h:29834
F_MC1
#define F_MC1
Definition: t4_regs.h:38032
F_ERR_INVALID_CIDX_INC
#define F_ERR_INVALID_CIDX_INC
Definition: t4_regs.h:1156
F_PORTERR
#define F_PORTERR
Definition: t4_regs.h:32723
F_HASHTBLACCFAIL
#define F_HASHTBLACCFAIL
Definition: t4_regs.h:39020
S_FCOE
#define S_FCOE
Definition: t4_regs.h:26825
F_ERR_BAD_DB_PIDX2
#define F_ERR_BAD_DB_PIDX2
Definition: t4_regs.h:1184
A_EDC_BIST_DATA_PATTERN
#define A_EDC_BIST_DATA_PATTERN
Definition: t4_regs.h:20293
F_CLCAMFIFOERR
#define F_CLCAMFIFOERR
Definition: t4_regs.h:38936
F_DB_OPTIONS_PAR_ERROR
#define F_DB_OPTIONS_PAR_ERROR
Definition: t4_regs.h:29814
F_HMA
#define F_HMA
Definition: t4_regs.h:37928
M_TFLENGTH
#define M_TFLENGTH
Definition: t4_regs.h:33856
F_SF
#define F_SF
Definition: t4_regs.h:38000
EDC_T5_REG
#define EDC_T5_REG(reg, idx)
Definition: t4_regs.h:510
V_MTUVALUE
#define V_MTUVALUE(x)
Definition: t4_regs.h:23115
G_MEM_WRAP_CLIENT_NUM
#define G_MEM_WRAP_CLIENT_NUM(x)
Definition: t4_regs.h:16333
F_HSSPDWNPLLB
#define F_HSSPDWNPLLB
Definition: t4_regs.h:46692
A_TP_OUT_CONFIG
#define A_TP_OUT_CONFIG
Definition: t4_regs.h:21499
VF_CIM_REG
#define VF_CIM_REG(reg_addr)
Definition: t4_regs.h:82
G_LKPTBLQUEUE1
#define G_LKPTBLQUEUE1(x)
Definition: t4_regs.h:23246
A_SGE_INT_ENABLE2
#define A_SGE_INT_ENABLE2
Definition: t4_regs.h:1110
F_ERR_FLM_IDMA0
#define F_ERR_FLM_IDMA0
Definition: t4_regs.h:1124
A_TP_MIB_TNL_IN_PKT_0
#define A_TP_MIB_TNL_IN_PKT_0
Definition: t4_regs.h:28701
A_SGE_INT_CAUSE1
#define A_SGE_INT_CAUSE1
Definition: t4_regs.h:808
F_TIEQOUTPARERRINT
#define F_TIEQOUTPARERRINT
Definition: t4_regs.h:20602
A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO
#define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO
Definition: t4_regs.h:33634
F_MACMATCH
#define F_MACMATCH
Definition: t4_regs.h:26799
A_MPS_PORT_STAT_TX_PORT_FRAMES_L
#define A_MPS_PORT_STAT_TX_PORT_FRAMES_L
Definition: t4_regs.h:32269
F_DBFIFO_LP_INT
#define F_DBFIFO_LP_INT
Definition: t4_regs.h:1212
G_MBOWNER
#define G_MBOWNER(x)
Definition: t4_regs.h:20368
F_VNIC_ID
#define F_VNIC_ID
Definition: t4_regs.h:26819
A_SGE_INT_ENABLE3
#define A_SGE_INT_ENABLE3
Definition: t4_regs.h:1250
A_LE_DB_INT_ENABLE
#define A_LE_DB_INT_ENABLE
Definition: t4_regs.h:38835
A_PCIE_CFG_SPACE_DATA
#define A_PCIE_CFG_SPACE_DATA
Definition: t4_regs.h:4916
F_BUBBLE
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Definition: t4_regs.h:32735
A_TP_MIB_TCP_V6OUT_RST
#define A_TP_MIB_TCP_V6OUT_RST
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F_MSTGRPPERR
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Definition: t4_regs.h:4297
V_TXTIMERSEPQ1
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A_PM_RX_STAT_COUNT
#define A_PM_RX_STAT_COUNT
Definition: t4_regs.h:29709
A_CIM_BOOT_CFG
#define A_CIM_BOOT_CFG
Definition: t4_regs.h:20389
V_SF_LOCK
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Definition: t4_regs.h:37808
A_SGE_CTXT_DATA0
#define A_SGE_CTXT_DATA0
Definition: t4_regs.h:2646
F_ILLRDBEINT
#define F_ILLRDBEINT
Definition: t4_regs.h:20858
LE_HASH_MASK_GEN_IPV4T5
#define LE_HASH_MASK_GEN_IPV4T5(idx)
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A_XGMAC_PORT_MAGIC_MACID_LO
#define A_XGMAC_PORT_MAGIC_MACID_LO
Definition: t4_regs.h:40808
F_MSIXADDRHPERR
#define F_MSIXADDRHPERR
Definition: t4_regs.h:4193
A_NCSI_INT_ENABLE
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Definition: t4_regs.h:39958
F_SGLRDBOOTINT
#define F_SGLRDBOOTINT
Definition: t4_regs.h:20850
G_TIMERVALUE1
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Definition: t4_regs.h:1711
V_UPDBGLARDPTR
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Definition: t4_regs.h:44292
A_MC_P_BIST_CMD_LEN
#define A_MC_P_BIST_CMD_LEN
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A_XGMAC_PORT_CFG2
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Definition: t4_regs.h:40730
F_TGTTAGQPERR
#define F_TGTTAGQPERR
Definition: t4_regs.h:4277
A_SGE_DEBUG_DATA_HIGH
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A_TP_PACE_TABLE
#define A_TP_PACE_TABLE
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A_TP_MIB_TNL_DROP_0
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F_PORT
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Definition: t4_regs.h:26823
F_T6_UNKNOWNCMD
#define F_T6_UNKNOWNCMD
Definition: t4_regs.h:39074
A_TP_MIB_CPL_IN_REQ_0
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Definition: t4_regs.h:28718
F_ULP_TX
#define F_ULP_TX
Definition: t4_regs.h:37920
F_C_PCMD_PAR_ERROR
#define F_C_PCMD_PAR_ERROR
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A_PM_TX_DBG_DATA
#define A_PM_TX_DBG_DATA
Definition: t4_regs.h:30491
A_TP_MIB_TCP_OUT_RST
#define A_TP_MIB_TCP_OUT_RST
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A_MAC_PORT_PERR_INT_EN_100G
#define A_MAC_PORT_PERR_INT_EN_100G
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A_PM_TX_STAT_CONFIG
#define A_PM_TX_STAT_CONFIG
Definition: t4_regs.h:30480
A_MC_P_BIST_STATUS_RDATA
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F_PIOTAGQPERR
#define F_PIOTAGQPERR
Definition: t4_regs.h:4241
F_READRSPERR
#define F_READRSPERR
Definition: t4_regs.h:4217
F_IBQPCIEPARERR
#define F_IBQPCIEPARERR
Definition: t4_regs.h:20596
F_REQOVRLOOKUPINT
#define F_REQOVRLOOKUPINT
Definition: t4_regs.h:20770
A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO
#define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO
Definition: t4_regs.h:33636
F_IPRXHDRGRPPERR
#define F_IPRXHDRGRPPERR
Definition: t4_regs.h:4237
F_T6_ACTCNTIPV6ZERO
#define F_T6_ACTCNTIPV6ZERO
Definition: t4_regs.h:39066
S_FRAGMENTATION
#define S_FRAGMENTATION
Definition: t4_regs.h:26789
A_SMB_INT_CAUSE
#define A_SMB_INT_CAUSE
Definition: t4_regs.h:36239
A_MC_ECC_STATUS
#define A_MC_ECC_STATUS
Definition: t4_regs.h:15926
F_TCIP
#define F_TCIP
Definition: t4_regs.h:6678
F_BLKRDBOOTINT
#define F_BLKRDBOOTINT
Definition: t4_regs.h:20842
F_CAUSE_CTX_0
#define F_CAUSE_CTX_0
Definition: t4_regs.h:36984
A_TP_MIB_OFD_CHN_DROP_0
#define A_TP_MIB_OFD_CHN_DROP_0
Definition: t4_regs.h:28693
A_CIM_HOST_UPACC_INT_ENABLE
#define A_CIM_HOST_UPACC_INT_ENABLE
Definition: t4_regs.h:20624
A_CPL_INTR_CAUSE
#define A_CPL_INTR_CAUSE
Definition: t4_regs.h:35990
M_DATAPORTNUM
#define M_DATAPORTNUM
Definition: t4_regs.h:34631
G_TIMERVALUE3
#define G_TIMERVALUE3(x)
Definition: t4_regs.h:1723
A_SMB_INT_ENABLE
#define A_SMB_INT_ENABLE
Definition: t4_regs.h:36149
F_PBL_BOUND_ERR_CH2
#define F_PBL_BOUND_ERR_CH2
Definition: t4_regs.h:28867
F_ERR_FLM_IDMA1
#define F_ERR_FLM_IDMA1
Definition: t4_regs.h:1120
A_PL_VF_WHOAMI
#define A_PL_VF_WHOAMI
Definition: t4_regs.h:37823
F_PLCIM_MSTRSPDATAPARERR
#define F_PLCIM_MSTRSPDATAPARERR
Definition: t4_regs.h:20564
A_TP_PARA_REG2
#define A_TP_PARA_REG2
Definition: t4_regs.h:22338
G_TSCALE
#define G_TSCALE(x)
Definition: t4_regs.h:1699
F_PM_TX
#define F_PM_TX
Definition: t4_regs.h:37944
V_TXDATAFIFO
#define V_TXDATAFIFO(x)
Definition: t4_regs.h:32744
A_MAC_PORT_PERR_INT_CAUSE
#define A_MAC_PORT_PERR_INT_CAUSE
Definition: t4_regs.h:46617
M_FILTMEM
#define M_FILTMEM
Definition: t4_regs.h:33940
A_EDC_INT_CAUSE
#define A_EDC_INT_CAUSE
Definition: t4_regs.h:20311
A_TP_DBG_LA_CONFIG
#define A_TP_DBG_LA_CONFIG
Definition: t4_regs.h:24282
F_CIM_FRAMING_ERROR
#define F_CIM_FRAMING_ERROR
Definition: t4_regs.h:35976
A_TP_MIB_MAC_IN_ERR_0
#define A_TP_MIB_MAC_IN_ERR_0
Definition: t4_regs.h:28670
A_MAC_PORT_PERR_INT_CAUSE_100G
#define A_MAC_PORT_PERR_INT_CAUSE_100G
Definition: t4_regs.h:46350
F_SGLWRFLASHINT
#define F_SGLWRFLASHINT
Definition: t4_regs.h:20830
F_ERR_BAD_DB_PIDX0
#define F_ERR_BAD_DB_PIDX0
Definition: t4_regs.h:1192
F_UPCRST
#define F_UPCRST
Definition: t4_regs.h:20407
F_GLOBALENABLE
#define F_GLOBALENABLE
Definition: t4_regs.h:640
F_PCIE2CIMINTFPARERR
#define F_PCIE2CIMINTFPARERR
Definition: t4_regs.h:20592
A_MPS_TRC_FILTER0_MATCH
#define A_MPS_TRC_FILTER0_MATCH
Definition: t4_regs.h:33953
V_MBOWNER
#define V_MBOWNER(x)
Definition: t4_regs.h:20367
F_MSIDATAPERR
#define F_MSIDATAPERR
Definition: t4_regs.h:4201
F_INTXCLRPERR
#define F_INTXCLRPERR
Definition: t4_regs.h:4125
V_POLADBGRDPTR
#define V_POLADBGRDPTR(x)
Definition: t4_regs.h:21002
A_MPS_PORT_STAT_RX_PORT_PAUSE_L
#define A_MPS_PORT_STAT_RX_PORT_PAUSE_L
Definition: t4_regs.h:32376
A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE
#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE
Definition: t4_regs.h:6762
F_MSTTAGQPERR
#define F_MSTTAGQPERR
Definition: t4_regs.h:4273
F_PCIESINT
#define F_PCIESINT
Definition: t4_regs.h:4101
A_DBG_GPIO_EN
#define A_DBG_GPIO_EN
Definition: t4_regs.h:11543
A_NCSI_INT_CAUSE
#define A_NCSI_INT_CAUSE
Definition: t4_regs.h:39996
F_LADBGEN
#define F_LADBGEN
Definition: t4_regs.h:21016
A_MPS_RX_PERR_INT_ENABLE
#define A_MPS_RX_PERR_INT_ENABLE
Definition: t4_regs.h:34995
A_MPS_STAT_PERR_INT_ENABLE_SRAM
#define A_MPS_STAT_PERR_INT_ENABLE_SRAM
Definition: t4_regs.h:33539
A_PL_VF_REVISION
#define A_PL_VF_REVISION
Definition: t4_regs.h:37870
F_ERR_CPL_EXCEED_IQE_SIZE
#define F_ERR_CPL_EXCEED_IQE_SIZE
Definition: t4_regs.h:1152
F_OBQDBGBUSY
#define F_OBQDBGBUSY
Definition: t4_regs.h:20990
A_MA_PARITY_ERROR_STATUS1
#define A_MA_PARITY_ERROR_STATUS1
Definition: t4_regs.h:16610
F_RSPOVRLOOKUPINT
#define F_RSPOVRLOOKUPINT
Definition: t4_regs.h:20766
F_RPLPERR
#define F_RPLPERR
Definition: t4_regs.h:4105
A_SGE_INGRESS_RX_THRESHOLD
#define A_SGE_INGRESS_RX_THRESHOLD
Definition: t4_regs.h:1479
A_CIM_VF_EXT_MAILBOX_STATUS
#define A_CIM_VF_EXT_MAILBOX_STATUS
Definition: t4_regs.h:20343
F_T6_ACTCNTIPV6TZERO
#define F_T6_ACTCNTIPV6TZERO
Definition: t4_regs.h:39058
A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H
#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H
Definition: t4_regs.h:31583
A_EDC_ECC_STATUS
#define A_EDC_ECC_STATUS
Definition: t4_regs.h:20325
F_SGLWREEPROMINT
#define F_SGLWREEPROMINT
Definition: t4_regs.h:20814
G_DBGLAWPTR
#define G_DBGLAWPTR(x)
Definition: t4_regs.h:24296
F_HREQPERR
#define F_HREQPERR
Definition: t4_regs.h:4141
F_MAGICEN
#define F_MAGICEN
Definition: t4_regs.h:40765
F_RCAP
#define F_RCAP
Definition: t4_regs.h:6682
F_EDC0
#define F_EDC0
Definition: t4_regs.h:37964
V_IBQDBGADDR
#define V_IBQDBGADDR(x)
Definition: t4_regs.h:20962
A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO
#define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO
Definition: t4_regs.h:33663
A_EDC_BIST_CMD_ADDR
#define A_EDC_BIST_CMD_ADDR
Definition: t4_regs.h:20291
F_SGE2CIMINTFPARERR
#define F_SGE2CIMINTFPARERR
Definition: t4_regs.h:20572
F_ILLTRANSINT
#define F_ILLTRANSINT
Definition: t4_regs.h:20870
A_MPS_CMN_CTL
#define A_MPS_CMN_CTL
Definition: t4_regs.h:32398
A_PCIE_INT_CAUSE
#define A_PCIE_INT_CAUSE
Definition: t4_regs.h:4299
G_MAXRXDATA
#define G_MAXRXDATA(x)
Definition: t4_regs.h:22343
A_PL_INT_MAP0
#define A_PL_INT_MAP0
Definition: t4_regs.h:38070
F_RCIP
#define F_RCIP
Definition: t4_regs.h:6162
F_LKPTBLROWVLD
#define F_LKPTBLROWVLD
Definition: t4_regs.h:23236
F_IBQSGEHIPARERR
#define F_IBQSGEHIPARERR
Definition: t4_regs.h:20516
F_IPSOTPERR
#define F_IPSOTPERR
Definition: t4_regs.h:4225
G_OFDRATE3
#define G_OFDRATE3(x)
Definition: t4_regs.h:24239
V_TXDESCFIFO
#define V_TXDESCFIFO(x)
Definition: t4_regs.h:32739
A_MA_PARITY_ERROR_ENABLE1
#define A_MA_PARITY_ERROR_ENABLE1
Definition: t4_regs.h:16479
A_ULP_RX_LA_RDDATA
#define A_ULP_RX_LA_RDDATA
Definition: t4_regs.h:37425
A_MC_BIST_DATA_PATTERN
#define A_MC_BIST_DATA_PATTERN
Definition: t4_regs.h:16010
M_TPFIFO
#define M_TPFIFO
Definition: t4_regs.h:32752
A_TP_TIMER_RESOLUTION
#define A_TP_TIMER_RESOLUTION
Definition: t4_regs.h:22914
F_CMDPRSRINTERR
#define F_CMDPRSRINTERR
Definition: t4_regs.h:38956
F_REQQPARERR
#define F_REQQPARERR
Definition: t4_regs.h:38844
F_PM_RX
#define F_PM_RX
Definition: t4_regs.h:37940
G_LKPTBLQUEUE0
#define G_LKPTBLQUEUE0(x)
Definition: t4_regs.h:23251
A_TP_MIB_FCOE_DROP_0
#define A_TP_MIB_FCOE_DROP_0
Definition: t4_regs.h:28738
F_TOTCNTERR
#define F_TOTCNTERR
Definition: t4_regs.h:38952
F_BLKRDPLINT
#define F_BLKRDPLINT
Definition: t4_regs.h:20778
A_SGE_TIMER_VALUE_4_AND_5
#define A_SGE_TIMER_VALUE_4_AND_5
Definition: t4_regs.h:1725
F_RPCP
#define F_RPCP
Definition: t4_regs.h:6158
F_HOSTWRITE
#define F_HOSTWRITE
Definition: t4_regs.h:20938
A_SGE_DEBUG_DATA_LOW_INDEX_3
#define A_SGE_DEBUG_DATA_LOW_INDEX_3
Definition: t4_regs.h:3651
F_CCNTPERR
#define F_CCNTPERR
Definition: t4_regs.h:4169
A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS
#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS
Definition: t4_regs.h:6658
F_VNIC
#define F_VNIC
Definition: t4_regs.h:26866
F_ERR_PCIE_ERROR2
#define F_ERR_PCIE_ERROR2
Definition: t4_regs.h:1136
G_KEYMODE
#define G_KEYMODE(x)
Definition: t4_regs.h:23468
F_CTCAMINVLDENT
#define F_CTCAMINVLDENT
Definition: t4_regs.h:38944
F_FCOE
#define F_FCOE
Definition: t4_regs.h:26827
A_TP_MIB_TID_DEL
#define A_TP_MIB_TID_DEL
Definition: t4_regs.h:28758
F_IBQDBGEN
#define F_IBQDBGEN
Definition: t4_regs.h:20975
F_ICSPI_PAR_ERROR
#define F_ICSPI_PAR_ERROR
Definition: t4_regs.h:30612
F_MSTTXFIFOPARINT
#define F_MSTTXFIFOPARINT
Definition: t4_regs.h:36243
F_MAGRPPERR
#define F_MAGRPPERR
Definition: t4_regs.h:4245
F_HSSPDWNPLLA
#define F_HSSPDWNPLLA
Definition: t4_regs.h:46688
F_ZERO_C_CMD_ERROR
#define F_ZERO_C_CMD_ERROR
Definition: t4_regs.h:30622
A_SGE_ERROR_STATS
#define A_SGE_ERROR_STATS
Definition: t4_regs.h:2062
F_TIMEOUTINT
#define F_TIMEOUTINT
Definition: t4_regs.h:20762
A_SGE_DEBUG_DATA_LOW_INDEX_2
#define A_SGE_DEBUG_DATA_LOW_INDEX_2
Definition: t4_regs.h:3614
F_FATAL_WRE_LEN
#define F_FATAL_WRE_LEN
Definition: t4_regs.h:1248
F_FIDPERR
#define F_FIDPERR
Definition: t4_regs.h:4129
F_MSIXADDRLPERR
#define F_MSIXADDRLPERR
Definition: t4_regs.h:4197
G_ERROR_QID
#define G_ERROR_QID(x)
Definition: t4_regs.h:2075
F_OCSPI_PAR_ERROR
#define F_OCSPI_PAR_ERROR
Definition: t4_regs.h:29810
A_SGE_FL_BUFFER_SIZE0
#define A_SGE_FL_BUFFER_SIZE0
Definition: t4_regs.h:1251
F_COUNTPAUSEMCTX
#define F_COUNTPAUSEMCTX
Definition: t4_regs.h:33526
F_RDPE
#define F_RDPE
Definition: t4_regs.h:6702
V_FUNCTION
#define V_FUNCTION(x)
Definition: t4_regs.h:4854
A_MPS_CLS_INT_CAUSE
#define A_MPS_CLS_INT_CAUSE
Definition: t4_regs.h:34257
F_MSIXDIPERR
#define F_MSIXDIPERR
Definition: t4_regs.h:4185
A_TP_MIB_TCP_V6IN_ERR_0
#define A_TP_MIB_TCP_V6IN_ERR_0
Definition: t4_regs.h:28705
F_PCMD_LEN_OVFL2
#define F_PCMD_LEN_OVFL2
Definition: t4_regs.h:30504
A_MPS_TRC_FILTER0_DONT_CARE
#define A_MPS_TRC_FILTER0_DONT_CARE
Definition: t4_regs.h:33954
F_MBHOSTPARERR
#define F_MBHOSTPARERR
Definition: t4_regs.h:20492
V_TFINVERTMATCH
#define V_TFINVERTMATCH(x)
Definition: t4_regs.h:33831
F_MATAGPERR
#define F_MATAGPERR
Definition: t4_regs.h:4121
A_TP_MIB_RQE_DFR_PKT
#define A_TP_MIB_RQE_DFR_PKT
Definition: t4_regs.h:28762
A_XGMAC_PORT_CFG
#define A_XGMAC_PORT_CFG
Definition: t4_regs.h:40558
M_TFMINPKTSIZE
#define M_TFMINPKTSIZE
Definition: t4_regs.h:33893
F_MPS
#define F_MPS
Definition: t4_regs.h:38012
F_DREQRDPERR
#define F_DREQRDPERR
Definition: t4_regs.h:4261
F_UNXSPLCPLERR
#define F_UNXSPLCPLERR
Definition: t4_regs.h:4093
F_ERR_CPL_OPCODE_0
#define F_ERR_CPL_OPCODE_0
Definition: t4_regs.h:1164
VF_PL_REG
#define VF_PL_REG(reg_addr)
Definition: t4_regs.h:76
F_CIM_OP_MAP_PERR
#define F_CIM_OP_MAP_PERR
Definition: t4_regs.h:35960
A_MC_P_BIST_CMD
#define A_MC_P_BIST_CMD
Definition: t4_regs.h:58475
A_MAC_PORT_PERR_INT_EN
#define A_MAC_PORT_PERR_INT_EN
Definition: t4_regs.h:46387
A_MC_BIST_CMD_LEN
#define A_MC_BIST_CMD_LEN
Definition: t4_regs.h:16009
A_TP_RSS_LKP_TABLE
#define A_TP_RSS_LKP_TABLE
Definition: t4_regs.h:23232
G_DBGLAMODE
#define G_DBGLAMODE(x)
Definition: t4_regs.h:24301
A_ULP_RX_INT_CAUSE_2
#define A_ULP_RX_INT_CAUSE_2
Definition: t4_regs.h:37665
MYPF_REG
#define MYPF_REG(reg_addr)
Definition: t4_regs.h:39
A_MPS_STAT_PERR_INT_ENABLE_SRAM1
#define A_MPS_STAT_PERR_INT_ENABLE_SRAM1
Definition: t4_regs.h:33721
A_TP_MIB_INDEX
#define A_TP_MIB_INDEX
Definition: t4_regs.h:23744
A_EDC_BIST_CMD
#define A_EDC_BIST_CMD
Definition: t4_regs.h:20290
A_CIM_VF_EXT_MAILBOX_CTRL
#define A_CIM_VF_EXT_MAILBOX_CTRL
Definition: t4_regs.h:20336
A_ULP_RX_INT_ENABLE_2
#define A_ULP_RX_INT_ENABLE_2
Definition: t4_regs.h:37627
V_T5_TFPORT
#define V_T5_TFPORT(x)
Definition: t4_regs.h:33887
G_DELAYEDACKRESOLUTION
#define G_DELAYEDACKRESOLUTION(x)
Definition: t4_regs.h:22929
F_SE_CNT_MISMATCH_0
#define F_SE_CNT_MISMATCH_0
Definition: t4_regs.h:36974
A_PL_PERR_CAUSE
#define A_PL_PERR_CAUSE
Definition: t4_regs.h:37912
A_MAC_PORT_HSS_CFG0
#define A_MAC_PORT_HSS_CFG0
Definition: t4_regs.h:46652
V_CTXTQID
#define V_CTXTQID(x)
Definition: t4_regs.h:2643
G_EGRTHRESHOLD
#define G_EGRTHRESHOLD(x)
Definition: t4_regs.h:1436
F_NONFATALERR
#define F_NONFATALERR
Definition: t4_regs.h:4089
F_IPRETRYPERR
#define F_IPRETRYPERR
Definition: t4_regs.h:4229
A_TP_MIB_OFD_VLN_DROP_0
#define A_TP_MIB_OFD_VLN_DROP_0
Definition: t4_regs.h:28750
F_MSIADDRHPERR
#define F_MSIADDRHPERR
Definition: t4_regs.h:4205
A_SGE_INT_CAUSE6
#define A_SGE_INT_CAUSE6
Definition: t4_regs.h:2414
G_TFPORT
#define G_TFPORT(x)
Definition: t4_regs.h:33845
F_MEM_WRAP_INT_CAUSE
#define F_MEM_WRAP_INT_CAUSE
Definition: t4_regs.h:16317
F_DBFIFO_HP_INT
#define F_DBFIFO_HP_INT
Definition: t4_regs.h:1208
F_HOSTBUSY
#define F_HOSTBUSY
Definition: t4_regs.h:20934
A_EDC_H_BIST_CMD_LEN
#define A_EDC_H_BIST_CMD_LEN
Definition: t4_regs.h:61858
A_SGE_TIMER_VALUE_0_AND_1
#define A_SGE_TIMER_VALUE_0_AND_1
Definition: t4_regs.h:1701
F_ERR_TIMER_ABOVE_MAX_QID
#define F_ERR_TIMER_ABOVE_MAX_QID
Definition: t4_regs.h:1148
F_MAC1
#define F_MAC1
Definition: t4_regs.h:38063
A_TP_TX_MOD_Q1_Q0_RATE_LIMIT
#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT
Definition: t4_regs.h:24479
F_SGLWRPLINT
#define F_SGLWRPLINT
Definition: t4_regs.h:20782
A_TP_MIB_CPL_OUT_RSP_0
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F_I2CM
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F_START_BIST
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V_TFCAPTUREMAX
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F_TCAMACCFAIL
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A_ULP_RX_INT_CAUSE
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V_TFPORT
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F_DBGLAWHLF
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A_TP_MIB_TNL_LPBK_0
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A_PL_PERR_ENABLE
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V_BYTECNT
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F_PATEN
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A_ULP_RX_LA_RDPTR
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A_TP_RSS_PF_MSK
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F_PCMD_LEN_OVFL1
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F_TFINVERTMATCH
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A_UP_UP_DBG_LA_CFG
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G_INGPADBOUNDARY
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MC_REG
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G_THRESHOLD_3
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F_IBQNCSIPARERR
#define F_IBQNCSIPARERR
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A_PM_RX_STAT_LSB
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A_CIM_PF_HOST_INT_CAUSE
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F_MSIADDRLPERR
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F_CIM
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Definition: t4_regs.h:38028
F_PIOREQPERR
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Definition: t4_regs.h:4177
F_TP
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F_IBQTP0PARERR
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A_MAC_PORT_INT_EN
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A_TP_MIB_TNL_CNG_DROP_0
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F_ERROR_QID_VALID
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Definition: t4_regs.h:2070
F_LE
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F_HCNTPERR
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A_SGE_HOST_PAGE_SIZE
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A_PM_RX_STAT_CONFIG
#define A_PM_RX_STAT_CONFIG
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A_TP_RSS_VFL_CONFIG
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F_TIMER0INT
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F_SGE_FRAMING_ERROR
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F_SLVFIFOPARINT
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F_PIOCPLGRPPERR
#define F_PIOCPLGRPPERR
Definition: t4_regs.h:4285
A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO
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A_LE_DB_INT_CAUSE
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A_TP_INT_CAUSE
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A_CIM_IBQ_DBG_CFG
#define A_CIM_IBQ_DBG_CFG
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F_TFEN
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Definition: t4_regs.h:33840
F_BUSY
#define F_BUSY
Definition: t4_regs.h:2629
F_ULP2CIMINTFPARERR
#define F_ULP2CIMINTFPARERR
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F_IBQSELECT
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Definition: t4_regs.h:20898
A_MPS_TRC_FILTER1_MATCH
#define A_MPS_TRC_FILTER1_MATCH
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F_NCSI
#define F_NCSI
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G_ECC_UECNT
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A_MC_INT_ENABLE
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Definition: t4_regs.h:15898
A_TP_MIB_OFD_ARP_DROP
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Definition: t4_regs.h:28716
F_DBPRIO
#define F_DBPRIO
Definition: t4_regs.h:524
M_QUEUESPERPAGEPF0
#define M_QUEUESPERPAGEPF0
Definition: t4_regs.h:722
A_CIM_PF_MAILBOX_DATA
#define A_CIM_PF_MAILBOX_DATA
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A_TP_PIO_ADDR
#define A_TP_PIO_ADDR
Definition: t4_regs.h:23732
F_MAC2
#define F_MAC2
Definition: t4_regs.h:38059
A_TP_TX_ORATE
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Definition: t4_regs.h:24234
G_ECC_CECNT
#define G_ECC_CECNT(x)
Definition: t4_regs.h:15931
F_PCMD_LEN_OVFL0
#define F_PCMD_LEN_OVFL0
Definition: t4_regs.h:30496
F_ENABLE
#define F_ENABLE
Definition: t4_regs.h:4832
F_TARTAGPERR
#define F_TARTAGPERR
Definition: t4_regs.h:4173
F_CMDTIDERR
#define F_CMDTIDERR
Definition: t4_regs.h:38960
F_ERR_ING_CTXT_PRIO
#define F_ERR_ING_CTXT_PRIO
Definition: t4_regs.h:1200
A_XGMAC_PORT_INT_CAUSE
#define A_XGMAC_PORT_INT_CAUSE
Definition: t4_regs.h:41086
F_DBGLAENABLE
#define F_DBGLAENABLE
Definition: t4_regs.h:24309
A_TP_DBG_LA_DATAL
#define A_TP_DBG_LA_DATAL
Definition: t4_regs.h:24316
F_OESPI_PAR_ERROR
#define F_OESPI_PAR_ERROR
Definition: t4_regs.h:30608
F_PREFDROPINT
#define F_PREFDROPINT
Definition: t4_regs.h:20618
F_PMU
#define F_PMU
Definition: t4_regs.h:37976
A_PL_PL_INT_ENABLE
#define A_PL_PL_INT_ENABLE
Definition: t4_regs.h:38208
F_IPRXDATAGRPPERR
#define F_IPRXDATAGRPPERR
Definition: t4_regs.h:4233
F_BLKRDEEPROMINT
#define F_BLKRDEEPROMINT
Definition: t4_regs.h:20810
F_SGLWRBOOTINT
#define F_SGLWRBOOTINT
Definition: t4_regs.h:20846
A_MAC_PORT_MAGIC_MACID_HI
#define A_MAC_PORT_MAGIC_MACID_HI
Definition: t4_regs.h:45483
F_PBL_BOUND_ERR_CH3
#define F_PBL_BOUND_ERR_CH3
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A_PM_TX_DBG_CTRL
#define A_PM_TX_DBG_CTRL
Definition: t4_regs.h:30483
A_EDC_BIST_STATUS_RDATA
#define A_EDC_BIST_STATUS_RDATA
Definition: t4_regs.h:20299
A_XGMAC_PORT_INT_EN
#define A_XGMAC_PORT_INT_EN
Definition: t4_regs.h:40976
F_EGRSTATUSPAGESIZE
#define F_EGRSTATUSPAGESIZE
Definition: t4_regs.h:604
G_TNLRATE1
#define G_TNLRATE1(x)
Definition: t4_regs.h:24275
F_VFWREN
#define F_VFWREN
Definition: t4_regs.h:23472
G_QUEFULLTHRSH
#define G_QUEFULLTHRSH(x)
Definition: t4_regs.h:20924
A_CIM_PO_LA_MADEBUGDATA
#define A_CIM_PO_LA_MADEBUGDATA
Definition: t4_regs.h:21054
A_CIM_PI_LA_MADEBUGDATA
#define A_CIM_PI_LA_MADEBUGDATA
Definition: t4_regs.h:21055
T5_PORT_BASE
#define T5_PORT_BASE(idx)
Definition: t4_regs.h:287
PF_REG
#define PF_REG(idx, reg)
Definition: t4_regs.h:67
F_TCAMINVLDENT
#define F_TCAMINVLDENT
Definition: t4_regs.h:38948
V_KEYWRADDRX
#define V_KEYWRADDRX(x)
Definition: t4_regs.h:23493
F_BLKWRFLASHINT
#define F_BLKWRFLASHINT
Definition: t4_regs.h:20822
A_SGE_INT_CAUSE2
#define A_SGE_INT_CAUSE2
Definition: t4_regs.h:948
A_EDC_H_BIST_DATA_PATTERN
#define A_EDC_H_BIST_DATA_PATTERN
Definition: t4_regs.h:61859
F_PERR_CPL_128TO128_0
#define F_PERR_CPL_128TO128_0
Definition: t4_regs.h:35988
F_T5_TFEN
#define F_T5_TFEN
Definition: t4_regs.h:33883
A_MPS_CLS_INT_ENABLE
#define A_MPS_CLS_INT_ENABLE
Definition: t4_regs.h:34251
F_RFTP
#define F_RFTP
Definition: t4_regs.h:6170
A_TP_PMM_TX_PAGE_SIZE
#define A_TP_PMM_TX_PAGE_SIZE
Definition: t4_regs.h:21772
A_MPS_TRC_INT_CAUSE
#define A_MPS_TRC_INT_CAUSE
Definition: t4_regs.h:33950
F_MBMSGVALID
#define F_MBMSGVALID
Definition: t4_regs.h:20359
F_UPDBGLARDEN
#define F_UPDBGLARDEN
Definition: t4_regs.h:44297
F_KEYWREN
#define F_KEYWREN
Definition: t4_regs.h:23476
A_TP_TM_PIO_DATA
#define A_TP_TM_PIO_DATA
Definition: t4_regs.h:23625
F_DREQPERR
#define F_DREQPERR
Definition: t4_regs.h:4153
A_XGMAC_PORT_MAGIC_MACID_HI
#define A_XGMAC_PORT_MAGIC_MACID_HI
Definition: t4_regs.h:40809
A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS
#define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS
Definition: t4_regs.h:6150
F_SGLRDPLINT
#define F_SGLRDPLINT
Definition: t4_regs.h:20786
G_TIMERVALUE2
#define G_TIMERVALUE2(x)
Definition: t4_regs.h:1718
G_EGRTHRESHOLDPACKING
#define G_EGRTHRESHOLDPACKING(x)
Definition: t4_regs.h:1454
F_PIOTAGPERR
#define F_PIOTAGPERR
Definition: t4_regs.h:4117
F_OBQULP2PARERR
#define F_OBQULP2PARERR
Definition: t4_regs.h:20532
F_TPCP
#define F_TPCP
Definition: t4_regs.h:6662
A_PM_TX_STAT_COUNT
#define A_PM_TX_STAT_COUNT
Definition: t4_regs.h:30481
A_TP_PIO_DATA
#define A_TP_PIO_DATA
Definition: t4_regs.h:23733
F_E_PCMD_PAR_ERROR
#define F_E_PCMD_PAR_ERROR
Definition: t4_regs.h:29822
F_PIOREQGRPPERR
#define F_PIOREQGRPPERR
Definition: t4_regs.h:4281
V_KEYWRADDR
#define V_KEYWRADDR(x)
Definition: t4_regs.h:23480
A_CIM_HOST_ACC_CTRL
#define A_CIM_HOST_ACC_CTRL
Definition: t4_regs.h:20930
F_UNKNOWNCMD
#define F_UNKNOWNCMD
Definition: t4_regs.h:38848
F_EEPROMWRINT
#define F_EEPROMWRINT
Definition: t4_regs.h:20754
G_TNLRATE0
#define G_TNLRATE0(x)
Definition: t4_regs.h:24280
A_ULP_RX_INT_ENABLE
#define A_ULP_RX_INT_ENABLE
Definition: t4_regs.h:36866
A_PL_INT_ENABLE
#define A_PL_INT_ENABLE
Definition: t4_regs.h:38069
F_TDUE
#define F_TDUE
Definition: t4_regs.h:6710
F_ERR_EGR_CTXT_PRIO
#define F_ERR_EGR_CTXT_PRIO
Definition: t4_regs.h:1204
A_MPS_TRC_FILTER_MATCH_CTL_A
#define A_MPS_TRC_FILTER_MATCH_CTL_A
Definition: t4_regs.h:33828
V_VFWRADDR
#define V_VFWRADDR(x)
Definition: t4_regs.h:23462
V_MTUINDEX
#define V_MTUINDEX(x)
Definition: t4_regs.h:23105
V_DATAPORTNUM
#define V_DATAPORTNUM(x)
Definition: t4_regs.h:34632
F_FRAGMENTATION
#define F_FRAGMENTATION
Definition: t4_regs.h:26791
F_COUNTPAUSEMCRX
#define F_COUNTPAUSEMCRX
Definition: t4_regs.h:33518
A_MPS_RX_PERR_INT_CAUSE
#define A_MPS_RX_PERR_INT_CAUSE
Definition: t4_regs.h:34893
M_HOSTPAGESIZEPF0
#define M_HOSTPAGESIZEPF0
Definition: t4_regs.h:680
F_OBQSELECT
#define F_OBQSELECT
Definition: t4_regs.h:20894
V_ADDRESS
#define V_ADDRESS(x)
Definition: t4_regs.h:40950
F_TIEQINPARERRINT
#define F_TIEQINPARERRINT
Definition: t4_regs.h:20606
F_ILLWRBEINT
#define F_ILLWRBEINT
Definition: t4_regs.h:20854
S_HOSTPAGESIZEPF1
#define S_HOSTPAGESIZEPF1
Definition: t4_regs.h:674
M_TXDATAFIFO
#define M_TXDATAFIFO
Definition: t4_regs.h:32743
F_CRXPKTENC
#define F_CRXPKTENC
Definition: t4_regs.h:21612
F_LIPMISS
#define F_LIPMISS
Definition: t4_regs.h:38884
F_CREQRDPERR
#define F_CREQRDPERR
Definition: t4_regs.h:4269
F_TIMER1INT
#define F_TIMER1INT
Definition: t4_regs.h:20610
G_CIMQSIZE
#define G_CIMQSIZE(x)
Definition: t4_regs.h:20910
A_MA_PARITY_ERROR_STATUS2
#define A_MA_PARITY_ERROR_STATUS2
Definition: t4_regs.h:16658
F_VFRDRG
#define F_VFRDRG
Definition: t4_regs.h:23433
F_PBL_BOUND_ERR_CH0
#define F_PBL_BOUND_ERR_CH0
Definition: t4_regs.h:28875
F_ERR_PCIE_ERROR0
#define F_ERR_PCIE_ERROR0
Definition: t4_regs.h:1144
A_MPS_PORT_STAT_TX_PORT_BYTES_L
#define A_MPS_PORT_STAT_TX_PORT_BYTES_L
Definition: t4_regs.h:32267
G_TIMERVALUE0
#define G_TIMERVALUE0(x)
Definition: t4_regs.h:1706
A_MA_INT_ENABLE
#define A_MA_INT_ENABLE
Definition: t4_regs.h:16295
V_BIST_OPCODE
#define V_BIST_OPCODE(x)
Definition: t4_regs.h:16005
F_ERR_ITP_TIME_PAUSED
#define F_ERR_ITP_TIME_PAUSED
Definition: t4_regs.h:1160
F_HREQWRPERR
#define F_HREQWRPERR
Definition: t4_regs.h:4257
A_TP_MTU_TABLE
#define A_TP_MTU_TABLE
Definition: t4_regs.h:23101
F_PIOCPLPERR
#define F_PIOCPLPERR
Definition: t4_regs.h:4181
A_CIM_HOST_ACC_DATA
#define A_CIM_HOST_ACC_DATA
Definition: t4_regs.h:20945
F_MC0
#define F_MC0
Definition: t4_regs.h:38036
V_OBQDBGADDR
#define V_OBQDBGADDR(x)
Definition: t4_regs.h:20981
A_MA_PARITY_ERROR_ENABLE2
#define A_MA_PARITY_ERROR_ENABLE2
Definition: t4_regs.h:16648
F_OBQULP3PARERR
#define F_OBQULP3PARERR
Definition: t4_regs.h:20536
F_CIM_DM_PRTY_ERR
#define F_CIM_DM_PRTY_ERR
Definition: t4_regs.h:39962
F_MAC3
#define F_MAC3
Definition: t4_regs.h:38055
A_EDC_H_BIST_CMD
#define A_EDC_H_BIST_CMD
Definition: t4_regs.h:61856
A_TP_RSS_VFH_CONFIG
#define A_TP_RSS_VFH_CONFIG
Definition: t4_regs.h:25102
A_SGE_VF_KDOORBELL
#define A_SGE_VF_KDOORBELL
Definition: t4_regs.h:531
G_TFCAPTUREMAX
#define G_TFCAPTUREMAX(x)
Definition: t4_regs.h:33900
F_T6_ACTCNTIPV4TZERO
#define F_T6_ACTCNTIPV4TZERO
Definition: t4_regs.h:39062
V_CONT
#define V_CONT(x)
Definition: t4_regs.h:37812
F_HASHSRAM
#define F_HASHSRAM
Definition: t4_regs.h:34241
A_CIM_DEBUGSTS
#define A_CIM_DEBUGSTS
Definition: t4_regs.h:21036
A_PM_RX_DBG_STAT_MSB
#define A_PM_RX_DBG_STAT_MSB
Definition: t4_regs.h:29868
F_CPL_SWITCH
#define F_CPL_SWITCH
Definition: t4_regs.h:37932
V_SIGNAL_DET
#define V_SIGNAL_DET(x)
Definition: t4_regs.h:40610
F_PBL_BOUND_ERR_CH1
#define F_PBL_BOUND_ERR_CH1
Definition: t4_regs.h:28871
F_OBQDBGEN
#define F_OBQDBGEN
Definition: t4_regs.h:20994
A_MC_BIST_CMD_ADDR
#define A_MC_BIST_CMD_ADDR
Definition: t4_regs.h:16008
F_DBTYPE
#define F_DBTYPE
Definition: t4_regs.h:535
A_CIM_PI_LA_DEBUGDATA
#define A_CIM_PI_LA_DEBUGDATA
Definition: t4_regs.h:21053
A_TP_TM_PIO_ADDR
#define A_TP_TM_PIO_ADDR
Definition: t4_regs.h:23624
F_CIM_OVFL_ERROR
#define F_CIM_OVFL_ERROR
Definition: t4_regs.h:35964
F_IESPI_PAR_ERROR
#define F_IESPI_PAR_ERROR
Definition: t4_regs.h:29818
G_THRESHOLD_0
#define G_THRESHOLD_0(x)
Definition: t4_regs.h:1484
F_PCIEPINT
#define F_PCIEPINT
Definition: t4_regs.h:4097
G_TFMINPKTSIZE
#define G_TFMINPKTSIZE(x)
Definition: t4_regs.h:33895
F_MC
#define F_MC
Definition: t4_regs.h:37968
F_IBQSGELOPARERR
#define F_IBQSGELOPARERR
Definition: t4_regs.h:20512
F_OBQSGEPARERR
#define F_OBQSGEPARERR
Definition: t4_regs.h:20540
A_MPS_VF_CTL
#define A_MPS_VF_CTL
Definition: t4_regs.h:31381
F_DBP_TBUF_FULL
#define F_DBP_TBUF_FULL
Definition: t4_regs.h:1244
F_NCSIFIFO
#define F_NCSIFIFO
Definition: t4_regs.h:32749
A_MPS_STAT_PERR_INT_CAUSE_SRAM1
#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1
Definition: t4_regs.h:33733
M_UPDBGLARDPTR
#define M_UPDBGLARDPTR
Definition: t4_regs.h:44291
F_T6_ACTCNTIPV4ZERO
#define F_T6_ACTCNTIPV4ZERO
Definition: t4_regs.h:39070
A_TP_PMM_RX_PAGE_SIZE
#define A_TP_PMM_RX_PAGE_SIZE
Definition: t4_regs.h:21760
M_T6_VFWRADDR
#define M_T6_VFWRADDR
Definition: t4_regs.h:23501
A_PM_TX_DBG_STAT_MSB
#define A_PM_TX_DBG_STAT_MSB
Definition: t4_regs.h:30654
A_CIM_OBQ_DBG_DATA
#define A_CIM_OBQ_DBG_DATA
Definition: t4_regs.h:20997
A_SF_DATA
#define A_SF_DATA
Definition: t4_regs.h:37804
PORT_BASE
#define PORT_BASE(idx)
Definition: t4_regs.h:100
F_MA
#define F_MA
Definition: t4_regs.h:37948
F_ACTRGNFULL
#define F_ACTRGNFULL
Definition: t4_regs.h:38876
G_TIMERVALUE5
#define G_TIMERVALUE5(x)
Definition: t4_regs.h:1735
A_MPS_PORT_CTL
#define A_MPS_PORT_CTL
Definition: t4_regs.h:31350
F_HSSPLLBYPA
#define F_HSSPLLBYPA
Definition: t4_regs.h:46680
A_TP_MIB_DATA
#define A_TP_MIB_DATA
Definition: t4_regs.h:23745
F_PL
#define F_PL
Definition: t4_regs.h:38004
A_ULP_RX_LA_CTL
#define A_ULP_RX_LA_CTL
Definition: t4_regs.h:37412
A_PM_RX_DBG_CTRL
#define A_PM_RX_DBG_CTRL
Definition: t4_regs.h:29711
G_OFDRATE2
#define G_OFDRATE2(x)
Definition: t4_regs.h:24244
G_CIMQBASE
#define G_CIMQBASE(x)
Definition: t4_regs.h:20915
V_PKTFIFO
#define V_PKTFIFO(x)
Definition: t4_regs.h:33936
A_TP_MIB_FCOE_DDP_0
#define A_TP_MIB_FCOE_DDP_0
Definition: t4_regs.h:28734
F_MSTTIMEOUTPERR
#define F_MSTTIMEOUTPERR
Definition: t4_regs.h:4293
A_PM_TX_DBG_STAT0
#define A_PM_TX_DBG_STAT0
Definition: t4_regs.h:30742
A_SGE_CONTROL
#define A_SGE_CONTROL
Definition: t4_regs.h:578
F_ERR_BAD_DB_PIDX1
#define F_ERR_BAD_DB_PIDX1
Definition: t4_regs.h:1188
V_T6_VFWRADDR
#define V_T6_VFWRADDR(x)
Definition: t4_regs.h:23502
A_TP_MIB_TNL_OUT_PKT_0
#define A_TP_MIB_TNL_OUT_PKT_0
Definition: t4_regs.h:28697
V_QUENUMSELECT
#define V_QUENUMSELECT(x)
Definition: t4_regs.h:20902
F_UNCAPTURED_ERROR
#define F_UNCAPTURED_ERROR
Definition: t4_regs.h:2066
F_TRCMULTIFILTER
#define F_TRCMULTIFILTER
Definition: t4_regs.h:33807
A_MPS_STAT_CTL
#define A_MPS_STAT_CTL
Definition: t4_regs.h:33486
G_TIMERRESOLUTION
#define G_TIMERRESOLUTION(x)
Definition: t4_regs.h:22919
VF_SGE_REG
#define VF_SGE_REG(reg_addr)
Definition: t4_regs.h:70
F_CRSPPERR
#define F_CRSPPERR
Definition: t4_regs.h:4161
F_COUNTPAUSESTATTX
#define F_COUNTPAUSESTATTX
Definition: t4_regs.h:33530
A_MC_BIST_STATUS_RDATA
#define A_MC_BIST_STATUS_RDATA
Definition: t4_regs.h:16028
F_TP2CIMINTFPARERR
#define F_TP2CIMINTFPARERR
Definition: t4_regs.h:20580
M_TXTIMERSEPQ0
#define M_TXTIMERSEPQ0
Definition: t4_regs.h:24397
A_SGE_VF_GTS
#define A_SGE_VF_GTS
Definition: t4_regs.h:567
F_VLAN
#define F_VLAN
Definition: t4_regs.h:26815
A_MA_INT_CAUSE
#define A_MA_INT_CAUSE
Definition: t4_regs.h:16309
A_ULP_RX_LA_WRPTR
#define A_ULP_RX_LA_WRPTR
Definition: t4_regs.h:37426
A_CPL_INTR_ENABLE
#define A_CPL_INTR_ENABLE
Definition: t4_regs.h:35956
A_TP_MIB_FCOE_BYTE_0_HI
#define A_TP_MIB_FCOE_BYTE_0_HI
Definition: t4_regs.h:28742
VF_MPS_REG
#define VF_MPS_REG(reg_addr)
Definition: t4_regs.h:73
V_FILTMEM
#define V_FILTMEM(x)
Definition: t4_regs.h:33941
F_TP_FRAMING_ERROR
#define F_TP_FRAMING_ERROR
Definition: t4_regs.h:35968
F_OBQSGERX0PARERR
#define F_OBQSGERX0PARERR
Definition: t4_regs.h:20588
V_MTUWIDTH
#define V_MTUWIDTH(x)
Definition: t4_regs.h:23110
A_SGE_INT_ENABLE4
#define A_SGE_INT_ENABLE4
Definition: t4_regs.h:1997
A_SGE_EGRESS_QUEUES_PER_PAGE_PF
#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF
Definition: t4_regs.h:684
F_MBUPPARERR
#define F_MBUPPARERR
Definition: t4_regs.h:20496
G_T5_TFPORT
#define G_T5_TFPORT(x)
Definition: t4_regs.h:33888
F_PCIE
#define F_PCIE
Definition: t4_regs.h:37972
A_EDC_H_BIST_CMD_ADDR
#define A_EDC_H_BIST_CMD_ADDR
Definition: t4_regs.h:61857
F_EDC1
#define F_EDC1
Definition: t4_regs.h:37960
F_COUNTPAUSESTATRX
#define F_COUNTPAUSESTATRX
Definition: t4_regs.h:33522
A_MC_P_INT_ENABLE
#define A_MC_P_INT_ENABLE
Definition: t4_regs.h:58378
F_MSIXSTIPERR
#define F_MSIXSTIPERR
Definition: t4_regs.h:4289
G_NUMPORTS
#define G_NUMPORTS(x)
Definition: t4_regs.h:32411
A_PL_PL_INT_CAUSE
#define A_PL_PL_INT_CAUSE
Definition: t4_regs.h:38178
A_SGE_INT_ENABLE5
#define A_SGE_INT_ENABLE5
Definition: t4_regs.h:2248
A_MC_BIST_CMD
#define A_MC_BIST_CMD
Definition: t4_regs.h:15992
G_PILADBGWRPTR
#define G_PILADBGWRPTR(x)
Definition: t4_regs.h:21050
F_ERR_FLM_HINT
#define F_ERR_FLM_HINT
Definition: t4_regs.h:1128
A_ULP_TX_INT_ENABLE_2
#define A_ULP_TX_INT_ENABLE_2
Definition: t4_regs.h:29238
A_CIM_QUEUE_CONFIG_CTRL
#define A_CIM_QUEUE_CONFIG_CTRL
Definition: t4_regs.h:20905
A_CIM_HOST_UPACC_INT_CAUSE
#define A_CIM_HOST_UPACC_INT_CAUSE
Definition: t4_regs.h:20750
V_T5_TFINVERTMATCH
#define V_T5_TFINVERTMATCH(x)
Definition: t4_regs.h:33874
NUM_CIM_PF_MAILBOX_DATA_INSTANCES
#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES
Definition: t4_regs.h:146
A_SGE_INT_ENABLE6
#define A_SGE_INT_ENABLE6
Definition: t4_regs.h:2515
A_EDC_H_ECC_ERR_ADDR
#define A_EDC_H_ECC_ERR_ADDR
Definition: t4_regs.h:61895
A_SGE_TIMER_VALUE_2_AND_3
#define A_SGE_TIMER_VALUE_2_AND_3
Definition: t4_regs.h:1713
A_ULP_TX_INT_CAUSE
#define A_ULP_TX_INT_CAUSE
Definition: t4_regs.h:28989
G_MEM_WRAP_ADDRESS
#define G_MEM_WRAP_ADDRESS(x)
Definition: t4_regs.h:16328
F_EGRESS_SIZE_ERR
#define F_EGRESS_SIZE_ERR
Definition: t4_regs.h:1224
F_MATCHTCAM
#define F_MATCHTCAM
Definition: t4_regs.h:34245
F_MSTRXFIFOPARINT
#define F_MSTRXFIFOPARINT
Definition: t4_regs.h:36247
A_MC_P_INT_CAUSE
#define A_MC_P_INT_CAUSE
Definition: t4_regs.h:58379
A_TP_INGRESS_CONFIG
#define A_TP_INGRESS_CONFIG
Definition: t4_regs.h:26841
F_HRSPPERR
#define F_HRSPPERR
Definition: t4_regs.h:4137
G_T6_EGRTHRESHOLDPACKING
#define G_T6_EGRTHRESHOLDPACKING(x)
Definition: t4_regs.h:1459
A_MPS_TRC_FILTER_MATCH_CTL_B
#define A_MPS_TRC_FILTER_MATCH_CTL_B
Definition: t4_regs.h:33890
A_CIM_IBQ_DBG_DATA
#define A_CIM_IBQ_DBG_DATA
Definition: t4_regs.h:20996
F_FRMERR
#define F_FRMERR
Definition: t4_regs.h:32727
F_MPSHITTYPE
#define F_MPSHITTYPE
Definition: t4_regs.h:26795
F_SGLRDFLASHINT
#define F_SGLRDFLASHINT
Definition: t4_regs.h:20834
F_BLKRDFLASHINT
#define F_BLKRDFLASHINT
Definition: t4_regs.h:20826
A_PM_RX_DBG_DATA
#define A_PM_RX_DBG_DATA
Definition: t4_regs.h:29729
EDC_REG
#define EDC_REG(reg, idx)
Definition: t4_regs.h:507
A_XGMAC_PORT_HSS_CFG0
#define A_XGMAC_PORT_HSS_CFG0
Definition: t4_regs.h:41087
F_BLKRDCTLINT
#define F_BLKRDCTLINT
Definition: t4_regs.h:20794
t4_regs_values.h
W_FT_PORT
#define W_FT_PORT
Definition: t4_regs_values.h:290
X_MBOWNER_PL
#define X_MBOWNER_PL
Definition: t4_regs_values.h:264
X_MBOWNER_FW
#define X_MBOWNER_FW
Definition: t4_regs_values.h:263
W_FT_FRAGMENTATION
#define W_FT_FRAGMENTATION
Definition: t4_regs_values.h:298
W_FT_VLAN
#define W_FT_VLAN
Definition: t4_regs_values.h:292
W_FT_MPSHITTYPE
#define W_FT_MPSHITTYPE
Definition: t4_regs_values.h:297
W_FT_ETHERTYPE
#define W_FT_ETHERTYPE
Definition: t4_regs_values.h:295
X_INGPADBOUNDARY_SHIFT
#define X_INGPADBOUNDARY_SHIFT
Definition: t4_regs_values.h:97
W_FT_VNIC_ID
#define W_FT_VNIC_ID
Definition: t4_regs_values.h:291
W_FT_PROTOCOL
#define W_FT_PROTOCOL
Definition: t4_regs_values.h:294
SGE_UDB_SIZE
#define SGE_UDB_SIZE
Definition: t4_regs_values.h:249
W_FT_FCOE
#define W_FT_FCOE
Definition: t4_regs_values.h:289
W_FT_TOS
#define W_FT_TOS
Definition: t4_regs_values.h:293
X_MBOWNER_NONE
#define X_MBOWNER_NONE
Definition: t4_regs_values.h:262
W_FT_MACMATCH
#define W_FT_MACMATCH
Definition: t4_regs_values.h:296
X_T6_INGPADBOUNDARY_SHIFT
#define X_T6_INGPADBOUNDARY_SHIFT
Definition: t4_regs_values.h:87
tscale
static int tscale
Definition: t4_sge.c:190
t4fw_interface.h
G_FW_PORT_CMD_MODTYPE
#define G_FW_PORT_CMD_MODTYPE(x)
Definition: t4fw_interface.h:7628
V_FW_EQ_ETH_CMD_EQID
#define V_FW_EQ_ETH_CMD_EQID(x)
Definition: t4fw_interface.h:5984
V_FW_EQ_ETH_CMD_PFN
#define V_FW_EQ_ETH_CMD_PFN(x)
Definition: t4fw_interface.h:5937
V_FW_VI_MAC_CMD_VNI
#define V_FW_VI_MAC_CMD_VNI(x)
Definition: t4fw_interface.h:6808
G_FW_VI_MAC_CMD_RAW_IDX
#define G_FW_VI_MAC_CMD_RAW_IDX(x)
Definition: t4fw_interface.h:6783
FW_ENOMEM
@ FW_ENOMEM
Definition: t4fw_interface.h:44
FW_SUCCESS
@ FW_SUCCESS
Definition: t4fw_interface.h:38
FW_SCHED_PARAMS_UNIT_BITRATE
@ FW_SCHED_PARAMS_UNIT_BITRATE
Definition: t4fw_interface.h:8748
FW_VI_MAC_MAC_BASED_FREE
#define FW_VI_MAC_MAC_BASED_FREE
Definition: t4fw_interface.h:6663
V_FW_ACL_VLAN_CMD_VFN
#define V_FW_ACL_VLAN_CMD_VFN(x)
Definition: t4fw_interface.h:7089
V_FW_HELLO_CMD_MBASYNCNOT
#define V_FW_HELLO_CMD_MBASYNCNOT(x)
Definition: t4fw_interface.h:4564
V_FW_PFVF_CMD_WX_CAPS
#define V_FW_PFVF_CMD_WX_CAPS(x)
Definition: t4fw_interface.h:5186
FW_PORT_CAP32_FC_TX
#define FW_PORT_CAP32_FC_TX
Definition: t4fw_interface.h:7211
V_FW_VI_RXMODE_CMD_VLANEXEN
#define V_FW_VI_RXMODE_CMD_VLANEXEN(x)
Definition: t4fw_interface.h:6876
V_FW_RSS_VI_CONFIG_CMD_VIID
#define V_FW_RSS_VI_CONFIG_CMD_VIID(x)
Definition: t4fw_interface.h:8659
V_FW_PARAMS_PARAM_FILTER_MASK
#define V_FW_PARAMS_PARAM_FILTER_MASK(x)
Definition: t4fw_interface.h:4781
F_FW_VI_ENABLE_CMD_LED
#define F_FW_VI_ENABLE_CMD_LED
Definition: t4fw_interface.h:6913
M_FW_PORT_CAP32_FEC
#define M_FW_PORT_CAP32_FEC
Definition: t4fw_interface.h:7270
F_FW_RESET_CMD_HALT
#define F_FW_RESET_CMD_HALT
Definition: t4fw_interface.h:4505
F_FW_LDST_CMD_LC
#define F_FW_LDST_CMD_LC
Definition: t4fw_interface.h:4454
V_FW_VI_MAC_CMD_DIP_HIT
#define V_FW_VI_MAC_CMD_DIP_HIT(x)
Definition: t4fw_interface.h:6801
M_FW_VI_RXMODE_CMD_ALLMULTIEN
#define M_FW_VI_RXMODE_CMD_ALLMULTIEN
Definition: t4fw_interface.h:6861
V_FW_VI_RXMODE_CMD_MTU
#define V_FW_VI_RXMODE_CMD_MTU(x)
Definition: t4fw_interface.h:6850
V_FW_EQ_ETH_CMD_VFN
#define V_FW_EQ_ETH_CMD_VFN(x)
Definition: t4fw_interface.h:5943
V_FW_PFVF_CMD_NIQFLINT
#define V_FW_PFVF_CMD_NIQFLINT(x)
Definition: t4fw_interface.h:5125
FW_PORT_CAP32_SPEED_1G
#define FW_PORT_CAP32_SPEED_1G
Definition: t4fw_interface.h:7198
V_FW_PORT_CMD_PORTID
#define V_FW_PORT_CMD_PORTID(x)
Definition: t4fw_interface.h:7494
V_FW_CMD_LEN16
#define V_FW_CMD_LEN16(x)
Definition: t4fw_interface.h:4229
PCIE_FW_EVAL_CRASH
@ PCIE_FW_EVAL_CRASH
Definition: t4fw_interface.h:9794
FW_PORT_CAP32_FEC_RS
#define FW_PORT_CAP32_FEC_RS
Definition: t4fw_interface.h:7217
fec_supported
static bool fec_supported(uint32_t caps)
Definition: t4fw_interface.h:7286
V_FW_PARAMS_CMD_VFN
#define V_FW_PARAMS_CMD_VFN(x)
Definition: t4fw_interface.h:5095
FW_PORT_CAP32_FORCE_PAUSE
#define FW_PORT_CAP32_FORCE_PAUSE
Definition: t4fw_interface.h:7222
V_FW_PORT_CAP32_SPEED
#define V_FW_PORT_CAP32_SPEED(x)
Definition: t4fw_interface.h:7228
FW_CMD_HELLO_TIMEOUT
#define FW_CMD_HELLO_TIMEOUT
Definition: t4fw_interface.h:4118
V_FW_PORT_CAP32_MDI
#define V_FW_PORT_CAP32_MDI(x)
Definition: t4fw_interface.h:7265
F_FW_HELLO_CMD_ERR
#define F_FW_HELLO_CMD_ERR
Definition: t4fw_interface.h:4526
FW_HELLO_CMD_STAGE_OS
@ FW_HELLO_CMD_STAGE_OS
Definition: t4fw_interface.h:4508
F_FW_LDST_CMD_CTXTFLUSH
#define F_FW_LDST_CMD_CTXTFLUSH
Definition: t4fw_interface.h:4403
G_FW_HELLO_CMD_MBMASTER
#define G_FW_HELLO_CMD_MBMASTER(x)
Definition: t4fw_interface.h:4552
FW_LDST_ADDRSPC_SGE_INGC
@ FW_LDST_ADDRSPC_SGE_INGC
Definition: t4fw_interface.h:4240
FW_LDST_ADDRSPC_SGE_CONMC
@ FW_LDST_ADDRSPC_SGE_CONMC
Definition: t4fw_interface.h:4242
FW_LDST_ADDRSPC_SGE_FLMC
@ FW_LDST_ADDRSPC_SGE_FLMC
Definition: t4fw_interface.h:4241
FW_LDST_ADDRSPC_SGE_EGRC
@ FW_LDST_ADDRSPC_SGE_EGRC
Definition: t4fw_interface.h:4239
FW_LDST_ADDRSPC_MDIO
@ FW_LDST_ADDRSPC_MDIO
Definition: t4fw_interface.h:4246
FW_LDST_ADDRSPC_TP_TM_PIO
@ FW_LDST_ADDRSPC_TP_TM_PIO
Definition: t4fw_interface.h:4244
FW_LDST_ADDRSPC_FUNC_PCIE
@ FW_LDST_ADDRSPC_FUNC_PCIE
Definition: t4fw_interface.h:4249
FW_LDST_ADDRSPC_TP_MIB
@ FW_LDST_ADDRSPC_TP_MIB
Definition: t4fw_interface.h:4245
FW_LDST_ADDRSPC_TP_PIO
@ FW_LDST_ADDRSPC_TP_PIO
Definition: t4fw_interface.h:4243
FW_LDST_ADDRSPC_FIRMWARE
@ FW_LDST_ADDRSPC_FIRMWARE
Definition: t4fw_interface.h:4238
FW_LDST_ADDRSPC_I2C
@ FW_LDST_ADDRSPC_I2C
Definition: t4fw_interface.h:4252
V_FW_VI_CMD_PORTID
#define V_FW_VI_CMD_PORTID(x)
Definition: t4fw_interface.h:6631
V_FW_VI_MAC_CMD_IDX
#define V_FW_VI_MAC_CMD_IDX(x)
Definition: t4fw_interface.h:6776
G_FW_PARAMS_PARAM_FILTER_MODE
#define G_FW_PARAMS_PARAM_FILTER_MODE(x)
Definition: t4fw_interface.h:4775
V_FW_VI_MAC_CMD_ENTRY_TYPE
#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)
Definition: t4fw_interface.h:6744
FW_PORT_CAP_ANEG
@ FW_PORT_CAP_ANEG
Definition: t4fw_interface.h:7138
FW_PORT_CAP_SPEED_100M
@ FW_PORT_CAP_SPEED_100M
Definition: t4fw_interface.h:7130
FW_PORT_CAP_SPEED_40G
@ FW_PORT_CAP_SPEED_40G
Definition: t4fw_interface.h:7134
FW_PORT_CAP_SPEED_10G
@ FW_PORT_CAP_SPEED_10G
Definition: t4fw_interface.h:7133
FW_PORT_CAP_SPEED_1G
@ FW_PORT_CAP_SPEED_1G
Definition: t4fw_interface.h:7131
FW_PORT_CAP_SPEED_25G
@ FW_PORT_CAP_SPEED_25G
Definition: t4fw_interface.h:7132
FW_PORT_CAP_SPEED_100G
@ FW_PORT_CAP_SPEED_100G
Definition: t4fw_interface.h:7135
V_FW_FILTER_WR_NOREPLY
#define V_FW_FILTER_WR_NOREPLY(x)
Definition: t4fw_interface.h:414
FW_VNIC_MODE_PF_VF
@ FW_VNIC_MODE_PF_VF
Definition: t4fw_interface.h:4882
FW_VNIC_MODE_OUTER_VLAN
@ FW_VNIC_MODE_OUTER_VLAN
Definition: t4fw_interface.h:4883
M_FW_PORT_CAP32_SPEED
#define M_FW_PORT_CAP32_SPEED
Definition: t4fw_interface.h:7227
G_FW_PORT_CMD_PORTID
#define G_FW_PORT_CMD_PORTID(x)
Definition: t4fw_interface.h:7495
fw_port_action
fw_port_action
Definition: t4fw_interface.h:7293
FW_PORT_ACTION_GET_PORT_INFO
@ FW_PORT_ACTION_GET_PORT_INFO
Definition: t4fw_interface.h:7296
FW_PORT_ACTION_L1_CFG32
@ FW_PORT_ACTION_L1_CFG32
Definition: t4fw_interface.h:7302
FW_PORT_ACTION_L1_CFG
@ FW_PORT_ACTION_L1_CFG
Definition: t4fw_interface.h:7294
FW_PORT_ACTION_GET_PORT_INFO32
@ FW_PORT_ACTION_GET_PORT_INFO32
Definition: t4fw_interface.h:7303
G_FW_PORT_CMD_MDIOADDR
#define G_FW_PORT_CMD_MDIOADDR(x)
Definition: t4fw_interface.h:7596
F_FW_VI_MAC_CMD_VALID
#define F_FW_VI_MAC_CMD_VALID
Definition: t4fw_interface.h:6760
FW_SCHED_SC_PARAMS
@ FW_SCHED_SC_PARAMS
Definition: t4fw_interface.h:8728
FW_SCHED_SC_CONFIG
@ FW_SCHED_SC_CONFIG
Definition: t4fw_interface.h:8727
V_FW_WR_OP
#define V_FW_WR_OP(x)
Definition: t4fw_interface.h:169
V_FW_EQ_OFLD_CMD_VFN
#define V_FW_EQ_OFLD_CMD_VFN(x)
Definition: t4fw_interface.h:6343
V_FW_PFVF_CMD_TC
#define V_FW_PFVF_CMD_TC(x)
Definition: t4fw_interface.h:5162
G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG
#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x)
Definition: t4fw_interface.h:8879
FW_VI_MAC_ID_BASED_FREE
#define FW_VI_MAC_ID_BASED_FREE
Definition: t4fw_interface.h:6664
V_FW_EQ_OFLD_CMD_EQID
#define V_FW_EQ_OFLD_CMD_EQID(x)
Definition: t4fw_interface.h:6384
V_FW_VI_RXMODE_CMD_VIID
#define V_FW_VI_RXMODE_CMD_VIID(x)
Definition: t4fw_interface.h:6844
V_FW_VI_RXMODE_CMD_ALLMULTIEN
#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x)
Definition: t4fw_interface.h:6862
FW_PORT_CAP32_FEC_NO_FEC
#define FW_PORT_CAP32_FEC_NO_FEC
Definition: t4fw_interface.h:7219
V_FW_PFVF_CMD_CMASK
#define V_FW_PFVF_CMD_CMASK(x)
Definition: t4fw_interface.h:5144
V_FW_PFVF_CMD_VFN
#define V_FW_PFVF_CMD_VFN(x)
Definition: t4fw_interface.h:5119
V_FW_ACL_MAC_CMD_PFN
#define V_FW_ACL_MAC_CMD_PFN(x)
Definition: t4fw_interface.h:7055
FW_PORT_CAP32_ANEG
#define FW_PORT_CAP32_ANEG
Definition: t4fw_interface.h:7214
V_FW_HDR_FW_VER_MICRO
#define V_FW_HDR_FW_VER_MICRO(x)
Definition: t4fw_interface.h:9991
V_FW_RSS_IND_TBL_CMD_VIID
#define V_FW_RSS_IND_TBL_CMD_VIID(x)
Definition: t4fw_interface.h:8313
V_FW_PFVF_CMD_NETHCTRL
#define V_FW_PFVF_CMD_NETHCTRL(x)
Definition: t4fw_interface.h:5192
FW_LDST_CMD
@ FW_LDST_CMD
Definition: t4fw_interface.h:4122
FW_DEBUG_CMD
@ FW_DEBUG_CMD
Definition: t4fw_interface.h:4168
FW_VI_RXMODE_CMD
@ FW_VI_RXMODE_CMD
Definition: t4fw_interface.h:4137
FW_RSS_VI_CONFIG_CMD
@ FW_RSS_VI_CONFIG_CMD
Definition: t4fw_interface.h:4149
FW_IQ_CMD
@ FW_IQ_CMD
Definition: t4fw_interface.h:4130
FW_WATCHDOG_CMD
@ FW_WATCHDOG_CMD
Definition: t4fw_interface.h:4152
FW_PORT_CMD
@ FW_PORT_CMD
Definition: t4fw_interface.h:4142
FW_ACL_MAC_CMD
@ FW_ACL_MAC_CMD
Definition: t4fw_interface.h:4140
FW_RSS_GLB_CONFIG_CMD
@ FW_RSS_GLB_CONFIG_CMD
Definition: t4fw_interface.h:4148
FW_EQ_OFLD_CMD
@ FW_EQ_OFLD_CMD
Definition: t4fw_interface.h:4134
FW_ACL_VLAN_CMD
@ FW_ACL_VLAN_CMD
Definition: t4fw_interface.h:4141
FW_VI_MAC_CMD
@ FW_VI_MAC_CMD
Definition: t4fw_interface.h:4136
FW_DEVLOG_CMD
@ FW_DEVLOG_CMD
Definition: t4fw_interface.h:4151
FW_EQ_CTRL_CMD
@ FW_EQ_CTRL_CMD
Definition: t4fw_interface.h:4133
FW_VI_ENABLE_CMD
@ FW_VI_ENABLE_CMD
Definition: t4fw_interface.h:4138
FW_RSS_IND_TBL_CMD
@ FW_RSS_IND_TBL_CMD
Definition: t4fw_interface.h:4147
FW_VI_CMD
@ FW_VI_CMD
Definition: t4fw_interface.h:4135
FW_SCHED_CMD
@ FW_SCHED_CMD
Definition: t4fw_interface.h:4150
FW_PARAMS_CMD
@ FW_PARAMS_CMD
Definition: t4fw_interface.h:4128
FW_PFVF_CMD
@ FW_PFVF_CMD
Definition: t4fw_interface.h:4129
FW_EQ_ETH_CMD
@ FW_EQ_ETH_CMD
Definition: t4fw_interface.h:4132
V_FW_LDST_CMD_FN
#define V_FW_LDST_CMD_FN(x)
Definition: t4fw_interface.h:4465
V_FW_VI_MAC_CMD_RAW_IDX
#define V_FW_VI_MAC_CMD_RAW_IDX(x)
Definition: t4fw_interface.h:6782
G_FW_VIID_VIN
#define G_FW_VIID_VIN(x)
Definition: t4fw_interface.h:6523
FW_PORT_CAP32_MDI_AUTO
@ FW_PORT_CAP32_MDI_AUTO
Definition: t4fw_interface.h:7258
FW_CMD_HELLO_RETRIES
#define FW_CMD_HELLO_RETRIES
Definition: t4fw_interface.h:4119
FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
Definition: t4fw_interface.h:8534
V_FW_PFVF_CMD_NEQ
#define V_FW_PFVF_CMD_NEQ(x)
Definition: t4fw_interface.h:5156
FW_PORT_CAP32_SPEED_100G
#define FW_PORT_CAP32_SPEED_100G
Definition: t4fw_interface.h:7203
M_FW_VI_RXMODE_CMD_PROMISCEN
#define M_FW_VI_RXMODE_CMD_PROMISCEN
Definition: t4fw_interface.h:6855
FW_VI_MAC_TYPE_EXACTMAC_VNI
@ FW_VI_MAC_TYPE_EXACTMAC_VNI
Definition: t4fw_interface.h:6684
FW_VI_MAC_TYPE_HASHVEC
@ FW_VI_MAC_TYPE_HASHVEC
Definition: t4fw_interface.h:6682
FW_VI_MAC_TYPE_EXACTMAC
@ FW_VI_MAC_TYPE_EXACTMAC
Definition: t4fw_interface.h:6681
FW_VI_MAC_TYPE_RAW
@ FW_VI_MAC_TYPE_RAW
Definition: t4fw_interface.h:6683
FW_VI_FUNC_ETH
@ FW_VI_FUNC_ETH
Definition: t4fw_interface.h:6543
M_FW_VIID_VIN
#define M_FW_VIID_VIN
Definition: t4fw_interface.h:6521
V_FW_WR_LEN16
#define V_FW_WR_LEN16(x)
Definition: t4fw_interface.h:236
V_FW_PARAMS_PARAM_Y
#define V_FW_PARAMS_PARAM_Y(x)
Definition: t4fw_interface.h:5017
FW_PORT_CAP32_FC_RX
#define FW_PORT_CAP32_FC_RX
Definition: t4fw_interface.h:7210
F_FW_FILTER_WR_DEL_FILTER
#define F_FW_FILTER_WR_DEL_FILTER
Definition: t4fw_interface.h:430
F_FW_ACL_VLAN_CMD_EN
#define F_FW_ACL_VLAN_CMD_EN
Definition: t4fw_interface.h:7098
F_PCIE_FW_ERR
#define F_PCIE_FW_ERR
Definition: t4fw_interface.h:9813
V_FW_PFVF_CMD_NVI
#define V_FW_PFVF_CMD_NVI(x)
Definition: t4fw_interface.h:5168
V_FW_HELLO_CMD_MBMASTER
#define V_FW_HELLO_CMD_MBMASTER(x)
Definition: t4fw_interface.h:4551
V_FW_FILTER_WR_TID
#define V_FW_FILTER_WR_TID(x)
Definition: t4fw_interface.h:401
V_FW_HDR_FW_VER_MINOR
#define V_FW_HDR_FW_VER_MINOR(x)
Definition: t4fw_interface.h:9984
V_FW_RSS_GLB_CONFIG_CMD_MODE
#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x)
Definition: t4fw_interface.h:8530
FW_PORT_CAP32_FORCE_FEC
#define FW_PORT_CAP32_FORCE_FEC
Definition: t4fw_interface.h:7223
F_FW_HELLO_CMD_CLEARINIT
#define F_FW_HELLO_CMD_CLEARINIT
Definition: t4fw_interface.h:4579
V_FW_PARAMS_PARAM_YZ
#define V_FW_PARAMS_PARAM_YZ(x)
Definition: t4fw_interface.h:5035
G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG
#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x)
Definition: t4fw_interface.h:8872
M_FW_VI_RXMODE_CMD_MTU
#define M_FW_VI_RXMODE_CMD_MTU
Definition: t4fw_interface.h:6849
F_FW_PORT_CMD_TXPAUSE
#define F_FW_PORT_CMD_TXPAUSE
Definition: t4fw_interface.h:7577
FW_PORT_CAP32_SPEED_10G
#define FW_PORT_CAP32_SPEED_10G
Definition: t4fw_interface.h:7199
V_FW_RSS_IND_TBL_CMD_IQ2
#define V_FW_RSS_IND_TBL_CMD_IQ2(x)
Definition: t4fw_interface.h:8331
G_PCIE_FW_EVAL
#define G_PCIE_FW_EVAL(x)
Definition: t4fw_interface.h:9830
F_FW_VI_CMD_NORSS
#define F_FW_VI_CMD_NORSS
Definition: t4fw_interface.h:6640
F_FW_PORT_CMD_RXPAUSE
#define F_FW_PORT_CMD_RXPAUSE
Definition: t4fw_interface.h:7584
V_FW_CMD_EXEC
#define V_FW_CMD_EXEC(x)
Definition: t4fw_interface.h:4213
V_FW_CMD_RETVAL
#define V_FW_CMD_RETVAL(x)
Definition: t4fw_interface.h:4224
V_FW_HELLO_CMD_STAGE
#define V_FW_HELLO_CMD_STAGE(x)
Definition: t4fw_interface.h:4570
F_FW_ACL_VLAN_CMD_DROPNOVLAN
#define F_FW_ACL_VLAN_CMD_DROPNOVLAN
Definition: t4fw_interface.h:7119
G_FW_PORT_CMD_ACTION
#define G_FW_PORT_CMD_ACTION(x)
Definition: t4fw_interface.h:7501
F_FW_CMD_WRITE
#define F_FW_CMD_WRITE
Definition: t4fw_interface.h:4209
G_PCIE_FW_PF_DEVLOG_MEMTYPE
#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x)
Definition: t4fw_interface.h:9934
FW_T4VF_MBDATA_BASE_ADDR
#define FW_T4VF_MBDATA_BASE_ADDR
Definition: t4fw_interface.h:4635
G_FW_PARAMS_PARAM_FILTER_MASK
#define G_FW_PARAMS_PARAM_FILTER_MASK(x)
Definition: t4fw_interface.h:4783
G_FW_PORT_CMD_MDIOADDR32
#define G_FW_PORT_CMD_MDIOADDR32(x)
Definition: t4fw_interface.h:7722
FW_PARAMS_PARAM_DEV_RSSINFO
@ FW_PARAMS_PARAM_DEV_RSSINFO
Definition: t4fw_interface.h:4818
FW_PARAMS_PARAM_DEV_TPCHMAP
@ FW_PARAMS_PARAM_DEV_TPCHMAP
Definition: t4fw_interface.h:4825
FW_PARAMS_PARAM_DEV_FILTER
@ FW_PARAMS_PARAM_DEV_FILTER
Definition: t4fw_interface.h:4840
FW_PARAMS_PARAM_DEV_RING_BACKBONE
@ FW_PARAMS_PARAM_DEV_RING_BACKBONE
Definition: t4fw_interface.h:4828
FW_PARAMS_PARAM_DEV_VPDREV
@ FW_PARAMS_PARAM_DEV_VPDREV
Definition: t4fw_interface.h:4820
FW_PARAMS_PARAM_DEV_FWCACHE
@ FW_PARAMS_PARAM_DEV_FWCACHE
Definition: t4fw_interface.h:4817
FW_PARAMS_PARAM_DEV_SCFGREV
@ FW_PARAMS_PARAM_DEV_SCFGREV
Definition: t4fw_interface.h:4819
FW_PARAMS_PARAM_DEV_MCINIT
@ FW_PARAMS_PARAM_DEV_MCINIT
Definition: t4fw_interface.h:4815
FW_PARAMS_PARAM_DEV_ADD_SMAC
@ FW_PARAMS_PARAM_DEV_ADD_SMAC
Definition: t4fw_interface.h:4831
FW_HDR_MAGIC_BOOTSTRAP
@ FW_HDR_MAGIC_BOOTSTRAP
Definition: t4fw_interface.h:10061
G_FW_CMD_RETVAL
#define G_FW_CMD_RETVAL(x)
Definition: t4fw_interface.h:4225
G_FW_VI_CMD_VFVLD
#define G_FW_VI_CMD_VFVLD(x)
Definition: t4fw_interface.h:6600
FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
Definition: t4fw_interface.h:8535
V_FW_PFVF_CMD_R_CAPS
#define V_FW_PFVF_CMD_R_CAPS(x)
Definition: t4fw_interface.h:5180
V_FW_FILTER_WR_RX_RPL_IQ
#define V_FW_FILTER_WR_RX_RPL_IQ(x)
Definition: t4fw_interface.h:593
F_FW_EQ_ETH_CMD_EQSTOP
#define F_FW_EQ_ETH_CMD_EQSTOP
Definition: t4fw_interface.h:5980
V_FW_VI_RXMODE_CMD_PROMISCEN
#define V_FW_VI_RXMODE_CMD_PROMISCEN(x)
Definition: t4fw_interface.h:6856
V_FW_PFVF_CMD_NEXACTF
#define V_FW_PFVF_CMD_NEXACTF(x)
Definition: t4fw_interface.h:5174
V_FW_IQ_CMD_PFN
#define V_FW_IQ_CMD_PFN(x)
Definition: t4fw_interface.h:5236
F_FW_IQ_CMD_FREE
#define F_FW_IQ_CMD_FREE
Definition: t4fw_interface.h:5258
V_FW_VI_CMD_VIID
#define V_FW_VI_CMD_VIID(x)
Definition: t4fw_interface.h:6625
F_FW_IQ_CMD_IQSTOP
#define F_FW_IQ_CMD_IQSTOP
Definition: t4fw_interface.h:5279
F_FW_PORT_CMD_LSTATUS32
#define F_FW_PORT_CMD_LSTATUS32
Definition: t4fw_interface.h:7697
V_FW_PORT_CAP32_FEC
#define V_FW_PORT_CAP32_FEC(x)
Definition: t4fw_interface.h:7271
FW_T6VF_MBDATA_BASE_ADDR
#define FW_T6VF_MBDATA_BASE_ADDR
Definition: t4fw_interface.h:4636
F_FW_HELLO_CMD_INIT
#define F_FW_HELLO_CMD_INIT
Definition: t4fw_interface.h:4533
FW_PORT_MOD_TYPE_NONE
@ FW_PORT_MOD_TYPE_NONE
Definition: t4fw_interface.h:7828
V_FW_VI_RXMODE_CMD_BROADCASTEN
#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x)
Definition: t4fw_interface.h:6869
F_FW_EQ_CTRL_CMD_FREE
#define F_FW_EQ_CTRL_CMD_FREE
Definition: t4fw_interface.h:6172
FW_PORT_CAP32_SPEED_50G
#define FW_PORT_CAP32_SPEED_50G
Definition: t4fw_interface.h:7202
V_FW_VI_ENABLE_CMD_VIID
#define V_FW_VI_ENABLE_CMD_VIID(x)
Definition: t4fw_interface.h:6890
V_FW_VI_MAC_CMD_VNI_MASK
#define V_FW_VI_MAC_CMD_VNI_MASK(x)
Definition: t4fw_interface.h:6827
V_FW_IQ_CMD_TYPE
#define V_FW_IQ_CMD_TYPE(x)
Definition: t4fw_interface.h:5283
F_PCIE_FW_HALT
#define F_PCIE_FW_HALT
Definition: t4fw_interface.h:9825
G_FW_PORT_CMD_PORTTYPE32
#define G_FW_PORT_CMD_PORTTYPE32(x)
Definition: t4fw_interface.h:7728
FW_PORT_CAP32_FEC_BASER_RS
#define FW_PORT_CAP32_FEC_BASER_RS
Definition: t4fw_interface.h:7218
F_FW_EQ_ETH_CMD_FREE
#define F_FW_EQ_ETH_CMD_FREE
Definition: t4fw_interface.h:5959
FW_VI_MAC_ADD_MAC
#define FW_VI_MAC_ADD_MAC
Definition: t4fw_interface.h:6661
F_PCIE_FW_MASTER_VLD
#define F_PCIE_FW_MASTER_VLD
Definition: t4fw_interface.h:9864
V_FW_HELLO_CMD_MASTERDIS
#define V_FW_HELLO_CMD_MASTERDIS(x)
Definition: t4fw_interface.h:4537
G_FW_VI_MAC_CMD_IDX
#define G_FW_VI_MAC_CMD_IDX(x)
Definition: t4fw_interface.h:6777
V_FW_VI_ENABLE_CMD_IEN
#define V_FW_VI_ENABLE_CMD_IEN(x)
Definition: t4fw_interface.h:6896
V_FW_VI_MAC_CMD_HASHUNIEN
#define V_FW_VI_MAC_CMD_HASHUNIEN(x)
Definition: t4fw_interface.h:6750
V_FW_PARAMS_MNEM
#define V_FW_PARAMS_MNEM(x)
Definition: t4fw_interface.h:5005
FW_HDR_CHIP_T5
@ FW_HDR_CHIP_T5
Definition: t4fw_interface.h:9971
FW_HDR_CHIP_T4
@ FW_HDR_CHIP_T4
Definition: t4fw_interface.h:9970
FW_HDR_CHIP_T6
@ FW_HDR_CHIP_T6
Definition: t4fw_interface.h:9972
V_FW_LDST_CMD_ADDRSPACE
#define V_FW_LDST_CMD_ADDRSPACE(x)
Definition: t4fw_interface.h:4381
G_FW_CMD_OP
#define G_FW_CMD_OP(x)
Definition: t4fw_interface.h:4191
V_FW_PORT_CMD_LSPEED
#define V_FW_PORT_CMD_LSPEED(x)
Definition: t4fw_interface.h:7568
G_PCIE_FW_PF_DEVLOG_ADDR16
#define G_PCIE_FW_PF_DEVLOG_ADDR16(x)
Definition: t4fw_interface.h:9928
V_FW_VI_CMD_VFN
#define V_FW_VI_CMD_VFN(x)
Definition: t4fw_interface.h:6579
FW_CMD_CAP_PORT
@ FW_CMD_CAP_PORT
Definition: t4fw_interface.h:4174
F_FW_VI_MAC_CMD_IS_SMAC
#define F_FW_VI_MAC_CMD_IS_SMAC
Definition: t4fw_interface.h:6740
V_FW_PFVF_CMD_PMASK
#define V_FW_PFVF_CMD_PMASK(x)
Definition: t4fw_interface.h:5150
G_FW_VI_CMD_VIN
#define G_FW_VI_CMD_VIN(x)
Definition: t4fw_interface.h:6607
V_FW_VI_CMD_TYPE
#define V_FW_VI_CMD_TYPE(x)
Definition: t4fw_interface.h:6612
V_FW_LDST_CMD_MMD
#define V_FW_LDST_CMD_MMD(x)
Definition: t4fw_interface.h:4413
fw_port_type
fw_port_type
Definition: t4fw_interface.h:7780
V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ
#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)
Definition: t4fw_interface.h:8665
V_FW_CMD_OP
#define V_FW_CMD_OP(x)
Definition: t4fw_interface.h:4190
G_FW_PORT_CMD_MODTYPE32
#define G_FW_PORT_CMD_MODTYPE32(x)
Definition: t4fw_interface.h:7734
PCIE_FW_PF_DEVLOG
#define PCIE_FW_PF_DEVLOG
Definition: t4fw_interface.h:9915
V_FW_RSS_IND_TBL_CMD_IQ1
#define V_FW_RSS_IND_TBL_CMD_IQ1(x)
Definition: t4fw_interface.h:8325
M_PCIE_FW_MASTER
#define M_PCIE_FW_MASTER
Definition: t4fw_interface.h:9867
V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX
#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x)
Definition: t4fw_interface.h:8720
V_FW_PORT_CMD_ACTION
#define V_FW_PORT_CMD_ACTION(x)
Definition: t4fw_interface.h:7500
G_FW_PORT_CMD_LINKDNRC32
#define G_FW_PORT_CMD_LINKDNRC32(x)
Definition: t4fw_interface.h:7702
F_FW_VI_CMD_FREE
#define F_FW_VI_CMD_FREE
Definition: t4fw_interface.h:6595
FW_FILTER_WR
@ FW_FILTER_WR
Definition: t4fw_interface.h:99
G_FW_VI_MAC_CMD_SMTID
#define G_FW_VI_MAC_CMD_SMTID(x)
Definition: t4fw_interface.h:6719
F_FW_CMD_READ
#define F_FW_CMD_READ
Definition: t4fw_interface.h:4203
F_FW_PORT_CMD_MDIOCAP32
#define F_FW_PORT_CMD_MDIOCAP32
Definition: t4fw_interface.h:7717
FW_PORT_CAP32_SPEED_100M
#define FW_PORT_CAP32_SPEED_100M
Definition: t4fw_interface.h:7197
G_FW_PORT_CMD_PTYPE
#define G_FW_PORT_CMD_PTYPE(x)
Definition: t4fw_interface.h:7616
V_FW_EQ_CTRL_CMD_EQID
#define V_FW_EQ_CTRL_CMD_EQID(x)
Definition: t4fw_interface.h:6203
M_FW_VI_RXMODE_CMD_VLANEXEN
#define M_FW_VI_RXMODE_CMD_VLANEXEN
Definition: t4fw_interface.h:6875
F_PCIE_FW_INIT
#define F_PCIE_FW_INIT
Definition: t4fw_interface.h:9819
V_FW_HELLO_CMD_MASTERFORCE
#define V_FW_HELLO_CMD_MASTERFORCE(x)
Definition: t4fw_interface.h:4544
V_FW_VI_MAC_CMD_SMAC_RESULT
#define V_FW_VI_MAC_CMD_SMAC_RESULT(x)
Definition: t4fw_interface.h:6770
F_FW_VI_CMD_ALLOC
#define F_FW_VI_CMD_ALLOC
Definition: t4fw_interface.h:6588
F_FW_EQ_OFLD_CMD_FREE
#define F_FW_EQ_OFLD_CMD_FREE
Definition: t4fw_interface.h:6359
FW_PORT_CAP32_SPEED_40G
#define FW_PORT_CAP32_SPEED_40G
Definition: t4fw_interface.h:7201
V_FW_HDR_FW_VER_BUILD
#define V_FW_HDR_FW_VER_BUILD(x)
Definition: t4fw_interface.h:9998
FW_SCHED_PARAMS_LEVEL_CL_RL
@ FW_SCHED_PARAMS_LEVEL_CL_RL
Definition: t4fw_interface.h:8737
FW_SCHED_PARAMS_LEVEL_CH_RL
@ FW_SCHED_PARAMS_LEVEL_CH_RL
Definition: t4fw_interface.h:8739
FW_SCHED_PARAMS_LEVEL_CL_WRR
@ FW_SCHED_PARAMS_LEVEL_CL_WRR
Definition: t4fw_interface.h:8738
F_FW_CMD_REQUEST
#define F_FW_CMD_REQUEST
Definition: t4fw_interface.h:4197
V_FW_VI_ENABLE_CMD_EEN
#define V_FW_VI_ENABLE_CMD_EEN(x)
Definition: t4fw_interface.h:6903
G_FW_VI_CMD_RSSSIZE
#define G_FW_VI_CMD_RSSSIZE(x)
Definition: t4fw_interface.h:6645
V_FW_VI_MAC_CMD_VIID
#define V_FW_VI_MAC_CMD_VIID(x)
Definition: t4fw_interface.h:6724
G_PCIE_FW_PF_DEVLOG_NENTRIES128
#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x)
Definition: t4fw_interface.h:9921
V_FW_EQ_CTRL_CMD_VFN
#define V_FW_EQ_CTRL_CMD_VFN(x)
Definition: t4fw_interface.h:6156
F_FW_CMD_EXEC
#define F_FW_CMD_EXEC
Definition: t4fw_interface.h:4215
FW_PARAMS_MNEM_DEV
@ FW_PARAMS_MNEM_DEV
Definition: t4fw_interface.h:4760
G_FW_PORT_CMD_LINKDNRC
#define G_FW_PORT_CMD_LINKDNRC(x)
Definition: t4fw_interface.h:7622
fw_params_param_dev_fwcache
fw_params_param_dev_fwcache
Definition: t4fw_interface.h:4894
V_FW_PARAMS_PARAM_X
#define V_FW_PARAMS_PARAM_X(x)
Definition: t4fw_interface.h:5011
V_FW_HDR_FW_VER_MAJOR
#define V_FW_HDR_FW_VER_MAJOR(x)
Definition: t4fw_interface.h:9977
G_FW_VI_CMD_VIID
#define G_FW_VI_CMD_VIID(x)
Definition: t4fw_interface.h:6626
FW_T4VF_REGMAP_SIZE
#define FW_T4VF_REGMAP_SIZE
Definition: t4fw_interface.h:4640
G_FW_VIID_VIVLD
#define G_FW_VIID_VIVLD(x)
Definition: t4fw_interface.h:6518
FW_SCHED_PARAMS_RATE_ABS
@ FW_SCHED_PARAMS_RATE_ABS
Definition: t4fw_interface.h:8754
V_FW_LDST_CMD_NACCESS
#define V_FW_LDST_CMD_NACCESS(x)
Definition: t4fw_interface.h:4477
V_FW_VI_ENABLE_CMD_DCB_INFO
#define V_FW_VI_ENABLE_CMD_DCB_INFO(x)
Definition: t4fw_interface.h:6917
FW_VI_MAC_MPS_TCAM_ENTRY
@ FW_VI_MAC_MPS_TCAM_ENTRY
Definition: t4fw_interface.h:6667
FW_VI_MAC_SMT_AND_MPSTCAM
@ FW_VI_MAC_SMT_AND_MPSTCAM
Definition: t4fw_interface.h:6670
V_FW_VI_CMD_FUNC
#define V_FW_VI_CMD_FUNC(x)
Definition: t4fw_interface.h:6619
M_FW_HELLO_CMD_MBMASTER
#define M_FW_HELLO_CMD_MBMASTER
Definition: t4fw_interface.h:4550
G_PCIE_FW_MASTER
#define G_PCIE_FW_MASTER(x)
Definition: t4fw_interface.h:9869
V_FW_VI_CMD_PFN
#define V_FW_VI_CMD_PFN(x)
Definition: t4fw_interface.h:6573
V_FW_PARAMS_PARAM_FILTER_MODE
#define V_FW_PARAMS_PARAM_FILTER_MODE(x)
Definition: t4fw_interface.h:4773
V_FW_IQ_CMD_VFN
#define V_FW_IQ_CMD_VFN(x)
Definition: t4fw_interface.h:5242
V_FW_RSS_IND_TBL_CMD_IQ0
#define V_FW_RSS_IND_TBL_CMD_IQ0(x)
Definition: t4fw_interface.h:8319
F_FW_PORT_CMD_LSTATUS
#define F_FW_PORT_CMD_LSTATUS
Definition: t4fw_interface.h:7564
V_FW_EQ_CTRL_CMD_PFN
#define V_FW_EQ_CTRL_CMD_PFN(x)
Definition: t4fw_interface.h:6150
V_FW_PARAMS_CMD_PFN
#define V_FW_PARAMS_CMD_PFN(x)
Definition: t4fw_interface.h:5089
FW_SCHED_TYPE_PKTSCHED
@ FW_SCHED_TYPE_PKTSCHED
Definition: t4fw_interface.h:8732
FW_CMD_MAX_TIMEOUT
#define FW_CMD_MAX_TIMEOUT
Definition: t4fw_interface.h:4109
F_FW_PORT_CMD_MDIOCAP
#define F_FW_PORT_CMD_MDIOCAP
Definition: t4fw_interface.h:7591
V_FW_PFVF_CMD_NIQ
#define V_FW_PFVF_CMD_NIQ(x)
Definition: t4fw_interface.h:5131
V_FW_ACL_MAC_CMD_VFN
#define V_FW_ACL_MAC_CMD_VFN(x)
Definition: t4fw_interface.h:7061
V_FW_PFVF_CMD_PFN
#define V_FW_PFVF_CMD_PFN(x)
Definition: t4fw_interface.h:5113
FW_PORT_CAP32_SPEED_25G
#define FW_PORT_CAP32_SPEED_25G
Definition: t4fw_interface.h:7200
FW_PARAM_DEV_FILTER_VNIC_MODE
@ FW_PARAM_DEV_FILTER_VNIC_MODE
Definition: t4fw_interface.h:4877
FW_PARAM_DEV_FILTER_MODE_MASK
@ FW_PARAM_DEV_FILTER_MODE_MASK
Definition: t4fw_interface.h:4878
V_FW_VI_MAC_CMD_LOOKUP_TYPE
#define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x)
Definition: t4fw_interface.h:6794
F_FW_ACL_VLAN_CMD_FM
#define F_FW_ACL_VLAN_CMD_FM
Definition: t4fw_interface.h:7126
FW_LEN16
#define FW_LEN16(fw_struct)
Definition: t4fw_interface.h:4232
V_FW_EQ_OFLD_CMD_PFN
#define V_FW_EQ_OFLD_CMD_PFN(x)
Definition: t4fw_interface.h:6337
V_FW_ACL_VLAN_CMD_PFN
#define V_FW_ACL_VLAN_CMD_PFN(x)
Definition: t4fw_interface.h:7083
V_FW_LDST_CMD_PADDR
#define V_FW_LDST_CMD_PADDR(x)
Definition: t4fw_interface.h:4407
FW_VI_MAC_ADD_PERSIST_MAC
#define FW_VI_MAC_ADD_PERSIST_MAC
Definition: t4fw_interface.h:6662
M_FW_VI_RXMODE_CMD_BROADCASTEN
#define M_FW_VI_RXMODE_CMD_BROADCASTEN
Definition: t4fw_interface.h:6868
V_FW_VI_MAC_CMD_FREEMACS
#define V_FW_VI_MAC_CMD_FREEMACS(x)
Definition: t4fw_interface.h:6730
fw_debug_cmd::fw_debug::assert
struct fw_debug_cmd::fw_debug::fw_debug_assert assert
fw_ldst_cmd::fw_ldst::idctxt
struct fw_ldst_cmd::fw_ldst::fw_ldst_idctxt idctxt
fw_ldst_cmd::fw_ldst::addrval
struct fw_ldst_cmd::fw_ldst::fw_ldst_addrval addrval
fw_ldst_cmd::fw_ldst::i2c
struct fw_ldst_cmd::fw_ldst::fw_ldst_i2c i2c
fw_ldst_cmd::fw_ldst::mdio
struct fw_ldst_cmd::fw_ldst::fw_ldst_mdio mdio
fw_ldst_cmd::fw_ldst::pcie
struct fw_ldst_cmd::fw_ldst::fw_ldst_pcie pcie
fw_port_cmd::fw_port::l1cfg32
struct fw_port_cmd::fw_port::fw_port_l1cfg32 l1cfg32
fw_port_cmd::fw_port::info
struct fw_port_cmd::fw_port::fw_port_info info
fw_port_cmd::fw_port::info32
struct fw_port_cmd::fw_port::fw_port_info32 info32
fw_port_cmd::fw_port::l1cfg
struct fw_port_cmd::fw_port::fw_port_l1cfg l1cfg
fw_rss_glb_config_cmd::fw_rss_glb_config::basicvirtual
struct fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual basicvirtual
fw_rss_glb_config_cmd::fw_rss_glb_config::manual
struct fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual manual
fw_rss_vi_config_cmd::fw_rss_vi_config::basicvirtual
struct fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual basicvirtual
fw_sched_cmd::fw_sched::params
struct fw_sched_cmd::fw_sched::fw_sched_params params
fw_sched_cmd::fw_sched::config
struct fw_sched_cmd::fw_sched::fw_sched_config config
fw_vi_mac_cmd::fw_vi_mac::exact_vni
struct fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni exact_vni[2]
fw_vi_mac_cmd::fw_vi_mac::hash
struct fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_hash hash
fw_vi_mac_cmd::fw_vi_mac::raw
struct fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw raw
fw_vi_mac_cmd::fw_vi_mac::exact
struct fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_exact exact[7]