d7/d70/t4fw__interface_8h_source.html

/*-

 * Copyright (c) 2012-2017 Chelsio Communications, Inc.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND

 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

 * SUCH DAMAGE.

 *

 * $FreeBSD$

 *

 */


#ifndef _T4FW_INTERFACE_H_

#define _T4FW_INTERFACE_H_


/******************************************************************************

 *   R E T U R N   V A L U E S

 ********************************/


enum fw_retval {

        FW_SUCCESS              = 0,    /* completed successfully */

        FW_EPERM                = 1,    /* operation not permitted */

        FW_ENOENT               = 2,    /* no such file or directory */

        FW_EIO                  = 5,    /* input/output error; hw bad */

        FW_ENOEXEC              = 8,    /* exec format error; inv microcode */

        FW_EAGAIN               = 11,   /* try again */

        FW_ENOMEM               = 12,   /* out of memory */

        FW_EFAULT               = 14,   /* bad address; fw bad */

        FW_EBUSY                = 16,   /* resource busy */

        FW_EEXIST               = 17,   /* file exists */

        FW_ENODEV               = 19,   /* no such device */

        FW_EINVAL               = 22,   /* invalid argument */

        FW_ENOSPC               = 28,   /* no space left on device */

        FW_ENOSYS               = 38,   /* functionality not implemented */

        FW_ENODATA              = 61,   /* no data available */

        FW_EPROTO               = 71,   /* protocol error */

        FW_EADDRINUSE           = 98,   /* address already in use */

        FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */

        FW_ENETDOWN             = 100,  /* network is down */

        FW_ENETUNREACH          = 101,  /* network is unreachable */

        FW_ENOBUFS              = 105,  /* no buffer space available */

        FW_ETIMEDOUT            = 110,  /* timeout */

        FW_EINPROGRESS          = 115,  /* fw internal */

        FW_SCSI_ABORT_REQUESTED = 128,  /* */

        FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */

        FW_SCSI_ABORTED         = 130,  /* */

        FW_SCSI_CLOSE_REQUESTED = 131,  /* */

        FW_ERR_LINK_DOWN        = 132,  /* */

        FW_RDEV_NOT_READY       = 133,  /* */

        FW_ERR_RDEV_LOST        = 134,  /* */

        FW_ERR_RDEV_LOGO        = 135,  /* */

        FW_FCOE_NO_XCHG         = 136,  /* */

        FW_SCSI_RSP_ERR         = 137,  /* */

        FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */

        FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */

        FW_SCSI_OVER_FLOW_ERR   = 140,  /* */

        FW_SCSI_DDP_ERR         = 141,  /* DDP error*/

        FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */

        FW_SCSI_IO_BLOCK        = 143,  /* IO is going to be blocked due to resource failure */

};


/******************************************************************************

 *   M E M O R Y   T Y P E s

 ******************************/


enum fw_memtype {

        FW_MEMTYPE_EDC0         = 0x0,

        FW_MEMTYPE_EDC1         = 0x1,

        FW_MEMTYPE_EXTMEM       = 0x2,

        FW_MEMTYPE_FLASH        = 0x4,

        FW_MEMTYPE_INTERNAL     = 0x5,

        FW_MEMTYPE_EXTMEM1      = 0x6,

        FW_MEMTYPE_HMA          = 0x7,

};


/******************************************************************************

 *   W O R K   R E Q U E S T s

 ********************************/


enum fw_wr_opcodes {

        FW_FRAG_WR              = 0x1d,

        FW_FILTER_WR            = 0x02,

        FW_ULPTX_WR             = 0x04,

        FW_TP_WR                = 0x05,

        FW_ETH_TX_PKT_WR        = 0x08,

        FW_ETH_TX_PKT2_WR       = 0x44,

        FW_ETH_TX_PKTS_WR       = 0x09,

        FW_ETH_TX_PKTS2_WR      = 0x78,

        FW_ETH_TX_EO_WR         = 0x1c,

        FW_EQ_FLUSH_WR          = 0x1b,

        FW_OFLD_CONNECTION_WR   = 0x2f,

        FW_FLOWC_WR             = 0x0a,

        FW_OFLD_TX_DATA_WR      = 0x0b,

        FW_CMD_WR               = 0x10,

        FW_ETH_TX_PKT_VM_WR     = 0x11,

        FW_ETH_TX_PKTS_VM_WR    = 0x12,

        FW_RI_RES_WR            = 0x0c,

        FW_RI_RDMA_WRITE_WR     = 0x14,

        FW_RI_SEND_WR           = 0x15,

        FW_RI_RDMA_READ_WR      = 0x16,

        FW_RI_RECV_WR           = 0x17,

        FW_RI_BIND_MW_WR        = 0x18,

        FW_RI_FR_NSMR_WR        = 0x19,

        FW_RI_FR_NSMR_TPTE_WR   = 0x20,

        FW_RI_RDMA_WRITE_CMPL_WR =  0x21,

        FW_RI_INV_LSTAG_WR      = 0x1a,

        FW_RI_SEND_IMMEDIATE_WR = 0x15,

        FW_RI_ATOMIC_WR         = 0x16,

        FW_RI_WR                = 0x0d,

        FW_CHNET_IFCONF_WR      = 0x6b,

        FW_RDEV_WR              = 0x38,

        FW_FOISCSI_NODE_WR      = 0x60,

        FW_FOISCSI_CTRL_WR      = 0x6a,

        FW_FOISCSI_CHAP_WR      = 0x6c,

        FW_FCOE_ELS_CT_WR       = 0x30,

        FW_SCSI_WRITE_WR        = 0x31,

        FW_SCSI_READ_WR         = 0x32,

        FW_SCSI_CMD_WR          = 0x33,

        FW_SCSI_ABRT_CLS_WR     = 0x34,

        FW_SCSI_TGT_ACC_WR      = 0x35,

        FW_SCSI_TGT_XMIT_WR     = 0x36,

        FW_SCSI_TGT_RSP_WR      = 0x37,

        FW_POFCOE_TCB_WR        = 0x42,

        FW_POFCOE_ULPTX_WR      = 0x43,

        FW_ISCSI_TX_DATA_WR     = 0x45,

        FW_PTP_TX_PKT_WR        = 0x46,

        FW_TLSTX_DATA_WR        = 0x68,

        FW_TLS_TUNNEL_OFLD_WR   = 0x69,

        FW_CRYPTO_LOOKASIDE_WR  = 0x6d,

        FW_COISCSI_TGT_WR       = 0x70,

        FW_COISCSI_TGT_CONN_WR  = 0x71,

        FW_COISCSI_TGT_XMIT_WR  = 0x72,

        FW_COISCSI_STATS_WR      = 0x73,

        FW_ISNS_WR              = 0x75,

        FW_ISNS_XMIT_WR         = 0x76,

        FW_FILTER2_WR           = 0x77,

        FW_LASTC2E_WR           = 0x80

};


/*

 * Generic work request header flit0

 */

struct fw_wr_hdr {

        __be32 hi;

        __be32 lo;

};


/*      work request opcode (hi)

 */

#define S_FW_WR_OP              24

#define M_FW_WR_OP              0xff

#define V_FW_WR_OP(x)           ((x) << S_FW_WR_OP)

#define G_FW_WR_OP(x)           (((x) >> S_FW_WR_OP) & M_FW_WR_OP)


/*      atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER

 */

#define S_FW_WR_ATOMIC          23

#define M_FW_WR_ATOMIC          0x1

#define V_FW_WR_ATOMIC(x)       ((x) << S_FW_WR_ATOMIC)

#define G_FW_WR_ATOMIC(x)       \

    (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)

#define F_FW_WR_ATOMIC          V_FW_WR_ATOMIC(1U)


/*      flush flag (hi) - firmware flushes flushable work request buffered

 *                            in the flow context.

 */

#define S_FW_WR_FLUSH     22

#define M_FW_WR_FLUSH     0x1

#define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)

#define G_FW_WR_FLUSH(x)  \

    (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)

#define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)


/*      completion flag (hi) - firmware generates a cpl_fw6_ack

 */

#define S_FW_WR_COMPL     21

#define M_FW_WR_COMPL     0x1

#define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)

#define G_FW_WR_COMPL(x)  \

    (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)

#define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)


/*      work request immediate data lengh (hi)

 */

#define S_FW_WR_IMMDLEN 0

#define M_FW_WR_IMMDLEN 0xff

#define V_FW_WR_IMMDLEN(x)      ((x) << S_FW_WR_IMMDLEN)

#define G_FW_WR_IMMDLEN(x)      \

    (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)


/*      egress queue status update to associated ingress queue entry (lo)

 */

#define S_FW_WR_EQUIQ           31

#define M_FW_WR_EQUIQ           0x1

#define V_FW_WR_EQUIQ(x)        ((x) << S_FW_WR_EQUIQ)

#define G_FW_WR_EQUIQ(x)        (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)

#define F_FW_WR_EQUIQ           V_FW_WR_EQUIQ(1U)


/*      egress queue status update to egress queue status entry (lo)

 */

#define S_FW_WR_EQUEQ           30

#define M_FW_WR_EQUEQ           0x1

#define V_FW_WR_EQUEQ(x)        ((x) << S_FW_WR_EQUEQ)

#define G_FW_WR_EQUEQ(x)        (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)

#define F_FW_WR_EQUEQ           V_FW_WR_EQUEQ(1U)


/*      flow context identifier (lo)

 */

#define S_FW_WR_FLOWID          8

#define M_FW_WR_FLOWID          0xfffff

#define V_FW_WR_FLOWID(x)       ((x) << S_FW_WR_FLOWID)

#define G_FW_WR_FLOWID(x)       (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)


/*      length in units of 16-bytes (lo)

 */

#define S_FW_WR_LEN16           0

#define M_FW_WR_LEN16           0xff

#define V_FW_WR_LEN16(x)        ((x) << S_FW_WR_LEN16)

#define G_FW_WR_LEN16(x)        (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)


struct fw_frag_wr {

        __be32 op_to_fragoff16;

        __be32 flowid_len16;

        __be64 r4;

};


#define S_FW_FRAG_WR_EOF        15

#define M_FW_FRAG_WR_EOF        0x1

#define V_FW_FRAG_WR_EOF(x)     ((x) << S_FW_FRAG_WR_EOF)

#define G_FW_FRAG_WR_EOF(x)     (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)

#define F_FW_FRAG_WR_EOF        V_FW_FRAG_WR_EOF(1U)


#define S_FW_FRAG_WR_FRAGOFF16          8

#define M_FW_FRAG_WR_FRAGOFF16          0x7f

#define V_FW_FRAG_WR_FRAGOFF16(x)       ((x) << S_FW_FRAG_WR_FRAGOFF16)

#define G_FW_FRAG_WR_FRAGOFF16(x)       \

    (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)


/* valid filter configurations for compressed tuple

 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple

 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,

 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,

 * OV - Outer VLAN/VNIC_ID,

*/

#define HW_TPL_FR_MT_M_E_P_FC           0x3C3

#define HW_TPL_FR_MT_M_PR_T_FC          0x3B3

#define HW_TPL_FR_MT_M_IV_P_FC          0x38B

#define HW_TPL_FR_MT_M_OV_P_FC          0x387

#define HW_TPL_FR_MT_E_PR_T             0x370

#define HW_TPL_FR_MT_E_PR_P_FC          0X363

#define HW_TPL_FR_MT_E_T_P_FC           0X353

#define HW_TPL_FR_MT_PR_IV_P_FC         0X32B

#define HW_TPL_FR_MT_PR_OV_P_FC         0X327

#define HW_TPL_FR_MT_T_IV_P_FC          0X31B

#define HW_TPL_FR_MT_T_OV_P_FC          0X317

#define HW_TPL_FR_M_E_PR_FC             0X2E1

#define HW_TPL_FR_M_E_T_FC              0X2D1

#define HW_TPL_FR_M_PR_IV_FC            0X2A9

#define HW_TPL_FR_M_PR_OV_FC            0X2A5

#define HW_TPL_FR_M_T_IV_FC             0X299

#define HW_TPL_FR_M_T_OV_FC             0X295

#define HW_TPL_FR_E_PR_T_P              0X272

#define HW_TPL_FR_E_PR_T_FC             0X271

#define HW_TPL_FR_E_IV_FC               0X249

#define HW_TPL_FR_E_OV_FC               0X245

#define HW_TPL_FR_PR_T_IV_FC            0X239

#define HW_TPL_FR_PR_T_OV_FC            0X235

#define HW_TPL_FR_IV_OV_FC              0X20D

#define HW_TPL_MT_M_E_PR                0X1E0

#define HW_TPL_MT_M_E_T                 0X1D0

#define HW_TPL_MT_E_PR_T_FC             0X171

#define HW_TPL_MT_E_IV                  0X148

#define HW_TPL_MT_E_OV                  0X144

#define HW_TPL_MT_PR_T_IV               0X138

#define HW_TPL_MT_PR_T_OV               0X134

#define HW_TPL_M_E_PR_P                 0X0E2

#define HW_TPL_M_E_T_P                  0X0D2

#define HW_TPL_E_PR_T_P_FC              0X073

#define HW_TPL_E_IV_P                   0X04A

#define HW_TPL_E_OV_P                   0X046

#define HW_TPL_PR_T_IV_P                0X03A

#define HW_TPL_PR_T_OV_P                0X036


/* filter wr reply code in cookie in CPL_SET_TCB_RPL */

enum fw_filter_wr_cookie {

        FW_FILTER_WR_SUCCESS,

        FW_FILTER_WR_FLT_ADDED,

        FW_FILTER_WR_FLT_DELETED,

        FW_FILTER_WR_SMT_TBL_FULL,

        FW_FILTER_WR_EINVAL,

};


enum fw_filter_wr_nat_mode {

        FW_FILTER_WR_NATMODE_NONE = 0,

        FW_FILTER_WR_NATMODE_DIP ,

        FW_FILTER_WR_NATMODE_DIPDP,

        FW_FILTER_WR_NATMODE_DIPDPSIP,

        FW_FILTER_WR_NATMODE_DIPDPSP,

        FW_FILTER_WR_NATMODE_SIPSP,

        FW_FILTER_WR_NATMODE_DIPSIPSP,

        FW_FILTER_WR_NATMODE_FOURTUPLE,

};


struct fw_filter_wr {

        __be32 op_pkd;

        __be32 len16_pkd;

        __be64 r3;

        __be32 tid_to_iq;

        __be32 del_filter_to_l2tix;

        __be16 ethtype;

        __be16 ethtypem;

        __u8   frag_to_ovlan_vldm;

        __u8   smac_sel;

        __be16 rx_chan_rx_rpl_iq;

        __be32 maci_to_matchtypem;

        __u8   ptcl;

        __u8   ptclm;

        __u8   ttyp;

        __u8   ttypm;

        __be16 ivlan;

        __be16 ivlanm;

        __be16 ovlan;

        __be16 ovlanm;

        __u8   lip[16];

        __u8   lipm[16];

        __u8   fip[16];

        __u8   fipm[16];

        __be16 lp;

        __be16 lpm;

        __be16 fp;

        __be16 fpm;

        __be16 r7;

        __u8   sma[6];

};


struct fw_filter2_wr {

        __be32 op_pkd;

        __be32 len16_pkd;

        __be64 r3;

        __be32 tid_to_iq;

        __be32 del_filter_to_l2tix;

        __be16 ethtype;

        __be16 ethtypem;

        __u8   frag_to_ovlan_vldm;

        __u8   smac_sel;

        __be16 rx_chan_rx_rpl_iq;

        __be32 maci_to_matchtypem;

        __u8   ptcl;

        __u8   ptclm;

        __u8   ttyp;

        __u8   ttypm;

        __be16 ivlan;

        __be16 ivlanm;

        __be16 ovlan;

        __be16 ovlanm;

        __u8   lip[16];

        __u8   lipm[16];

        __u8   fip[16];

        __u8   fipm[16];

        __be16 lp;

        __be16 lpm;

        __be16 fp;

        __be16 fpm;

        __be16 r7;

        __u8   sma[6];

        __be16 r8;

        __u8   filter_type_swapmac;

        __u8   natmode_to_ulp_type;

        __be16 newlport;

        __be16 newfport;

        __u8   newlip[16];

        __u8   newfip[16];

        __be32 natseqcheck;

        __be32 r9;

        __be64 r10;

        __be64 r11;

        __be64 r12;

        __be64 r13;

};


#define S_FW_FILTER_WR_TID      12

#define M_FW_FILTER_WR_TID      0xfffff

#define V_FW_FILTER_WR_TID(x)   ((x) << S_FW_FILTER_WR_TID)

#define G_FW_FILTER_WR_TID(x)   \

    (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)


#define S_FW_FILTER_WR_RQTYPE           11

#define M_FW_FILTER_WR_RQTYPE           0x1

#define V_FW_FILTER_WR_RQTYPE(x)        ((x) << S_FW_FILTER_WR_RQTYPE)

#define G_FW_FILTER_WR_RQTYPE(x)        \

    (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)

#define F_FW_FILTER_WR_RQTYPE   V_FW_FILTER_WR_RQTYPE(1U)


#define S_FW_FILTER_WR_NOREPLY          10

#define M_FW_FILTER_WR_NOREPLY          0x1

#define V_FW_FILTER_WR_NOREPLY(x)       ((x) << S_FW_FILTER_WR_NOREPLY)

#define G_FW_FILTER_WR_NOREPLY(x)       \

    (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)

#define F_FW_FILTER_WR_NOREPLY  V_FW_FILTER_WR_NOREPLY(1U)


#define S_FW_FILTER_WR_IQ       0

#define M_FW_FILTER_WR_IQ       0x3ff

#define V_FW_FILTER_WR_IQ(x)    ((x) << S_FW_FILTER_WR_IQ)

#define G_FW_FILTER_WR_IQ(x)    \

    (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)


#define S_FW_FILTER_WR_DEL_FILTER       31

#define M_FW_FILTER_WR_DEL_FILTER       0x1

#define V_FW_FILTER_WR_DEL_FILTER(x)    ((x) << S_FW_FILTER_WR_DEL_FILTER)

#define G_FW_FILTER_WR_DEL_FILTER(x)    \

    (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)

#define F_FW_FILTER_WR_DEL_FILTER       V_FW_FILTER_WR_DEL_FILTER(1U)


#define S_FW_FILTER2_WR_DROP_ENCAP      30

#define M_FW_FILTER2_WR_DROP_ENCAP      0x1

#define V_FW_FILTER2_WR_DROP_ENCAP(x)   ((x) << S_FW_FILTER2_WR_DROP_ENCAP)

#define G_FW_FILTER2_WR_DROP_ENCAP(x)   \

    (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)

#define F_FW_FILTER2_WR_DROP_ENCAP      V_FW_FILTER2_WR_DROP_ENCAP(1U)


#define S_FW_FILTER2_WR_TX_LOOP         29

#define M_FW_FILTER2_WR_TX_LOOP         0x1

#define V_FW_FILTER2_WR_TX_LOOP(x)      ((x) << S_FW_FILTER2_WR_TX_LOOP)

#define G_FW_FILTER2_WR_TX_LOOP(x)      \

            (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)

#define F_FW_FILTER2_WR_TX_LOOP         V_FW_FILTER2_WR_TX_LOOP(1U)


#define S_FW_FILTER_WR_RPTTID           25

#define M_FW_FILTER_WR_RPTTID           0x1

#define V_FW_FILTER_WR_RPTTID(x)        ((x) << S_FW_FILTER_WR_RPTTID)

#define G_FW_FILTER_WR_RPTTID(x)        \

    (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)

#define F_FW_FILTER_WR_RPTTID   V_FW_FILTER_WR_RPTTID(1U)


#define S_FW_FILTER_WR_DROP     24

#define M_FW_FILTER_WR_DROP     0x1

#define V_FW_FILTER_WR_DROP(x)  ((x) << S_FW_FILTER_WR_DROP)

#define G_FW_FILTER_WR_DROP(x)  \

    (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)

#define F_FW_FILTER_WR_DROP     V_FW_FILTER_WR_DROP(1U)


#define S_FW_FILTER_WR_DIRSTEER         23

#define M_FW_FILTER_WR_DIRSTEER         0x1

#define V_FW_FILTER_WR_DIRSTEER(x)      ((x) << S_FW_FILTER_WR_DIRSTEER)

#define G_FW_FILTER_WR_DIRSTEER(x)      \

    (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)

#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)


#define S_FW_FILTER_WR_MASKHASH         22

#define M_FW_FILTER_WR_MASKHASH         0x1

#define V_FW_FILTER_WR_MASKHASH(x)      ((x) << S_FW_FILTER_WR_MASKHASH)

#define G_FW_FILTER_WR_MASKHASH(x)      \

    (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)

#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)


#define S_FW_FILTER_WR_DIRSTEERHASH     21

#define M_FW_FILTER_WR_DIRSTEERHASH     0x1

#define V_FW_FILTER_WR_DIRSTEERHASH(x)  ((x) << S_FW_FILTER_WR_DIRSTEERHASH)

#define G_FW_FILTER_WR_DIRSTEERHASH(x)  \

    (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)

#define F_FW_FILTER_WR_DIRSTEERHASH     V_FW_FILTER_WR_DIRSTEERHASH(1U)


#define S_FW_FILTER_WR_LPBK     20

#define M_FW_FILTER_WR_LPBK     0x1

#define V_FW_FILTER_WR_LPBK(x)  ((x) << S_FW_FILTER_WR_LPBK)

#define G_FW_FILTER_WR_LPBK(x)  \

    (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)

#define F_FW_FILTER_WR_LPBK     V_FW_FILTER_WR_LPBK(1U)


#define S_FW_FILTER_WR_DMAC     19

#define M_FW_FILTER_WR_DMAC     0x1

#define V_FW_FILTER_WR_DMAC(x)  ((x) << S_FW_FILTER_WR_DMAC)

#define G_FW_FILTER_WR_DMAC(x)  \

    (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)

#define F_FW_FILTER_WR_DMAC     V_FW_FILTER_WR_DMAC(1U)


#define S_FW_FILTER_WR_SMAC     18

#define M_FW_FILTER_WR_SMAC     0x1

#define V_FW_FILTER_WR_SMAC(x)  ((x) << S_FW_FILTER_WR_SMAC)

#define G_FW_FILTER_WR_SMAC(x)  \

    (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)

#define F_FW_FILTER_WR_SMAC     V_FW_FILTER_WR_SMAC(1U)


#define S_FW_FILTER_WR_INSVLAN          17

#define M_FW_FILTER_WR_INSVLAN          0x1

#define V_FW_FILTER_WR_INSVLAN(x)       ((x) << S_FW_FILTER_WR_INSVLAN)

#define G_FW_FILTER_WR_INSVLAN(x)       \

    (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)

#define F_FW_FILTER_WR_INSVLAN  V_FW_FILTER_WR_INSVLAN(1U)


#define S_FW_FILTER_WR_RMVLAN           16

#define M_FW_FILTER_WR_RMVLAN           0x1

#define V_FW_FILTER_WR_RMVLAN(x)        ((x) << S_FW_FILTER_WR_RMVLAN)

#define G_FW_FILTER_WR_RMVLAN(x)        \

    (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)

#define F_FW_FILTER_WR_RMVLAN   V_FW_FILTER_WR_RMVLAN(1U)


#define S_FW_FILTER_WR_HITCNTS          15

#define M_FW_FILTER_WR_HITCNTS          0x1

#define V_FW_FILTER_WR_HITCNTS(x)       ((x) << S_FW_FILTER_WR_HITCNTS)

#define G_FW_FILTER_WR_HITCNTS(x)       \

    (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)

#define F_FW_FILTER_WR_HITCNTS  V_FW_FILTER_WR_HITCNTS(1U)


#define S_FW_FILTER_WR_TXCHAN           13

#define M_FW_FILTER_WR_TXCHAN           0x3

#define V_FW_FILTER_WR_TXCHAN(x)        ((x) << S_FW_FILTER_WR_TXCHAN)

#define G_FW_FILTER_WR_TXCHAN(x)        \

    (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)


#define S_FW_FILTER_WR_PRIO     12

#define M_FW_FILTER_WR_PRIO     0x1

#define V_FW_FILTER_WR_PRIO(x)  ((x) << S_FW_FILTER_WR_PRIO)

#define G_FW_FILTER_WR_PRIO(x)  \

    (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)

#define F_FW_FILTER_WR_PRIO     V_FW_FILTER_WR_PRIO(1U)


#define S_FW_FILTER_WR_L2TIX    0

#define M_FW_FILTER_WR_L2TIX    0xfff

#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)

#define G_FW_FILTER_WR_L2TIX(x) \

    (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)


#define S_FW_FILTER_WR_FRAG     7

#define M_FW_FILTER_WR_FRAG     0x1

#define V_FW_FILTER_WR_FRAG(x)  ((x) << S_FW_FILTER_WR_FRAG)

#define G_FW_FILTER_WR_FRAG(x)  \

    (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)

#define F_FW_FILTER_WR_FRAG     V_FW_FILTER_WR_FRAG(1U)


#define S_FW_FILTER_WR_FRAGM    6

#define M_FW_FILTER_WR_FRAGM    0x1

#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)

#define G_FW_FILTER_WR_FRAGM(x) \

    (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)

#define F_FW_FILTER_WR_FRAGM    V_FW_FILTER_WR_FRAGM(1U)


#define S_FW_FILTER_WR_IVLAN_VLD        5

#define M_FW_FILTER_WR_IVLAN_VLD        0x1

#define V_FW_FILTER_WR_IVLAN_VLD(x)     ((x) << S_FW_FILTER_WR_IVLAN_VLD)

#define G_FW_FILTER_WR_IVLAN_VLD(x)     \

    (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)

#define F_FW_FILTER_WR_IVLAN_VLD        V_FW_FILTER_WR_IVLAN_VLD(1U)


#define S_FW_FILTER_WR_OVLAN_VLD        4

#define M_FW_FILTER_WR_OVLAN_VLD        0x1

#define V_FW_FILTER_WR_OVLAN_VLD(x)     ((x) << S_FW_FILTER_WR_OVLAN_VLD)

#define G_FW_FILTER_WR_OVLAN_VLD(x)     \

    (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)

#define F_FW_FILTER_WR_OVLAN_VLD        V_FW_FILTER_WR_OVLAN_VLD(1U)


#define S_FW_FILTER_WR_IVLAN_VLDM       3

#define M_FW_FILTER_WR_IVLAN_VLDM       0x1

#define V_FW_FILTER_WR_IVLAN_VLDM(x)    ((x) << S_FW_FILTER_WR_IVLAN_VLDM)

#define G_FW_FILTER_WR_IVLAN_VLDM(x)    \

    (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)

#define F_FW_FILTER_WR_IVLAN_VLDM       V_FW_FILTER_WR_IVLAN_VLDM(1U)


#define S_FW_FILTER_WR_OVLAN_VLDM       2

#define M_FW_FILTER_WR_OVLAN_VLDM       0x1

#define V_FW_FILTER_WR_OVLAN_VLDM(x)    ((x) << S_FW_FILTER_WR_OVLAN_VLDM)

#define G_FW_FILTER_WR_OVLAN_VLDM(x)    \

    (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)

#define F_FW_FILTER_WR_OVLAN_VLDM       V_FW_FILTER_WR_OVLAN_VLDM(1U)


#define S_FW_FILTER_WR_RX_CHAN          15

#define M_FW_FILTER_WR_RX_CHAN          0x1

#define V_FW_FILTER_WR_RX_CHAN(x)       ((x) << S_FW_FILTER_WR_RX_CHAN)

#define G_FW_FILTER_WR_RX_CHAN(x)       \

    (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)

#define F_FW_FILTER_WR_RX_CHAN  V_FW_FILTER_WR_RX_CHAN(1U)


#define S_FW_FILTER_WR_RX_RPL_IQ        0

#define M_FW_FILTER_WR_RX_RPL_IQ        0x3ff

#define V_FW_FILTER_WR_RX_RPL_IQ(x)     ((x) << S_FW_FILTER_WR_RX_RPL_IQ)

#define G_FW_FILTER_WR_RX_RPL_IQ(x)     \

    (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)


#define S_FW_FILTER2_WR_FILTER_TYPE     1

#define M_FW_FILTER2_WR_FILTER_TYPE     0x1

#define V_FW_FILTER2_WR_FILTER_TYPE(x)  ((x) << S_FW_FILTER2_WR_FILTER_TYPE)

#define G_FW_FILTER2_WR_FILTER_TYPE(x)  \

    (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)

#define F_FW_FILTER2_WR_FILTER_TYPE     V_FW_FILTER2_WR_FILTER_TYPE(1U)


#define S_FW_FILTER2_WR_SWAPMAC         0

#define M_FW_FILTER2_WR_SWAPMAC         0x1

#define V_FW_FILTER2_WR_SWAPMAC(x)      ((x) << S_FW_FILTER2_WR_SWAPMAC)

#define G_FW_FILTER2_WR_SWAPMAC(x)      \

    (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)

#define F_FW_FILTER2_WR_SWAPMAC         V_FW_FILTER2_WR_SWAPMAC(1U)


#define S_FW_FILTER2_WR_NATMODE         5

#define M_FW_FILTER2_WR_NATMODE         0x7

#define V_FW_FILTER2_WR_NATMODE(x)      ((x) << S_FW_FILTER2_WR_NATMODE)

#define G_FW_FILTER2_WR_NATMODE(x)      \

    (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)


#define S_FW_FILTER2_WR_NATFLAGCHECK    4

#define M_FW_FILTER2_WR_NATFLAGCHECK    0x1

#define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK)

#define G_FW_FILTER2_WR_NATFLAGCHECK(x) \

    (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)

#define F_FW_FILTER2_WR_NATFLAGCHECK    V_FW_FILTER2_WR_NATFLAGCHECK(1U)


#define S_FW_FILTER2_WR_ULP_TYPE        0

#define M_FW_FILTER2_WR_ULP_TYPE        0xf

#define V_FW_FILTER2_WR_ULP_TYPE(x)     ((x) << S_FW_FILTER2_WR_ULP_TYPE)

#define G_FW_FILTER2_WR_ULP_TYPE(x)     \

    (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)


#define S_FW_FILTER_WR_MACI     23

#define M_FW_FILTER_WR_MACI     0x1ff

#define V_FW_FILTER_WR_MACI(x)  ((x) << S_FW_FILTER_WR_MACI)

#define G_FW_FILTER_WR_MACI(x)  \

    (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)


#define S_FW_FILTER_WR_MACIM    14

#define M_FW_FILTER_WR_MACIM    0x1ff

#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)

#define G_FW_FILTER_WR_MACIM(x) \

    (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)


#define S_FW_FILTER_WR_FCOE     13

#define M_FW_FILTER_WR_FCOE     0x1

#define V_FW_FILTER_WR_FCOE(x)  ((x) << S_FW_FILTER_WR_FCOE)

#define G_FW_FILTER_WR_FCOE(x)  \

    (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)

#define F_FW_FILTER_WR_FCOE     V_FW_FILTER_WR_FCOE(1U)


#define S_FW_FILTER_WR_FCOEM    12

#define M_FW_FILTER_WR_FCOEM    0x1

#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)

#define G_FW_FILTER_WR_FCOEM(x) \

    (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)

#define F_FW_FILTER_WR_FCOEM    V_FW_FILTER_WR_FCOEM(1U)


#define S_FW_FILTER_WR_PORT     9

#define M_FW_FILTER_WR_PORT     0x7

#define V_FW_FILTER_WR_PORT(x)  ((x) << S_FW_FILTER_WR_PORT)

#define G_FW_FILTER_WR_PORT(x)  \

    (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)


#define S_FW_FILTER_WR_PORTM    6

#define M_FW_FILTER_WR_PORTM    0x7

#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)

#define G_FW_FILTER_WR_PORTM(x) \

    (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)


#define S_FW_FILTER_WR_MATCHTYPE        3

#define M_FW_FILTER_WR_MATCHTYPE        0x7

#define V_FW_FILTER_WR_MATCHTYPE(x)     ((x) << S_FW_FILTER_WR_MATCHTYPE)

#define G_FW_FILTER_WR_MATCHTYPE(x)     \

    (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)


#define S_FW_FILTER_WR_MATCHTYPEM       0

#define M_FW_FILTER_WR_MATCHTYPEM       0x7

#define V_FW_FILTER_WR_MATCHTYPEM(x)    ((x) << S_FW_FILTER_WR_MATCHTYPEM)

#define G_FW_FILTER_WR_MATCHTYPEM(x)    \

    (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)


struct fw_ulptx_wr {

        __be32 op_to_compl;

        __be32 flowid_len16;

        __u64  cookie;

};


/*      flag for packet type - control packet (0), data packet (1)

 */

#define S_FW_ULPTX_WR_DATA      28

#define M_FW_ULPTX_WR_DATA      0x1

#define V_FW_ULPTX_WR_DATA(x)   ((x) << S_FW_ULPTX_WR_DATA)

#define G_FW_ULPTX_WR_DATA(x)   \

    (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)

#define F_FW_ULPTX_WR_DATA      V_FW_ULPTX_WR_DATA(1U)


struct fw_tp_wr {

        __be32 op_to_immdlen;

        __be32 flowid_len16;

        __u64  cookie;

};


struct fw_eth_tx_pkt_wr {

        __be32 op_immdlen;

        __be32 equiq_to_len16;

        __be64 r3;

};


#define S_FW_ETH_TX_PKT_WR_IMMDLEN      0

#define M_FW_ETH_TX_PKT_WR_IMMDLEN      0x1ff

#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)   ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)

#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)   \

    (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)


struct fw_eth_tx_pkt2_wr {

        __be32 op_immdlen;

        __be32 equiq_to_len16;

        __be32 r3;

        __be32 L4ChkDisable_to_IpHdrLen;

};


#define S_FW_ETH_TX_PKT2_WR_IMMDLEN     0

#define M_FW_ETH_TX_PKT2_WR_IMMDLEN     0x1ff

#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)  ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)

#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)  \

    (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)


#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE        31

#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE        0x1

#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)     \

    ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)

#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)     \

    (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \

     M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)

#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE        \

    V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)


#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE        30

#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE        0x1

#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)     \

    ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)

#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)     \

    (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \

     M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)

#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE        \

    V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)


#define S_FW_ETH_TX_PKT2_WR_IVLAN       28

#define M_FW_ETH_TX_PKT2_WR_IVLAN       0x1

#define V_FW_ETH_TX_PKT2_WR_IVLAN(x)    ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)

#define G_FW_ETH_TX_PKT2_WR_IVLAN(x)    \

    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)

#define F_FW_ETH_TX_PKT2_WR_IVLAN       V_FW_ETH_TX_PKT2_WR_IVLAN(1U)


#define S_FW_ETH_TX_PKT2_WR_IVLANTAG    12

#define M_FW_ETH_TX_PKT2_WR_IVLANTAG    0xffff

#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)

#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \

    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)


#define S_FW_ETH_TX_PKT2_WR_CHKTYPE     8

#define M_FW_ETH_TX_PKT2_WR_CHKTYPE     0xf

#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)  ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)

#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)  \

    (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)


#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN    0

#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN    0xff

#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)

#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \

    (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)


struct fw_eth_tx_pkts_wr {

        __be32 op_pkd;

        __be32 equiq_to_len16;

        __be32 r3;

        __be16 plen;

        __u8   npkt;

        __u8   type;

};


#define S_FW_PTP_TX_PKT_WR_IMMDLEN      0

#define M_FW_PTP_TX_PKT_WR_IMMDLEN      0x1ff

#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x)   ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)

#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x)   \

    (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)


struct fw_eth_tx_pkt_ptp_wr {

        __be32 op_immdlen;

        __be32 equiq_to_len16;

        __be64 r3;

};


enum fw_eth_tx_eo_type {

        FW_ETH_TX_EO_TYPE_UDPSEG,

        FW_ETH_TX_EO_TYPE_TCPSEG,

        FW_ETH_TX_EO_TYPE_NVGRESEG,

        FW_ETH_TX_EO_TYPE_VXLANSEG,

        FW_ETH_TX_EO_TYPE_GENEVESEG,

};


struct fw_eth_tx_eo_wr {

        __be32 op_immdlen;

        __be32 equiq_to_len16;

        __be64 r3;

        union fw_eth_tx_eo {

                struct fw_eth_tx_eo_udpseg {

                        __u8   type;

                        __u8   ethlen;

                        __be16 iplen;

                        __u8   udplen;

                        __u8   rtplen;

                        __be16 r4;

                        __be16 mss;

                        __be16 schedpktsize;

                        __be32 plen;

                } udpseg;

                struct fw_eth_tx_eo_tcpseg {

                        __u8   type;

                        __u8   ethlen;

                        __be16 iplen;

                        __u8   tcplen;

                        __u8   tsclk_tsoff;

                        __be16 r4;

                        __be16 mss;

                        __be16 r5;

                        __be32 plen;

                } tcpseg;

                struct fw_eth_tx_eo_nvgreseg {

                        __u8   type;

                        __u8   iphdroffout;

                        __be16 grehdroff;

                        __be16 iphdroffin;

                        __be16 tcphdroffin;

                        __be16 mss;

                        __be16 r4;

                        __be32 plen;

                } nvgreseg;

                struct fw_eth_tx_eo_vxlanseg {

                        __u8   type;

                        __u8   iphdroffout;

                        __be16 vxlanhdroff;

                        __be16 iphdroffin;

                        __be16 tcphdroffin;

                        __be16 mss;

                        __be16 r4;

                        __be32 plen;


                } vxlanseg;

                struct fw_eth_tx_eo_geneveseg {

                        __u8   type;

                        __u8   iphdroffout;

                        __be16 genevehdroff;

                        __be16 iphdroffin;

                        __be16 tcphdroffin;

                        __be16 mss;

                        __be16 r4;

                        __be32 plen;

                } geneveseg;

        } u;

};


#define S_FW_ETH_TX_EO_WR_IMMDLEN       0

#define M_FW_ETH_TX_EO_WR_IMMDLEN       0x1ff

#define V_FW_ETH_TX_EO_WR_IMMDLEN(x)    ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)

#define G_FW_ETH_TX_EO_WR_IMMDLEN(x)    \

    (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)


#define S_FW_ETH_TX_EO_WR_TSCLK         6

#define M_FW_ETH_TX_EO_WR_TSCLK         0x3

#define V_FW_ETH_TX_EO_WR_TSCLK(x)      ((x) << S_FW_ETH_TX_EO_WR_TSCLK)

#define G_FW_ETH_TX_EO_WR_TSCLK(x)      \

    (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)


#define S_FW_ETH_TX_EO_WR_TSOFF         0

#define M_FW_ETH_TX_EO_WR_TSOFF         0x3f

#define V_FW_ETH_TX_EO_WR_TSOFF(x)      ((x) << S_FW_ETH_TX_EO_WR_TSOFF)

#define G_FW_ETH_TX_EO_WR_TSOFF(x)      \

    (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)


struct fw_eq_flush_wr {

        __u8   opcode;

        __u8   r1[3];

        __be32 equiq_to_len16;

        __be64 r3;

};


struct fw_ofld_connection_wr {

        __be32 op_compl;

        __be32 len16_pkd;

        __u64  cookie;

        __be64 r2;

        __be64 r3;

        struct fw_ofld_connection_le {

                __be32 version_cpl;

                __be32 filter;

                __be32 r1;

                __be16 lport;

                __be16 pport;

                union fw_ofld_connection_leip {

                        struct fw_ofld_connection_le_ipv4 {

                                __be32 pip;

                                __be32 lip;

                                __be64 r0;

                                __be64 r1;

                                __be64 r2;

                        } ipv4;

                        struct fw_ofld_connection_le_ipv6 {

                                __be64 pip_hi;

                                __be64 pip_lo;

                                __be64 lip_hi;

                                __be64 lip_lo;

                        } ipv6;

                } u;

        } le;

        struct fw_ofld_connection_tcb {

                __be32 t_state_to_astid;

                __be16 cplrxdataack_cplpassacceptrpl;

                __be16 rcv_adv;

                __be32 rcv_nxt;

                __be32 tx_max;

                __be64 opt0;

                __be32 opt2;

                __be32 r1;

                __be64 r2;

                __be64 r3;

        } tcb;

};


#define S_FW_OFLD_CONNECTION_WR_VERSION         31

#define M_FW_OFLD_CONNECTION_WR_VERSION         0x1

#define V_FW_OFLD_CONNECTION_WR_VERSION(x)      \

    ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)

#define G_FW_OFLD_CONNECTION_WR_VERSION(x)      \

    (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \

     M_FW_OFLD_CONNECTION_WR_VERSION)

#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U)


#define S_FW_OFLD_CONNECTION_WR_CPL     30

#define M_FW_OFLD_CONNECTION_WR_CPL     0x1

#define V_FW_OFLD_CONNECTION_WR_CPL(x)  ((x) << S_FW_OFLD_CONNECTION_WR_CPL)

#define G_FW_OFLD_CONNECTION_WR_CPL(x)  \

    (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)

#define F_FW_OFLD_CONNECTION_WR_CPL     V_FW_OFLD_CONNECTION_WR_CPL(1U)


#define S_FW_OFLD_CONNECTION_WR_T_STATE         28

#define M_FW_OFLD_CONNECTION_WR_T_STATE         0xf

#define V_FW_OFLD_CONNECTION_WR_T_STATE(x)      \

    ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)

#define G_FW_OFLD_CONNECTION_WR_T_STATE(x)      \

    (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \

     M_FW_OFLD_CONNECTION_WR_T_STATE)


#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE       24

#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE       0xf

#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)    \

    ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)

#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)    \

    (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \

     M_FW_OFLD_CONNECTION_WR_RCV_SCALE)


#define S_FW_OFLD_CONNECTION_WR_ASTID           0

#define M_FW_OFLD_CONNECTION_WR_ASTID           0xffffff

#define V_FW_OFLD_CONNECTION_WR_ASTID(x)        \

    ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)

#define G_FW_OFLD_CONNECTION_WR_ASTID(x)        \

    (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)


#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK    15

#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK    0x1

#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \

    ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)

#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \

    (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \

     M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)

#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK    \

    V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)


#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL        14

#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL        0x1

#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)     \

    ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)

#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)     \

    (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \

     M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)

#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL        \

    V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)


enum fw_flowc_mnem_tcpstate {

        FW_FLOWC_MNEM_TCPSTATE_CLOSED   = 0, /* illegal */

        FW_FLOWC_MNEM_TCPSTATE_LISTEN   = 1, /* illegal */

        FW_FLOWC_MNEM_TCPSTATE_SYNSENT  = 2, /* illegal */

        FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */

        FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */

        FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */

        FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and

                                              * will resend FIN - equiv ESTAB

                                              */

        FW_FLOWC_MNEM_TCPSTATE_CLOSING  = 7, /* haven't gotten ACK for FIN and

                                              * will resend FIN but have

                                              * received FIN

                                              */

        FW_FLOWC_MNEM_TCPSTATE_LASTACK  = 8, /* haven't gotten ACK for FIN and

                                              * will resend FIN but have

                                              * received FIN

                                              */

        FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,

                                              * waiting for FIN

                                              */

        FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */

};


enum fw_flowc_mnem_eostate {

        FW_FLOWC_MNEM_EOSTATE_CLOSED    = 0, /* illegal */

        FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */

        FW_FLOWC_MNEM_EOSTATE_CLOSING   = 2, /* graceful close, after sending

                                              * outstanding payload

                                              */

        FW_FLOWC_MNEM_EOSTATE_ABORTING  = 3, /* immediate close, after

                                              * discarding outstanding payload

                                              */

};


enum fw_flowc_mnem {

        FW_FLOWC_MNEM_PFNVFN            = 0, /* PFN [15:8] VFN [7:0] */

        FW_FLOWC_MNEM_CH                = 1,

        FW_FLOWC_MNEM_PORT              = 2,

        FW_FLOWC_MNEM_IQID              = 3,

        FW_FLOWC_MNEM_SNDNXT            = 4,

        FW_FLOWC_MNEM_RCVNXT            = 5,

        FW_FLOWC_MNEM_SNDBUF            = 6,

        FW_FLOWC_MNEM_MSS               = 7,

        FW_FLOWC_MNEM_TXDATAPLEN_MAX    = 8,

        FW_FLOWC_MNEM_TCPSTATE          = 9,

        FW_FLOWC_MNEM_EOSTATE           = 10,

        FW_FLOWC_MNEM_SCHEDCLASS        = 11,

        FW_FLOWC_MNEM_DCBPRIO           = 12,

        FW_FLOWC_MNEM_SND_SCALE         = 13,

        FW_FLOWC_MNEM_RCV_SCALE         = 14,

        FW_FLOWC_MNEM_ULP_MODE          = 15,

        FW_FLOWC_MNEM_MAX               = 16,

};


struct fw_flowc_mnemval {

        __u8   mnemonic;

        __u8   r4[3];

        __be32 val;

};


struct fw_flowc_wr {

        __be32 op_to_nparams;

        __be32 flowid_len16;

#ifndef C99_NOT_SUPPORTED

        struct fw_flowc_mnemval mnemval[0];

#endif

};


#define S_FW_FLOWC_WR_NPARAMS           0

#define M_FW_FLOWC_WR_NPARAMS           0xff

#define V_FW_FLOWC_WR_NPARAMS(x)        ((x) << S_FW_FLOWC_WR_NPARAMS)

#define G_FW_FLOWC_WR_NPARAMS(x)        \

    (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)


struct fw_ofld_tx_data_wr {

        __be32 op_to_immdlen;

        __be32 flowid_len16;

        __be32 plen;

        __be32 lsodisable_to_flags;

};


#define S_FW_OFLD_TX_DATA_WR_LSODISABLE         31

#define M_FW_OFLD_TX_DATA_WR_LSODISABLE         0x1

#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x)      \

    ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)

#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x)      \

    (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \

     M_FW_OFLD_TX_DATA_WR_LSODISABLE)

#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)


#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD           30

#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD           0x1

#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)        \

    ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)

#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)        \

    (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)

#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD   V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)


#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE      29

#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE      0x1

#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)   \

    ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)

#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)   \

    (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \

     M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)

#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE      \

    V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)


#define S_FW_OFLD_TX_DATA_WR_FLAGS      0

#define M_FW_OFLD_TX_DATA_WR_FLAGS      0xfffffff

#define V_FW_OFLD_TX_DATA_WR_FLAGS(x)   ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)

#define G_FW_OFLD_TX_DATA_WR_FLAGS(x)   \

    (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)


/* Use fw_ofld_tx_data_wr structure */

#define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI          10

#define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI          0x3fffff

#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)       \

    ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)

#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)       \

    (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)


#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO    9

#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO    0x1

#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \

    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)

#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \

    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \

     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)

#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO    \

    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)


#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI     8

#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI     0x1

#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)  \

    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)

#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)  \

    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \

     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)

#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI     \

    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)


#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC           7

#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC           0x1

#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)        \

    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)

#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)        \

    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \

     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)

#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC   \

    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)


#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC           6

#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC           0x1

#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)        \

    ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)

#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)        \

    (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \

     M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)

#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC   \

    V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)


#define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO          0

#define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO          0x3f

#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)       \

    ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)

#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)       \

    (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)


struct fw_cmd_wr {

        __be32 op_dma;

        __be32 len16_pkd;

        __be64 cookie_daddr;

};


#define S_FW_CMD_WR_DMA         17

#define M_FW_CMD_WR_DMA         0x1

#define V_FW_CMD_WR_DMA(x)      ((x) << S_FW_CMD_WR_DMA)

#define G_FW_CMD_WR_DMA(x)      (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)

#define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U)


struct fw_eth_tx_pkt_vm_wr {

        __be32 op_immdlen;

        __be32 equiq_to_len16;

        __be32 r3[2];

        __u8   ethmacdst[6];

        __u8   ethmacsrc[6];

        __be16 ethtype;

        __be16 vlantci;

};


struct fw_eth_tx_pkts_vm_wr {

        __be32 op_pkd;

        __be32 equiq_to_len16;

        __be32 r3;

        __be16 plen;

        __u8   npkt;

        __u8   r4;

        __u8   ethmacdst[6];

        __u8   ethmacsrc[6];

        __be16 ethtype;

        __be16 vlantci;

};


/******************************************************************************

 *   R I   W O R K   R E Q U E S T s

 **************************************/


enum fw_ri_wr_opcode {

        FW_RI_RDMA_WRITE                = 0x0,  /* IETF RDMAP v1.0 ... */

        FW_RI_READ_REQ                  = 0x1,

        FW_RI_READ_RESP                 = 0x2,

        FW_RI_SEND                      = 0x3,

        FW_RI_SEND_WITH_INV             = 0x4,

        FW_RI_SEND_WITH_SE              = 0x5,

        FW_RI_SEND_WITH_SE_INV          = 0x6,

        FW_RI_TERMINATE                 = 0x7,

        FW_RI_RDMA_INIT                 = 0x8,  /* CHELSIO RI specific ... */

        FW_RI_BIND_MW                   = 0x9,

        FW_RI_FAST_REGISTER             = 0xa,

        FW_RI_LOCAL_INV                 = 0xb,

        FW_RI_QP_MODIFY                 = 0xc,

        FW_RI_BYPASS                    = 0xd,

        FW_RI_RECEIVE                   = 0xe,

#if 0

        FW_RI_SEND_IMMEDIATE            = 0x8,

        FW_RI_SEND_IMMEDIATE_WITH_SE    = 0x9,

        FW_RI_ATOMIC_REQUEST            = 0xa,

        FW_RI_ATOMIC_RESPONSE           = 0xb,


        FW_RI_BIND_MW                   = 0xc, /* CHELSIO RI specific ... */

        FW_RI_FAST_REGISTER             = 0xd,

        FW_RI_LOCAL_INV                 = 0xe,

#endif

        FW_RI_SGE_EC_CR_RETURN          = 0xf,

        FW_RI_WRITE_IMMEDIATE   = FW_RI_RDMA_INIT,

};


enum fw_ri_wr_flags {

        FW_RI_COMPLETION_FLAG           = 0x01,

        FW_RI_NOTIFICATION_FLAG         = 0x02,

        FW_RI_SOLICITED_EVENT_FLAG      = 0x04,

        FW_RI_READ_FENCE_FLAG           = 0x08,

        FW_RI_LOCAL_FENCE_FLAG          = 0x10,

        FW_RI_RDMA_READ_INVALIDATE      = 0x20,

        FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40

};


enum fw_ri_mpa_attrs {

        FW_RI_MPA_RX_MARKER_ENABLE      = 0x01,

        FW_RI_MPA_TX_MARKER_ENABLE      = 0x02,

        FW_RI_MPA_CRC_ENABLE            = 0x04,

        FW_RI_MPA_IETF_ENABLE           = 0x08

};


enum fw_ri_qp_caps {

        FW_RI_QP_RDMA_READ_ENABLE       = 0x01,

        FW_RI_QP_RDMA_WRITE_ENABLE      = 0x02,

        FW_RI_QP_BIND_ENABLE            = 0x04,

        FW_RI_QP_FAST_REGISTER_ENABLE   = 0x08,

        FW_RI_QP_STAG0_ENABLE           = 0x10,

        FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,

};


enum fw_ri_addr_type {

        FW_RI_ZERO_BASED_TO             = 0x00,

        FW_RI_VA_BASED_TO               = 0x01

};


enum fw_ri_mem_perms {

        FW_RI_MEM_ACCESS_REM_WRITE      = 0x01,

        FW_RI_MEM_ACCESS_REM_READ       = 0x02,

        FW_RI_MEM_ACCESS_REM            = 0x03,

        FW_RI_MEM_ACCESS_LOCAL_WRITE    = 0x04,

        FW_RI_MEM_ACCESS_LOCAL_READ     = 0x08,

        FW_RI_MEM_ACCESS_LOCAL          = 0x0C

};


enum fw_ri_stag_type {

        FW_RI_STAG_NSMR                 = 0x00,

        FW_RI_STAG_SMR                  = 0x01,

        FW_RI_STAG_MW                   = 0x02,

        FW_RI_STAG_MW_RELAXED           = 0x03

};


enum fw_ri_data_op {

        FW_RI_DATA_IMMD                 = 0x81,

        FW_RI_DATA_DSGL                 = 0x82,

        FW_RI_DATA_ISGL                 = 0x83

};


enum fw_ri_sgl_depth {

        FW_RI_SGL_DEPTH_MAX_SQ          = 16,

        FW_RI_SGL_DEPTH_MAX_RQ          = 4

};


enum fw_ri_cqe_err {

        FW_RI_CQE_ERR_SUCCESS           = 0x00, /* success, no error detected */

        FW_RI_CQE_ERR_STAG              = 0x01, /* STAG invalid */

        FW_RI_CQE_ERR_PDID              = 0x02, /* PDID mismatch */

        FW_RI_CQE_ERR_QPID              = 0x03, /* QPID mismatch */

        FW_RI_CQE_ERR_ACCESS            = 0x04, /* Invalid access right */

        FW_RI_CQE_ERR_WRAP              = 0x05, /* Wrap error */

        FW_RI_CQE_ERR_BOUND             = 0x06, /* base and bounds violation */

        FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */

        FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */

        FW_RI_CQE_ERR_ECC               = 0x09, /* ECC error detected */

        FW_RI_CQE_ERR_ECC_PSTAG         = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */

        FW_RI_CQE_ERR_PBL_ADDR_BOUND    = 0x0B, /* pbl address out of bound : software error */

        FW_RI_CQE_ERR_CRC               = 0x10, /* CRC error */

        FW_RI_CQE_ERR_MARKER            = 0x11, /* Marker error */

        FW_RI_CQE_ERR_PDU_LEN_ERR       = 0x12, /* invalid PDU length */

        FW_RI_CQE_ERR_OUT_OF_RQE        = 0x13, /* out of RQE */

        FW_RI_CQE_ERR_DDP_VERSION       = 0x14, /* wrong DDP version */

        FW_RI_CQE_ERR_RDMA_VERSION      = 0x15, /* wrong RDMA version */

        FW_RI_CQE_ERR_OPCODE            = 0x16, /* invalid rdma opcode */

        FW_RI_CQE_ERR_DDP_QUEUE_NUM     = 0x17, /* invalid ddp queue number */

        FW_RI_CQE_ERR_MSN               = 0x18, /* MSN error */

        FW_RI_CQE_ERR_TBIT              = 0x19, /* tag bit not set correctly */

        FW_RI_CQE_ERR_MO                = 0x1A, /* MO not zero for TERMINATE or READ_REQ */

        FW_RI_CQE_ERR_MSN_GAP           = 0x1B, /* */

        FW_RI_CQE_ERR_MSN_RANGE         = 0x1C, /* */

        FW_RI_CQE_ERR_IRD_OVERFLOW      = 0x1D, /* */

        FW_RI_CQE_ERR_RQE_ADDR_BOUND    = 0x1E, /*  RQE address out of bound : software error */

        FW_RI_CQE_ERR_INTERNAL_ERR      = 0x1F  /* internel error (opcode mismatch) */


};


struct fw_ri_dsge_pair {

        __be32  len[2];

        __be64  addr[2];

};


struct fw_ri_dsgl {

        __u8    op;

        __u8    r1;

        __be16  nsge;

        __be32  len0;

        __be64  addr0;

#ifndef C99_NOT_SUPPORTED

        struct fw_ri_dsge_pair sge[0];

#endif

};


struct fw_ri_sge {

        __be32 stag;

        __be32 len;

        __be64 to;

};


struct fw_ri_isgl {

        __u8    op;

        __u8    r1;

        __be16  nsge;

        __be32  r2;

#ifndef C99_NOT_SUPPORTED

        struct fw_ri_sge sge[0];

#endif

};


struct fw_ri_immd {

        __u8    op;

        __u8    r1;

        __be16  r2;

        __be32  immdlen;

#ifndef C99_NOT_SUPPORTED

        __u8    data[0];

#endif

};


struct fw_ri_tpte {

        __be32 valid_to_pdid;

        __be32 locread_to_qpid;

        __be32 nosnoop_pbladdr;

        __be32 len_lo;

        __be32 va_hi;

        __be32 va_lo_fbo;

        __be32 dca_mwbcnt_pstag;

        __be32 len_hi;

};


#define S_FW_RI_TPTE_VALID              31

#define M_FW_RI_TPTE_VALID              0x1

#define V_FW_RI_TPTE_VALID(x)           ((x) << S_FW_RI_TPTE_VALID)

#define G_FW_RI_TPTE_VALID(x)           \

    (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)

#define F_FW_RI_TPTE_VALID              V_FW_RI_TPTE_VALID(1U)


#define S_FW_RI_TPTE_STAGKEY            23

#define M_FW_RI_TPTE_STAGKEY            0xff

#define V_FW_RI_TPTE_STAGKEY(x)         ((x) << S_FW_RI_TPTE_STAGKEY)

#define G_FW_RI_TPTE_STAGKEY(x)         \

    (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)


#define S_FW_RI_TPTE_STAGSTATE          22

#define M_FW_RI_TPTE_STAGSTATE          0x1

#define V_FW_RI_TPTE_STAGSTATE(x)       ((x) << S_FW_RI_TPTE_STAGSTATE)

#define G_FW_RI_TPTE_STAGSTATE(x)       \

    (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)

#define F_FW_RI_TPTE_STAGSTATE          V_FW_RI_TPTE_STAGSTATE(1U)


#define S_FW_RI_TPTE_STAGTYPE           20

#define M_FW_RI_TPTE_STAGTYPE           0x3

#define V_FW_RI_TPTE_STAGTYPE(x)        ((x) << S_FW_RI_TPTE_STAGTYPE)

#define G_FW_RI_TPTE_STAGTYPE(x)        \

    (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)


#define S_FW_RI_TPTE_PDID               0

#define M_FW_RI_TPTE_PDID               0xfffff

#define V_FW_RI_TPTE_PDID(x)            ((x) << S_FW_RI_TPTE_PDID)

#define G_FW_RI_TPTE_PDID(x)            \

    (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)


#define S_FW_RI_TPTE_PERM               28

#define M_FW_RI_TPTE_PERM               0xf

#define V_FW_RI_TPTE_PERM(x)            ((x) << S_FW_RI_TPTE_PERM)

#define G_FW_RI_TPTE_PERM(x)            \

    (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)


#define S_FW_RI_TPTE_REMINVDIS          27

#define M_FW_RI_TPTE_REMINVDIS          0x1

#define V_FW_RI_TPTE_REMINVDIS(x)       ((x) << S_FW_RI_TPTE_REMINVDIS)

#define G_FW_RI_TPTE_REMINVDIS(x)       \

    (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)

#define F_FW_RI_TPTE_REMINVDIS          V_FW_RI_TPTE_REMINVDIS(1U)


#define S_FW_RI_TPTE_ADDRTYPE           26

#define M_FW_RI_TPTE_ADDRTYPE           1

#define V_FW_RI_TPTE_ADDRTYPE(x)        ((x) << S_FW_RI_TPTE_ADDRTYPE)

#define G_FW_RI_TPTE_ADDRTYPE(x)        \

    (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)

#define F_FW_RI_TPTE_ADDRTYPE           V_FW_RI_TPTE_ADDRTYPE(1U)


#define S_FW_RI_TPTE_MWBINDEN           25

#define M_FW_RI_TPTE_MWBINDEN           0x1

#define V_FW_RI_TPTE_MWBINDEN(x)        ((x) << S_FW_RI_TPTE_MWBINDEN)

#define G_FW_RI_TPTE_MWBINDEN(x)        \

    (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)

#define F_FW_RI_TPTE_MWBINDEN           V_FW_RI_TPTE_MWBINDEN(1U)


#define S_FW_RI_TPTE_PS                 20

#define M_FW_RI_TPTE_PS                 0x1f

#define V_FW_RI_TPTE_PS(x)              ((x) << S_FW_RI_TPTE_PS)

#define G_FW_RI_TPTE_PS(x)              \

    (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)


#define S_FW_RI_TPTE_QPID               0

#define M_FW_RI_TPTE_QPID               0xfffff

#define V_FW_RI_TPTE_QPID(x)            ((x) << S_FW_RI_TPTE_QPID)

#define G_FW_RI_TPTE_QPID(x)            \

    (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)


#define S_FW_RI_TPTE_NOSNOOP            31

#define M_FW_RI_TPTE_NOSNOOP            0x1

#define V_FW_RI_TPTE_NOSNOOP(x)         ((x) << S_FW_RI_TPTE_NOSNOOP)

#define G_FW_RI_TPTE_NOSNOOP(x)         \

    (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)

#define F_FW_RI_TPTE_NOSNOOP            V_FW_RI_TPTE_NOSNOOP(1U)


#define S_FW_RI_TPTE_PBLADDR            0

#define M_FW_RI_TPTE_PBLADDR            0x1fffffff

#define V_FW_RI_TPTE_PBLADDR(x)         ((x) << S_FW_RI_TPTE_PBLADDR)

#define G_FW_RI_TPTE_PBLADDR(x)         \

    (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)


#define S_FW_RI_TPTE_DCA                24

#define M_FW_RI_TPTE_DCA                0x1f

#define V_FW_RI_TPTE_DCA(x)             ((x) << S_FW_RI_TPTE_DCA)

#define G_FW_RI_TPTE_DCA(x)             \

    (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)


#define S_FW_RI_TPTE_MWBCNT_PSTAG       0

#define M_FW_RI_TPTE_MWBCNT_PSTAG       0xffffff

#define V_FW_RI_TPTE_MWBCNT_PSTAT(x)    \

    ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)

#define G_FW_RI_TPTE_MWBCNT_PSTAG(x)    \

    (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)


enum fw_ri_cqe_rxtx {

        FW_RI_CQE_RXTX_RX = 0x0,

        FW_RI_CQE_RXTX_TX = 0x1,

};


struct fw_ri_cqe {

        union fw_ri_rxtx {

                struct fw_ri_scqe {

                __be32  qpid_n_stat_rxtx_type;

                __be32  plen;

                __be32  stag;

                __be32  wrid;

                } scqe;

                struct fw_ri_rcqe {

                __be32  qpid_n_stat_rxtx_type;

                __be32  plen;

                __be32  stag;

                __be32  msn;

                } rcqe;

                struct fw_ri_rcqe_imm {

                __be32  qpid_n_stat_rxtx_type;

                __be32  plen;

                __be32  mo;

                __be32  msn;

                __u64   imm_data;

                } imm_data_rcqe;

        } u;

};


#define S_FW_RI_CQE_QPID      12

#define M_FW_RI_CQE_QPID      0xfffff

#define V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)

#define G_FW_RI_CQE_QPID(x)   \

    (((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)


#define S_FW_RI_CQE_NOTIFY    10

#define M_FW_RI_CQE_NOTIFY    0x1

#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)

#define G_FW_RI_CQE_NOTIFY(x) \

    (((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)


#define S_FW_RI_CQE_STATUS    5

#define M_FW_RI_CQE_STATUS    0x1f

#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)

#define G_FW_RI_CQE_STATUS(x) \

    (((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)


#define S_FW_RI_CQE_RXTX      4

#define M_FW_RI_CQE_RXTX      0x1

#define V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)

#define G_FW_RI_CQE_RXTX(x)   \

    (((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)


#define S_FW_RI_CQE_TYPE      0

#define M_FW_RI_CQE_TYPE      0xf

#define V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)

#define G_FW_RI_CQE_TYPE(x)   \

    (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)


enum fw_ri_res_type {

        FW_RI_RES_TYPE_SQ,

        FW_RI_RES_TYPE_RQ,

        FW_RI_RES_TYPE_CQ,

        FW_RI_RES_TYPE_SRQ,

};


enum fw_ri_res_op {

        FW_RI_RES_OP_WRITE,

        FW_RI_RES_OP_RESET,

};


struct fw_ri_res {

        union fw_ri_restype {

                struct fw_ri_res_sqrq {

                        __u8   restype;

                        __u8   op;

                        __be16 r3;

                        __be32 eqid;

                        __be32 r4[2];

                        __be32 fetchszm_to_iqid;

                        __be32 dcaen_to_eqsize;

                        __be64 eqaddr;

                } sqrq;

                struct fw_ri_res_cq {

                        __u8   restype;

                        __u8   op;

                        __be16 r3;

                        __be32 iqid;

                        __be32 r4[2];

                        __be32 iqandst_to_iqandstindex;

                        __be16 iqdroprss_to_iqesize;

                        __be16 iqsize;

                        __be64 iqaddr;

                        __be32 iqns_iqro;

                        __be32 r6_lo;

                        __be64 r7;

                } cq;

                struct fw_ri_res_srq {

                        __u8   restype;

                        __u8   op;

                        __be16 r3;

                        __be32 eqid;

                        __be32 r4[2];

                        __be32 fetchszm_to_iqid;

                        __be32 dcaen_to_eqsize;

                        __be64 eqaddr;

                        __be32 srqid;

                        __be32 pdid;

                        __be32 hwsrqsize;

                        __be32 hwsrqaddr;

                } srq;

        } u;

};


struct fw_ri_res_wr {

        __be32 op_nres;

        __be32 len16_pkd;

        __u64  cookie;

#ifndef C99_NOT_SUPPORTED

        struct fw_ri_res res[0];

#endif

};


#define S_FW_RI_RES_WR_VFN              8

#define M_FW_RI_RES_WR_VFN              0xff

#define V_FW_RI_RES_WR_VFN(x)           ((x) << S_FW_RI_RES_WR_VFN)

#define G_FW_RI_RES_WR_VFN(x)           \

    (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)


#define S_FW_RI_RES_WR_NRES     0

#define M_FW_RI_RES_WR_NRES     0xff

#define V_FW_RI_RES_WR_NRES(x)  ((x) << S_FW_RI_RES_WR_NRES)

#define G_FW_RI_RES_WR_NRES(x)  \

    (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)


#define S_FW_RI_RES_WR_FETCHSZM         26

#define M_FW_RI_RES_WR_FETCHSZM         0x1

#define V_FW_RI_RES_WR_FETCHSZM(x)      ((x) << S_FW_RI_RES_WR_FETCHSZM)

#define G_FW_RI_RES_WR_FETCHSZM(x)      \

    (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)

#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)


#define S_FW_RI_RES_WR_STATUSPGNS       25

#define M_FW_RI_RES_WR_STATUSPGNS       0x1

#define V_FW_RI_RES_WR_STATUSPGNS(x)    ((x) << S_FW_RI_RES_WR_STATUSPGNS)

#define G_FW_RI_RES_WR_STATUSPGNS(x)    \

    (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)

#define F_FW_RI_RES_WR_STATUSPGNS       V_FW_RI_RES_WR_STATUSPGNS(1U)


#define S_FW_RI_RES_WR_STATUSPGRO       24

#define M_FW_RI_RES_WR_STATUSPGRO       0x1

#define V_FW_RI_RES_WR_STATUSPGRO(x)    ((x) << S_FW_RI_RES_WR_STATUSPGRO)

#define G_FW_RI_RES_WR_STATUSPGRO(x)    \

    (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)

#define F_FW_RI_RES_WR_STATUSPGRO       V_FW_RI_RES_WR_STATUSPGRO(1U)


#define S_FW_RI_RES_WR_FETCHNS          23

#define M_FW_RI_RES_WR_FETCHNS          0x1

#define V_FW_RI_RES_WR_FETCHNS(x)       ((x) << S_FW_RI_RES_WR_FETCHNS)

#define G_FW_RI_RES_WR_FETCHNS(x)       \

    (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)

#define F_FW_RI_RES_WR_FETCHNS  V_FW_RI_RES_WR_FETCHNS(1U)


#define S_FW_RI_RES_WR_FETCHRO          22

#define M_FW_RI_RES_WR_FETCHRO          0x1

#define V_FW_RI_RES_WR_FETCHRO(x)       ((x) << S_FW_RI_RES_WR_FETCHRO)

#define G_FW_RI_RES_WR_FETCHRO(x)       \

    (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)

#define F_FW_RI_RES_WR_FETCHRO  V_FW_RI_RES_WR_FETCHRO(1U)


#define S_FW_RI_RES_WR_HOSTFCMODE       20

#define M_FW_RI_RES_WR_HOSTFCMODE       0x3

#define V_FW_RI_RES_WR_HOSTFCMODE(x)    ((x) << S_FW_RI_RES_WR_HOSTFCMODE)

#define G_FW_RI_RES_WR_HOSTFCMODE(x)    \

    (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)


#define S_FW_RI_RES_WR_CPRIO    19

#define M_FW_RI_RES_WR_CPRIO    0x1

#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)

#define G_FW_RI_RES_WR_CPRIO(x) \

    (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)

#define F_FW_RI_RES_WR_CPRIO    V_FW_RI_RES_WR_CPRIO(1U)


#define S_FW_RI_RES_WR_ONCHIP           18

#define M_FW_RI_RES_WR_ONCHIP           0x1

#define V_FW_RI_RES_WR_ONCHIP(x)        ((x) << S_FW_RI_RES_WR_ONCHIP)

#define G_FW_RI_RES_WR_ONCHIP(x)        \

    (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)

#define F_FW_RI_RES_WR_ONCHIP   V_FW_RI_RES_WR_ONCHIP(1U)


#define S_FW_RI_RES_WR_PCIECHN          16

#define M_FW_RI_RES_WR_PCIECHN          0x3

#define V_FW_RI_RES_WR_PCIECHN(x)       ((x) << S_FW_RI_RES_WR_PCIECHN)

#define G_FW_RI_RES_WR_PCIECHN(x)       \

    (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)


#define S_FW_RI_RES_WR_IQID     0

#define M_FW_RI_RES_WR_IQID     0xffff

#define V_FW_RI_RES_WR_IQID(x)  ((x) << S_FW_RI_RES_WR_IQID)

#define G_FW_RI_RES_WR_IQID(x)  \

    (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)


#define S_FW_RI_RES_WR_DCAEN    31

#define M_FW_RI_RES_WR_DCAEN    0x1

#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)

#define G_FW_RI_RES_WR_DCAEN(x) \

    (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)

#define F_FW_RI_RES_WR_DCAEN    V_FW_RI_RES_WR_DCAEN(1U)


#define S_FW_RI_RES_WR_DCACPU           26

#define M_FW_RI_RES_WR_DCACPU           0x1f

#define V_FW_RI_RES_WR_DCACPU(x)        ((x) << S_FW_RI_RES_WR_DCACPU)

#define G_FW_RI_RES_WR_DCACPU(x)        \

    (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)


#define S_FW_RI_RES_WR_FBMIN    23

#define M_FW_RI_RES_WR_FBMIN    0x7

#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)

#define G_FW_RI_RES_WR_FBMIN(x) \

    (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)


#define S_FW_RI_RES_WR_FBMAX    20

#define M_FW_RI_RES_WR_FBMAX    0x7

#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)

#define G_FW_RI_RES_WR_FBMAX(x) \

    (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)


#define S_FW_RI_RES_WR_CIDXFTHRESHO     19

#define M_FW_RI_RES_WR_CIDXFTHRESHO     0x1

#define V_FW_RI_RES_WR_CIDXFTHRESHO(x)  ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)

#define G_FW_RI_RES_WR_CIDXFTHRESHO(x)  \

    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)

#define F_FW_RI_RES_WR_CIDXFTHRESHO     V_FW_RI_RES_WR_CIDXFTHRESHO(1U)


#define S_FW_RI_RES_WR_CIDXFTHRESH      16

#define M_FW_RI_RES_WR_CIDXFTHRESH      0x7

#define V_FW_RI_RES_WR_CIDXFTHRESH(x)   ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)

#define G_FW_RI_RES_WR_CIDXFTHRESH(x)   \

    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)


#define S_FW_RI_RES_WR_EQSIZE           0

#define M_FW_RI_RES_WR_EQSIZE           0xffff

#define V_FW_RI_RES_WR_EQSIZE(x)        ((x) << S_FW_RI_RES_WR_EQSIZE)

#define G_FW_RI_RES_WR_EQSIZE(x)        \

    (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)


#define S_FW_RI_RES_WR_IQANDST          15

#define M_FW_RI_RES_WR_IQANDST          0x1

#define V_FW_RI_RES_WR_IQANDST(x)       ((x) << S_FW_RI_RES_WR_IQANDST)

#define G_FW_RI_RES_WR_IQANDST(x)       \

    (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)

#define F_FW_RI_RES_WR_IQANDST  V_FW_RI_RES_WR_IQANDST(1U)


#define S_FW_RI_RES_WR_IQANUS           14

#define M_FW_RI_RES_WR_IQANUS           0x1

#define V_FW_RI_RES_WR_IQANUS(x)        ((x) << S_FW_RI_RES_WR_IQANUS)

#define G_FW_RI_RES_WR_IQANUS(x)        \

    (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)

#define F_FW_RI_RES_WR_IQANUS   V_FW_RI_RES_WR_IQANUS(1U)


#define S_FW_RI_RES_WR_IQANUD           12

#define M_FW_RI_RES_WR_IQANUD           0x3

#define V_FW_RI_RES_WR_IQANUD(x)        ((x) << S_FW_RI_RES_WR_IQANUD)

#define G_FW_RI_RES_WR_IQANUD(x)        \

    (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)


#define S_FW_RI_RES_WR_IQANDSTINDEX     0

#define M_FW_RI_RES_WR_IQANDSTINDEX     0xfff

#define V_FW_RI_RES_WR_IQANDSTINDEX(x)  ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)

#define G_FW_RI_RES_WR_IQANDSTINDEX(x)  \

    (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)


#define S_FW_RI_RES_WR_IQDROPRSS        15

#define M_FW_RI_RES_WR_IQDROPRSS        0x1

#define V_FW_RI_RES_WR_IQDROPRSS(x)     ((x) << S_FW_RI_RES_WR_IQDROPRSS)

#define G_FW_RI_RES_WR_IQDROPRSS(x)     \

    (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)

#define F_FW_RI_RES_WR_IQDROPRSS        V_FW_RI_RES_WR_IQDROPRSS(1U)


#define S_FW_RI_RES_WR_IQGTSMODE        14

#define M_FW_RI_RES_WR_IQGTSMODE        0x1

#define V_FW_RI_RES_WR_IQGTSMODE(x)     ((x) << S_FW_RI_RES_WR_IQGTSMODE)

#define G_FW_RI_RES_WR_IQGTSMODE(x)     \

    (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)

#define F_FW_RI_RES_WR_IQGTSMODE        V_FW_RI_RES_WR_IQGTSMODE(1U)


#define S_FW_RI_RES_WR_IQPCIECH         12

#define M_FW_RI_RES_WR_IQPCIECH         0x3

#define V_FW_RI_RES_WR_IQPCIECH(x)      ((x) << S_FW_RI_RES_WR_IQPCIECH)

#define G_FW_RI_RES_WR_IQPCIECH(x)      \

    (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)


#define S_FW_RI_RES_WR_IQDCAEN          11

#define M_FW_RI_RES_WR_IQDCAEN          0x1

#define V_FW_RI_RES_WR_IQDCAEN(x)       ((x) << S_FW_RI_RES_WR_IQDCAEN)

#define G_FW_RI_RES_WR_IQDCAEN(x)       \

    (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)

#define F_FW_RI_RES_WR_IQDCAEN  V_FW_RI_RES_WR_IQDCAEN(1U)


#define S_FW_RI_RES_WR_IQDCACPU         6

#define M_FW_RI_RES_WR_IQDCACPU         0x1f

#define V_FW_RI_RES_WR_IQDCACPU(x)      ((x) << S_FW_RI_RES_WR_IQDCACPU)

#define G_FW_RI_RES_WR_IQDCACPU(x)      \

    (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)


#define S_FW_RI_RES_WR_IQINTCNTTHRESH           4

#define M_FW_RI_RES_WR_IQINTCNTTHRESH           0x3

#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)        \

    ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)

#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)        \

    (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)


#define S_FW_RI_RES_WR_IQO      3

#define M_FW_RI_RES_WR_IQO      0x1

#define V_FW_RI_RES_WR_IQO(x)   ((x) << S_FW_RI_RES_WR_IQO)

#define G_FW_RI_RES_WR_IQO(x)   \

    (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)

#define F_FW_RI_RES_WR_IQO      V_FW_RI_RES_WR_IQO(1U)


#define S_FW_RI_RES_WR_IQCPRIO          2

#define M_FW_RI_RES_WR_IQCPRIO          0x1

#define V_FW_RI_RES_WR_IQCPRIO(x)       ((x) << S_FW_RI_RES_WR_IQCPRIO)

#define G_FW_RI_RES_WR_IQCPRIO(x)       \

    (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)

#define F_FW_RI_RES_WR_IQCPRIO  V_FW_RI_RES_WR_IQCPRIO(1U)


#define S_FW_RI_RES_WR_IQESIZE          0

#define M_FW_RI_RES_WR_IQESIZE          0x3

#define V_FW_RI_RES_WR_IQESIZE(x)       ((x) << S_FW_RI_RES_WR_IQESIZE)

#define G_FW_RI_RES_WR_IQESIZE(x)       \

    (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)


#define S_FW_RI_RES_WR_IQNS     31

#define M_FW_RI_RES_WR_IQNS     0x1

#define V_FW_RI_RES_WR_IQNS(x)  ((x) << S_FW_RI_RES_WR_IQNS)

#define G_FW_RI_RES_WR_IQNS(x)  \

    (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)

#define F_FW_RI_RES_WR_IQNS     V_FW_RI_RES_WR_IQNS(1U)


#define S_FW_RI_RES_WR_IQRO     30

#define M_FW_RI_RES_WR_IQRO     0x1

#define V_FW_RI_RES_WR_IQRO(x)  ((x) << S_FW_RI_RES_WR_IQRO)

#define G_FW_RI_RES_WR_IQRO(x)  \

    (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)

#define F_FW_RI_RES_WR_IQRO     V_FW_RI_RES_WR_IQRO(1U)


struct fw_ri_rdma_write_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __u64  immd_data;

        __be32 plen;

        __be32 stag_sink;

        __be64 to_sink;

#ifndef C99_NOT_SUPPORTED

        union {

                struct fw_ri_immd immd_src[0];

                struct fw_ri_isgl isgl_src[0];

        } u;

#endif

};


struct fw_ri_send_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __be32 sendop_pkd;

        __be32 stag_inv;

        __be32 plen;

        __be32 r3;

        __be64 r4;

#ifndef C99_NOT_SUPPORTED

        union {

                struct fw_ri_immd immd_src[0];

                struct fw_ri_isgl isgl_src[0];

        } u;

#endif

};


#define S_FW_RI_SEND_WR_SENDOP          0

#define M_FW_RI_SEND_WR_SENDOP          0xf

#define V_FW_RI_SEND_WR_SENDOP(x)       ((x) << S_FW_RI_SEND_WR_SENDOP)

#define G_FW_RI_SEND_WR_SENDOP(x)       \

    (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)


struct fw_ri_rdma_write_cmpl_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __u8   r2;

        __u8   flags_send;

        __u16  wrid_send;

        __be32 stag_inv;

        __be32 plen;

        __be32 stag_sink;

        __be64 to_sink;

        union fw_ri_cmpl {

                struct fw_ri_immd_cmpl {

                        __u8   op;

                        __u8   r1[6];

                        __u8   immdlen;

                        __u8   data[16];

                } immd_src;

                struct fw_ri_isgl isgl_src;

        } u_cmpl;

        __be64 r3;

#ifndef C99_NOT_SUPPORTED

        union fw_ri_write {

                struct fw_ri_immd immd_src[0];

                struct fw_ri_isgl isgl_src[0];

        } u;

#endif

};


struct fw_ri_rdma_read_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __be64 r2;

        __be32 stag_sink;

        __be32 to_sink_hi;

        __be32 to_sink_lo;

        __be32 plen;

        __be32 stag_src;

        __be32 to_src_hi;

        __be32 to_src_lo;

        __be32 r5;

};


struct fw_ri_recv_wr {

        __u8   opcode;

        __u8   r1;

        __u16  wrid;

        __u8   r2[3];

        __u8   len16;

        struct fw_ri_isgl isgl;

};


struct fw_ri_bind_mw_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __u8   qpbinde_to_dcacpu;

        __u8   pgsz_shift;

        __u8   addr_type;

        __u8   mem_perms;

        __be32 stag_mr;

        __be32 stag_mw;

        __be32 r3;

        __be64 len_mw;

        __be64 va_fbo;

        __be64 r4;

};


#define S_FW_RI_BIND_MW_WR_QPBINDE      6

#define M_FW_RI_BIND_MW_WR_QPBINDE      0x1

#define V_FW_RI_BIND_MW_WR_QPBINDE(x)   ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)

#define G_FW_RI_BIND_MW_WR_QPBINDE(x)   \

    (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)

#define F_FW_RI_BIND_MW_WR_QPBINDE      V_FW_RI_BIND_MW_WR_QPBINDE(1U)


#define S_FW_RI_BIND_MW_WR_NS           5

#define M_FW_RI_BIND_MW_WR_NS           0x1

#define V_FW_RI_BIND_MW_WR_NS(x)        ((x) << S_FW_RI_BIND_MW_WR_NS)

#define G_FW_RI_BIND_MW_WR_NS(x)        \

    (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)

#define F_FW_RI_BIND_MW_WR_NS   V_FW_RI_BIND_MW_WR_NS(1U)


#define S_FW_RI_BIND_MW_WR_DCACPU       0

#define M_FW_RI_BIND_MW_WR_DCACPU       0x1f

#define V_FW_RI_BIND_MW_WR_DCACPU(x)    ((x) << S_FW_RI_BIND_MW_WR_DCACPU)

#define G_FW_RI_BIND_MW_WR_DCACPU(x)    \

    (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)


struct fw_ri_fr_nsmr_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __u8   qpbinde_to_dcacpu;

        __u8   pgsz_shift;

        __u8   addr_type;

        __u8   mem_perms;

        __be32 stag;

        __be32 len_hi;

        __be32 len_lo;

        __be32 va_hi;

        __be32 va_lo_fbo;

};


#define S_FW_RI_FR_NSMR_WR_QPBINDE      6

#define M_FW_RI_FR_NSMR_WR_QPBINDE      0x1

#define V_FW_RI_FR_NSMR_WR_QPBINDE(x)   ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)

#define G_FW_RI_FR_NSMR_WR_QPBINDE(x)   \

    (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)

#define F_FW_RI_FR_NSMR_WR_QPBINDE      V_FW_RI_FR_NSMR_WR_QPBINDE(1U)


#define S_FW_RI_FR_NSMR_WR_NS           5

#define M_FW_RI_FR_NSMR_WR_NS           0x1

#define V_FW_RI_FR_NSMR_WR_NS(x)        ((x) << S_FW_RI_FR_NSMR_WR_NS)

#define G_FW_RI_FR_NSMR_WR_NS(x)        \

    (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)

#define F_FW_RI_FR_NSMR_WR_NS   V_FW_RI_FR_NSMR_WR_NS(1U)


#define S_FW_RI_FR_NSMR_WR_DCACPU       0

#define M_FW_RI_FR_NSMR_WR_DCACPU       0x1f

#define V_FW_RI_FR_NSMR_WR_DCACPU(x)    ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)

#define G_FW_RI_FR_NSMR_WR_DCACPU(x)    \

    (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)


struct fw_ri_fr_nsmr_tpte_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __be32 r2;

        __be32 stag;

        struct fw_ri_tpte tpte;

        __be64 pbl[2];

};


struct fw_ri_inv_lstag_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __be32 r2;

        __be32 stag_inv;

};


struct fw_ri_send_immediate_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __be32 sendimmop_pkd;

        __be32 r3;

        __be32 plen;

        __be32 r4;

        __be64 r5;

#ifndef C99_NOT_SUPPORTED

        struct fw_ri_immd immd_src[0];

#endif

};


#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP     0

#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP     0xf

#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)  \

    ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)

#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)  \

    (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \

     M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)


enum fw_ri_atomic_op {

        FW_RI_ATOMIC_OP_FETCHADD,

        FW_RI_ATOMIC_OP_SWAP,

        FW_RI_ATOMIC_OP_CMDSWAP,

};


struct fw_ri_atomic_wr {

        __u8   opcode;

        __u8   flags;

        __u16  wrid;

        __u8   r1[3];

        __u8   len16;

        __be32 atomicop_pkd;

        __be64 r3;

        __be32 aopcode_pkd;

        __be32 reqid;

        __be32 stag;

        __be32 to_hi;

        __be32 to_lo;

        __be32 addswap_data_hi;

        __be32 addswap_data_lo;

        __be32 addswap_mask_hi;

        __be32 addswap_mask_lo;

        __be32 compare_data_hi;

        __be32 compare_data_lo;

        __be32 compare_mask_hi;

        __be32 compare_mask_lo;

        __be32 r5;

};


#define S_FW_RI_ATOMIC_WR_ATOMICOP      0

#define M_FW_RI_ATOMIC_WR_ATOMICOP      0xf

#define V_FW_RI_ATOMIC_WR_ATOMICOP(x)   ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)

#define G_FW_RI_ATOMIC_WR_ATOMICOP(x)   \

    (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)


#define S_FW_RI_ATOMIC_WR_AOPCODE       0

#define M_FW_RI_ATOMIC_WR_AOPCODE       0xf

#define V_FW_RI_ATOMIC_WR_AOPCODE(x)    ((x) << S_FW_RI_ATOMIC_WR_AOPCODE)

#define G_FW_RI_ATOMIC_WR_AOPCODE(x)    \

    (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)


enum fw_ri_type {

        FW_RI_TYPE_INIT,

        FW_RI_TYPE_FINI,

        FW_RI_TYPE_TERMINATE

};


enum fw_ri_init_p2ptype {

        FW_RI_INIT_P2PTYPE_RDMA_WRITE           = FW_RI_RDMA_WRITE,

        FW_RI_INIT_P2PTYPE_READ_REQ             = FW_RI_READ_REQ,

        FW_RI_INIT_P2PTYPE_SEND                 = FW_RI_SEND,

        FW_RI_INIT_P2PTYPE_SEND_WITH_INV        = FW_RI_SEND_WITH_INV,

        FW_RI_INIT_P2PTYPE_SEND_WITH_SE         = FW_RI_SEND_WITH_SE,

        FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV     = FW_RI_SEND_WITH_SE_INV,

        FW_RI_INIT_P2PTYPE_DISABLED             = 0xf,

};


enum fw_ri_init_rqeqid_srq {

        FW_RI_INIT_RQEQID_SRQ                   = 1 << 31,

};


struct fw_ri_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __u64  cookie;

        union fw_ri {

                struct fw_ri_init {

                        __u8   type;

                        __u8   mpareqbit_p2ptype;

                        __u8   r4[2];

                        __u8   mpa_attrs;

                        __u8   qp_caps;

                        __be16 nrqe;

                        __be32 pdid;

                        __be32 qpid;

                        __be32 sq_eqid;

                        __be32 rq_eqid;

                        __be32 scqid;

                        __be32 rcqid;

                        __be32 ord_max;

                        __be32 ird_max;

                        __be32 iss;

                        __be32 irs;

                        __be32 hwrqsize;

                        __be32 hwrqaddr;

                        __be64 r5;

                        union fw_ri_init_p2p {

                                struct fw_ri_rdma_write_wr write;

                                struct fw_ri_rdma_read_wr read;

                                struct fw_ri_send_wr send;

                        } u;

                } init;

                struct fw_ri_fini {

                        __u8   type;

                        __u8   r3[7];

                        __be64 r4;

                } fini;

                struct fw_ri_terminate {

                        __u8   type;

                        __u8   r3[3];

                        __be32 immdlen;

                        __u8   termmsg[40];

                } terminate;

        } u;

};


#define S_FW_RI_WR_MPAREQBIT    7

#define M_FW_RI_WR_MPAREQBIT    0x1

#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)

#define G_FW_RI_WR_MPAREQBIT(x) \

    (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)

#define F_FW_RI_WR_MPAREQBIT    V_FW_RI_WR_MPAREQBIT(1U)


#define S_FW_RI_WR_0BRRBIT      6

#define M_FW_RI_WR_0BRRBIT      0x1

#define V_FW_RI_WR_0BRRBIT(x)   ((x) << S_FW_RI_WR_0BRRBIT)

#define G_FW_RI_WR_0BRRBIT(x)   \

    (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)

#define F_FW_RI_WR_0BRRBIT      V_FW_RI_WR_0BRRBIT(1U)


#define S_FW_RI_WR_P2PTYPE      0

#define M_FW_RI_WR_P2PTYPE      0xf

#define V_FW_RI_WR_P2PTYPE(x)   ((x) << S_FW_RI_WR_P2PTYPE)

#define G_FW_RI_WR_P2PTYPE(x)   \

    (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)


/******************************************************************************

 *  F O i S C S I   W O R K R E Q U E S T s

 *********************************************/


#define FW_FOISCSI_NAME_MAX_LEN         224

#define FW_FOISCSI_ALIAS_MAX_LEN        224

#define FW_FOISCSI_KEY_MAX_LEN  64

#define FW_FOISCSI_VAL_MAX_LEN  256

#define FW_FOISCSI_CHAP_SEC_MAX_LEN     128

#define FW_FOISCSI_INIT_NODE_MAX        8


enum fw_chnet_ifconf_wr_subop {

        FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,


        FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,

        FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,


        FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,

        FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,


        FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,

        FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,


        FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,

        FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,


        FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,

        FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,


        FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,

        FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,


        FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,

        FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,


        FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,

        FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,

        FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,


        FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4,

        FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6,


        FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4,

        FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6,


        FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR,


        FW_CHNET_IFCONF_WR_SUBOP_MAX,

};


struct fw_chnet_ifconf_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __u64  cookie;

        __be32 if_flowid;

        __u8   idx;

        __u8   subop;

        __u8   retval;

        __u8   r2;

        union {

                __be64 r3;

                struct fw_chnet_ifconf_ping {

                        __be16 ping_time;

                        __u8   ping_rsptype;

                        __u8   ping_param_rspcode_to_fin_bit;

                        __u8   ping_pktsize;

                        __u8   ping_ttl;

                        __be16 ping_seq;

                } ping;

                struct fw_chnet_ifconf_mac {

                        __u8   peer_mac[6];

                        __u8   smac_idx;

                } mac;

        } u;

        struct fw_chnet_ifconf_params {

                __be16 ping_pldsize;

                __be16 r0;

                __be16 vlanid;

                __be16 mtu;

                union fw_chnet_ifconf_addr_type {

                        struct fw_chnet_ifconf_ipv4 {

                                __be32 addr;

                                __be32 mask;

                                __be32 router;

                                __be32 r0;

                                __be64 r1;

                        } ipv4;

                        struct fw_chnet_ifconf_ipv6 {

                                __u8   prefix_len;

                                __u8   r0;

                                __be16 r1;

                                __be32 r2;

                                __be64 addr_hi;

                                __be64 addr_lo;

                                __be64 router_hi;

                                __be64 router_lo;

                        } ipv6;

                } in_attr;

        } param;

};


#define S_FW_CHNET_IFCONF_WR_PING_MACBIT        1

#define M_FW_CHNET_IFCONF_WR_PING_MACBIT        0x1

#define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x)     \

    ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT)

#define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x)     \

    (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \

     M_FW_CHNET_IFCONF_WR_PING_MACBIT)

#define F_FW_CHNET_IFCONF_WR_PING_MACBIT        \

    V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U)


#define S_FW_CHNET_IFCONF_WR_FIN_BIT    0

#define M_FW_CHNET_IFCONF_WR_FIN_BIT    0x1

#define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT)

#define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \

    (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT)

#define F_FW_CHNET_IFCONF_WR_FIN_BIT    V_FW_CHNET_IFCONF_WR_FIN_BIT(1U)


enum fw_foiscsi_node_type {

        FW_FOISCSI_NODE_TYPE_INITIATOR = 0,

        FW_FOISCSI_NODE_TYPE_TARGET,

};


enum fw_foiscsi_session_type {

        FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,

        FW_FOISCSI_SESSION_TYPE_NORMAL,

};


enum fw_foiscsi_auth_policy {

        FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,

        FW_FOISCSI_AUTH_POLICY_MUTUAL,

};


enum fw_foiscsi_auth_method {

        FW_FOISCSI_AUTH_METHOD_NONE = 0,

        FW_FOISCSI_AUTH_METHOD_CHAP,

        FW_FOISCSI_AUTH_METHOD_CHAP_FST,

        FW_FOISCSI_AUTH_METHOD_CHAP_SEC,

};


enum fw_foiscsi_digest_type {

        FW_FOISCSI_DIGEST_TYPE_NONE = 0,

        FW_FOISCSI_DIGEST_TYPE_CRC32,

        FW_FOISCSI_DIGEST_TYPE_CRC32_FST,

        FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,

};


enum fw_foiscsi_wr_subop {

        FW_FOISCSI_WR_SUBOP_ADD = 1,

        FW_FOISCSI_WR_SUBOP_DEL = 2,

        FW_FOISCSI_WR_SUBOP_MOD = 4,

};


enum fw_coiscsi_stats_wr_subop {

        FW_COISCSI_WR_SUBOP_TOT = 1,

        FW_COISCSI_WR_SUBOP_MAX = 2,

        FW_COISCSI_WR_SUBOP_CUR = 3,

        FW_COISCSI_WR_SUBOP_CLR = 4,

};


enum fw_foiscsi_ctrl_state {

        FW_FOISCSI_CTRL_STATE_FREE = 0,

        FW_FOISCSI_CTRL_STATE_ONLINE = 1,

        FW_FOISCSI_CTRL_STATE_FAILED,

        FW_FOISCSI_CTRL_STATE_IN_RECOVERY,

        FW_FOISCSI_CTRL_STATE_REDIRECT,

};


struct fw_rdev_wr {

        __be32 op_to_immdlen;

        __be32 alloc_to_len16;

        __be64 cookie;

        __u8   protocol;

        __u8   event_cause;

        __u8   cur_state;

        __u8   prev_state;

        __be32 flags_to_assoc_flowid;

        union rdev_entry {

                struct fcoe_rdev_entry {

                        __be32 flowid;

                        __u8   protocol;

                        __u8   event_cause;

                        __u8   flags;

                        __u8   rjt_reason;

                        __u8   cur_login_st;

                        __u8   prev_login_st;

                        __be16 rcv_fr_sz;

                        __u8   rd_xfer_rdy_to_rport_type;

                        __u8   vft_to_qos;

                        __u8   org_proc_assoc_to_acc_rsp_code;

                        __u8   enh_disc_to_tgt;

                        __u8   wwnn[8];

                        __u8   wwpn[8];

                        __be16 iqid;

                        __u8   fc_oui[3];

                        __u8   r_id[3];

                } fcoe_rdev;

                struct iscsi_rdev_entry {

                        __be32 flowid;

                        __u8   protocol;

                        __u8   event_cause;

                        __u8   flags;

                        __u8   r3;

                        __be16 iscsi_opts;

                        __be16 tcp_opts;

                        __be16 ip_opts;

                        __be16 max_rcv_len;

                        __be16 max_snd_len;

                        __be16 first_brst_len;

                        __be16 max_brst_len;

                        __be16 r4;

                        __be16 def_time2wait;

                        __be16 def_time2ret;

                        __be16 nop_out_intrvl;

                        __be16 non_scsi_to;

                        __be16 isid;

                        __be16 tsid;

                        __be16 port;

                        __be16 tpgt;

                        __u8   r5[6];

                        __be16 iqid;

                } iscsi_rdev;

        } u;

};


#define S_FW_RDEV_WR_IMMDLEN    0

#define M_FW_RDEV_WR_IMMDLEN    0xff

#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN)

#define G_FW_RDEV_WR_IMMDLEN(x) \

    (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)


#define S_FW_RDEV_WR_ALLOC      31

#define M_FW_RDEV_WR_ALLOC      0x1

#define V_FW_RDEV_WR_ALLOC(x)   ((x) << S_FW_RDEV_WR_ALLOC)

#define G_FW_RDEV_WR_ALLOC(x)   \

    (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)

#define F_FW_RDEV_WR_ALLOC      V_FW_RDEV_WR_ALLOC(1U)


#define S_FW_RDEV_WR_FREE       30

#define M_FW_RDEV_WR_FREE       0x1

#define V_FW_RDEV_WR_FREE(x)    ((x) << S_FW_RDEV_WR_FREE)

#define G_FW_RDEV_WR_FREE(x)    \

    (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)

#define F_FW_RDEV_WR_FREE       V_FW_RDEV_WR_FREE(1U)


#define S_FW_RDEV_WR_MODIFY     29

#define M_FW_RDEV_WR_MODIFY     0x1

#define V_FW_RDEV_WR_MODIFY(x)  ((x) << S_FW_RDEV_WR_MODIFY)

#define G_FW_RDEV_WR_MODIFY(x)  \

    (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)

#define F_FW_RDEV_WR_MODIFY     V_FW_RDEV_WR_MODIFY(1U)


#define S_FW_RDEV_WR_FLOWID     8

#define M_FW_RDEV_WR_FLOWID     0xfffff

#define V_FW_RDEV_WR_FLOWID(x)  ((x) << S_FW_RDEV_WR_FLOWID)

#define G_FW_RDEV_WR_FLOWID(x)  \

    (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)


#define S_FW_RDEV_WR_LEN16      0

#define M_FW_RDEV_WR_LEN16      0xff

#define V_FW_RDEV_WR_LEN16(x)   ((x) << S_FW_RDEV_WR_LEN16)

#define G_FW_RDEV_WR_LEN16(x)   \

    (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)


#define S_FW_RDEV_WR_FLAGS      24

#define M_FW_RDEV_WR_FLAGS      0xff

#define V_FW_RDEV_WR_FLAGS(x)   ((x) << S_FW_RDEV_WR_FLAGS)

#define G_FW_RDEV_WR_FLAGS(x)   \

    (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)


#define S_FW_RDEV_WR_GET_NEXT           20

#define M_FW_RDEV_WR_GET_NEXT           0xf

#define V_FW_RDEV_WR_GET_NEXT(x)        ((x) << S_FW_RDEV_WR_GET_NEXT)

#define G_FW_RDEV_WR_GET_NEXT(x)        \

    (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)


#define S_FW_RDEV_WR_ASSOC_FLOWID       0

#define M_FW_RDEV_WR_ASSOC_FLOWID       0xfffff

#define V_FW_RDEV_WR_ASSOC_FLOWID(x)    ((x) << S_FW_RDEV_WR_ASSOC_FLOWID)

#define G_FW_RDEV_WR_ASSOC_FLOWID(x)    \

    (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)


#define S_FW_RDEV_WR_RJT        7

#define M_FW_RDEV_WR_RJT        0x1

#define V_FW_RDEV_WR_RJT(x)     ((x) << S_FW_RDEV_WR_RJT)

#define G_FW_RDEV_WR_RJT(x)     (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)

#define F_FW_RDEV_WR_RJT        V_FW_RDEV_WR_RJT(1U)


#define S_FW_RDEV_WR_REASON     0

#define M_FW_RDEV_WR_REASON     0x7f

#define V_FW_RDEV_WR_REASON(x)  ((x) << S_FW_RDEV_WR_REASON)

#define G_FW_RDEV_WR_REASON(x)  \

    (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)


#define S_FW_RDEV_WR_RD_XFER_RDY        7

#define M_FW_RDEV_WR_RD_XFER_RDY        0x1

#define V_FW_RDEV_WR_RD_XFER_RDY(x)     ((x) << S_FW_RDEV_WR_RD_XFER_RDY)

#define G_FW_RDEV_WR_RD_XFER_RDY(x)     \

    (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)

#define F_FW_RDEV_WR_RD_XFER_RDY        V_FW_RDEV_WR_RD_XFER_RDY(1U)


#define S_FW_RDEV_WR_WR_XFER_RDY        6

#define M_FW_RDEV_WR_WR_XFER_RDY        0x1

#define V_FW_RDEV_WR_WR_XFER_RDY(x)     ((x) << S_FW_RDEV_WR_WR_XFER_RDY)

#define G_FW_RDEV_WR_WR_XFER_RDY(x)     \

    (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)

#define F_FW_RDEV_WR_WR_XFER_RDY        V_FW_RDEV_WR_WR_XFER_RDY(1U)


#define S_FW_RDEV_WR_FC_SP      5

#define M_FW_RDEV_WR_FC_SP      0x1

#define V_FW_RDEV_WR_FC_SP(x)   ((x) << S_FW_RDEV_WR_FC_SP)

#define G_FW_RDEV_WR_FC_SP(x)   \

    (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)

#define F_FW_RDEV_WR_FC_SP      V_FW_RDEV_WR_FC_SP(1U)


#define S_FW_RDEV_WR_RPORT_TYPE         0

#define M_FW_RDEV_WR_RPORT_TYPE         0x1f

#define V_FW_RDEV_WR_RPORT_TYPE(x)      ((x) << S_FW_RDEV_WR_RPORT_TYPE)

#define G_FW_RDEV_WR_RPORT_TYPE(x)      \

    (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)


#define S_FW_RDEV_WR_VFT        7

#define M_FW_RDEV_WR_VFT        0x1

#define V_FW_RDEV_WR_VFT(x)     ((x) << S_FW_RDEV_WR_VFT)

#define G_FW_RDEV_WR_VFT(x)     (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)

#define F_FW_RDEV_WR_VFT        V_FW_RDEV_WR_VFT(1U)


#define S_FW_RDEV_WR_NPIV       6

#define M_FW_RDEV_WR_NPIV       0x1

#define V_FW_RDEV_WR_NPIV(x)    ((x) << S_FW_RDEV_WR_NPIV)

#define G_FW_RDEV_WR_NPIV(x)    \

    (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)

#define F_FW_RDEV_WR_NPIV       V_FW_RDEV_WR_NPIV(1U)


#define S_FW_RDEV_WR_CLASS      4

#define M_FW_RDEV_WR_CLASS      0x3

#define V_FW_RDEV_WR_CLASS(x)   ((x) << S_FW_RDEV_WR_CLASS)

#define G_FW_RDEV_WR_CLASS(x)   \

    (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)


#define S_FW_RDEV_WR_SEQ_DEL    3

#define M_FW_RDEV_WR_SEQ_DEL    0x1

#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL)

#define G_FW_RDEV_WR_SEQ_DEL(x) \

    (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)

#define F_FW_RDEV_WR_SEQ_DEL    V_FW_RDEV_WR_SEQ_DEL(1U)


#define S_FW_RDEV_WR_PRIO_PREEMP        2

#define M_FW_RDEV_WR_PRIO_PREEMP        0x1

#define V_FW_RDEV_WR_PRIO_PREEMP(x)     ((x) << S_FW_RDEV_WR_PRIO_PREEMP)

#define G_FW_RDEV_WR_PRIO_PREEMP(x)     \

    (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)

#define F_FW_RDEV_WR_PRIO_PREEMP        V_FW_RDEV_WR_PRIO_PREEMP(1U)


#define S_FW_RDEV_WR_PREF       1

#define M_FW_RDEV_WR_PREF       0x1

#define V_FW_RDEV_WR_PREF(x)    ((x) << S_FW_RDEV_WR_PREF)

#define G_FW_RDEV_WR_PREF(x)    \

    (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)

#define F_FW_RDEV_WR_PREF       V_FW_RDEV_WR_PREF(1U)


#define S_FW_RDEV_WR_QOS        0

#define M_FW_RDEV_WR_QOS        0x1

#define V_FW_RDEV_WR_QOS(x)     ((x) << S_FW_RDEV_WR_QOS)

#define G_FW_RDEV_WR_QOS(x)     (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)

#define F_FW_RDEV_WR_QOS        V_FW_RDEV_WR_QOS(1U)


#define S_FW_RDEV_WR_ORG_PROC_ASSOC     7

#define M_FW_RDEV_WR_ORG_PROC_ASSOC     0x1

#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x)  ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)

#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x)  \

    (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)

#define F_FW_RDEV_WR_ORG_PROC_ASSOC     V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)


#define S_FW_RDEV_WR_RSP_PROC_ASSOC     6

#define M_FW_RDEV_WR_RSP_PROC_ASSOC     0x1

#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x)  ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)

#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x)  \

    (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)

#define F_FW_RDEV_WR_RSP_PROC_ASSOC     V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)


#define S_FW_RDEV_WR_IMAGE_PAIR         5

#define M_FW_RDEV_WR_IMAGE_PAIR         0x1

#define V_FW_RDEV_WR_IMAGE_PAIR(x)      ((x) << S_FW_RDEV_WR_IMAGE_PAIR)

#define G_FW_RDEV_WR_IMAGE_PAIR(x)      \

    (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)

#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U)


#define S_FW_RDEV_WR_ACC_RSP_CODE       0

#define M_FW_RDEV_WR_ACC_RSP_CODE       0x1f

#define V_FW_RDEV_WR_ACC_RSP_CODE(x)    ((x) << S_FW_RDEV_WR_ACC_RSP_CODE)

#define G_FW_RDEV_WR_ACC_RSP_CODE(x)    \

    (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)


#define S_FW_RDEV_WR_ENH_DISC           7

#define M_FW_RDEV_WR_ENH_DISC           0x1

#define V_FW_RDEV_WR_ENH_DISC(x)        ((x) << S_FW_RDEV_WR_ENH_DISC)

#define G_FW_RDEV_WR_ENH_DISC(x)        \

    (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)

#define F_FW_RDEV_WR_ENH_DISC   V_FW_RDEV_WR_ENH_DISC(1U)


#define S_FW_RDEV_WR_REC        6

#define M_FW_RDEV_WR_REC        0x1

#define V_FW_RDEV_WR_REC(x)     ((x) << S_FW_RDEV_WR_REC)

#define G_FW_RDEV_WR_REC(x)     (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)

#define F_FW_RDEV_WR_REC        V_FW_RDEV_WR_REC(1U)


#define S_FW_RDEV_WR_TASK_RETRY_ID      5

#define M_FW_RDEV_WR_TASK_RETRY_ID      0x1

#define V_FW_RDEV_WR_TASK_RETRY_ID(x)   ((x) << S_FW_RDEV_WR_TASK_RETRY_ID)

#define G_FW_RDEV_WR_TASK_RETRY_ID(x)   \

    (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)

#define F_FW_RDEV_WR_TASK_RETRY_ID      V_FW_RDEV_WR_TASK_RETRY_ID(1U)


#define S_FW_RDEV_WR_RETRY      4

#define M_FW_RDEV_WR_RETRY      0x1

#define V_FW_RDEV_WR_RETRY(x)   ((x) << S_FW_RDEV_WR_RETRY)

#define G_FW_RDEV_WR_RETRY(x)   \

    (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)

#define F_FW_RDEV_WR_RETRY      V_FW_RDEV_WR_RETRY(1U)


#define S_FW_RDEV_WR_CONF_CMPL          3

#define M_FW_RDEV_WR_CONF_CMPL          0x1

#define V_FW_RDEV_WR_CONF_CMPL(x)       ((x) << S_FW_RDEV_WR_CONF_CMPL)

#define G_FW_RDEV_WR_CONF_CMPL(x)       \

    (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)

#define F_FW_RDEV_WR_CONF_CMPL  V_FW_RDEV_WR_CONF_CMPL(1U)


#define S_FW_RDEV_WR_DATA_OVLY          2

#define M_FW_RDEV_WR_DATA_OVLY          0x1

#define V_FW_RDEV_WR_DATA_OVLY(x)       ((x) << S_FW_RDEV_WR_DATA_OVLY)

#define G_FW_RDEV_WR_DATA_OVLY(x)       \

    (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)

#define F_FW_RDEV_WR_DATA_OVLY  V_FW_RDEV_WR_DATA_OVLY(1U)


#define S_FW_RDEV_WR_INI        1

#define M_FW_RDEV_WR_INI        0x1

#define V_FW_RDEV_WR_INI(x)     ((x) << S_FW_RDEV_WR_INI)

#define G_FW_RDEV_WR_INI(x)     (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)

#define F_FW_RDEV_WR_INI        V_FW_RDEV_WR_INI(1U)


#define S_FW_RDEV_WR_TGT        0

#define M_FW_RDEV_WR_TGT        0x1

#define V_FW_RDEV_WR_TGT(x)     ((x) << S_FW_RDEV_WR_TGT)

#define G_FW_RDEV_WR_TGT(x)     (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)

#define F_FW_RDEV_WR_TGT        V_FW_RDEV_WR_TGT(1U)


struct fw_foiscsi_node_wr {

        __be32 op_to_immdlen;

        __be32 no_sess_recv_to_len16;

        __u64  cookie;

        __u8   subop;

        __u8   status;

        __u8   alias_len;

        __u8   iqn_len;

        __be32 node_flowid;

        __be16 nodeid;

        __be16 login_retry;

        __be16 retry_timeout;

        __be16 r3;

        __u8   iqn[224];

        __u8   alias[224];

        __be32 isid_tval_to_isid_cval;

};


#define S_FW_FOISCSI_NODE_WR_IMMDLEN    0

#define M_FW_FOISCSI_NODE_WR_IMMDLEN    0xffff

#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)

#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \

    (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)


#define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV       28

#define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV       0x1

#define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x)    \

    ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV)

#define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x)    \

    (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \

     M_FW_FOISCSI_NODE_WR_NO_SESS_RECV)

#define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV       \

    V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U)


#define S_FW_FOISCSI_NODE_WR_ISID_TVAL          30

#define M_FW_FOISCSI_NODE_WR_ISID_TVAL          0x3

#define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x)       \

    ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL)

#define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x)       \

    (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL)


#define S_FW_FOISCSI_NODE_WR_ISID_AVAL          24

#define M_FW_FOISCSI_NODE_WR_ISID_AVAL          0x3f

#define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x)       \

    ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL)

#define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x)       \

    (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL)


#define S_FW_FOISCSI_NODE_WR_ISID_BVAL          8

#define M_FW_FOISCSI_NODE_WR_ISID_BVAL          0xffff

#define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x)       \

    ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL)

#define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x)       \

    (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL)


#define S_FW_FOISCSI_NODE_WR_ISID_CVAL          0

#define M_FW_FOISCSI_NODE_WR_ISID_CVAL          0xff

#define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x)       \

    ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL)

#define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x)       \

    (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL)


struct fw_foiscsi_ctrl_wr {

        __be32 op_to_no_fin;

        __be32 flowid_len16;

        __u64  cookie;

        __u8   subop;

        __u8   status;

        __u8   ctrl_state;

        __u8   io_state;

        __be32 node_id;

        __be32 ctrl_id;

        __be32 io_id;

        struct fw_foiscsi_sess_attr {

                __be32 sess_type_to_erl;

                __be16 max_conn;

                __be16 max_r2t;

                __be16 time2wait;

                __be16 time2retain;

                __be32 max_burst;

                __be32 first_burst;

                __be32 r1;

        } sess_attr;

        struct fw_foiscsi_conn_attr {

                __be32 hdigest_to_tcp_ws_en;

                __be32 max_rcv_dsl;

                __be32 ping_tmo;

                __be16 dst_port;

                __be16 src_port;

                union fw_foiscsi_conn_attr_addr {

                        struct fw_foiscsi_conn_attr_ipv6 {

                                __be64 dst_addr[2];

                                __be64 src_addr[2];

                        } ipv6_addr;

                        struct fw_foiscsi_conn_attr_ipv4 {

                                __be32 dst_addr;

                                __be32 src_addr;

                        } ipv4_addr;

                } u;

        } conn_attr;

        __u8   tgt_name_len;

        __u8   r3[7];

        __u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];

};


#define S_FW_FOISCSI_CTRL_WR_PORTID     1

#define M_FW_FOISCSI_CTRL_WR_PORTID     0x7

#define V_FW_FOISCSI_CTRL_WR_PORTID(x)  ((x) << S_FW_FOISCSI_CTRL_WR_PORTID)

#define G_FW_FOISCSI_CTRL_WR_PORTID(x)  \

    (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID)


#define S_FW_FOISCSI_CTRL_WR_NO_FIN     0

#define M_FW_FOISCSI_CTRL_WR_NO_FIN     0x1

#define V_FW_FOISCSI_CTRL_WR_NO_FIN(x)  ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN)

#define G_FW_FOISCSI_CTRL_WR_NO_FIN(x)  \

    (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN)

#define F_FW_FOISCSI_CTRL_WR_NO_FIN     V_FW_FOISCSI_CTRL_WR_NO_FIN(1U)


#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE          30

#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE          0x3

#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)       \

    ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)

#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)       \

    (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)


#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER        29

#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER        0x1

#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)     \

    ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)

#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)     \

    (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \

     M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)

#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER        \

    V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)


#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER        28

#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER        0x1

#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)     \

    ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)

#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)     \

    (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \

     M_FW_FOISCSI_CTRL_WR_PDU_INORDER)

#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER        \

    V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)


#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN       27

#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN       0x1

#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)    \

    ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)

#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)    \

    (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \

     M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)

#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN       \

    V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)


#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN        26

#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN        0x1

#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)     \

    ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)

#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)     \

    (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \

     M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)

#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN        \

    V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)


#define S_FW_FOISCSI_CTRL_WR_ERL        24

#define M_FW_FOISCSI_CTRL_WR_ERL        0x3

#define V_FW_FOISCSI_CTRL_WR_ERL(x)     ((x) << S_FW_FOISCSI_CTRL_WR_ERL)

#define G_FW_FOISCSI_CTRL_WR_ERL(x)     \

    (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)


#define S_FW_FOISCSI_CTRL_WR_HDIGEST    30

#define M_FW_FOISCSI_CTRL_WR_HDIGEST    0x3

#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)

#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \

    (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)


#define S_FW_FOISCSI_CTRL_WR_DDIGEST    28

#define M_FW_FOISCSI_CTRL_WR_DDIGEST    0x3

#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)

#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \

    (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)


#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD        25

#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD        0x7

#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)     \

    ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)

#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)     \

    (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \

     M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)


#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY        23

#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY        0x3

#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)     \

    ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)

#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)     \

    (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \

     M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)


#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ           21

#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ           0x3

#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)        \

    ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)

#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)        \

    (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)


#define S_FW_FOISCSI_CTRL_WR_IPV6       20

#define M_FW_FOISCSI_CTRL_WR_IPV6       0x1

#define V_FW_FOISCSI_CTRL_WR_IPV6(x)    ((x) << S_FW_FOISCSI_CTRL_WR_IPV6)

#define G_FW_FOISCSI_CTRL_WR_IPV6(x)    \

    (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)

#define F_FW_FOISCSI_CTRL_WR_IPV6       V_FW_FOISCSI_CTRL_WR_IPV6(1U)


#define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX          16

#define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX          0xf

#define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x)       \

    ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX)

#define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x)       \

    (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX)


#define S_FW_FOISCSI_CTRL_WR_TCP_WS     12

#define M_FW_FOISCSI_CTRL_WR_TCP_WS     0xf

#define V_FW_FOISCSI_CTRL_WR_TCP_WS(x)  ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS)

#define G_FW_FOISCSI_CTRL_WR_TCP_WS(x)  \

    (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS)


#define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN          11

#define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN          0x1

#define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x)       \

    ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN)

#define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x)       \

    (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN)

#define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN  V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U)


struct fw_foiscsi_chap_wr {

        __be32 op_to_kv_flag;

        __be32 flowid_len16;

        __u64  cookie;

        __u8   status;

        union fw_foiscsi_len {

                struct fw_foiscsi_chap_lens {

                        __u8   id_len;

                        __u8   sec_len;

                } chapl;

                struct fw_foiscsi_vend_kv_lens {

                        __u8   key_len;

                        __u8   val_len;

                } vend_kvl;

        } lenu;

        __u8   node_type;

        __be16 node_id;

        __u8   r3[2];

        union fw_foiscsi_chap_vend {

                struct fw_foiscsi_chap {

                        __u8   chap_id[224];

                        __u8   chap_sec[128];

                } chap;

                struct fw_foiscsi_vend_kv {

                        __u8   vend_key[64];

                        __u8   vend_val[256];

                } vend_kv;

        } u;

};


#define S_FW_FOISCSI_CHAP_WR_KV_FLAG    20

#define M_FW_FOISCSI_CHAP_WR_KV_FLAG    0x1

#define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG)

#define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \

    (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG)

#define F_FW_FOISCSI_CHAP_WR_KV_FLAG    V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U)


/******************************************************************************

 *  C O i S C S I  W O R K R E Q U E S T S

 ********************************************/


enum fw_chnet_addr_type {

        FW_CHNET_ADDD_TYPE_NONE = 0,

        FW_CHNET_ADDR_TYPE_IPV4,

        FW_CHNET_ADDR_TYPE_IPV6,

};


enum fw_msg_wr_type {

        FW_MSG_WR_TYPE_RPL = 0,

        FW_MSG_WR_TYPE_ERR,

        FW_MSG_WR_TYPE_PLD,

};


struct fw_coiscsi_tgt_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __u64  cookie;

        __u8   subop;

        __u8   status;

        __be16 r4;

        __be32 flags;

        struct fw_coiscsi_tgt_conn_attr {

                __be32 in_tid;

                __be16 in_port;

                __u8   in_type;

                __u8   r6;

                union fw_coiscsi_tgt_conn_attr_addr {

                        struct fw_coiscsi_tgt_conn_attr_in_addr {

                                __be32 addr;

                                __be32 r7;

                                __be32 r8[2];

                        } in_addr;

                        struct fw_coiscsi_tgt_conn_attr_in_addr6 {

                                __be64 addr[2];

                        } in_addr6;

                } u;

        } conn_attr;

};


#define S_FW_COISCSI_TGT_WR_PORTID      0

#define M_FW_COISCSI_TGT_WR_PORTID      0x7

#define V_FW_COISCSI_TGT_WR_PORTID(x)   ((x) << S_FW_COISCSI_TGT_WR_PORTID)

#define G_FW_COISCSI_TGT_WR_PORTID(x)   \

    (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID)


struct fw_coiscsi_tgt_conn_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __u64  cookie;

        __u8   subop;

        __u8   status;

        __be16 iq_id;

        __be32 in_stid;

        __be32 io_id;

        __be32 flags_fin;

        union {

                struct fw_coiscsi_tgt_conn_tcp {

                        __be16 in_sport;

                        __be16 in_dport;

                        __u8   wscale_wsen;

                        __u8   r4[3];

                        union fw_coiscsi_tgt_conn_tcp_addr {

                                struct fw_coiscsi_tgt_conn_tcp_in_addr {

                                        __be32 saddr;

                                        __be32 daddr;

                                } in_addr;

                                struct fw_coiscsi_tgt_conn_tcp_in_addr6 {

                                        __be64 saddr[2];

                                        __be64 daddr[2];

                                } in_addr6;

                        } u;

                } conn_tcp;

                struct fw_coiscsi_tgt_conn_stats {

                        __be32 ddp_reqs;

                        __be32 ddp_cmpls;

                        __be16 ddp_aborts;

                        __be16 ddp_bps;

                } stats;

        } u;

        struct fw_coiscsi_tgt_conn_iscsi {

                __be32 hdigest_to_ddp_pgsz;

                __be32 tgt_id;

                __be16 max_r2t;

                __be16 r5;

                __be32 max_burst;

                __be32 max_rdsl;

                __be32 max_tdsl;

                __be32 cur_sn;

                __be32 r6;

        } conn_iscsi;

};


#define S_FW_COISCSI_TGT_CONN_WR_PORTID         0

#define M_FW_COISCSI_TGT_CONN_WR_PORTID         0x7

#define V_FW_COISCSI_TGT_CONN_WR_PORTID(x)      \

    ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID)

#define G_FW_COISCSI_TGT_CONN_WR_PORTID(x)      \

    (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \

     M_FW_COISCSI_TGT_CONN_WR_PORTID)


#define S_FW_COISCSI_TGT_CONN_WR_FIN    0

#define M_FW_COISCSI_TGT_CONN_WR_FIN    0x1

#define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN)

#define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \

    (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN)

#define F_FW_COISCSI_TGT_CONN_WR_FIN    V_FW_COISCSI_TGT_CONN_WR_FIN(1U)


#define S_FW_COISCSI_TGT_CONN_WR_WSCALE         1

#define M_FW_COISCSI_TGT_CONN_WR_WSCALE         0xf

#define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x)      \

    ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE)

#define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x)      \

    (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \

     M_FW_COISCSI_TGT_CONN_WR_WSCALE)


#define S_FW_COISCSI_TGT_CONN_WR_WSEN           0

#define M_FW_COISCSI_TGT_CONN_WR_WSEN           0x1

#define V_FW_COISCSI_TGT_CONN_WR_WSEN(x)        \

    ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN)

#define G_FW_COISCSI_TGT_CONN_WR_WSEN(x)        \

    (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN)

#define F_FW_COISCSI_TGT_CONN_WR_WSEN   V_FW_COISCSI_TGT_CONN_WR_WSEN(1U)


struct fw_coiscsi_tgt_xmit_wr {

        __be32 op_to_immdlen;

        union {

                struct cmpl_stat {

                        __be32 cmpl_status_pkd;

                } cs;

                struct flowid_len {

                        __be32 flowid_len16;

                } fllen;

        } u;

        __u64  cookie;

        __be16 iq_id;

        __be16 r3;

        __be32 pz_off;

        __be32 t_xfer_len;

        union {

                __be32 tag;

                __be32 datasn;

                __be32 ddp_status;

        } cu;

};


#define S_FW_COISCSI_TGT_XMIT_WR_DDGST          23

#define M_FW_COISCSI_TGT_XMIT_WR_DDGST          0x1

#define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x)       \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST)

#define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x)       \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST)

#define F_FW_COISCSI_TGT_XMIT_WR_DDGST  V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U)


#define S_FW_COISCSI_TGT_XMIT_WR_HDGST          22

#define M_FW_COISCSI_TGT_XMIT_WR_HDGST          0x1

#define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x)       \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST)

#define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x)       \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST)

#define F_FW_COISCSI_TGT_XMIT_WR_HDGST  V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U)


#define S_FW_COISCSI_TGT_XMIT_WR_DDP    20

#define M_FW_COISCSI_TGT_XMIT_WR_DDP    0x1

#define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP)

#define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP)

#define F_FW_COISCSI_TGT_XMIT_WR_DDP    V_FW_COISCSI_TGT_XMIT_WR_DDP(1U)


#define S_FW_COISCSI_TGT_XMIT_WR_ABORT          19

#define M_FW_COISCSI_TGT_XMIT_WR_ABORT          0x1

#define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x)       \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT)

#define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x)       \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT)

#define F_FW_COISCSI_TGT_XMIT_WR_ABORT  V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U)


#define S_FW_COISCSI_TGT_XMIT_WR_FINAL          18

#define M_FW_COISCSI_TGT_XMIT_WR_FINAL          0x1

#define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x)       \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL)

#define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x)       \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL)

#define F_FW_COISCSI_TGT_XMIT_WR_FINAL  V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U)


#define S_FW_COISCSI_TGT_XMIT_WR_PADLEN         16

#define M_FW_COISCSI_TGT_XMIT_WR_PADLEN         0x3

#define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x)      \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN)

#define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x)      \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \

     M_FW_COISCSI_TGT_XMIT_WR_PADLEN)


#define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN      15

#define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN      0x1

#define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x)   \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)

#define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x)   \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \

     M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)

#define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN      \

    V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U)


#define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN        0

#define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN        0xff

#define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x)     \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)

#define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x)     \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \

     M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)


#define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS    8

#define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS    0xff

#define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \

    ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)

#define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \

    (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \

     M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)


struct fw_coiscsi_stats_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __u64  cookie;

        __u8   subop;

        __u8   status;

        union fw_coiscsi_stats {

                struct fw_coiscsi_resource {

                        __u8   num_ipv4_tgt;

                        __u8   num_ipv6_tgt;

                        __be16 num_l2t_entries;

                        __be16 num_csocks;

                        __be16 num_tasks;

                        __be16 num_ppods_zone[11];

                        __be32 num_bufll64;

                        __u8   r2[12];

                } rsrc;

        } u;

};


#define S_FW_COISCSI_STATS_WR_PORTID    0

#define M_FW_COISCSI_STATS_WR_PORTID    0x7

#define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID)

#define G_FW_COISCSI_STATS_WR_PORTID(x) \

    (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID)


struct fw_isns_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __u64  cookie;

        __u8   subop;

        __u8   status;

        __be16 iq_id;

        __be16 vlanid;

        __be16 r4;

        struct fw_tcp_conn_attr {

                __be32 in_tid;

                __be16 in_port;

                __u8   in_type;

                __u8   r6;

                union fw_tcp_conn_attr_addr {

                        struct fw_tcp_conn_attr_in_addr {

                                __be32 addr;

                                __be32 r7;

                                __be32 r8[2];

                        } in_addr;

                        struct fw_tcp_conn_attr_in_addr6 {

                                __be64 addr[2];

                        } in_addr6;

                } u;

        } conn_attr;

};


#define S_FW_ISNS_WR_PORTID     0

#define M_FW_ISNS_WR_PORTID     0x7

#define V_FW_ISNS_WR_PORTID(x)  ((x) << S_FW_ISNS_WR_PORTID)

#define G_FW_ISNS_WR_PORTID(x)  \

    (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID)


struct fw_isns_xmit_wr {

        __be32 op_to_immdlen;

        __be32 flowid_len16;

        __u64  cookie;

        __be16 iq_id;

        __be16 r4;

        __be32 xfer_len;

        __be64 r5;

};


#define S_FW_ISNS_XMIT_WR_IMMDLEN       0

#define M_FW_ISNS_XMIT_WR_IMMDLEN       0xff

#define V_FW_ISNS_XMIT_WR_IMMDLEN(x)    ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)

#define G_FW_ISNS_XMIT_WR_IMMDLEN(x)    \

    (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)


/******************************************************************************

 *  F O F C O E   W O R K R E Q U E S T s

 *******************************************/


struct fw_fcoe_els_ct_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   tmo_val;

        __u8   els_ct_type;

        __u8   ctl_pri;

        __u8   cp_en_class;

        __be16 xfer_cnt;

        __u8   fl_to_sp;

        __u8   l_id[3];

        __u8   r5;

        __u8   r_id[3];

        __be64 rsp_dmaaddr;

        __be32 rsp_dmalen;

        __be32 r6;

};


#define S_FW_FCOE_ELS_CT_WR_OPCODE      24

#define M_FW_FCOE_ELS_CT_WR_OPCODE      0xff

#define V_FW_FCOE_ELS_CT_WR_OPCODE(x)   ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)

#define G_FW_FCOE_ELS_CT_WR_OPCODE(x)   \

    (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)


#define S_FW_FCOE_ELS_CT_WR_IMMDLEN     0

#define M_FW_FCOE_ELS_CT_WR_IMMDLEN     0xff

#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)  ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)

#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)  \

    (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)


#define S_FW_FCOE_ELS_CT_WR_FLOWID      8

#define M_FW_FCOE_ELS_CT_WR_FLOWID      0xfffff

#define V_FW_FCOE_ELS_CT_WR_FLOWID(x)   ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)

#define G_FW_FCOE_ELS_CT_WR_FLOWID(x)   \

    (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)


#define S_FW_FCOE_ELS_CT_WR_LEN16       0

#define M_FW_FCOE_ELS_CT_WR_LEN16       0xff

#define V_FW_FCOE_ELS_CT_WR_LEN16(x)    ((x) << S_FW_FCOE_ELS_CT_WR_LEN16)

#define G_FW_FCOE_ELS_CT_WR_LEN16(x)    \

    (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)


#define S_FW_FCOE_ELS_CT_WR_CP_EN       6

#define M_FW_FCOE_ELS_CT_WR_CP_EN       0x3

#define V_FW_FCOE_ELS_CT_WR_CP_EN(x)    ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)

#define G_FW_FCOE_ELS_CT_WR_CP_EN(x)    \

    (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)


#define S_FW_FCOE_ELS_CT_WR_CLASS       4

#define M_FW_FCOE_ELS_CT_WR_CLASS       0x3

#define V_FW_FCOE_ELS_CT_WR_CLASS(x)    ((x) << S_FW_FCOE_ELS_CT_WR_CLASS)

#define G_FW_FCOE_ELS_CT_WR_CLASS(x)    \

    (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)


#define S_FW_FCOE_ELS_CT_WR_FL          2

#define M_FW_FCOE_ELS_CT_WR_FL          0x1

#define V_FW_FCOE_ELS_CT_WR_FL(x)       ((x) << S_FW_FCOE_ELS_CT_WR_FL)

#define G_FW_FCOE_ELS_CT_WR_FL(x)       \

    (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)

#define F_FW_FCOE_ELS_CT_WR_FL  V_FW_FCOE_ELS_CT_WR_FL(1U)


#define S_FW_FCOE_ELS_CT_WR_NPIV        1

#define M_FW_FCOE_ELS_CT_WR_NPIV        0x1

#define V_FW_FCOE_ELS_CT_WR_NPIV(x)     ((x) << S_FW_FCOE_ELS_CT_WR_NPIV)

#define G_FW_FCOE_ELS_CT_WR_NPIV(x)     \

    (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)

#define F_FW_FCOE_ELS_CT_WR_NPIV        V_FW_FCOE_ELS_CT_WR_NPIV(1U)


#define S_FW_FCOE_ELS_CT_WR_SP          0

#define M_FW_FCOE_ELS_CT_WR_SP          0x1

#define V_FW_FCOE_ELS_CT_WR_SP(x)       ((x) << S_FW_FCOE_ELS_CT_WR_SP)

#define G_FW_FCOE_ELS_CT_WR_SP(x)       \

    (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)

#define F_FW_FCOE_ELS_CT_WR_SP  V_FW_FCOE_ELS_CT_WR_SP(1U)


/******************************************************************************

 *  S C S I   W O R K R E Q U E S T s   (FOiSCSI and FCOE unified data path)

 *****************************************************************************/


struct fw_scsi_write_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   tmo_val;

        __u8   use_xfer_cnt;

        union fw_scsi_write_priv {

                struct fcoe_write_priv {

                        __u8   ctl_pri;

                        __u8   cp_en_class;

                        __u8   r3_lo[2];

                } fcoe;

                struct iscsi_write_priv {

                        __u8   r3[4];

                } iscsi;

        } u;

        __be32 xfer_cnt;

        __be32 ini_xfer_cnt;

        __be64 rsp_dmaaddr;

        __be32 rsp_dmalen;

        __be32 r4;

};


#define S_FW_SCSI_WRITE_WR_OPCODE       24

#define M_FW_SCSI_WRITE_WR_OPCODE       0xff

#define V_FW_SCSI_WRITE_WR_OPCODE(x)    ((x) << S_FW_SCSI_WRITE_WR_OPCODE)

#define G_FW_SCSI_WRITE_WR_OPCODE(x)    \

    (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)


#define S_FW_SCSI_WRITE_WR_IMMDLEN      0

#define M_FW_SCSI_WRITE_WR_IMMDLEN      0xff

#define V_FW_SCSI_WRITE_WR_IMMDLEN(x)   ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)

#define G_FW_SCSI_WRITE_WR_IMMDLEN(x)   \

    (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)


#define S_FW_SCSI_WRITE_WR_FLOWID       8

#define M_FW_SCSI_WRITE_WR_FLOWID       0xfffff

#define V_FW_SCSI_WRITE_WR_FLOWID(x)    ((x) << S_FW_SCSI_WRITE_WR_FLOWID)

#define G_FW_SCSI_WRITE_WR_FLOWID(x)    \

    (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)


#define S_FW_SCSI_WRITE_WR_LEN16        0

#define M_FW_SCSI_WRITE_WR_LEN16        0xff

#define V_FW_SCSI_WRITE_WR_LEN16(x)     ((x) << S_FW_SCSI_WRITE_WR_LEN16)

#define G_FW_SCSI_WRITE_WR_LEN16(x)     \

    (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)


#define S_FW_SCSI_WRITE_WR_CP_EN        6

#define M_FW_SCSI_WRITE_WR_CP_EN        0x3

#define V_FW_SCSI_WRITE_WR_CP_EN(x)     ((x) << S_FW_SCSI_WRITE_WR_CP_EN)

#define G_FW_SCSI_WRITE_WR_CP_EN(x)     \

    (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)


#define S_FW_SCSI_WRITE_WR_CLASS        4

#define M_FW_SCSI_WRITE_WR_CLASS        0x3

#define V_FW_SCSI_WRITE_WR_CLASS(x)     ((x) << S_FW_SCSI_WRITE_WR_CLASS)

#define G_FW_SCSI_WRITE_WR_CLASS(x)     \

    (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)


struct fw_scsi_read_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   tmo_val;

        __u8   use_xfer_cnt;

        union fw_scsi_read_priv {

                struct fcoe_read_priv {

                        __u8   ctl_pri;

                        __u8   cp_en_class;

                        __u8   r3_lo[2];

                } fcoe;

                struct iscsi_read_priv {

                        __u8   r3[4];

                } iscsi;

        } u;

        __be32 xfer_cnt;

        __be32 ini_xfer_cnt;

        __be64 rsp_dmaaddr;

        __be32 rsp_dmalen;

        __be32 r4;

};


#define S_FW_SCSI_READ_WR_OPCODE        24

#define M_FW_SCSI_READ_WR_OPCODE        0xff

#define V_FW_SCSI_READ_WR_OPCODE(x)     ((x) << S_FW_SCSI_READ_WR_OPCODE)

#define G_FW_SCSI_READ_WR_OPCODE(x)     \

    (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)


#define S_FW_SCSI_READ_WR_IMMDLEN       0

#define M_FW_SCSI_READ_WR_IMMDLEN       0xff

#define V_FW_SCSI_READ_WR_IMMDLEN(x)    ((x) << S_FW_SCSI_READ_WR_IMMDLEN)

#define G_FW_SCSI_READ_WR_IMMDLEN(x)    \

    (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)


#define S_FW_SCSI_READ_WR_FLOWID        8

#define M_FW_SCSI_READ_WR_FLOWID        0xfffff

#define V_FW_SCSI_READ_WR_FLOWID(x)     ((x) << S_FW_SCSI_READ_WR_FLOWID)

#define G_FW_SCSI_READ_WR_FLOWID(x)     \

    (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)


#define S_FW_SCSI_READ_WR_LEN16         0

#define M_FW_SCSI_READ_WR_LEN16         0xff

#define V_FW_SCSI_READ_WR_LEN16(x)      ((x) << S_FW_SCSI_READ_WR_LEN16)

#define G_FW_SCSI_READ_WR_LEN16(x)      \

    (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)


#define S_FW_SCSI_READ_WR_CP_EN         6

#define M_FW_SCSI_READ_WR_CP_EN         0x3

#define V_FW_SCSI_READ_WR_CP_EN(x)      ((x) << S_FW_SCSI_READ_WR_CP_EN)

#define G_FW_SCSI_READ_WR_CP_EN(x)      \

    (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)


#define S_FW_SCSI_READ_WR_CLASS         4

#define M_FW_SCSI_READ_WR_CLASS         0x3

#define V_FW_SCSI_READ_WR_CLASS(x)      ((x) << S_FW_SCSI_READ_WR_CLASS)

#define G_FW_SCSI_READ_WR_CLASS(x)      \

    (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)


struct fw_scsi_cmd_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   tmo_val;

        __u8   r3;

        union fw_scsi_cmd_priv {

                struct fcoe_cmd_priv {

                        __u8   ctl_pri;

                        __u8   cp_en_class;

                        __u8   r4_lo[2];

                } fcoe;

                struct iscsi_cmd_priv {

                        __u8   r4[4];

                } iscsi;

        } u;

        __u8   r5[8];

        __be64 rsp_dmaaddr;

        __be32 rsp_dmalen;

        __be32 r6;

};


#define S_FW_SCSI_CMD_WR_OPCODE         24

#define M_FW_SCSI_CMD_WR_OPCODE         0xff

#define V_FW_SCSI_CMD_WR_OPCODE(x)      ((x) << S_FW_SCSI_CMD_WR_OPCODE)

#define G_FW_SCSI_CMD_WR_OPCODE(x)      \

    (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)


#define S_FW_SCSI_CMD_WR_IMMDLEN        0

#define M_FW_SCSI_CMD_WR_IMMDLEN        0xff

#define V_FW_SCSI_CMD_WR_IMMDLEN(x)     ((x) << S_FW_SCSI_CMD_WR_IMMDLEN)

#define G_FW_SCSI_CMD_WR_IMMDLEN(x)     \

    (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)


#define S_FW_SCSI_CMD_WR_FLOWID         8

#define M_FW_SCSI_CMD_WR_FLOWID         0xfffff

#define V_FW_SCSI_CMD_WR_FLOWID(x)      ((x) << S_FW_SCSI_CMD_WR_FLOWID)

#define G_FW_SCSI_CMD_WR_FLOWID(x)      \

    (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)


#define S_FW_SCSI_CMD_WR_LEN16          0

#define M_FW_SCSI_CMD_WR_LEN16          0xff

#define V_FW_SCSI_CMD_WR_LEN16(x)       ((x) << S_FW_SCSI_CMD_WR_LEN16)

#define G_FW_SCSI_CMD_WR_LEN16(x)       \

    (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)


#define S_FW_SCSI_CMD_WR_CP_EN          6

#define M_FW_SCSI_CMD_WR_CP_EN          0x3

#define V_FW_SCSI_CMD_WR_CP_EN(x)       ((x) << S_FW_SCSI_CMD_WR_CP_EN)

#define G_FW_SCSI_CMD_WR_CP_EN(x)       \

    (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)


#define S_FW_SCSI_CMD_WR_CLASS          4

#define M_FW_SCSI_CMD_WR_CLASS          0x3

#define V_FW_SCSI_CMD_WR_CLASS(x)       ((x) << S_FW_SCSI_CMD_WR_CLASS)

#define G_FW_SCSI_CMD_WR_CLASS(x)       \

    (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)


struct fw_scsi_abrt_cls_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   tmo_val;

        __u8   sub_opcode_to_chk_all_io;

        __u8   r3[4];

        __be64 t_cookie;

};


#define S_FW_SCSI_ABRT_CLS_WR_OPCODE    24

#define M_FW_SCSI_ABRT_CLS_WR_OPCODE    0xff

#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)

#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)


#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN           0

#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN           0xff

#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)        \

    ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)

#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)        \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)


#define S_FW_SCSI_ABRT_CLS_WR_FLOWID    8

#define M_FW_SCSI_ABRT_CLS_WR_FLOWID    0xfffff

#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)

#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)


#define S_FW_SCSI_ABRT_CLS_WR_LEN16     0

#define M_FW_SCSI_ABRT_CLS_WR_LEN16     0xff

#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x)  ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)

#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x)  \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)


#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE        2

#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE        0x3f

#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)     \

    ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)

#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)     \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \

     M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)


#define S_FW_SCSI_ABRT_CLS_WR_UNSOL     1

#define M_FW_SCSI_ABRT_CLS_WR_UNSOL     0x1

#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)  ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)

#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)  \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)

#define F_FW_SCSI_ABRT_CLS_WR_UNSOL     V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)


#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO        0

#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO        0x1

#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)     \

    ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)

#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)     \

    (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \

     M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)

#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO        \

    V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)


struct fw_scsi_tgt_acc_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   r3;

        __u8   use_burst_len;

        union fw_scsi_tgt_acc_priv {

                struct fcoe_tgt_acc_priv {

                        __u8   ctl_pri;

                        __u8   cp_en_class;

                        __u8   r4_lo[2];

                } fcoe;

                struct iscsi_tgt_acc_priv {

                        __u8   r4[4];

                } iscsi;

        } u;

        __be32 burst_len;

        __be32 rel_off;

        __be64 r5;

        __be32 r6;

        __be32 tot_xfer_len;

};


#define S_FW_SCSI_TGT_ACC_WR_OPCODE     24

#define M_FW_SCSI_TGT_ACC_WR_OPCODE     0xff

#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x)  ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)

#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x)  \

    (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)


#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN    0

#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN    0xff

#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)

#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \

    (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)


#define S_FW_SCSI_TGT_ACC_WR_FLOWID     8

#define M_FW_SCSI_TGT_ACC_WR_FLOWID     0xfffff

#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x)  ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)

#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x)  \

    (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)


#define S_FW_SCSI_TGT_ACC_WR_LEN16      0

#define M_FW_SCSI_TGT_ACC_WR_LEN16      0xff

#define V_FW_SCSI_TGT_ACC_WR_LEN16(x)   ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)

#define G_FW_SCSI_TGT_ACC_WR_LEN16(x)   \

    (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)


#define S_FW_SCSI_TGT_ACC_WR_CP_EN      6

#define M_FW_SCSI_TGT_ACC_WR_CP_EN      0x3

#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x)   ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)

#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x)   \

    (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)


#define S_FW_SCSI_TGT_ACC_WR_CLASS      4

#define M_FW_SCSI_TGT_ACC_WR_CLASS      0x3

#define V_FW_SCSI_TGT_ACC_WR_CLASS(x)   ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)

#define G_FW_SCSI_TGT_ACC_WR_CLASS(x)   \

    (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)


struct fw_scsi_tgt_xmit_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   auto_rsp;

        __u8   use_xfer_cnt;

        union fw_scsi_tgt_xmit_priv {

                struct fcoe_tgt_xmit_priv {

                        __u8   ctl_pri;

                        __u8   cp_en_class;

                        __u8   r3_lo[2];

                } fcoe;

                struct iscsi_tgt_xmit_priv {

                        __u8   r3[4];

                } iscsi;

        } u;

        __be32 xfer_cnt;

        __be32 r4;

        __be64 r5;

        __be32 r6;

        __be32 tot_xfer_len;

};


#define S_FW_SCSI_TGT_XMIT_WR_OPCODE    24

#define M_FW_SCSI_TGT_XMIT_WR_OPCODE    0xff

#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)

#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \

    (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)


#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN           0

#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN           0xff

#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)        \

    ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)

#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)        \

    (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)


#define S_FW_SCSI_TGT_XMIT_WR_FLOWID    8

#define M_FW_SCSI_TGT_XMIT_WR_FLOWID    0xfffff

#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)

#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \

    (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)


#define S_FW_SCSI_TGT_XMIT_WR_LEN16     0

#define M_FW_SCSI_TGT_XMIT_WR_LEN16     0xff

#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x)  ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)

#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x)  \

    (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)


#define S_FW_SCSI_TGT_XMIT_WR_CP_EN     6

#define M_FW_SCSI_TGT_XMIT_WR_CP_EN     0x3

#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)  ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)

#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)  \

    (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)


#define S_FW_SCSI_TGT_XMIT_WR_CLASS     4

#define M_FW_SCSI_TGT_XMIT_WR_CLASS     0x3

#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x)  ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)

#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x)  \

    (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)


struct fw_scsi_tgt_rsp_wr {

        __be32 op_immdlen;

        __be32 flowid_len16;

        __be64 cookie;

        __be16 iqid;

        __u8   r3[2];

        union fw_scsi_tgt_rsp_priv {

                struct fcoe_tgt_rsp_priv {

                        __u8   ctl_pri;

                        __u8   cp_en_class;

                        __u8   r4_lo[2];

                } fcoe;

                struct iscsi_tgt_rsp_priv {

                        __u8   r4[4];

                } iscsi;

        } u;

        __u8   r5[8];

};


#define S_FW_SCSI_TGT_RSP_WR_OPCODE     24

#define M_FW_SCSI_TGT_RSP_WR_OPCODE     0xff

#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x)  ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)

#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x)  \

    (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)


#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN    0

#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN    0xff

#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)

#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \

    (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)


#define S_FW_SCSI_TGT_RSP_WR_FLOWID     8

#define M_FW_SCSI_TGT_RSP_WR_FLOWID     0xfffff

#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x)  ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)

#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x)  \

    (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)


#define S_FW_SCSI_TGT_RSP_WR_LEN16      0

#define M_FW_SCSI_TGT_RSP_WR_LEN16      0xff

#define V_FW_SCSI_TGT_RSP_WR_LEN16(x)   ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)

#define G_FW_SCSI_TGT_RSP_WR_LEN16(x)   \

    (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)


#define S_FW_SCSI_TGT_RSP_WR_CP_EN      6

#define M_FW_SCSI_TGT_RSP_WR_CP_EN      0x3

#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x)   ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)

#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x)   \

    (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)


#define S_FW_SCSI_TGT_RSP_WR_CLASS      4

#define M_FW_SCSI_TGT_RSP_WR_CLASS      0x3

#define V_FW_SCSI_TGT_RSP_WR_CLASS(x)   ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)

#define G_FW_SCSI_TGT_RSP_WR_CLASS(x)   \

    (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)


struct fw_pofcoe_tcb_wr {

        __be32 op_compl;

        __be32 equiq_to_len16;

        __be32 r4;

        __be32 xfer_len;

        __be32 tid_to_port;

        __be16 x_id;

        __be16 vlan_id;

        __be64 cookie;

        __be32 s_id;

        __be32 d_id;

        __be32 tag;

        __be16 r6;

        __be16 iqid;

};


#define S_FW_POFCOE_TCB_WR_TID          12

#define M_FW_POFCOE_TCB_WR_TID          0xfffff

#define V_FW_POFCOE_TCB_WR_TID(x)       ((x) << S_FW_POFCOE_TCB_WR_TID)

#define G_FW_POFCOE_TCB_WR_TID(x)       \

    (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)


#define S_FW_POFCOE_TCB_WR_ALLOC        4

#define M_FW_POFCOE_TCB_WR_ALLOC        0x1

#define V_FW_POFCOE_TCB_WR_ALLOC(x)     ((x) << S_FW_POFCOE_TCB_WR_ALLOC)

#define G_FW_POFCOE_TCB_WR_ALLOC(x)     \

    (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)

#define F_FW_POFCOE_TCB_WR_ALLOC        V_FW_POFCOE_TCB_WR_ALLOC(1U)


#define S_FW_POFCOE_TCB_WR_FREE         3

#define M_FW_POFCOE_TCB_WR_FREE         0x1

#define V_FW_POFCOE_TCB_WR_FREE(x)      ((x) << S_FW_POFCOE_TCB_WR_FREE)

#define G_FW_POFCOE_TCB_WR_FREE(x)      \

    (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)

#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U)


#define S_FW_POFCOE_TCB_WR_PORT         0

#define M_FW_POFCOE_TCB_WR_PORT         0x7

#define V_FW_POFCOE_TCB_WR_PORT(x)      ((x) << S_FW_POFCOE_TCB_WR_PORT)

#define G_FW_POFCOE_TCB_WR_PORT(x)      \

    (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)


struct fw_pofcoe_ulptx_wr {

        __be32 op_pkd;

        __be32 equiq_to_len16;

        __u64  cookie;

};


/*******************************************************************

 *  T10 DIF related definition

 *******************************************************************/

struct fw_tx_pi_header {

        __be16 op_to_inline;

        __u8   pi_interval_tag_type;

        __u8   num_pi;

        __be32 pi_start4_pi_end4;

        __u8   tag_gen_enabled_pkd;

        __u8   num_pi_dsg;

        __be16 app_tag;

        __be32 ref_tag;

};


#define S_FW_TX_PI_HEADER_OP    8

#define M_FW_TX_PI_HEADER_OP    0xff

#define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP)

#define G_FW_TX_PI_HEADER_OP(x) \

    (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)


#define S_FW_TX_PI_HEADER_ULPTXMORE     7

#define M_FW_TX_PI_HEADER_ULPTXMORE     0x1

#define V_FW_TX_PI_HEADER_ULPTXMORE(x)  ((x) << S_FW_TX_PI_HEADER_ULPTXMORE)

#define G_FW_TX_PI_HEADER_ULPTXMORE(x)  \

    (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)

#define F_FW_TX_PI_HEADER_ULPTXMORE     V_FW_TX_PI_HEADER_ULPTXMORE(1U)


#define S_FW_TX_PI_HEADER_PI_CONTROL    4

#define M_FW_TX_PI_HEADER_PI_CONTROL    0x7

#define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL)

#define G_FW_TX_PI_HEADER_PI_CONTROL(x) \

    (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)


#define S_FW_TX_PI_HEADER_GUARD_TYPE    2

#define M_FW_TX_PI_HEADER_GUARD_TYPE    0x1

#define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)

#define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \

    (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)

#define F_FW_TX_PI_HEADER_GUARD_TYPE    V_FW_TX_PI_HEADER_GUARD_TYPE(1U)


#define S_FW_TX_PI_HEADER_VALIDATE      1

#define M_FW_TX_PI_HEADER_VALIDATE      0x1

#define V_FW_TX_PI_HEADER_VALIDATE(x)   ((x) << S_FW_TX_PI_HEADER_VALIDATE)

#define G_FW_TX_PI_HEADER_VALIDATE(x)   \

    (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)

#define F_FW_TX_PI_HEADER_VALIDATE      V_FW_TX_PI_HEADER_VALIDATE(1U)


#define S_FW_TX_PI_HEADER_INLINE        0

#define M_FW_TX_PI_HEADER_INLINE        0x1

#define V_FW_TX_PI_HEADER_INLINE(x)     ((x) << S_FW_TX_PI_HEADER_INLINE)

#define G_FW_TX_PI_HEADER_INLINE(x)     \

    (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)

#define F_FW_TX_PI_HEADER_INLINE        V_FW_TX_PI_HEADER_INLINE(1U)


#define S_FW_TX_PI_HEADER_PI_INTERVAL           7

#define M_FW_TX_PI_HEADER_PI_INTERVAL           0x1

#define V_FW_TX_PI_HEADER_PI_INTERVAL(x)        \

    ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)

#define G_FW_TX_PI_HEADER_PI_INTERVAL(x)        \

    (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)

#define F_FW_TX_PI_HEADER_PI_INTERVAL   V_FW_TX_PI_HEADER_PI_INTERVAL(1U)


#define S_FW_TX_PI_HEADER_TAG_TYPE      5

#define M_FW_TX_PI_HEADER_TAG_TYPE      0x3

#define V_FW_TX_PI_HEADER_TAG_TYPE(x)   ((x) << S_FW_TX_PI_HEADER_TAG_TYPE)

#define G_FW_TX_PI_HEADER_TAG_TYPE(x)   \

    (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)


#define S_FW_TX_PI_HEADER_PI_START4     22

#define M_FW_TX_PI_HEADER_PI_START4     0x3ff

#define V_FW_TX_PI_HEADER_PI_START4(x)  ((x) << S_FW_TX_PI_HEADER_PI_START4)

#define G_FW_TX_PI_HEADER_PI_START4(x)  \

    (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)


#define S_FW_TX_PI_HEADER_PI_END4       0

#define M_FW_TX_PI_HEADER_PI_END4       0x3fffff

#define V_FW_TX_PI_HEADER_PI_END4(x)    ((x) << S_FW_TX_PI_HEADER_PI_END4)

#define G_FW_TX_PI_HEADER_PI_END4(x)    \

    (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)


#define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED       6

#define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED       0x3

#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)    \

    ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)

#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)    \

    (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \

     M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)


enum fw_pi_error_type {

        FW_PI_ERROR_GUARD_CHECK_FAILED = 0,

};


struct fw_pi_error {

        __be32 err_type_pkd;

        __be32 flowid_len16;

        __be16 r2;

        __be16 app_tag;

        __be32 ref_tag;

        __be32  pisc[4];

};


#define S_FW_PI_ERROR_ERR_TYPE          24

#define M_FW_PI_ERROR_ERR_TYPE          0xff

#define V_FW_PI_ERROR_ERR_TYPE(x)       ((x) << S_FW_PI_ERROR_ERR_TYPE)

#define G_FW_PI_ERROR_ERR_TYPE(x)       \

    (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)


struct fw_tlstx_data_wr {

        __be32 op_to_immdlen;

        __be32 flowid_len16;

        __be32 plen;

        __be32 lsodisable_to_flags;

        __be32 r5;

        __be32 ctxloc_to_exp;

        __be16 mfs;

        __be16 adjustedplen_pkd;

        __be16 expinplenmax_pkd;

        __u8   pdusinplenmax_pkd;

        __u8   r10;

};


#define S_FW_TLSTX_DATA_WR_OPCODE       24

#define M_FW_TLSTX_DATA_WR_OPCODE       0xff

#define V_FW_TLSTX_DATA_WR_OPCODE(x)    ((x) << S_FW_TLSTX_DATA_WR_OPCODE)

#define G_FW_TLSTX_DATA_WR_OPCODE(x)    \

    (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)


#define S_FW_TLSTX_DATA_WR_COMPL        21

#define M_FW_TLSTX_DATA_WR_COMPL        0x1

#define V_FW_TLSTX_DATA_WR_COMPL(x)     ((x) << S_FW_TLSTX_DATA_WR_COMPL)

#define G_FW_TLSTX_DATA_WR_COMPL(x)     \

    (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)

#define F_FW_TLSTX_DATA_WR_COMPL        V_FW_TLSTX_DATA_WR_COMPL(1U)


#define S_FW_TLSTX_DATA_WR_IMMDLEN      0

#define M_FW_TLSTX_DATA_WR_IMMDLEN      0xff

#define V_FW_TLSTX_DATA_WR_IMMDLEN(x)   ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)

#define G_FW_TLSTX_DATA_WR_IMMDLEN(x)   \

    (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)


#define S_FW_TLSTX_DATA_WR_FLOWID       8

#define M_FW_TLSTX_DATA_WR_FLOWID       0xfffff

#define V_FW_TLSTX_DATA_WR_FLOWID(x)    ((x) << S_FW_TLSTX_DATA_WR_FLOWID)

#define G_FW_TLSTX_DATA_WR_FLOWID(x)    \

    (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)


#define S_FW_TLSTX_DATA_WR_LEN16        0

#define M_FW_TLSTX_DATA_WR_LEN16        0xff

#define V_FW_TLSTX_DATA_WR_LEN16(x)     ((x) << S_FW_TLSTX_DATA_WR_LEN16)

#define G_FW_TLSTX_DATA_WR_LEN16(x)     \

    (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)


#define S_FW_TLSTX_DATA_WR_LSODISABLE   31

#define M_FW_TLSTX_DATA_WR_LSODISABLE   0x1

#define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \

    ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)

#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \

    (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)

#define F_FW_TLSTX_DATA_WR_LSODISABLE   V_FW_TLSTX_DATA_WR_LSODISABLE(1U)


#define S_FW_TLSTX_DATA_WR_ALIGNPLD     30

#define M_FW_TLSTX_DATA_WR_ALIGNPLD     0x1

#define V_FW_TLSTX_DATA_WR_ALIGNPLD(x)  ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)

#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x)  \

    (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)

#define F_FW_TLSTX_DATA_WR_ALIGNPLD     V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)


#define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29

#define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1

#define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \

    ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)

#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \

    (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \

     M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)

#define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)


#define S_FW_TLSTX_DATA_WR_FLAGS        0

#define M_FW_TLSTX_DATA_WR_FLAGS        0xfffffff

#define V_FW_TLSTX_DATA_WR_FLAGS(x)     ((x) << S_FW_TLSTX_DATA_WR_FLAGS)

#define G_FW_TLSTX_DATA_WR_FLAGS(x)     \

    (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)


#define S_FW_TLSTX_DATA_WR_CTXLOC       30

#define M_FW_TLSTX_DATA_WR_CTXLOC       0x3

#define V_FW_TLSTX_DATA_WR_CTXLOC(x)    ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)

#define G_FW_TLSTX_DATA_WR_CTXLOC(x)    \

    (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)


#define S_FW_TLSTX_DATA_WR_IVDSGL       29

#define M_FW_TLSTX_DATA_WR_IVDSGL       0x1

#define V_FW_TLSTX_DATA_WR_IVDSGL(x)    ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)

#define G_FW_TLSTX_DATA_WR_IVDSGL(x)    \

    (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)

#define F_FW_TLSTX_DATA_WR_IVDSGL       V_FW_TLSTX_DATA_WR_IVDSGL(1U)


#define S_FW_TLSTX_DATA_WR_KEYSIZE      24

#define M_FW_TLSTX_DATA_WR_KEYSIZE      0x1f

#define V_FW_TLSTX_DATA_WR_KEYSIZE(x)   ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)

#define G_FW_TLSTX_DATA_WR_KEYSIZE(x)   \

    (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)


#define S_FW_TLSTX_DATA_WR_NUMIVS       14

#define M_FW_TLSTX_DATA_WR_NUMIVS       0xff

#define V_FW_TLSTX_DATA_WR_NUMIVS(x)    ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)

#define G_FW_TLSTX_DATA_WR_NUMIVS(x)    \

    (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)


#define S_FW_TLSTX_DATA_WR_EXP          0

#define M_FW_TLSTX_DATA_WR_EXP          0x3fff

#define V_FW_TLSTX_DATA_WR_EXP(x)       ((x) << S_FW_TLSTX_DATA_WR_EXP)

#define G_FW_TLSTX_DATA_WR_EXP(x)       \

    (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)


#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1

#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff

#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \

    ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)

#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \

    (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \

     M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)


#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4

#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff

#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \

    ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)

#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \

    (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \

     M_FW_TLSTX_DATA_WR_EXPINPLENMAX)


#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2

#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f

#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \

    ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)

#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \

    (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \

     M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)


struct fw_crypto_lookaside_wr {

        __be32 op_to_cctx_size;

        __be32 len16_pkd;

        __be32 session_id;

        __be32 rx_chid_to_rx_q_id;

        __be32 key_addr;

        __be32 pld_size_hash_size;

        __be64 cookie;

};


#define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24

#define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff

#define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)

#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \

     M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)


#define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23

#define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1

#define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)

#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \

     M_FW_CRYPTO_LOOKASIDE_WR_COMPL)

#define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)


#define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15

#define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff

#define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)

#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \

     M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)


#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5

#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3

#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)

#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \

     M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)


#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0

#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f

#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)

#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \

     M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)


#define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0

#define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff

#define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)

#define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \

     M_FW_CRYPTO_LOOKASIDE_WR_LEN16)


#define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29

#define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3

#define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)

#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \

     M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)


#define S_FW_CRYPTO_LOOKASIDE_WR_LCB  27

#define M_FW_CRYPTO_LOOKASIDE_WR_LCB  0x3

#define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)

#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)


#define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25

#define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3

#define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)

#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \

     M_FW_CRYPTO_LOOKASIDE_WR_PHASH)


#define S_FW_CRYPTO_LOOKASIDE_WR_IV   23

#define M_FW_CRYPTO_LOOKASIDE_WR_IV   0x3

#define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)

#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)


#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX  15

#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX  0xff

#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \

        ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)

#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \

        (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\

          M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)


#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10

#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3

#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)

#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \

     M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)


#define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0

#define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff

#define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)

#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \

     M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)


#define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24

#define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff

#define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)

#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \

     M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)


#define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17

#define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f

#define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \

    ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)

#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \

    (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \

     M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)


struct fw_tls_tunnel_ofld_wr {

        __be32 op_compl;

        __be32 flowid_len16;

        __be32 plen;

        __be32 r4;

};


/******************************************************************************

 *  C O M M A N D s

 *********************/


/*

 * The maximum length of time, in miliseconds, that we expect any firmware

 * command to take to execute and return a reply to the host.  The RESET

 * and INITIALIZE commands can take a fair amount of time to execute but

 * most execute in far less time than this maximum.  This constant is used

 * by host software to determine how long to wait for a firmware command

 * reply before declaring the firmware as dead/unreachable ...

 */

#define FW_CMD_MAX_TIMEOUT      10000


/*

 * If a host driver does a HELLO and discovers that there's already a MASTER

 * selected, we may have to wait for that MASTER to finish issuing RESET,

 * configuration and INITIALIZE commands.  Also, there's a possibility that

 * our own HELLO may get lost if it happens right as the MASTER is issuign a

 * RESET command, so we need to be willing to make a few retries of our HELLO.

 */

#define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)

#define FW_CMD_HELLO_RETRIES    3


enum fw_cmd_opcodes {

        FW_LDST_CMD                    = 0x01,

        FW_RESET_CMD                   = 0x03,

        FW_HELLO_CMD                   = 0x04,

        FW_BYE_CMD                     = 0x05,

        FW_INITIALIZE_CMD              = 0x06,

        FW_CAPS_CONFIG_CMD             = 0x07,

        FW_PARAMS_CMD                  = 0x08,

        FW_PFVF_CMD                    = 0x09,

        FW_IQ_CMD                      = 0x10,

        FW_EQ_MNGT_CMD                 = 0x11,

        FW_EQ_ETH_CMD                  = 0x12,

        FW_EQ_CTRL_CMD                 = 0x13,

        FW_EQ_OFLD_CMD                 = 0x21,

        FW_VI_CMD                      = 0x14,

        FW_VI_MAC_CMD                  = 0x15,

        FW_VI_RXMODE_CMD               = 0x16,

        FW_VI_ENABLE_CMD               = 0x17,

        FW_VI_STATS_CMD                = 0x1a,

        FW_ACL_MAC_CMD                 = 0x18,

        FW_ACL_VLAN_CMD                = 0x19,

        FW_PORT_CMD                    = 0x1b,

        FW_PORT_STATS_CMD              = 0x1c,

        FW_PORT_LB_STATS_CMD           = 0x1d,

        FW_PORT_TRACE_CMD              = 0x1e,

        FW_PORT_TRACE_MMAP_CMD         = 0x1f,

        FW_RSS_IND_TBL_CMD             = 0x20,

        FW_RSS_GLB_CONFIG_CMD          = 0x22,

        FW_RSS_VI_CONFIG_CMD           = 0x23,

        FW_SCHED_CMD                   = 0x24,

        FW_DEVLOG_CMD                  = 0x25,

        FW_WATCHDOG_CMD                = 0x27,

        FW_CLIP_CMD                    = 0x28,

        FW_CLIP2_CMD                   = 0x29,

        FW_CHNET_IFACE_CMD             = 0x26,

        FW_FCOE_RES_INFO_CMD           = 0x31,

        FW_FCOE_LINK_CMD               = 0x32,

        FW_FCOE_VNP_CMD                = 0x33,

        FW_FCOE_SPARAMS_CMD            = 0x35,

        FW_FCOE_STATS_CMD              = 0x37,

        FW_FCOE_FCF_CMD                = 0x38,

        FW_DCB_IEEE_CMD                = 0x3a,

        FW_DIAG_CMD                    = 0x3d,

        FW_PTP_CMD                     = 0x3e,

        FW_HMA_CMD                     = 0x3f,

        FW_LASTC2E_CMD                 = 0x40,

        FW_ERROR_CMD                   = 0x80,

        FW_DEBUG_CMD                   = 0x81,

};


enum fw_cmd_cap {

        FW_CMD_CAP_PF                  = 0x01,

        FW_CMD_CAP_DMAQ                = 0x02,

        FW_CMD_CAP_PORT                = 0x04,

        FW_CMD_CAP_PORTPROMISC         = 0x08,

        FW_CMD_CAP_PORTSTATS           = 0x10,

        FW_CMD_CAP_VF                  = 0x80,

};


/*

 * Generic command header flit0

 */

struct fw_cmd_hdr {

        __be32 hi;

        __be32 lo;

};


#define S_FW_CMD_OP             24

#define M_FW_CMD_OP             0xff

#define V_FW_CMD_OP(x)          ((x) << S_FW_CMD_OP)

#define G_FW_CMD_OP(x)          (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)


#define S_FW_CMD_REQUEST        23

#define M_FW_CMD_REQUEST        0x1

#define V_FW_CMD_REQUEST(x)     ((x) << S_FW_CMD_REQUEST)

#define G_FW_CMD_REQUEST(x)     (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)

#define F_FW_CMD_REQUEST        V_FW_CMD_REQUEST(1U)


#define S_FW_CMD_READ           22

#define M_FW_CMD_READ           0x1

#define V_FW_CMD_READ(x)        ((x) << S_FW_CMD_READ)

#define G_FW_CMD_READ(x)        (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)

#define F_FW_CMD_READ           V_FW_CMD_READ(1U)


#define S_FW_CMD_WRITE          21

#define M_FW_CMD_WRITE          0x1

#define V_FW_CMD_WRITE(x)       ((x) << S_FW_CMD_WRITE)

#define G_FW_CMD_WRITE(x)       (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)

#define F_FW_CMD_WRITE          V_FW_CMD_WRITE(1U)


#define S_FW_CMD_EXEC           20

#define M_FW_CMD_EXEC           0x1

#define V_FW_CMD_EXEC(x)        ((x) << S_FW_CMD_EXEC)

#define G_FW_CMD_EXEC(x)        (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)

#define F_FW_CMD_EXEC           V_FW_CMD_EXEC(1U)


#define S_FW_CMD_RAMASK         20

#define M_FW_CMD_RAMASK         0xf

#define V_FW_CMD_RAMASK(x)      ((x) << S_FW_CMD_RAMASK)

#define G_FW_CMD_RAMASK(x)      (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)


#define S_FW_CMD_RETVAL         8

#define M_FW_CMD_RETVAL         0xff

#define V_FW_CMD_RETVAL(x)      ((x) << S_FW_CMD_RETVAL)

#define G_FW_CMD_RETVAL(x)      (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)


#define S_FW_CMD_LEN16          0

#define M_FW_CMD_LEN16          0xff

#define V_FW_CMD_LEN16(x)       ((x) << S_FW_CMD_LEN16)

#define G_FW_CMD_LEN16(x)       (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)


#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)


/*

 *      address spaces

 */

enum fw_ldst_addrspc {

        FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,

        FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,

        FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,

        FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,

        FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,

        FW_LDST_ADDRSPC_TP_PIO    = 0x0010,

        FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,

        FW_LDST_ADDRSPC_TP_MIB    = 0x0012,

        FW_LDST_ADDRSPC_MDIO      = 0x0018,

        FW_LDST_ADDRSPC_MPS       = 0x0020,

        FW_LDST_ADDRSPC_FUNC      = 0x0028,

        FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,

        FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */

        FW_LDST_ADDRSPC_LE        = 0x0030,

        FW_LDST_ADDRSPC_I2C       = 0x0038,

        FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,

        FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,

        FW_LDST_ADDRSPC_PCIE_PHY  = 0x0042,

        FW_LDST_ADDRSPC_CIM_Q     = 0x0048,

};


/*

 *      MDIO VSC8634 register access control field

 */

enum fw_ldst_mdio_vsc8634_aid {

        FW_LDST_MDIO_VS_STANDARD,

        FW_LDST_MDIO_VS_EXTENDED,

        FW_LDST_MDIO_VS_GPIO

};


enum fw_ldst_mps_fid {

        FW_LDST_MPS_ATRB,

        FW_LDST_MPS_RPLC

};


enum fw_ldst_func_access_ctl {

        FW_LDST_FUNC_ACC_CTL_VIID,

        FW_LDST_FUNC_ACC_CTL_FID

};


enum fw_ldst_func_mod_index {

        FW_LDST_FUNC_MPS

};


struct fw_ldst_cmd {

        __be32 op_to_addrspace;

        __be32 cycles_to_len16;

        union fw_ldst {

                struct fw_ldst_addrval {

                        __be32 addr;

                        __be32 val;

                } addrval;

                struct fw_ldst_idctxt {

                        __be32 physid;

                        __be32 msg_ctxtflush;

                        __be32 ctxt_data7;

                        __be32 ctxt_data6;

                        __be32 ctxt_data5;

                        __be32 ctxt_data4;

                        __be32 ctxt_data3;

                        __be32 ctxt_data2;

                        __be32 ctxt_data1;

                        __be32 ctxt_data0;

                } idctxt;

                struct fw_ldst_mdio {

                        __be16 paddr_mmd;

                        __be16 raddr;

                        __be16 vctl;

                        __be16 rval;

                } mdio;

                struct fw_ldst_cim_rq {

                        __u8   req_first64[8];

                        __u8   req_second64[8];

                        __u8   resp_first64[8];

                        __u8   resp_second64[8];

                        __be32 r3[2];

                } cim_rq;

                union fw_ldst_mps {

                        struct fw_ldst_mps_rplc {

                                __be16 fid_idx;

                                __be16 rplcpf_pkd;

                                __be32 rplc255_224;

                                __be32 rplc223_192;

                                __be32 rplc191_160;

                                __be32 rplc159_128;

                                __be32 rplc127_96;

                                __be32 rplc95_64;

                                __be32 rplc63_32;

                                __be32 rplc31_0;

                        } rplc;

                        struct fw_ldst_mps_atrb {

                                __be16 fid_mpsid;

                                __be16 r2[3];

                                __be32 r3[2];

                                __be32 r4;

                                __be32 atrb;

                                __be16 vlan[16];

                        } atrb;

                } mps;

                struct fw_ldst_func {

                        __u8   access_ctl;

                        __u8   mod_index;

                        __be16 ctl_id;

                        __be32 offset;

                        __be64 data0;

                        __be64 data1;

                } func;

                struct fw_ldst_pcie {

                        __u8   ctrl_to_fn;

                        __u8   bnum;

                        __u8   r;

                        __u8   ext_r;

                        __u8   select_naccess;

                        __u8   pcie_fn;

                        __be16 nset_pkd;

                        __be32 data[12];

                } pcie;

                struct fw_ldst_i2c_deprecated {

                        __u8   pid_pkd;

                        __u8   base;

                        __u8   boffset;

                        __u8   data;

                        __be32 r9;

                } i2c_deprecated;

                struct fw_ldst_i2c {

                        __u8   pid;

                        __u8   did;

                        __u8   boffset;

                        __u8   blen;

                        __be32 r9;

                        __u8   data[48];

                } i2c;

                struct fw_ldst_le {

                        __be32 index;

                        __be32 r9;

                        __u8   val[33];

                        __u8   r11[7];

                } le;

        } u;

};


#define S_FW_LDST_CMD_ADDRSPACE         0

#define M_FW_LDST_CMD_ADDRSPACE         0xff

#define V_FW_LDST_CMD_ADDRSPACE(x)      ((x) << S_FW_LDST_CMD_ADDRSPACE)

#define G_FW_LDST_CMD_ADDRSPACE(x)      \

    (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)


#define S_FW_LDST_CMD_CYCLES            16

#define M_FW_LDST_CMD_CYCLES            0xffff

#define V_FW_LDST_CMD_CYCLES(x)         ((x) << S_FW_LDST_CMD_CYCLES)

#define G_FW_LDST_CMD_CYCLES(x)         \

    (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)


#define S_FW_LDST_CMD_MSG               31

#define M_FW_LDST_CMD_MSG               0x1

#define V_FW_LDST_CMD_MSG(x)            ((x) << S_FW_LDST_CMD_MSG)

#define G_FW_LDST_CMD_MSG(x)            \

    (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)

#define F_FW_LDST_CMD_MSG               V_FW_LDST_CMD_MSG(1U)


#define S_FW_LDST_CMD_CTXTFLUSH         30

#define M_FW_LDST_CMD_CTXTFLUSH         0x1

#define V_FW_LDST_CMD_CTXTFLUSH(x)      ((x) << S_FW_LDST_CMD_CTXTFLUSH)

#define G_FW_LDST_CMD_CTXTFLUSH(x)      \

    (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)

#define F_FW_LDST_CMD_CTXTFLUSH         V_FW_LDST_CMD_CTXTFLUSH(1U)


#define S_FW_LDST_CMD_PADDR             8

#define M_FW_LDST_CMD_PADDR             0x1f

#define V_FW_LDST_CMD_PADDR(x)          ((x) << S_FW_LDST_CMD_PADDR)

#define G_FW_LDST_CMD_PADDR(x)          \

    (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)


#define S_FW_LDST_CMD_MMD               0

#define M_FW_LDST_CMD_MMD               0x1f

#define V_FW_LDST_CMD_MMD(x)            ((x) << S_FW_LDST_CMD_MMD)

#define G_FW_LDST_CMD_MMD(x)            \

    (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)


#define S_FW_LDST_CMD_FID               15

#define M_FW_LDST_CMD_FID               0x1

#define V_FW_LDST_CMD_FID(x)            ((x) << S_FW_LDST_CMD_FID)

#define G_FW_LDST_CMD_FID(x)            \

    (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)

#define F_FW_LDST_CMD_FID               V_FW_LDST_CMD_FID(1U)


#define S_FW_LDST_CMD_IDX               0

#define M_FW_LDST_CMD_IDX               0x7fff

#define V_FW_LDST_CMD_IDX(x)            ((x) << S_FW_LDST_CMD_IDX)

#define G_FW_LDST_CMD_IDX(x)            \

    (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)


#define S_FW_LDST_CMD_RPLCPF            0

#define M_FW_LDST_CMD_RPLCPF            0xff

#define V_FW_LDST_CMD_RPLCPF(x)         ((x) << S_FW_LDST_CMD_RPLCPF)

#define G_FW_LDST_CMD_RPLCPF(x)         \

    (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)


#define S_FW_LDST_CMD_MPSID             0

#define M_FW_LDST_CMD_MPSID             0x7fff

#define V_FW_LDST_CMD_MPSID(x)          ((x) << S_FW_LDST_CMD_MPSID)

#define G_FW_LDST_CMD_MPSID(x)          \

    (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)


#define S_FW_LDST_CMD_CTRL              7

#define M_FW_LDST_CMD_CTRL              0x1

#define V_FW_LDST_CMD_CTRL(x)           ((x) << S_FW_LDST_CMD_CTRL)

#define G_FW_LDST_CMD_CTRL(x)           \

    (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)

#define F_FW_LDST_CMD_CTRL              V_FW_LDST_CMD_CTRL(1U)


#define S_FW_LDST_CMD_LC                4

#define M_FW_LDST_CMD_LC                0x1

#define V_FW_LDST_CMD_LC(x)             ((x) << S_FW_LDST_CMD_LC)

#define G_FW_LDST_CMD_LC(x)             \

    (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)

#define F_FW_LDST_CMD_LC                V_FW_LDST_CMD_LC(1U)


#define S_FW_LDST_CMD_AI                3

#define M_FW_LDST_CMD_AI                0x1

#define V_FW_LDST_CMD_AI(x)             ((x) << S_FW_LDST_CMD_AI)

#define G_FW_LDST_CMD_AI(x)             \

    (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)

#define F_FW_LDST_CMD_AI                V_FW_LDST_CMD_AI(1U)


#define S_FW_LDST_CMD_FN                0

#define M_FW_LDST_CMD_FN                0x7

#define V_FW_LDST_CMD_FN(x)             ((x) << S_FW_LDST_CMD_FN)

#define G_FW_LDST_CMD_FN(x)             \

    (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)


#define S_FW_LDST_CMD_SELECT            4

#define M_FW_LDST_CMD_SELECT            0xf

#define V_FW_LDST_CMD_SELECT(x)         ((x) << S_FW_LDST_CMD_SELECT)

#define G_FW_LDST_CMD_SELECT(x)         \

    (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)


#define S_FW_LDST_CMD_NACCESS           0

#define M_FW_LDST_CMD_NACCESS           0xf

#define V_FW_LDST_CMD_NACCESS(x)        ((x) << S_FW_LDST_CMD_NACCESS)

#define G_FW_LDST_CMD_NACCESS(x)        \

    (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)


#define S_FW_LDST_CMD_NSET              14

#define M_FW_LDST_CMD_NSET              0x3

#define V_FW_LDST_CMD_NSET(x)           ((x) << S_FW_LDST_CMD_NSET)

#define G_FW_LDST_CMD_NSET(x)           \

    (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)


#define S_FW_LDST_CMD_PID               6

#define M_FW_LDST_CMD_PID               0x3

#define V_FW_LDST_CMD_PID(x)            ((x) << S_FW_LDST_CMD_PID)

#define G_FW_LDST_CMD_PID(x)            \

    (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)


struct fw_reset_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        __be32 val;

        __be32 halt_pkd;

};


#define S_FW_RESET_CMD_HALT             31

#define M_FW_RESET_CMD_HALT             0x1

#define V_FW_RESET_CMD_HALT(x)          ((x) << S_FW_RESET_CMD_HALT)

#define G_FW_RESET_CMD_HALT(x)          \

    (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)

#define F_FW_RESET_CMD_HALT             V_FW_RESET_CMD_HALT(1U)


enum {

        FW_HELLO_CMD_STAGE_OS           = 0,

        FW_HELLO_CMD_STAGE_PREOS0       = 1,

        FW_HELLO_CMD_STAGE_PREOS1       = 2,

        FW_HELLO_CMD_STAGE_POSTOS       = 3,

};


struct fw_hello_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        __be32 err_to_clearinit;

        __be32 fwrev;

};


#define S_FW_HELLO_CMD_ERR              31

#define M_FW_HELLO_CMD_ERR              0x1

#define V_FW_HELLO_CMD_ERR(x)           ((x) << S_FW_HELLO_CMD_ERR)

#define G_FW_HELLO_CMD_ERR(x)           \

    (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)

#define F_FW_HELLO_CMD_ERR              V_FW_HELLO_CMD_ERR(1U)


#define S_FW_HELLO_CMD_INIT             30

#define M_FW_HELLO_CMD_INIT             0x1

#define V_FW_HELLO_CMD_INIT(x)          ((x) << S_FW_HELLO_CMD_INIT)

#define G_FW_HELLO_CMD_INIT(x)          \

    (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)

#define F_FW_HELLO_CMD_INIT             V_FW_HELLO_CMD_INIT(1U)


#define S_FW_HELLO_CMD_MASTERDIS        29

#define M_FW_HELLO_CMD_MASTERDIS        0x1

#define V_FW_HELLO_CMD_MASTERDIS(x)     ((x) << S_FW_HELLO_CMD_MASTERDIS)

#define G_FW_HELLO_CMD_MASTERDIS(x)     \

    (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)

#define F_FW_HELLO_CMD_MASTERDIS        V_FW_HELLO_CMD_MASTERDIS(1U)


#define S_FW_HELLO_CMD_MASTERFORCE      28

#define M_FW_HELLO_CMD_MASTERFORCE      0x1

#define V_FW_HELLO_CMD_MASTERFORCE(x)   ((x) << S_FW_HELLO_CMD_MASTERFORCE)

#define G_FW_HELLO_CMD_MASTERFORCE(x)   \

    (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)

#define F_FW_HELLO_CMD_MASTERFORCE      V_FW_HELLO_CMD_MASTERFORCE(1U)


#define S_FW_HELLO_CMD_MBMASTER         24

#define M_FW_HELLO_CMD_MBMASTER         0xf

#define V_FW_HELLO_CMD_MBMASTER(x)      ((x) << S_FW_HELLO_CMD_MBMASTER)

#define G_FW_HELLO_CMD_MBMASTER(x)      \

    (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)


#define S_FW_HELLO_CMD_MBASYNCNOTINT    23

#define M_FW_HELLO_CMD_MBASYNCNOTINT    0x1

#define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)

#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \

    (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)

#define F_FW_HELLO_CMD_MBASYNCNOTINT    V_FW_HELLO_CMD_MBASYNCNOTINT(1U)


#define S_FW_HELLO_CMD_MBASYNCNOT       20

#define M_FW_HELLO_CMD_MBASYNCNOT       0x7

#define V_FW_HELLO_CMD_MBASYNCNOT(x)    ((x) << S_FW_HELLO_CMD_MBASYNCNOT)

#define G_FW_HELLO_CMD_MBASYNCNOT(x)    \

    (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)


#define S_FW_HELLO_CMD_STAGE            17

#define M_FW_HELLO_CMD_STAGE            0x7

#define V_FW_HELLO_CMD_STAGE(x)         ((x) << S_FW_HELLO_CMD_STAGE)

#define G_FW_HELLO_CMD_STAGE(x)         \

    (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)


#define S_FW_HELLO_CMD_CLEARINIT        16

#define M_FW_HELLO_CMD_CLEARINIT        0x1

#define V_FW_HELLO_CMD_CLEARINIT(x)     ((x) << S_FW_HELLO_CMD_CLEARINIT)

#define G_FW_HELLO_CMD_CLEARINIT(x)     \

    (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)

#define F_FW_HELLO_CMD_CLEARINIT        V_FW_HELLO_CMD_CLEARINIT(1U)


struct fw_bye_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        __be64 r3;

};


struct fw_initialize_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        __be64 r3;

};


enum fw_caps_config_hm {

        FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,

        FW_CAPS_CONFIG_HM_PL            = 0x00000002,

        FW_CAPS_CONFIG_HM_SGE           = 0x00000004,

        FW_CAPS_CONFIG_HM_CIM           = 0x00000008,

        FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,

        FW_CAPS_CONFIG_HM_TP            = 0x00000020,

        FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,

        FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,

        FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,

        FW_CAPS_CONFIG_HM_MC            = 0x00000200,

        FW_CAPS_CONFIG_HM_LE            = 0x00000400,

        FW_CAPS_CONFIG_HM_MPS           = 0x00000800,

        FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,

        FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,

        FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,

        FW_CAPS_CONFIG_HM_MI            = 0x00008000,

        FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,

        FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,

        FW_CAPS_CONFIG_HM_SMB           = 0x00040000,

        FW_CAPS_CONFIG_HM_MA            = 0x00080000,

        FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,

        FW_CAPS_CONFIG_HM_PMU           = 0x00200000,

        FW_CAPS_CONFIG_HM_UART          = 0x00400000,

        FW_CAPS_CONFIG_HM_SF            = 0x00800000,

};


/*

 * The VF Register Map.

 *

 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local

 * bus module (PL) and CPU Interface Module (CIM) components are mapped via

 * the Slice to Module Map Table (see below) in the Physical Function Register

 * Map.  The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base

 * and Offset registers in the PF Register Map.  The MBDATA base address is

 * quite constrained as it determines the Mailbox Data addresses for both PFs

 * and VFs, and therefore must fit in both the VF and PF Register Maps without

 * overlapping other registers.

 */

#define FW_T4VF_SGE_BASE_ADDR      0x0000

#define FW_T4VF_MPS_BASE_ADDR      0x0100

#define FW_T4VF_PL_BASE_ADDR       0x0200

#define FW_T4VF_MBDATA_BASE_ADDR   0x0240

#define FW_T6VF_MBDATA_BASE_ADDR   0x0280 /* aligned to mbox size 128B */

#define FW_T4VF_CIM_BASE_ADDR      0x0300


#define FW_T4VF_REGMAP_START       0x0000

#define FW_T4VF_REGMAP_SIZE        0x0400


enum fw_caps_config_nbm {

        FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,

        FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,

};


enum fw_caps_config_link {

        FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,

        FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,

        FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,

};


enum fw_caps_config_switch {

        FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,

        FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,

};


enum fw_caps_config_nic {

        FW_CAPS_CONFIG_NIC              = 0x00000001,

        FW_CAPS_CONFIG_NIC_VM           = 0x00000002,

        FW_CAPS_CONFIG_NIC_IDS          = 0x00000004,

        FW_CAPS_CONFIG_NIC_UM           = 0x00000008,

        FW_CAPS_CONFIG_NIC_UM_ISGL      = 0x00000010,

        FW_CAPS_CONFIG_NIC_HASHFILTER   = 0x00000020,

        FW_CAPS_CONFIG_NIC_ETHOFLD      = 0x00000040,

};


enum fw_caps_config_toe {

        FW_CAPS_CONFIG_TOE              = 0x00000001,

};


enum fw_caps_config_rdma {

        FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,

        FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,

};


enum fw_caps_config_iscsi {

        FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,

        FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,

        FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,

        FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,

        FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,

        FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,

        FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,

        FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,

        FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,

};


enum fw_caps_config_crypto {

        FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,

        FW_CAPS_CONFIG_TLSKEYS = 0x00000002,

        FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,

        FW_CAPS_CONFIG_TLS_HW = 0x00000008,

};


enum fw_caps_config_fcoe {

        FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,

        FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,

        FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,

        FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,

        FW_CAPS_CONFIG_POFCOE_TARGET    = 0x00000010,

};


enum fw_memtype_cf {

        FW_MEMTYPE_CF_EDC0              = FW_MEMTYPE_EDC0,

        FW_MEMTYPE_CF_EDC1              = FW_MEMTYPE_EDC1,

        FW_MEMTYPE_CF_EXTMEM            = FW_MEMTYPE_EXTMEM,

        FW_MEMTYPE_CF_FLASH             = FW_MEMTYPE_FLASH,

        FW_MEMTYPE_CF_INTERNAL          = FW_MEMTYPE_INTERNAL,

        FW_MEMTYPE_CF_EXTMEM1           = FW_MEMTYPE_EXTMEM1,

};


struct fw_caps_config_cmd {

        __be32 op_to_write;

        __be32 cfvalid_to_len16;

        __be32 r2;

        __be32 hwmbitmap;

        __be16 nbmcaps;

        __be16 linkcaps;

        __be16 switchcaps;

        __be16 r3;

        __be16 niccaps;

        __be16 toecaps;

        __be16 rdmacaps;

        __be16 cryptocaps;

        __be16 iscsicaps;

        __be16 fcoecaps;

        __be32 cfcsum;

        __be32 finiver;

        __be32 finicsum;

};


#define S_FW_CAPS_CONFIG_CMD_CFVALID    27

#define M_FW_CAPS_CONFIG_CMD_CFVALID    0x1

#define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)

#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \

    (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)

#define F_FW_CAPS_CONFIG_CMD_CFVALID    V_FW_CAPS_CONFIG_CMD_CFVALID(1U)


#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24

#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7

#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \

    ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)

#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \

    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \

     M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)


#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16

#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff

#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \

    ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)

#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \

    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \

     M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)


/*

 * params command mnemonics

 */

enum fw_params_mnem {

        FW_PARAMS_MNEM_DEV              = 1,    /* device params */

        FW_PARAMS_MNEM_PFVF             = 2,    /* function params */

        FW_PARAMS_MNEM_REG              = 3,    /* limited register access */

        FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */

        FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */

        FW_PARAMS_MNEM_LAST

};


/*

 * device parameters

 */

#define S_FW_PARAMS_PARAM_FILTER_MODE 16

#define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff

#define V_FW_PARAMS_PARAM_FILTER_MODE(x) \

    ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)

#define G_FW_PARAMS_PARAM_FILTER_MODE(x) \

    (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \

        M_FW_PARAMS_PARAM_FILTER_MODE)


#define S_FW_PARAMS_PARAM_FILTER_MASK 0

#define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff

#define V_FW_PARAMS_PARAM_FILTER_MASK(x) \

    ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)

#define G_FW_PARAMS_PARAM_FILTER_MASK(x) \

    (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \

        M_FW_PARAMS_PARAM_FILTER_MASK)


enum fw_params_param_dev {

        FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */

        FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */

        FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs

                                                 * allocated by the device's

                                                 * Lookup Engine

                                                 */

        FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,

        FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04,

        FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,

        FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,

        FW_PARAMS_PARAM_DEV_INTFVER_RI  = 0x07,

        FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,

        FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,

        FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,

        FW_PARAMS_PARAM_DEV_FWREV       = 0x0B,

        FW_PARAMS_PARAM_DEV_TPREV       = 0x0C,

        FW_PARAMS_PARAM_DEV_CF          = 0x0D,

        FW_PARAMS_PARAM_DEV_BYPASS      = 0x0E,

        FW_PARAMS_PARAM_DEV_PHYFW       = 0x0F,

        FW_PARAMS_PARAM_DEV_LOAD        = 0x10,

        FW_PARAMS_PARAM_DEV_DIAG        = 0x11,

        FW_PARAMS_PARAM_DEV_UCLK        = 0x12, /* uP clock in khz */

        FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD

                                                 */

        FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD

                                                 */

        FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,

        FW_PARAMS_PARAM_DEV_MCINIT      = 0x16,

        FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,

        FW_PARAMS_PARAM_DEV_FWCACHE     = 0x18,

        FW_PARAMS_PARAM_DEV_RSSINFO     = 0x19,

        FW_PARAMS_PARAM_DEV_SCFGREV     = 0x1A,

        FW_PARAMS_PARAM_DEV_VPDREV      = 0x1B,

        FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR  = 0x1C,

        FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,


        FW_PARAMS_PARAM_DEV_MPSBGMAP    = 0x1E,

        FW_PARAMS_PARAM_DEV_TPCHMAP     = 0x1F,

        FW_PARAMS_PARAM_DEV_HMA_SIZE    = 0x20,

        FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,

        FW_PARAMS_PARAM_DEV_RING_BACKBONE       = 0x22,

        FW_PARAMS_PARAM_DEV_PPOD_EDRAM  = 0x23,

        FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR    = 0x24,

        FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25,

        FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,

        FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,

        FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,

        FW_PARAMS_PARAM_DEV_DBQ_TIMER   = 0x29,

        FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,

        FW_PARAMS_PARAM_DEV_NUM_TM_CLASS        = 0x2B,

        FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C,

        FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D,

        FW_PARAMS_PARAM_DEV_FILTER = 0x2E,

        FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F,

        FW_PARAMS_PARAM_DEV_DEV_512SGL_MR = 0x30,

        FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,

        FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32,

};


/*

 * dev bypass parameters; actions and modes

 */

enum fw_params_param_dev_bypass {


        /* actions

         */

        FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,

        FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,


        /* modes

         */

        FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,

        FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,

        FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,

};


enum fw_params_param_dev_phyfw {

        FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,

        FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,

};


enum fw_params_param_dev_diag {

        FW_PARAM_DEV_DIAG_TMP           = 0x00,

        FW_PARAM_DEV_DIAG_VDD           = 0x01,

        FW_PARAM_DEV_DIAG_MAXTMPTHRESH  = 0x02,

        FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03,

};


enum fw_params_param_dev_filter{

        FW_PARAM_DEV_FILTER_VNIC_MODE   = 0x00,

        FW_PARAM_DEV_FILTER_MODE_MASK   = 0x01,

};


enum fw_filter_vnic_mode {

        FW_VNIC_MODE_PF_VF = 0,

        FW_VNIC_MODE_OUTER_VLAN = 1,

        FW_VNIC_MODE_ENCAP_EN = 2,

};


enum fw_params_param_dev_ktls_hw {

        FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00,

        FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE  = 0x01,

        FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE = 0x00,

        FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE  = 0x01,

};


enum fw_params_param_dev_fwcache {

        FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,

        FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,

};


/*

 * physical and virtual function parameters

 */

enum fw_params_param_pfvf {

        FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,

        FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,

        FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,

        FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,

        FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,

        FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,

        FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,

        FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,

        FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,

        FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,

        FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,

        FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,

        FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,

        FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,

        FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,

        FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,

        FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,

        FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,

        FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,

        FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,

        FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,

        FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,

        FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,

        FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,

        FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,

        FW_PARAMS_PARAM_PFVF_SRQ_START  = 0x19,

        FW_PARAMS_PARAM_PFVF_SRQ_END    = 0x1A,

        FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,

        FW_PARAMS_PARAM_PFVF_VIID       = 0x24,

        FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,

        FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,

        FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,

        FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,

        FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,

        FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,

        FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,

        FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,

        FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,

        FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,

        FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,

        FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,

        FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,

        FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,

        FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,

        FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,

        FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,

        FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,

        FW_PARAMS_PARAM_PFVF_RAWF_END   = 0x37,

        FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,

        FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,

        FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,

        FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,

        FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,

        FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,

        FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,

        FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,

        FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,

};


/*

 * virtual link state as seen by the specified VF

 */

enum vf_link_states {

        VF_LINK_STATE_AUTO              = 0x00,

        VF_LINK_STATE_ENABLE            = 0x01,

        VF_LINK_STATE_DISABLE           = 0x02,

};


/*

 * dma queue parameters

 */

enum fw_params_param_dmaq {

        FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,

        FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,

        FW_PARAMS_PARAM_DMAQ_IQ_INTIDX  = 0x02,

        FW_PARAMS_PARAM_DMAQ_IQ_DCA     = 0x03,

        FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,

        FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,

        FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,

        FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,

        FW_PARAMS_PARAM_DMAQ_EQ_DCA     = 0x14,

        FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,

        FW_PARAMS_PARAM_DMAQ_CONM_CTXT  = 0x20,

        FW_PARAMS_PARAM_DMAQ_FLM_DCA    = 0x30

};


/*

 * chnet parameters

 */

enum fw_params_param_chnet {

        FW_PARAMS_PARAM_CHNET_FLAGS             = 0x00,

};


enum fw_params_param_chnet_flags {

        FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1,

        FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD  = 0x2,

        FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,

        FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8,

};


#define S_FW_PARAMS_MNEM        24

#define M_FW_PARAMS_MNEM        0xff

#define V_FW_PARAMS_MNEM(x)     ((x) << S_FW_PARAMS_MNEM)

#define G_FW_PARAMS_MNEM(x)     \

    (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)


#define S_FW_PARAMS_PARAM_X     16

#define M_FW_PARAMS_PARAM_X     0xff

#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)

#define G_FW_PARAMS_PARAM_X(x) \

    (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)


#define S_FW_PARAMS_PARAM_Y     8

#define M_FW_PARAMS_PARAM_Y     0xff

#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)

#define G_FW_PARAMS_PARAM_Y(x) \

    (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)


#define S_FW_PARAMS_PARAM_Z     0

#define M_FW_PARAMS_PARAM_Z     0xff

#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)

#define G_FW_PARAMS_PARAM_Z(x) \

    (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)


#define S_FW_PARAMS_PARAM_XYZ   0

#define M_FW_PARAMS_PARAM_XYZ   0xffffff

#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)

#define G_FW_PARAMS_PARAM_XYZ(x) \

    (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)


#define S_FW_PARAMS_PARAM_YZ    0

#define M_FW_PARAMS_PARAM_YZ    0xffff

#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)

#define G_FW_PARAMS_PARAM_YZ(x) \

    (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)


#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31

#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1

#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \

    ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)

#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \

    (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \

        M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)


#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24

#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3

#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \

    ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)

#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \

    (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \

        M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)


#define S_FW_PARAMS_PARAM_DMAQ_DCA_ST   0

#define M_FW_PARAMS_PARAM_DMAQ_DCA_ST   0x7ff

#define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \

    ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)

#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \

    (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)


#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE     29

#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE     0x7

#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x)  \

    ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)

#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x)  \

    (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \

     M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)


#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX    0

#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX    0x3ff

#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \

    ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)

#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \

    (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \

     M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)


struct fw_params_cmd {

        __be32 op_to_vfn;

        __be32 retval_len16;

        struct fw_params_param {

                __be32 mnem;

                __be32 val;

        } param[7];

};


#define S_FW_PARAMS_CMD_PFN             8

#define M_FW_PARAMS_CMD_PFN             0x7

#define V_FW_PARAMS_CMD_PFN(x)          ((x) << S_FW_PARAMS_CMD_PFN)

#define G_FW_PARAMS_CMD_PFN(x)          \

    (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)


#define S_FW_PARAMS_CMD_VFN             0

#define M_FW_PARAMS_CMD_VFN             0xff

#define V_FW_PARAMS_CMD_VFN(x)          ((x) << S_FW_PARAMS_CMD_VFN)

#define G_FW_PARAMS_CMD_VFN(x)          \

    (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)


struct fw_pfvf_cmd {

        __be32 op_to_vfn;

        __be32 retval_len16;

        __be32 niqflint_niq;

        __be32 type_to_neq;

        __be32 tc_to_nexactf;

        __be32 r_caps_to_nethctrl;

        __be16 nricq;

        __be16 nriqp;

        __be32 r4;

};


#define S_FW_PFVF_CMD_PFN               8

#define M_FW_PFVF_CMD_PFN               0x7

#define V_FW_PFVF_CMD_PFN(x)            ((x) << S_FW_PFVF_CMD_PFN)

#define G_FW_PFVF_CMD_PFN(x)            \

    (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)


#define S_FW_PFVF_CMD_VFN               0

#define M_FW_PFVF_CMD_VFN               0xff

#define V_FW_PFVF_CMD_VFN(x)            ((x) << S_FW_PFVF_CMD_VFN)

#define G_FW_PFVF_CMD_VFN(x)            \

    (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)


#define S_FW_PFVF_CMD_NIQFLINT          20

#define M_FW_PFVF_CMD_NIQFLINT          0xfff

#define V_FW_PFVF_CMD_NIQFLINT(x)       ((x) << S_FW_PFVF_CMD_NIQFLINT)

#define G_FW_PFVF_CMD_NIQFLINT(x)       \

    (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)


#define S_FW_PFVF_CMD_NIQ               0

#define M_FW_PFVF_CMD_NIQ               0xfffff

#define V_FW_PFVF_CMD_NIQ(x)            ((x) << S_FW_PFVF_CMD_NIQ)

#define G_FW_PFVF_CMD_NIQ(x)            \

    (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)


#define S_FW_PFVF_CMD_TYPE              31

#define M_FW_PFVF_CMD_TYPE              0x1

#define V_FW_PFVF_CMD_TYPE(x)           ((x) << S_FW_PFVF_CMD_TYPE)

#define G_FW_PFVF_CMD_TYPE(x)           \

    (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)

#define F_FW_PFVF_CMD_TYPE              V_FW_PFVF_CMD_TYPE(1U)


#define S_FW_PFVF_CMD_CMASK             24

#define M_FW_PFVF_CMD_CMASK             0xf

#define V_FW_PFVF_CMD_CMASK(x)          ((x) << S_FW_PFVF_CMD_CMASK)

#define G_FW_PFVF_CMD_CMASK(x)          \

    (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)


#define S_FW_PFVF_CMD_PMASK             20

#define M_FW_PFVF_CMD_PMASK             0xf

#define V_FW_PFVF_CMD_PMASK(x)          ((x) << S_FW_PFVF_CMD_PMASK)

#define G_FW_PFVF_CMD_PMASK(x)          \

    (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)


#define S_FW_PFVF_CMD_NEQ               0

#define M_FW_PFVF_CMD_NEQ               0xfffff

#define V_FW_PFVF_CMD_NEQ(x)            ((x) << S_FW_PFVF_CMD_NEQ)

#define G_FW_PFVF_CMD_NEQ(x)            \

    (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)


#define S_FW_PFVF_CMD_TC                24

#define M_FW_PFVF_CMD_TC                0xff

#define V_FW_PFVF_CMD_TC(x)             ((x) << S_FW_PFVF_CMD_TC)

#define G_FW_PFVF_CMD_TC(x)             \

    (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)


#define S_FW_PFVF_CMD_NVI               16

#define M_FW_PFVF_CMD_NVI               0xff

#define V_FW_PFVF_CMD_NVI(x)            ((x) << S_FW_PFVF_CMD_NVI)

#define G_FW_PFVF_CMD_NVI(x)            \

    (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)


#define S_FW_PFVF_CMD_NEXACTF           0

#define M_FW_PFVF_CMD_NEXACTF           0xffff

#define V_FW_PFVF_CMD_NEXACTF(x)        ((x) << S_FW_PFVF_CMD_NEXACTF)

#define G_FW_PFVF_CMD_NEXACTF(x)        \

    (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)


#define S_FW_PFVF_CMD_R_CAPS            24

#define M_FW_PFVF_CMD_R_CAPS            0xff

#define V_FW_PFVF_CMD_R_CAPS(x)         ((x) << S_FW_PFVF_CMD_R_CAPS)

#define G_FW_PFVF_CMD_R_CAPS(x)         \

    (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)


#define S_FW_PFVF_CMD_WX_CAPS           16

#define M_FW_PFVF_CMD_WX_CAPS           0xff

#define V_FW_PFVF_CMD_WX_CAPS(x)        ((x) << S_FW_PFVF_CMD_WX_CAPS)

#define G_FW_PFVF_CMD_WX_CAPS(x)        \

    (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)


#define S_FW_PFVF_CMD_NETHCTRL          0

#define M_FW_PFVF_CMD_NETHCTRL          0xffff

#define V_FW_PFVF_CMD_NETHCTRL(x)       ((x) << S_FW_PFVF_CMD_NETHCTRL)

#define G_FW_PFVF_CMD_NETHCTRL(x)       \

    (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)


/*

 *      ingress queue type; the first 1K ingress queues can have associated 0,

 *      1 or 2 free lists and an interrupt, all other ingress queues lack these

 *      capabilities

 */

enum fw_iq_type {

        FW_IQ_TYPE_FL_INT_CAP,

        FW_IQ_TYPE_NO_FL_INT_CAP,

        FW_IQ_TYPE_VF_CQ

};


enum fw_iq_iqtype {

        FW_IQ_IQTYPE_OTHER,

        FW_IQ_IQTYPE_NIC,

        FW_IQ_IQTYPE_OFLD,

};


struct fw_iq_cmd {

        __be32 op_to_vfn;

        __be32 alloc_to_len16;

        __be16 physiqid;

        __be16 iqid;

        __be16 fl0id;

        __be16 fl1id;

        __be32 type_to_iqandstindex;

        __be16 iqdroprss_to_iqesize;

        __be16 iqsize;

        __be64 iqaddr;

        __be32 iqns_to_fl0congen;

        __be16 fl0dcaen_to_fl0cidxfthresh;

        __be16 fl0size;

        __be64 fl0addr;

        __be32 fl1cngchmap_to_fl1congen;

        __be16 fl1dcaen_to_fl1cidxfthresh;

        __be16 fl1size;

        __be64 fl1addr;

};


#define S_FW_IQ_CMD_PFN                 8

#define M_FW_IQ_CMD_PFN                 0x7

#define V_FW_IQ_CMD_PFN(x)              ((x) << S_FW_IQ_CMD_PFN)

#define G_FW_IQ_CMD_PFN(x)              \

    (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)


#define S_FW_IQ_CMD_VFN                 0

#define M_FW_IQ_CMD_VFN                 0xff

#define V_FW_IQ_CMD_VFN(x)              ((x) << S_FW_IQ_CMD_VFN)

#define G_FW_IQ_CMD_VFN(x)              \

    (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)


#define S_FW_IQ_CMD_ALLOC               31

#define M_FW_IQ_CMD_ALLOC               0x1

#define V_FW_IQ_CMD_ALLOC(x)            ((x) << S_FW_IQ_CMD_ALLOC)

#define G_FW_IQ_CMD_ALLOC(x)            \

    (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)

#define F_FW_IQ_CMD_ALLOC               V_FW_IQ_CMD_ALLOC(1U)


#define S_FW_IQ_CMD_FREE                30

#define M_FW_IQ_CMD_FREE                0x1

#define V_FW_IQ_CMD_FREE(x)             ((x) << S_FW_IQ_CMD_FREE)

#define G_FW_IQ_CMD_FREE(x)             \

    (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)

#define F_FW_IQ_CMD_FREE                V_FW_IQ_CMD_FREE(1U)


#define S_FW_IQ_CMD_MODIFY              29

#define M_FW_IQ_CMD_MODIFY              0x1

#define V_FW_IQ_CMD_MODIFY(x)           ((x) << S_FW_IQ_CMD_MODIFY)

#define G_FW_IQ_CMD_MODIFY(x)           \

    (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)

#define F_FW_IQ_CMD_MODIFY              V_FW_IQ_CMD_MODIFY(1U)


#define S_FW_IQ_CMD_IQSTART             28

#define M_FW_IQ_CMD_IQSTART             0x1

#define V_FW_IQ_CMD_IQSTART(x)          ((x) << S_FW_IQ_CMD_IQSTART)

#define G_FW_IQ_CMD_IQSTART(x)          \

    (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)

#define F_FW_IQ_CMD_IQSTART             V_FW_IQ_CMD_IQSTART(1U)


#define S_FW_IQ_CMD_IQSTOP              27

#define M_FW_IQ_CMD_IQSTOP              0x1

#define V_FW_IQ_CMD_IQSTOP(x)           ((x) << S_FW_IQ_CMD_IQSTOP)

#define G_FW_IQ_CMD_IQSTOP(x)           \

    (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)

#define F_FW_IQ_CMD_IQSTOP              V_FW_IQ_CMD_IQSTOP(1U)


#define S_FW_IQ_CMD_TYPE                29

#define M_FW_IQ_CMD_TYPE                0x7

#define V_FW_IQ_CMD_TYPE(x)             ((x) << S_FW_IQ_CMD_TYPE)

#define G_FW_IQ_CMD_TYPE(x)             \

    (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)


#define S_FW_IQ_CMD_IQASYNCH            28

#define M_FW_IQ_CMD_IQASYNCH            0x1

#define V_FW_IQ_CMD_IQASYNCH(x)         ((x) << S_FW_IQ_CMD_IQASYNCH)

#define G_FW_IQ_CMD_IQASYNCH(x)         \

    (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)

#define F_FW_IQ_CMD_IQASYNCH            V_FW_IQ_CMD_IQASYNCH(1U)


#define S_FW_IQ_CMD_VIID                16

#define M_FW_IQ_CMD_VIID                0xfff

#define V_FW_IQ_CMD_VIID(x)             ((x) << S_FW_IQ_CMD_VIID)

#define G_FW_IQ_CMD_VIID(x)             \

    (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)


#define S_FW_IQ_CMD_IQANDST             15

#define M_FW_IQ_CMD_IQANDST             0x1

#define V_FW_IQ_CMD_IQANDST(x)          ((x) << S_FW_IQ_CMD_IQANDST)

#define G_FW_IQ_CMD_IQANDST(x)          \

    (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)

#define F_FW_IQ_CMD_IQANDST             V_FW_IQ_CMD_IQANDST(1U)


#define S_FW_IQ_CMD_IQANUS              14

#define M_FW_IQ_CMD_IQANUS              0x1

#define V_FW_IQ_CMD_IQANUS(x)           ((x) << S_FW_IQ_CMD_IQANUS)

#define G_FW_IQ_CMD_IQANUS(x)           \

    (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)

#define F_FW_IQ_CMD_IQANUS              V_FW_IQ_CMD_IQANUS(1U)


#define S_FW_IQ_CMD_IQANUD              12

#define M_FW_IQ_CMD_IQANUD              0x3

#define V_FW_IQ_CMD_IQANUD(x)           ((x) << S_FW_IQ_CMD_IQANUD)

#define G_FW_IQ_CMD_IQANUD(x)           \

    (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)


#define S_FW_IQ_CMD_IQANDSTINDEX        0

#define M_FW_IQ_CMD_IQANDSTINDEX        0xfff

#define V_FW_IQ_CMD_IQANDSTINDEX(x)     ((x) << S_FW_IQ_CMD_IQANDSTINDEX)

#define G_FW_IQ_CMD_IQANDSTINDEX(x)     \

    (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)


#define S_FW_IQ_CMD_IQDROPRSS           15

#define M_FW_IQ_CMD_IQDROPRSS           0x1

#define V_FW_IQ_CMD_IQDROPRSS(x)        ((x) << S_FW_IQ_CMD_IQDROPRSS)

#define G_FW_IQ_CMD_IQDROPRSS(x)        \

    (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)

#define F_FW_IQ_CMD_IQDROPRSS           V_FW_IQ_CMD_IQDROPRSS(1U)


#define S_FW_IQ_CMD_IQGTSMODE           14

#define M_FW_IQ_CMD_IQGTSMODE           0x1

#define V_FW_IQ_CMD_IQGTSMODE(x)        ((x) << S_FW_IQ_CMD_IQGTSMODE)

#define G_FW_IQ_CMD_IQGTSMODE(x)        \

    (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)

#define F_FW_IQ_CMD_IQGTSMODE           V_FW_IQ_CMD_IQGTSMODE(1U)


#define S_FW_IQ_CMD_IQPCIECH            12

#define M_FW_IQ_CMD_IQPCIECH            0x3

#define V_FW_IQ_CMD_IQPCIECH(x)         ((x) << S_FW_IQ_CMD_IQPCIECH)

#define G_FW_IQ_CMD_IQPCIECH(x)         \

    (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)


#define S_FW_IQ_CMD_IQDCAEN             11

#define M_FW_IQ_CMD_IQDCAEN             0x1

#define V_FW_IQ_CMD_IQDCAEN(x)          ((x) << S_FW_IQ_CMD_IQDCAEN)

#define G_FW_IQ_CMD_IQDCAEN(x)          \

    (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)

#define F_FW_IQ_CMD_IQDCAEN             V_FW_IQ_CMD_IQDCAEN(1U)


#define S_FW_IQ_CMD_IQDCACPU            6

#define M_FW_IQ_CMD_IQDCACPU            0x1f

#define V_FW_IQ_CMD_IQDCACPU(x)         ((x) << S_FW_IQ_CMD_IQDCACPU)

#define G_FW_IQ_CMD_IQDCACPU(x)         \

    (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)


#define S_FW_IQ_CMD_IQINTCNTTHRESH      4

#define M_FW_IQ_CMD_IQINTCNTTHRESH      0x3

#define V_FW_IQ_CMD_IQINTCNTTHRESH(x)   ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)

#define G_FW_IQ_CMD_IQINTCNTTHRESH(x)   \

    (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)


#define S_FW_IQ_CMD_IQO                 3

#define M_FW_IQ_CMD_IQO                 0x1

#define V_FW_IQ_CMD_IQO(x)              ((x) << S_FW_IQ_CMD_IQO)

#define G_FW_IQ_CMD_IQO(x)              \

    (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)

#define F_FW_IQ_CMD_IQO                 V_FW_IQ_CMD_IQO(1U)


#define S_FW_IQ_CMD_IQCPRIO             2

#define M_FW_IQ_CMD_IQCPRIO             0x1

#define V_FW_IQ_CMD_IQCPRIO(x)          ((x) << S_FW_IQ_CMD_IQCPRIO)

#define G_FW_IQ_CMD_IQCPRIO(x)          \

    (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)

#define F_FW_IQ_CMD_IQCPRIO             V_FW_IQ_CMD_IQCPRIO(1U)


#define S_FW_IQ_CMD_IQESIZE             0

#define M_FW_IQ_CMD_IQESIZE             0x3

#define V_FW_IQ_CMD_IQESIZE(x)          ((x) << S_FW_IQ_CMD_IQESIZE)

#define G_FW_IQ_CMD_IQESIZE(x)          \

    (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)


#define S_FW_IQ_CMD_IQNS                31

#define M_FW_IQ_CMD_IQNS                0x1

#define V_FW_IQ_CMD_IQNS(x)             ((x) << S_FW_IQ_CMD_IQNS)

#define G_FW_IQ_CMD_IQNS(x)             \

    (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)

#define F_FW_IQ_CMD_IQNS                V_FW_IQ_CMD_IQNS(1U)


#define S_FW_IQ_CMD_IQRO                30

#define M_FW_IQ_CMD_IQRO                0x1

#define V_FW_IQ_CMD_IQRO(x)             ((x) << S_FW_IQ_CMD_IQRO)

#define G_FW_IQ_CMD_IQRO(x)             \

    (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)

#define F_FW_IQ_CMD_IQRO                V_FW_IQ_CMD_IQRO(1U)


#define S_FW_IQ_CMD_IQFLINTIQHSEN       28

#define M_FW_IQ_CMD_IQFLINTIQHSEN       0x3

#define V_FW_IQ_CMD_IQFLINTIQHSEN(x)    ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)

#define G_FW_IQ_CMD_IQFLINTIQHSEN(x)    \

    (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)


#define S_FW_IQ_CMD_IQFLINTCONGEN       27

#define M_FW_IQ_CMD_IQFLINTCONGEN       0x1

#define V_FW_IQ_CMD_IQFLINTCONGEN(x)    ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)

#define G_FW_IQ_CMD_IQFLINTCONGEN(x)    \

    (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)

#define F_FW_IQ_CMD_IQFLINTCONGEN       V_FW_IQ_CMD_IQFLINTCONGEN(1U)


#define S_FW_IQ_CMD_IQFLINTISCSIC       26

#define M_FW_IQ_CMD_IQFLINTISCSIC       0x1

#define V_FW_IQ_CMD_IQFLINTISCSIC(x)    ((x) << S_FW_IQ_CMD_IQFLINTISCSIC)

#define G_FW_IQ_CMD_IQFLINTISCSIC(x)    \

    (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)

#define F_FW_IQ_CMD_IQFLINTISCSIC       V_FW_IQ_CMD_IQFLINTISCSIC(1U)


#define S_FW_IQ_CMD_IQTYPE      24

#define M_FW_IQ_CMD_IQTYPE      0x3

#define V_FW_IQ_CMD_IQTYPE(x)   ((x) << S_FW_IQ_CMD_IQTYPE)

#define G_FW_IQ_CMD_IQTYPE(x)   \

    (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)


#define S_FW_IQ_CMD_FL0CNGCHMAP         20

#define M_FW_IQ_CMD_FL0CNGCHMAP         0xf

#define V_FW_IQ_CMD_FL0CNGCHMAP(x)      ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)

#define G_FW_IQ_CMD_FL0CNGCHMAP(x)      \

    (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)


#define S_FW_IQ_CMD_FL0CONGDROP         16

#define M_FW_IQ_CMD_FL0CONGDROP         0x1

#define V_FW_IQ_CMD_FL0CONGDROP(x)      ((x) << S_FW_IQ_CMD_FL0CONGDROP)

#define G_FW_IQ_CMD_FL0CONGDROP(x)      \

    (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)

#define F_FW_IQ_CMD_FL0CONGDROP         V_FW_IQ_CMD_FL0CONGDROP(1U)


#define S_FW_IQ_CMD_FL0CACHELOCK        15

#define M_FW_IQ_CMD_FL0CACHELOCK        0x1

#define V_FW_IQ_CMD_FL0CACHELOCK(x)     ((x) << S_FW_IQ_CMD_FL0CACHELOCK)

#define G_FW_IQ_CMD_FL0CACHELOCK(x)     \

    (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)

#define F_FW_IQ_CMD_FL0CACHELOCK        V_FW_IQ_CMD_FL0CACHELOCK(1U)


#define S_FW_IQ_CMD_FL0DBP              14

#define M_FW_IQ_CMD_FL0DBP              0x1

#define V_FW_IQ_CMD_FL0DBP(x)           ((x) << S_FW_IQ_CMD_FL0DBP)

#define G_FW_IQ_CMD_FL0DBP(x)           \

    (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)

#define F_FW_IQ_CMD_FL0DBP              V_FW_IQ_CMD_FL0DBP(1U)


#define S_FW_IQ_CMD_FL0DATANS           13

#define M_FW_IQ_CMD_FL0DATANS           0x1

#define V_FW_IQ_CMD_FL0DATANS(x)        ((x) << S_FW_IQ_CMD_FL0DATANS)

#define G_FW_IQ_CMD_FL0DATANS(x)        \

    (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)

#define F_FW_IQ_CMD_FL0DATANS           V_FW_IQ_CMD_FL0DATANS(1U)


#define S_FW_IQ_CMD_FL0DATARO           12

#define M_FW_IQ_CMD_FL0DATARO           0x1

#define V_FW_IQ_CMD_FL0DATARO(x)        ((x) << S_FW_IQ_CMD_FL0DATARO)

#define G_FW_IQ_CMD_FL0DATARO(x)        \

    (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)

#define F_FW_IQ_CMD_FL0DATARO           V_FW_IQ_CMD_FL0DATARO(1U)


#define S_FW_IQ_CMD_FL0CONGCIF          11

#define M_FW_IQ_CMD_FL0CONGCIF          0x1

#define V_FW_IQ_CMD_FL0CONGCIF(x)       ((x) << S_FW_IQ_CMD_FL0CONGCIF)

#define G_FW_IQ_CMD_FL0CONGCIF(x)       \

    (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)

#define F_FW_IQ_CMD_FL0CONGCIF          V_FW_IQ_CMD_FL0CONGCIF(1U)


#define S_FW_IQ_CMD_FL0ONCHIP           10

#define M_FW_IQ_CMD_FL0ONCHIP           0x1

#define V_FW_IQ_CMD_FL0ONCHIP(x)        ((x) << S_FW_IQ_CMD_FL0ONCHIP)

#define G_FW_IQ_CMD_FL0ONCHIP(x)        \

    (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)

#define F_FW_IQ_CMD_FL0ONCHIP           V_FW_IQ_CMD_FL0ONCHIP(1U)


#define S_FW_IQ_CMD_FL0STATUSPGNS       9

#define M_FW_IQ_CMD_FL0STATUSPGNS       0x1

#define V_FW_IQ_CMD_FL0STATUSPGNS(x)    ((x) << S_FW_IQ_CMD_FL0STATUSPGNS)

#define G_FW_IQ_CMD_FL0STATUSPGNS(x)    \

    (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)

#define F_FW_IQ_CMD_FL0STATUSPGNS       V_FW_IQ_CMD_FL0STATUSPGNS(1U)


#define S_FW_IQ_CMD_FL0STATUSPGRO       8

#define M_FW_IQ_CMD_FL0STATUSPGRO       0x1

#define V_FW_IQ_CMD_FL0STATUSPGRO(x)    ((x) << S_FW_IQ_CMD_FL0STATUSPGRO)

#define G_FW_IQ_CMD_FL0STATUSPGRO(x)    \

    (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)

#define F_FW_IQ_CMD_FL0STATUSPGRO       V_FW_IQ_CMD_FL0STATUSPGRO(1U)


#define S_FW_IQ_CMD_FL0FETCHNS          7

#define M_FW_IQ_CMD_FL0FETCHNS          0x1

#define V_FW_IQ_CMD_FL0FETCHNS(x)       ((x) << S_FW_IQ_CMD_FL0FETCHNS)

#define G_FW_IQ_CMD_FL0FETCHNS(x)       \

    (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)

#define F_FW_IQ_CMD_FL0FETCHNS          V_FW_IQ_CMD_FL0FETCHNS(1U)


#define S_FW_IQ_CMD_FL0FETCHRO          6

#define M_FW_IQ_CMD_FL0FETCHRO          0x1

#define V_FW_IQ_CMD_FL0FETCHRO(x)       ((x) << S_FW_IQ_CMD_FL0FETCHRO)

#define G_FW_IQ_CMD_FL0FETCHRO(x)       \

    (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)

#define F_FW_IQ_CMD_FL0FETCHRO          V_FW_IQ_CMD_FL0FETCHRO(1U)


#define S_FW_IQ_CMD_FL0HOSTFCMODE       4

#define M_FW_IQ_CMD_FL0HOSTFCMODE       0x3

#define V_FW_IQ_CMD_FL0HOSTFCMODE(x)    ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)

#define G_FW_IQ_CMD_FL0HOSTFCMODE(x)    \

    (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)


#define S_FW_IQ_CMD_FL0CPRIO            3

#define M_FW_IQ_CMD_FL0CPRIO            0x1

#define V_FW_IQ_CMD_FL0CPRIO(x)         ((x) << S_FW_IQ_CMD_FL0CPRIO)

#define G_FW_IQ_CMD_FL0CPRIO(x)         \

    (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)

#define F_FW_IQ_CMD_FL0CPRIO            V_FW_IQ_CMD_FL0CPRIO(1U)


#define S_FW_IQ_CMD_FL0PADEN            2

#define M_FW_IQ_CMD_FL0PADEN            0x1

#define V_FW_IQ_CMD_FL0PADEN(x)         ((x) << S_FW_IQ_CMD_FL0PADEN)

#define G_FW_IQ_CMD_FL0PADEN(x)         \

    (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)

#define F_FW_IQ_CMD_FL0PADEN            V_FW_IQ_CMD_FL0PADEN(1U)


#define S_FW_IQ_CMD_FL0PACKEN           1

#define M_FW_IQ_CMD_FL0PACKEN           0x1

#define V_FW_IQ_CMD_FL0PACKEN(x)        ((x) << S_FW_IQ_CMD_FL0PACKEN)

#define G_FW_IQ_CMD_FL0PACKEN(x)        \

    (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)

#define F_FW_IQ_CMD_FL0PACKEN           V_FW_IQ_CMD_FL0PACKEN(1U)


#define S_FW_IQ_CMD_FL0CONGEN           0

#define M_FW_IQ_CMD_FL0CONGEN           0x1

#define V_FW_IQ_CMD_FL0CONGEN(x)        ((x) << S_FW_IQ_CMD_FL0CONGEN)

#define G_FW_IQ_CMD_FL0CONGEN(x)        \

    (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)

#define F_FW_IQ_CMD_FL0CONGEN           V_FW_IQ_CMD_FL0CONGEN(1U)


#define S_FW_IQ_CMD_FL0DCAEN            15

#define M_FW_IQ_CMD_FL0DCAEN            0x1

#define V_FW_IQ_CMD_FL0DCAEN(x)         ((x) << S_FW_IQ_CMD_FL0DCAEN)

#define G_FW_IQ_CMD_FL0DCAEN(x)         \

    (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)

#define F_FW_IQ_CMD_FL0DCAEN            V_FW_IQ_CMD_FL0DCAEN(1U)


#define S_FW_IQ_CMD_FL0DCACPU           10

#define M_FW_IQ_CMD_FL0DCACPU           0x1f

#define V_FW_IQ_CMD_FL0DCACPU(x)        ((x) << S_FW_IQ_CMD_FL0DCACPU)

#define G_FW_IQ_CMD_FL0DCACPU(x)        \

    (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)


#define S_FW_IQ_CMD_FL0FBMIN            7

#define M_FW_IQ_CMD_FL0FBMIN            0x7

#define V_FW_IQ_CMD_FL0FBMIN(x)         ((x) << S_FW_IQ_CMD_FL0FBMIN)

#define G_FW_IQ_CMD_FL0FBMIN(x)         \

    (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)


#define S_FW_IQ_CMD_FL0FBMAX            4

#define M_FW_IQ_CMD_FL0FBMAX            0x7

#define V_FW_IQ_CMD_FL0FBMAX(x)         ((x) << S_FW_IQ_CMD_FL0FBMAX)

#define G_FW_IQ_CMD_FL0FBMAX(x)         \

    (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)


#define S_FW_IQ_CMD_FL0CIDXFTHRESHO     3

#define M_FW_IQ_CMD_FL0CIDXFTHRESHO     0x1

#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x)  ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)

#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x)  \

    (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)

#define F_FW_IQ_CMD_FL0CIDXFTHRESHO     V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)


#define S_FW_IQ_CMD_FL0CIDXFTHRESH      0

#define M_FW_IQ_CMD_FL0CIDXFTHRESH      0x7

#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x)   ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)

#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x)   \

    (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)


#define S_FW_IQ_CMD_FL1CNGCHMAP         20

#define M_FW_IQ_CMD_FL1CNGCHMAP         0xf

#define V_FW_IQ_CMD_FL1CNGCHMAP(x)      ((x) << S_FW_IQ_CMD_FL1CNGCHMAP)

#define G_FW_IQ_CMD_FL1CNGCHMAP(x)      \

    (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)


#define S_FW_IQ_CMD_FL1CONGDROP         16

#define M_FW_IQ_CMD_FL1CONGDROP         0x1

#define V_FW_IQ_CMD_FL1CONGDROP(x)      ((x) << S_FW_IQ_CMD_FL1CONGDROP)

#define G_FW_IQ_CMD_FL1CONGDROP(x)      \

    (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)

#define F_FW_IQ_CMD_FL1CONGDROP         V_FW_IQ_CMD_FL1CONGDROP(1U)


#define S_FW_IQ_CMD_FL1CACHELOCK        15

#define M_FW_IQ_CMD_FL1CACHELOCK        0x1

#define V_FW_IQ_CMD_FL1CACHELOCK(x)     ((x) << S_FW_IQ_CMD_FL1CACHELOCK)

#define G_FW_IQ_CMD_FL1CACHELOCK(x)     \

    (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)

#define F_FW_IQ_CMD_FL1CACHELOCK        V_FW_IQ_CMD_FL1CACHELOCK(1U)


#define S_FW_IQ_CMD_FL1DBP              14

#define M_FW_IQ_CMD_FL1DBP              0x1

#define V_FW_IQ_CMD_FL1DBP(x)           ((x) << S_FW_IQ_CMD_FL1DBP)

#define G_FW_IQ_CMD_FL1DBP(x)           \

    (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)

#define F_FW_IQ_CMD_FL1DBP              V_FW_IQ_CMD_FL1DBP(1U)


#define S_FW_IQ_CMD_FL1DATANS           13

#define M_FW_IQ_CMD_FL1DATANS           0x1

#define V_FW_IQ_CMD_FL1DATANS(x)        ((x) << S_FW_IQ_CMD_FL1DATANS)

#define G_FW_IQ_CMD_FL1DATANS(x)        \

    (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)

#define F_FW_IQ_CMD_FL1DATANS           V_FW_IQ_CMD_FL1DATANS(1U)


#define S_FW_IQ_CMD_FL1DATARO           12

#define M_FW_IQ_CMD_FL1DATARO           0x1

#define V_FW_IQ_CMD_FL1DATARO(x)        ((x) << S_FW_IQ_CMD_FL1DATARO)

#define G_FW_IQ_CMD_FL1DATARO(x)        \

    (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)

#define F_FW_IQ_CMD_FL1DATARO           V_FW_IQ_CMD_FL1DATARO(1U)


#define S_FW_IQ_CMD_FL1CONGCIF          11

#define M_FW_IQ_CMD_FL1CONGCIF          0x1

#define V_FW_IQ_CMD_FL1CONGCIF(x)       ((x) << S_FW_IQ_CMD_FL1CONGCIF)

#define G_FW_IQ_CMD_FL1CONGCIF(x)       \

    (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)

#define F_FW_IQ_CMD_FL1CONGCIF          V_FW_IQ_CMD_FL1CONGCIF(1U)


#define S_FW_IQ_CMD_FL1ONCHIP           10

#define M_FW_IQ_CMD_FL1ONCHIP           0x1

#define V_FW_IQ_CMD_FL1ONCHIP(x)        ((x) << S_FW_IQ_CMD_FL1ONCHIP)

#define G_FW_IQ_CMD_FL1ONCHIP(x)        \

    (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)

#define F_FW_IQ_CMD_FL1ONCHIP           V_FW_IQ_CMD_FL1ONCHIP(1U)


#define S_FW_IQ_CMD_FL1STATUSPGNS       9

#define M_FW_IQ_CMD_FL1STATUSPGNS       0x1

#define V_FW_IQ_CMD_FL1STATUSPGNS(x)    ((x) << S_FW_IQ_CMD_FL1STATUSPGNS)

#define G_FW_IQ_CMD_FL1STATUSPGNS(x)    \

    (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)

#define F_FW_IQ_CMD_FL1STATUSPGNS       V_FW_IQ_CMD_FL1STATUSPGNS(1U)


#define S_FW_IQ_CMD_FL1STATUSPGRO       8

#define M_FW_IQ_CMD_FL1STATUSPGRO       0x1

#define V_FW_IQ_CMD_FL1STATUSPGRO(x)    ((x) << S_FW_IQ_CMD_FL1STATUSPGRO)

#define G_FW_IQ_CMD_FL1STATUSPGRO(x)    \

    (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)

#define F_FW_IQ_CMD_FL1STATUSPGRO       V_FW_IQ_CMD_FL1STATUSPGRO(1U)


#define S_FW_IQ_CMD_FL1FETCHNS          7

#define M_FW_IQ_CMD_FL1FETCHNS          0x1

#define V_FW_IQ_CMD_FL1FETCHNS(x)       ((x) << S_FW_IQ_CMD_FL1FETCHNS)

#define G_FW_IQ_CMD_FL1FETCHNS(x)       \

    (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)

#define F_FW_IQ_CMD_FL1FETCHNS          V_FW_IQ_CMD_FL1FETCHNS(1U)


#define S_FW_IQ_CMD_FL1FETCHRO          6

#define M_FW_IQ_CMD_FL1FETCHRO          0x1

#define V_FW_IQ_CMD_FL1FETCHRO(x)       ((x) << S_FW_IQ_CMD_FL1FETCHRO)

#define G_FW_IQ_CMD_FL1FETCHRO(x)       \

    (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)

#define F_FW_IQ_CMD_FL1FETCHRO          V_FW_IQ_CMD_FL1FETCHRO(1U)


#define S_FW_IQ_CMD_FL1HOSTFCMODE       4

#define M_FW_IQ_CMD_FL1HOSTFCMODE       0x3

#define V_FW_IQ_CMD_FL1HOSTFCMODE(x)    ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)

#define G_FW_IQ_CMD_FL1HOSTFCMODE(x)    \

    (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)


#define S_FW_IQ_CMD_FL1CPRIO            3

#define M_FW_IQ_CMD_FL1CPRIO            0x1

#define V_FW_IQ_CMD_FL1CPRIO(x)         ((x) << S_FW_IQ_CMD_FL1CPRIO)

#define G_FW_IQ_CMD_FL1CPRIO(x)         \

    (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)

#define F_FW_IQ_CMD_FL1CPRIO            V_FW_IQ_CMD_FL1CPRIO(1U)


#define S_FW_IQ_CMD_FL1PADEN            2

#define M_FW_IQ_CMD_FL1PADEN            0x1

#define V_FW_IQ_CMD_FL1PADEN(x)         ((x) << S_FW_IQ_CMD_FL1PADEN)

#define G_FW_IQ_CMD_FL1PADEN(x)         \

    (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)

#define F_FW_IQ_CMD_FL1PADEN            V_FW_IQ_CMD_FL1PADEN(1U)


#define S_FW_IQ_CMD_FL1PACKEN           1

#define M_FW_IQ_CMD_FL1PACKEN           0x1

#define V_FW_IQ_CMD_FL1PACKEN(x)        ((x) << S_FW_IQ_CMD_FL1PACKEN)

#define G_FW_IQ_CMD_FL1PACKEN(x)        \

    (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)

#define F_FW_IQ_CMD_FL1PACKEN           V_FW_IQ_CMD_FL1PACKEN(1U)


#define S_FW_IQ_CMD_FL1CONGEN           0

#define M_FW_IQ_CMD_FL1CONGEN           0x1

#define V_FW_IQ_CMD_FL1CONGEN(x)        ((x) << S_FW_IQ_CMD_FL1CONGEN)

#define G_FW_IQ_CMD_FL1CONGEN(x)        \

    (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)

#define F_FW_IQ_CMD_FL1CONGEN           V_FW_IQ_CMD_FL1CONGEN(1U)


#define S_FW_IQ_CMD_FL1DCAEN            15

#define M_FW_IQ_CMD_FL1DCAEN            0x1

#define V_FW_IQ_CMD_FL1DCAEN(x)         ((x) << S_FW_IQ_CMD_FL1DCAEN)

#define G_FW_IQ_CMD_FL1DCAEN(x)         \

    (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)

#define F_FW_IQ_CMD_FL1DCAEN            V_FW_IQ_CMD_FL1DCAEN(1U)


#define S_FW_IQ_CMD_FL1DCACPU           10

#define M_FW_IQ_CMD_FL1DCACPU           0x1f

#define V_FW_IQ_CMD_FL1DCACPU(x)        ((x) << S_FW_IQ_CMD_FL1DCACPU)

#define G_FW_IQ_CMD_FL1DCACPU(x)        \

    (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)


#define S_FW_IQ_CMD_FL1FBMIN            7

#define M_FW_IQ_CMD_FL1FBMIN            0x7

#define V_FW_IQ_CMD_FL1FBMIN(x)         ((x) << S_FW_IQ_CMD_FL1FBMIN)

#define G_FW_IQ_CMD_FL1FBMIN(x)         \

    (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)


#define S_FW_IQ_CMD_FL1FBMAX            4

#define M_FW_IQ_CMD_FL1FBMAX            0x7

#define V_FW_IQ_CMD_FL1FBMAX(x)         ((x) << S_FW_IQ_CMD_FL1FBMAX)

#define G_FW_IQ_CMD_FL1FBMAX(x)         \

    (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)


#define S_FW_IQ_CMD_FL1CIDXFTHRESHO     3

#define M_FW_IQ_CMD_FL1CIDXFTHRESHO     0x1

#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x)  ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)

#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x)  \

    (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)

#define F_FW_IQ_CMD_FL1CIDXFTHRESHO     V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)


#define S_FW_IQ_CMD_FL1CIDXFTHRESH      0

#define M_FW_IQ_CMD_FL1CIDXFTHRESH      0x7

#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x)   ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)

#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x)   \

    (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)


struct fw_eq_mngt_cmd {

        __be32 op_to_vfn;

        __be32 alloc_to_len16;

        __be32 cmpliqid_eqid;

        __be32 physeqid_pkd;

        __be32 fetchszm_to_iqid;

        __be32 dcaen_to_eqsize;

        __be64 eqaddr;

};


#define S_FW_EQ_MNGT_CMD_PFN            8

#define M_FW_EQ_MNGT_CMD_PFN            0x7

#define V_FW_EQ_MNGT_CMD_PFN(x)         ((x) << S_FW_EQ_MNGT_CMD_PFN)

#define G_FW_EQ_MNGT_CMD_PFN(x)         \

    (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)


#define S_FW_EQ_MNGT_CMD_VFN            0

#define M_FW_EQ_MNGT_CMD_VFN            0xff

#define V_FW_EQ_MNGT_CMD_VFN(x)         ((x) << S_FW_EQ_MNGT_CMD_VFN)

#define G_FW_EQ_MNGT_CMD_VFN(x)         \

    (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)


#define S_FW_EQ_MNGT_CMD_ALLOC          31

#define M_FW_EQ_MNGT_CMD_ALLOC          0x1

#define V_FW_EQ_MNGT_CMD_ALLOC(x)       ((x) << S_FW_EQ_MNGT_CMD_ALLOC)

#define G_FW_EQ_MNGT_CMD_ALLOC(x)       \

    (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)

#define F_FW_EQ_MNGT_CMD_ALLOC          V_FW_EQ_MNGT_CMD_ALLOC(1U)


#define S_FW_EQ_MNGT_CMD_FREE           30

#define M_FW_EQ_MNGT_CMD_FREE           0x1

#define V_FW_EQ_MNGT_CMD_FREE(x)        ((x) << S_FW_EQ_MNGT_CMD_FREE)

#define G_FW_EQ_MNGT_CMD_FREE(x)        \

    (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)

#define F_FW_EQ_MNGT_CMD_FREE           V_FW_EQ_MNGT_CMD_FREE(1U)


#define S_FW_EQ_MNGT_CMD_MODIFY         29

#define M_FW_EQ_MNGT_CMD_MODIFY         0x1

#define V_FW_EQ_MNGT_CMD_MODIFY(x)      ((x) << S_FW_EQ_MNGT_CMD_MODIFY)

#define G_FW_EQ_MNGT_CMD_MODIFY(x)      \

    (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)

#define F_FW_EQ_MNGT_CMD_MODIFY         V_FW_EQ_MNGT_CMD_MODIFY(1U)


#define S_FW_EQ_MNGT_CMD_EQSTART        28

#define M_FW_EQ_MNGT_CMD_EQSTART        0x1

#define V_FW_EQ_MNGT_CMD_EQSTART(x)     ((x) << S_FW_EQ_MNGT_CMD_EQSTART)

#define G_FW_EQ_MNGT_CMD_EQSTART(x)     \

    (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)

#define F_FW_EQ_MNGT_CMD_EQSTART        V_FW_EQ_MNGT_CMD_EQSTART(1U)


#define S_FW_EQ_MNGT_CMD_EQSTOP         27

#define M_FW_EQ_MNGT_CMD_EQSTOP         0x1

#define V_FW_EQ_MNGT_CMD_EQSTOP(x)      ((x) << S_FW_EQ_MNGT_CMD_EQSTOP)

#define G_FW_EQ_MNGT_CMD_EQSTOP(x)      \

    (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)

#define F_FW_EQ_MNGT_CMD_EQSTOP         V_FW_EQ_MNGT_CMD_EQSTOP(1U)


#define S_FW_EQ_MNGT_CMD_CMPLIQID       20

#define M_FW_EQ_MNGT_CMD_CMPLIQID       0xfff

#define V_FW_EQ_MNGT_CMD_CMPLIQID(x)    ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)

#define G_FW_EQ_MNGT_CMD_CMPLIQID(x)    \

    (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)


#define S_FW_EQ_MNGT_CMD_EQID           0

#define M_FW_EQ_MNGT_CMD_EQID           0xfffff

#define V_FW_EQ_MNGT_CMD_EQID(x)        ((x) << S_FW_EQ_MNGT_CMD_EQID)

#define G_FW_EQ_MNGT_CMD_EQID(x)        \

    (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)


#define S_FW_EQ_MNGT_CMD_PHYSEQID       0

#define M_FW_EQ_MNGT_CMD_PHYSEQID       0xfffff

#define V_FW_EQ_MNGT_CMD_PHYSEQID(x)    ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)

#define G_FW_EQ_MNGT_CMD_PHYSEQID(x)    \

    (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)


#define S_FW_EQ_MNGT_CMD_FETCHSZM       26

#define M_FW_EQ_MNGT_CMD_FETCHSZM       0x1

#define V_FW_EQ_MNGT_CMD_FETCHSZM(x)    ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)

#define G_FW_EQ_MNGT_CMD_FETCHSZM(x)    \

    (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)

#define F_FW_EQ_MNGT_CMD_FETCHSZM       V_FW_EQ_MNGT_CMD_FETCHSZM(1U)


#define S_FW_EQ_MNGT_CMD_STATUSPGNS     25

#define M_FW_EQ_MNGT_CMD_STATUSPGNS     0x1

#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x)  ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)

#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x)  \

    (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)

#define F_FW_EQ_MNGT_CMD_STATUSPGNS     V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)


#define S_FW_EQ_MNGT_CMD_STATUSPGRO     24

#define M_FW_EQ_MNGT_CMD_STATUSPGRO     0x1

#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x)  ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)

#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x)  \

    (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)

#define F_FW_EQ_MNGT_CMD_STATUSPGRO     V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)


#define S_FW_EQ_MNGT_CMD_FETCHNS        23

#define M_FW_EQ_MNGT_CMD_FETCHNS        0x1

#define V_FW_EQ_MNGT_CMD_FETCHNS(x)     ((x) << S_FW_EQ_MNGT_CMD_FETCHNS)

#define G_FW_EQ_MNGT_CMD_FETCHNS(x)     \

    (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)

#define F_FW_EQ_MNGT_CMD_FETCHNS        V_FW_EQ_MNGT_CMD_FETCHNS(1U)


#define S_FW_EQ_MNGT_CMD_FETCHRO        22

#define M_FW_EQ_MNGT_CMD_FETCHRO        0x1

#define V_FW_EQ_MNGT_CMD_FETCHRO(x)     ((x) << S_FW_EQ_MNGT_CMD_FETCHRO)

#define G_FW_EQ_MNGT_CMD_FETCHRO(x)     \

    (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)

#define F_FW_EQ_MNGT_CMD_FETCHRO        V_FW_EQ_MNGT_CMD_FETCHRO(1U)


#define S_FW_EQ_MNGT_CMD_HOSTFCMODE     20

#define M_FW_EQ_MNGT_CMD_HOSTFCMODE     0x3

#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x)  ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)

#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x)  \

    (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)


#define S_FW_EQ_MNGT_CMD_CPRIO          19

#define M_FW_EQ_MNGT_CMD_CPRIO          0x1

#define V_FW_EQ_MNGT_CMD_CPRIO(x)       ((x) << S_FW_EQ_MNGT_CMD_CPRIO)

#define G_FW_EQ_MNGT_CMD_CPRIO(x)       \

    (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)

#define F_FW_EQ_MNGT_CMD_CPRIO          V_FW_EQ_MNGT_CMD_CPRIO(1U)


#define S_FW_EQ_MNGT_CMD_ONCHIP         18

#define M_FW_EQ_MNGT_CMD_ONCHIP         0x1

#define V_FW_EQ_MNGT_CMD_ONCHIP(x)      ((x) << S_FW_EQ_MNGT_CMD_ONCHIP)

#define G_FW_EQ_MNGT_CMD_ONCHIP(x)      \

    (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)

#define F_FW_EQ_MNGT_CMD_ONCHIP         V_FW_EQ_MNGT_CMD_ONCHIP(1U)


#define S_FW_EQ_MNGT_CMD_PCIECHN        16

#define M_FW_EQ_MNGT_CMD_PCIECHN        0x3

#define V_FW_EQ_MNGT_CMD_PCIECHN(x)     ((x) << S_FW_EQ_MNGT_CMD_PCIECHN)

#define G_FW_EQ_MNGT_CMD_PCIECHN(x)     \

    (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)


#define S_FW_EQ_MNGT_CMD_IQID           0

#define M_FW_EQ_MNGT_CMD_IQID           0xffff

#define V_FW_EQ_MNGT_CMD_IQID(x)        ((x) << S_FW_EQ_MNGT_CMD_IQID)

#define G_FW_EQ_MNGT_CMD_IQID(x)        \

    (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)


#define S_FW_EQ_MNGT_CMD_DCAEN          31

#define M_FW_EQ_MNGT_CMD_DCAEN          0x1

#define V_FW_EQ_MNGT_CMD_DCAEN(x)       ((x) << S_FW_EQ_MNGT_CMD_DCAEN)

#define G_FW_EQ_MNGT_CMD_DCAEN(x)       \

    (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)

#define F_FW_EQ_MNGT_CMD_DCAEN          V_FW_EQ_MNGT_CMD_DCAEN(1U)


#define S_FW_EQ_MNGT_CMD_DCACPU         26

#define M_FW_EQ_MNGT_CMD_DCACPU         0x1f

#define V_FW_EQ_MNGT_CMD_DCACPU(x)      ((x) << S_FW_EQ_MNGT_CMD_DCACPU)

#define G_FW_EQ_MNGT_CMD_DCACPU(x)      \

    (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)


#define S_FW_EQ_MNGT_CMD_FBMIN          23

#define M_FW_EQ_MNGT_CMD_FBMIN          0x7

#define V_FW_EQ_MNGT_CMD_FBMIN(x)       ((x) << S_FW_EQ_MNGT_CMD_FBMIN)

#define G_FW_EQ_MNGT_CMD_FBMIN(x)       \

    (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)


#define S_FW_EQ_MNGT_CMD_FBMAX          20

#define M_FW_EQ_MNGT_CMD_FBMAX          0x7

#define V_FW_EQ_MNGT_CMD_FBMAX(x)       ((x) << S_FW_EQ_MNGT_CMD_FBMAX)

#define G_FW_EQ_MNGT_CMD_FBMAX(x)       \

    (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)


#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO   19

#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO   0x1

#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \

    ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)

#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \

    (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)

#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO   V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)


#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH    16

#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH    0x7

#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)

#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \

    (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)


#define S_FW_EQ_MNGT_CMD_EQSIZE         0

#define M_FW_EQ_MNGT_CMD_EQSIZE         0xffff

#define V_FW_EQ_MNGT_CMD_EQSIZE(x)      ((x) << S_FW_EQ_MNGT_CMD_EQSIZE)

#define G_FW_EQ_MNGT_CMD_EQSIZE(x)      \

    (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)


struct fw_eq_eth_cmd {

        __be32 op_to_vfn;

        __be32 alloc_to_len16;

        __be32 eqid_pkd;

        __be32 physeqid_pkd;

        __be32 fetchszm_to_iqid;

        __be32 dcaen_to_eqsize;

        __be64 eqaddr;

        __be32 autoequiqe_to_viid;

        __be32 timeren_timerix;

        __be64 r9;

};


#define S_FW_EQ_ETH_CMD_PFN             8

#define M_FW_EQ_ETH_CMD_PFN             0x7

#define V_FW_EQ_ETH_CMD_PFN(x)          ((x) << S_FW_EQ_ETH_CMD_PFN)

#define G_FW_EQ_ETH_CMD_PFN(x)          \

    (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)


#define S_FW_EQ_ETH_CMD_VFN             0

#define M_FW_EQ_ETH_CMD_VFN             0xff

#define V_FW_EQ_ETH_CMD_VFN(x)          ((x) << S_FW_EQ_ETH_CMD_VFN)

#define G_FW_EQ_ETH_CMD_VFN(x)          \

    (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)


#define S_FW_EQ_ETH_CMD_ALLOC           31

#define M_FW_EQ_ETH_CMD_ALLOC           0x1

#define V_FW_EQ_ETH_CMD_ALLOC(x)        ((x) << S_FW_EQ_ETH_CMD_ALLOC)

#define G_FW_EQ_ETH_CMD_ALLOC(x)        \

    (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)

#define F_FW_EQ_ETH_CMD_ALLOC           V_FW_EQ_ETH_CMD_ALLOC(1U)


#define S_FW_EQ_ETH_CMD_FREE            30

#define M_FW_EQ_ETH_CMD_FREE            0x1

#define V_FW_EQ_ETH_CMD_FREE(x)         ((x) << S_FW_EQ_ETH_CMD_FREE)

#define G_FW_EQ_ETH_CMD_FREE(x)         \

    (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)

#define F_FW_EQ_ETH_CMD_FREE            V_FW_EQ_ETH_CMD_FREE(1U)


#define S_FW_EQ_ETH_CMD_MODIFY          29

#define M_FW_EQ_ETH_CMD_MODIFY          0x1

#define V_FW_EQ_ETH_CMD_MODIFY(x)       ((x) << S_FW_EQ_ETH_CMD_MODIFY)

#define G_FW_EQ_ETH_CMD_MODIFY(x)       \

    (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)

#define F_FW_EQ_ETH_CMD_MODIFY          V_FW_EQ_ETH_CMD_MODIFY(1U)


#define S_FW_EQ_ETH_CMD_EQSTART         28

#define M_FW_EQ_ETH_CMD_EQSTART         0x1

#define V_FW_EQ_ETH_CMD_EQSTART(x)      ((x) << S_FW_EQ_ETH_CMD_EQSTART)

#define G_FW_EQ_ETH_CMD_EQSTART(x)      \

    (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)

#define F_FW_EQ_ETH_CMD_EQSTART         V_FW_EQ_ETH_CMD_EQSTART(1U)


#define S_FW_EQ_ETH_CMD_EQSTOP          27

#define M_FW_EQ_ETH_CMD_EQSTOP          0x1

#define V_FW_EQ_ETH_CMD_EQSTOP(x)       ((x) << S_FW_EQ_ETH_CMD_EQSTOP)

#define G_FW_EQ_ETH_CMD_EQSTOP(x)       \

    (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)

#define F_FW_EQ_ETH_CMD_EQSTOP          V_FW_EQ_ETH_CMD_EQSTOP(1U)


#define S_FW_EQ_ETH_CMD_EQID            0

#define M_FW_EQ_ETH_CMD_EQID            0xfffff

#define V_FW_EQ_ETH_CMD_EQID(x)         ((x) << S_FW_EQ_ETH_CMD_EQID)

#define G_FW_EQ_ETH_CMD_EQID(x)         \

    (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)


#define S_FW_EQ_ETH_CMD_PHYSEQID        0

#define M_FW_EQ_ETH_CMD_PHYSEQID        0xfffff

#define V_FW_EQ_ETH_CMD_PHYSEQID(x)     ((x) << S_FW_EQ_ETH_CMD_PHYSEQID)

#define G_FW_EQ_ETH_CMD_PHYSEQID(x)     \

    (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)


#define S_FW_EQ_ETH_CMD_FETCHSZM        26

#define M_FW_EQ_ETH_CMD_FETCHSZM        0x1

#define V_FW_EQ_ETH_CMD_FETCHSZM(x)     ((x) << S_FW_EQ_ETH_CMD_FETCHSZM)

#define G_FW_EQ_ETH_CMD_FETCHSZM(x)     \

    (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)

#define F_FW_EQ_ETH_CMD_FETCHSZM        V_FW_EQ_ETH_CMD_FETCHSZM(1U)


#define S_FW_EQ_ETH_CMD_STATUSPGNS      25

#define M_FW_EQ_ETH_CMD_STATUSPGNS      0x1

#define V_FW_EQ_ETH_CMD_STATUSPGNS(x)   ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)

#define G_FW_EQ_ETH_CMD_STATUSPGNS(x)   \

    (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)

#define F_FW_EQ_ETH_CMD_STATUSPGNS      V_FW_EQ_ETH_CMD_STATUSPGNS(1U)


#define S_FW_EQ_ETH_CMD_STATUSPGRO      24

#define M_FW_EQ_ETH_CMD_STATUSPGRO      0x1

#define V_FW_EQ_ETH_CMD_STATUSPGRO(x)   ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)

#define G_FW_EQ_ETH_CMD_STATUSPGRO(x)   \

    (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)

#define F_FW_EQ_ETH_CMD_STATUSPGRO      V_FW_EQ_ETH_CMD_STATUSPGRO(1U)


#define S_FW_EQ_ETH_CMD_FETCHNS         23

#define M_FW_EQ_ETH_CMD_FETCHNS         0x1

#define V_FW_EQ_ETH_CMD_FETCHNS(x)      ((x) << S_FW_EQ_ETH_CMD_FETCHNS)

#define G_FW_EQ_ETH_CMD_FETCHNS(x)      \

    (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)

#define F_FW_EQ_ETH_CMD_FETCHNS         V_FW_EQ_ETH_CMD_FETCHNS(1U)


#define S_FW_EQ_ETH_CMD_FETCHRO         22

#define M_FW_EQ_ETH_CMD_FETCHRO         0x1

#define V_FW_EQ_ETH_CMD_FETCHRO(x)      ((x) << S_FW_EQ_ETH_CMD_FETCHRO)

#define G_FW_EQ_ETH_CMD_FETCHRO(x)      \

    (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)

#define F_FW_EQ_ETH_CMD_FETCHRO         V_FW_EQ_ETH_CMD_FETCHRO(1U)


#define S_FW_EQ_ETH_CMD_HOSTFCMODE      20

#define M_FW_EQ_ETH_CMD_HOSTFCMODE      0x3

#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x)   ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)

#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x)   \

    (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)


#define S_FW_EQ_ETH_CMD_CPRIO           19

#define M_FW_EQ_ETH_CMD_CPRIO           0x1

#define V_FW_EQ_ETH_CMD_CPRIO(x)        ((x) << S_FW_EQ_ETH_CMD_CPRIO)

#define G_FW_EQ_ETH_CMD_CPRIO(x)        \

    (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)

#define F_FW_EQ_ETH_CMD_CPRIO           V_FW_EQ_ETH_CMD_CPRIO(1U)


#define S_FW_EQ_ETH_CMD_ONCHIP          18

#define M_FW_EQ_ETH_CMD_ONCHIP          0x1

#define V_FW_EQ_ETH_CMD_ONCHIP(x)       ((x) << S_FW_EQ_ETH_CMD_ONCHIP)

#define G_FW_EQ_ETH_CMD_ONCHIP(x)       \

    (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)

#define F_FW_EQ_ETH_CMD_ONCHIP          V_FW_EQ_ETH_CMD_ONCHIP(1U)


#define S_FW_EQ_ETH_CMD_PCIECHN         16

#define M_FW_EQ_ETH_CMD_PCIECHN         0x3

#define V_FW_EQ_ETH_CMD_PCIECHN(x)      ((x) << S_FW_EQ_ETH_CMD_PCIECHN)

#define G_FW_EQ_ETH_CMD_PCIECHN(x)      \

    (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)


#define S_FW_EQ_ETH_CMD_IQID            0

#define M_FW_EQ_ETH_CMD_IQID            0xffff

#define V_FW_EQ_ETH_CMD_IQID(x)         ((x) << S_FW_EQ_ETH_CMD_IQID)

#define G_FW_EQ_ETH_CMD_IQID(x)         \

    (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)


#define S_FW_EQ_ETH_CMD_DCAEN           31

#define M_FW_EQ_ETH_CMD_DCAEN           0x1

#define V_FW_EQ_ETH_CMD_DCAEN(x)        ((x) << S_FW_EQ_ETH_CMD_DCAEN)

#define G_FW_EQ_ETH_CMD_DCAEN(x)        \

    (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)

#define F_FW_EQ_ETH_CMD_DCAEN           V_FW_EQ_ETH_CMD_DCAEN(1U)


#define S_FW_EQ_ETH_CMD_DCACPU          26

#define M_FW_EQ_ETH_CMD_DCACPU          0x1f

#define V_FW_EQ_ETH_CMD_DCACPU(x)       ((x) << S_FW_EQ_ETH_CMD_DCACPU)

#define G_FW_EQ_ETH_CMD_DCACPU(x)       \

    (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)


#define S_FW_EQ_ETH_CMD_FBMIN           23

#define M_FW_EQ_ETH_CMD_FBMIN           0x7

#define V_FW_EQ_ETH_CMD_FBMIN(x)        ((x) << S_FW_EQ_ETH_CMD_FBMIN)

#define G_FW_EQ_ETH_CMD_FBMIN(x)        \

    (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)


#define S_FW_EQ_ETH_CMD_FBMAX           20

#define M_FW_EQ_ETH_CMD_FBMAX           0x7

#define V_FW_EQ_ETH_CMD_FBMAX(x)        ((x) << S_FW_EQ_ETH_CMD_FBMAX)

#define G_FW_EQ_ETH_CMD_FBMAX(x)        \

    (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)


#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO    19

#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO    0x1

#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)

#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \

    (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)

#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO    V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)


#define S_FW_EQ_ETH_CMD_CIDXFTHRESH     16

#define M_FW_EQ_ETH_CMD_CIDXFTHRESH     0x7

#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)  ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)

#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)  \

    (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)


#define S_FW_EQ_ETH_CMD_EQSIZE          0

#define M_FW_EQ_ETH_CMD_EQSIZE          0xffff

#define V_FW_EQ_ETH_CMD_EQSIZE(x)       ((x) << S_FW_EQ_ETH_CMD_EQSIZE)

#define G_FW_EQ_ETH_CMD_EQSIZE(x)       \

    (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)


#define S_FW_EQ_ETH_CMD_AUTOEQUIQE      31

#define M_FW_EQ_ETH_CMD_AUTOEQUIQE      0x1

#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x)   ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)

#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x)   \

    (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)

#define F_FW_EQ_ETH_CMD_AUTOEQUIQE      V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)


#define S_FW_EQ_ETH_CMD_AUTOEQUEQE      30

#define M_FW_EQ_ETH_CMD_AUTOEQUEQE      0x1

#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x)   ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)

#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x)   \

    (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)

#define F_FW_EQ_ETH_CMD_AUTOEQUEQE      V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)


#define S_FW_EQ_ETH_CMD_VIID            16

#define M_FW_EQ_ETH_CMD_VIID            0xfff

#define V_FW_EQ_ETH_CMD_VIID(x)         ((x) << S_FW_EQ_ETH_CMD_VIID)

#define G_FW_EQ_ETH_CMD_VIID(x)         \

    (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)


#define S_FW_EQ_ETH_CMD_TIMEREN         3

#define M_FW_EQ_ETH_CMD_TIMEREN         0x1

#define V_FW_EQ_ETH_CMD_TIMEREN(x)      ((x) << S_FW_EQ_ETH_CMD_TIMEREN)

#define G_FW_EQ_ETH_CMD_TIMEREN(x)      \

    (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)

#define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U)


#define S_FW_EQ_ETH_CMD_TIMERIX         0

#define M_FW_EQ_ETH_CMD_TIMERIX         0x7

#define V_FW_EQ_ETH_CMD_TIMERIX(x)      ((x) << S_FW_EQ_ETH_CMD_TIMERIX)

#define G_FW_EQ_ETH_CMD_TIMERIX(x)      \

    (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)


struct fw_eq_ctrl_cmd {

        __be32 op_to_vfn;

        __be32 alloc_to_len16;

        __be32 cmpliqid_eqid;

        __be32 physeqid_pkd;

        __be32 fetchszm_to_iqid;

        __be32 dcaen_to_eqsize;

        __be64 eqaddr;

};


#define S_FW_EQ_CTRL_CMD_PFN            8

#define M_FW_EQ_CTRL_CMD_PFN            0x7

#define V_FW_EQ_CTRL_CMD_PFN(x)         ((x) << S_FW_EQ_CTRL_CMD_PFN)

#define G_FW_EQ_CTRL_CMD_PFN(x)         \

    (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)


#define S_FW_EQ_CTRL_CMD_VFN            0

#define M_FW_EQ_CTRL_CMD_VFN            0xff

#define V_FW_EQ_CTRL_CMD_VFN(x)         ((x) << S_FW_EQ_CTRL_CMD_VFN)

#define G_FW_EQ_CTRL_CMD_VFN(x)         \

    (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)


#define S_FW_EQ_CTRL_CMD_ALLOC          31

#define M_FW_EQ_CTRL_CMD_ALLOC          0x1

#define V_FW_EQ_CTRL_CMD_ALLOC(x)       ((x) << S_FW_EQ_CTRL_CMD_ALLOC)

#define G_FW_EQ_CTRL_CMD_ALLOC(x)       \

    (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)

#define F_FW_EQ_CTRL_CMD_ALLOC          V_FW_EQ_CTRL_CMD_ALLOC(1U)


#define S_FW_EQ_CTRL_CMD_FREE           30

#define M_FW_EQ_CTRL_CMD_FREE           0x1

#define V_FW_EQ_CTRL_CMD_FREE(x)        ((x) << S_FW_EQ_CTRL_CMD_FREE)

#define G_FW_EQ_CTRL_CMD_FREE(x)        \

    (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)

#define F_FW_EQ_CTRL_CMD_FREE           V_FW_EQ_CTRL_CMD_FREE(1U)


#define S_FW_EQ_CTRL_CMD_MODIFY         29

#define M_FW_EQ_CTRL_CMD_MODIFY         0x1

#define V_FW_EQ_CTRL_CMD_MODIFY(x)      ((x) << S_FW_EQ_CTRL_CMD_MODIFY)

#define G_FW_EQ_CTRL_CMD_MODIFY(x)      \

    (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)

#define F_FW_EQ_CTRL_CMD_MODIFY         V_FW_EQ_CTRL_CMD_MODIFY(1U)


#define S_FW_EQ_CTRL_CMD_EQSTART        28

#define M_FW_EQ_CTRL_CMD_EQSTART        0x1

#define V_FW_EQ_CTRL_CMD_EQSTART(x)     ((x) << S_FW_EQ_CTRL_CMD_EQSTART)

#define G_FW_EQ_CTRL_CMD_EQSTART(x)     \

    (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)

#define F_FW_EQ_CTRL_CMD_EQSTART        V_FW_EQ_CTRL_CMD_EQSTART(1U)


#define S_FW_EQ_CTRL_CMD_EQSTOP         27

#define M_FW_EQ_CTRL_CMD_EQSTOP         0x1

#define V_FW_EQ_CTRL_CMD_EQSTOP(x)      ((x) << S_FW_EQ_CTRL_CMD_EQSTOP)

#define G_FW_EQ_CTRL_CMD_EQSTOP(x)      \

    (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)

#define F_FW_EQ_CTRL_CMD_EQSTOP         V_FW_EQ_CTRL_CMD_EQSTOP(1U)


#define S_FW_EQ_CTRL_CMD_CMPLIQID       20

#define M_FW_EQ_CTRL_CMD_CMPLIQID       0xfff

#define V_FW_EQ_CTRL_CMD_CMPLIQID(x)    ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)

#define G_FW_EQ_CTRL_CMD_CMPLIQID(x)    \

    (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)


#define S_FW_EQ_CTRL_CMD_EQID           0

#define M_FW_EQ_CTRL_CMD_EQID           0xfffff

#define V_FW_EQ_CTRL_CMD_EQID(x)        ((x) << S_FW_EQ_CTRL_CMD_EQID)

#define G_FW_EQ_CTRL_CMD_EQID(x)        \

    (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)


#define S_FW_EQ_CTRL_CMD_PHYSEQID       0

#define M_FW_EQ_CTRL_CMD_PHYSEQID       0xfffff

#define V_FW_EQ_CTRL_CMD_PHYSEQID(x)    ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)

#define G_FW_EQ_CTRL_CMD_PHYSEQID(x)    \

    (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)


#define S_FW_EQ_CTRL_CMD_FETCHSZM       26

#define M_FW_EQ_CTRL_CMD_FETCHSZM       0x1

#define V_FW_EQ_CTRL_CMD_FETCHSZM(x)    ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)

#define G_FW_EQ_CTRL_CMD_FETCHSZM(x)    \

    (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)

#define F_FW_EQ_CTRL_CMD_FETCHSZM       V_FW_EQ_CTRL_CMD_FETCHSZM(1U)


#define S_FW_EQ_CTRL_CMD_STATUSPGNS     25

#define M_FW_EQ_CTRL_CMD_STATUSPGNS     0x1

#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x)  ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)

#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x)  \

    (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)

#define F_FW_EQ_CTRL_CMD_STATUSPGNS     V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)


#define S_FW_EQ_CTRL_CMD_STATUSPGRO     24

#define M_FW_EQ_CTRL_CMD_STATUSPGRO     0x1

#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x)  ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)

#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x)  \

    (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)

#define F_FW_EQ_CTRL_CMD_STATUSPGRO     V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)


#define S_FW_EQ_CTRL_CMD_FETCHNS        23

#define M_FW_EQ_CTRL_CMD_FETCHNS        0x1

#define V_FW_EQ_CTRL_CMD_FETCHNS(x)     ((x) << S_FW_EQ_CTRL_CMD_FETCHNS)

#define G_FW_EQ_CTRL_CMD_FETCHNS(x)     \

    (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)

#define F_FW_EQ_CTRL_CMD_FETCHNS        V_FW_EQ_CTRL_CMD_FETCHNS(1U)


#define S_FW_EQ_CTRL_CMD_FETCHRO        22

#define M_FW_EQ_CTRL_CMD_FETCHRO        0x1

#define V_FW_EQ_CTRL_CMD_FETCHRO(x)     ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)

#define G_FW_EQ_CTRL_CMD_FETCHRO(x)     \

    (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)

#define F_FW_EQ_CTRL_CMD_FETCHRO        V_FW_EQ_CTRL_CMD_FETCHRO(1U)


#define S_FW_EQ_CTRL_CMD_HOSTFCMODE     20

#define M_FW_EQ_CTRL_CMD_HOSTFCMODE     0x3

#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x)  ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)

#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x)  \

    (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)


#define S_FW_EQ_CTRL_CMD_CPRIO          19

#define M_FW_EQ_CTRL_CMD_CPRIO          0x1

#define V_FW_EQ_CTRL_CMD_CPRIO(x)       ((x) << S_FW_EQ_CTRL_CMD_CPRIO)

#define G_FW_EQ_CTRL_CMD_CPRIO(x)       \

    (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)

#define F_FW_EQ_CTRL_CMD_CPRIO          V_FW_EQ_CTRL_CMD_CPRIO(1U)


#define S_FW_EQ_CTRL_CMD_ONCHIP         18

#define M_FW_EQ_CTRL_CMD_ONCHIP         0x1

#define V_FW_EQ_CTRL_CMD_ONCHIP(x)      ((x) << S_FW_EQ_CTRL_CMD_ONCHIP)

#define G_FW_EQ_CTRL_CMD_ONCHIP(x)      \

    (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)

#define F_FW_EQ_CTRL_CMD_ONCHIP         V_FW_EQ_CTRL_CMD_ONCHIP(1U)


#define S_FW_EQ_CTRL_CMD_PCIECHN        16

#define M_FW_EQ_CTRL_CMD_PCIECHN        0x3

#define V_FW_EQ_CTRL_CMD_PCIECHN(x)     ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)

#define G_FW_EQ_CTRL_CMD_PCIECHN(x)     \

    (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)


#define S_FW_EQ_CTRL_CMD_IQID           0

#define M_FW_EQ_CTRL_CMD_IQID           0xffff

#define V_FW_EQ_CTRL_CMD_IQID(x)        ((x) << S_FW_EQ_CTRL_CMD_IQID)

#define G_FW_EQ_CTRL_CMD_IQID(x)        \

    (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)


#define S_FW_EQ_CTRL_CMD_DCAEN          31

#define M_FW_EQ_CTRL_CMD_DCAEN          0x1

#define V_FW_EQ_CTRL_CMD_DCAEN(x)       ((x) << S_FW_EQ_CTRL_CMD_DCAEN)

#define G_FW_EQ_CTRL_CMD_DCAEN(x)       \

    (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)

#define F_FW_EQ_CTRL_CMD_DCAEN          V_FW_EQ_CTRL_CMD_DCAEN(1U)


#define S_FW_EQ_CTRL_CMD_DCACPU         26

#define M_FW_EQ_CTRL_CMD_DCACPU         0x1f

#define V_FW_EQ_CTRL_CMD_DCACPU(x)      ((x) << S_FW_EQ_CTRL_CMD_DCACPU)

#define G_FW_EQ_CTRL_CMD_DCACPU(x)      \

    (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)


#define S_FW_EQ_CTRL_CMD_FBMIN          23

#define M_FW_EQ_CTRL_CMD_FBMIN          0x7

#define V_FW_EQ_CTRL_CMD_FBMIN(x)       ((x) << S_FW_EQ_CTRL_CMD_FBMIN)

#define G_FW_EQ_CTRL_CMD_FBMIN(x)       \

    (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)


#define S_FW_EQ_CTRL_CMD_FBMAX          20

#define M_FW_EQ_CTRL_CMD_FBMAX          0x7

#define V_FW_EQ_CTRL_CMD_FBMAX(x)       ((x) << S_FW_EQ_CTRL_CMD_FBMAX)

#define G_FW_EQ_CTRL_CMD_FBMAX(x)       \

    (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)


#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO   19

#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO   0x1

#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \

    ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)

#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \

    (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)

#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO   V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)


#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH    16

#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH    0x7

#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)

#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \

    (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)


#define S_FW_EQ_CTRL_CMD_EQSIZE         0

#define M_FW_EQ_CTRL_CMD_EQSIZE         0xffff

#define V_FW_EQ_CTRL_CMD_EQSIZE(x)      ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)

#define G_FW_EQ_CTRL_CMD_EQSIZE(x)      \

    (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)


struct fw_eq_ofld_cmd {

        __be32 op_to_vfn;

        __be32 alloc_to_len16;

        __be32 eqid_pkd;

        __be32 physeqid_pkd;

        __be32 fetchszm_to_iqid;

        __be32 dcaen_to_eqsize;

        __be64 eqaddr;

};


#define S_FW_EQ_OFLD_CMD_PFN            8

#define M_FW_EQ_OFLD_CMD_PFN            0x7

#define V_FW_EQ_OFLD_CMD_PFN(x)         ((x) << S_FW_EQ_OFLD_CMD_PFN)

#define G_FW_EQ_OFLD_CMD_PFN(x)         \

    (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)


#define S_FW_EQ_OFLD_CMD_VFN            0

#define M_FW_EQ_OFLD_CMD_VFN            0xff

#define V_FW_EQ_OFLD_CMD_VFN(x)         ((x) << S_FW_EQ_OFLD_CMD_VFN)

#define G_FW_EQ_OFLD_CMD_VFN(x)         \

    (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)


#define S_FW_EQ_OFLD_CMD_ALLOC          31

#define M_FW_EQ_OFLD_CMD_ALLOC          0x1

#define V_FW_EQ_OFLD_CMD_ALLOC(x)       ((x) << S_FW_EQ_OFLD_CMD_ALLOC)

#define G_FW_EQ_OFLD_CMD_ALLOC(x)       \

    (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)

#define F_FW_EQ_OFLD_CMD_ALLOC          V_FW_EQ_OFLD_CMD_ALLOC(1U)


#define S_FW_EQ_OFLD_CMD_FREE           30

#define M_FW_EQ_OFLD_CMD_FREE           0x1

#define V_FW_EQ_OFLD_CMD_FREE(x)        ((x) << S_FW_EQ_OFLD_CMD_FREE)

#define G_FW_EQ_OFLD_CMD_FREE(x)        \

    (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)

#define F_FW_EQ_OFLD_CMD_FREE           V_FW_EQ_OFLD_CMD_FREE(1U)


#define S_FW_EQ_OFLD_CMD_MODIFY         29

#define M_FW_EQ_OFLD_CMD_MODIFY         0x1

#define V_FW_EQ_OFLD_CMD_MODIFY(x)      ((x) << S_FW_EQ_OFLD_CMD_MODIFY)

#define G_FW_EQ_OFLD_CMD_MODIFY(x)      \

    (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)

#define F_FW_EQ_OFLD_CMD_MODIFY         V_FW_EQ_OFLD_CMD_MODIFY(1U)


#define S_FW_EQ_OFLD_CMD_EQSTART        28

#define M_FW_EQ_OFLD_CMD_EQSTART        0x1

#define V_FW_EQ_OFLD_CMD_EQSTART(x)     ((x) << S_FW_EQ_OFLD_CMD_EQSTART)

#define G_FW_EQ_OFLD_CMD_EQSTART(x)     \

    (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)

#define F_FW_EQ_OFLD_CMD_EQSTART        V_FW_EQ_OFLD_CMD_EQSTART(1U)


#define S_FW_EQ_OFLD_CMD_EQSTOP         27

#define M_FW_EQ_OFLD_CMD_EQSTOP         0x1

#define V_FW_EQ_OFLD_CMD_EQSTOP(x)      ((x) << S_FW_EQ_OFLD_CMD_EQSTOP)

#define G_FW_EQ_OFLD_CMD_EQSTOP(x)      \

    (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)

#define F_FW_EQ_OFLD_CMD_EQSTOP         V_FW_EQ_OFLD_CMD_EQSTOP(1U)


#define S_FW_EQ_OFLD_CMD_EQID           0

#define M_FW_EQ_OFLD_CMD_EQID           0xfffff

#define V_FW_EQ_OFLD_CMD_EQID(x)        ((x) << S_FW_EQ_OFLD_CMD_EQID)

#define G_FW_EQ_OFLD_CMD_EQID(x)        \

    (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)


#define S_FW_EQ_OFLD_CMD_PHYSEQID       0

#define M_FW_EQ_OFLD_CMD_PHYSEQID       0xfffff

#define V_FW_EQ_OFLD_CMD_PHYSEQID(x)    ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)

#define G_FW_EQ_OFLD_CMD_PHYSEQID(x)    \

    (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)


#define S_FW_EQ_OFLD_CMD_FETCHSZM       26

#define M_FW_EQ_OFLD_CMD_FETCHSZM       0x1

#define V_FW_EQ_OFLD_CMD_FETCHSZM(x)    ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)

#define G_FW_EQ_OFLD_CMD_FETCHSZM(x)    \

    (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)

#define F_FW_EQ_OFLD_CMD_FETCHSZM       V_FW_EQ_OFLD_CMD_FETCHSZM(1U)


#define S_FW_EQ_OFLD_CMD_STATUSPGNS     25

#define M_FW_EQ_OFLD_CMD_STATUSPGNS     0x1

#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x)  ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)

#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x)  \

    (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)

#define F_FW_EQ_OFLD_CMD_STATUSPGNS     V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)


#define S_FW_EQ_OFLD_CMD_STATUSPGRO     24

#define M_FW_EQ_OFLD_CMD_STATUSPGRO     0x1

#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x)  ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)

#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x)  \

    (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)

#define F_FW_EQ_OFLD_CMD_STATUSPGRO     V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)


#define S_FW_EQ_OFLD_CMD_FETCHNS        23

#define M_FW_EQ_OFLD_CMD_FETCHNS        0x1

#define V_FW_EQ_OFLD_CMD_FETCHNS(x)     ((x) << S_FW_EQ_OFLD_CMD_FETCHNS)

#define G_FW_EQ_OFLD_CMD_FETCHNS(x)     \

    (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)

#define F_FW_EQ_OFLD_CMD_FETCHNS        V_FW_EQ_OFLD_CMD_FETCHNS(1U)


#define S_FW_EQ_OFLD_CMD_FETCHRO        22

#define M_FW_EQ_OFLD_CMD_FETCHRO        0x1

#define V_FW_EQ_OFLD_CMD_FETCHRO(x)     ((x) << S_FW_EQ_OFLD_CMD_FETCHRO)

#define G_FW_EQ_OFLD_CMD_FETCHRO(x)     \

    (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)

#define F_FW_EQ_OFLD_CMD_FETCHRO        V_FW_EQ_OFLD_CMD_FETCHRO(1U)


#define S_FW_EQ_OFLD_CMD_HOSTFCMODE     20

#define M_FW_EQ_OFLD_CMD_HOSTFCMODE     0x3

#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x)  ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)

#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x)  \

    (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)


#define S_FW_EQ_OFLD_CMD_CPRIO          19

#define M_FW_EQ_OFLD_CMD_CPRIO          0x1

#define V_FW_EQ_OFLD_CMD_CPRIO(x)       ((x) << S_FW_EQ_OFLD_CMD_CPRIO)

#define G_FW_EQ_OFLD_CMD_CPRIO(x)       \

    (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)

#define F_FW_EQ_OFLD_CMD_CPRIO          V_FW_EQ_OFLD_CMD_CPRIO(1U)


#define S_FW_EQ_OFLD_CMD_ONCHIP         18

#define M_FW_EQ_OFLD_CMD_ONCHIP         0x1

#define V_FW_EQ_OFLD_CMD_ONCHIP(x)      ((x) << S_FW_EQ_OFLD_CMD_ONCHIP)

#define G_FW_EQ_OFLD_CMD_ONCHIP(x)      \

    (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)

#define F_FW_EQ_OFLD_CMD_ONCHIP         V_FW_EQ_OFLD_CMD_ONCHIP(1U)


#define S_FW_EQ_OFLD_CMD_PCIECHN        16

#define M_FW_EQ_OFLD_CMD_PCIECHN        0x3

#define V_FW_EQ_OFLD_CMD_PCIECHN(x)     ((x) << S_FW_EQ_OFLD_CMD_PCIECHN)

#define G_FW_EQ_OFLD_CMD_PCIECHN(x)     \

    (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)


#define S_FW_EQ_OFLD_CMD_IQID           0

#define M_FW_EQ_OFLD_CMD_IQID           0xffff

#define V_FW_EQ_OFLD_CMD_IQID(x)        ((x) << S_FW_EQ_OFLD_CMD_IQID)

#define G_FW_EQ_OFLD_CMD_IQID(x)        \

    (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)


#define S_FW_EQ_OFLD_CMD_DCAEN          31

#define M_FW_EQ_OFLD_CMD_DCAEN          0x1

#define V_FW_EQ_OFLD_CMD_DCAEN(x)       ((x) << S_FW_EQ_OFLD_CMD_DCAEN)

#define G_FW_EQ_OFLD_CMD_DCAEN(x)       \

    (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)

#define F_FW_EQ_OFLD_CMD_DCAEN          V_FW_EQ_OFLD_CMD_DCAEN(1U)


#define S_FW_EQ_OFLD_CMD_DCACPU         26

#define M_FW_EQ_OFLD_CMD_DCACPU         0x1f

#define V_FW_EQ_OFLD_CMD_DCACPU(x)      ((x) << S_FW_EQ_OFLD_CMD_DCACPU)

#define G_FW_EQ_OFLD_CMD_DCACPU(x)      \

    (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)


#define S_FW_EQ_OFLD_CMD_FBMIN          23

#define M_FW_EQ_OFLD_CMD_FBMIN          0x7

#define V_FW_EQ_OFLD_CMD_FBMIN(x)       ((x) << S_FW_EQ_OFLD_CMD_FBMIN)

#define G_FW_EQ_OFLD_CMD_FBMIN(x)       \

    (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)


#define S_FW_EQ_OFLD_CMD_FBMAX          20

#define M_FW_EQ_OFLD_CMD_FBMAX          0x7

#define V_FW_EQ_OFLD_CMD_FBMAX(x)       ((x) << S_FW_EQ_OFLD_CMD_FBMAX)

#define G_FW_EQ_OFLD_CMD_FBMAX(x)       \

    (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)


#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO   19

#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO   0x1

#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \

    ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)

#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \

    (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)

#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO   V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)


#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH    16

#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH    0x7

#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)

#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \

    (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)


#define S_FW_EQ_OFLD_CMD_EQSIZE         0

#define M_FW_EQ_OFLD_CMD_EQSIZE         0xffff

#define V_FW_EQ_OFLD_CMD_EQSIZE(x)      ((x) << S_FW_EQ_OFLD_CMD_EQSIZE)

#define G_FW_EQ_OFLD_CMD_EQSIZE(x)      \

    (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)


/* Following macros present here only to maintain backward

 * compatibiity. Driver must not use these anymore */

/* Macros for VIID parsing:

   VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */

#define S_FW_VIID_PFN           8

#define M_FW_VIID_PFN           0x7

#define V_FW_VIID_PFN(x)        ((x) << S_FW_VIID_PFN)

#define G_FW_VIID_PFN(x)        (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)


#define S_FW_VIID_VIVLD         7

#define M_FW_VIID_VIVLD         0x1

#define V_FW_VIID_VIVLD(x)      ((x) << S_FW_VIID_VIVLD)

#define G_FW_VIID_VIVLD(x)      (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)


#define S_FW_VIID_VIN           0

#define M_FW_VIID_VIN           0x7F

#define V_FW_VIID_VIN(x)        ((x) << S_FW_VIID_VIN)

#define G_FW_VIID_VIN(x)        (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)


/* Macros for VIID parsing:

   VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */

#define S_FW_256VIID_PFN                9

#define M_FW_256VIID_PFN                0x7

#define V_FW_256VIID_PFN(x)             ((x) << S_FW_256VIID_PFN)

#define G_FW_256VIID_PFN(x)             (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)


#define S_FW_256VIID_VIVLD              8

#define M_FW_256VIID_VIVLD              0x1

#define V_FW_256VIID_VIVLD(x)           ((x) << S_FW_256VIID_VIVLD)

#define G_FW_256VIID_VIVLD(x)           (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)


#define S_FW_256VIID_VIN                0

#define M_FW_256VIID_VIN                0xFF

#define V_FW_256VIID_VIN(x)             ((x) << S_FW_256VIID_VIN)

#define G_FW_256VIID_VIN(x)             (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)


enum fw_vi_func {

        FW_VI_FUNC_ETH,

        FW_VI_FUNC_OFLD,

        FW_VI_FUNC_IWARP,

        FW_VI_FUNC_OPENISCSI,

        FW_VI_FUNC_OPENFCOE,

        FW_VI_FUNC_FOISCSI,

        FW_VI_FUNC_FOFCOE,

        FW_VI_FUNC_FW,

};


struct fw_vi_cmd {

        __be32 op_to_vfn;

        __be32 alloc_to_len16;

        __be16 type_to_viid;

        __u8   mac[6];

        __u8   portid_pkd;

        __u8   nmac;

        __u8   nmac0[6];

        __be16 norss_rsssize;

        __u8   nmac1[6];

        __be16 idsiiq_pkd;

        __u8   nmac2[6];

        __be16 idseiq_pkd;

        __u8   nmac3[6];

        __be64 r9;

        __be64 r10;

};


#define S_FW_VI_CMD_PFN                 8

#define M_FW_VI_CMD_PFN                 0x7

#define V_FW_VI_CMD_PFN(x)              ((x) << S_FW_VI_CMD_PFN)

#define G_FW_VI_CMD_PFN(x)              \

    (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)


#define S_FW_VI_CMD_VFN                 0

#define M_FW_VI_CMD_VFN                 0xff

#define V_FW_VI_CMD_VFN(x)              ((x) << S_FW_VI_CMD_VFN)

#define G_FW_VI_CMD_VFN(x)              \

    (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)


#define S_FW_VI_CMD_ALLOC               31

#define M_FW_VI_CMD_ALLOC               0x1

#define V_FW_VI_CMD_ALLOC(x)            ((x) << S_FW_VI_CMD_ALLOC)

#define G_FW_VI_CMD_ALLOC(x)            \

    (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)

#define F_FW_VI_CMD_ALLOC               V_FW_VI_CMD_ALLOC(1U)


#define S_FW_VI_CMD_FREE                30

#define M_FW_VI_CMD_FREE                0x1

#define V_FW_VI_CMD_FREE(x)             ((x) << S_FW_VI_CMD_FREE)

#define G_FW_VI_CMD_FREE(x)             \

    (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)

#define F_FW_VI_CMD_FREE                V_FW_VI_CMD_FREE(1U)


#define S_FW_VI_CMD_VFVLD               24

#define M_FW_VI_CMD_VFVLD               0x1

#define V_FW_VI_CMD_VFVLD(x)            ((x) << S_FW_VI_CMD_VFVLD)

#define G_FW_VI_CMD_VFVLD(x)            \

    (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)

#define F_FW_VI_CMD_VFVLD               V_FW_VI_CMD_VFVLD(1U)


#define S_FW_VI_CMD_VIN                 16

#define M_FW_VI_CMD_VIN                 0xff

#define V_FW_VI_CMD_VIN(x)              ((x) << S_FW_VI_CMD_VIN)

#define G_FW_VI_CMD_VIN(x)              \

    (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)


#define S_FW_VI_CMD_TYPE                15

#define M_FW_VI_CMD_TYPE                0x1

#define V_FW_VI_CMD_TYPE(x)             ((x) << S_FW_VI_CMD_TYPE)

#define G_FW_VI_CMD_TYPE(x)             \

    (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)

#define F_FW_VI_CMD_TYPE                V_FW_VI_CMD_TYPE(1U)


#define S_FW_VI_CMD_FUNC                12

#define M_FW_VI_CMD_FUNC                0x7

#define V_FW_VI_CMD_FUNC(x)             ((x) << S_FW_VI_CMD_FUNC)

#define G_FW_VI_CMD_FUNC(x)             \

    (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)


#define S_FW_VI_CMD_VIID                0

#define M_FW_VI_CMD_VIID                0xfff

#define V_FW_VI_CMD_VIID(x)             ((x) << S_FW_VI_CMD_VIID)

#define G_FW_VI_CMD_VIID(x)             \

    (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)


#define S_FW_VI_CMD_PORTID              4

#define M_FW_VI_CMD_PORTID              0xf

#define V_FW_VI_CMD_PORTID(x)           ((x) << S_FW_VI_CMD_PORTID)

#define G_FW_VI_CMD_PORTID(x)           \

    (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)


#define S_FW_VI_CMD_NORSS               11

#define M_FW_VI_CMD_NORSS               0x1

#define V_FW_VI_CMD_NORSS(x)            ((x) << S_FW_VI_CMD_NORSS)

#define G_FW_VI_CMD_NORSS(x)            \

    (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)

#define F_FW_VI_CMD_NORSS               V_FW_VI_CMD_NORSS(1U)


#define S_FW_VI_CMD_RSSSIZE             0

#define M_FW_VI_CMD_RSSSIZE             0x7ff

#define V_FW_VI_CMD_RSSSIZE(x)          ((x) << S_FW_VI_CMD_RSSSIZE)

#define G_FW_VI_CMD_RSSSIZE(x)          \

    (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)


#define S_FW_VI_CMD_IDSIIQ              0

#define M_FW_VI_CMD_IDSIIQ              0x3ff

#define V_FW_VI_CMD_IDSIIQ(x)           ((x) << S_FW_VI_CMD_IDSIIQ)

#define G_FW_VI_CMD_IDSIIQ(x)           \

    (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)


#define S_FW_VI_CMD_IDSEIQ              0

#define M_FW_VI_CMD_IDSEIQ              0x3ff

#define V_FW_VI_CMD_IDSEIQ(x)           ((x) << S_FW_VI_CMD_IDSEIQ)

#define G_FW_VI_CMD_IDSEIQ(x)           \

    (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)


/* Special VI_MAC command index ids */

#define FW_VI_MAC_ADD_MAC               0x3FF

#define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE

#define FW_VI_MAC_MAC_BASED_FREE        0x3FD

#define FW_VI_MAC_ID_BASED_FREE         0x3FC


enum fw_vi_mac_smac {

        FW_VI_MAC_MPS_TCAM_ENTRY,

        FW_VI_MAC_MPS_TCAM_ONLY,

        FW_VI_MAC_SMT_ONLY,

        FW_VI_MAC_SMT_AND_MPSTCAM

};


enum fw_vi_mac_result {

        FW_VI_MAC_R_SUCCESS,

        FW_VI_MAC_R_F_NONEXISTENT_NOMEM,

        FW_VI_MAC_R_SMAC_FAIL,

        FW_VI_MAC_R_F_ACL_CHECK

};


enum fw_vi_mac_entry_types {

        FW_VI_MAC_TYPE_EXACTMAC,

        FW_VI_MAC_TYPE_HASHVEC,

        FW_VI_MAC_TYPE_RAW,

        FW_VI_MAC_TYPE_EXACTMAC_VNI,

};


struct fw_vi_mac_cmd {

        __be32 op_to_viid;

        __be32 freemacs_to_len16;

        union fw_vi_mac {

                struct fw_vi_mac_exact {

                        __be16 valid_to_idx;

                        __u8   macaddr[6];

                } exact[7];

                struct fw_vi_mac_hash {

                        __be64 hashvec;

                } hash;

                struct fw_vi_mac_raw {

                        __be32 raw_idx_pkd;

                        __be32 data0_pkd;

                        __be32 data1[2];

                        __be64 data0m_pkd;

                        __be32 data1m[2];

                } raw;

                struct fw_vi_mac_vni {

                        __be16 valid_to_idx;

                        __u8   macaddr[6];

                        __be16 r7;

                        __u8   macaddr_mask[6];

                        __be32 lookup_type_to_vni;

                        __be32 vni_mask_pkd;

                } exact_vni[2];

        } u;

};


#define S_FW_VI_MAC_CMD_SMTID           12

#define M_FW_VI_MAC_CMD_SMTID           0xff

#define V_FW_VI_MAC_CMD_SMTID(x)        ((x) << S_FW_VI_MAC_CMD_SMTID)

#define G_FW_VI_MAC_CMD_SMTID(x)        \

    (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID)


#define S_FW_VI_MAC_CMD_VIID            0

#define M_FW_VI_MAC_CMD_VIID            0xfff

#define V_FW_VI_MAC_CMD_VIID(x)         ((x) << S_FW_VI_MAC_CMD_VIID)

#define G_FW_VI_MAC_CMD_VIID(x)         \

    (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)


#define S_FW_VI_MAC_CMD_FREEMACS        31

#define M_FW_VI_MAC_CMD_FREEMACS        0x1

#define V_FW_VI_MAC_CMD_FREEMACS(x)     ((x) << S_FW_VI_MAC_CMD_FREEMACS)

#define G_FW_VI_MAC_CMD_FREEMACS(x)     \

    (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)

#define F_FW_VI_MAC_CMD_FREEMACS        V_FW_VI_MAC_CMD_FREEMACS(1U)


#define S_FW_VI_MAC_CMD_IS_SMAC         30

#define M_FW_VI_MAC_CMD_IS_SMAC         0x1

#define V_FW_VI_MAC_CMD_IS_SMAC(x)      ((x) << S_FW_VI_MAC_CMD_IS_SMAC)

#define G_FW_VI_MAC_CMD_IS_SMAC(x)      \

    (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC)

#define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U)


#define S_FW_VI_MAC_CMD_ENTRY_TYPE      23

#define M_FW_VI_MAC_CMD_ENTRY_TYPE      0x7

#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)   ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)

#define G_FW_VI_MAC_CMD_ENTRY_TYPE(x)   \

    (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)


#define S_FW_VI_MAC_CMD_HASHUNIEN       22

#define M_FW_VI_MAC_CMD_HASHUNIEN       0x1

#define V_FW_VI_MAC_CMD_HASHUNIEN(x)    ((x) << S_FW_VI_MAC_CMD_HASHUNIEN)

#define G_FW_VI_MAC_CMD_HASHUNIEN(x)    \

    (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)

#define F_FW_VI_MAC_CMD_HASHUNIEN       V_FW_VI_MAC_CMD_HASHUNIEN(1U)


#define S_FW_VI_MAC_CMD_VALID           15

#define M_FW_VI_MAC_CMD_VALID           0x1

#define V_FW_VI_MAC_CMD_VALID(x)        ((x) << S_FW_VI_MAC_CMD_VALID)

#define G_FW_VI_MAC_CMD_VALID(x)        \

    (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)

#define F_FW_VI_MAC_CMD_VALID           V_FW_VI_MAC_CMD_VALID(1U)


#define S_FW_VI_MAC_CMD_PRIO            12

#define M_FW_VI_MAC_CMD_PRIO            0x7

#define V_FW_VI_MAC_CMD_PRIO(x)         ((x) << S_FW_VI_MAC_CMD_PRIO)

#define G_FW_VI_MAC_CMD_PRIO(x)         \

    (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)


#define S_FW_VI_MAC_CMD_SMAC_RESULT     10

#define M_FW_VI_MAC_CMD_SMAC_RESULT     0x3

#define V_FW_VI_MAC_CMD_SMAC_RESULT(x)  ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)

#define G_FW_VI_MAC_CMD_SMAC_RESULT(x)  \

    (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)


#define S_FW_VI_MAC_CMD_IDX             0

#define M_FW_VI_MAC_CMD_IDX             0x3ff

#define V_FW_VI_MAC_CMD_IDX(x)          ((x) << S_FW_VI_MAC_CMD_IDX)

#define G_FW_VI_MAC_CMD_IDX(x)          \

    (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)


#define S_FW_VI_MAC_CMD_RAW_IDX         16

#define M_FW_VI_MAC_CMD_RAW_IDX         0xffff

#define V_FW_VI_MAC_CMD_RAW_IDX(x)      ((x) << S_FW_VI_MAC_CMD_RAW_IDX)

#define G_FW_VI_MAC_CMD_RAW_IDX(x)      \

    (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)


#define S_FW_VI_MAC_CMD_DATA0           0

#define M_FW_VI_MAC_CMD_DATA0           0xffff

#define V_FW_VI_MAC_CMD_DATA0(x)        ((x) << S_FW_VI_MAC_CMD_DATA0)

#define G_FW_VI_MAC_CMD_DATA0(x)        \

    (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)


#define S_FW_VI_MAC_CMD_LOOKUP_TYPE     31

#define M_FW_VI_MAC_CMD_LOOKUP_TYPE     0x1

#define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x)  ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)

#define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x)  \

    (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)

#define F_FW_VI_MAC_CMD_LOOKUP_TYPE     V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)


#define S_FW_VI_MAC_CMD_DIP_HIT         30

#define M_FW_VI_MAC_CMD_DIP_HIT         0x1

#define V_FW_VI_MAC_CMD_DIP_HIT(x)      ((x) << S_FW_VI_MAC_CMD_DIP_HIT)

#define G_FW_VI_MAC_CMD_DIP_HIT(x)      \

    (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)

#define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U)


#define S_FW_VI_MAC_CMD_VNI     0

#define M_FW_VI_MAC_CMD_VNI     0xffffff

#define V_FW_VI_MAC_CMD_VNI(x)  ((x) << S_FW_VI_MAC_CMD_VNI)

#define G_FW_VI_MAC_CMD_VNI(x)  \

    (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)


/* Extracting loopback port number passed from driver.

 * as a part of fw_vi_mac_vni For non loopback entries

 * ignore the field and update port number from flowc.

 * Fw will ignore if physical port number received.

 * expected range (4-7).

 */


#define S_FW_VI_MAC_CMD_PORT            24

#define M_FW_VI_MAC_CMD_PORT            0x7

#define V_FW_VI_MAC_CMD_PORT(x)         ((x) << S_FW_VI_MAC_CMD_PORT)

#define G_FW_VI_MAC_CMD_PORT(x)         \

    (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT)


#define S_FW_VI_MAC_CMD_VNI_MASK        0

#define M_FW_VI_MAC_CMD_VNI_MASK        0xffffff

#define V_FW_VI_MAC_CMD_VNI_MASK(x)     ((x) << S_FW_VI_MAC_CMD_VNI_MASK)

#define G_FW_VI_MAC_CMD_VNI_MASK(x)     \

    (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)


/* T4 max MTU supported */

#define T4_MAX_MTU_SUPPORTED    9600

#define FW_RXMODE_MTU_NO_CHG    65535


struct fw_vi_rxmode_cmd {

        __be32 op_to_viid;

        __be32 retval_len16;

        __be32 mtu_to_vlanexen;

        __be32 r4_lo;

};


#define S_FW_VI_RXMODE_CMD_VIID         0

#define M_FW_VI_RXMODE_CMD_VIID         0xfff

#define V_FW_VI_RXMODE_CMD_VIID(x)      ((x) << S_FW_VI_RXMODE_CMD_VIID)

#define G_FW_VI_RXMODE_CMD_VIID(x)      \

    (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)


#define S_FW_VI_RXMODE_CMD_MTU          16

#define M_FW_VI_RXMODE_CMD_MTU          0xffff

#define V_FW_VI_RXMODE_CMD_MTU(x)       ((x) << S_FW_VI_RXMODE_CMD_MTU)

#define G_FW_VI_RXMODE_CMD_MTU(x)       \

    (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)


#define S_FW_VI_RXMODE_CMD_PROMISCEN    14

#define M_FW_VI_RXMODE_CMD_PROMISCEN    0x3

#define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)

#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \

    (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)


#define S_FW_VI_RXMODE_CMD_ALLMULTIEN   12

#define M_FW_VI_RXMODE_CMD_ALLMULTIEN   0x3

#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \

    ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)

#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \

    (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)


#define S_FW_VI_RXMODE_CMD_BROADCASTEN  10

#define M_FW_VI_RXMODE_CMD_BROADCASTEN  0x3

#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \

    ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)

#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \

    (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)


#define S_FW_VI_RXMODE_CMD_VLANEXEN     8

#define M_FW_VI_RXMODE_CMD_VLANEXEN     0x3

#define V_FW_VI_RXMODE_CMD_VLANEXEN(x)  ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)

#define G_FW_VI_RXMODE_CMD_VLANEXEN(x)  \

    (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)


struct fw_vi_enable_cmd {

        __be32 op_to_viid;

        __be32 ien_to_len16;

        __be16 blinkdur;

        __be16 r3;

        __be32 r4;

};


#define S_FW_VI_ENABLE_CMD_VIID         0

#define M_FW_VI_ENABLE_CMD_VIID         0xfff

#define V_FW_VI_ENABLE_CMD_VIID(x)      ((x) << S_FW_VI_ENABLE_CMD_VIID)

#define G_FW_VI_ENABLE_CMD_VIID(x)      \

    (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)


#define S_FW_VI_ENABLE_CMD_IEN          31

#define M_FW_VI_ENABLE_CMD_IEN          0x1

#define V_FW_VI_ENABLE_CMD_IEN(x)       ((x) << S_FW_VI_ENABLE_CMD_IEN)

#define G_FW_VI_ENABLE_CMD_IEN(x)       \

    (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)

#define F_FW_VI_ENABLE_CMD_IEN          V_FW_VI_ENABLE_CMD_IEN(1U)


#define S_FW_VI_ENABLE_CMD_EEN          30

#define M_FW_VI_ENABLE_CMD_EEN          0x1

#define V_FW_VI_ENABLE_CMD_EEN(x)       ((x) << S_FW_VI_ENABLE_CMD_EEN)

#define G_FW_VI_ENABLE_CMD_EEN(x)       \

    (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)

#define F_FW_VI_ENABLE_CMD_EEN          V_FW_VI_ENABLE_CMD_EEN(1U)


#define S_FW_VI_ENABLE_CMD_LED          29

#define M_FW_VI_ENABLE_CMD_LED          0x1

#define V_FW_VI_ENABLE_CMD_LED(x)       ((x) << S_FW_VI_ENABLE_CMD_LED)

#define G_FW_VI_ENABLE_CMD_LED(x)       \

    (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)

#define F_FW_VI_ENABLE_CMD_LED          V_FW_VI_ENABLE_CMD_LED(1U)


#define S_FW_VI_ENABLE_CMD_DCB_INFO     28

#define M_FW_VI_ENABLE_CMD_DCB_INFO     0x1

#define V_FW_VI_ENABLE_CMD_DCB_INFO(x)  ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)

#define G_FW_VI_ENABLE_CMD_DCB_INFO(x)  \

    (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)

#define F_FW_VI_ENABLE_CMD_DCB_INFO     V_FW_VI_ENABLE_CMD_DCB_INFO(1U)


/* VI VF stats offset definitions */

#define VI_VF_NUM_STATS 16

enum fw_vi_stats_vf_index {

        FW_VI_VF_STAT_TX_BCAST_BYTES_IX,

        FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,

        FW_VI_VF_STAT_TX_MCAST_BYTES_IX,

        FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,

        FW_VI_VF_STAT_TX_UCAST_BYTES_IX,

        FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,

        FW_VI_VF_STAT_TX_DROP_FRAMES_IX,

        FW_VI_VF_STAT_TX_OFLD_BYTES_IX,

        FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,

        FW_VI_VF_STAT_RX_BCAST_BYTES_IX,

        FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,

        FW_VI_VF_STAT_RX_MCAST_BYTES_IX,

        FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,

        FW_VI_VF_STAT_RX_UCAST_BYTES_IX,

        FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,

        FW_VI_VF_STAT_RX_ERR_FRAMES_IX

};


/* VI PF stats offset definitions */

#define VI_PF_NUM_STATS 17

enum fw_vi_stats_pf_index {

        FW_VI_PF_STAT_TX_BCAST_BYTES_IX,

        FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,

        FW_VI_PF_STAT_TX_MCAST_BYTES_IX,

        FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,

        FW_VI_PF_STAT_TX_UCAST_BYTES_IX,

        FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,

        FW_VI_PF_STAT_TX_OFLD_BYTES_IX,

        FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,

        FW_VI_PF_STAT_RX_BYTES_IX,

        FW_VI_PF_STAT_RX_FRAMES_IX,

        FW_VI_PF_STAT_RX_BCAST_BYTES_IX,

        FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,

        FW_VI_PF_STAT_RX_MCAST_BYTES_IX,

        FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,

        FW_VI_PF_STAT_RX_UCAST_BYTES_IX,

        FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,

        FW_VI_PF_STAT_RX_ERR_FRAMES_IX

};


struct fw_vi_stats_cmd {

        __be32 op_to_viid;

        __be32 retval_len16;

        union fw_vi_stats {

                struct fw_vi_stats_ctl {

                        __be16 nstats_ix;

                        __be16 r6;

                        __be32 r7;

                        __be64 stat0;

                        __be64 stat1;

                        __be64 stat2;

                        __be64 stat3;

                        __be64 stat4;

                        __be64 stat5;

                } ctl;

                struct fw_vi_stats_pf {

                        __be64 tx_bcast_bytes;

                        __be64 tx_bcast_frames;

                        __be64 tx_mcast_bytes;

                        __be64 tx_mcast_frames;

                        __be64 tx_ucast_bytes;

                        __be64 tx_ucast_frames;

                        __be64 tx_offload_bytes;

                        __be64 tx_offload_frames;

                        __be64 rx_pf_bytes;

                        __be64 rx_pf_frames;

                        __be64 rx_bcast_bytes;

                        __be64 rx_bcast_frames;

                        __be64 rx_mcast_bytes;

                        __be64 rx_mcast_frames;

                        __be64 rx_ucast_bytes;

                        __be64 rx_ucast_frames;

                        __be64 rx_err_frames;

                } pf;

                struct fw_vi_stats_vf {

                        __be64 tx_bcast_bytes;

                        __be64 tx_bcast_frames;

                        __be64 tx_mcast_bytes;

                        __be64 tx_mcast_frames;

                        __be64 tx_ucast_bytes;

                        __be64 tx_ucast_frames;

                        __be64 tx_drop_frames;

                        __be64 tx_offload_bytes;

                        __be64 tx_offload_frames;

                        __be64 rx_bcast_bytes;

                        __be64 rx_bcast_frames;

                        __be64 rx_mcast_bytes;

                        __be64 rx_mcast_frames;

                        __be64 rx_ucast_bytes;

                        __be64 rx_ucast_frames;

                        __be64 rx_err_frames;

                } vf;

        } u;

};


#define S_FW_VI_STATS_CMD_VIID          0

#define M_FW_VI_STATS_CMD_VIID          0xfff

#define V_FW_VI_STATS_CMD_VIID(x)       ((x) << S_FW_VI_STATS_CMD_VIID)

#define G_FW_VI_STATS_CMD_VIID(x)       \

    (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)


#define S_FW_VI_STATS_CMD_NSTATS        12

#define M_FW_VI_STATS_CMD_NSTATS        0x7

#define V_FW_VI_STATS_CMD_NSTATS(x)     ((x) << S_FW_VI_STATS_CMD_NSTATS)

#define G_FW_VI_STATS_CMD_NSTATS(x)     \

    (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)


#define S_FW_VI_STATS_CMD_IX            0

#define M_FW_VI_STATS_CMD_IX            0x1f

#define V_FW_VI_STATS_CMD_IX(x)         ((x) << S_FW_VI_STATS_CMD_IX)

#define G_FW_VI_STATS_CMD_IX(x)         \

    (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)


struct fw_acl_mac_cmd {

        __be32 op_to_vfn;

        __be32 en_to_len16;

        __u8   nmac;

        __u8   r3[7];

        __be16 r4;

        __u8   macaddr0[6];

        __be16 r5;

        __u8   macaddr1[6];

        __be16 r6;

        __u8   macaddr2[6];

        __be16 r7;

        __u8   macaddr3[6];

};


#define S_FW_ACL_MAC_CMD_PFN            8

#define M_FW_ACL_MAC_CMD_PFN            0x7

#define V_FW_ACL_MAC_CMD_PFN(x)         ((x) << S_FW_ACL_MAC_CMD_PFN)

#define G_FW_ACL_MAC_CMD_PFN(x)         \

    (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)


#define S_FW_ACL_MAC_CMD_VFN            0

#define M_FW_ACL_MAC_CMD_VFN            0xff

#define V_FW_ACL_MAC_CMD_VFN(x)         ((x) << S_FW_ACL_MAC_CMD_VFN)

#define G_FW_ACL_MAC_CMD_VFN(x)         \

    (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)


#define S_FW_ACL_MAC_CMD_EN             31

#define M_FW_ACL_MAC_CMD_EN             0x1

#define V_FW_ACL_MAC_CMD_EN(x)          ((x) << S_FW_ACL_MAC_CMD_EN)

#define G_FW_ACL_MAC_CMD_EN(x)          \

    (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)

#define F_FW_ACL_MAC_CMD_EN             V_FW_ACL_MAC_CMD_EN(1U)


struct fw_acl_vlan_cmd {

        __be32 op_to_vfn;

        __be32 en_to_len16;

        __u8   nvlan;

        __u8   dropnovlan_fm;

        __u8   r3_lo[6];

        __be16 vlanid[16];

};


#define S_FW_ACL_VLAN_CMD_PFN           8

#define M_FW_ACL_VLAN_CMD_PFN           0x7

#define V_FW_ACL_VLAN_CMD_PFN(x)        ((x) << S_FW_ACL_VLAN_CMD_PFN)

#define G_FW_ACL_VLAN_CMD_PFN(x)        \

    (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)


#define S_FW_ACL_VLAN_CMD_VFN           0

#define M_FW_ACL_VLAN_CMD_VFN           0xff

#define V_FW_ACL_VLAN_CMD_VFN(x)        ((x) << S_FW_ACL_VLAN_CMD_VFN)

#define G_FW_ACL_VLAN_CMD_VFN(x)        \

    (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)


#define S_FW_ACL_VLAN_CMD_EN            31

#define M_FW_ACL_VLAN_CMD_EN            0x1

#define V_FW_ACL_VLAN_CMD_EN(x)         ((x) << S_FW_ACL_VLAN_CMD_EN)

#define G_FW_ACL_VLAN_CMD_EN(x)         \

    (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)

#define F_FW_ACL_VLAN_CMD_EN            V_FW_ACL_VLAN_CMD_EN(1U)


#define S_FW_ACL_VLAN_CMD_TRANSPARENT   30

#define M_FW_ACL_VLAN_CMD_TRANSPARENT   0x1

#define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \

    ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT)

#define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \

    (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT)

#define F_FW_ACL_VLAN_CMD_TRANSPARENT   V_FW_ACL_VLAN_CMD_TRANSPARENT(1U)


#define S_FW_ACL_VLAN_CMD_PMASK         16

#define M_FW_ACL_VLAN_CMD_PMASK         0xf

#define V_FW_ACL_VLAN_CMD_PMASK(x)      ((x) << S_FW_ACL_VLAN_CMD_PMASK)

#define G_FW_ACL_VLAN_CMD_PMASK(x)      \

    (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK)


#define S_FW_ACL_VLAN_CMD_DROPNOVLAN    7

#define M_FW_ACL_VLAN_CMD_DROPNOVLAN    0x1

#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)

#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \

    (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)

#define F_FW_ACL_VLAN_CMD_DROPNOVLAN    V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)


#define S_FW_ACL_VLAN_CMD_FM            6

#define M_FW_ACL_VLAN_CMD_FM            0x1

#define V_FW_ACL_VLAN_CMD_FM(x)         ((x) << S_FW_ACL_VLAN_CMD_FM)

#define G_FW_ACL_VLAN_CMD_FM(x)         \

    (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)

#define F_FW_ACL_VLAN_CMD_FM            V_FW_ACL_VLAN_CMD_FM(1U)


/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */

enum fw_port_cap {

        FW_PORT_CAP_SPEED_100M          = 0x0001,

        FW_PORT_CAP_SPEED_1G            = 0x0002,

        FW_PORT_CAP_SPEED_25G           = 0x0004,

        FW_PORT_CAP_SPEED_10G           = 0x0008,

        FW_PORT_CAP_SPEED_40G           = 0x0010,

        FW_PORT_CAP_SPEED_100G          = 0x0020,

        FW_PORT_CAP_FC_RX               = 0x0040,

        FW_PORT_CAP_FC_TX               = 0x0080,

        FW_PORT_CAP_ANEG                = 0x0100,

        FW_PORT_CAP_MDIAUTO             = 0x0200,

        FW_PORT_CAP_MDISTRAIGHT         = 0x0400,

        FW_PORT_CAP_FEC_RS              = 0x0800,

        FW_PORT_CAP_FEC_BASER_RS        = 0x1000,

        FW_PORT_CAP_FORCE_PAUSE         = 0x2000,

        FW_PORT_CAP_802_3_PAUSE         = 0x4000,

        FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,

};


#define S_FW_PORT_CAP_SPEED     0

#define M_FW_PORT_CAP_SPEED     0x3f

#define V_FW_PORT_CAP_SPEED(x)  ((x) << S_FW_PORT_CAP_SPEED)

#define G_FW_PORT_CAP_SPEED(x) \

    (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)


#define S_FW_PORT_CAP_FC        6

#define M_FW_PORT_CAP_FC        0x3

#define V_FW_PORT_CAP_FC(x)     ((x) << S_FW_PORT_CAP_FC)

#define G_FW_PORT_CAP_FC(x) \

    (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)


#define S_FW_PORT_CAP_ANEG      8

#define M_FW_PORT_CAP_ANEG      0x1

#define V_FW_PORT_CAP_ANEG(x)   ((x) << S_FW_PORT_CAP_ANEG)

#define G_FW_PORT_CAP_ANEG(x) \

    (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)


#define S_FW_PORT_CAP_FEC       11

#define M_FW_PORT_CAP_FEC       0x3

#define V_FW_PORT_CAP_FEC(x)    ((x) << S_FW_PORT_CAP_FEC)

#define G_FW_PORT_CAP_FEC(x) \

    (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)


#define S_FW_PORT_CAP_FORCE_PAUSE       13

#define M_FW_PORT_CAP_FORCE_PAUSE       0x1

#define V_FW_PORT_CAP_FORCE_PAUSE(x)    ((x) << S_FW_PORT_CAP_FORCE_PAUSE)

#define G_FW_PORT_CAP_FORCE_PAUSE(x) \

    (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)


#define S_FW_PORT_CAP_802_3     14

#define M_FW_PORT_CAP_802_3     0x3

#define V_FW_PORT_CAP_802_3(x)  ((x) << S_FW_PORT_CAP_802_3)

#define G_FW_PORT_CAP_802_3(x) \

    (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)


enum fw_port_mdi {

        FW_PORT_CAP_MDI_UNCHANGED,

        FW_PORT_CAP_MDI_AUTO,

        FW_PORT_CAP_MDI_F_STRAIGHT,

        FW_PORT_CAP_MDI_F_CROSSOVER

};


#define S_FW_PORT_CAP_MDI 9

#define M_FW_PORT_CAP_MDI 3

#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)

#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)


/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */

#define FW_PORT_CAP32_SPEED_100M        0x00000001UL

#define FW_PORT_CAP32_SPEED_1G          0x00000002UL

#define FW_PORT_CAP32_SPEED_10G         0x00000004UL

#define FW_PORT_CAP32_SPEED_25G         0x00000008UL

#define FW_PORT_CAP32_SPEED_40G         0x00000010UL

#define FW_PORT_CAP32_SPEED_50G         0x00000020UL

#define FW_PORT_CAP32_SPEED_100G        0x00000040UL

#define FW_PORT_CAP32_SPEED_200G        0x00000080UL

#define FW_PORT_CAP32_SPEED_400G        0x00000100UL

#define FW_PORT_CAP32_SPEED_RESERVED1   0x00000200UL

#define FW_PORT_CAP32_SPEED_RESERVED2   0x00000400UL

#define FW_PORT_CAP32_SPEED_RESERVED3   0x00000800UL

#define FW_PORT_CAP32_RESERVED1         0x0000f000UL

#define FW_PORT_CAP32_FC_RX             0x00010000UL

#define FW_PORT_CAP32_FC_TX             0x00020000UL

#define FW_PORT_CAP32_802_3_PAUSE       0x00040000UL

#define FW_PORT_CAP32_802_3_ASM_DIR     0x00080000UL

#define FW_PORT_CAP32_ANEG              0x00100000UL

#define FW_PORT_CAP32_MDIAUTO           0x00200000UL

#define FW_PORT_CAP32_MDISTRAIGHT       0x00400000UL

#define FW_PORT_CAP32_FEC_RS            0x00800000UL

#define FW_PORT_CAP32_FEC_BASER_RS      0x01000000UL

#define FW_PORT_CAP32_FEC_NO_FEC        0x02000000UL

#define FW_PORT_CAP32_FEC_RESERVED2     0x04000000UL

#define FW_PORT_CAP32_FEC_RESERVED3     0x08000000UL

#define FW_PORT_CAP32_FORCE_PAUSE       0x10000000UL

#define FW_PORT_CAP32_FORCE_FEC         0x20000000UL

#define FW_PORT_CAP32_RESERVED2         0xc0000000UL


#define S_FW_PORT_CAP32_SPEED   0

#define M_FW_PORT_CAP32_SPEED   0xfff

#define V_FW_PORT_CAP32_SPEED(x)        ((x) << S_FW_PORT_CAP32_SPEED)

#define G_FW_PORT_CAP32_SPEED(x) \

    (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)


#define S_FW_PORT_CAP32_FC      16

#define M_FW_PORT_CAP32_FC      0x3

#define V_FW_PORT_CAP32_FC(x)   ((x) << S_FW_PORT_CAP32_FC)

#define G_FW_PORT_CAP32_FC(x) \

    (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)


#define S_FW_PORT_CAP32_802_3   18

#define M_FW_PORT_CAP32_802_3   0x3

#define V_FW_PORT_CAP32_802_3(x)        ((x) << S_FW_PORT_CAP32_802_3)

#define G_FW_PORT_CAP32_802_3(x) \

    (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)


#define S_FW_PORT_CAP32_ANEG    20

#define M_FW_PORT_CAP32_ANEG    0x1

#define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG)

#define G_FW_PORT_CAP32_ANEG(x) \

    (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)


#define S_FW_PORT_CAP32_FORCE_PAUSE     28

#define M_FW_PORT_CAP32_FORCE_PAUSE     0x1

#define V_FW_PORT_CAP32_FORCE_PAUSE(x)  ((x) << S_FW_PORT_CAP32_FORCE_PAUSE)

#define G_FW_PORT_CAP32_FORCE_PAUSE(x) \

    (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)


enum fw_port_mdi32 {

        FW_PORT_CAP32_MDI_UNCHANGED,

        FW_PORT_CAP32_MDI_AUTO,

        FW_PORT_CAP32_MDI_F_STRAIGHT,

        FW_PORT_CAP32_MDI_F_CROSSOVER

};


#define S_FW_PORT_CAP32_MDI 21

#define M_FW_PORT_CAP32_MDI 3

#define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)

#define G_FW_PORT_CAP32_MDI(x) \

    (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)


#define S_FW_PORT_CAP32_FEC     23

#define M_FW_PORT_CAP32_FEC     0x1f

#define V_FW_PORT_CAP32_FEC(x)  ((x) << S_FW_PORT_CAP32_FEC)

#define G_FW_PORT_CAP32_FEC(x) \

    (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)


/* macros to isolate various 32-bit Port Capabilities sub-fields */

#define CAP32_SPEED(__cap32) \

        (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32)


#define CAP32_FEC(__cap32) \

        (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)


#define CAP32_FC(__cap32) \

        (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)


static inline bool

fec_supported(uint32_t caps)

{


        return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G |

            FW_PORT_CAP32_SPEED_100G)) != 0);

}


enum fw_port_action {

        FW_PORT_ACTION_L1_CFG           = 0x0001,

        FW_PORT_ACTION_L2_CFG           = 0x0002,

        FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,

        FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,

        FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,

        FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,

        FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,

        FW_PORT_ACTION_DCB_READ_DET     = 0x0008,

        FW_PORT_ACTION_L1_CFG32         = 0x0009,

        FW_PORT_ACTION_GET_PORT_INFO32  = 0x000a,

        FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,

        FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,

        FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,

        FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,

        FW_PORT_ACTION_LPBK_SS_ASIC     = 0x0022,

        FW_PORT_ACTION_LPBK_WS_ASIC     = 0x0023,

        FW_PORT_ACTION_LPBK_WS_EXT_PHY  = 0x0025,

        FW_PORT_ACTION_LPBK_SS_EXT      = 0x0026,

        FW_PORT_ACTION_DIAGNOSTICS      = 0x0027,

        FW_PORT_ACTION_LPBK_SS_EXT_PHY  = 0x0028,

        FW_PORT_ACTION_PHY_RESET        = 0x0040,

        FW_PORT_ACTION_PMA_RESET        = 0x0041,

        FW_PORT_ACTION_PCS_RESET        = 0x0042,

        FW_PORT_ACTION_PHYXS_RESET      = 0x0043,

        FW_PORT_ACTION_DTEXS_REEST      = 0x0044,

        FW_PORT_ACTION_AN_RESET         = 0x0045,

};


enum fw_port_l2cfg_ctlbf {

        FW_PORT_L2_CTLBF_OVLAN0 = 0x01,

        FW_PORT_L2_CTLBF_OVLAN1 = 0x02,

        FW_PORT_L2_CTLBF_OVLAN2 = 0x04,

        FW_PORT_L2_CTLBF_OVLAN3 = 0x08,

        FW_PORT_L2_CTLBF_IVLAN  = 0x10,

        FW_PORT_L2_CTLBF_TXIPG  = 0x20,

        FW_PORT_L2_CTLBF_MTU    = 0x40,

        FW_PORT_L2_CTLBF_OVLAN_FILT     = 0x80,

};


enum fw_dcb_app_tlv_sf {

        FW_DCB_APP_SF_ETHERTYPE,

        FW_DCB_APP_SF_SOCKET_TCP,

        FW_DCB_APP_SF_SOCKET_UDP,

        FW_DCB_APP_SF_SOCKET_ALL,

};


enum fw_port_dcb_versions {

        FW_PORT_DCB_VER_UNKNOWN,

        FW_PORT_DCB_VER_CEE1D0,

        FW_PORT_DCB_VER_CEE1D01,

        FW_PORT_DCB_VER_IEEE,

        FW_PORT_DCB_VER_AUTO=7

};


enum fw_port_dcb_cfg {

        FW_PORT_DCB_CFG_PG      = 0x01,

        FW_PORT_DCB_CFG_PFC     = 0x02,

        FW_PORT_DCB_CFG_APPL    = 0x04

};


enum fw_port_dcb_cfg_rc {

        FW_PORT_DCB_CFG_SUCCESS = 0x0,

        FW_PORT_DCB_CFG_ERROR   = 0x1

};


enum fw_port_dcb_type {

        FW_PORT_DCB_TYPE_PGID           = 0x00,

        FW_PORT_DCB_TYPE_PGRATE         = 0x01,

        FW_PORT_DCB_TYPE_PRIORATE       = 0x02,

        FW_PORT_DCB_TYPE_PFC            = 0x03,

        FW_PORT_DCB_TYPE_APP_ID         = 0x04,

        FW_PORT_DCB_TYPE_CONTROL        = 0x05,

};


enum fw_port_dcb_feature_state {

        FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,

        FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,

        FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,

        FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,

};


enum fw_port_diag_ops {

        FW_PORT_DIAGS_TEMP              = 0x00,

        FW_PORT_DIAGS_TX_POWER          = 0x01,

        FW_PORT_DIAGS_RX_POWER          = 0x02,

        FW_PORT_DIAGS_TX_DIS            = 0x03,

};


struct fw_port_cmd {

        __be32 op_to_portid;

        __be32 action_to_len16;

        union fw_port {

                struct fw_port_l1cfg {

                        __be32 rcap;

                        __be32 r;

                } l1cfg;

                struct fw_port_l2cfg {

                        __u8   ctlbf;

                        __u8   ovlan3_to_ivlan0;

                        __be16 ivlantype;

                        __be16 txipg_force_pinfo;

                        __be16 mtu;

                        __be16 ovlan0mask;

                        __be16 ovlan0type;

                        __be16 ovlan1mask;

                        __be16 ovlan1type;

                        __be16 ovlan2mask;

                        __be16 ovlan2type;

                        __be16 ovlan3mask;

                        __be16 ovlan3type;

                } l2cfg;

                struct fw_port_info {

                        __be32 lstatus_to_modtype;

                        __be16 pcap;

                        __be16 acap;

                        __be16 mtu;

                        __u8   cbllen;

                        __u8   auxlinfo;

                        __u8   dcbxdis_pkd;

                        __u8   r8_lo;

                        __be16 lpacap;

                        __be64 r9;

                } info;

                struct fw_port_diags {

                        __u8   diagop;

                        __u8   r[3];

                        __be32 diagval;

                } diags;

                union fw_port_dcb {

                        struct fw_port_dcb_pgid {

                                __u8   type;

                                __u8   apply_pkd;

                                __u8   r10_lo[2];

                                __be32 pgid;

                                __be64 r11;

                        } pgid;

                        struct fw_port_dcb_pgrate {

                                __u8   type;

                                __u8   apply_pkd;

                                __u8   r10_lo[5];

                                __u8   num_tcs_supported;

                                __u8   pgrate[8];

                                __u8   tsa[8];

                        } pgrate;

                        struct fw_port_dcb_priorate {

                                __u8   type;

                                __u8   apply_pkd;

                                __u8   r10_lo[6];

                                __u8   strict_priorate[8];

                        } priorate;

                        struct fw_port_dcb_pfc {

                                __u8   type;

                                __u8   pfcen;

                                __u8   apply_pkd;

                                __u8   r10_lo[4];

                                __u8   max_pfc_tcs;

                                __be64 r11;

                        } pfc;

                        struct fw_port_app_priority {

                                __u8   type;

                                __u8   apply_pkd;

                                __u8   r10_lo;

                                __u8   idx;

                                __u8   user_prio_map;

                                __u8   sel_field;

                                __be16 protocolid;

                                __be64 r12;

                        } app_priority;

                        struct fw_port_dcb_control {

                                __u8   type;

                                __u8   all_syncd_pkd;

                                __be16 dcb_version_to_app_state;

                                __be32 r11;

                                __be64 r12;

                        } control;

                } dcb;

                struct fw_port_l1cfg32 {

                        __be32 rcap32;

                        __be32 r;

                } l1cfg32;

                struct fw_port_info32 {

                        __be32 lstatus32_to_cbllen32;

                        __be32 auxlinfo32_mtu32;

                        __be32 linkattr32;

                        __be32 pcaps32;

                        __be32 acaps32;

                        __be32 lpacaps32;

                } info32;

        } u;

};


#define S_FW_PORT_CMD_READ              22

#define M_FW_PORT_CMD_READ              0x1

#define V_FW_PORT_CMD_READ(x)           ((x) << S_FW_PORT_CMD_READ)

#define G_FW_PORT_CMD_READ(x)           \

    (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)

#define F_FW_PORT_CMD_READ              V_FW_PORT_CMD_READ(1U)


#define S_FW_PORT_CMD_PORTID            0

#define M_FW_PORT_CMD_PORTID            0xf

#define V_FW_PORT_CMD_PORTID(x)         ((x) << S_FW_PORT_CMD_PORTID)

#define G_FW_PORT_CMD_PORTID(x)         \

    (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)


#define S_FW_PORT_CMD_ACTION            16

#define M_FW_PORT_CMD_ACTION            0xffff

#define V_FW_PORT_CMD_ACTION(x)         ((x) << S_FW_PORT_CMD_ACTION)

#define G_FW_PORT_CMD_ACTION(x)         \

    (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)


#define S_FW_PORT_CMD_OVLAN3            7

#define M_FW_PORT_CMD_OVLAN3            0x1

#define V_FW_PORT_CMD_OVLAN3(x)         ((x) << S_FW_PORT_CMD_OVLAN3)

#define G_FW_PORT_CMD_OVLAN3(x)         \

    (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)

#define F_FW_PORT_CMD_OVLAN3            V_FW_PORT_CMD_OVLAN3(1U)


#define S_FW_PORT_CMD_OVLAN2            6

#define M_FW_PORT_CMD_OVLAN2            0x1

#define V_FW_PORT_CMD_OVLAN2(x)         ((x) << S_FW_PORT_CMD_OVLAN2)

#define G_FW_PORT_CMD_OVLAN2(x)         \

    (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)

#define F_FW_PORT_CMD_OVLAN2            V_FW_PORT_CMD_OVLAN2(1U)


#define S_FW_PORT_CMD_OVLAN1            5

#define M_FW_PORT_CMD_OVLAN1            0x1

#define V_FW_PORT_CMD_OVLAN1(x)         ((x) << S_FW_PORT_CMD_OVLAN1)

#define G_FW_PORT_CMD_OVLAN1(x)         \

    (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)

#define F_FW_PORT_CMD_OVLAN1            V_FW_PORT_CMD_OVLAN1(1U)


#define S_FW_PORT_CMD_OVLAN0            4

#define M_FW_PORT_CMD_OVLAN0            0x1

#define V_FW_PORT_CMD_OVLAN0(x)         ((x) << S_FW_PORT_CMD_OVLAN0)

#define G_FW_PORT_CMD_OVLAN0(x)         \

    (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)

#define F_FW_PORT_CMD_OVLAN0            V_FW_PORT_CMD_OVLAN0(1U)


#define S_FW_PORT_CMD_IVLAN0            3

#define M_FW_PORT_CMD_IVLAN0            0x1

#define V_FW_PORT_CMD_IVLAN0(x)         ((x) << S_FW_PORT_CMD_IVLAN0)

#define G_FW_PORT_CMD_IVLAN0(x)         \

    (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)

#define F_FW_PORT_CMD_IVLAN0            V_FW_PORT_CMD_IVLAN0(1U)


#define S_FW_PORT_CMD_OVLAN_FILT        2

#define M_FW_PORT_CMD_OVLAN_FILT        0x1

#define V_FW_PORT_CMD_OVLAN_FILT(x)     ((x) << S_FW_PORT_CMD_OVLAN_FILT)

#define G_FW_PORT_CMD_OVLAN_FILT(x)     \

    (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)

#define F_FW_PORT_CMD_OVLAN_FILT        V_FW_PORT_CMD_OVLAN_FILT(1U)


#define S_FW_PORT_CMD_TXIPG             3

#define M_FW_PORT_CMD_TXIPG             0x1fff

#define V_FW_PORT_CMD_TXIPG(x)          ((x) << S_FW_PORT_CMD_TXIPG)

#define G_FW_PORT_CMD_TXIPG(x)          \

    (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)


#define S_FW_PORT_CMD_FORCE_PINFO       0

#define M_FW_PORT_CMD_FORCE_PINFO       0x1

#define V_FW_PORT_CMD_FORCE_PINFO(x)    ((x) << S_FW_PORT_CMD_FORCE_PINFO)

#define G_FW_PORT_CMD_FORCE_PINFO(x)    \

    (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)

#define F_FW_PORT_CMD_FORCE_PINFO       V_FW_PORT_CMD_FORCE_PINFO(1U)


#define S_FW_PORT_CMD_LSTATUS           31

#define M_FW_PORT_CMD_LSTATUS           0x1

#define V_FW_PORT_CMD_LSTATUS(x)        ((x) << S_FW_PORT_CMD_LSTATUS)

#define G_FW_PORT_CMD_LSTATUS(x)        \

    (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)

#define F_FW_PORT_CMD_LSTATUS           V_FW_PORT_CMD_LSTATUS(1U)


#define S_FW_PORT_CMD_LSPEED            24

#define M_FW_PORT_CMD_LSPEED            0x3f

#define V_FW_PORT_CMD_LSPEED(x)         ((x) << S_FW_PORT_CMD_LSPEED)

#define G_FW_PORT_CMD_LSPEED(x)         \

    (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)


#define S_FW_PORT_CMD_TXPAUSE           23

#define M_FW_PORT_CMD_TXPAUSE           0x1

#define V_FW_PORT_CMD_TXPAUSE(x)        ((x) << S_FW_PORT_CMD_TXPAUSE)

#define G_FW_PORT_CMD_TXPAUSE(x)        \

    (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)

#define F_FW_PORT_CMD_TXPAUSE           V_FW_PORT_CMD_TXPAUSE(1U)


#define S_FW_PORT_CMD_RXPAUSE           22

#define M_FW_PORT_CMD_RXPAUSE           0x1

#define V_FW_PORT_CMD_RXPAUSE(x)        ((x) << S_FW_PORT_CMD_RXPAUSE)

#define G_FW_PORT_CMD_RXPAUSE(x)        \

    (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)

#define F_FW_PORT_CMD_RXPAUSE           V_FW_PORT_CMD_RXPAUSE(1U)


#define S_FW_PORT_CMD_MDIOCAP           21

#define M_FW_PORT_CMD_MDIOCAP           0x1

#define V_FW_PORT_CMD_MDIOCAP(x)        ((x) << S_FW_PORT_CMD_MDIOCAP)

#define G_FW_PORT_CMD_MDIOCAP(x)        \

    (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)

#define F_FW_PORT_CMD_MDIOCAP           V_FW_PORT_CMD_MDIOCAP(1U)


#define S_FW_PORT_CMD_MDIOADDR          16

#define M_FW_PORT_CMD_MDIOADDR          0x1f

#define V_FW_PORT_CMD_MDIOADDR(x)       ((x) << S_FW_PORT_CMD_MDIOADDR)

#define G_FW_PORT_CMD_MDIOADDR(x)       \

    (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)


#define S_FW_PORT_CMD_LPTXPAUSE         15

#define M_FW_PORT_CMD_LPTXPAUSE         0x1

#define V_FW_PORT_CMD_LPTXPAUSE(x)      ((x) << S_FW_PORT_CMD_LPTXPAUSE)

#define G_FW_PORT_CMD_LPTXPAUSE(x)      \

    (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)

#define F_FW_PORT_CMD_LPTXPAUSE         V_FW_PORT_CMD_LPTXPAUSE(1U)


#define S_FW_PORT_CMD_LPRXPAUSE         14

#define M_FW_PORT_CMD_LPRXPAUSE         0x1

#define V_FW_PORT_CMD_LPRXPAUSE(x)      ((x) << S_FW_PORT_CMD_LPRXPAUSE)

#define G_FW_PORT_CMD_LPRXPAUSE(x)      \

    (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)

#define F_FW_PORT_CMD_LPRXPAUSE         V_FW_PORT_CMD_LPRXPAUSE(1U)


#define S_FW_PORT_CMD_PTYPE             8

#define M_FW_PORT_CMD_PTYPE             0x1f

#define V_FW_PORT_CMD_PTYPE(x)          ((x) << S_FW_PORT_CMD_PTYPE)

#define G_FW_PORT_CMD_PTYPE(x)          \

    (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)


#define S_FW_PORT_CMD_LINKDNRC          5

#define M_FW_PORT_CMD_LINKDNRC          0x7

#define V_FW_PORT_CMD_LINKDNRC(x)       ((x) << S_FW_PORT_CMD_LINKDNRC)

#define G_FW_PORT_CMD_LINKDNRC(x)       \

    (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)


#define S_FW_PORT_CMD_MODTYPE           0

#define M_FW_PORT_CMD_MODTYPE           0x1f

#define V_FW_PORT_CMD_MODTYPE(x)        ((x) << S_FW_PORT_CMD_MODTYPE)

#define G_FW_PORT_CMD_MODTYPE(x)        \

    (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)


#define S_FW_PORT_AUXLINFO_KX4  2

#define M_FW_PORT_AUXLINFO_KX4  0x1

#define V_FW_PORT_AUXLINFO_KX4(x) \

    ((x) << S_FW_PORT_AUXLINFO_KX4)

#define G_FW_PORT_AUXLINFO_KX4(x) \

    (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)

#define F_FW_PORT_AUXLINFO_KX4  V_FW_PORT_AUXLINFO_KX4(1U)


#define S_FW_PORT_AUXLINFO_KR   1

#define M_FW_PORT_AUXLINFO_KR   0x1

#define V_FW_PORT_AUXLINFO_KR(x) \

    ((x) << S_FW_PORT_AUXLINFO_KR)

#define G_FW_PORT_AUXLINFO_KR(x) \

    (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)

#define F_FW_PORT_AUXLINFO_KR   V_FW_PORT_AUXLINFO_KR(1U)


#define S_FW_PORT_CMD_DCBXDIS           7

#define M_FW_PORT_CMD_DCBXDIS           0x1

#define V_FW_PORT_CMD_DCBXDIS(x)        ((x) << S_FW_PORT_CMD_DCBXDIS)

#define G_FW_PORT_CMD_DCBXDIS(x)        \

    (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)

#define F_FW_PORT_CMD_DCBXDIS           V_FW_PORT_CMD_DCBXDIS(1U)


#define S_FW_PORT_CMD_APPLY             7

#define M_FW_PORT_CMD_APPLY             0x1

#define V_FW_PORT_CMD_APPLY(x)          ((x) << S_FW_PORT_CMD_APPLY)

#define G_FW_PORT_CMD_APPLY(x)          \

    (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)

#define F_FW_PORT_CMD_APPLY             V_FW_PORT_CMD_APPLY(1U)


#define S_FW_PORT_CMD_ALL_SYNCD         7

#define M_FW_PORT_CMD_ALL_SYNCD         0x1

#define V_FW_PORT_CMD_ALL_SYNCD(x)      ((x) << S_FW_PORT_CMD_ALL_SYNCD)

#define G_FW_PORT_CMD_ALL_SYNCD(x)      \

    (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)

#define F_FW_PORT_CMD_ALL_SYNCD         V_FW_PORT_CMD_ALL_SYNCD(1U)


#define S_FW_PORT_CMD_DCB_VERSION       12

#define M_FW_PORT_CMD_DCB_VERSION       0x7

#define V_FW_PORT_CMD_DCB_VERSION(x)    ((x) << S_FW_PORT_CMD_DCB_VERSION)

#define G_FW_PORT_CMD_DCB_VERSION(x)    \

    (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)


#define S_FW_PORT_CMD_PFC_STATE         8

#define M_FW_PORT_CMD_PFC_STATE         0xf

#define V_FW_PORT_CMD_PFC_STATE(x)      ((x) << S_FW_PORT_CMD_PFC_STATE)

#define G_FW_PORT_CMD_PFC_STATE(x)      \

    (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)


#define S_FW_PORT_CMD_ETS_STATE         4

#define M_FW_PORT_CMD_ETS_STATE         0xf

#define V_FW_PORT_CMD_ETS_STATE(x)      ((x) << S_FW_PORT_CMD_ETS_STATE)

#define G_FW_PORT_CMD_ETS_STATE(x)      \

    (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)


#define S_FW_PORT_CMD_APP_STATE         0

#define M_FW_PORT_CMD_APP_STATE         0xf

#define V_FW_PORT_CMD_APP_STATE(x)      ((x) << S_FW_PORT_CMD_APP_STATE)

#define G_FW_PORT_CMD_APP_STATE(x)      \

    (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)


#define S_FW_PORT_CMD_LSTATUS32         31

#define M_FW_PORT_CMD_LSTATUS32         0x1

#define V_FW_PORT_CMD_LSTATUS32(x)      ((x) << S_FW_PORT_CMD_LSTATUS32)

#define G_FW_PORT_CMD_LSTATUS32(x)      \

    (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)

#define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)


#define S_FW_PORT_CMD_LINKDNRC32        28

#define M_FW_PORT_CMD_LINKDNRC32        0x7

#define V_FW_PORT_CMD_LINKDNRC32(x)     ((x) << S_FW_PORT_CMD_LINKDNRC32)

#define G_FW_PORT_CMD_LINKDNRC32(x)     \

    (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)


#define S_FW_PORT_CMD_DCBXDIS32         27

#define M_FW_PORT_CMD_DCBXDIS32         0x1

#define V_FW_PORT_CMD_DCBXDIS32(x)      ((x) << S_FW_PORT_CMD_DCBXDIS32)

#define G_FW_PORT_CMD_DCBXDIS32(x)      \

    (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)

#define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U)


#define S_FW_PORT_CMD_MDIOCAP32         26

#define M_FW_PORT_CMD_MDIOCAP32         0x1

#define V_FW_PORT_CMD_MDIOCAP32(x)      ((x) << S_FW_PORT_CMD_MDIOCAP32)

#define G_FW_PORT_CMD_MDIOCAP32(x)      \

    (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)

#define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)


#define S_FW_PORT_CMD_MDIOADDR32        21

#define M_FW_PORT_CMD_MDIOADDR32        0x1f

#define V_FW_PORT_CMD_MDIOADDR32(x)     ((x) << S_FW_PORT_CMD_MDIOADDR32)

#define G_FW_PORT_CMD_MDIOADDR32(x)     \

    (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)


#define S_FW_PORT_CMD_PORTTYPE32        13

#define M_FW_PORT_CMD_PORTTYPE32        0xff

#define V_FW_PORT_CMD_PORTTYPE32(x)     ((x) << S_FW_PORT_CMD_PORTTYPE32)

#define G_FW_PORT_CMD_PORTTYPE32(x)     \

    (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)


#define S_FW_PORT_CMD_MODTYPE32         8

#define M_FW_PORT_CMD_MODTYPE32         0x1f

#define V_FW_PORT_CMD_MODTYPE32(x)      ((x) << S_FW_PORT_CMD_MODTYPE32)

#define G_FW_PORT_CMD_MODTYPE32(x)      \

    (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)


#define S_FW_PORT_CMD_CBLLEN32          0

#define M_FW_PORT_CMD_CBLLEN32          0xff

#define V_FW_PORT_CMD_CBLLEN32(x)       ((x) << S_FW_PORT_CMD_CBLLEN32)

#define G_FW_PORT_CMD_CBLLEN32(x)       \

    (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)


#define S_FW_PORT_CMD_AUXLINFO32        24

#define M_FW_PORT_CMD_AUXLINFO32        0xff

#define V_FW_PORT_CMD_AUXLINFO32(x)     ((x) << S_FW_PORT_CMD_AUXLINFO32)

#define G_FW_PORT_CMD_AUXLINFO32(x)     \

    (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)


#define S_FW_PORT_AUXLINFO32_KX4        2

#define M_FW_PORT_AUXLINFO32_KX4        0x1

#define V_FW_PORT_AUXLINFO32_KX4(x) \

    ((x) << S_FW_PORT_AUXLINFO32_KX4)

#define G_FW_PORT_AUXLINFO32_KX4(x) \

    (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)

#define F_FW_PORT_AUXLINFO32_KX4        V_FW_PORT_AUXLINFO32_KX4(1U)


#define S_FW_PORT_AUXLINFO32_KR 1

#define M_FW_PORT_AUXLINFO32_KR 0x1

#define V_FW_PORT_AUXLINFO32_KR(x) \

    ((x) << S_FW_PORT_AUXLINFO32_KR)

#define G_FW_PORT_AUXLINFO32_KR(x) \

    (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)

#define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U)


#define S_FW_PORT_CMD_MTU32     0

#define M_FW_PORT_CMD_MTU32     0xffff

#define V_FW_PORT_CMD_MTU32(x)  ((x) << S_FW_PORT_CMD_MTU32)

#define G_FW_PORT_CMD_MTU32(x)  \

    (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)


/*

 *      These are configured into the VPD and hence tools that generate

 *      VPD may use this enumeration.

 *      extPHY  #lanes  T4_I2C  extI2C  BP_Eq   BP_ANEG Speed

 *

 *      REMEMBER:

 *          Update the Common Code t4_hw.c:t4_get_port_type_description()

 *          with any new Firmware Port Technology Types!

 */

enum fw_port_type {

        FW_PORT_TYPE_FIBER_XFI  =  0,   /* Y, 1, N, Y, N, N, 10G */

        FW_PORT_TYPE_FIBER_XAUI =  1,   /* Y, 4, N, Y, N, N, 10G */

        FW_PORT_TYPE_BT_SGMII   =  2,   /* Y, 1, No, No, No, No, 1G/100M */

        FW_PORT_TYPE_BT_XFI     =  3,   /* Y, 1, No, No, No, No, 10G/1G/100M */

        FW_PORT_TYPE_BT_XAUI    =  4,   /* Y, 4, No, No, No, No, 10G/1G/100M */

        FW_PORT_TYPE_KX4        =  5,   /* No, 4, No, No, Yes, Yes, 10G */

        FW_PORT_TYPE_CX4        =  6,   /* No, 4, No, No, No, No, 10G */

        FW_PORT_TYPE_KX         =  7,   /* No, 1, No, No, Yes, No, 1G */

        FW_PORT_TYPE_KR         =  8,   /* No, 1, No, No, Yes, Yes, 10G */

        FW_PORT_TYPE_SFP        =  9,   /* No, 1, Yes, No, No, No, 10G */

        FW_PORT_TYPE_BP_AP      = 10,   /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */

        FW_PORT_TYPE_BP4_AP     = 11,   /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */

        FW_PORT_TYPE_QSFP_10G   = 12,   /* No, 1, Yes, No, No, No, 10G */

        FW_PORT_TYPE_QSA        = 13,   /* No, 1, Yes, No, No, No, 10G */

        FW_PORT_TYPE_QSFP       = 14,   /* No, 4, Yes, No, No, No, 40G */

        FW_PORT_TYPE_BP40_BA    = 15,   /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */

        FW_PORT_TYPE_KR4_100G   = 16,   /* No, 4, 100G/40G/25G, Backplane */

        FW_PORT_TYPE_CR4_QSFP   = 17,   /* No, 4, 100G/40G/25G */

        FW_PORT_TYPE_CR_QSFP    = 18,   /* No, 1, 25G Spider cable */

        FW_PORT_TYPE_CR2_QSFP   = 19,   /* No, 2, 50G */

        FW_PORT_TYPE_SFP28      = 20,   /* No, 1, 25G/10G/1G */

        FW_PORT_TYPE_KR_SFP28   = 21,   /* No, 1, 25G/10G/1G using Backplane */

        FW_PORT_TYPE_KR_XLAUI   = 22,   /* No, 4, 40G/10G/1G, No AN*/

        FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE

};


static inline bool

is_bt(enum fw_port_type port_type)

{

        return (port_type == FW_PORT_TYPE_BT_SGMII ||

            port_type == FW_PORT_TYPE_BT_XFI ||

            port_type == FW_PORT_TYPE_BT_XAUI);

}


/* These are read from module's EEPROM and determined once the

   module is inserted. */

enum fw_port_module_type {

        FW_PORT_MOD_TYPE_NA             = 0x0,

        FW_PORT_MOD_TYPE_LR             = 0x1,

        FW_PORT_MOD_TYPE_SR             = 0x2,

        FW_PORT_MOD_TYPE_ER             = 0x3,

        FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,

        FW_PORT_MOD_TYPE_TWINAX_ACTIVE  = 0x5,

        FW_PORT_MOD_TYPE_LRM            = 0x6,

        FW_PORT_MOD_TYPE_ERROR          = M_FW_PORT_CMD_MODTYPE - 3,

        FW_PORT_MOD_TYPE_UNKNOWN        = M_FW_PORT_CMD_MODTYPE - 2,

        FW_PORT_MOD_TYPE_NOTSUPPORTED   = M_FW_PORT_CMD_MODTYPE - 1,

        FW_PORT_MOD_TYPE_NONE           = M_FW_PORT_CMD_MODTYPE

};


/* used by FW and tools may use this to generate VPD */

enum fw_port_mod_sub_type {

        FW_PORT_MOD_SUB_TYPE_NA,

        FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,

        FW_PORT_MOD_SUB_TYPE_TN8022=0x2,

        FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,

        FW_PORT_MOD_SUB_TYPE_88x3120=0x4,

        FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,

        FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,

        FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,

        FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,


        /*

         * The following will never been in the VPD.  They are TWINAX cable

         * lengths decoded from SFP+ module i2c PROMs.  These should almost

         * certainly go somewhere else ...

         */

        FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,

        FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,

        FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,

        FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,

};


/* link down reason codes (3b) */

enum fw_port_link_dn_rc {

        FW_PORT_LINK_DN_RC_NONE,

        FW_PORT_LINK_DN_RC_REMFLT,      /* Remote fault detected */

        FW_PORT_LINK_DN_ANEG_F,         /* Auto-negotiation fault */

        FW_PORT_LINK_DN_RESERVED3,

        FW_PORT_LINK_DN_OVERHEAT,       /* Port overheated */

        FW_PORT_LINK_DN_UNKNOWN,        /* Unable to determine reason */

        FW_PORT_LINK_DN_RX_LOS,         /* No RX signal detected */

        FW_PORT_LINK_DN_RESERVED7

};

enum fw_port_stats_tx_index {

        FW_STAT_TX_PORT_BYTES_IX = 0,

        FW_STAT_TX_PORT_FRAMES_IX,

        FW_STAT_TX_PORT_BCAST_IX,

        FW_STAT_TX_PORT_MCAST_IX,

        FW_STAT_TX_PORT_UCAST_IX,

        FW_STAT_TX_PORT_ERROR_IX,

        FW_STAT_TX_PORT_64B_IX,

        FW_STAT_TX_PORT_65B_127B_IX,

        FW_STAT_TX_PORT_128B_255B_IX,

        FW_STAT_TX_PORT_256B_511B_IX,

        FW_STAT_TX_PORT_512B_1023B_IX,

        FW_STAT_TX_PORT_1024B_1518B_IX,

        FW_STAT_TX_PORT_1519B_MAX_IX,

        FW_STAT_TX_PORT_DROP_IX,

        FW_STAT_TX_PORT_PAUSE_IX,

        FW_STAT_TX_PORT_PPP0_IX,

        FW_STAT_TX_PORT_PPP1_IX,

        FW_STAT_TX_PORT_PPP2_IX,

        FW_STAT_TX_PORT_PPP3_IX,

        FW_STAT_TX_PORT_PPP4_IX,

        FW_STAT_TX_PORT_PPP5_IX,

        FW_STAT_TX_PORT_PPP6_IX,

        FW_STAT_TX_PORT_PPP7_IX,

        FW_NUM_PORT_TX_STATS

};


enum fw_port_stat_rx_index {

        FW_STAT_RX_PORT_BYTES_IX = 0,

        FW_STAT_RX_PORT_FRAMES_IX,

        FW_STAT_RX_PORT_BCAST_IX,

        FW_STAT_RX_PORT_MCAST_IX,

        FW_STAT_RX_PORT_UCAST_IX,

        FW_STAT_RX_PORT_MTU_ERROR_IX,

        FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,

        FW_STAT_RX_PORT_CRC_ERROR_IX,

        FW_STAT_RX_PORT_LEN_ERROR_IX,

        FW_STAT_RX_PORT_SYM_ERROR_IX,

        FW_STAT_RX_PORT_64B_IX,

        FW_STAT_RX_PORT_65B_127B_IX,

        FW_STAT_RX_PORT_128B_255B_IX,

        FW_STAT_RX_PORT_256B_511B_IX,

        FW_STAT_RX_PORT_512B_1023B_IX,

        FW_STAT_RX_PORT_1024B_1518B_IX,

        FW_STAT_RX_PORT_1519B_MAX_IX,

        FW_STAT_RX_PORT_PAUSE_IX,

        FW_STAT_RX_PORT_PPP0_IX,

        FW_STAT_RX_PORT_PPP1_IX,

        FW_STAT_RX_PORT_PPP2_IX,

        FW_STAT_RX_PORT_PPP3_IX,

        FW_STAT_RX_PORT_PPP4_IX,

        FW_STAT_RX_PORT_PPP5_IX,

        FW_STAT_RX_PORT_PPP6_IX,

        FW_STAT_RX_PORT_PPP7_IX,

        FW_STAT_RX_PORT_LESS_64B_IX,

        FW_STAT_RX_PORT_MAC_ERROR_IX,

        FW_NUM_PORT_RX_STATS

};

/* port stats */

#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \

                                 FW_NUM_PORT_RX_STATS)


struct fw_port_stats_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        union fw_port_stats {

                struct fw_port_stats_ctl {

                        __u8   nstats_bg_bm;

                        __u8   tx_ix;

                        __be16 r6;

                        __be32 r7;

                        __be64 stat0;

                        __be64 stat1;

                        __be64 stat2;

                        __be64 stat3;

                        __be64 stat4;

                        __be64 stat5;

                } ctl;

                struct fw_port_stats_all {

                        __be64 tx_bytes;

                        __be64 tx_frames;

                        __be64 tx_bcast;

                        __be64 tx_mcast;

                        __be64 tx_ucast;

                        __be64 tx_error;

                        __be64 tx_64b;

                        __be64 tx_65b_127b;

                        __be64 tx_128b_255b;

                        __be64 tx_256b_511b;

                        __be64 tx_512b_1023b;

                        __be64 tx_1024b_1518b;

                        __be64 tx_1519b_max;

                        __be64 tx_drop;

                        __be64 tx_pause;

                        __be64 tx_ppp0;

                        __be64 tx_ppp1;

                        __be64 tx_ppp2;

                        __be64 tx_ppp3;

                        __be64 tx_ppp4;

                        __be64 tx_ppp5;

                        __be64 tx_ppp6;

                        __be64 tx_ppp7;

                        __be64 rx_bytes;

                        __be64 rx_frames;

                        __be64 rx_bcast;

                        __be64 rx_mcast;

                        __be64 rx_ucast;

                        __be64 rx_mtu_error;

                        __be64 rx_mtu_crc_error;

                        __be64 rx_crc_error;

                        __be64 rx_len_error;

                        __be64 rx_sym_error;

                        __be64 rx_64b;

                        __be64 rx_65b_127b;

                        __be64 rx_128b_255b;

                        __be64 rx_256b_511b;

                        __be64 rx_512b_1023b;

                        __be64 rx_1024b_1518b;

                        __be64 rx_1519b_max;

                        __be64 rx_pause;

                        __be64 rx_ppp0;

                        __be64 rx_ppp1;

                        __be64 rx_ppp2;

                        __be64 rx_ppp3;

                        __be64 rx_ppp4;

                        __be64 rx_ppp5;

                        __be64 rx_ppp6;

                        __be64 rx_ppp7;

                        __be64 rx_less_64b;

                        __be64 rx_bg_drop;

                        __be64 rx_bg_trunc;

                } all;

        } u;

};


#define S_FW_PORT_STATS_CMD_NSTATS      4

#define M_FW_PORT_STATS_CMD_NSTATS      0x7

#define V_FW_PORT_STATS_CMD_NSTATS(x)   ((x) << S_FW_PORT_STATS_CMD_NSTATS)

#define G_FW_PORT_STATS_CMD_NSTATS(x)   \

    (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)


#define S_FW_PORT_STATS_CMD_BG_BM       0

#define M_FW_PORT_STATS_CMD_BG_BM       0x3

#define V_FW_PORT_STATS_CMD_BG_BM(x)    ((x) << S_FW_PORT_STATS_CMD_BG_BM)

#define G_FW_PORT_STATS_CMD_BG_BM(x)    \

    (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)


#define S_FW_PORT_STATS_CMD_TX          7

#define M_FW_PORT_STATS_CMD_TX          0x1

#define V_FW_PORT_STATS_CMD_TX(x)       ((x) << S_FW_PORT_STATS_CMD_TX)

#define G_FW_PORT_STATS_CMD_TX(x)       \

    (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)

#define F_FW_PORT_STATS_CMD_TX          V_FW_PORT_STATS_CMD_TX(1U)


#define S_FW_PORT_STATS_CMD_IX          0

#define M_FW_PORT_STATS_CMD_IX          0x3f

#define V_FW_PORT_STATS_CMD_IX(x)       ((x) << S_FW_PORT_STATS_CMD_IX)

#define G_FW_PORT_STATS_CMD_IX(x)       \

    (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)


/* port loopback stats */

#define FW_NUM_LB_STATS 14

enum fw_port_lb_stats_index {

        FW_STAT_LB_PORT_BYTES_IX,

        FW_STAT_LB_PORT_FRAMES_IX,

        FW_STAT_LB_PORT_BCAST_IX,

        FW_STAT_LB_PORT_MCAST_IX,

        FW_STAT_LB_PORT_UCAST_IX,

        FW_STAT_LB_PORT_ERROR_IX,

        FW_STAT_LB_PORT_64B_IX,

        FW_STAT_LB_PORT_65B_127B_IX,

        FW_STAT_LB_PORT_128B_255B_IX,

        FW_STAT_LB_PORT_256B_511B_IX,

        FW_STAT_LB_PORT_512B_1023B_IX,

        FW_STAT_LB_PORT_1024B_1518B_IX,

        FW_STAT_LB_PORT_1519B_MAX_IX,

        FW_STAT_LB_PORT_DROP_FRAMES_IX

};


struct fw_port_lb_stats_cmd {

        __be32 op_to_lbport;

        __be32 retval_len16;

        union fw_port_lb_stats {

                struct fw_port_lb_stats_ctl {

                        __u8   nstats_bg_bm;

                        __u8   ix_pkd;

                        __be16 r6;

                        __be32 r7;

                        __be64 stat0;

                        __be64 stat1;

                        __be64 stat2;

                        __be64 stat3;

                        __be64 stat4;

                        __be64 stat5;

                } ctl;

                struct fw_port_lb_stats_all {

                        __be64 tx_bytes;

                        __be64 tx_frames;

                        __be64 tx_bcast;

                        __be64 tx_mcast;

                        __be64 tx_ucast;

                        __be64 tx_error;

                        __be64 tx_64b;

                        __be64 tx_65b_127b;

                        __be64 tx_128b_255b;

                        __be64 tx_256b_511b;

                        __be64 tx_512b_1023b;

                        __be64 tx_1024b_1518b;

                        __be64 tx_1519b_max;

                        __be64 rx_lb_drop;

                        __be64 rx_lb_trunc;

                } all;

        } u;

};


#define S_FW_PORT_LB_STATS_CMD_LBPORT   0

#define M_FW_PORT_LB_STATS_CMD_LBPORT   0xf

#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \

    ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)

#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \

    (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)


#define S_FW_PORT_LB_STATS_CMD_NSTATS   4

#define M_FW_PORT_LB_STATS_CMD_NSTATS   0x7

#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \

    ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)

#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \

    (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)


#define S_FW_PORT_LB_STATS_CMD_BG_BM    0

#define M_FW_PORT_LB_STATS_CMD_BG_BM    0x3

#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)

#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \

    (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)


#define S_FW_PORT_LB_STATS_CMD_IX       0

#define M_FW_PORT_LB_STATS_CMD_IX       0xf

#define V_FW_PORT_LB_STATS_CMD_IX(x)    ((x) << S_FW_PORT_LB_STATS_CMD_IX)

#define G_FW_PORT_LB_STATS_CMD_IX(x)    \

    (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)


/* Trace related defines */

#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240

#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE  2560


struct fw_port_trace_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        __be16 traceen_to_pciech;

        __be16 qnum;

        __be32 r5;

};


#define S_FW_PORT_TRACE_CMD_PORTID      0

#define M_FW_PORT_TRACE_CMD_PORTID      0xf

#define V_FW_PORT_TRACE_CMD_PORTID(x)   ((x) << S_FW_PORT_TRACE_CMD_PORTID)

#define G_FW_PORT_TRACE_CMD_PORTID(x)   \

    (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)


#define S_FW_PORT_TRACE_CMD_TRACEEN     15

#define M_FW_PORT_TRACE_CMD_TRACEEN     0x1

#define V_FW_PORT_TRACE_CMD_TRACEEN(x)  ((x) << S_FW_PORT_TRACE_CMD_TRACEEN)

#define G_FW_PORT_TRACE_CMD_TRACEEN(x)  \

    (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)

#define F_FW_PORT_TRACE_CMD_TRACEEN     V_FW_PORT_TRACE_CMD_TRACEEN(1U)


#define S_FW_PORT_TRACE_CMD_FLTMODE     14

#define M_FW_PORT_TRACE_CMD_FLTMODE     0x1

#define V_FW_PORT_TRACE_CMD_FLTMODE(x)  ((x) << S_FW_PORT_TRACE_CMD_FLTMODE)

#define G_FW_PORT_TRACE_CMD_FLTMODE(x)  \

    (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)

#define F_FW_PORT_TRACE_CMD_FLTMODE     V_FW_PORT_TRACE_CMD_FLTMODE(1U)


#define S_FW_PORT_TRACE_CMD_DUPLEN      13

#define M_FW_PORT_TRACE_CMD_DUPLEN      0x1

#define V_FW_PORT_TRACE_CMD_DUPLEN(x)   ((x) << S_FW_PORT_TRACE_CMD_DUPLEN)

#define G_FW_PORT_TRACE_CMD_DUPLEN(x)   \

    (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)

#define F_FW_PORT_TRACE_CMD_DUPLEN      V_FW_PORT_TRACE_CMD_DUPLEN(1U)


#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8

#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f

#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \

    ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)

#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \

    (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \

     M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)


#define S_FW_PORT_TRACE_CMD_PCIECH      6

#define M_FW_PORT_TRACE_CMD_PCIECH      0x3

#define V_FW_PORT_TRACE_CMD_PCIECH(x)   ((x) << S_FW_PORT_TRACE_CMD_PCIECH)

#define G_FW_PORT_TRACE_CMD_PCIECH(x)   \

    (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)


struct fw_port_trace_mmap_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        __be32 fid_to_skipoffset;

        __be32 minpktsize_capturemax;

        __u8   map[224];

};


#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0

#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf

#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)

#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \

     M_FW_PORT_TRACE_MMAP_CMD_PORTID)


#define S_FW_PORT_TRACE_MMAP_CMD_FID    30

#define M_FW_PORT_TRACE_MMAP_CMD_FID    0x3

#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)

#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)


#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29

#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1

#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)

#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \

     M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)

#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)


#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28

#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1

#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)

#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \

     M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)

#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)


#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8

#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f

#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)

#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \

     M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)


#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0

#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f

#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)

#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \

     M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)


#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18

#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff

#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)

#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \

     M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)


#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0

#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff

#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \

    ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)

#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \

    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \

     M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)


enum fw_ptp_subop {


        /* none */

        FW_PTP_SC_INIT_TIMER            = 0x00,

        FW_PTP_SC_TX_TYPE               = 0x01,


        /* init */

        FW_PTP_SC_RXTIME_STAMP          = 0x08,

        FW_PTP_SC_RDRX_TYPE             = 0x09,


        /* ts */

        FW_PTP_SC_ADJ_FREQ              = 0x10,

        FW_PTP_SC_ADJ_TIME              = 0x11,

        FW_PTP_SC_ADJ_FTIME             = 0x12,

        FW_PTP_SC_WALL_CLOCK            = 0x13,

        FW_PTP_SC_GET_TIME              = 0x14,

        FW_PTP_SC_SET_TIME              = 0x15,

};


struct fw_ptp_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        union fw_ptp {

                struct fw_ptp_sc {

                        __u8   sc;

                        __u8   r3[7];

                } scmd;

                struct fw_ptp_init {

                        __u8   sc;

                        __u8   txchan;

                        __be16 absid;

                        __be16 mode;

                        __be16 ptp_rx_ctrl_pkd;

                } init;

                struct fw_ptp_ts {

                        __u8   sc;

                        __u8   sign;

                        __be16 r3;

                        __be32 ppb;

                        __be64 tm;

                } ts;

        } u;

        __be64 r3;

};


#define S_FW_PTP_CMD_PORTID             0

#define M_FW_PTP_CMD_PORTID             0xf

#define V_FW_PTP_CMD_PORTID(x)          ((x) << S_FW_PTP_CMD_PORTID)

#define G_FW_PTP_CMD_PORTID(x)          \

    (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)


#define S_FW_PTP_CMD_PTP_RX_CTRL        15

#define M_FW_PTP_CMD_PTP_RX_CTRL        0x1

#define V_FW_PTP_CMD_PTP_RX_CTRL(x)     ((x) << S_FW_PTP_CMD_PTP_RX_CTRL)

#define G_FW_PTP_CMD_PTP_RX_CTRL(x)     \

    (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)

#define F_FW_PTP_CMD_PTP_RX_CTRL        V_FW_PTP_CMD_PTP_RX_CTRL(1U)


struct fw_rss_ind_tbl_cmd {

        __be32 op_to_viid;

        __be32 retval_len16;

        __be16 niqid;

        __be16 startidx;

        __be32 r3;

        __be32 iq0_to_iq2;

        __be32 iq3_to_iq5;

        __be32 iq6_to_iq8;

        __be32 iq9_to_iq11;

        __be32 iq12_to_iq14;

        __be32 iq15_to_iq17;

        __be32 iq18_to_iq20;

        __be32 iq21_to_iq23;

        __be32 iq24_to_iq26;

        __be32 iq27_to_iq29;

        __be32 iq30_iq31;

        __be32 r15_lo;

};


#define S_FW_RSS_IND_TBL_CMD_VIID       0

#define M_FW_RSS_IND_TBL_CMD_VIID       0xfff

#define V_FW_RSS_IND_TBL_CMD_VIID(x)    ((x) << S_FW_RSS_IND_TBL_CMD_VIID)

#define G_FW_RSS_IND_TBL_CMD_VIID(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)


#define S_FW_RSS_IND_TBL_CMD_IQ0        20

#define M_FW_RSS_IND_TBL_CMD_IQ0        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ0(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)

#define G_FW_RSS_IND_TBL_CMD_IQ0(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)


#define S_FW_RSS_IND_TBL_CMD_IQ1        10

#define M_FW_RSS_IND_TBL_CMD_IQ1        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ1(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)

#define G_FW_RSS_IND_TBL_CMD_IQ1(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)


#define S_FW_RSS_IND_TBL_CMD_IQ2        0

#define M_FW_RSS_IND_TBL_CMD_IQ2        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ2(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)

#define G_FW_RSS_IND_TBL_CMD_IQ2(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)


#define S_FW_RSS_IND_TBL_CMD_IQ3        20

#define M_FW_RSS_IND_TBL_CMD_IQ3        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ3(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ3)

#define G_FW_RSS_IND_TBL_CMD_IQ3(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)


#define S_FW_RSS_IND_TBL_CMD_IQ4        10

#define M_FW_RSS_IND_TBL_CMD_IQ4        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ4(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ4)

#define G_FW_RSS_IND_TBL_CMD_IQ4(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)


#define S_FW_RSS_IND_TBL_CMD_IQ5        0

#define M_FW_RSS_IND_TBL_CMD_IQ5        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ5(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ5)

#define G_FW_RSS_IND_TBL_CMD_IQ5(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)


#define S_FW_RSS_IND_TBL_CMD_IQ6        20

#define M_FW_RSS_IND_TBL_CMD_IQ6        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ6(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ6)

#define G_FW_RSS_IND_TBL_CMD_IQ6(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)


#define S_FW_RSS_IND_TBL_CMD_IQ7        10

#define M_FW_RSS_IND_TBL_CMD_IQ7        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ7(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ7)

#define G_FW_RSS_IND_TBL_CMD_IQ7(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)


#define S_FW_RSS_IND_TBL_CMD_IQ8        0

#define M_FW_RSS_IND_TBL_CMD_IQ8        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ8(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ8)

#define G_FW_RSS_IND_TBL_CMD_IQ8(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)


#define S_FW_RSS_IND_TBL_CMD_IQ9        20

#define M_FW_RSS_IND_TBL_CMD_IQ9        0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ9(x)     ((x) << S_FW_RSS_IND_TBL_CMD_IQ9)

#define G_FW_RSS_IND_TBL_CMD_IQ9(x)     \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)


#define S_FW_RSS_IND_TBL_CMD_IQ10       10

#define M_FW_RSS_IND_TBL_CMD_IQ10       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ10(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ10)

#define G_FW_RSS_IND_TBL_CMD_IQ10(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)


#define S_FW_RSS_IND_TBL_CMD_IQ11       0

#define M_FW_RSS_IND_TBL_CMD_IQ11       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ11(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ11)

#define G_FW_RSS_IND_TBL_CMD_IQ11(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)


#define S_FW_RSS_IND_TBL_CMD_IQ12       20

#define M_FW_RSS_IND_TBL_CMD_IQ12       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ12(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ12)

#define G_FW_RSS_IND_TBL_CMD_IQ12(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)


#define S_FW_RSS_IND_TBL_CMD_IQ13       10

#define M_FW_RSS_IND_TBL_CMD_IQ13       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ13(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ13)

#define G_FW_RSS_IND_TBL_CMD_IQ13(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)


#define S_FW_RSS_IND_TBL_CMD_IQ14       0

#define M_FW_RSS_IND_TBL_CMD_IQ14       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ14(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ14)

#define G_FW_RSS_IND_TBL_CMD_IQ14(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)


#define S_FW_RSS_IND_TBL_CMD_IQ15       20

#define M_FW_RSS_IND_TBL_CMD_IQ15       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ15(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ15)

#define G_FW_RSS_IND_TBL_CMD_IQ15(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)


#define S_FW_RSS_IND_TBL_CMD_IQ16       10

#define M_FW_RSS_IND_TBL_CMD_IQ16       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ16(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ16)

#define G_FW_RSS_IND_TBL_CMD_IQ16(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)


#define S_FW_RSS_IND_TBL_CMD_IQ17       0

#define M_FW_RSS_IND_TBL_CMD_IQ17       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ17(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ17)

#define G_FW_RSS_IND_TBL_CMD_IQ17(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)


#define S_FW_RSS_IND_TBL_CMD_IQ18       20

#define M_FW_RSS_IND_TBL_CMD_IQ18       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ18(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ18)

#define G_FW_RSS_IND_TBL_CMD_IQ18(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)


#define S_FW_RSS_IND_TBL_CMD_IQ19       10

#define M_FW_RSS_IND_TBL_CMD_IQ19       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ19(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ19)

#define G_FW_RSS_IND_TBL_CMD_IQ19(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)


#define S_FW_RSS_IND_TBL_CMD_IQ20       0

#define M_FW_RSS_IND_TBL_CMD_IQ20       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ20(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ20)

#define G_FW_RSS_IND_TBL_CMD_IQ20(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)


#define S_FW_RSS_IND_TBL_CMD_IQ21       20

#define M_FW_RSS_IND_TBL_CMD_IQ21       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ21(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ21)

#define G_FW_RSS_IND_TBL_CMD_IQ21(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)


#define S_FW_RSS_IND_TBL_CMD_IQ22       10

#define M_FW_RSS_IND_TBL_CMD_IQ22       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ22(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ22)

#define G_FW_RSS_IND_TBL_CMD_IQ22(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)


#define S_FW_RSS_IND_TBL_CMD_IQ23       0

#define M_FW_RSS_IND_TBL_CMD_IQ23       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ23(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ23)

#define G_FW_RSS_IND_TBL_CMD_IQ23(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)


#define S_FW_RSS_IND_TBL_CMD_IQ24       20

#define M_FW_RSS_IND_TBL_CMD_IQ24       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ24(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ24)

#define G_FW_RSS_IND_TBL_CMD_IQ24(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)


#define S_FW_RSS_IND_TBL_CMD_IQ25       10

#define M_FW_RSS_IND_TBL_CMD_IQ25       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ25(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ25)

#define G_FW_RSS_IND_TBL_CMD_IQ25(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)


#define S_FW_RSS_IND_TBL_CMD_IQ26       0

#define M_FW_RSS_IND_TBL_CMD_IQ26       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ26(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ26)

#define G_FW_RSS_IND_TBL_CMD_IQ26(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)


#define S_FW_RSS_IND_TBL_CMD_IQ27       20

#define M_FW_RSS_IND_TBL_CMD_IQ27       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ27(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ27)

#define G_FW_RSS_IND_TBL_CMD_IQ27(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)


#define S_FW_RSS_IND_TBL_CMD_IQ28       10

#define M_FW_RSS_IND_TBL_CMD_IQ28       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ28(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ28)

#define G_FW_RSS_IND_TBL_CMD_IQ28(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)


#define S_FW_RSS_IND_TBL_CMD_IQ29       0

#define M_FW_RSS_IND_TBL_CMD_IQ29       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ29(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ29)

#define G_FW_RSS_IND_TBL_CMD_IQ29(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)


#define S_FW_RSS_IND_TBL_CMD_IQ30       20

#define M_FW_RSS_IND_TBL_CMD_IQ30       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ30(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ30)

#define G_FW_RSS_IND_TBL_CMD_IQ30(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)


#define S_FW_RSS_IND_TBL_CMD_IQ31       10

#define M_FW_RSS_IND_TBL_CMD_IQ31       0x3ff

#define V_FW_RSS_IND_TBL_CMD_IQ31(x)    ((x) << S_FW_RSS_IND_TBL_CMD_IQ31)

#define G_FW_RSS_IND_TBL_CMD_IQ31(x)    \

    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)


struct fw_rss_glb_config_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        union fw_rss_glb_config {

                struct fw_rss_glb_config_manual {

                        __be32 mode_pkd;

                        __be32 r3;

                        __be64 r4;

                        __be64 r5;

                } manual;

                struct fw_rss_glb_config_basicvirtual {

                        __be32 mode_keymode;

                        __be32 synmapen_to_hashtoeplitz;

                        __be64 r8;

                        __be64 r9;

                } basicvirtual;

        } u;

};


#define S_FW_RSS_GLB_CONFIG_CMD_MODE    28

#define M_FW_RSS_GLB_CONFIG_CMD_MODE    0xf

#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)

#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)


#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0

#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1

#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX          1


#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26

#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3

#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)

#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \

     M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)


#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY    0

#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1

#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY  2

#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3


#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8

#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)

#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \

     M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)

#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7

#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)

#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \

     M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)

#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \

    V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6

#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)

#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \

     M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)

#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \

    V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5

#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)

#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \

     M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)

#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \

    V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4

#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)

#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \

     M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)

#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \

    V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3

#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)

#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \

     M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)

#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2

#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)

#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \

     M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)

#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1

#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)

#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \

     M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)

#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \

    V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)


#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0

#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1

#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \

    ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)

#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \

    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \

     M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)

#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \

    V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)


struct fw_rss_vi_config_cmd {

        __be32 op_to_viid;

        __be32 retval_len16;

        union fw_rss_vi_config {

                struct fw_rss_vi_config_manual {

                        __be64 r3;

                        __be64 r4;

                        __be64 r5;

                } manual;

                struct fw_rss_vi_config_basicvirtual {

                        __be32 r6;

                        __be32 defaultq_to_udpen;

                        __be32 secretkeyidx_pkd;

                        __be32 secretkeyxor;

                        __be64 r10;

                } basicvirtual;

        } u;

};


#define S_FW_RSS_VI_CONFIG_CMD_VIID     0

#define M_FW_RSS_VI_CONFIG_CMD_VIID     0xfff

#define V_FW_RSS_VI_CONFIG_CMD_VIID(x)  ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)

#define G_FW_RSS_VI_CONFIG_CMD_VIID(x)  \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)


#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16

#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff

#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \

    ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)

#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \

     M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)


#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4

#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1

#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \

    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)

#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \

     M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)

#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \

    V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)


#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3

#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1

#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \

    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)

#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \

     M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)

#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \

    V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)


#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2

#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1

#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \

    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)

#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \

     M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)

#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \

    V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)


#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1

#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1

#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \

    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)

#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \

     M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)

#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \

    V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)


#define S_FW_RSS_VI_CONFIG_CMD_UDPEN    0

#define M_FW_RSS_VI_CONFIG_CMD_UDPEN    0x1

#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)

#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)

#define F_FW_RSS_VI_CONFIG_CMD_UDPEN    V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)


#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0

#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf

#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \

    ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)

#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \

    (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \

     M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)


enum fw_sched_sc {

        FW_SCHED_SC_CONFIG              = 0,

        FW_SCHED_SC_PARAMS              = 1,

};


enum fw_sched_type {

        FW_SCHED_TYPE_PKTSCHED          = 0,

        FW_SCHED_TYPE_STREAMSCHED       = 1,

};


enum fw_sched_params_level {

        FW_SCHED_PARAMS_LEVEL_CL_RL     = 0,

        FW_SCHED_PARAMS_LEVEL_CL_WRR    = 1,

        FW_SCHED_PARAMS_LEVEL_CH_RL     = 2,

};


enum fw_sched_params_mode {

        FW_SCHED_PARAMS_MODE_CLASS      = 0,

        FW_SCHED_PARAMS_MODE_FLOW       = 1,

};


enum fw_sched_params_unit {

        FW_SCHED_PARAMS_UNIT_BITRATE    = 0,

        FW_SCHED_PARAMS_UNIT_PKTRATE    = 1,

};


enum fw_sched_params_rate {

        FW_SCHED_PARAMS_RATE_REL        = 0,

        FW_SCHED_PARAMS_RATE_ABS        = 1,

};


struct fw_sched_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        union fw_sched {

                struct fw_sched_config {

                        __u8   sc;

                        __u8   type;

                        __u8   minmaxen;

                        __u8   r3[5];

                        __u8   nclasses[4];

                        __be32 r4;

                } config;

                struct fw_sched_params {

                        __u8   sc;

                        __u8   type;

                        __u8   level;

                        __u8   mode;

                        __u8   unit;

                        __u8   rate;

                        __u8   ch;

                        __u8   cl;

                        __be32 min;

                        __be32 max;

                        __be16 weight;

                        __be16 pktsize;

                        __be16 burstsize;

                        __be16 r4;

                } params;

        } u;

};


/*

 *      length of the formatting string

 */

#define FW_DEVLOG_FMT_LEN       192


/*

 *      maximum number of the formatting string parameters

 */

#define FW_DEVLOG_FMT_PARAMS_NUM 8


/*

 *      priority levels

 */

enum fw_devlog_level {

        FW_DEVLOG_LEVEL_EMERG   = 0x0,

        FW_DEVLOG_LEVEL_CRIT    = 0x1,

        FW_DEVLOG_LEVEL_ERR     = 0x2,

        FW_DEVLOG_LEVEL_NOTICE  = 0x3,

        FW_DEVLOG_LEVEL_INFO    = 0x4,

        FW_DEVLOG_LEVEL_DEBUG   = 0x5,

        FW_DEVLOG_LEVEL_MAX     = 0x5,

};


/*

 *      facilities that may send a log message

 */

enum fw_devlog_facility {

        FW_DEVLOG_FACILITY_CORE         = 0x00,

        FW_DEVLOG_FACILITY_CF           = 0x01,

        FW_DEVLOG_FACILITY_SCHED        = 0x02,

        FW_DEVLOG_FACILITY_TIMER        = 0x04,

        FW_DEVLOG_FACILITY_RES          = 0x06,

        FW_DEVLOG_FACILITY_HW           = 0x08,

        FW_DEVLOG_FACILITY_FLR          = 0x10,

        FW_DEVLOG_FACILITY_DMAQ         = 0x12,

        FW_DEVLOG_FACILITY_PHY          = 0x14,

        FW_DEVLOG_FACILITY_MAC          = 0x16,

        FW_DEVLOG_FACILITY_PORT         = 0x18,

        FW_DEVLOG_FACILITY_VI           = 0x1A,

        FW_DEVLOG_FACILITY_FILTER       = 0x1C,

        FW_DEVLOG_FACILITY_ACL          = 0x1E,

        FW_DEVLOG_FACILITY_TM           = 0x20,

        FW_DEVLOG_FACILITY_QFC          = 0x22,

        FW_DEVLOG_FACILITY_DCB          = 0x24,

        FW_DEVLOG_FACILITY_ETH          = 0x26,

        FW_DEVLOG_FACILITY_OFLD         = 0x28,

        FW_DEVLOG_FACILITY_RI           = 0x2A,

        FW_DEVLOG_FACILITY_ISCSI        = 0x2C,

        FW_DEVLOG_FACILITY_FCOE         = 0x2E,

        FW_DEVLOG_FACILITY_FOISCSI      = 0x30,

        FW_DEVLOG_FACILITY_FOFCOE       = 0x32,

        FW_DEVLOG_FACILITY_CHNET        = 0x34,

        FW_DEVLOG_FACILITY_COISCSI      = 0x36,

        FW_DEVLOG_FACILITY_MAX          = 0x38,

};


/*

 *      log message format

 */

struct fw_devlog_e {

        __be64  timestamp;

        __be32  seqno;

        __be16  reserved1;

        __u8    level;

        __u8    facility;

        __u8    fmt[FW_DEVLOG_FMT_LEN];

        __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];

        __be32  reserved3[4];

};


struct fw_devlog_cmd {

        __be32 op_to_write;

        __be32 retval_len16;

        __u8   level;

        __u8   r2[7];

        __be32 memtype_devlog_memaddr16_devlog;

        __be32 memsize_devlog;

        __be32 r3[2];

};


#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG  28

#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG  0xf

#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \

    ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)

#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \

    (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)


#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0

#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff

#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \

    ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)

#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \

    (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \

     M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)


enum fw_watchdog_actions {

        FW_WATCHDOG_ACTION_SHUTDOWN = 0,

        FW_WATCHDOG_ACTION_FLR = 1,

        FW_WATCHDOG_ACTION_BYPASS = 2,

        FW_WATCHDOG_ACTION_TMPCHK = 3,

        FW_WATCHDOG_ACTION_PAUSEOFF = 4,


        FW_WATCHDOG_ACTION_MAX = 5,

};


#define FW_WATCHDOG_MAX_TIMEOUT_SECS    60


struct fw_watchdog_cmd {

        __be32 op_to_vfn;

        __be32 retval_len16;

        __be32 timeout;

        __be32 action;

};


#define S_FW_WATCHDOG_CMD_PFN           8

#define M_FW_WATCHDOG_CMD_PFN           0x7

#define V_FW_WATCHDOG_CMD_PFN(x)        ((x) << S_FW_WATCHDOG_CMD_PFN)

#define G_FW_WATCHDOG_CMD_PFN(x)        \

    (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)


#define S_FW_WATCHDOG_CMD_VFN           0

#define M_FW_WATCHDOG_CMD_VFN           0xff

#define V_FW_WATCHDOG_CMD_VFN(x)        ((x) << S_FW_WATCHDOG_CMD_VFN)

#define G_FW_WATCHDOG_CMD_VFN(x)        \

    (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)


struct fw_clip_cmd {

        __be32 op_to_write;

        __be32 alloc_to_len16;

        __be64 ip_hi;

        __be64 ip_lo;

        __be32 r4[2];

};


#define S_FW_CLIP_CMD_ALLOC             31

#define M_FW_CLIP_CMD_ALLOC             0x1

#define V_FW_CLIP_CMD_ALLOC(x)          ((x) << S_FW_CLIP_CMD_ALLOC)

#define G_FW_CLIP_CMD_ALLOC(x)          \

    (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)

#define F_FW_CLIP_CMD_ALLOC             V_FW_CLIP_CMD_ALLOC(1U)


#define S_FW_CLIP_CMD_FREE              30

#define M_FW_CLIP_CMD_FREE              0x1

#define V_FW_CLIP_CMD_FREE(x)           ((x) << S_FW_CLIP_CMD_FREE)

#define G_FW_CLIP_CMD_FREE(x)           \

    (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)

#define F_FW_CLIP_CMD_FREE              V_FW_CLIP_CMD_FREE(1U)


#define S_FW_CLIP_CMD_INDEX     16

#define M_FW_CLIP_CMD_INDEX     0x1fff

#define V_FW_CLIP_CMD_INDEX(x)  ((x) << S_FW_CLIP_CMD_INDEX)

#define G_FW_CLIP_CMD_INDEX(x)  \

    (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)


struct fw_clip2_cmd {

        __be32 op_to_write;

        __be32 alloc_to_len16;

        __be64 ip_hi;

        __be64 ip_lo;

        __be64 ipm_hi;

        __be64 ipm_lo;

        __be32 r4[2];

};


/******************************************************************************

 *   F O i S C S I   C O M M A N D s

 **************************************/


#define FW_CHNET_IFACE_ADDR_MAX 3


enum fw_chnet_iface_cmd_subop {

        FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,


        FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,

        FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,


        FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,

        FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,


        FW_CHNET_IFACE_CMD_SUBOP_MAX,

};


struct fw_chnet_iface_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        __u8   subop;

        __u8   r2[2];

        __u8   flags;

        __be32 ifid_ifstate;

        __be16 mtu;

        __be16 vlanid;

        __be32 r3;

        __be16 r4;

        __u8   mac[6];

};


#define S_FW_CHNET_IFACE_CMD_PORTID     0

#define M_FW_CHNET_IFACE_CMD_PORTID     0xf

#define V_FW_CHNET_IFACE_CMD_PORTID(x)  ((x) << S_FW_CHNET_IFACE_CMD_PORTID)

#define G_FW_CHNET_IFACE_CMD_PORTID(x)  \

    (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)


#define S_FW_CHNET_IFACE_CMD_RSS_IQID           16

#define M_FW_CHNET_IFACE_CMD_RSS_IQID           0xffff

#define V_FW_CHNET_IFACE_CMD_RSS_IQID(x)        \

    ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID)

#define G_FW_CHNET_IFACE_CMD_RSS_IQID(x)        \

    (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID)


#define S_FW_CHNET_IFACE_CMD_RSS_IQID_F         0

#define M_FW_CHNET_IFACE_CMD_RSS_IQID_F         0x1

#define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x)      \

    ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F)

#define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x)      \

    (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \

    M_FW_CHNET_IFACE_CMD_RSS_IQID_F)

#define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U)


#define S_FW_CHNET_IFACE_CMD_IFID       8

#define M_FW_CHNET_IFACE_CMD_IFID       0xffffff

#define V_FW_CHNET_IFACE_CMD_IFID(x)    ((x) << S_FW_CHNET_IFACE_CMD_IFID)

#define G_FW_CHNET_IFACE_CMD_IFID(x)    \

    (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)


#define S_FW_CHNET_IFACE_CMD_IFSTATE    0

#define M_FW_CHNET_IFACE_CMD_IFSTATE    0xff

#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)

#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \

    (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)


struct fw_fcoe_res_info_cmd {

        __be32 op_to_read;

        __be32 retval_len16;

        __be16 e_d_tov;

        __be16 r_a_tov_seq;

        __be16 r_a_tov_els;

        __be16 r_r_tov;

        __be32 max_xchgs;

        __be32 max_ssns;

        __be32 used_xchgs;

        __be32 used_ssns;

        __be32 max_fcfs;

        __be32 max_vnps;

        __be32 used_fcfs;

        __be32 used_vnps;

};


struct fw_fcoe_link_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        __be32 sub_opcode_fcfi;

        __u8   r3;

        __u8   lstatus;

        __be16 flags;

        __u8   r4;

        __u8   set_vlan;

        __be16 vlan_id;

        __be32 vnpi_pkd;

        __be16 r6;

        __u8   phy_mac[6];

        __u8   vnport_wwnn[8];

        __u8   vnport_wwpn[8];

};


#define S_FW_FCOE_LINK_CMD_PORTID       0

#define M_FW_FCOE_LINK_CMD_PORTID       0xf

#define V_FW_FCOE_LINK_CMD_PORTID(x)    ((x) << S_FW_FCOE_LINK_CMD_PORTID)

#define G_FW_FCOE_LINK_CMD_PORTID(x)    \

    (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)


#define S_FW_FCOE_LINK_CMD_SUB_OPCODE   24

#define M_FW_FCOE_LINK_CMD_SUB_OPCODE   0xff

#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \

    ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)

#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \

    (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)


#define S_FW_FCOE_LINK_CMD_FCFI         0

#define M_FW_FCOE_LINK_CMD_FCFI         0xffffff

#define V_FW_FCOE_LINK_CMD_FCFI(x)      ((x) << S_FW_FCOE_LINK_CMD_FCFI)

#define G_FW_FCOE_LINK_CMD_FCFI(x)      \

    (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)


#define S_FW_FCOE_LINK_CMD_VNPI         0

#define M_FW_FCOE_LINK_CMD_VNPI         0xfffff

#define V_FW_FCOE_LINK_CMD_VNPI(x)      ((x) << S_FW_FCOE_LINK_CMD_VNPI)

#define G_FW_FCOE_LINK_CMD_VNPI(x)      \

    (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)


struct fw_fcoe_vnp_cmd {

        __be32 op_to_fcfi;

        __be32 alloc_to_len16;

        __be32 gen_wwn_to_vnpi;

        __be32 vf_id;

        __be16 iqid;

        __u8   vnport_mac[6];

        __u8   vnport_wwnn[8];

        __u8   vnport_wwpn[8];

        __u8   cmn_srv_parms[16];

        __u8   clsp_word_0_1[8];

};


#define S_FW_FCOE_VNP_CMD_FCFI          0

#define M_FW_FCOE_VNP_CMD_FCFI          0xfffff

#define V_FW_FCOE_VNP_CMD_FCFI(x)       ((x) << S_FW_FCOE_VNP_CMD_FCFI)

#define G_FW_FCOE_VNP_CMD_FCFI(x)       \

    (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)


#define S_FW_FCOE_VNP_CMD_ALLOC         31

#define M_FW_FCOE_VNP_CMD_ALLOC         0x1

#define V_FW_FCOE_VNP_CMD_ALLOC(x)      ((x) << S_FW_FCOE_VNP_CMD_ALLOC)

#define G_FW_FCOE_VNP_CMD_ALLOC(x)      \

    (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)

#define F_FW_FCOE_VNP_CMD_ALLOC         V_FW_FCOE_VNP_CMD_ALLOC(1U)


#define S_FW_FCOE_VNP_CMD_FREE          30

#define M_FW_FCOE_VNP_CMD_FREE          0x1

#define V_FW_FCOE_VNP_CMD_FREE(x)       ((x) << S_FW_FCOE_VNP_CMD_FREE)

#define G_FW_FCOE_VNP_CMD_FREE(x)       \

    (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)

#define F_FW_FCOE_VNP_CMD_FREE          V_FW_FCOE_VNP_CMD_FREE(1U)


#define S_FW_FCOE_VNP_CMD_MODIFY        29

#define M_FW_FCOE_VNP_CMD_MODIFY        0x1

#define V_FW_FCOE_VNP_CMD_MODIFY(x)     ((x) << S_FW_FCOE_VNP_CMD_MODIFY)

#define G_FW_FCOE_VNP_CMD_MODIFY(x)     \

    (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)

#define F_FW_FCOE_VNP_CMD_MODIFY        V_FW_FCOE_VNP_CMD_MODIFY(1U)


#define S_FW_FCOE_VNP_CMD_GEN_WWN       22

#define M_FW_FCOE_VNP_CMD_GEN_WWN       0x1

#define V_FW_FCOE_VNP_CMD_GEN_WWN(x)    ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)

#define G_FW_FCOE_VNP_CMD_GEN_WWN(x)    \

    (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)

#define F_FW_FCOE_VNP_CMD_GEN_WWN       V_FW_FCOE_VNP_CMD_GEN_WWN(1U)


#define S_FW_FCOE_VNP_CMD_PERSIST       21

#define M_FW_FCOE_VNP_CMD_PERSIST       0x1

#define V_FW_FCOE_VNP_CMD_PERSIST(x)    ((x) << S_FW_FCOE_VNP_CMD_PERSIST)

#define G_FW_FCOE_VNP_CMD_PERSIST(x)    \

    (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)

#define F_FW_FCOE_VNP_CMD_PERSIST       V_FW_FCOE_VNP_CMD_PERSIST(1U)


#define S_FW_FCOE_VNP_CMD_VFID_EN       20

#define M_FW_FCOE_VNP_CMD_VFID_EN       0x1

#define V_FW_FCOE_VNP_CMD_VFID_EN(x)    ((x) << S_FW_FCOE_VNP_CMD_VFID_EN)

#define G_FW_FCOE_VNP_CMD_VFID_EN(x)    \

    (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)

#define F_FW_FCOE_VNP_CMD_VFID_EN       V_FW_FCOE_VNP_CMD_VFID_EN(1U)


#define S_FW_FCOE_VNP_CMD_VNPI          0

#define M_FW_FCOE_VNP_CMD_VNPI          0xfffff

#define V_FW_FCOE_VNP_CMD_VNPI(x)       ((x) << S_FW_FCOE_VNP_CMD_VNPI)

#define G_FW_FCOE_VNP_CMD_VNPI(x)       \

    (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)


struct fw_fcoe_sparams_cmd {

        __be32 op_to_portid;

        __be32 retval_len16;

        __u8   r3[7];

        __u8   cos;

        __u8   lport_wwnn[8];

        __u8   lport_wwpn[8];

        __u8   cmn_srv_parms[16];

        __u8   cls_srv_parms[16];

};


#define S_FW_FCOE_SPARAMS_CMD_PORTID    0

#define M_FW_FCOE_SPARAMS_CMD_PORTID    0xf

#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)

#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \

    (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)


struct fw_fcoe_stats_cmd {

        __be32 op_to_flowid;

        __be32 free_to_len16;

        union fw_fcoe_stats {

                struct fw_fcoe_stats_ctl {

                        __u8   nstats_port;

                        __u8   port_valid_ix;

                        __be16 r6;

                        __be32 r7;

                        __be64 stat0;

                        __be64 stat1;

                        __be64 stat2;

                        __be64 stat3;

                        __be64 stat4;

                        __be64 stat5;

                } ctl;

                struct fw_fcoe_port_stats {

                        __be64 tx_bcast_bytes;

                        __be64 tx_bcast_frames;

                        __be64 tx_mcast_bytes;

                        __be64 tx_mcast_frames;

                        __be64 tx_ucast_bytes;

                        __be64 tx_ucast_frames;

                        __be64 tx_drop_frames;

                        __be64 tx_offload_bytes;

                        __be64 tx_offload_frames;

                        __be64 rx_bcast_bytes;

                        __be64 rx_bcast_frames;

                        __be64 rx_mcast_bytes;

                        __be64 rx_mcast_frames;

                        __be64 rx_ucast_bytes;

                        __be64 rx_ucast_frames;

                        __be64 rx_err_frames;

                } port_stats;

                struct fw_fcoe_fcf_stats {

                        __be32 fip_tx_bytes;

                        __be32 fip_tx_fr;

                        __be64 fcf_ka;

                        __be64 mcast_adv_rcvd;

                        __be16 ucast_adv_rcvd;

                        __be16 sol_sent;

                        __be16 vlan_req;

                        __be16 vlan_rpl;

                        __be16 clr_vlink;

                        __be16 link_down;

                        __be16 link_up;

                        __be16 logo;

                        __be16 flogi_req;

                        __be16 flogi_rpl;

                        __be16 fdisc_req;

                        __be16 fdisc_rpl;

                        __be16 fka_prd_chg;

                        __be16 fc_map_chg;

                        __be16 vfid_chg;

                        __u8   no_fka_req;

                        __u8   no_vnp;

                } fcf_stats;

                struct fw_fcoe_pcb_stats {

                        __be64 tx_bytes;

                        __be64 tx_frames;

                        __be64 rx_bytes;

                        __be64 rx_frames;

                        __be32 vnp_ka;

                        __be32 unsol_els_rcvd;

                        __be64 unsol_cmd_rcvd;

                        __be16 implicit_logo;

                        __be16 flogi_inv_sparm;

                        __be16 fdisc_inv_sparm;

                        __be16 flogi_rjt;

                        __be16 fdisc_rjt;

                        __be16 no_ssn;

                        __be16 mac_flt_fail;

                        __be16 inv_fr_rcvd;

                } pcb_stats;

                struct fw_fcoe_scb_stats {

                        __be64 tx_bytes;

                        __be64 tx_frames;

                        __be64 rx_bytes;

                        __be64 rx_frames;

                        __be32 host_abrt_req;

                        __be32 adap_auto_abrt;

                        __be32 adap_abrt_rsp;

                        __be32 host_ios_req;

                        __be16 ssn_offl_ios;

                        __be16 ssn_not_rdy_ios;

                        __u8   rx_data_ddp_err;

                        __u8   ddp_flt_set_err;

                        __be16 rx_data_fr_err;

                        __u8   bad_st_abrt_req;

                        __u8   no_io_abrt_req;

                        __u8   abort_tmo;

                        __u8   abort_tmo_2;

                        __be32 abort_req;

                        __u8   no_ppod_res_tmo;

                        __u8   bp_tmo;

                        __u8   adap_auto_cls;

                        __u8   no_io_cls_req;

                        __be32 host_cls_req;

                        __be64 unsol_cmd_rcvd;

                        __be32 plogi_req_rcvd;

                        __be32 prli_req_rcvd;

                        __be16 logo_req_rcvd;

                        __be16 prlo_req_rcvd;

                        __be16 plogi_rjt_rcvd;

                        __be16 prli_rjt_rcvd;

                        __be32 adisc_req_rcvd;

                        __be32 rscn_rcvd;

                        __be32 rrq_req_rcvd;

                        __be32 unsol_els_rcvd;

                        __u8   adisc_rjt_rcvd;

                        __u8   scr_rjt;

                        __u8   ct_rjt;

                        __u8   inval_bls_rcvd;

                        __be32 ba_rjt_rcvd;

                } scb_stats;

        } u;

};


#define S_FW_FCOE_STATS_CMD_FLOWID      0

#define M_FW_FCOE_STATS_CMD_FLOWID      0xfffff

#define V_FW_FCOE_STATS_CMD_FLOWID(x)   ((x) << S_FW_FCOE_STATS_CMD_FLOWID)

#define G_FW_FCOE_STATS_CMD_FLOWID(x)   \

    (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)


#define S_FW_FCOE_STATS_CMD_FREE        30

#define M_FW_FCOE_STATS_CMD_FREE        0x1

#define V_FW_FCOE_STATS_CMD_FREE(x)     ((x) << S_FW_FCOE_STATS_CMD_FREE)

#define G_FW_FCOE_STATS_CMD_FREE(x)     \

    (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)

#define F_FW_FCOE_STATS_CMD_FREE        V_FW_FCOE_STATS_CMD_FREE(1U)


#define S_FW_FCOE_STATS_CMD_NSTATS      4

#define M_FW_FCOE_STATS_CMD_NSTATS      0x7

#define V_FW_FCOE_STATS_CMD_NSTATS(x)   ((x) << S_FW_FCOE_STATS_CMD_NSTATS)

#define G_FW_FCOE_STATS_CMD_NSTATS(x)   \

    (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)


#define S_FW_FCOE_STATS_CMD_PORT        0

#define M_FW_FCOE_STATS_CMD_PORT        0x3

#define V_FW_FCOE_STATS_CMD_PORT(x)     ((x) << S_FW_FCOE_STATS_CMD_PORT)

#define G_FW_FCOE_STATS_CMD_PORT(x)     \

    (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)


#define S_FW_FCOE_STATS_CMD_PORT_VALID  7

#define M_FW_FCOE_STATS_CMD_PORT_VALID  0x1

#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \

    ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)

#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \

    (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)

#define F_FW_FCOE_STATS_CMD_PORT_VALID  V_FW_FCOE_STATS_CMD_PORT_VALID(1U)


#define S_FW_FCOE_STATS_CMD_IX          0

#define M_FW_FCOE_STATS_CMD_IX          0x3f

#define V_FW_FCOE_STATS_CMD_IX(x)       ((x) << S_FW_FCOE_STATS_CMD_IX)

#define G_FW_FCOE_STATS_CMD_IX(x)       \

    (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)


struct fw_fcoe_fcf_cmd {

        __be32 op_to_fcfi;

        __be32 retval_len16;

        __be16 priority_pkd;

        __u8   mac[6];

        __u8   name_id[8];

        __u8   fabric[8];

        __be16 vf_id;

        __be16 max_fcoe_size;

        __u8   vlan_id;

        __u8   fc_map[3];

        __be32 fka_adv;

        __be32 r6;

        __u8   r7_hi;

        __u8   fpma_to_portid;

        __u8   spma_mac[6];

        __be64 r8;

};


#define S_FW_FCOE_FCF_CMD_FCFI          0

#define M_FW_FCOE_FCF_CMD_FCFI          0xfffff

#define V_FW_FCOE_FCF_CMD_FCFI(x)       ((x) << S_FW_FCOE_FCF_CMD_FCFI)

#define G_FW_FCOE_FCF_CMD_FCFI(x)       \

    (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)


#define S_FW_FCOE_FCF_CMD_PRIORITY      0

#define M_FW_FCOE_FCF_CMD_PRIORITY      0xff

#define V_FW_FCOE_FCF_CMD_PRIORITY(x)   ((x) << S_FW_FCOE_FCF_CMD_PRIORITY)

#define G_FW_FCOE_FCF_CMD_PRIORITY(x)   \

    (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)


#define S_FW_FCOE_FCF_CMD_FPMA          6

#define M_FW_FCOE_FCF_CMD_FPMA          0x1

#define V_FW_FCOE_FCF_CMD_FPMA(x)       ((x) << S_FW_FCOE_FCF_CMD_FPMA)

#define G_FW_FCOE_FCF_CMD_FPMA(x)       \

    (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)

#define F_FW_FCOE_FCF_CMD_FPMA          V_FW_FCOE_FCF_CMD_FPMA(1U)


#define S_FW_FCOE_FCF_CMD_SPMA          5

#define M_FW_FCOE_FCF_CMD_SPMA          0x1

#define V_FW_FCOE_FCF_CMD_SPMA(x)       ((x) << S_FW_FCOE_FCF_CMD_SPMA)

#define G_FW_FCOE_FCF_CMD_SPMA(x)       \

    (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)

#define F_FW_FCOE_FCF_CMD_SPMA          V_FW_FCOE_FCF_CMD_SPMA(1U)


#define S_FW_FCOE_FCF_CMD_LOGIN         4

#define M_FW_FCOE_FCF_CMD_LOGIN         0x1

#define V_FW_FCOE_FCF_CMD_LOGIN(x)      ((x) << S_FW_FCOE_FCF_CMD_LOGIN)

#define G_FW_FCOE_FCF_CMD_LOGIN(x)      \

    (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)

#define F_FW_FCOE_FCF_CMD_LOGIN         V_FW_FCOE_FCF_CMD_LOGIN(1U)


#define S_FW_FCOE_FCF_CMD_PORTID        0

#define M_FW_FCOE_FCF_CMD_PORTID        0xf

#define V_FW_FCOE_FCF_CMD_PORTID(x)     ((x) << S_FW_FCOE_FCF_CMD_PORTID)

#define G_FW_FCOE_FCF_CMD_PORTID(x)     \

    (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)


/******************************************************************************

 *   E R R O R   a n d   D E B U G   C O M M A N D s

 ******************************************************/


enum fw_error_type {

        FW_ERROR_TYPE_EXCEPTION         = 0x0,

        FW_ERROR_TYPE_HWMODULE          = 0x1,

        FW_ERROR_TYPE_WR                = 0x2,

        FW_ERROR_TYPE_ACL               = 0x3,

};


enum fw_dcb_ieee_locations {

        FW_IEEE_LOC_LOCAL,

        FW_IEEE_LOC_PEER,

        FW_IEEE_LOC_OPERATIONAL,

};


struct fw_dcb_ieee_cmd {

        __be32 op_to_location;

        __be32 changed_to_len16;

        union fw_dcbx_stats {

                struct fw_dcbx_pfc_stats_ieee {

                        __be32 pfc_mbc_pkd;

                        __be32 pfc_willing_to_pfc_en;

                } dcbx_pfc_stats;

                struct fw_dcbx_ets_stats_ieee {

                        __be32 cbs_to_ets_max_tc;

                        __be32 pg_table;

                        __u8   pg_percent[8];

                        __u8   tsa[8];

                } dcbx_ets_stats;

                struct fw_dcbx_app_stats_ieee {

                        __be32 num_apps_pkd;

                        __be32 r6;

                        __be32 app[4];

                } dcbx_app_stats;

                struct fw_dcbx_control {

                        __be32 multi_peer_invalidated;

                        __u8 version;

                        __u8 r6[3];

                } dcbx_control;

        } u;

};


#define S_FW_DCB_IEEE_CMD_PORT          8

#define M_FW_DCB_IEEE_CMD_PORT          0x7

#define V_FW_DCB_IEEE_CMD_PORT(x)       ((x) << S_FW_DCB_IEEE_CMD_PORT)

#define G_FW_DCB_IEEE_CMD_PORT(x)       \

    (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)


#define S_FW_DCB_IEEE_CMD_FEATURE       2

#define M_FW_DCB_IEEE_CMD_FEATURE       0x7

#define V_FW_DCB_IEEE_CMD_FEATURE(x)    ((x) << S_FW_DCB_IEEE_CMD_FEATURE)

#define G_FW_DCB_IEEE_CMD_FEATURE(x)    \

    (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)


#define S_FW_DCB_IEEE_CMD_LOCATION      0

#define M_FW_DCB_IEEE_CMD_LOCATION      0x3

#define V_FW_DCB_IEEE_CMD_LOCATION(x)   ((x) << S_FW_DCB_IEEE_CMD_LOCATION)

#define G_FW_DCB_IEEE_CMD_LOCATION(x)   \

    (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)


#define S_FW_DCB_IEEE_CMD_CHANGED       20

#define M_FW_DCB_IEEE_CMD_CHANGED       0x1

#define V_FW_DCB_IEEE_CMD_CHANGED(x)    ((x) << S_FW_DCB_IEEE_CMD_CHANGED)

#define G_FW_DCB_IEEE_CMD_CHANGED(x)    \

    (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)

#define F_FW_DCB_IEEE_CMD_CHANGED       V_FW_DCB_IEEE_CMD_CHANGED(1U)


#define S_FW_DCB_IEEE_CMD_RECEIVED      19

#define M_FW_DCB_IEEE_CMD_RECEIVED      0x1

#define V_FW_DCB_IEEE_CMD_RECEIVED(x)   ((x) << S_FW_DCB_IEEE_CMD_RECEIVED)

#define G_FW_DCB_IEEE_CMD_RECEIVED(x)   \

    (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)

#define F_FW_DCB_IEEE_CMD_RECEIVED      V_FW_DCB_IEEE_CMD_RECEIVED(1U)


#define S_FW_DCB_IEEE_CMD_APPLY         18

#define M_FW_DCB_IEEE_CMD_APPLY         0x1

#define V_FW_DCB_IEEE_CMD_APPLY(x)      ((x) << S_FW_DCB_IEEE_CMD_APPLY)

#define G_FW_DCB_IEEE_CMD_APPLY(x)      \

    (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)

#define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U)


#define S_FW_DCB_IEEE_CMD_DISABLED      17

#define M_FW_DCB_IEEE_CMD_DISABLED      0x1

#define V_FW_DCB_IEEE_CMD_DISABLED(x)   ((x) << S_FW_DCB_IEEE_CMD_DISABLED)

#define G_FW_DCB_IEEE_CMD_DISABLED(x)   \

    (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)

#define F_FW_DCB_IEEE_CMD_DISABLED      V_FW_DCB_IEEE_CMD_DISABLED(1U)


#define S_FW_DCB_IEEE_CMD_MORE          16

#define M_FW_DCB_IEEE_CMD_MORE          0x1

#define V_FW_DCB_IEEE_CMD_MORE(x)       ((x) << S_FW_DCB_IEEE_CMD_MORE)

#define G_FW_DCB_IEEE_CMD_MORE(x)       \

    (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)

#define F_FW_DCB_IEEE_CMD_MORE  V_FW_DCB_IEEE_CMD_MORE(1U)


#define S_FW_DCB_IEEE_CMD_PFC_MBC       0

#define M_FW_DCB_IEEE_CMD_PFC_MBC       0x1

#define V_FW_DCB_IEEE_CMD_PFC_MBC(x)    ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)

#define G_FW_DCB_IEEE_CMD_PFC_MBC(x)    \

    (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)

#define F_FW_DCB_IEEE_CMD_PFC_MBC       V_FW_DCB_IEEE_CMD_PFC_MBC(1U)


#define S_FW_DCB_IEEE_CMD_PFC_WILLING           16

#define M_FW_DCB_IEEE_CMD_PFC_WILLING           0x1

#define V_FW_DCB_IEEE_CMD_PFC_WILLING(x)        \

    ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)

#define G_FW_DCB_IEEE_CMD_PFC_WILLING(x)        \

    (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)

#define F_FW_DCB_IEEE_CMD_PFC_WILLING   V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)


#define S_FW_DCB_IEEE_CMD_PFC_MAX_TC    8

#define M_FW_DCB_IEEE_CMD_PFC_MAX_TC    0xff

#define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)

#define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \

    (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)


#define S_FW_DCB_IEEE_CMD_PFC_EN        0

#define M_FW_DCB_IEEE_CMD_PFC_EN        0xff

#define V_FW_DCB_IEEE_CMD_PFC_EN(x)     ((x) << S_FW_DCB_IEEE_CMD_PFC_EN)

#define G_FW_DCB_IEEE_CMD_PFC_EN(x)     \

    (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)


#define S_FW_DCB_IEEE_CMD_CBS           16

#define M_FW_DCB_IEEE_CMD_CBS           0x1

#define V_FW_DCB_IEEE_CMD_CBS(x)        ((x) << S_FW_DCB_IEEE_CMD_CBS)

#define G_FW_DCB_IEEE_CMD_CBS(x)        \

    (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)

#define F_FW_DCB_IEEE_CMD_CBS   V_FW_DCB_IEEE_CMD_CBS(1U)


#define S_FW_DCB_IEEE_CMD_ETS_WILLING           8

#define M_FW_DCB_IEEE_CMD_ETS_WILLING           0x1

#define V_FW_DCB_IEEE_CMD_ETS_WILLING(x)        \

    ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)

#define G_FW_DCB_IEEE_CMD_ETS_WILLING(x)        \

    (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)

#define F_FW_DCB_IEEE_CMD_ETS_WILLING   V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)


#define S_FW_DCB_IEEE_CMD_ETS_MAX_TC    0

#define M_FW_DCB_IEEE_CMD_ETS_MAX_TC    0xff

#define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)

#define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \

    (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)


#define S_FW_DCB_IEEE_CMD_NUM_APPS      0

#define M_FW_DCB_IEEE_CMD_NUM_APPS      0x7

#define V_FW_DCB_IEEE_CMD_NUM_APPS(x)   ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)

#define G_FW_DCB_IEEE_CMD_NUM_APPS(x)   \

    (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)


#define S_FW_DCB_IEEE_CMD_MULTI_PEER    31

#define M_FW_DCB_IEEE_CMD_MULTI_PEER    0x1

#define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)

#define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \

    (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)

#define F_FW_DCB_IEEE_CMD_MULTI_PEER    V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)


#define S_FW_DCB_IEEE_CMD_INVALIDATED           30

#define M_FW_DCB_IEEE_CMD_INVALIDATED           0x1

#define V_FW_DCB_IEEE_CMD_INVALIDATED(x)        \

    ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)

#define G_FW_DCB_IEEE_CMD_INVALIDATED(x)        \

    (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)

#define F_FW_DCB_IEEE_CMD_INVALIDATED   V_FW_DCB_IEEE_CMD_INVALIDATED(1U)


/* Hand-written */

#define S_FW_DCB_IEEE_CMD_APP_PROTOCOL  16

#define M_FW_DCB_IEEE_CMD_APP_PROTOCOL  0xffff

#define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)       ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)

#define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)       \

    (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)


#define S_FW_DCB_IEEE_CMD_APP_SELECT    3

#define M_FW_DCB_IEEE_CMD_APP_SELECT    0x7

#define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)

#define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \

    (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)


#define S_FW_DCB_IEEE_CMD_APP_PRIORITY  0

#define M_FW_DCB_IEEE_CMD_APP_PRIORITY  0x7

#define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x)       ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)

#define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x)       \

    (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)


struct fw_error_cmd {

        __be32 op_to_type;

        __be32 len16_pkd;

        union fw_error {

                struct fw_error_exception {

                        __be32 info[6];

                } exception;

                struct fw_error_hwmodule {

                        __be32 regaddr;

                        __be32 regval;

                } hwmodule;

                struct fw_error_wr {

                        __be16 cidx;

                        __be16 pfn_vfn;

                        __be32 eqid;

                        __u8   wrhdr[16];

                } wr;

                struct fw_error_acl {

                        __be16 cidx;

                        __be16 pfn_vfn;

                        __be32 eqid;

                        __be16 mv_pkd;

                        __u8   val[6];

                        __be64 r4;

                } acl;

        } u;

};


#define S_FW_ERROR_CMD_FATAL            4

#define M_FW_ERROR_CMD_FATAL            0x1

#define V_FW_ERROR_CMD_FATAL(x)         ((x) << S_FW_ERROR_CMD_FATAL)

#define G_FW_ERROR_CMD_FATAL(x)         \

    (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)

#define F_FW_ERROR_CMD_FATAL            V_FW_ERROR_CMD_FATAL(1U)


#define S_FW_ERROR_CMD_TYPE             0

#define M_FW_ERROR_CMD_TYPE             0xf

#define V_FW_ERROR_CMD_TYPE(x)          ((x) << S_FW_ERROR_CMD_TYPE)

#define G_FW_ERROR_CMD_TYPE(x)          \

    (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)


#define S_FW_ERROR_CMD_PFN              8

#define M_FW_ERROR_CMD_PFN              0x7

#define V_FW_ERROR_CMD_PFN(x)           ((x) << S_FW_ERROR_CMD_PFN)

#define G_FW_ERROR_CMD_PFN(x)           \

    (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)


#define S_FW_ERROR_CMD_VFN              0

#define M_FW_ERROR_CMD_VFN              0xff

#define V_FW_ERROR_CMD_VFN(x)           ((x) << S_FW_ERROR_CMD_VFN)

#define G_FW_ERROR_CMD_VFN(x)           \

    (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)


#define S_FW_ERROR_CMD_PFN              8

#define M_FW_ERROR_CMD_PFN              0x7

#define V_FW_ERROR_CMD_PFN(x)           ((x) << S_FW_ERROR_CMD_PFN)

#define G_FW_ERROR_CMD_PFN(x)           \

    (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)


#define S_FW_ERROR_CMD_VFN              0

#define M_FW_ERROR_CMD_VFN              0xff

#define V_FW_ERROR_CMD_VFN(x)           ((x) << S_FW_ERROR_CMD_VFN)

#define G_FW_ERROR_CMD_VFN(x)           \

    (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)


#define S_FW_ERROR_CMD_MV               15

#define M_FW_ERROR_CMD_MV               0x1

#define V_FW_ERROR_CMD_MV(x)            ((x) << S_FW_ERROR_CMD_MV)

#define G_FW_ERROR_CMD_MV(x)            \

    (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)

#define F_FW_ERROR_CMD_MV               V_FW_ERROR_CMD_MV(1U)


struct fw_debug_cmd {

        __be32 op_type;

        __be32 len16_pkd;

        union fw_debug {

                struct fw_debug_assert {

                        __be32 fcid;

                        __be32 line;

                        __be32 x;

                        __be32 y;

                        __u8   filename_0_7[8];

                        __u8   filename_8_15[8];

                        __be64 r3;

                } assert;

                struct fw_debug_prt {

                        __be16 dprtstridx;

                        __be16 r3[3];

                        __be32 dprtstrparam0;

                        __be32 dprtstrparam1;

                        __be32 dprtstrparam2;

                        __be32 dprtstrparam3;

                } prt;

        } u;

};


#define S_FW_DEBUG_CMD_TYPE             0

#define M_FW_DEBUG_CMD_TYPE             0xff

#define V_FW_DEBUG_CMD_TYPE(x)          ((x) << S_FW_DEBUG_CMD_TYPE)

#define G_FW_DEBUG_CMD_TYPE(x)          \

    (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)


enum fw_diag_cmd_type {

        FW_DIAG_CMD_TYPE_OFLDIAG = 0,

        FW_DIAG_CMD_TYPE_MEM_TEST_DIAG,

};


enum fw_diag_cmd_ofldiag_op {

        FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,

        FW_DIAG_CMD_OFLDIAG_TEST_START,

        FW_DIAG_CMD_OFLDIAG_TEST_STOP,

        FW_DIAG_CMD_OFLDIAG_TEST_STATUS,

};


enum fw_diag_cmd_ofldiag_status {

        FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,

        FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,

        FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,

        FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,

};


enum fw_diag_cmd_memdiag_op {

        FW_DIAG_CMD_MEMDIAG_TEST_START=1,

        FW_DIAG_CMD_MEMDIAG_TEST_STOP,

        FW_DIAG_CMD_MEMDIAG_TEST_STATUS,

        FW_DIAG_CMD_MEMDIAG_TEST_INIT,

};


enum fw_diag_cmd_memdiag_status {

        FW_DIAG_CMD_MEMDIAG_STATUS_NONE,

        FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING,

        FW_DIAG_CMD_MEMDIAG_STATUS_FAILED,

        FW_DIAG_CMD_MEMDIAG_STATUS_PASSED

};


struct fw_diag_cmd {

        __be32 op_type;

        __be32 len16_pkd;

        union fw_diag_test {

                struct fw_diag_test_ofldiag {

                        __u8   test_op;

                        __u8   r3;

                        __be16 test_status;

                        __be32 duration;

                } ofldiag;

                struct fw_diag_test_memtest_diag {

                        __u8   test_op;

                        __u8   test_status;

                        __be16 size;  /* in KB */

                        __be32 duration; /* in seconds */

                } memdiag;

        } u;

};


#define S_FW_DIAG_CMD_OPCODE        24

#define M_FW_DIAG_CMD_OPCODE        0xff

#define V_FW_DIAG_CMD_OPCODE(x)     ((x) << S_FW_DIAG_CMD_OPCODE)

#define G_FW_DIAG_CMD_OPCODE(x)     \

            (((x) >> S_FW_DIAG_CMD_OPCODE) & M_FW_DIAG_CMD_OPCODE)


#define S_FW_DIAG_CMD_TYPE      0

#define M_FW_DIAG_CMD_TYPE      0xff

#define V_FW_DIAG_CMD_TYPE(x)       ((x) << S_FW_DIAG_CMD_TYPE)

#define G_FW_DIAG_CMD_TYPE(x)       \

            (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)


#define S_FW_DIAG_CMD_LEN16     0

#define M_FW_DIAG_CMD_LEN16     0xff

#define V_FW_DIAG_CMD_LEN16(x)      ((x) << S_FW_DIAG_CMD_LEN16)

#define G_FW_DIAG_CMD_LEN16(x)      \

            (((x) >> S_FW_DIAG_CMD_LEN16) & M_FW_DIAG_CMD_LEN16)


struct fw_hma_cmd {

        __be32 op_pkd;

        __be32 retval_len16;

        __be32 mode_to_pcie_params;

        __be32 naddr_size;

        __be32 addr_size_pkd;

        __be32 r6;

        __be64 phy_address[5];

};


#define S_FW_HMA_CMD_MODE       31

#define M_FW_HMA_CMD_MODE       0x1

#define V_FW_HMA_CMD_MODE(x)    ((x) << S_FW_HMA_CMD_MODE)

#define G_FW_HMA_CMD_MODE(x)    \

    (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)

#define F_FW_HMA_CMD_MODE       V_FW_HMA_CMD_MODE(1U)


#define S_FW_HMA_CMD_SOC        30

#define M_FW_HMA_CMD_SOC        0x1

#define V_FW_HMA_CMD_SOC(x)     ((x) << S_FW_HMA_CMD_SOC)

#define G_FW_HMA_CMD_SOC(x)     (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)

#define F_FW_HMA_CMD_SOC        V_FW_HMA_CMD_SOC(1U)


#define S_FW_HMA_CMD_EOC        29

#define M_FW_HMA_CMD_EOC        0x1

#define V_FW_HMA_CMD_EOC(x)     ((x) << S_FW_HMA_CMD_EOC)

#define G_FW_HMA_CMD_EOC(x)     (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)

#define F_FW_HMA_CMD_EOC        V_FW_HMA_CMD_EOC(1U)


#define S_FW_HMA_CMD_PCIE_PARAMS        0

#define M_FW_HMA_CMD_PCIE_PARAMS        0x7ffffff

#define V_FW_HMA_CMD_PCIE_PARAMS(x)     ((x) << S_FW_HMA_CMD_PCIE_PARAMS)

#define G_FW_HMA_CMD_PCIE_PARAMS(x)     \

    (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)


#define S_FW_HMA_CMD_NADDR      12

#define M_FW_HMA_CMD_NADDR      0x3f

#define V_FW_HMA_CMD_NADDR(x)   ((x) << S_FW_HMA_CMD_NADDR)

#define G_FW_HMA_CMD_NADDR(x)   \

    (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)


#define S_FW_HMA_CMD_SIZE       0

#define M_FW_HMA_CMD_SIZE       0xfff

#define V_FW_HMA_CMD_SIZE(x)    ((x) << S_FW_HMA_CMD_SIZE)

#define G_FW_HMA_CMD_SIZE(x)    \

    (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)


#define S_FW_HMA_CMD_ADDR_SIZE          11

#define M_FW_HMA_CMD_ADDR_SIZE          0x1fffff

#define V_FW_HMA_CMD_ADDR_SIZE(x)       ((x) << S_FW_HMA_CMD_ADDR_SIZE)

#define G_FW_HMA_CMD_ADDR_SIZE(x)       \

    (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)


/******************************************************************************

 *   P C I E   F W   R E G I S T E R

 **************************************/


enum pcie_fw_eval {

        PCIE_FW_EVAL_CRASH              = 0,

        PCIE_FW_EVAL_PREP               = 1,

        PCIE_FW_EVAL_CONF               = 2,

        PCIE_FW_EVAL_INIT               = 3,

        PCIE_FW_EVAL_UNEXPECTEDEVENT    = 4,

        PCIE_FW_EVAL_OVERHEAT           = 5,

        PCIE_FW_EVAL_DEVICESHUTDOWN     = 6,

};


#define S_PCIE_FW_ERR           31

#define M_PCIE_FW_ERR           0x1

#define V_PCIE_FW_ERR(x)        ((x) << S_PCIE_FW_ERR)

#define G_PCIE_FW_ERR(x)        (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)

#define F_PCIE_FW_ERR           V_PCIE_FW_ERR(1U)


#define S_PCIE_FW_INIT          30

#define M_PCIE_FW_INIT          0x1

#define V_PCIE_FW_INIT(x)       ((x) << S_PCIE_FW_INIT)

#define G_PCIE_FW_INIT(x)       (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)

#define F_PCIE_FW_INIT          V_PCIE_FW_INIT(1U)


#define S_PCIE_FW_HALT          29

#define M_PCIE_FW_HALT          0x1

#define V_PCIE_FW_HALT(x)       ((x) << S_PCIE_FW_HALT)

#define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)

#define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)


#define S_PCIE_FW_EVAL          24

#define M_PCIE_FW_EVAL          0x7

#define V_PCIE_FW_EVAL(x)       ((x) << S_PCIE_FW_EVAL)

#define G_PCIE_FW_EVAL(x)       (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)


#define S_PCIE_FW_STAGE         21

#define M_PCIE_FW_STAGE         0x7

#define V_PCIE_FW_STAGE(x)      ((x) << S_PCIE_FW_STAGE)

#define G_PCIE_FW_STAGE(x)      (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)


#define S_PCIE_FW_ASYNCNOT_VLD  20

#define M_PCIE_FW_ASYNCNOT_VLD  0x1

#define V_PCIE_FW_ASYNCNOT_VLD(x) \

    ((x) << S_PCIE_FW_ASYNCNOT_VLD)

#define G_PCIE_FW_ASYNCNOT_VLD(x) \

    (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)

#define F_PCIE_FW_ASYNCNOT_VLD  V_PCIE_FW_ASYNCNOT_VLD(1U)


#define S_PCIE_FW_ASYNCNOTINT   19

#define M_PCIE_FW_ASYNCNOTINT   0x1

#define V_PCIE_FW_ASYNCNOTINT(x) \

    ((x) << S_PCIE_FW_ASYNCNOTINT)

#define G_PCIE_FW_ASYNCNOTINT(x) \

    (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)

#define F_PCIE_FW_ASYNCNOTINT   V_PCIE_FW_ASYNCNOTINT(1U)


#define S_PCIE_FW_ASYNCNOT      16

#define M_PCIE_FW_ASYNCNOT      0x7

#define V_PCIE_FW_ASYNCNOT(x)   ((x) << S_PCIE_FW_ASYNCNOT)

#define G_PCIE_FW_ASYNCNOT(x)   \

    (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)


#define S_PCIE_FW_MASTER_VLD    15

#define M_PCIE_FW_MASTER_VLD    0x1

#define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)

#define G_PCIE_FW_MASTER_VLD(x) \

    (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)

#define F_PCIE_FW_MASTER_VLD    V_PCIE_FW_MASTER_VLD(1U)


#define S_PCIE_FW_MASTER        12

#define M_PCIE_FW_MASTER        0x7

#define V_PCIE_FW_MASTER(x)     ((x) << S_PCIE_FW_MASTER)

#define G_PCIE_FW_MASTER(x)     (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)


#define S_PCIE_FW_RESET_VLD             11

#define M_PCIE_FW_RESET_VLD             0x1

#define V_PCIE_FW_RESET_VLD(x)  ((x) << S_PCIE_FW_RESET_VLD)

#define G_PCIE_FW_RESET_VLD(x)  \

    (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)

#define F_PCIE_FW_RESET_VLD     V_PCIE_FW_RESET_VLD(1U)


#define S_PCIE_FW_RESET         8

#define M_PCIE_FW_RESET         0x7

#define V_PCIE_FW_RESET(x)      ((x) << S_PCIE_FW_RESET)

#define G_PCIE_FW_RESET(x)      \

    (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)


#define S_PCIE_FW_REGISTERED    0

#define M_PCIE_FW_REGISTERED    0xff

#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)

#define G_PCIE_FW_REGISTERED(x) \

    (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)


/******************************************************************************

 *   P C I E   F W   P F 0   R E G I S T E R

 **********************************************/


/*

 *      this register is available as 32-bit of persistent storage (across

 *      PL_RST based chip-reset) for boot drivers (i.e. firmware and driver

 *      will not write it)

 */


/******************************************************************************

 *   P C I E   F W   P F 7   R E G I S T E R

 **********************************************/


/*

 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to

 * access the "devlog" which needing to contact firmware.  The encoding is

 * mostly the same as that returned by the DEVLOG command except for the size

 * which is encoded as the number of entries in multiples-1 of 128 here rather

 * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128

 * and 15 means 2048.  This of course in turn constrains the allowed values

 * for the devlog size ...

 */

#define PCIE_FW_PF_DEVLOG               7


#define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28

#define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf

#define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \

        ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)

#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \

        (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \

         M_PCIE_FW_PF_DEVLOG_NENTRIES128)


#define S_PCIE_FW_PF_DEVLOG_ADDR16      4

#define M_PCIE_FW_PF_DEVLOG_ADDR16      0xffffff

#define V_PCIE_FW_PF_DEVLOG_ADDR16(x)   ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)

#define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \

        (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)


#define S_PCIE_FW_PF_DEVLOG_MEMTYPE     0

#define M_PCIE_FW_PF_DEVLOG_MEMTYPE     0xf

#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x)  ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)

#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \

        (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)


/******************************************************************************

 *   B I N A R Y   H E A D E R   F O R M A T

 **********************************************/


/*

 *      firmware binary header format

 */

struct fw_hdr {

        __u8    ver;

        __u8    chip;                   /* terminator chip family */

        __be16  len512;                 /* bin length in units of 512-bytes */

        __be32  fw_ver;                 /* firmware version */

        __be32  tp_microcode_ver;       /* tcp processor microcode version */

        __u8    intfver_nic;

        __u8    intfver_vnic;

        __u8    intfver_ofld;

        __u8    intfver_ri;

        __u8    intfver_iscsipdu;

        __u8    intfver_iscsi;

        __u8    intfver_fcoepdu;

        __u8    intfver_fcoe;

        __u32   reserved2;

        __u32   reserved3;

        __be32  magic;                  /* runtime or bootstrap fw */

        __be32  flags;

        __be32  reserved6[4];

        __u8    reserved7[3];

        __u8    dsign_len;

        __u8    dsign[72];              /* fw binary digital signature */

};


enum fw_hdr_chip {

        FW_HDR_CHIP_T4,

        FW_HDR_CHIP_T5,

        FW_HDR_CHIP_T6

};


#define S_FW_HDR_FW_VER_MAJOR   24

#define M_FW_HDR_FW_VER_MAJOR   0xff

#define V_FW_HDR_FW_VER_MAJOR(x) \

    ((x) << S_FW_HDR_FW_VER_MAJOR)

#define G_FW_HDR_FW_VER_MAJOR(x) \

    (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)


#define S_FW_HDR_FW_VER_MINOR   16

#define M_FW_HDR_FW_VER_MINOR   0xff

#define V_FW_HDR_FW_VER_MINOR(x) \

    ((x) << S_FW_HDR_FW_VER_MINOR)

#define G_FW_HDR_FW_VER_MINOR(x) \

    (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)


#define S_FW_HDR_FW_VER_MICRO   8

#define M_FW_HDR_FW_VER_MICRO   0xff

#define V_FW_HDR_FW_VER_MICRO(x) \

    ((x) << S_FW_HDR_FW_VER_MICRO)

#define G_FW_HDR_FW_VER_MICRO(x) \

    (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)


#define S_FW_HDR_FW_VER_BUILD   0

#define M_FW_HDR_FW_VER_BUILD   0xff

#define V_FW_HDR_FW_VER_BUILD(x) \

    ((x) << S_FW_HDR_FW_VER_BUILD)

#define G_FW_HDR_FW_VER_BUILD(x) \

    (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)


enum {

        T4FW_VERSION_MAJOR      = 1,

        T4FW_VERSION_MINOR      = 26,

        T4FW_VERSION_MICRO      = 6,

        T4FW_VERSION_BUILD      = 0,


        T5FW_VERSION_MAJOR      = 1,

        T5FW_VERSION_MINOR      = 26,

        T5FW_VERSION_MICRO      = 6,

        T5FW_VERSION_BUILD      = 0,


        T6FW_VERSION_MAJOR      = 1,

        T6FW_VERSION_MINOR      = 26,

        T6FW_VERSION_MICRO      = 6,

        T6FW_VERSION_BUILD      = 0,

};


enum {

        /* T4

         */

        T4FW_HDR_INTFVER_NIC    = 0x00,

        T4FW_HDR_INTFVER_VNIC   = 0x00,

        T4FW_HDR_INTFVER_OFLD   = 0x00,

        T4FW_HDR_INTFVER_RI     = 0x00,

        T4FW_HDR_INTFVER_ISCSIPDU= 0x00,

        T4FW_HDR_INTFVER_ISCSI  = 0x00,

        T4FW_HDR_INTFVER_FCOEPDU  = 0x00,

        T4FW_HDR_INTFVER_FCOE   = 0x00,


        /* T5

         */

        T5FW_HDR_INTFVER_NIC    = 0x00,

        T5FW_HDR_INTFVER_VNIC   = 0x00,

        T5FW_HDR_INTFVER_OFLD   = 0x00,

        T5FW_HDR_INTFVER_RI     = 0x00,

        T5FW_HDR_INTFVER_ISCSIPDU= 0x00,

        T5FW_HDR_INTFVER_ISCSI  = 0x00,

        T5FW_HDR_INTFVER_FCOEPDU= 0x00,

        T5FW_HDR_INTFVER_FCOE   = 0x00,


        /* T6

         */

        T6FW_HDR_INTFVER_NIC    = 0x00,

        T6FW_HDR_INTFVER_VNIC   = 0x00,

        T6FW_HDR_INTFVER_OFLD   = 0x00,

        T6FW_HDR_INTFVER_RI     = 0x00,

        T6FW_HDR_INTFVER_ISCSIPDU= 0x00,

        T6FW_HDR_INTFVER_ISCSI  = 0x00,

        T6FW_HDR_INTFVER_FCOEPDU= 0x00,

        T6FW_HDR_INTFVER_FCOE   = 0x00,

};


#define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \

    V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \

    V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD))


enum {

        FW_HDR_MAGIC_RUNTIME    = 0x00000000,

        FW_HDR_MAGIC_BOOTSTRAP  = 0x626f6f74,

};


enum fw_hdr_flags {

        FW_HDR_FLAGS_RESET_HALT = 0x00000001,

        FW_HDR_FLAGS_SIGNED_FW  = 0x00000002,

};


/*

 *      External PHY firmware binary header format

 */

struct fw_ephy_hdr {

        __u8    ver;

        __u8    reserved;

        __be16  len512;                 /* bin length in units of 512-bytes */

        __be32  magic;


        __be16  vendor_id;

        __be16  device_id;

        __be32  version;


        __be32  reserved1[4];

};


enum {

        FW_EPHY_HDR_MAGIC       = 0x65706879,

};


struct fw_ifconf_dhcp_info {

        __be32          addr;

        __be32          mask;

        __be16          vlanid;

        __be16          mtu;

        __be32          gw;

        __u8            op;

        __u8            len;

        __u8            data[270];

};


struct fw_ifconf_ping_info {

        __be16          ping_pldsize;

};


#endif /* _T4FW_INTERFACE_H_ */

__be32
uint32_t __be32
Definition: osdep.h:69

__u32
uint32_t __u32
Definition: osdep.h:65

__be64
uint64_t __be64
Definition: osdep.h:70

__u8
uint8_t __u8
Definition: osdep.h:63

__be16
uint16_t __be16
Definition: osdep.h:68

__u16
uint16_t __u16
Definition: osdep.h:64

__u64
uint64_t __u64
Definition: osdep.h:66

fw_acl_mac_cmd
Definition: t4fw_interface.h:7038

fw_acl_mac_cmd::macaddr1
__u8 macaddr1[6]
Definition: t4fw_interface.h:7046

fw_acl_mac_cmd::r3
__u8 r3[7]
Definition: t4fw_interface.h:7042

fw_acl_mac_cmd::macaddr2
__u8 macaddr2[6]
Definition: t4fw_interface.h:7048

fw_acl_mac_cmd::macaddr0
__u8 macaddr0[6]
Definition: t4fw_interface.h:7044

fw_acl_mac_cmd::r5
__be16 r5
Definition: t4fw_interface.h:7045

fw_acl_mac_cmd::nmac
__u8 nmac
Definition: t4fw_interface.h:7041

fw_acl_mac_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:7039

fw_acl_mac_cmd::r6
__be16 r6
Definition: t4fw_interface.h:7047

fw_acl_mac_cmd::r4
__be16 r4
Definition: t4fw_interface.h:7043

fw_acl_mac_cmd::en_to_len16
__be32 en_to_len16
Definition: t4fw_interface.h:7040

fw_acl_mac_cmd::r7
__be16 r7
Definition: t4fw_interface.h:7049

fw_acl_mac_cmd::macaddr3
__u8 macaddr3[6]
Definition: t4fw_interface.h:7050

fw_acl_vlan_cmd
Definition: t4fw_interface.h:7072

fw_acl_vlan_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:7073

fw_acl_vlan_cmd::en_to_len16
__be32 en_to_len16
Definition: t4fw_interface.h:7074

fw_acl_vlan_cmd::vlanid
__be16 vlanid[16]
Definition: t4fw_interface.h:7078

fw_acl_vlan_cmd::nvlan
__u8 nvlan
Definition: t4fw_interface.h:7075

fw_acl_vlan_cmd::r3_lo
__u8 r3_lo[6]
Definition: t4fw_interface.h:7077

fw_acl_vlan_cmd::dropnovlan_fm
__u8 dropnovlan_fm
Definition: t4fw_interface.h:7076

fw_bye_cmd
Definition: t4fw_interface.h:4581

fw_bye_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:4582

fw_bye_cmd::r3
__be64 r3
Definition: t4fw_interface.h:4584

fw_bye_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:4583

fw_caps_config_cmd
Definition: t4fw_interface.h:4713

fw_caps_config_cmd::toecaps
__be16 toecaps
Definition: t4fw_interface.h:4723

fw_caps_config_cmd::r2
__be32 r2
Definition: t4fw_interface.h:4716

fw_caps_config_cmd::switchcaps
__be16 switchcaps
Definition: t4fw_interface.h:4720

fw_caps_config_cmd::hwmbitmap
__be32 hwmbitmap
Definition: t4fw_interface.h:4717

fw_caps_config_cmd::cryptocaps
__be16 cryptocaps
Definition: t4fw_interface.h:4725

fw_caps_config_cmd::cfvalid_to_len16
__be32 cfvalid_to_len16
Definition: t4fw_interface.h:4715

fw_caps_config_cmd::r3
__be16 r3
Definition: t4fw_interface.h:4721

fw_caps_config_cmd::finiver
__be32 finiver
Definition: t4fw_interface.h:4729

fw_caps_config_cmd::linkcaps
__be16 linkcaps
Definition: t4fw_interface.h:4719

fw_caps_config_cmd::finicsum
__be32 finicsum
Definition: t4fw_interface.h:4730

fw_caps_config_cmd::rdmacaps
__be16 rdmacaps
Definition: t4fw_interface.h:4724

fw_caps_config_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:4714

fw_caps_config_cmd::fcoecaps
__be16 fcoecaps
Definition: t4fw_interface.h:4727

fw_caps_config_cmd::iscsicaps
__be16 iscsicaps
Definition: t4fw_interface.h:4726

fw_caps_config_cmd::cfcsum
__be32 cfcsum
Definition: t4fw_interface.h:4728

fw_caps_config_cmd::niccaps
__be16 niccaps
Definition: t4fw_interface.h:4722

fw_caps_config_cmd::nbmcaps
__be16 nbmcaps
Definition: t4fw_interface.h:4718

fw_chnet_iface_cmd
Definition: t4fw_interface.h:8970

fw_chnet_iface_cmd::r2
__u8 r2[2]
Definition: t4fw_interface.h:8974

fw_chnet_iface_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8972

fw_chnet_iface_cmd::mac
__u8 mac[6]
Definition: t4fw_interface.h:8981

fw_chnet_iface_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:8971

fw_chnet_iface_cmd::vlanid
__be16 vlanid
Definition: t4fw_interface.h:8978

fw_chnet_iface_cmd::flags
__u8 flags
Definition: t4fw_interface.h:8975

fw_chnet_iface_cmd::r4
__be16 r4
Definition: t4fw_interface.h:8980

fw_chnet_iface_cmd::mtu
__be16 mtu
Definition: t4fw_interface.h:8977

fw_chnet_iface_cmd::subop
__u8 subop
Definition: t4fw_interface.h:8973

fw_chnet_iface_cmd::ifid_ifstate
__be32 ifid_ifstate
Definition: t4fw_interface.h:8976

fw_chnet_iface_cmd::r3
__be32 r3
Definition: t4fw_interface.h:8979

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4
Definition: t4fw_interface.h:2242

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4::r1
__be64 r1
Definition: t4fw_interface.h:2247

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4::r0
__be32 r0
Definition: t4fw_interface.h:2246

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4::router
__be32 router
Definition: t4fw_interface.h:2245

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4::addr
__be32 addr
Definition: t4fw_interface.h:2243

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4::mask
__be32 mask
Definition: t4fw_interface.h:2244

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6
Definition: t4fw_interface.h:2249

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::addr_lo
__be64 addr_lo
Definition: t4fw_interface.h:2255

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::router_hi
__be64 router_hi
Definition: t4fw_interface.h:2256

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::r0
__u8 r0
Definition: t4fw_interface.h:2251

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::r1
__be16 r1
Definition: t4fw_interface.h:2252

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::prefix_len
__u8 prefix_len
Definition: t4fw_interface.h:2250

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::router_lo
__be64 router_lo
Definition: t4fw_interface.h:2257

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::addr_hi
__be64 addr_hi
Definition: t4fw_interface.h:2254

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6::r2
__be32 r2
Definition: t4fw_interface.h:2253

fw_chnet_ifconf_wr::fw_chnet_ifconf_params
Definition: t4fw_interface.h:2236

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::in_attr
union fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type in_attr

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::r0
__be16 r0
Definition: t4fw_interface.h:2238

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::ping_pldsize
__be16 ping_pldsize
Definition: t4fw_interface.h:2237

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::mtu
__be16 mtu
Definition: t4fw_interface.h:2240

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::vlanid
__be16 vlanid
Definition: t4fw_interface.h:2239

fw_chnet_ifconf_wr
Definition: t4fw_interface.h:2212

fw_chnet_ifconf_wr::r2
__u8 r2
Definition: t4fw_interface.h:2220

fw_chnet_ifconf_wr::peer_mac
__u8 peer_mac[6]
Definition: t4fw_interface.h:2232

fw_chnet_ifconf_wr::u
union fw_chnet_ifconf_wr::@69 u

fw_chnet_ifconf_wr::ping_seq
__be16 ping_seq
Definition: t4fw_interface.h:2229

fw_chnet_ifconf_wr::ping_ttl
__u8 ping_ttl
Definition: t4fw_interface.h:2228

fw_chnet_ifconf_wr::r3
__be64 r3
Definition: t4fw_interface.h:2222

fw_chnet_ifconf_wr::ping_param_rspcode_to_fin_bit
__u8 ping_param_rspcode_to_fin_bit
Definition: t4fw_interface.h:2226

fw_chnet_ifconf_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:2214

fw_chnet_ifconf_wr::smac_idx
__u8 smac_idx
Definition: t4fw_interface.h:2233

fw_chnet_ifconf_wr::if_flowid
__be32 if_flowid
Definition: t4fw_interface.h:2216

fw_chnet_ifconf_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2215

fw_chnet_ifconf_wr::subop
__u8 subop
Definition: t4fw_interface.h:2218

fw_chnet_ifconf_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:2213

fw_chnet_ifconf_wr::idx
__u8 idx
Definition: t4fw_interface.h:2217

fw_chnet_ifconf_wr::ping_time
__be16 ping_time
Definition: t4fw_interface.h:2224

fw_chnet_ifconf_wr::ping_rsptype
__u8 ping_rsptype
Definition: t4fw_interface.h:2225

fw_chnet_ifconf_wr::retval
__u8 retval
Definition: t4fw_interface.h:2219

fw_chnet_ifconf_wr::ping
struct fw_chnet_ifconf_wr::@69::fw_chnet_ifconf_ping ping

fw_chnet_ifconf_wr::ping_pktsize
__u8 ping_pktsize
Definition: t4fw_interface.h:2227

fw_chnet_ifconf_wr::mac
struct fw_chnet_ifconf_wr::@69::fw_chnet_ifconf_mac mac

fw_chnet_ifconf_wr::param
struct fw_chnet_ifconf_wr::fw_chnet_ifconf_params param

fw_clip2_cmd
Definition: t4fw_interface.h:8942

fw_clip2_cmd::ipm_lo
__be64 ipm_lo
Definition: t4fw_interface.h:8948

fw_clip2_cmd::ipm_hi
__be64 ipm_hi
Definition: t4fw_interface.h:8947

fw_clip2_cmd::ip_hi
__be64 ip_hi
Definition: t4fw_interface.h:8945

fw_clip2_cmd::ip_lo
__be64 ip_lo
Definition: t4fw_interface.h:8946

fw_clip2_cmd::r4
__be32 r4[2]
Definition: t4fw_interface.h:8949

fw_clip2_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8943

fw_clip2_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:8944

fw_clip_cmd
Definition: t4fw_interface.h:8914

fw_clip_cmd::ip_hi
__be64 ip_hi
Definition: t4fw_interface.h:8917

fw_clip_cmd::ip_lo
__be64 ip_lo
Definition: t4fw_interface.h:8918

fw_clip_cmd::r4
__be32 r4[2]
Definition: t4fw_interface.h:8919

fw_clip_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:8916

fw_clip_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8915

fw_cmd_hdr
Definition: t4fw_interface.h:4183

fw_cmd_hdr::hi
__be32 hi
Definition: t4fw_interface.h:4184

fw_cmd_hdr::lo
__be32 lo
Definition: t4fw_interface.h:4185

fw_cmd_wr
Definition: t4fw_interface.h:1158

fw_cmd_wr::op_dma
__be32 op_dma
Definition: t4fw_interface.h:1159

fw_cmd_wr::cookie_daddr
__be64 cookie_daddr
Definition: t4fw_interface.h:1161

fw_cmd_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:1160

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource
Definition: t4fw_interface.h:3108

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_ipv4_tgt
__u8 num_ipv4_tgt
Definition: t4fw_interface.h:3109

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_bufll64
__be32 num_bufll64
Definition: t4fw_interface.h:3115

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_l2t_entries
__be16 num_l2t_entries
Definition: t4fw_interface.h:3111

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_ppods_zone
__be16 num_ppods_zone[11]
Definition: t4fw_interface.h:3114

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_csocks
__be16 num_csocks
Definition: t4fw_interface.h:3112

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::r2
__u8 r2[12]
Definition: t4fw_interface.h:3116

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_tasks
__be16 num_tasks
Definition: t4fw_interface.h:3113

fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource::num_ipv6_tgt
__u8 num_ipv6_tgt
Definition: t4fw_interface.h:3110

fw_coiscsi_stats_wr
Definition: t4fw_interface.h:3101

fw_coiscsi_stats_wr::subop
__u8 subop
Definition: t4fw_interface.h:3105

fw_coiscsi_stats_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:3102

fw_coiscsi_stats_wr::status
__u8 status
Definition: t4fw_interface.h:3106

fw_coiscsi_stats_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3103

fw_coiscsi_stats_wr::u
union fw_coiscsi_stats_wr::fw_coiscsi_stats u

fw_coiscsi_stats_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:3104

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi
Definition: t4fw_interface.h:2962

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::cur_sn
__be32 cur_sn
Definition: t4fw_interface.h:2970

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::tgt_id
__be32 tgt_id
Definition: t4fw_interface.h:2964

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::max_rdsl
__be32 max_rdsl
Definition: t4fw_interface.h:2968

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::r6
__be32 r6
Definition: t4fw_interface.h:2971

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::max_burst
__be32 max_burst
Definition: t4fw_interface.h:2967

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::max_r2t
__be16 max_r2t
Definition: t4fw_interface.h:2965

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::max_tdsl
__be32 max_tdsl
Definition: t4fw_interface.h:2969

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::r5
__be16 r5
Definition: t4fw_interface.h:2966

fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi::hdigest_to_ddp_pgsz
__be32 hdigest_to_ddp_pgsz
Definition: t4fw_interface.h:2963

fw_coiscsi_tgt_conn_wr
Definition: t4fw_interface.h:2928

fw_coiscsi_tgt_conn_wr::in_stid
__be32 in_stid
Definition: t4fw_interface.h:2935

fw_coiscsi_tgt_conn_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:2929

fw_coiscsi_tgt_conn_wr::u
union fw_coiscsi_tgt_conn_wr::@70::fw_coiscsi_tgt_conn_tcp::fw_coiscsi_tgt_conn_tcp_addr u

fw_coiscsi_tgt_conn_wr::flags_fin
__be32 flags_fin
Definition: t4fw_interface.h:2937

fw_coiscsi_tgt_conn_wr::in_sport
__be16 in_sport
Definition: t4fw_interface.h:2940

fw_coiscsi_tgt_conn_wr::conn_iscsi
struct fw_coiscsi_tgt_conn_wr::fw_coiscsi_tgt_conn_iscsi conn_iscsi

fw_coiscsi_tgt_conn_wr::iq_id
__be16 iq_id
Definition: t4fw_interface.h:2934

fw_coiscsi_tgt_conn_wr::in_addr
struct fw_coiscsi_tgt_conn_wr::@70::fw_coiscsi_tgt_conn_tcp::fw_coiscsi_tgt_conn_tcp_addr::fw_coiscsi_tgt_conn_tcp_in_addr in_addr

fw_coiscsi_tgt_conn_wr::io_id
__be32 io_id
Definition: t4fw_interface.h:2936

fw_coiscsi_tgt_conn_wr::saddr
__be32 saddr
Definition: t4fw_interface.h:2946

fw_coiscsi_tgt_conn_wr::wscale_wsen
__u8 wscale_wsen
Definition: t4fw_interface.h:2942

fw_coiscsi_tgt_conn_wr::daddr
__be32 daddr
Definition: t4fw_interface.h:2947

fw_coiscsi_tgt_conn_wr::subop
__u8 subop
Definition: t4fw_interface.h:2932

fw_coiscsi_tgt_conn_wr::conn_tcp
struct fw_coiscsi_tgt_conn_wr::@70::fw_coiscsi_tgt_conn_tcp conn_tcp

fw_coiscsi_tgt_conn_wr::r4
__u8 r4[3]
Definition: t4fw_interface.h:2943

fw_coiscsi_tgt_conn_wr::in_dport
__be16 in_dport
Definition: t4fw_interface.h:2941

fw_coiscsi_tgt_conn_wr::ddp_aborts
__be16 ddp_aborts
Definition: t4fw_interface.h:2958

fw_coiscsi_tgt_conn_wr::status
__u8 status
Definition: t4fw_interface.h:2933

fw_coiscsi_tgt_conn_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:2930

fw_coiscsi_tgt_conn_wr::ddp_reqs
__be32 ddp_reqs
Definition: t4fw_interface.h:2956

fw_coiscsi_tgt_conn_wr::in_addr6
struct fw_coiscsi_tgt_conn_wr::@70::fw_coiscsi_tgt_conn_tcp::fw_coiscsi_tgt_conn_tcp_addr::fw_coiscsi_tgt_conn_tcp_in_addr6 in_addr6

fw_coiscsi_tgt_conn_wr::stats
struct fw_coiscsi_tgt_conn_wr::@70::fw_coiscsi_tgt_conn_stats stats

fw_coiscsi_tgt_conn_wr::ddp_bps
__be16 ddp_bps
Definition: t4fw_interface.h:2959

fw_coiscsi_tgt_conn_wr::ddp_cmpls
__be32 ddp_cmpls
Definition: t4fw_interface.h:2957

fw_coiscsi_tgt_conn_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2931

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr
Definition: t4fw_interface.h:2910

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr::addr
__be32 addr
Definition: t4fw_interface.h:2911

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr::r8
__be32 r8[2]
Definition: t4fw_interface.h:2913

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr::r7
__be32 r7
Definition: t4fw_interface.h:2912

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr6
Definition: t4fw_interface.h:2915

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr6::addr
__be64 addr[2]
Definition: t4fw_interface.h:2916

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr
Definition: t4fw_interface.h:2904

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::in_type
__u8 in_type
Definition: t4fw_interface.h:2907

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::u
union fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr u

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::in_tid
__be32 in_tid
Definition: t4fw_interface.h:2905

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::in_port
__be16 in_port
Definition: t4fw_interface.h:2906

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::r6
__u8 r6
Definition: t4fw_interface.h:2908

fw_coiscsi_tgt_wr
Definition: t4fw_interface.h:2896

fw_coiscsi_tgt_wr::conn_attr
struct fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr conn_attr

fw_coiscsi_tgt_wr::flags
__be32 flags
Definition: t4fw_interface.h:2903

fw_coiscsi_tgt_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:2897

fw_coiscsi_tgt_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:2898

fw_coiscsi_tgt_wr::status
__u8 status
Definition: t4fw_interface.h:2901

fw_coiscsi_tgt_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2899

fw_coiscsi_tgt_wr::subop
__u8 subop
Definition: t4fw_interface.h:2900

fw_coiscsi_tgt_wr::r4
__be16 r4
Definition: t4fw_interface.h:2902

fw_coiscsi_tgt_xmit_wr
Definition: t4fw_interface.h:3006

fw_coiscsi_tgt_xmit_wr::cu
union fw_coiscsi_tgt_xmit_wr::@72 cu

fw_coiscsi_tgt_xmit_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:3007

fw_coiscsi_tgt_xmit_wr::fllen
struct fw_coiscsi_tgt_xmit_wr::@71::flowid_len fllen

fw_coiscsi_tgt_xmit_wr::pz_off
__be32 pz_off
Definition: t4fw_interface.h:3019

fw_coiscsi_tgt_xmit_wr::r3
__be16 r3
Definition: t4fw_interface.h:3018

fw_coiscsi_tgt_xmit_wr::tag
__be32 tag
Definition: t4fw_interface.h:3022

fw_coiscsi_tgt_xmit_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:3016

fw_coiscsi_tgt_xmit_wr::u
union fw_coiscsi_tgt_xmit_wr::@71 u

fw_coiscsi_tgt_xmit_wr::iq_id
__be16 iq_id
Definition: t4fw_interface.h:3017

fw_coiscsi_tgt_xmit_wr::ddp_status
__be32 ddp_status
Definition: t4fw_interface.h:3024

fw_coiscsi_tgt_xmit_wr::t_xfer_len
__be32 t_xfer_len
Definition: t4fw_interface.h:3020

fw_coiscsi_tgt_xmit_wr::cs
struct fw_coiscsi_tgt_xmit_wr::@71::cmpl_stat cs

fw_coiscsi_tgt_xmit_wr::cmpl_status_pkd
__be32 cmpl_status_pkd
Definition: t4fw_interface.h:3010

fw_coiscsi_tgt_xmit_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3013

fw_coiscsi_tgt_xmit_wr::datasn
__be32 datasn
Definition: t4fw_interface.h:3023

fw_crypto_lookaside_wr
Definition: t4fw_interface.h:3961

fw_crypto_lookaside_wr::session_id
__be32 session_id
Definition: t4fw_interface.h:3964

fw_crypto_lookaside_wr::pld_size_hash_size
__be32 pld_size_hash_size
Definition: t4fw_interface.h:3967

fw_crypto_lookaside_wr::key_addr
__be32 key_addr
Definition: t4fw_interface.h:3966

fw_crypto_lookaside_wr::rx_chid_to_rx_q_id
__be32 rx_chid_to_rx_q_id
Definition: t4fw_interface.h:3965

fw_crypto_lookaside_wr::op_to_cctx_size
__be32 op_to_cctx_size
Definition: t4fw_interface.h:3962

fw_crypto_lookaside_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:3963

fw_crypto_lookaside_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3968

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_app_stats_ieee
Definition: t4fw_interface.h:9407

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_app_stats_ieee::r6
__be32 r6
Definition: t4fw_interface.h:9409

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_app_stats_ieee::app
__be32 app[4]
Definition: t4fw_interface.h:9410

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_app_stats_ieee::num_apps_pkd
__be32 num_apps_pkd
Definition: t4fw_interface.h:9408

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_control
Definition: t4fw_interface.h:9412

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_control::r6
__u8 r6[3]
Definition: t4fw_interface.h:9415

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_control::version
__u8 version
Definition: t4fw_interface.h:9414

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_control::multi_peer_invalidated
__be32 multi_peer_invalidated
Definition: t4fw_interface.h:9413

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_ets_stats_ieee
Definition: t4fw_interface.h:9401

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_ets_stats_ieee::tsa
__u8 tsa[8]
Definition: t4fw_interface.h:9405

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_ets_stats_ieee::pg_table
__be32 pg_table
Definition: t4fw_interface.h:9403

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_ets_stats_ieee::cbs_to_ets_max_tc
__be32 cbs_to_ets_max_tc
Definition: t4fw_interface.h:9402

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_ets_stats_ieee::pg_percent
__u8 pg_percent[8]
Definition: t4fw_interface.h:9404

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_pfc_stats_ieee
Definition: t4fw_interface.h:9397

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_pfc_stats_ieee::pfc_willing_to_pfc_en
__be32 pfc_willing_to_pfc_en
Definition: t4fw_interface.h:9399

fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_pfc_stats_ieee::pfc_mbc_pkd
__be32 pfc_mbc_pkd
Definition: t4fw_interface.h:9398

fw_dcb_ieee_cmd
Definition: t4fw_interface.h:9393

fw_dcb_ieee_cmd::changed_to_len16
__be32 changed_to_len16
Definition: t4fw_interface.h:9395

fw_dcb_ieee_cmd::op_to_location
__be32 op_to_location
Definition: t4fw_interface.h:9394

fw_dcb_ieee_cmd::u
union fw_dcb_ieee_cmd::fw_dcbx_stats u

fw_debug_cmd::fw_debug::fw_debug_assert
Definition: t4fw_interface.h:9638

fw_debug_cmd::fw_debug::fw_debug_assert::y
__be32 y
Definition: t4fw_interface.h:9642

fw_debug_cmd::fw_debug::fw_debug_assert::filename_8_15
__u8 filename_8_15[8]
Definition: t4fw_interface.h:9644

fw_debug_cmd::fw_debug::fw_debug_assert::line
__be32 line
Definition: t4fw_interface.h:9640

fw_debug_cmd::fw_debug::fw_debug_assert::fcid
__be32 fcid
Definition: t4fw_interface.h:9639

fw_debug_cmd::fw_debug::fw_debug_assert::filename_0_7
__u8 filename_0_7[8]
Definition: t4fw_interface.h:9643

fw_debug_cmd::fw_debug::fw_debug_assert::r3
__be64 r3
Definition: t4fw_interface.h:9645

fw_debug_cmd::fw_debug::fw_debug_assert::x
__be32 x
Definition: t4fw_interface.h:9641

fw_debug_cmd::fw_debug::fw_debug_prt
Definition: t4fw_interface.h:9647

fw_debug_cmd::fw_debug::fw_debug_prt::dprtstrparam3
__be32 dprtstrparam3
Definition: t4fw_interface.h:9653

fw_debug_cmd::fw_debug::fw_debug_prt::dprtstrparam2
__be32 dprtstrparam2
Definition: t4fw_interface.h:9652

fw_debug_cmd::fw_debug::fw_debug_prt::dprtstrparam0
__be32 dprtstrparam0
Definition: t4fw_interface.h:9650

fw_debug_cmd::fw_debug::fw_debug_prt::r3
__be16 r3[3]
Definition: t4fw_interface.h:9649

fw_debug_cmd::fw_debug::fw_debug_prt::dprtstridx
__be16 dprtstridx
Definition: t4fw_interface.h:9648

fw_debug_cmd::fw_debug::fw_debug_prt::dprtstrparam1
__be32 dprtstrparam1
Definition: t4fw_interface.h:9651

fw_debug_cmd
Definition: t4fw_interface.h:9634

fw_debug_cmd::u
union fw_debug_cmd::fw_debug u

fw_debug_cmd::op_type
__be32 op_type
Definition: t4fw_interface.h:9635

fw_debug_cmd::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:9636

fw_devlog_cmd
Definition: t4fw_interface.h:8858

fw_devlog_cmd::r2
__u8 r2[7]
Definition: t4fw_interface.h:8862

fw_devlog_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8860

fw_devlog_cmd::memtype_devlog_memaddr16_devlog
__be32 memtype_devlog_memaddr16_devlog
Definition: t4fw_interface.h:8863

fw_devlog_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8859

fw_devlog_cmd::level
__u8 level
Definition: t4fw_interface.h:8861

fw_devlog_cmd::r3
__be32 r3[2]
Definition: t4fw_interface.h:8865

fw_devlog_cmd::memsize_devlog
__be32 memsize_devlog
Definition: t4fw_interface.h:8864

fw_devlog_e
Definition: t4fw_interface.h:8847

fw_devlog_e::seqno
__be32 seqno
Definition: t4fw_interface.h:8849

fw_devlog_e::facility
__u8 facility
Definition: t4fw_interface.h:8852

fw_devlog_e::timestamp
__be64 timestamp
Definition: t4fw_interface.h:8848

fw_devlog_e::reserved1
__be16 reserved1
Definition: t4fw_interface.h:8850

fw_devlog_e::fmt
__u8 fmt[FW_DEVLOG_FMT_LEN]
Definition: t4fw_interface.h:8853

fw_devlog_e::params
__be32 params[FW_DEVLOG_FMT_PARAMS_NUM]
Definition: t4fw_interface.h:8854

fw_devlog_e::reserved3
__be32 reserved3[4]
Definition: t4fw_interface.h:8855

fw_devlog_e::level
__u8 level
Definition: t4fw_interface.h:8851

fw_diag_cmd::fw_diag_test::fw_diag_test_memtest_diag
Definition: t4fw_interface.h:9709

fw_diag_cmd::fw_diag_test::fw_diag_test_memtest_diag::duration
__be32 duration
Definition: t4fw_interface.h:9713

fw_diag_cmd::fw_diag_test::fw_diag_test_memtest_diag::size
__be16 size
Definition: t4fw_interface.h:9712

fw_diag_cmd::fw_diag_test::fw_diag_test_memtest_diag::test_op
__u8 test_op
Definition: t4fw_interface.h:9710

fw_diag_cmd::fw_diag_test::fw_diag_test_memtest_diag::test_status
__u8 test_status
Definition: t4fw_interface.h:9711

fw_diag_cmd::fw_diag_test::fw_diag_test_ofldiag
Definition: t4fw_interface.h:9703

fw_diag_cmd::fw_diag_test::fw_diag_test_ofldiag::test_op
__u8 test_op
Definition: t4fw_interface.h:9704

fw_diag_cmd::fw_diag_test::fw_diag_test_ofldiag::test_status
__be16 test_status
Definition: t4fw_interface.h:9706

fw_diag_cmd::fw_diag_test::fw_diag_test_ofldiag::duration
__be32 duration
Definition: t4fw_interface.h:9707

fw_diag_cmd::fw_diag_test::fw_diag_test_ofldiag::r3
__u8 r3
Definition: t4fw_interface.h:9705

fw_diag_cmd
Definition: t4fw_interface.h:9699

fw_diag_cmd::op_type
__be32 op_type
Definition: t4fw_interface.h:9700

fw_diag_cmd::u
union fw_diag_cmd::fw_diag_test u

fw_diag_cmd::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:9701

fw_ephy_hdr
Definition: t4fw_interface.h:10072

fw_ephy_hdr::version
__be32 version
Definition: t4fw_interface.h:10080

fw_ephy_hdr::reserved1
__be32 reserved1[4]
Definition: t4fw_interface.h:10082

fw_ephy_hdr::vendor_id
__be16 vendor_id
Definition: t4fw_interface.h:10078

fw_ephy_hdr::magic
__be32 magic
Definition: t4fw_interface.h:10076

fw_ephy_hdr::len512
__be16 len512
Definition: t4fw_interface.h:10075

fw_ephy_hdr::device_id
__be16 device_id
Definition: t4fw_interface.h:10079

fw_ephy_hdr::ver
__u8 ver
Definition: t4fw_interface.h:10073

fw_ephy_hdr::reserved
__u8 reserved
Definition: t4fw_interface.h:10074

fw_eq_ctrl_cmd
Definition: t4fw_interface.h:6138

fw_eq_ctrl_cmd::eqaddr
__be64 eqaddr
Definition: t4fw_interface.h:6145

fw_eq_ctrl_cmd::dcaen_to_eqsize
__be32 dcaen_to_eqsize
Definition: t4fw_interface.h:6144

fw_eq_ctrl_cmd::fetchszm_to_iqid
__be32 fetchszm_to_iqid
Definition: t4fw_interface.h:6143

fw_eq_ctrl_cmd::cmpliqid_eqid
__be32 cmpliqid_eqid
Definition: t4fw_interface.h:6141

fw_eq_ctrl_cmd::physeqid_pkd
__be32 physeqid_pkd
Definition: t4fw_interface.h:6142

fw_eq_ctrl_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:6140

fw_eq_ctrl_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:6139

fw_eq_eth_cmd
Definition: t4fw_interface.h:5922

fw_eq_eth_cmd::dcaen_to_eqsize
__be32 dcaen_to_eqsize
Definition: t4fw_interface.h:5928

fw_eq_eth_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5923

fw_eq_eth_cmd::r9
__be64 r9
Definition: t4fw_interface.h:5932

fw_eq_eth_cmd::physeqid_pkd
__be32 physeqid_pkd
Definition: t4fw_interface.h:5926

fw_eq_eth_cmd::timeren_timerix
__be32 timeren_timerix
Definition: t4fw_interface.h:5931

fw_eq_eth_cmd::autoequiqe_to_viid
__be32 autoequiqe_to_viid
Definition: t4fw_interface.h:5930

fw_eq_eth_cmd::fetchszm_to_iqid
__be32 fetchszm_to_iqid
Definition: t4fw_interface.h:5927

fw_eq_eth_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:5924

fw_eq_eth_cmd::eqid_pkd
__be32 eqid_pkd
Definition: t4fw_interface.h:5925

fw_eq_eth_cmd::eqaddr
__be64 eqaddr
Definition: t4fw_interface.h:5929

fw_eq_flush_wr
Definition: t4fw_interface.h:879

fw_eq_flush_wr::r3
__be64 r3
Definition: t4fw_interface.h:883

fw_eq_flush_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:882

fw_eq_flush_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:880

fw_eq_flush_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:881

fw_eq_mngt_cmd
Definition: t4fw_interface.h:5735

fw_eq_mngt_cmd::dcaen_to_eqsize
__be32 dcaen_to_eqsize
Definition: t4fw_interface.h:5741

fw_eq_mngt_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5736

fw_eq_mngt_cmd::eqaddr
__be64 eqaddr
Definition: t4fw_interface.h:5742

fw_eq_mngt_cmd::physeqid_pkd
__be32 physeqid_pkd
Definition: t4fw_interface.h:5739

fw_eq_mngt_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:5737

fw_eq_mngt_cmd::cmpliqid_eqid
__be32 cmpliqid_eqid
Definition: t4fw_interface.h:5738

fw_eq_mngt_cmd::fetchszm_to_iqid
__be32 fetchszm_to_iqid
Definition: t4fw_interface.h:5740

fw_eq_ofld_cmd
Definition: t4fw_interface.h:6325

fw_eq_ofld_cmd::eqaddr
__be64 eqaddr
Definition: t4fw_interface.h:6332

fw_eq_ofld_cmd::fetchszm_to_iqid
__be32 fetchszm_to_iqid
Definition: t4fw_interface.h:6330

fw_eq_ofld_cmd::eqid_pkd
__be32 eqid_pkd
Definition: t4fw_interface.h:6328

fw_eq_ofld_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:6326

fw_eq_ofld_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:6327

fw_eq_ofld_cmd::dcaen_to_eqsize
__be32 dcaen_to_eqsize
Definition: t4fw_interface.h:6331

fw_eq_ofld_cmd::physeqid_pkd
__be32 physeqid_pkd
Definition: t4fw_interface.h:6329

fw_error_cmd::fw_error::fw_error_acl
Definition: t4fw_interface.h:9579

fw_error_cmd::fw_error::fw_error_acl::val
__u8 val[6]
Definition: t4fw_interface.h:9584

fw_error_cmd::fw_error::fw_error_acl::cidx
__be16 cidx
Definition: t4fw_interface.h:9580

fw_error_cmd::fw_error::fw_error_acl::eqid
__be32 eqid
Definition: t4fw_interface.h:9582

fw_error_cmd::fw_error::fw_error_acl::mv_pkd
__be16 mv_pkd
Definition: t4fw_interface.h:9583

fw_error_cmd::fw_error::fw_error_acl::r4
__be64 r4
Definition: t4fw_interface.h:9585

fw_error_cmd::fw_error::fw_error_acl::pfn_vfn
__be16 pfn_vfn
Definition: t4fw_interface.h:9581

fw_error_cmd::fw_error::fw_error_exception
Definition: t4fw_interface.h:9566

fw_error_cmd::fw_error::fw_error_exception::info
__be32 info[6]
Definition: t4fw_interface.h:9567

fw_error_cmd::fw_error::fw_error_hwmodule
Definition: t4fw_interface.h:9569

fw_error_cmd::fw_error::fw_error_hwmodule::regval
__be32 regval
Definition: t4fw_interface.h:9571

fw_error_cmd::fw_error::fw_error_hwmodule::regaddr
__be32 regaddr
Definition: t4fw_interface.h:9570

fw_error_cmd::fw_error::fw_error_wr
Definition: t4fw_interface.h:9573

fw_error_cmd::fw_error::fw_error_wr::wrhdr
__u8 wrhdr[16]
Definition: t4fw_interface.h:9577

fw_error_cmd::fw_error::fw_error_wr::pfn_vfn
__be16 pfn_vfn
Definition: t4fw_interface.h:9575

fw_error_cmd::fw_error::fw_error_wr::cidx
__be16 cidx
Definition: t4fw_interface.h:9574

fw_error_cmd::fw_error::fw_error_wr::eqid
__be32 eqid
Definition: t4fw_interface.h:9576

fw_error_cmd
Definition: t4fw_interface.h:9562

fw_error_cmd::u
union fw_error_cmd::fw_error u

fw_error_cmd::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:9564

fw_error_cmd::op_to_type
__be32 op_to_type
Definition: t4fw_interface.h:9563

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg
Definition: t4fw_interface.h:848

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::iphdroffin
__be16 iphdroffin
Definition: t4fw_interface.h:852

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::iphdroffout
__u8 iphdroffout
Definition: t4fw_interface.h:850

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::tcphdroffin
__be16 tcphdroffin
Definition: t4fw_interface.h:853

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::type
__u8 type
Definition: t4fw_interface.h:849

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::genevehdroff
__be16 genevehdroff
Definition: t4fw_interface.h:851

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::r4
__be16 r4
Definition: t4fw_interface.h:855

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::plen
__be32 plen
Definition: t4fw_interface.h:856

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg::mss
__be16 mss
Definition: t4fw_interface.h:854

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg
Definition: t4fw_interface.h:827

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::tcphdroffin
__be16 tcphdroffin
Definition: t4fw_interface.h:832

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::mss
__be16 mss
Definition: t4fw_interface.h:833

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::iphdroffout
__u8 iphdroffout
Definition: t4fw_interface.h:829

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::r4
__be16 r4
Definition: t4fw_interface.h:834

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::iphdroffin
__be16 iphdroffin
Definition: t4fw_interface.h:831

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::plen
__be32 plen
Definition: t4fw_interface.h:835

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::type
__u8 type
Definition: t4fw_interface.h:828

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg::grehdroff
__be16 grehdroff
Definition: t4fw_interface.h:830

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg
Definition: t4fw_interface.h:816

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::r4
__be16 r4
Definition: t4fw_interface.h:822

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::tsclk_tsoff
__u8 tsclk_tsoff
Definition: t4fw_interface.h:821

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::plen
__be32 plen
Definition: t4fw_interface.h:825

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::ethlen
__u8 ethlen
Definition: t4fw_interface.h:818

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::r5
__be16 r5
Definition: t4fw_interface.h:824

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::mss
__be16 mss
Definition: t4fw_interface.h:823

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::iplen
__be16 iplen
Definition: t4fw_interface.h:819

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::tcplen
__u8 tcplen
Definition: t4fw_interface.h:820

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg::type
__u8 type
Definition: t4fw_interface.h:817

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg
Definition: t4fw_interface.h:805

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::iplen
__be16 iplen
Definition: t4fw_interface.h:808

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::ethlen
__u8 ethlen
Definition: t4fw_interface.h:807

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::schedpktsize
__be16 schedpktsize
Definition: t4fw_interface.h:813

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::type
__u8 type
Definition: t4fw_interface.h:806

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::r4
__be16 r4
Definition: t4fw_interface.h:811

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::mss
__be16 mss
Definition: t4fw_interface.h:812

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::rtplen
__u8 rtplen
Definition: t4fw_interface.h:810

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::plen
__be32 plen
Definition: t4fw_interface.h:814

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg::udplen
__u8 udplen
Definition: t4fw_interface.h:809

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg
Definition: t4fw_interface.h:837

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::r4
__be16 r4
Definition: t4fw_interface.h:844

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::plen
__be32 plen
Definition: t4fw_interface.h:845

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::vxlanhdroff
__be16 vxlanhdroff
Definition: t4fw_interface.h:840

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::mss
__be16 mss
Definition: t4fw_interface.h:843

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::iphdroffin
__be16 iphdroffin
Definition: t4fw_interface.h:841

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::type
__u8 type
Definition: t4fw_interface.h:838

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::iphdroffout
__u8 iphdroffout
Definition: t4fw_interface.h:839

fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg::tcphdroffin
__be16 tcphdroffin
Definition: t4fw_interface.h:842

fw_eth_tx_eo_wr
Definition: t4fw_interface.h:800

fw_eth_tx_eo_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:802

fw_eth_tx_eo_wr::r3
__be64 r3
Definition: t4fw_interface.h:803

fw_eth_tx_eo_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:801

fw_eth_tx_eo_wr::u
union fw_eth_tx_eo_wr::fw_eth_tx_eo u

fw_eth_tx_pkt2_wr
Definition: t4fw_interface.h:713

fw_eth_tx_pkt2_wr::r3
__be32 r3
Definition: t4fw_interface.h:716

fw_eth_tx_pkt2_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:715

fw_eth_tx_pkt2_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:714

fw_eth_tx_pkt2_wr::L4ChkDisable_to_IpHdrLen
__be32 L4ChkDisable_to_IpHdrLen
Definition: t4fw_interface.h:717

fw_eth_tx_pkt_ptp_wr
Definition: t4fw_interface.h:786

fw_eth_tx_pkt_ptp_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:787

fw_eth_tx_pkt_ptp_wr::r3
__be64 r3
Definition: t4fw_interface.h:789

fw_eth_tx_pkt_ptp_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:788

fw_eth_tx_pkt_vm_wr
Definition: t4fw_interface.h:1170

fw_eth_tx_pkt_vm_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:1171

fw_eth_tx_pkt_vm_wr::vlantci
__be16 vlantci
Definition: t4fw_interface.h:1177

fw_eth_tx_pkt_vm_wr::ethmacdst
__u8 ethmacdst[6]
Definition: t4fw_interface.h:1174

fw_eth_tx_pkt_vm_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:1172

fw_eth_tx_pkt_vm_wr::ethmacsrc
__u8 ethmacsrc[6]
Definition: t4fw_interface.h:1175

fw_eth_tx_pkt_vm_wr::ethtype
__be16 ethtype
Definition: t4fw_interface.h:1176

fw_eth_tx_pkt_vm_wr::r3
__be32 r3[2]
Definition: t4fw_interface.h:1173

fw_eth_tx_pkt_wr
Definition: t4fw_interface.h:701

fw_eth_tx_pkt_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:703

fw_eth_tx_pkt_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:702

fw_eth_tx_pkt_wr::r3
__be64 r3
Definition: t4fw_interface.h:704

fw_eth_tx_pkts_vm_wr
Definition: t4fw_interface.h:1180

fw_eth_tx_pkts_vm_wr::npkt
__u8 npkt
Definition: t4fw_interface.h:1185

fw_eth_tx_pkts_vm_wr::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:1181

fw_eth_tx_pkts_vm_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:1182

fw_eth_tx_pkts_vm_wr::r3
__be32 r3
Definition: t4fw_interface.h:1183

fw_eth_tx_pkts_vm_wr::plen
__be16 plen
Definition: t4fw_interface.h:1184

fw_eth_tx_pkts_vm_wr::ethtype
__be16 ethtype
Definition: t4fw_interface.h:1189

fw_eth_tx_pkts_vm_wr::vlantci
__be16 vlantci
Definition: t4fw_interface.h:1190

fw_eth_tx_pkts_vm_wr::r4
__u8 r4
Definition: t4fw_interface.h:1186

fw_eth_tx_pkts_vm_wr::ethmacdst
__u8 ethmacdst[6]
Definition: t4fw_interface.h:1187

fw_eth_tx_pkts_vm_wr::ethmacsrc
__u8 ethmacsrc[6]
Definition: t4fw_interface.h:1188

fw_eth_tx_pkts_wr
Definition: t4fw_interface.h:771

fw_eth_tx_pkts_wr::r3
__be32 r3
Definition: t4fw_interface.h:774

fw_eth_tx_pkts_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:773

fw_eth_tx_pkts_wr::plen
__be16 plen
Definition: t4fw_interface.h:775

fw_eth_tx_pkts_wr::type
__u8 type
Definition: t4fw_interface.h:777

fw_eth_tx_pkts_wr::npkt
__u8 npkt
Definition: t4fw_interface.h:776

fw_eth_tx_pkts_wr::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:772

fw_fcoe_els_ct_wr
Definition: t4fw_interface.h:3180

fw_fcoe_els_ct_wr::rsp_dmaaddr
__be64 rsp_dmaaddr
Definition: t4fw_interface.h:3194

fw_fcoe_els_ct_wr::r_id
__u8 r_id[3]
Definition: t4fw_interface.h:3193

fw_fcoe_els_ct_wr::xfer_cnt
__be16 xfer_cnt
Definition: t4fw_interface.h:3189

fw_fcoe_els_ct_wr::els_ct_type
__u8 els_ct_type
Definition: t4fw_interface.h:3186

fw_fcoe_els_ct_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3182

fw_fcoe_els_ct_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3183

fw_fcoe_els_ct_wr::rsp_dmalen
__be32 rsp_dmalen
Definition: t4fw_interface.h:3195

fw_fcoe_els_ct_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3184

fw_fcoe_els_ct_wr::r5
__u8 r5
Definition: t4fw_interface.h:3192

fw_fcoe_els_ct_wr::tmo_val
__u8 tmo_val
Definition: t4fw_interface.h:3185

fw_fcoe_els_ct_wr::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3188

fw_fcoe_els_ct_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3181

fw_fcoe_els_ct_wr::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3187

fw_fcoe_els_ct_wr::l_id
__u8 l_id[3]
Definition: t4fw_interface.h:3191

fw_fcoe_els_ct_wr::fl_to_sp
__u8 fl_to_sp
Definition: t4fw_interface.h:3190

fw_fcoe_els_ct_wr::r6
__be32 r6
Definition: t4fw_interface.h:3196

fw_fcoe_fcf_cmd
Definition: t4fw_interface.h:9318

fw_fcoe_fcf_cmd::fc_map
__u8 fc_map[3]
Definition: t4fw_interface.h:9328

fw_fcoe_fcf_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:9320

fw_fcoe_fcf_cmd::r7_hi
__u8 r7_hi
Definition: t4fw_interface.h:9331

fw_fcoe_fcf_cmd::op_to_fcfi
__be32 op_to_fcfi
Definition: t4fw_interface.h:9319

fw_fcoe_fcf_cmd::vf_id
__be16 vf_id
Definition: t4fw_interface.h:9325

fw_fcoe_fcf_cmd::r6
__be32 r6
Definition: t4fw_interface.h:9330

fw_fcoe_fcf_cmd::fpma_to_portid
__u8 fpma_to_portid
Definition: t4fw_interface.h:9332

fw_fcoe_fcf_cmd::spma_mac
__u8 spma_mac[6]
Definition: t4fw_interface.h:9333

fw_fcoe_fcf_cmd::r8
__be64 r8
Definition: t4fw_interface.h:9334

fw_fcoe_fcf_cmd::priority_pkd
__be16 priority_pkd
Definition: t4fw_interface.h:9321

fw_fcoe_fcf_cmd::fka_adv
__be32 fka_adv
Definition: t4fw_interface.h:9329

fw_fcoe_fcf_cmd::mac
__u8 mac[6]
Definition: t4fw_interface.h:9322

fw_fcoe_fcf_cmd::fabric
__u8 fabric[8]
Definition: t4fw_interface.h:9324

fw_fcoe_fcf_cmd::vlan_id
__u8 vlan_id
Definition: t4fw_interface.h:9327

fw_fcoe_fcf_cmd::name_id
__u8 name_id[8]
Definition: t4fw_interface.h:9323

fw_fcoe_fcf_cmd::max_fcoe_size
__be16 max_fcoe_size
Definition: t4fw_interface.h:9326

fw_fcoe_link_cmd
Definition: t4fw_interface.h:9035

fw_fcoe_link_cmd::flags
__be16 flags
Definition: t4fw_interface.h:9041

fw_fcoe_link_cmd::r4
__u8 r4
Definition: t4fw_interface.h:9042

fw_fcoe_link_cmd::lstatus
__u8 lstatus
Definition: t4fw_interface.h:9040

fw_fcoe_link_cmd::vnpi_pkd
__be32 vnpi_pkd
Definition: t4fw_interface.h:9045

fw_fcoe_link_cmd::phy_mac
__u8 phy_mac[6]
Definition: t4fw_interface.h:9047

fw_fcoe_link_cmd::r6
__be16 r6
Definition: t4fw_interface.h:9046

fw_fcoe_link_cmd::vnport_wwpn
__u8 vnport_wwpn[8]
Definition: t4fw_interface.h:9049

fw_fcoe_link_cmd::r3
__u8 r3
Definition: t4fw_interface.h:9039

fw_fcoe_link_cmd::vlan_id
__be16 vlan_id
Definition: t4fw_interface.h:9044

fw_fcoe_link_cmd::vnport_wwnn
__u8 vnport_wwnn[8]
Definition: t4fw_interface.h:9048

fw_fcoe_link_cmd::sub_opcode_fcfi
__be32 sub_opcode_fcfi
Definition: t4fw_interface.h:9038

fw_fcoe_link_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:9036

fw_fcoe_link_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:9037

fw_fcoe_link_cmd::set_vlan
__u8 set_vlan
Definition: t4fw_interface.h:9043

fw_fcoe_res_info_cmd
Definition: t4fw_interface.h:9018

fw_fcoe_res_info_cmd::r_a_tov_seq
__be16 r_a_tov_seq
Definition: t4fw_interface.h:9022

fw_fcoe_res_info_cmd::r_a_tov_els
__be16 r_a_tov_els
Definition: t4fw_interface.h:9023

fw_fcoe_res_info_cmd::max_vnps
__be32 max_vnps
Definition: t4fw_interface.h:9030

fw_fcoe_res_info_cmd::used_fcfs
__be32 used_fcfs
Definition: t4fw_interface.h:9031

fw_fcoe_res_info_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:9020

fw_fcoe_res_info_cmd::used_xchgs
__be32 used_xchgs
Definition: t4fw_interface.h:9027

fw_fcoe_res_info_cmd::max_fcfs
__be32 max_fcfs
Definition: t4fw_interface.h:9029

fw_fcoe_res_info_cmd::op_to_read
__be32 op_to_read
Definition: t4fw_interface.h:9019

fw_fcoe_res_info_cmd::max_ssns
__be32 max_ssns
Definition: t4fw_interface.h:9026

fw_fcoe_res_info_cmd::used_ssns
__be32 used_ssns
Definition: t4fw_interface.h:9028

fw_fcoe_res_info_cmd::r_r_tov
__be16 r_r_tov
Definition: t4fw_interface.h:9024

fw_fcoe_res_info_cmd::used_vnps
__be32 used_vnps
Definition: t4fw_interface.h:9032

fw_fcoe_res_info_cmd::max_xchgs
__be32 max_xchgs
Definition: t4fw_interface.h:9025

fw_fcoe_res_info_cmd::e_d_tov
__be16 e_d_tov
Definition: t4fw_interface.h:9021

fw_fcoe_sparams_cmd
Definition: t4fw_interface.h:9144

fw_fcoe_sparams_cmd::cmn_srv_parms
__u8 cmn_srv_parms[16]
Definition: t4fw_interface.h:9151

fw_fcoe_sparams_cmd::lport_wwpn
__u8 lport_wwpn[8]
Definition: t4fw_interface.h:9150

fw_fcoe_sparams_cmd::lport_wwnn
__u8 lport_wwnn[8]
Definition: t4fw_interface.h:9149

fw_fcoe_sparams_cmd::cos
__u8 cos
Definition: t4fw_interface.h:9148

fw_fcoe_sparams_cmd::cls_srv_parms
__u8 cls_srv_parms[16]
Definition: t4fw_interface.h:9152

fw_fcoe_sparams_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:9146

fw_fcoe_sparams_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:9145

fw_fcoe_sparams_cmd::r3
__u8 r3[7]
Definition: t4fw_interface.h:9147

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats
Definition: t4fw_interface.h:9195

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fcf_ka
__be64 fcf_ka
Definition: t4fw_interface.h:9198

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::clr_vlink
__be16 clr_vlink
Definition: t4fw_interface.h:9204

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fip_tx_fr
__be32 fip_tx_fr
Definition: t4fw_interface.h:9197

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::link_up
__be16 link_up
Definition: t4fw_interface.h:9206

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::no_vnp
__u8 no_vnp
Definition: t4fw_interface.h:9216

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fdisc_req
__be16 fdisc_req
Definition: t4fw_interface.h:9210

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::no_fka_req
__u8 no_fka_req
Definition: t4fw_interface.h:9215

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::sol_sent
__be16 sol_sent
Definition: t4fw_interface.h:9201

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::flogi_rpl
__be16 flogi_rpl
Definition: t4fw_interface.h:9209

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fdisc_rpl
__be16 fdisc_rpl
Definition: t4fw_interface.h:9211

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::vlan_req
__be16 vlan_req
Definition: t4fw_interface.h:9202

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fc_map_chg
__be16 fc_map_chg
Definition: t4fw_interface.h:9213

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::vfid_chg
__be16 vfid_chg
Definition: t4fw_interface.h:9214

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::ucast_adv_rcvd
__be16 ucast_adv_rcvd
Definition: t4fw_interface.h:9200

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fip_tx_bytes
__be32 fip_tx_bytes
Definition: t4fw_interface.h:9196

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::vlan_rpl
__be16 vlan_rpl
Definition: t4fw_interface.h:9203

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::flogi_req
__be16 flogi_req
Definition: t4fw_interface.h:9208

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::logo
__be16 logo
Definition: t4fw_interface.h:9207

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::link_down
__be16 link_down
Definition: t4fw_interface.h:9205

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::mcast_adv_rcvd
__be64 mcast_adv_rcvd
Definition: t4fw_interface.h:9199

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats::fka_prd_chg
__be16 fka_prd_chg
Definition: t4fw_interface.h:9212

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats
Definition: t4fw_interface.h:9218

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::flogi_rjt
__be16 flogi_rjt
Definition: t4fw_interface.h:9229

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::fdisc_rjt
__be16 fdisc_rjt
Definition: t4fw_interface.h:9230

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::mac_flt_fail
__be16 mac_flt_fail
Definition: t4fw_interface.h:9232

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::tx_frames
__be64 tx_frames
Definition: t4fw_interface.h:9220

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::unsol_els_rcvd
__be32 unsol_els_rcvd
Definition: t4fw_interface.h:9224

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::flogi_inv_sparm
__be16 flogi_inv_sparm
Definition: t4fw_interface.h:9227

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::unsol_cmd_rcvd
__be64 unsol_cmd_rcvd
Definition: t4fw_interface.h:9225

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::inv_fr_rcvd
__be16 inv_fr_rcvd
Definition: t4fw_interface.h:9233

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::vnp_ka
__be32 vnp_ka
Definition: t4fw_interface.h:9223

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::rx_bytes
__be64 rx_bytes
Definition: t4fw_interface.h:9221

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::rx_frames
__be64 rx_frames
Definition: t4fw_interface.h:9222

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::tx_bytes
__be64 tx_bytes
Definition: t4fw_interface.h:9219

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::fdisc_inv_sparm
__be16 fdisc_inv_sparm
Definition: t4fw_interface.h:9228

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::implicit_logo
__be16 implicit_logo
Definition: t4fw_interface.h:9226

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats::no_ssn
__be16 no_ssn
Definition: t4fw_interface.h:9231

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats
Definition: t4fw_interface.h:9177

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_offload_frames
__be64 tx_offload_frames
Definition: t4fw_interface.h:9186

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_err_frames
__be64 rx_err_frames
Definition: t4fw_interface.h:9193

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_mcast_bytes
__be64 rx_mcast_bytes
Definition: t4fw_interface.h:9189

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_bcast_bytes
__be64 tx_bcast_bytes
Definition: t4fw_interface.h:9178

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_mcast_frames
__be64 tx_mcast_frames
Definition: t4fw_interface.h:9181

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_ucast_frames
__be64 rx_ucast_frames
Definition: t4fw_interface.h:9192

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_bcast_frames
__be64 rx_bcast_frames
Definition: t4fw_interface.h:9188

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_offload_bytes
__be64 tx_offload_bytes
Definition: t4fw_interface.h:9185

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_mcast_bytes
__be64 tx_mcast_bytes
Definition: t4fw_interface.h:9180

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_bcast_frames
__be64 tx_bcast_frames
Definition: t4fw_interface.h:9179

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_ucast_bytes
__be64 rx_ucast_bytes
Definition: t4fw_interface.h:9191

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_ucast_bytes
__be64 tx_ucast_bytes
Definition: t4fw_interface.h:9182

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_ucast_frames
__be64 tx_ucast_frames
Definition: t4fw_interface.h:9183

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_mcast_frames
__be64 rx_mcast_frames
Definition: t4fw_interface.h:9190

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::rx_bcast_bytes
__be64 rx_bcast_bytes
Definition: t4fw_interface.h:9187

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats::tx_drop_frames
__be64 tx_drop_frames
Definition: t4fw_interface.h:9184

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats
Definition: t4fw_interface.h:9235

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::adap_abrt_rsp
__be32 adap_abrt_rsp
Definition: t4fw_interface.h:9242

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::ct_rjt
__u8 ct_rjt
Definition: t4fw_interface.h:9272

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::no_io_cls_req
__u8 no_io_cls_req
Definition: t4fw_interface.h:9257

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::host_ios_req
__be32 host_ios_req
Definition: t4fw_interface.h:9243

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::prlo_req_rcvd
__be16 prlo_req_rcvd
Definition: t4fw_interface.h:9263

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::adisc_req_rcvd
__be32 adisc_req_rcvd
Definition: t4fw_interface.h:9266

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::abort_req
__be32 abort_req
Definition: t4fw_interface.h:9253

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::rx_bytes
__be64 rx_bytes
Definition: t4fw_interface.h:9238

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::adisc_rjt_rcvd
__u8 adisc_rjt_rcvd
Definition: t4fw_interface.h:9270

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::bp_tmo
__u8 bp_tmo
Definition: t4fw_interface.h:9255

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::plogi_rjt_rcvd
__be16 plogi_rjt_rcvd
Definition: t4fw_interface.h:9264

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::host_cls_req
__be32 host_cls_req
Definition: t4fw_interface.h:9258

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::host_abrt_req
__be32 host_abrt_req
Definition: t4fw_interface.h:9240

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::bad_st_abrt_req
__u8 bad_st_abrt_req
Definition: t4fw_interface.h:9249

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::adap_auto_cls
__u8 adap_auto_cls
Definition: t4fw_interface.h:9256

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::abort_tmo
__u8 abort_tmo
Definition: t4fw_interface.h:9251

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::rx_data_fr_err
__be16 rx_data_fr_err
Definition: t4fw_interface.h:9248

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::plogi_req_rcvd
__be32 plogi_req_rcvd
Definition: t4fw_interface.h:9260

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::inval_bls_rcvd
__u8 inval_bls_rcvd
Definition: t4fw_interface.h:9273

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::prli_rjt_rcvd
__be16 prli_rjt_rcvd
Definition: t4fw_interface.h:9265

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::ssn_offl_ios
__be16 ssn_offl_ios
Definition: t4fw_interface.h:9244

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::prli_req_rcvd
__be32 prli_req_rcvd
Definition: t4fw_interface.h:9261

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::abort_tmo_2
__u8 abort_tmo_2
Definition: t4fw_interface.h:9252

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::scr_rjt
__u8 scr_rjt
Definition: t4fw_interface.h:9271

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::rx_data_ddp_err
__u8 rx_data_ddp_err
Definition: t4fw_interface.h:9246

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::ssn_not_rdy_ios
__be16 ssn_not_rdy_ios
Definition: t4fw_interface.h:9245

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::tx_bytes
__be64 tx_bytes
Definition: t4fw_interface.h:9236

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::unsol_els_rcvd
__be32 unsol_els_rcvd
Definition: t4fw_interface.h:9269

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::rscn_rcvd
__be32 rscn_rcvd
Definition: t4fw_interface.h:9267

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::rx_frames
__be64 rx_frames
Definition: t4fw_interface.h:9239

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::ddp_flt_set_err
__u8 ddp_flt_set_err
Definition: t4fw_interface.h:9247

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::no_io_abrt_req
__u8 no_io_abrt_req
Definition: t4fw_interface.h:9250

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::no_ppod_res_tmo
__u8 no_ppod_res_tmo
Definition: t4fw_interface.h:9254

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::rrq_req_rcvd
__be32 rrq_req_rcvd
Definition: t4fw_interface.h:9268

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::ba_rjt_rcvd
__be32 ba_rjt_rcvd
Definition: t4fw_interface.h:9274

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::unsol_cmd_rcvd
__be64 unsol_cmd_rcvd
Definition: t4fw_interface.h:9259

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::adap_auto_abrt
__be32 adap_auto_abrt
Definition: t4fw_interface.h:9241

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::logo_req_rcvd
__be16 logo_req_rcvd
Definition: t4fw_interface.h:9262

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats::tx_frames
__be64 tx_frames
Definition: t4fw_interface.h:9237

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl
Definition: t4fw_interface.h:9165

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::stat4
__be64 stat4
Definition: t4fw_interface.h:9174

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::port_valid_ix
__u8 port_valid_ix
Definition: t4fw_interface.h:9167

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::stat1
__be64 stat1
Definition: t4fw_interface.h:9171

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::stat3
__be64 stat3
Definition: t4fw_interface.h:9173

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::stat5
__be64 stat5
Definition: t4fw_interface.h:9175

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::r7
__be32 r7
Definition: t4fw_interface.h:9169

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::stat2
__be64 stat2
Definition: t4fw_interface.h:9172

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::stat0
__be64 stat0
Definition: t4fw_interface.h:9170

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::nstats_port
__u8 nstats_port
Definition: t4fw_interface.h:9166

fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl::r6
__be16 r6
Definition: t4fw_interface.h:9168

fw_fcoe_stats_cmd
Definition: t4fw_interface.h:9161

fw_fcoe_stats_cmd::free_to_len16
__be32 free_to_len16
Definition: t4fw_interface.h:9163

fw_fcoe_stats_cmd::op_to_flowid
__be32 op_to_flowid
Definition: t4fw_interface.h:9162

fw_fcoe_stats_cmd::u
union fw_fcoe_stats_cmd::fw_fcoe_stats u

fw_fcoe_vnp_cmd
Definition: t4fw_interface.h:9077

fw_fcoe_vnp_cmd::cmn_srv_parms
__u8 cmn_srv_parms[16]
Definition: t4fw_interface.h:9086

fw_fcoe_vnp_cmd::op_to_fcfi
__be32 op_to_fcfi
Definition: t4fw_interface.h:9078

fw_fcoe_vnp_cmd::clsp_word_0_1
__u8 clsp_word_0_1[8]
Definition: t4fw_interface.h:9087

fw_fcoe_vnp_cmd::vnport_wwpn
__u8 vnport_wwpn[8]
Definition: t4fw_interface.h:9085

fw_fcoe_vnp_cmd::vf_id
__be32 vf_id
Definition: t4fw_interface.h:9081

fw_fcoe_vnp_cmd::gen_wwn_to_vnpi
__be32 gen_wwn_to_vnpi
Definition: t4fw_interface.h:9080

fw_fcoe_vnp_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:9079

fw_fcoe_vnp_cmd::iqid
__be16 iqid
Definition: t4fw_interface.h:9082

fw_fcoe_vnp_cmd::vnport_mac
__u8 vnport_mac[6]
Definition: t4fw_interface.h:9083

fw_fcoe_vnp_cmd::vnport_wwnn
__u8 vnport_wwnn[8]
Definition: t4fw_interface.h:9084

fw_filter2_wr
Definition: t4fw_interface.h:354

fw_filter2_wr::ttyp
__u8 ttyp
Definition: t4fw_interface.h:368

fw_filter2_wr::natmode_to_ulp_type
__u8 natmode_to_ulp_type
Definition: t4fw_interface.h:386

fw_filter2_wr::lipm
__u8 lipm[16]
Definition: t4fw_interface.h:375

fw_filter2_wr::lip
__u8 lip[16]
Definition: t4fw_interface.h:374

fw_filter2_wr::newfport
__be16 newfport
Definition: t4fw_interface.h:388

fw_filter2_wr::ptclm
__u8 ptclm
Definition: t4fw_interface.h:367

fw_filter2_wr::filter_type_swapmac
__u8 filter_type_swapmac
Definition: t4fw_interface.h:385

fw_filter2_wr::fp
__be16 fp
Definition: t4fw_interface.h:380

fw_filter2_wr::r8
__be16 r8
Definition: t4fw_interface.h:384

fw_filter2_wr::fipm
__u8 fipm[16]
Definition: t4fw_interface.h:377

fw_filter2_wr::r9
__be32 r9
Definition: t4fw_interface.h:392

fw_filter2_wr::ttypm
__u8 ttypm
Definition: t4fw_interface.h:369

fw_filter2_wr::ptcl
__u8 ptcl
Definition: t4fw_interface.h:366

fw_filter2_wr::ivlan
__be16 ivlan
Definition: t4fw_interface.h:370

fw_filter2_wr::r10
__be64 r10
Definition: t4fw_interface.h:393

fw_filter2_wr::ivlanm
__be16 ivlanm
Definition: t4fw_interface.h:371

fw_filter2_wr::newfip
__u8 newfip[16]
Definition: t4fw_interface.h:390

fw_filter2_wr::r13
__be64 r13
Definition: t4fw_interface.h:396

fw_filter2_wr::ethtypem
__be16 ethtypem
Definition: t4fw_interface.h:361

fw_filter2_wr::maci_to_matchtypem
__be32 maci_to_matchtypem
Definition: t4fw_interface.h:365

fw_filter2_wr::ethtype
__be16 ethtype
Definition: t4fw_interface.h:360

fw_filter2_wr::natseqcheck
__be32 natseqcheck
Definition: t4fw_interface.h:391

fw_filter2_wr::frag_to_ovlan_vldm
__u8 frag_to_ovlan_vldm
Definition: t4fw_interface.h:362

fw_filter2_wr::r7
__be16 r7
Definition: t4fw_interface.h:382

fw_filter2_wr::r12
__be64 r12
Definition: t4fw_interface.h:395

fw_filter2_wr::sma
__u8 sma[6]
Definition: t4fw_interface.h:383

fw_filter2_wr::rx_chan_rx_rpl_iq
__be16 rx_chan_rx_rpl_iq
Definition: t4fw_interface.h:364

fw_filter2_wr::smac_sel
__u8 smac_sel
Definition: t4fw_interface.h:363

fw_filter2_wr::del_filter_to_l2tix
__be32 del_filter_to_l2tix
Definition: t4fw_interface.h:359

fw_filter2_wr::r11
__be64 r11
Definition: t4fw_interface.h:394

fw_filter2_wr::ovlanm
__be16 ovlanm
Definition: t4fw_interface.h:373

fw_filter2_wr::ovlan
__be16 ovlan
Definition: t4fw_interface.h:372

fw_filter2_wr::newlport
__be16 newlport
Definition: t4fw_interface.h:387

fw_filter2_wr::fip
__u8 fip[16]
Definition: t4fw_interface.h:376

fw_filter2_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:356

fw_filter2_wr::lp
__be16 lp
Definition: t4fw_interface.h:378

fw_filter2_wr::tid_to_iq
__be32 tid_to_iq
Definition: t4fw_interface.h:358

fw_filter2_wr::lpm
__be16 lpm
Definition: t4fw_interface.h:379

fw_filter2_wr::fpm
__be16 fpm
Definition: t4fw_interface.h:381

fw_filter2_wr::r3
__be64 r3
Definition: t4fw_interface.h:357

fw_filter2_wr::newlip
__u8 newlip[16]
Definition: t4fw_interface.h:389

fw_filter2_wr::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:355

fw_filter_wr
Definition: t4fw_interface.h:322

fw_filter_wr::lp
__be16 lp
Definition: t4fw_interface.h:346

fw_filter_wr::ivlan
__be16 ivlan
Definition: t4fw_interface.h:338

fw_filter_wr::fp
__be16 fp
Definition: t4fw_interface.h:348

fw_filter_wr::fip
__u8 fip[16]
Definition: t4fw_interface.h:344

fw_filter_wr::ttypm
__u8 ttypm
Definition: t4fw_interface.h:337

fw_filter_wr::maci_to_matchtypem
__be32 maci_to_matchtypem
Definition: t4fw_interface.h:333

fw_filter_wr::lipm
__u8 lipm[16]
Definition: t4fw_interface.h:343

fw_filter_wr::ptclm
__u8 ptclm
Definition: t4fw_interface.h:335

fw_filter_wr::fipm
__u8 fipm[16]
Definition: t4fw_interface.h:345

fw_filter_wr::tid_to_iq
__be32 tid_to_iq
Definition: t4fw_interface.h:326

fw_filter_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:324

fw_filter_wr::r7
__be16 r7
Definition: t4fw_interface.h:350

fw_filter_wr::ovlanm
__be16 ovlanm
Definition: t4fw_interface.h:341

fw_filter_wr::ttyp
__u8 ttyp
Definition: t4fw_interface.h:336

fw_filter_wr::frag_to_ovlan_vldm
__u8 frag_to_ovlan_vldm
Definition: t4fw_interface.h:330

fw_filter_wr::lpm
__be16 lpm
Definition: t4fw_interface.h:347

fw_filter_wr::rx_chan_rx_rpl_iq
__be16 rx_chan_rx_rpl_iq
Definition: t4fw_interface.h:332

fw_filter_wr::lip
__u8 lip[16]
Definition: t4fw_interface.h:342

fw_filter_wr::ethtype
__be16 ethtype
Definition: t4fw_interface.h:328

fw_filter_wr::sma
__u8 sma[6]
Definition: t4fw_interface.h:351

fw_filter_wr::fpm
__be16 fpm
Definition: t4fw_interface.h:349

fw_filter_wr::del_filter_to_l2tix
__be32 del_filter_to_l2tix
Definition: t4fw_interface.h:327

fw_filter_wr::ivlanm
__be16 ivlanm
Definition: t4fw_interface.h:339

fw_filter_wr::ovlan
__be16 ovlan
Definition: t4fw_interface.h:340

fw_filter_wr::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:323

fw_filter_wr::ethtypem
__be16 ethtypem
Definition: t4fw_interface.h:329

fw_filter_wr::smac_sel
__u8 smac_sel
Definition: t4fw_interface.h:331

fw_filter_wr::r3
__be64 r3
Definition: t4fw_interface.h:325

fw_filter_wr::ptcl
__u8 ptcl
Definition: t4fw_interface.h:334

fw_flowc_mnemval
Definition: t4fw_interface.h:1042

fw_flowc_mnemval::r4
__u8 r4[3]
Definition: t4fw_interface.h:1044

fw_flowc_mnemval::val
__be32 val
Definition: t4fw_interface.h:1045

fw_flowc_mnemval::mnemonic
__u8 mnemonic
Definition: t4fw_interface.h:1043

fw_flowc_wr
Definition: t4fw_interface.h:1048

fw_flowc_wr::mnemval
struct fw_flowc_mnemval mnemval[0]
Definition: t4fw_interface.h:1052

fw_flowc_wr::op_to_nparams
__be32 op_to_nparams
Definition: t4fw_interface.h:1049

fw_flowc_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:1050

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_chap
Definition: t4fw_interface.h:2862

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_chap::chap_id
__u8 chap_id[224]
Definition: t4fw_interface.h:2863

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_chap::chap_sec
__u8 chap_sec[128]
Definition: t4fw_interface.h:2864

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_vend_kv
Definition: t4fw_interface.h:2866

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_vend_kv::vend_val
__u8 vend_val[256]
Definition: t4fw_interface.h:2868

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_vend_kv::vend_key
__u8 vend_key[64]
Definition: t4fw_interface.h:2867

fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_chap_lens
Definition: t4fw_interface.h:2849

fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_chap_lens::sec_len
__u8 sec_len
Definition: t4fw_interface.h:2851

fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_chap_lens::id_len
__u8 id_len
Definition: t4fw_interface.h:2850

fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_vend_kv_lens
Definition: t4fw_interface.h:2853

fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_vend_kv_lens::key_len
__u8 key_len
Definition: t4fw_interface.h:2854

fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_vend_kv_lens::val_len
__u8 val_len
Definition: t4fw_interface.h:2855

fw_foiscsi_chap_wr
Definition: t4fw_interface.h:2843

fw_foiscsi_chap_wr::r3
__u8 r3[2]
Definition: t4fw_interface.h:2860

fw_foiscsi_chap_wr::u
union fw_foiscsi_chap_wr::fw_foiscsi_chap_vend u

fw_foiscsi_chap_wr::op_to_kv_flag
__be32 op_to_kv_flag
Definition: t4fw_interface.h:2844

fw_foiscsi_chap_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2846

fw_foiscsi_chap_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:2845

fw_foiscsi_chap_wr::status
__u8 status
Definition: t4fw_interface.h:2847

fw_foiscsi_chap_wr::node_id
__be16 node_id
Definition: t4fw_interface.h:2859

fw_foiscsi_chap_wr::lenu
union fw_foiscsi_chap_wr::fw_foiscsi_len lenu

fw_foiscsi_chap_wr::node_type
__u8 node_type
Definition: t4fw_interface.h:2858

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv4
Definition: t4fw_interface.h:2703

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv4::dst_addr
__be32 dst_addr
Definition: t4fw_interface.h:2704

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv4::src_addr
__be32 src_addr
Definition: t4fw_interface.h:2705

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv6
Definition: t4fw_interface.h:2699

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv6::dst_addr
__be64 dst_addr[2]
Definition: t4fw_interface.h:2700

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv6::src_addr
__be64 src_addr[2]
Definition: t4fw_interface.h:2701

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr
Definition: t4fw_interface.h:2692

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::max_rcv_dsl
__be32 max_rcv_dsl
Definition: t4fw_interface.h:2694

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::src_port
__be16 src_port
Definition: t4fw_interface.h:2697

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::hdigest_to_tcp_ws_en
__be32 hdigest_to_tcp_ws_en
Definition: t4fw_interface.h:2693

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::dst_port
__be16 dst_port
Definition: t4fw_interface.h:2696

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::ping_tmo
__be32 ping_tmo
Definition: t4fw_interface.h:2695

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::u
union fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr u

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr
Definition: t4fw_interface.h:2682

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::time2retain
__be16 time2retain
Definition: t4fw_interface.h:2687

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::sess_type_to_erl
__be32 sess_type_to_erl
Definition: t4fw_interface.h:2683

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::r1
__be32 r1
Definition: t4fw_interface.h:2690

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::time2wait
__be16 time2wait
Definition: t4fw_interface.h:2686

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::max_conn
__be16 max_conn
Definition: t4fw_interface.h:2684

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::max_burst
__be32 max_burst
Definition: t4fw_interface.h:2688

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::max_r2t
__be16 max_r2t
Definition: t4fw_interface.h:2685

fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr::first_burst
__be32 first_burst
Definition: t4fw_interface.h:2689

fw_foiscsi_ctrl_wr
Definition: t4fw_interface.h:2671

fw_foiscsi_ctrl_wr::io_state
__u8 io_state
Definition: t4fw_interface.h:2678

fw_foiscsi_ctrl_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:2673

fw_foiscsi_ctrl_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2674

fw_foiscsi_ctrl_wr::tgt_name_len
__u8 tgt_name_len
Definition: t4fw_interface.h:2709

fw_foiscsi_ctrl_wr::sess_attr
struct fw_foiscsi_ctrl_wr::fw_foiscsi_sess_attr sess_attr

fw_foiscsi_ctrl_wr::op_to_no_fin
__be32 op_to_no_fin
Definition: t4fw_interface.h:2672

fw_foiscsi_ctrl_wr::subop
__u8 subop
Definition: t4fw_interface.h:2675

fw_foiscsi_ctrl_wr::status
__u8 status
Definition: t4fw_interface.h:2676

fw_foiscsi_ctrl_wr::tgt_name
__u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]
Definition: t4fw_interface.h:2711

fw_foiscsi_ctrl_wr::node_id
__be32 node_id
Definition: t4fw_interface.h:2679

fw_foiscsi_ctrl_wr::ctrl_id
__be32 ctrl_id
Definition: t4fw_interface.h:2680

fw_foiscsi_ctrl_wr::ctrl_state
__u8 ctrl_state
Definition: t4fw_interface.h:2677

fw_foiscsi_ctrl_wr::conn_attr
struct fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr conn_attr

fw_foiscsi_ctrl_wr::r3
__u8 r3[7]
Definition: t4fw_interface.h:2710

fw_foiscsi_ctrl_wr::io_id
__be32 io_id
Definition: t4fw_interface.h:2681

fw_foiscsi_node_wr
Definition: t4fw_interface.h:2609

fw_foiscsi_node_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:2610

fw_foiscsi_node_wr::subop
__u8 subop
Definition: t4fw_interface.h:2613

fw_foiscsi_node_wr::login_retry
__be16 login_retry
Definition: t4fw_interface.h:2619

fw_foiscsi_node_wr::no_sess_recv_to_len16
__be32 no_sess_recv_to_len16
Definition: t4fw_interface.h:2611

fw_foiscsi_node_wr::status
__u8 status
Definition: t4fw_interface.h:2614

fw_foiscsi_node_wr::isid_tval_to_isid_cval
__be32 isid_tval_to_isid_cval
Definition: t4fw_interface.h:2624

fw_foiscsi_node_wr::node_flowid
__be32 node_flowid
Definition: t4fw_interface.h:2617

fw_foiscsi_node_wr::nodeid
__be16 nodeid
Definition: t4fw_interface.h:2618

fw_foiscsi_node_wr::retry_timeout
__be16 retry_timeout
Definition: t4fw_interface.h:2620

fw_foiscsi_node_wr::iqn_len
__u8 iqn_len
Definition: t4fw_interface.h:2616

fw_foiscsi_node_wr::r3
__be16 r3
Definition: t4fw_interface.h:2621

fw_foiscsi_node_wr::alias
__u8 alias[224]
Definition: t4fw_interface.h:2623

fw_foiscsi_node_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2612

fw_foiscsi_node_wr::alias_len
__u8 alias_len
Definition: t4fw_interface.h:2615

fw_foiscsi_node_wr::iqn
__u8 iqn[224]
Definition: t4fw_interface.h:2622

fw_frag_wr
Definition: t4fw_interface.h:239

fw_frag_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:241

fw_frag_wr::op_to_fragoff16
__be32 op_to_fragoff16
Definition: t4fw_interface.h:240

fw_frag_wr::r4
__be64 r4
Definition: t4fw_interface.h:242

fw_hdr
Definition: t4fw_interface.h:9945

fw_hdr::intfver_ofld
__u8 intfver_ofld
Definition: t4fw_interface.h:9953

fw_hdr::chip
__u8 chip
Definition: t4fw_interface.h:9947

fw_hdr::intfver_ri
__u8 intfver_ri
Definition: t4fw_interface.h:9954

fw_hdr::fw_ver
__be32 fw_ver
Definition: t4fw_interface.h:9949

fw_hdr::flags
__be32 flags
Definition: t4fw_interface.h:9962

fw_hdr::reserved3
__u32 reserved3
Definition: t4fw_interface.h:9960

fw_hdr::dsign_len
__u8 dsign_len
Definition: t4fw_interface.h:9965

fw_hdr::intfver_fcoepdu
__u8 intfver_fcoepdu
Definition: t4fw_interface.h:9957

fw_hdr::intfver_iscsipdu
__u8 intfver_iscsipdu
Definition: t4fw_interface.h:9955

fw_hdr::reserved2
__u32 reserved2
Definition: t4fw_interface.h:9959

fw_hdr::intfver_vnic
__u8 intfver_vnic
Definition: t4fw_interface.h:9952

fw_hdr::intfver_nic
__u8 intfver_nic
Definition: t4fw_interface.h:9951

fw_hdr::dsign
__u8 dsign[72]
Definition: t4fw_interface.h:9966

fw_hdr::intfver_iscsi
__u8 intfver_iscsi
Definition: t4fw_interface.h:9956

fw_hdr::reserved7
__u8 reserved7[3]
Definition: t4fw_interface.h:9964

fw_hdr::magic
__be32 magic
Definition: t4fw_interface.h:9961

fw_hdr::intfver_fcoe
__u8 intfver_fcoe
Definition: t4fw_interface.h:9958

fw_hdr::len512
__be16 len512
Definition: t4fw_interface.h:9948

fw_hdr::tp_microcode_ver
__be32 tp_microcode_ver
Definition: t4fw_interface.h:9950

fw_hdr::ver
__u8 ver
Definition: t4fw_interface.h:9946

fw_hdr::reserved6
__be32 reserved6[4]
Definition: t4fw_interface.h:9963

fw_hello_cmd
Definition: t4fw_interface.h:4514

fw_hello_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:4515

fw_hello_cmd::fwrev
__be32 fwrev
Definition: t4fw_interface.h:4518

fw_hello_cmd::err_to_clearinit
__be32 err_to_clearinit
Definition: t4fw_interface.h:4517

fw_hello_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:4516

fw_hma_cmd
Definition: t4fw_interface.h:9736

fw_hma_cmd::r6
__be32 r6
Definition: t4fw_interface.h:9742

fw_hma_cmd::addr_size_pkd
__be32 addr_size_pkd
Definition: t4fw_interface.h:9741

fw_hma_cmd::phy_address
__be64 phy_address[5]
Definition: t4fw_interface.h:9743

fw_hma_cmd::naddr_size
__be32 naddr_size
Definition: t4fw_interface.h:9740

fw_hma_cmd::mode_to_pcie_params
__be32 mode_to_pcie_params
Definition: t4fw_interface.h:9739

fw_hma_cmd::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:9737

fw_hma_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:9738

fw_ifconf_dhcp_info
Definition: t4fw_interface.h:10089

fw_ifconf_dhcp_info::op
__u8 op
Definition: t4fw_interface.h:10095

fw_ifconf_dhcp_info::data
__u8 data[270]
Definition: t4fw_interface.h:10097

fw_ifconf_dhcp_info::mask
__be32 mask
Definition: t4fw_interface.h:10091

fw_ifconf_dhcp_info::vlanid
__be16 vlanid
Definition: t4fw_interface.h:10092

fw_ifconf_dhcp_info::mtu
__be16 mtu
Definition: t4fw_interface.h:10093

fw_ifconf_dhcp_info::gw
__be32 gw
Definition: t4fw_interface.h:10094

fw_ifconf_dhcp_info::addr
__be32 addr
Definition: t4fw_interface.h:10090

fw_ifconf_dhcp_info::len
__u8 len
Definition: t4fw_interface.h:10096

fw_ifconf_ping_info
Definition: t4fw_interface.h:10100

fw_ifconf_ping_info::ping_pldsize
__be16 ping_pldsize
Definition: t4fw_interface.h:10101

fw_initialize_cmd
Definition: t4fw_interface.h:4587

fw_initialize_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:4588

fw_initialize_cmd::r3
__be64 r3
Definition: t4fw_interface.h:4590

fw_initialize_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:4589

fw_iq_cmd
Definition: t4fw_interface.h:5213

fw_iq_cmd::fl1addr
__be64 fl1addr
Definition: t4fw_interface.h:5231

fw_iq_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:5215

fw_iq_cmd::fl0addr
__be64 fl0addr
Definition: t4fw_interface.h:5227

fw_iq_cmd::fl0id
__be16 fl0id
Definition: t4fw_interface.h:5218

fw_iq_cmd::iqid
__be16 iqid
Definition: t4fw_interface.h:5217

fw_iq_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5214

fw_iq_cmd::iqns_to_fl0congen
__be32 iqns_to_fl0congen
Definition: t4fw_interface.h:5224

fw_iq_cmd::iqsize
__be16 iqsize
Definition: t4fw_interface.h:5222

fw_iq_cmd::fl1size
__be16 fl1size
Definition: t4fw_interface.h:5230

fw_iq_cmd::fl1cngchmap_to_fl1congen
__be32 fl1cngchmap_to_fl1congen
Definition: t4fw_interface.h:5228

fw_iq_cmd::iqaddr
__be64 iqaddr
Definition: t4fw_interface.h:5223

fw_iq_cmd::fl0size
__be16 fl0size
Definition: t4fw_interface.h:5226

fw_iq_cmd::iqdroprss_to_iqesize
__be16 iqdroprss_to_iqesize
Definition: t4fw_interface.h:5221

fw_iq_cmd::fl0dcaen_to_fl0cidxfthresh
__be16 fl0dcaen_to_fl0cidxfthresh
Definition: t4fw_interface.h:5225

fw_iq_cmd::physiqid
__be16 physiqid
Definition: t4fw_interface.h:5216

fw_iq_cmd::type_to_iqandstindex
__be32 type_to_iqandstindex
Definition: t4fw_interface.h:5220

fw_iq_cmd::fl1dcaen_to_fl1cidxfthresh
__be16 fl1dcaen_to_fl1cidxfthresh
Definition: t4fw_interface.h:5229

fw_iq_cmd::fl1id
__be16 fl1id
Definition: t4fw_interface.h:5219

fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr::fw_tcp_conn_attr_in_addr6
Definition: t4fw_interface.h:3147

fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr::fw_tcp_conn_attr_in_addr6::addr
__be64 addr[2]
Definition: t4fw_interface.h:3148

fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr::fw_tcp_conn_attr_in_addr
Definition: t4fw_interface.h:3142

fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr::fw_tcp_conn_attr_in_addr::r8
__be32 r8[2]
Definition: t4fw_interface.h:3145

fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr::fw_tcp_conn_attr_in_addr::addr
__be32 addr
Definition: t4fw_interface.h:3143

fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr::fw_tcp_conn_attr_in_addr::r7
__be32 r7
Definition: t4fw_interface.h:3144

fw_isns_wr::fw_tcp_conn_attr
Definition: t4fw_interface.h:3136

fw_isns_wr::fw_tcp_conn_attr::in_type
__u8 in_type
Definition: t4fw_interface.h:3139

fw_isns_wr::fw_tcp_conn_attr::r6
__u8 r6
Definition: t4fw_interface.h:3140

fw_isns_wr::fw_tcp_conn_attr::u
union fw_isns_wr::fw_tcp_conn_attr::fw_tcp_conn_attr_addr u

fw_isns_wr::fw_tcp_conn_attr::in_tid
__be32 in_tid
Definition: t4fw_interface.h:3137

fw_isns_wr::fw_tcp_conn_attr::in_port
__be16 in_port
Definition: t4fw_interface.h:3138

fw_isns_wr
Definition: t4fw_interface.h:3127

fw_isns_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3129

fw_isns_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:3128

fw_isns_wr::r4
__be16 r4
Definition: t4fw_interface.h:3135

fw_isns_wr::subop
__u8 subop
Definition: t4fw_interface.h:3131

fw_isns_wr::conn_attr
struct fw_isns_wr::fw_tcp_conn_attr conn_attr

fw_isns_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:3130

fw_isns_wr::iq_id
__be16 iq_id
Definition: t4fw_interface.h:3133

fw_isns_wr::vlanid
__be16 vlanid
Definition: t4fw_interface.h:3134

fw_isns_wr::status
__u8 status
Definition: t4fw_interface.h:3132

fw_isns_xmit_wr
Definition: t4fw_interface.h:3160

fw_isns_xmit_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3162

fw_isns_xmit_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:3163

fw_isns_xmit_wr::r5
__be64 r5
Definition: t4fw_interface.h:3167

fw_isns_xmit_wr::xfer_len
__be32 xfer_len
Definition: t4fw_interface.h:3166

fw_isns_xmit_wr::r4
__be16 r4
Definition: t4fw_interface.h:3165

fw_isns_xmit_wr::iq_id
__be16 iq_id
Definition: t4fw_interface.h:3164

fw_isns_xmit_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:3161

fw_ldst_cmd::fw_ldst::fw_ldst_addrval
Definition: t4fw_interface.h:4286

fw_ldst_cmd::fw_ldst::fw_ldst_addrval::val
__be32 val
Definition: t4fw_interface.h:4288

fw_ldst_cmd::fw_ldst::fw_ldst_addrval::addr
__be32 addr
Definition: t4fw_interface.h:4287

fw_ldst_cmd::fw_ldst::fw_ldst_cim_rq
Definition: t4fw_interface.h:4308

fw_ldst_cmd::fw_ldst::fw_ldst_cim_rq::req_first64
__u8 req_first64[8]
Definition: t4fw_interface.h:4309

fw_ldst_cmd::fw_ldst::fw_ldst_cim_rq::r3
__be32 r3[2]
Definition: t4fw_interface.h:4313

fw_ldst_cmd::fw_ldst::fw_ldst_cim_rq::resp_second64
__u8 resp_second64[8]
Definition: t4fw_interface.h:4312

fw_ldst_cmd::fw_ldst::fw_ldst_cim_rq::resp_first64
__u8 resp_first64[8]
Definition: t4fw_interface.h:4311

fw_ldst_cmd::fw_ldst::fw_ldst_cim_rq::req_second64
__u8 req_second64[8]
Definition: t4fw_interface.h:4310

fw_ldst_cmd::fw_ldst::fw_ldst_func
Definition: t4fw_interface.h:4337

fw_ldst_cmd::fw_ldst::fw_ldst_func::offset
__be32 offset
Definition: t4fw_interface.h:4341

fw_ldst_cmd::fw_ldst::fw_ldst_func::access_ctl
__u8 access_ctl
Definition: t4fw_interface.h:4338

fw_ldst_cmd::fw_ldst::fw_ldst_func::ctl_id
__be16 ctl_id
Definition: t4fw_interface.h:4340

fw_ldst_cmd::fw_ldst::fw_ldst_func::data0
__be64 data0
Definition: t4fw_interface.h:4342

fw_ldst_cmd::fw_ldst::fw_ldst_func::mod_index
__u8 mod_index
Definition: t4fw_interface.h:4339

fw_ldst_cmd::fw_ldst::fw_ldst_func::data1
__be64 data1
Definition: t4fw_interface.h:4343

fw_ldst_cmd::fw_ldst::fw_ldst_i2c_deprecated
Definition: t4fw_interface.h:4355

fw_ldst_cmd::fw_ldst::fw_ldst_i2c_deprecated::pid_pkd
__u8 pid_pkd
Definition: t4fw_interface.h:4356

fw_ldst_cmd::fw_ldst::fw_ldst_i2c_deprecated::base
__u8 base
Definition: t4fw_interface.h:4357

fw_ldst_cmd::fw_ldst::fw_ldst_i2c_deprecated::r9
__be32 r9
Definition: t4fw_interface.h:4360

fw_ldst_cmd::fw_ldst::fw_ldst_i2c_deprecated::boffset
__u8 boffset
Definition: t4fw_interface.h:4358

fw_ldst_cmd::fw_ldst::fw_ldst_i2c_deprecated::data
__u8 data
Definition: t4fw_interface.h:4359

fw_ldst_cmd::fw_ldst::fw_ldst_i2c
Definition: t4fw_interface.h:4362

fw_ldst_cmd::fw_ldst::fw_ldst_i2c::r9
__be32 r9
Definition: t4fw_interface.h:4367

fw_ldst_cmd::fw_ldst::fw_ldst_i2c::boffset
__u8 boffset
Definition: t4fw_interface.h:4365

fw_ldst_cmd::fw_ldst::fw_ldst_i2c::blen
__u8 blen
Definition: t4fw_interface.h:4366

fw_ldst_cmd::fw_ldst::fw_ldst_i2c::pid
__u8 pid
Definition: t4fw_interface.h:4363

fw_ldst_cmd::fw_ldst::fw_ldst_i2c::data
__u8 data[48]
Definition: t4fw_interface.h:4368

fw_ldst_cmd::fw_ldst::fw_ldst_i2c::did
__u8 did
Definition: t4fw_interface.h:4364

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt
Definition: t4fw_interface.h:4290

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data6
__be32 ctxt_data6
Definition: t4fw_interface.h:4294

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data7
__be32 ctxt_data7
Definition: t4fw_interface.h:4293

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data3
__be32 ctxt_data3
Definition: t4fw_interface.h:4297

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data1
__be32 ctxt_data1
Definition: t4fw_interface.h:4299

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data5
__be32 ctxt_data5
Definition: t4fw_interface.h:4295

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data0
__be32 ctxt_data0
Definition: t4fw_interface.h:4300

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data2
__be32 ctxt_data2
Definition: t4fw_interface.h:4298

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::physid
__be32 physid
Definition: t4fw_interface.h:4291

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::ctxt_data4
__be32 ctxt_data4
Definition: t4fw_interface.h:4296

fw_ldst_cmd::fw_ldst::fw_ldst_idctxt::msg_ctxtflush
__be32 msg_ctxtflush
Definition: t4fw_interface.h:4292

fw_ldst_cmd::fw_ldst::fw_ldst_le
Definition: t4fw_interface.h:4370

fw_ldst_cmd::fw_ldst::fw_ldst_le::index
__be32 index
Definition: t4fw_interface.h:4371

fw_ldst_cmd::fw_ldst::fw_ldst_le::r11
__u8 r11[7]
Definition: t4fw_interface.h:4374

fw_ldst_cmd::fw_ldst::fw_ldst_le::val
__u8 val[33]
Definition: t4fw_interface.h:4373

fw_ldst_cmd::fw_ldst::fw_ldst_le::r9
__be32 r9
Definition: t4fw_interface.h:4372

fw_ldst_cmd::fw_ldst::fw_ldst_mdio
Definition: t4fw_interface.h:4302

fw_ldst_cmd::fw_ldst::fw_ldst_mdio::paddr_mmd
__be16 paddr_mmd
Definition: t4fw_interface.h:4303

fw_ldst_cmd::fw_ldst::fw_ldst_mdio::rval
__be16 rval
Definition: t4fw_interface.h:4306

fw_ldst_cmd::fw_ldst::fw_ldst_mdio::raddr
__be16 raddr
Definition: t4fw_interface.h:4304

fw_ldst_cmd::fw_ldst::fw_ldst_mdio::vctl
__be16 vctl
Definition: t4fw_interface.h:4305

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb
Definition: t4fw_interface.h:4328

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb::r3
__be32 r3[2]
Definition: t4fw_interface.h:4331

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb::vlan
__be16 vlan[16]
Definition: t4fw_interface.h:4334

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb::atrb
__be32 atrb
Definition: t4fw_interface.h:4333

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb::r2
__be16 r2[3]
Definition: t4fw_interface.h:4330

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb::fid_mpsid
__be16 fid_mpsid
Definition: t4fw_interface.h:4329

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_atrb::r4
__be32 r4
Definition: t4fw_interface.h:4332

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc
Definition: t4fw_interface.h:4316

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc223_192
__be32 rplc223_192
Definition: t4fw_interface.h:4320

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplcpf_pkd
__be16 rplcpf_pkd
Definition: t4fw_interface.h:4318

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc127_96
__be32 rplc127_96
Definition: t4fw_interface.h:4323

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc63_32
__be32 rplc63_32
Definition: t4fw_interface.h:4325

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc95_64
__be32 rplc95_64
Definition: t4fw_interface.h:4324

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc255_224
__be32 rplc255_224
Definition: t4fw_interface.h:4319

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::fid_idx
__be16 fid_idx
Definition: t4fw_interface.h:4317

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc159_128
__be32 rplc159_128
Definition: t4fw_interface.h:4322

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc191_160
__be32 rplc191_160
Definition: t4fw_interface.h:4321

fw_ldst_cmd::fw_ldst::fw_ldst_mps::fw_ldst_mps_rplc::rplc31_0
__be32 rplc31_0
Definition: t4fw_interface.h:4326

fw_ldst_cmd::fw_ldst::fw_ldst_pcie
Definition: t4fw_interface.h:4345

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::data
__be32 data[12]
Definition: t4fw_interface.h:4353

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::select_naccess
__u8 select_naccess
Definition: t4fw_interface.h:4350

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::bnum
__u8 bnum
Definition: t4fw_interface.h:4347

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::pcie_fn
__u8 pcie_fn
Definition: t4fw_interface.h:4351

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::ctrl_to_fn
__u8 ctrl_to_fn
Definition: t4fw_interface.h:4346

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::nset_pkd
__be16 nset_pkd
Definition: t4fw_interface.h:4352

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::r
__u8 r
Definition: t4fw_interface.h:4348

fw_ldst_cmd::fw_ldst::fw_ldst_pcie::ext_r
__u8 ext_r
Definition: t4fw_interface.h:4349

fw_ldst_cmd
Definition: t4fw_interface.h:4282

fw_ldst_cmd::u
union fw_ldst_cmd::fw_ldst u

fw_ldst_cmd::op_to_addrspace
__be32 op_to_addrspace
Definition: t4fw_interface.h:4283

fw_ldst_cmd::cycles_to_len16
__be32 cycles_to_len16
Definition: t4fw_interface.h:4284

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv4
Definition: t4fw_interface.h:899

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv4::r2
__be64 r2
Definition: t4fw_interface.h:904

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv4::r0
__be64 r0
Definition: t4fw_interface.h:902

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv4::pip
__be32 pip
Definition: t4fw_interface.h:900

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv4::lip
__be32 lip
Definition: t4fw_interface.h:901

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv4::r1
__be64 r1
Definition: t4fw_interface.h:903

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv6
Definition: t4fw_interface.h:906

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv6::pip_lo
__be64 pip_lo
Definition: t4fw_interface.h:908

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv6::lip_hi
__be64 lip_hi
Definition: t4fw_interface.h:909

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv6::pip_hi
__be64 pip_hi
Definition: t4fw_interface.h:907

fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip::fw_ofld_connection_le_ipv6::lip_lo
__be64 lip_lo
Definition: t4fw_interface.h:910

fw_ofld_connection_wr::fw_ofld_connection_le
Definition: t4fw_interface.h:892

fw_ofld_connection_wr::fw_ofld_connection_le::u
union fw_ofld_connection_wr::fw_ofld_connection_le::fw_ofld_connection_leip u

fw_ofld_connection_wr::fw_ofld_connection_le::lport
__be16 lport
Definition: t4fw_interface.h:896

fw_ofld_connection_wr::fw_ofld_connection_le::filter
__be32 filter
Definition: t4fw_interface.h:894

fw_ofld_connection_wr::fw_ofld_connection_le::pport
__be16 pport
Definition: t4fw_interface.h:897

fw_ofld_connection_wr::fw_ofld_connection_le::r1
__be32 r1
Definition: t4fw_interface.h:895

fw_ofld_connection_wr::fw_ofld_connection_le::version_cpl
__be32 version_cpl
Definition: t4fw_interface.h:893

fw_ofld_connection_wr::fw_ofld_connection_tcb
Definition: t4fw_interface.h:914

fw_ofld_connection_wr::fw_ofld_connection_tcb::r2
__be64 r2
Definition: t4fw_interface.h:923

fw_ofld_connection_wr::fw_ofld_connection_tcb::t_state_to_astid
__be32 t_state_to_astid
Definition: t4fw_interface.h:915

fw_ofld_connection_wr::fw_ofld_connection_tcb::tx_max
__be32 tx_max
Definition: t4fw_interface.h:919

fw_ofld_connection_wr::fw_ofld_connection_tcb::r1
__be32 r1
Definition: t4fw_interface.h:922

fw_ofld_connection_wr::fw_ofld_connection_tcb::rcv_adv
__be16 rcv_adv
Definition: t4fw_interface.h:917

fw_ofld_connection_wr::fw_ofld_connection_tcb::opt0
__be64 opt0
Definition: t4fw_interface.h:920

fw_ofld_connection_wr::fw_ofld_connection_tcb::r3
__be64 r3
Definition: t4fw_interface.h:924

fw_ofld_connection_wr::fw_ofld_connection_tcb::cplrxdataack_cplpassacceptrpl
__be16 cplrxdataack_cplpassacceptrpl
Definition: t4fw_interface.h:916

fw_ofld_connection_wr::fw_ofld_connection_tcb::rcv_nxt
__be32 rcv_nxt
Definition: t4fw_interface.h:918

fw_ofld_connection_wr::fw_ofld_connection_tcb::opt2
__be32 opt2
Definition: t4fw_interface.h:921

fw_ofld_connection_wr
Definition: t4fw_interface.h:886

fw_ofld_connection_wr::r2
__be64 r2
Definition: t4fw_interface.h:890

fw_ofld_connection_wr::tcb
struct fw_ofld_connection_wr::fw_ofld_connection_tcb tcb

fw_ofld_connection_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:889

fw_ofld_connection_wr::le
struct fw_ofld_connection_wr::fw_ofld_connection_le le

fw_ofld_connection_wr::r3
__be64 r3
Definition: t4fw_interface.h:891

fw_ofld_connection_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:888

fw_ofld_connection_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:887

fw_ofld_tx_data_wr
Definition: t4fw_interface.h:1062

fw_ofld_tx_data_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:1063

fw_ofld_tx_data_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:1064

fw_ofld_tx_data_wr::plen
__be32 plen
Definition: t4fw_interface.h:1065

fw_ofld_tx_data_wr::lsodisable_to_flags
__be32 lsodisable_to_flags
Definition: t4fw_interface.h:1066

fw_params_cmd::fw_params_param
Definition: t4fw_interface.h:5081

fw_params_cmd::fw_params_param::val
__be32 val
Definition: t4fw_interface.h:5083

fw_params_cmd::fw_params_param::mnem
__be32 mnem
Definition: t4fw_interface.h:5082

fw_params_cmd
Definition: t4fw_interface.h:5078

fw_params_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:5080

fw_params_cmd::param
struct fw_params_cmd::fw_params_param param[7]

fw_params_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5079

fw_pfvf_cmd
Definition: t4fw_interface.h:5099

fw_pfvf_cmd::r_caps_to_nethctrl
__be32 r_caps_to_nethctrl
Definition: t4fw_interface.h:5105

fw_pfvf_cmd::r4
__be32 r4
Definition: t4fw_interface.h:5108

fw_pfvf_cmd::niqflint_niq
__be32 niqflint_niq
Definition: t4fw_interface.h:5102

fw_pfvf_cmd::tc_to_nexactf
__be32 tc_to_nexactf
Definition: t4fw_interface.h:5104

fw_pfvf_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:5100

fw_pfvf_cmd::nricq
__be16 nricq
Definition: t4fw_interface.h:5106

fw_pfvf_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:5101

fw_pfvf_cmd::nriqp
__be16 nriqp
Definition: t4fw_interface.h:5107

fw_pfvf_cmd::type_to_neq
__be32 type_to_neq
Definition: t4fw_interface.h:5103

fw_pi_error
Definition: t4fw_interface.h:3816

fw_pi_error::ref_tag
__be32 ref_tag
Definition: t4fw_interface.h:3821

fw_pi_error::r2
__be16 r2
Definition: t4fw_interface.h:3819

fw_pi_error::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3818

fw_pi_error::err_type_pkd
__be32 err_type_pkd
Definition: t4fw_interface.h:3817

fw_pi_error::app_tag
__be16 app_tag
Definition: t4fw_interface.h:3820

fw_pi_error::pisc
__be32 pisc[4]
Definition: t4fw_interface.h:3822

fw_pofcoe_tcb_wr
Definition: t4fw_interface.h:3676

fw_pofcoe_tcb_wr::xfer_len
__be32 xfer_len
Definition: t4fw_interface.h:3680

fw_pofcoe_tcb_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:3677

fw_pofcoe_tcb_wr::r6
__be16 r6
Definition: t4fw_interface.h:3688

fw_pofcoe_tcb_wr::vlan_id
__be16 vlan_id
Definition: t4fw_interface.h:3683

fw_pofcoe_tcb_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3684

fw_pofcoe_tcb_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3689

fw_pofcoe_tcb_wr::x_id
__be16 x_id
Definition: t4fw_interface.h:3682

fw_pofcoe_tcb_wr::d_id
__be32 d_id
Definition: t4fw_interface.h:3686

fw_pofcoe_tcb_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:3678

fw_pofcoe_tcb_wr::r4
__be32 r4
Definition: t4fw_interface.h:3679

fw_pofcoe_tcb_wr::s_id
__be32 s_id
Definition: t4fw_interface.h:3685

fw_pofcoe_tcb_wr::tid_to_port
__be32 tid_to_port
Definition: t4fw_interface.h:3681

fw_pofcoe_tcb_wr::tag
__be32 tag
Definition: t4fw_interface.h:3687

fw_pofcoe_ulptx_wr
Definition: t4fw_interface.h:3718

fw_pofcoe_ulptx_wr::equiq_to_len16
__be32 equiq_to_len16
Definition: t4fw_interface.h:3720

fw_pofcoe_ulptx_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:3721

fw_pofcoe_ulptx_wr::op_pkd
__be32 op_pkd
Definition: t4fw_interface.h:3719

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority
Definition: t4fw_interface.h:7452

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::sel_field
__u8 sel_field
Definition: t4fw_interface.h:7458

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::protocolid
__be16 protocolid
Definition: t4fw_interface.h:7459

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::r10_lo
__u8 r10_lo
Definition: t4fw_interface.h:7455

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::idx
__u8 idx
Definition: t4fw_interface.h:7456

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::r12
__be64 r12
Definition: t4fw_interface.h:7460

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::user_prio_map
__u8 user_prio_map
Definition: t4fw_interface.h:7457

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::apply_pkd
__u8 apply_pkd
Definition: t4fw_interface.h:7454

fw_port_cmd::fw_port::fw_port_dcb::fw_port_app_priority::type
__u8 type
Definition: t4fw_interface.h:7453

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_control
Definition: t4fw_interface.h:7462

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_control::all_syncd_pkd
__u8 all_syncd_pkd
Definition: t4fw_interface.h:7464

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_control::r12
__be64 r12
Definition: t4fw_interface.h:7467

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_control::dcb_version_to_app_state
__be16 dcb_version_to_app_state
Definition: t4fw_interface.h:7465

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_control::r11
__be32 r11
Definition: t4fw_interface.h:7466

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_control::type
__u8 type
Definition: t4fw_interface.h:7463

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc
Definition: t4fw_interface.h:7444

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc::type
__u8 type
Definition: t4fw_interface.h:7445

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc::max_pfc_tcs
__u8 max_pfc_tcs
Definition: t4fw_interface.h:7449

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc::pfcen
__u8 pfcen
Definition: t4fw_interface.h:7446

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc::r11
__be64 r11
Definition: t4fw_interface.h:7450

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc::apply_pkd
__u8 apply_pkd
Definition: t4fw_interface.h:7447

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pfc::r10_lo
__u8 r10_lo[4]
Definition: t4fw_interface.h:7448

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgid
Definition: t4fw_interface.h:7423

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgid::r11
__be64 r11
Definition: t4fw_interface.h:7428

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgid::apply_pkd
__u8 apply_pkd
Definition: t4fw_interface.h:7425

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgid::type
__u8 type
Definition: t4fw_interface.h:7424

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgid::pgid
__be32 pgid
Definition: t4fw_interface.h:7427

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgid::r10_lo
__u8 r10_lo[2]
Definition: t4fw_interface.h:7426

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate
Definition: t4fw_interface.h:7430

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate::pgrate
__u8 pgrate[8]
Definition: t4fw_interface.h:7435

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate::tsa
__u8 tsa[8]
Definition: t4fw_interface.h:7436

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate::apply_pkd
__u8 apply_pkd
Definition: t4fw_interface.h:7432

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate::type
__u8 type
Definition: t4fw_interface.h:7431

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate::r10_lo
__u8 r10_lo[5]
Definition: t4fw_interface.h:7433

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_pgrate::num_tcs_supported
__u8 num_tcs_supported
Definition: t4fw_interface.h:7434

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_priorate
Definition: t4fw_interface.h:7438

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_priorate::type
__u8 type
Definition: t4fw_interface.h:7439

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_priorate::r10_lo
__u8 r10_lo[6]
Definition: t4fw_interface.h:7441

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_priorate::strict_priorate
__u8 strict_priorate[8]
Definition: t4fw_interface.h:7442

fw_port_cmd::fw_port::fw_port_dcb::fw_port_dcb_priorate::apply_pkd
__u8 apply_pkd
Definition: t4fw_interface.h:7440

fw_port_cmd::fw_port::fw_port_diags
Definition: t4fw_interface.h:7417

fw_port_cmd::fw_port::fw_port_diags::diagop
__u8 diagop
Definition: t4fw_interface.h:7418

fw_port_cmd::fw_port::fw_port_diags::diagval
__be32 diagval
Definition: t4fw_interface.h:7420

fw_port_cmd::fw_port::fw_port_diags::r
__u8 r[3]
Definition: t4fw_interface.h:7419

fw_port_cmd::fw_port::fw_port_info32
Definition: t4fw_interface.h:7474

fw_port_cmd::fw_port::fw_port_info32::auxlinfo32_mtu32
__be32 auxlinfo32_mtu32
Definition: t4fw_interface.h:7476

fw_port_cmd::fw_port::fw_port_info32::lstatus32_to_cbllen32
__be32 lstatus32_to_cbllen32
Definition: t4fw_interface.h:7475

fw_port_cmd::fw_port::fw_port_info32::pcaps32
__be32 pcaps32
Definition: t4fw_interface.h:7478

fw_port_cmd::fw_port::fw_port_info32::lpacaps32
__be32 lpacaps32
Definition: t4fw_interface.h:7480

fw_port_cmd::fw_port::fw_port_info32::linkattr32
__be32 linkattr32
Definition: t4fw_interface.h:7477

fw_port_cmd::fw_port::fw_port_info32::acaps32
__be32 acaps32
Definition: t4fw_interface.h:7479

fw_port_cmd::fw_port::fw_port_info
Definition: t4fw_interface.h:7405

fw_port_cmd::fw_port::fw_port_info::auxlinfo
__u8 auxlinfo
Definition: t4fw_interface.h:7411

fw_port_cmd::fw_port::fw_port_info::pcap
__be16 pcap
Definition: t4fw_interface.h:7407

fw_port_cmd::fw_port::fw_port_info::mtu
__be16 mtu
Definition: t4fw_interface.h:7409

fw_port_cmd::fw_port::fw_port_info::lstatus_to_modtype
__be32 lstatus_to_modtype
Definition: t4fw_interface.h:7406

fw_port_cmd::fw_port::fw_port_info::lpacap
__be16 lpacap
Definition: t4fw_interface.h:7414

fw_port_cmd::fw_port::fw_port_info::cbllen
__u8 cbllen
Definition: t4fw_interface.h:7410

fw_port_cmd::fw_port::fw_port_info::acap
__be16 acap
Definition: t4fw_interface.h:7408

fw_port_cmd::fw_port::fw_port_info::r8_lo
__u8 r8_lo
Definition: t4fw_interface.h:7413

fw_port_cmd::fw_port::fw_port_info::dcbxdis_pkd
__u8 dcbxdis_pkd
Definition: t4fw_interface.h:7412

fw_port_cmd::fw_port::fw_port_info::r9
__be64 r9
Definition: t4fw_interface.h:7415

fw_port_cmd::fw_port::fw_port_l1cfg32
Definition: t4fw_interface.h:7470

fw_port_cmd::fw_port::fw_port_l1cfg32::r
__be32 r
Definition: t4fw_interface.h:7472

fw_port_cmd::fw_port::fw_port_l1cfg32::rcap32
__be32 rcap32
Definition: t4fw_interface.h:7471

fw_port_cmd::fw_port::fw_port_l1cfg
Definition: t4fw_interface.h:7386

fw_port_cmd::fw_port::fw_port_l1cfg::r
__be32 r
Definition: t4fw_interface.h:7388

fw_port_cmd::fw_port::fw_port_l1cfg::rcap
__be32 rcap
Definition: t4fw_interface.h:7387

fw_port_cmd::fw_port::fw_port_l2cfg
Definition: t4fw_interface.h:7390

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan3type
__be16 ovlan3type
Definition: t4fw_interface.h:7403

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan3mask
__be16 ovlan3mask
Definition: t4fw_interface.h:7402

fw_port_cmd::fw_port::fw_port_l2cfg::ctlbf
__u8 ctlbf
Definition: t4fw_interface.h:7391

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan0type
__be16 ovlan0type
Definition: t4fw_interface.h:7397

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan1mask
__be16 ovlan1mask
Definition: t4fw_interface.h:7398

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan3_to_ivlan0
__u8 ovlan3_to_ivlan0
Definition: t4fw_interface.h:7392

fw_port_cmd::fw_port::fw_port_l2cfg::ivlantype
__be16 ivlantype
Definition: t4fw_interface.h:7393

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan2type
__be16 ovlan2type
Definition: t4fw_interface.h:7401

fw_port_cmd::fw_port::fw_port_l2cfg::txipg_force_pinfo
__be16 txipg_force_pinfo
Definition: t4fw_interface.h:7394

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan0mask
__be16 ovlan0mask
Definition: t4fw_interface.h:7396

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan1type
__be16 ovlan1type
Definition: t4fw_interface.h:7399

fw_port_cmd::fw_port::fw_port_l2cfg::ovlan2mask
__be16 ovlan2mask
Definition: t4fw_interface.h:7400

fw_port_cmd::fw_port::fw_port_l2cfg::mtu
__be16 mtu
Definition: t4fw_interface.h:7395

fw_port_cmd
Definition: t4fw_interface.h:7382

fw_port_cmd::u
union fw_port_cmd::fw_port u

fw_port_cmd::action_to_len16
__be32 action_to_len16
Definition: t4fw_interface.h:7384

fw_port_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:7383

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all
Definition: t4fw_interface.h:8061

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_bcast
__be64 tx_bcast
Definition: t4fw_interface.h:8064

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_ucast
__be64 tx_ucast
Definition: t4fw_interface.h:8066

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_512b_1023b
__be64 tx_512b_1023b
Definition: t4fw_interface.h:8072

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_256b_511b
__be64 tx_256b_511b
Definition: t4fw_interface.h:8071

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_128b_255b
__be64 tx_128b_255b
Definition: t4fw_interface.h:8070

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_1024b_1518b
__be64 tx_1024b_1518b
Definition: t4fw_interface.h:8073

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_error
__be64 tx_error
Definition: t4fw_interface.h:8067

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_frames
__be64 tx_frames
Definition: t4fw_interface.h:8063

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_bytes
__be64 tx_bytes
Definition: t4fw_interface.h:8062

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::rx_lb_drop
__be64 rx_lb_drop
Definition: t4fw_interface.h:8075

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_1519b_max
__be64 tx_1519b_max
Definition: t4fw_interface.h:8074

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_mcast
__be64 tx_mcast
Definition: t4fw_interface.h:8065

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_64b
__be64 tx_64b
Definition: t4fw_interface.h:8068

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::tx_65b_127b
__be64 tx_65b_127b
Definition: t4fw_interface.h:8069

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_all::rx_lb_trunc
__be64 rx_lb_trunc
Definition: t4fw_interface.h:8076

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl
Definition: t4fw_interface.h:8049

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::r7
__be32 r7
Definition: t4fw_interface.h:8053

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::r6
__be16 r6
Definition: t4fw_interface.h:8052

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::stat0
__be64 stat0
Definition: t4fw_interface.h:8054

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::nstats_bg_bm
__u8 nstats_bg_bm
Definition: t4fw_interface.h:8050

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::stat1
__be64 stat1
Definition: t4fw_interface.h:8055

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::stat4
__be64 stat4
Definition: t4fw_interface.h:8058

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::stat2
__be64 stat2
Definition: t4fw_interface.h:8056

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::stat3
__be64 stat3
Definition: t4fw_interface.h:8057

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::stat5
__be64 stat5
Definition: t4fw_interface.h:8059

fw_port_lb_stats_cmd::fw_port_lb_stats::fw_port_lb_stats_ctl::ix_pkd
__u8 ix_pkd
Definition: t4fw_interface.h:8051

fw_port_lb_stats_cmd
Definition: t4fw_interface.h:8045

fw_port_lb_stats_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8047

fw_port_lb_stats_cmd::op_to_lbport
__be32 op_to_lbport
Definition: t4fw_interface.h:8046

fw_port_lb_stats_cmd::u
union fw_port_lb_stats_cmd::fw_port_lb_stats u

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all
Definition: t4fw_interface.h:7944

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_sym_error
__be64 rx_sym_error
Definition: t4fw_interface.h:7977

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_bg_drop
__be64 rx_bg_drop
Definition: t4fw_interface.h:7995

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ucast
__be64 rx_ucast
Definition: t4fw_interface.h:7972

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_mtu_crc_error
__be64 rx_mtu_crc_error
Definition: t4fw_interface.h:7974

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_64b
__be64 tx_64b
Definition: t4fw_interface.h:7951

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp2
__be64 tx_ppp2
Definition: t4fw_interface.h:7962

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_mtu_error
__be64 rx_mtu_error
Definition: t4fw_interface.h:7973

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_1024b_1518b
__be64 tx_1024b_1518b
Definition: t4fw_interface.h:7956

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_drop
__be64 tx_drop
Definition: t4fw_interface.h:7958

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp6
__be64 rx_ppp6
Definition: t4fw_interface.h:7992

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_1519b_max
__be64 rx_1519b_max
Definition: t4fw_interface.h:7984

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_bcast
__be64 rx_bcast
Definition: t4fw_interface.h:7970

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp4
__be64 rx_ppp4
Definition: t4fw_interface.h:7990

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_bcast
__be64 tx_bcast
Definition: t4fw_interface.h:7947

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_64b
__be64 rx_64b
Definition: t4fw_interface.h:7978

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_65b_127b
__be64 tx_65b_127b
Definition: t4fw_interface.h:7952

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_65b_127b
__be64 rx_65b_127b
Definition: t4fw_interface.h:7979

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_bytes
__be64 tx_bytes
Definition: t4fw_interface.h:7945

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp4
__be64 tx_ppp4
Definition: t4fw_interface.h:7964

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp3
__be64 rx_ppp3
Definition: t4fw_interface.h:7989

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp2
__be64 rx_ppp2
Definition: t4fw_interface.h:7988

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ucast
__be64 tx_ucast
Definition: t4fw_interface.h:7949

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_bg_trunc
__be64 rx_bg_trunc
Definition: t4fw_interface.h:7996

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_error
__be64 tx_error
Definition: t4fw_interface.h:7950

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_256b_511b
__be64 rx_256b_511b
Definition: t4fw_interface.h:7981

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_mcast
__be64 tx_mcast
Definition: t4fw_interface.h:7948

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_256b_511b
__be64 tx_256b_511b
Definition: t4fw_interface.h:7954

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_512b_1023b
__be64 tx_512b_1023b
Definition: t4fw_interface.h:7955

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_1519b_max
__be64 tx_1519b_max
Definition: t4fw_interface.h:7957

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_pause
__be64 rx_pause
Definition: t4fw_interface.h:7985

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_128b_255b
__be64 tx_128b_255b
Definition: t4fw_interface.h:7953

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_frames
__be64 rx_frames
Definition: t4fw_interface.h:7969

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp0
__be64 tx_ppp0
Definition: t4fw_interface.h:7960

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_mcast
__be64 rx_mcast
Definition: t4fw_interface.h:7971

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_512b_1023b
__be64 rx_512b_1023b
Definition: t4fw_interface.h:7982

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_128b_255b
__be64 rx_128b_255b
Definition: t4fw_interface.h:7980

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp3
__be64 tx_ppp3
Definition: t4fw_interface.h:7963

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp1
__be64 tx_ppp1
Definition: t4fw_interface.h:7961

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp5
__be64 tx_ppp5
Definition: t4fw_interface.h:7965

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp5
__be64 rx_ppp5
Definition: t4fw_interface.h:7991

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp6
__be64 tx_ppp6
Definition: t4fw_interface.h:7966

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp1
__be64 rx_ppp1
Definition: t4fw_interface.h:7987

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_1024b_1518b
__be64 rx_1024b_1518b
Definition: t4fw_interface.h:7983

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_len_error
__be64 rx_len_error
Definition: t4fw_interface.h:7976

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp0
__be64 rx_ppp0
Definition: t4fw_interface.h:7986

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_ppp7
__be64 tx_ppp7
Definition: t4fw_interface.h:7967

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_pause
__be64 tx_pause
Definition: t4fw_interface.h:7959

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_crc_error
__be64 rx_crc_error
Definition: t4fw_interface.h:7975

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_ppp7
__be64 rx_ppp7
Definition: t4fw_interface.h:7993

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::tx_frames
__be64 tx_frames
Definition: t4fw_interface.h:7946

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_bytes
__be64 rx_bytes
Definition: t4fw_interface.h:7968

fw_port_stats_cmd::fw_port_stats::fw_port_stats_all::rx_less_64b
__be64 rx_less_64b
Definition: t4fw_interface.h:7994

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl
Definition: t4fw_interface.h:7932

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::r6
__be16 r6
Definition: t4fw_interface.h:7935

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::nstats_bg_bm
__u8 nstats_bg_bm
Definition: t4fw_interface.h:7933

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::stat2
__be64 stat2
Definition: t4fw_interface.h:7939

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::stat0
__be64 stat0
Definition: t4fw_interface.h:7937

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::stat5
__be64 stat5
Definition: t4fw_interface.h:7942

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::tx_ix
__u8 tx_ix
Definition: t4fw_interface.h:7934

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::stat1
__be64 stat1
Definition: t4fw_interface.h:7938

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::stat4
__be64 stat4
Definition: t4fw_interface.h:7941

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::r7
__be32 r7
Definition: t4fw_interface.h:7936

fw_port_stats_cmd::fw_port_stats::fw_port_stats_ctl::stat3
__be64 stat3
Definition: t4fw_interface.h:7940

fw_port_stats_cmd
Definition: t4fw_interface.h:7928

fw_port_stats_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:7930

fw_port_stats_cmd::u
union fw_port_stats_cmd::fw_port_stats u

fw_port_stats_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:7929

fw_port_trace_cmd
Definition: t4fw_interface.h:8111

fw_port_trace_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8113

fw_port_trace_cmd::r5
__be32 r5
Definition: t4fw_interface.h:8116

fw_port_trace_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:8112

fw_port_trace_cmd::qnum
__be16 qnum
Definition: t4fw_interface.h:8115

fw_port_trace_cmd::traceen_to_pciech
__be16 traceen_to_pciech
Definition: t4fw_interface.h:8114

fw_port_trace_mmap_cmd
Definition: t4fw_interface.h:8160

fw_port_trace_mmap_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:8161

fw_port_trace_mmap_cmd::map
__u8 map[224]
Definition: t4fw_interface.h:8165

fw_port_trace_mmap_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8162

fw_port_trace_mmap_cmd::minpktsize_capturemax
__be32 minpktsize_capturemax
Definition: t4fw_interface.h:8164

fw_port_trace_mmap_cmd::fid_to_skipoffset
__be32 fid_to_skipoffset
Definition: t4fw_interface.h:8163

fw_ptp_cmd::fw_ptp::fw_ptp_init
Definition: t4fw_interface.h:8259

fw_ptp_cmd::fw_ptp::fw_ptp_init::txchan
__u8 txchan
Definition: t4fw_interface.h:8261

fw_ptp_cmd::fw_ptp::fw_ptp_init::sc
__u8 sc
Definition: t4fw_interface.h:8260

fw_ptp_cmd::fw_ptp::fw_ptp_init::ptp_rx_ctrl_pkd
__be16 ptp_rx_ctrl_pkd
Definition: t4fw_interface.h:8264

fw_ptp_cmd::fw_ptp::fw_ptp_init::absid
__be16 absid
Definition: t4fw_interface.h:8262

fw_ptp_cmd::fw_ptp::fw_ptp_init::mode
__be16 mode
Definition: t4fw_interface.h:8263

fw_ptp_cmd::fw_ptp::fw_ptp_sc
Definition: t4fw_interface.h:8255

fw_ptp_cmd::fw_ptp::fw_ptp_sc::sc
__u8 sc
Definition: t4fw_interface.h:8256

fw_ptp_cmd::fw_ptp::fw_ptp_sc::r3
__u8 r3[7]
Definition: t4fw_interface.h:8257

fw_ptp_cmd::fw_ptp::fw_ptp_ts
Definition: t4fw_interface.h:8266

fw_ptp_cmd::fw_ptp::fw_ptp_ts::sign
__u8 sign
Definition: t4fw_interface.h:8268

fw_ptp_cmd::fw_ptp::fw_ptp_ts::ppb
__be32 ppb
Definition: t4fw_interface.h:8270

fw_ptp_cmd::fw_ptp::fw_ptp_ts::sc
__u8 sc
Definition: t4fw_interface.h:8267

fw_ptp_cmd::fw_ptp::fw_ptp_ts::tm
__be64 tm
Definition: t4fw_interface.h:8271

fw_ptp_cmd::fw_ptp::fw_ptp_ts::r3
__be16 r3
Definition: t4fw_interface.h:8269

fw_ptp_cmd
Definition: t4fw_interface.h:8251

fw_ptp_cmd::r3
__be64 r3
Definition: t4fw_interface.h:8274

fw_ptp_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8253

fw_ptp_cmd::u
union fw_ptp_cmd::fw_ptp u

fw_ptp_cmd::op_to_portid
__be32 op_to_portid
Definition: t4fw_interface.h:8252

fw_rdev_wr::rdev_entry::fcoe_rdev_entry
Definition: t4fw_interface.h:2340

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::vft_to_qos
__u8 vft_to_qos
Definition: t4fw_interface.h:2350

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::wwpn
__u8 wwpn[8]
Definition: t4fw_interface.h:2354

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::r_id
__u8 r_id[3]
Definition: t4fw_interface.h:2357

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::wwnn
__u8 wwnn[8]
Definition: t4fw_interface.h:2353

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::iqid
__be16 iqid
Definition: t4fw_interface.h:2355

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::flowid
__be32 flowid
Definition: t4fw_interface.h:2341

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::rcv_fr_sz
__be16 rcv_fr_sz
Definition: t4fw_interface.h:2348

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::prev_login_st
__u8 prev_login_st
Definition: t4fw_interface.h:2347

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::rjt_reason
__u8 rjt_reason
Definition: t4fw_interface.h:2345

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::org_proc_assoc_to_acc_rsp_code
__u8 org_proc_assoc_to_acc_rsp_code
Definition: t4fw_interface.h:2351

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::protocol
__u8 protocol
Definition: t4fw_interface.h:2342

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::rd_xfer_rdy_to_rport_type
__u8 rd_xfer_rdy_to_rport_type
Definition: t4fw_interface.h:2349

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::event_cause
__u8 event_cause
Definition: t4fw_interface.h:2343

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::flags
__u8 flags
Definition: t4fw_interface.h:2344

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::fc_oui
__u8 fc_oui[3]
Definition: t4fw_interface.h:2356

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::enh_disc_to_tgt
__u8 enh_disc_to_tgt
Definition: t4fw_interface.h:2352

fw_rdev_wr::rdev_entry::fcoe_rdev_entry::cur_login_st
__u8 cur_login_st
Definition: t4fw_interface.h:2346

fw_rdev_wr::rdev_entry::iscsi_rdev_entry
Definition: t4fw_interface.h:2359

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::first_brst_len
__be16 first_brst_len
Definition: t4fw_interface.h:2370

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::non_scsi_to
__be16 non_scsi_to
Definition: t4fw_interface.h:2376

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::protocol
__u8 protocol
Definition: t4fw_interface.h:2361

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::iqid
__be16 iqid
Definition: t4fw_interface.h:2382

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::def_time2ret
__be16 def_time2ret
Definition: t4fw_interface.h:2374

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::def_time2wait
__be16 def_time2wait
Definition: t4fw_interface.h:2373

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::tcp_opts
__be16 tcp_opts
Definition: t4fw_interface.h:2366

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::r5
__u8 r5[6]
Definition: t4fw_interface.h:2381

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::tpgt
__be16 tpgt
Definition: t4fw_interface.h:2380

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::max_brst_len
__be16 max_brst_len
Definition: t4fw_interface.h:2371

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::nop_out_intrvl
__be16 nop_out_intrvl
Definition: t4fw_interface.h:2375

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::tsid
__be16 tsid
Definition: t4fw_interface.h:2378

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::r3
__u8 r3
Definition: t4fw_interface.h:2364

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::iscsi_opts
__be16 iscsi_opts
Definition: t4fw_interface.h:2365

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::r4
__be16 r4
Definition: t4fw_interface.h:2372

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::flowid
__be32 flowid
Definition: t4fw_interface.h:2360

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::port
__be16 port
Definition: t4fw_interface.h:2379

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::max_rcv_len
__be16 max_rcv_len
Definition: t4fw_interface.h:2368

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::max_snd_len
__be16 max_snd_len
Definition: t4fw_interface.h:2369

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::isid
__be16 isid
Definition: t4fw_interface.h:2377

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::ip_opts
__be16 ip_opts
Definition: t4fw_interface.h:2367

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::event_cause
__u8 event_cause
Definition: t4fw_interface.h:2362

fw_rdev_wr::rdev_entry::iscsi_rdev_entry::flags
__u8 flags
Definition: t4fw_interface.h:2363

fw_rdev_wr
Definition: t4fw_interface.h:2330

fw_rdev_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:2331

fw_rdev_wr::flags_to_assoc_flowid
__be32 flags_to_assoc_flowid
Definition: t4fw_interface.h:2338

fw_rdev_wr::prev_state
__u8 prev_state
Definition: t4fw_interface.h:2337

fw_rdev_wr::cur_state
__u8 cur_state
Definition: t4fw_interface.h:2336

fw_rdev_wr::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:2332

fw_rdev_wr::event_cause
__u8 event_cause
Definition: t4fw_interface.h:2335

fw_rdev_wr::protocol
__u8 protocol
Definition: t4fw_interface.h:2334

fw_rdev_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:2333

fw_rdev_wr::u
union fw_rdev_wr::rdev_entry u

fw_reset_cmd
Definition: t4fw_interface.h:4493

fw_reset_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:4495

fw_reset_cmd::halt_pkd
__be32 halt_pkd
Definition: t4fw_interface.h:4497

fw_reset_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:4494

fw_reset_cmd::val
__be32 val
Definition: t4fw_interface.h:4496

fw_ri_atomic_wr
Definition: t4fw_interface.h:2041

fw_ri_atomic_wr::to_lo
__be32 to_lo
Definition: t4fw_interface.h:2053

fw_ri_atomic_wr::atomicop_pkd
__be32 atomicop_pkd
Definition: t4fw_interface.h:2047

fw_ri_atomic_wr::stag
__be32 stag
Definition: t4fw_interface.h:2051

fw_ri_atomic_wr::compare_mask_hi
__be32 compare_mask_hi
Definition: t4fw_interface.h:2060

fw_ri_atomic_wr::r3
__be64 r3
Definition: t4fw_interface.h:2048

fw_ri_atomic_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:2044

fw_ri_atomic_wr::addswap_mask_lo
__be32 addswap_mask_lo
Definition: t4fw_interface.h:2057

fw_ri_atomic_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:2045

fw_ri_atomic_wr::addswap_data_lo
__be32 addswap_data_lo
Definition: t4fw_interface.h:2055

fw_ri_atomic_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:2042

fw_ri_atomic_wr::aopcode_pkd
__be32 aopcode_pkd
Definition: t4fw_interface.h:2049

fw_ri_atomic_wr::r5
__be32 r5
Definition: t4fw_interface.h:2062

fw_ri_atomic_wr::addswap_mask_hi
__be32 addswap_mask_hi
Definition: t4fw_interface.h:2056

fw_ri_atomic_wr::compare_data_hi
__be32 compare_data_hi
Definition: t4fw_interface.h:2058

fw_ri_atomic_wr::len16
__u8 len16
Definition: t4fw_interface.h:2046

fw_ri_atomic_wr::reqid
__be32 reqid
Definition: t4fw_interface.h:2050

fw_ri_atomic_wr::flags
__u8 flags
Definition: t4fw_interface.h:2043

fw_ri_atomic_wr::addswap_data_hi
__be32 addswap_data_hi
Definition: t4fw_interface.h:2054

fw_ri_atomic_wr::to_hi
__be32 to_hi
Definition: t4fw_interface.h:2052

fw_ri_atomic_wr::compare_mask_lo
__be32 compare_mask_lo
Definition: t4fw_interface.h:2061

fw_ri_atomic_wr::compare_data_lo
__be32 compare_data_lo
Definition: t4fw_interface.h:2059

fw_ri_bind_mw_wr
Definition: t4fw_interface.h:1914

fw_ri_bind_mw_wr::stag_mw
__be32 stag_mw
Definition: t4fw_interface.h:1925

fw_ri_bind_mw_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1917

fw_ri_bind_mw_wr::mem_perms
__u8 mem_perms
Definition: t4fw_interface.h:1923

fw_ri_bind_mw_wr::stag_mr
__be32 stag_mr
Definition: t4fw_interface.h:1924

fw_ri_bind_mw_wr::qpbinde_to_dcacpu
__u8 qpbinde_to_dcacpu
Definition: t4fw_interface.h:1920

fw_ri_bind_mw_wr::len16
__u8 len16
Definition: t4fw_interface.h:1919

fw_ri_bind_mw_wr::flags
__u8 flags
Definition: t4fw_interface.h:1916

fw_ri_bind_mw_wr::r4
__be64 r4
Definition: t4fw_interface.h:1929

fw_ri_bind_mw_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1915

fw_ri_bind_mw_wr::pgsz_shift
__u8 pgsz_shift
Definition: t4fw_interface.h:1921

fw_ri_bind_mw_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1918

fw_ri_bind_mw_wr::r3
__be32 r3
Definition: t4fw_interface.h:1926

fw_ri_bind_mw_wr::va_fbo
__be64 va_fbo
Definition: t4fw_interface.h:1928

fw_ri_bind_mw_wr::addr_type
__u8 addr_type
Definition: t4fw_interface.h:1922

fw_ri_bind_mw_wr::len_mw
__be64 len_mw
Definition: t4fw_interface.h:1927

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe_imm
Definition: t4fw_interface.h:1486

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe_imm::plen
__be32 plen
Definition: t4fw_interface.h:1488

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe_imm::qpid_n_stat_rxtx_type
__be32 qpid_n_stat_rxtx_type
Definition: t4fw_interface.h:1487

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe_imm::mo
__be32 mo
Definition: t4fw_interface.h:1489

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe_imm::msn
__be32 msn
Definition: t4fw_interface.h:1490

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe_imm::imm_data
__u64 imm_data
Definition: t4fw_interface.h:1491

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe
Definition: t4fw_interface.h:1480

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe::msn
__be32 msn
Definition: t4fw_interface.h:1484

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe::plen
__be32 plen
Definition: t4fw_interface.h:1482

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe::qpid_n_stat_rxtx_type
__be32 qpid_n_stat_rxtx_type
Definition: t4fw_interface.h:1481

fw_ri_cqe::fw_ri_rxtx::fw_ri_rcqe::stag
__be32 stag
Definition: t4fw_interface.h:1483

fw_ri_cqe::fw_ri_rxtx::fw_ri_scqe
Definition: t4fw_interface.h:1474

fw_ri_cqe::fw_ri_rxtx::fw_ri_scqe::wrid
__be32 wrid
Definition: t4fw_interface.h:1478

fw_ri_cqe::fw_ri_rxtx::fw_ri_scqe::plen
__be32 plen
Definition: t4fw_interface.h:1476

fw_ri_cqe::fw_ri_rxtx::fw_ri_scqe::qpid_n_stat_rxtx_type
__be32 qpid_n_stat_rxtx_type
Definition: t4fw_interface.h:1475

fw_ri_cqe::fw_ri_rxtx::fw_ri_scqe::stag
__be32 stag
Definition: t4fw_interface.h:1477

fw_ri_cqe
Definition: t4fw_interface.h:1472

fw_ri_cqe::u
union fw_ri_cqe::fw_ri_rxtx u

fw_ri_dsge_pair
Definition: t4fw_interface.h:1317

fw_ri_dsge_pair::len
__be32 len[2]
Definition: t4fw_interface.h:1318

fw_ri_dsge_pair::addr
__be64 addr[2]
Definition: t4fw_interface.h:1319

fw_ri_dsgl
Definition: t4fw_interface.h:1322

fw_ri_dsgl::addr0
__be64 addr0
Definition: t4fw_interface.h:1327

fw_ri_dsgl::len0
__be32 len0
Definition: t4fw_interface.h:1326

fw_ri_dsgl::nsge
__be16 nsge
Definition: t4fw_interface.h:1325

fw_ri_dsgl::op
__u8 op
Definition: t4fw_interface.h:1323

fw_ri_dsgl::r1
__u8 r1
Definition: t4fw_interface.h:1324

fw_ri_fr_nsmr_tpte_wr
Definition: t4fw_interface.h:1989

fw_ri_fr_nsmr_tpte_wr::stag
__be32 stag
Definition: t4fw_interface.h:1996

fw_ri_fr_nsmr_tpte_wr::tpte
struct fw_ri_tpte tpte
Definition: t4fw_interface.h:1997

fw_ri_fr_nsmr_tpte_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1993

fw_ri_fr_nsmr_tpte_wr::flags
__u8 flags
Definition: t4fw_interface.h:1991

fw_ri_fr_nsmr_tpte_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1990

fw_ri_fr_nsmr_tpte_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1992

fw_ri_fr_nsmr_tpte_wr::len16
__u8 len16
Definition: t4fw_interface.h:1994

fw_ri_fr_nsmr_tpte_wr::pbl
__be64 pbl[2]
Definition: t4fw_interface.h:1998

fw_ri_fr_nsmr_tpte_wr::r2
__be32 r2
Definition: t4fw_interface.h:1995

fw_ri_fr_nsmr_wr
Definition: t4fw_interface.h:1952

fw_ri_fr_nsmr_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1956

fw_ri_fr_nsmr_wr::addr_type
__u8 addr_type
Definition: t4fw_interface.h:1960

fw_ri_fr_nsmr_wr::len_hi
__be32 len_hi
Definition: t4fw_interface.h:1963

fw_ri_fr_nsmr_wr::len16
__u8 len16
Definition: t4fw_interface.h:1957

fw_ri_fr_nsmr_wr::va_lo_fbo
__be32 va_lo_fbo
Definition: t4fw_interface.h:1966

fw_ri_fr_nsmr_wr::va_hi
__be32 va_hi
Definition: t4fw_interface.h:1965

fw_ri_fr_nsmr_wr::mem_perms
__u8 mem_perms
Definition: t4fw_interface.h:1961

fw_ri_fr_nsmr_wr::len_lo
__be32 len_lo
Definition: t4fw_interface.h:1964

fw_ri_fr_nsmr_wr::qpbinde_to_dcacpu
__u8 qpbinde_to_dcacpu
Definition: t4fw_interface.h:1958

fw_ri_fr_nsmr_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1955

fw_ri_fr_nsmr_wr::pgsz_shift
__u8 pgsz_shift
Definition: t4fw_interface.h:1959

fw_ri_fr_nsmr_wr::stag
__be32 stag
Definition: t4fw_interface.h:1962

fw_ri_fr_nsmr_wr::flags
__u8 flags
Definition: t4fw_interface.h:1954

fw_ri_fr_nsmr_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1953

fw_ri_immd
Definition: t4fw_interface.h:1349

fw_ri_immd::r1
__u8 r1
Definition: t4fw_interface.h:1351

fw_ri_immd::op
__u8 op
Definition: t4fw_interface.h:1350

fw_ri_immd::immdlen
__be32 immdlen
Definition: t4fw_interface.h:1353

fw_ri_immd::data
__u8 data[0]
Definition: t4fw_interface.h:1355

fw_ri_immd::r2
__be16 r2
Definition: t4fw_interface.h:1352

fw_ri_inv_lstag_wr
Definition: t4fw_interface.h:2001

fw_ri_inv_lstag_wr::r2
__be32 r2
Definition: t4fw_interface.h:2007

fw_ri_inv_lstag_wr::len16
__u8 len16
Definition: t4fw_interface.h:2006

fw_ri_inv_lstag_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:2005

fw_ri_inv_lstag_wr::flags
__u8 flags
Definition: t4fw_interface.h:2003

fw_ri_inv_lstag_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:2004

fw_ri_inv_lstag_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:2002

fw_ri_inv_lstag_wr::stag_inv
__be32 stag_inv
Definition: t4fw_interface.h:2008

fw_ri_isgl
Definition: t4fw_interface.h:1339

fw_ri_isgl::nsge
__be16 nsge
Definition: t4fw_interface.h:1342

fw_ri_isgl::r1
__u8 r1
Definition: t4fw_interface.h:1341

fw_ri_isgl::r2
__be32 r2
Definition: t4fw_interface.h:1343

fw_ri_isgl::op
__u8 op
Definition: t4fw_interface.h:1340

fw_ri_rdma_read_wr
Definition: t4fw_interface.h:1888

fw_ri_rdma_read_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1892

fw_ri_rdma_read_wr::r2
__be64 r2
Definition: t4fw_interface.h:1894

fw_ri_rdma_read_wr::to_src_lo
__be32 to_src_lo
Definition: t4fw_interface.h:1901

fw_ri_rdma_read_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1889

fw_ri_rdma_read_wr::to_sink_hi
__be32 to_sink_hi
Definition: t4fw_interface.h:1896

fw_ri_rdma_read_wr::plen
__be32 plen
Definition: t4fw_interface.h:1898

fw_ri_rdma_read_wr::flags
__u8 flags
Definition: t4fw_interface.h:1890

fw_ri_rdma_read_wr::stag_src
__be32 stag_src
Definition: t4fw_interface.h:1899

fw_ri_rdma_read_wr::len16
__u8 len16
Definition: t4fw_interface.h:1893

fw_ri_rdma_read_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1891

fw_ri_rdma_read_wr::stag_sink
__be32 stag_sink
Definition: t4fw_interface.h:1895

fw_ri_rdma_read_wr::to_sink_lo
__be32 to_sink_lo
Definition: t4fw_interface.h:1897

fw_ri_rdma_read_wr::to_src_hi
__be32 to_src_hi
Definition: t4fw_interface.h:1900

fw_ri_rdma_read_wr::r5
__be32 r5
Definition: t4fw_interface.h:1902

fw_ri_rdma_write_cmpl_wr::fw_ri_cmpl::fw_ri_immd_cmpl
Definition: t4fw_interface.h:1871

fw_ri_rdma_write_cmpl_wr::fw_ri_cmpl::fw_ri_immd_cmpl::data
__u8 data[16]
Definition: t4fw_interface.h:1875

fw_ri_rdma_write_cmpl_wr::fw_ri_cmpl::fw_ri_immd_cmpl::r1
__u8 r1[6]
Definition: t4fw_interface.h:1873

fw_ri_rdma_write_cmpl_wr::fw_ri_cmpl::fw_ri_immd_cmpl::immdlen
__u8 immdlen
Definition: t4fw_interface.h:1874

fw_ri_rdma_write_cmpl_wr::fw_ri_cmpl::fw_ri_immd_cmpl::op
__u8 op
Definition: t4fw_interface.h:1872

fw_ri_rdma_write_cmpl_wr
Definition: t4fw_interface.h:1857

fw_ri_rdma_write_cmpl_wr::to_sink
__be64 to_sink
Definition: t4fw_interface.h:1869

fw_ri_rdma_write_cmpl_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1860

fw_ri_rdma_write_cmpl_wr::stag_inv
__be32 stag_inv
Definition: t4fw_interface.h:1866

fw_ri_rdma_write_cmpl_wr::len16
__u8 len16
Definition: t4fw_interface.h:1862

fw_ri_rdma_write_cmpl_wr::r3
__be64 r3
Definition: t4fw_interface.h:1879

fw_ri_rdma_write_cmpl_wr::u
union fw_ri_rdma_write_cmpl_wr::fw_ri_write u

fw_ri_rdma_write_cmpl_wr::flags
__u8 flags
Definition: t4fw_interface.h:1859

fw_ri_rdma_write_cmpl_wr::u_cmpl
union fw_ri_rdma_write_cmpl_wr::fw_ri_cmpl u_cmpl

fw_ri_rdma_write_cmpl_wr::flags_send
__u8 flags_send
Definition: t4fw_interface.h:1864

fw_ri_rdma_write_cmpl_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1861

fw_ri_rdma_write_cmpl_wr::plen
__be32 plen
Definition: t4fw_interface.h:1867

fw_ri_rdma_write_cmpl_wr::stag_sink
__be32 stag_sink
Definition: t4fw_interface.h:1868

fw_ri_rdma_write_cmpl_wr::r2
__u8 r2
Definition: t4fw_interface.h:1863

fw_ri_rdma_write_cmpl_wr::wrid_send
__u16 wrid_send
Definition: t4fw_interface.h:1865

fw_ri_rdma_write_cmpl_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1858

fw_ri_rdma_write_wr
Definition: t4fw_interface.h:1814

fw_ri_rdma_write_wr::isgl_src
struct fw_ri_isgl isgl_src[0]
Definition: t4fw_interface.h:1827

fw_ri_rdma_write_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1818

fw_ri_rdma_write_wr::flags
__u8 flags
Definition: t4fw_interface.h:1816

fw_ri_rdma_write_wr::u
union fw_ri_rdma_write_wr::@67 u

fw_ri_rdma_write_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1815

fw_ri_rdma_write_wr::stag_sink
__be32 stag_sink
Definition: t4fw_interface.h:1822

fw_ri_rdma_write_wr::to_sink
__be64 to_sink
Definition: t4fw_interface.h:1823

fw_ri_rdma_write_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1817

fw_ri_rdma_write_wr::len16
__u8 len16
Definition: t4fw_interface.h:1819

fw_ri_rdma_write_wr::plen
__be32 plen
Definition: t4fw_interface.h:1821

fw_ri_rdma_write_wr::immd_src
struct fw_ri_immd immd_src[0]
Definition: t4fw_interface.h:1826

fw_ri_rdma_write_wr::immd_data
__u64 immd_data
Definition: t4fw_interface.h:1820

fw_ri_recv_wr
Definition: t4fw_interface.h:1905

fw_ri_recv_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1908

fw_ri_recv_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1906

fw_ri_recv_wr::r2
__u8 r2[3]
Definition: t4fw_interface.h:1909

fw_ri_recv_wr::len16
__u8 len16
Definition: t4fw_interface.h:1910

fw_ri_recv_wr::isgl
struct fw_ri_isgl isgl
Definition: t4fw_interface.h:1911

fw_ri_recv_wr::r1
__u8 r1
Definition: t4fw_interface.h:1907

fw_ri_res::fw_ri_restype::fw_ri_res_cq
Definition: t4fw_interface.h:1551

fw_ri_res::fw_ri_restype::fw_ri_res_cq::r3
__be16 r3
Definition: t4fw_interface.h:1554

fw_ri_res::fw_ri_restype::fw_ri_res_cq::iqsize
__be16 iqsize
Definition: t4fw_interface.h:1559

fw_ri_res::fw_ri_restype::fw_ri_res_cq::iqaddr
__be64 iqaddr
Definition: t4fw_interface.h:1560

fw_ri_res::fw_ri_restype::fw_ri_res_cq::r7
__be64 r7
Definition: t4fw_interface.h:1563

fw_ri_res::fw_ri_restype::fw_ri_res_cq::iqandst_to_iqandstindex
__be32 iqandst_to_iqandstindex
Definition: t4fw_interface.h:1557

fw_ri_res::fw_ri_restype::fw_ri_res_cq::r6_lo
__be32 r6_lo
Definition: t4fw_interface.h:1562

fw_ri_res::fw_ri_restype::fw_ri_res_cq::r4
__be32 r4[2]
Definition: t4fw_interface.h:1556

fw_ri_res::fw_ri_restype::fw_ri_res_cq::iqdroprss_to_iqesize
__be16 iqdroprss_to_iqesize
Definition: t4fw_interface.h:1558

fw_ri_res::fw_ri_restype::fw_ri_res_cq::iqns_iqro
__be32 iqns_iqro
Definition: t4fw_interface.h:1561

fw_ri_res::fw_ri_restype::fw_ri_res_cq::iqid
__be32 iqid
Definition: t4fw_interface.h:1555

fw_ri_res::fw_ri_restype::fw_ri_res_cq::op
__u8 op
Definition: t4fw_interface.h:1553

fw_ri_res::fw_ri_restype::fw_ri_res_cq::restype
__u8 restype
Definition: t4fw_interface.h:1552

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq
Definition: t4fw_interface.h:1541

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::eqaddr
__be64 eqaddr
Definition: t4fw_interface.h:1549

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::eqid
__be32 eqid
Definition: t4fw_interface.h:1545

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::op
__u8 op
Definition: t4fw_interface.h:1543

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::r3
__be16 r3
Definition: t4fw_interface.h:1544

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::fetchszm_to_iqid
__be32 fetchszm_to_iqid
Definition: t4fw_interface.h:1547

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::r4
__be32 r4[2]
Definition: t4fw_interface.h:1546

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::restype
__u8 restype
Definition: t4fw_interface.h:1542

fw_ri_res::fw_ri_restype::fw_ri_res_sqrq::dcaen_to_eqsize
__be32 dcaen_to_eqsize
Definition: t4fw_interface.h:1548

fw_ri_res::fw_ri_restype::fw_ri_res_srq
Definition: t4fw_interface.h:1565

fw_ri_res::fw_ri_restype::fw_ri_res_srq::hwsrqaddr
__be32 hwsrqaddr
Definition: t4fw_interface.h:1577

fw_ri_res::fw_ri_restype::fw_ri_res_srq::dcaen_to_eqsize
__be32 dcaen_to_eqsize
Definition: t4fw_interface.h:1572

fw_ri_res::fw_ri_restype::fw_ri_res_srq::fetchszm_to_iqid
__be32 fetchszm_to_iqid
Definition: t4fw_interface.h:1571

fw_ri_res::fw_ri_restype::fw_ri_res_srq::eqid
__be32 eqid
Definition: t4fw_interface.h:1569

fw_ri_res::fw_ri_restype::fw_ri_res_srq::srqid
__be32 srqid
Definition: t4fw_interface.h:1574

fw_ri_res::fw_ri_restype::fw_ri_res_srq::pdid
__be32 pdid
Definition: t4fw_interface.h:1575

fw_ri_res::fw_ri_restype::fw_ri_res_srq::op
__u8 op
Definition: t4fw_interface.h:1567

fw_ri_res::fw_ri_restype::fw_ri_res_srq::eqaddr
__be64 eqaddr
Definition: t4fw_interface.h:1573

fw_ri_res::fw_ri_restype::fw_ri_res_srq::r4
__be32 r4[2]
Definition: t4fw_interface.h:1570

fw_ri_res::fw_ri_restype::fw_ri_res_srq::restype
__u8 restype
Definition: t4fw_interface.h:1566

fw_ri_res::fw_ri_restype::fw_ri_res_srq::r3
__be16 r3
Definition: t4fw_interface.h:1568

fw_ri_res::fw_ri_restype::fw_ri_res_srq::hwsrqsize
__be32 hwsrqsize
Definition: t4fw_interface.h:1576

fw_ri_res_wr
Definition: t4fw_interface.h:1582

fw_ri_res_wr::op_nres
__be32 op_nres
Definition: t4fw_interface.h:1583

fw_ri_res_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:1585

fw_ri_res_wr::res
struct fw_ri_res res[0]
Definition: t4fw_interface.h:1587

fw_ri_res_wr::len16_pkd
__be32 len16_pkd
Definition: t4fw_interface.h:1584

fw_ri_res
Definition: t4fw_interface.h:1539

fw_ri_res::u
union fw_ri_res::fw_ri_restype u

fw_ri_send_immediate_wr
Definition: t4fw_interface.h:2011

fw_ri_send_immediate_wr::plen
__be32 plen
Definition: t4fw_interface.h:2019

fw_ri_send_immediate_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:2015

fw_ri_send_immediate_wr::flags
__u8 flags
Definition: t4fw_interface.h:2013

fw_ri_send_immediate_wr::r4
__be32 r4
Definition: t4fw_interface.h:2020

fw_ri_send_immediate_wr::immd_src
struct fw_ri_immd immd_src[0]
Definition: t4fw_interface.h:2023

fw_ri_send_immediate_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:2014

fw_ri_send_immediate_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:2012

fw_ri_send_immediate_wr::r3
__be32 r3
Definition: t4fw_interface.h:2018

fw_ri_send_immediate_wr::len16
__u8 len16
Definition: t4fw_interface.h:2016

fw_ri_send_immediate_wr::sendimmop_pkd
__be32 sendimmop_pkd
Definition: t4fw_interface.h:2017

fw_ri_send_immediate_wr::r5
__be64 r5
Definition: t4fw_interface.h:2021

fw_ri_send_wr
Definition: t4fw_interface.h:1832

fw_ri_send_wr::wrid
__u16 wrid
Definition: t4fw_interface.h:1835

fw_ri_send_wr::plen
__be32 plen
Definition: t4fw_interface.h:1840

fw_ri_send_wr::opcode
__u8 opcode
Definition: t4fw_interface.h:1833

fw_ri_send_wr::len16
__u8 len16
Definition: t4fw_interface.h:1837

fw_ri_send_wr::r3
__be32 r3
Definition: t4fw_interface.h:1841

fw_ri_send_wr::immd_src
struct fw_ri_immd immd_src[0]
Definition: t4fw_interface.h:1845

fw_ri_send_wr::isgl_src
struct fw_ri_isgl isgl_src[0]
Definition: t4fw_interface.h:1846

fw_ri_send_wr::r1
__u8 r1[3]
Definition: t4fw_interface.h:1836

fw_ri_send_wr::u
union fw_ri_send_wr::@68 u

fw_ri_send_wr::stag_inv
__be32 stag_inv
Definition: t4fw_interface.h:1839

fw_ri_send_wr::r4
__be64 r4
Definition: t4fw_interface.h:1842

fw_ri_send_wr::flags
__u8 flags
Definition: t4fw_interface.h:1834

fw_ri_send_wr::sendop_pkd
__be32 sendop_pkd
Definition: t4fw_interface.h:1838

fw_ri_sge
Definition: t4fw_interface.h:1333

fw_ri_sge::stag
__be32 stag
Definition: t4fw_interface.h:1334

fw_ri_sge::len
__be32 len
Definition: t4fw_interface.h:1335

fw_ri_sge::to
__be64 to
Definition: t4fw_interface.h:1336

fw_ri_tpte
Definition: t4fw_interface.h:1359

fw_ri_tpte::dca_mwbcnt_pstag
__be32 dca_mwbcnt_pstag
Definition: t4fw_interface.h:1366

fw_ri_tpte::va_lo_fbo
__be32 va_lo_fbo
Definition: t4fw_interface.h:1365

fw_ri_tpte::valid_to_pdid
__be32 valid_to_pdid
Definition: t4fw_interface.h:1360

fw_ri_tpte::va_hi
__be32 va_hi
Definition: t4fw_interface.h:1364

fw_ri_tpte::locread_to_qpid
__be32 locread_to_qpid
Definition: t4fw_interface.h:1361

fw_ri_tpte::nosnoop_pbladdr
__be32 nosnoop_pbladdr
Definition: t4fw_interface.h:1362

fw_ri_tpte::len_hi
__be32 len_hi
Definition: t4fw_interface.h:1367

fw_ri_tpte::len_lo
__be32 len_lo
Definition: t4fw_interface.h:1363

fw_ri_wr::fw_ri::fw_ri_fini
Definition: t4fw_interface.h:2128

fw_ri_wr::fw_ri::fw_ri_fini::r4
__be64 r4
Definition: t4fw_interface.h:2131

fw_ri_wr::fw_ri::fw_ri_fini::type
__u8 type
Definition: t4fw_interface.h:2129

fw_ri_wr::fw_ri::fw_ri_fini::r3
__u8 r3[7]
Definition: t4fw_interface.h:2130

fw_ri_wr::fw_ri::fw_ri_init
Definition: t4fw_interface.h:2102

fw_ri_wr::fw_ri::fw_ri_init::r4
__u8 r4[2]
Definition: t4fw_interface.h:2105

fw_ri_wr::fw_ri::fw_ri_init::type
__u8 type
Definition: t4fw_interface.h:2103

fw_ri_wr::fw_ri::fw_ri_init::mpa_attrs
__u8 mpa_attrs
Definition: t4fw_interface.h:2106

fw_ri_wr::fw_ri::fw_ri_init::iss
__be32 iss
Definition: t4fw_interface.h:2117

fw_ri_wr::fw_ri::fw_ri_init::rcqid
__be32 rcqid
Definition: t4fw_interface.h:2114

fw_ri_wr::fw_ri::fw_ri_init::qpid
__be32 qpid
Definition: t4fw_interface.h:2110

fw_ri_wr::fw_ri::fw_ri_init::qp_caps
__u8 qp_caps
Definition: t4fw_interface.h:2107

fw_ri_wr::fw_ri::fw_ri_init::r5
__be64 r5
Definition: t4fw_interface.h:2121

fw_ri_wr::fw_ri::fw_ri_init::irs
__be32 irs
Definition: t4fw_interface.h:2118

fw_ri_wr::fw_ri::fw_ri_init::ird_max
__be32 ird_max
Definition: t4fw_interface.h:2116

fw_ri_wr::fw_ri::fw_ri_init::hwrqaddr
__be32 hwrqaddr
Definition: t4fw_interface.h:2120

fw_ri_wr::fw_ri::fw_ri_init::u
union fw_ri_wr::fw_ri::fw_ri_init::fw_ri_init_p2p u

fw_ri_wr::fw_ri::fw_ri_init::scqid
__be32 scqid
Definition: t4fw_interface.h:2113

fw_ri_wr::fw_ri::fw_ri_init::rq_eqid
__be32 rq_eqid
Definition: t4fw_interface.h:2112

fw_ri_wr::fw_ri::fw_ri_init::sq_eqid
__be32 sq_eqid
Definition: t4fw_interface.h:2111

fw_ri_wr::fw_ri::fw_ri_init::pdid
__be32 pdid
Definition: t4fw_interface.h:2109

fw_ri_wr::fw_ri::fw_ri_init::ord_max
__be32 ord_max
Definition: t4fw_interface.h:2115

fw_ri_wr::fw_ri::fw_ri_init::hwrqsize
__be32 hwrqsize
Definition: t4fw_interface.h:2119

fw_ri_wr::fw_ri::fw_ri_init::mpareqbit_p2ptype
__u8 mpareqbit_p2ptype
Definition: t4fw_interface.h:2104

fw_ri_wr::fw_ri::fw_ri_init::nrqe
__be16 nrqe
Definition: t4fw_interface.h:2108

fw_ri_wr::fw_ri::fw_ri_terminate
Definition: t4fw_interface.h:2133

fw_ri_wr::fw_ri::fw_ri_terminate::r3
__u8 r3[3]
Definition: t4fw_interface.h:2135

fw_ri_wr::fw_ri::fw_ri_terminate::termmsg
__u8 termmsg[40]
Definition: t4fw_interface.h:2137

fw_ri_wr::fw_ri::fw_ri_terminate::immdlen
__be32 immdlen
Definition: t4fw_interface.h:2136

fw_ri_wr::fw_ri::fw_ri_terminate::type
__u8 type
Definition: t4fw_interface.h:2134

fw_ri_wr
Definition: t4fw_interface.h:2097

fw_ri_wr::u
union fw_ri_wr::fw_ri u

fw_ri_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:2098

fw_ri_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:2100

fw_ri_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:2099

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual
Definition: t4fw_interface.h:8519

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual::synmapen_to_hashtoeplitz
__be32 synmapen_to_hashtoeplitz
Definition: t4fw_interface.h:8521

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual::mode_keymode
__be32 mode_keymode
Definition: t4fw_interface.h:8520

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual::r9
__be64 r9
Definition: t4fw_interface.h:8523

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_basicvirtual::r8
__be64 r8
Definition: t4fw_interface.h:8522

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual
Definition: t4fw_interface.h:8513

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual::r4
__be64 r4
Definition: t4fw_interface.h:8516

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual::r3
__be32 r3
Definition: t4fw_interface.h:8515

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual::mode_pkd
__be32 mode_pkd
Definition: t4fw_interface.h:8514

fw_rss_glb_config_cmd::fw_rss_glb_config::fw_rss_glb_config_manual::r5
__be64 r5
Definition: t4fw_interface.h:8517

fw_rss_glb_config_cmd
Definition: t4fw_interface.h:8509

fw_rss_glb_config_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8510

fw_rss_glb_config_cmd::u
union fw_rss_glb_config_cmd::fw_rss_glb_config u

fw_rss_glb_config_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8511

fw_rss_ind_tbl_cmd
Definition: t4fw_interface.h:8291

fw_rss_ind_tbl_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:8292

fw_rss_ind_tbl_cmd::iq15_to_iq17
__be32 iq15_to_iq17
Definition: t4fw_interface.h:8302

fw_rss_ind_tbl_cmd::iq6_to_iq8
__be32 iq6_to_iq8
Definition: t4fw_interface.h:8299

fw_rss_ind_tbl_cmd::iq18_to_iq20
__be32 iq18_to_iq20
Definition: t4fw_interface.h:8303

fw_rss_ind_tbl_cmd::iq3_to_iq5
__be32 iq3_to_iq5
Definition: t4fw_interface.h:8298

fw_rss_ind_tbl_cmd::niqid
__be16 niqid
Definition: t4fw_interface.h:8294

fw_rss_ind_tbl_cmd::r15_lo
__be32 r15_lo
Definition: t4fw_interface.h:8308

fw_rss_ind_tbl_cmd::r3
__be32 r3
Definition: t4fw_interface.h:8296

fw_rss_ind_tbl_cmd::iq30_iq31
__be32 iq30_iq31
Definition: t4fw_interface.h:8307

fw_rss_ind_tbl_cmd::iq0_to_iq2
__be32 iq0_to_iq2
Definition: t4fw_interface.h:8297

fw_rss_ind_tbl_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8293

fw_rss_ind_tbl_cmd::iq24_to_iq26
__be32 iq24_to_iq26
Definition: t4fw_interface.h:8305

fw_rss_ind_tbl_cmd::iq27_to_iq29
__be32 iq27_to_iq29
Definition: t4fw_interface.h:8306

fw_rss_ind_tbl_cmd::iq21_to_iq23
__be32 iq21_to_iq23
Definition: t4fw_interface.h:8304

fw_rss_ind_tbl_cmd::iq9_to_iq11
__be32 iq9_to_iq11
Definition: t4fw_interface.h:8300

fw_rss_ind_tbl_cmd::startidx
__be16 startidx
Definition: t4fw_interface.h:8295

fw_rss_ind_tbl_cmd::iq12_to_iq14
__be32 iq12_to_iq14
Definition: t4fw_interface.h:8301

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual
Definition: t4fw_interface.h:8647

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::secretkeyxor
__be32 secretkeyxor
Definition: t4fw_interface.h:8651

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::defaultq_to_udpen
__be32 defaultq_to_udpen
Definition: t4fw_interface.h:8649

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::r10
__be64 r10
Definition: t4fw_interface.h:8652

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::r6
__be32 r6
Definition: t4fw_interface.h:8648

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_basicvirtual::secretkeyidx_pkd
__be32 secretkeyidx_pkd
Definition: t4fw_interface.h:8650

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_manual
Definition: t4fw_interface.h:8642

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_manual::r5
__be64 r5
Definition: t4fw_interface.h:8645

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_manual::r4
__be64 r4
Definition: t4fw_interface.h:8644

fw_rss_vi_config_cmd::fw_rss_vi_config::fw_rss_vi_config_manual::r3
__be64 r3
Definition: t4fw_interface.h:8643

fw_rss_vi_config_cmd
Definition: t4fw_interface.h:8638

fw_rss_vi_config_cmd::u
union fw_rss_vi_config_cmd::fw_rss_vi_config u

fw_rss_vi_config_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:8639

fw_rss_vi_config_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8640

fw_sched_cmd::fw_sched::fw_sched_config
Definition: t4fw_interface.h:8761

fw_sched_cmd::fw_sched::fw_sched_config::sc
__u8 sc
Definition: t4fw_interface.h:8762

fw_sched_cmd::fw_sched::fw_sched_config::nclasses
__u8 nclasses[4]
Definition: t4fw_interface.h:8766

fw_sched_cmd::fw_sched::fw_sched_config::type
__u8 type
Definition: t4fw_interface.h:8763

fw_sched_cmd::fw_sched::fw_sched_config::r3
__u8 r3[5]
Definition: t4fw_interface.h:8765

fw_sched_cmd::fw_sched::fw_sched_config::minmaxen
__u8 minmaxen
Definition: t4fw_interface.h:8764

fw_sched_cmd::fw_sched::fw_sched_config::r4
__be32 r4
Definition: t4fw_interface.h:8767

fw_sched_cmd::fw_sched::fw_sched_params
Definition: t4fw_interface.h:8769

fw_sched_cmd::fw_sched::fw_sched_params::max
__be32 max
Definition: t4fw_interface.h:8779

fw_sched_cmd::fw_sched::fw_sched_params::unit
__u8 unit
Definition: t4fw_interface.h:8774

fw_sched_cmd::fw_sched::fw_sched_params::weight
__be16 weight
Definition: t4fw_interface.h:8780

fw_sched_cmd::fw_sched::fw_sched_params::ch
__u8 ch
Definition: t4fw_interface.h:8776

fw_sched_cmd::fw_sched::fw_sched_params::type
__u8 type
Definition: t4fw_interface.h:8771

fw_sched_cmd::fw_sched::fw_sched_params::rate
__u8 rate
Definition: t4fw_interface.h:8775

fw_sched_cmd::fw_sched::fw_sched_params::min
__be32 min
Definition: t4fw_interface.h:8778

fw_sched_cmd::fw_sched::fw_sched_params::burstsize
__be16 burstsize
Definition: t4fw_interface.h:8782

fw_sched_cmd::fw_sched::fw_sched_params::cl
__u8 cl
Definition: t4fw_interface.h:8777

fw_sched_cmd::fw_sched::fw_sched_params::pktsize
__be16 pktsize
Definition: t4fw_interface.h:8781

fw_sched_cmd::fw_sched::fw_sched_params::mode
__u8 mode
Definition: t4fw_interface.h:8773

fw_sched_cmd::fw_sched::fw_sched_params::sc
__u8 sc
Definition: t4fw_interface.h:8770

fw_sched_cmd::fw_sched::fw_sched_params::r4
__be16 r4
Definition: t4fw_interface.h:8783

fw_sched_cmd::fw_sched::fw_sched_params::level
__u8 level
Definition: t4fw_interface.h:8772

fw_sched_cmd
Definition: t4fw_interface.h:8757

fw_sched_cmd::op_to_write
__be32 op_to_write
Definition: t4fw_interface.h:8758

fw_sched_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8759

fw_sched_cmd::u
union fw_sched_cmd::fw_sched u

fw_scsi_abrt_cls_wr
Definition: t4fw_interface.h:3439

fw_scsi_abrt_cls_wr::sub_opcode_to_chk_all_io
__u8 sub_opcode_to_chk_all_io
Definition: t4fw_interface.h:3445

fw_scsi_abrt_cls_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3442

fw_scsi_abrt_cls_wr::r3
__u8 r3[4]
Definition: t4fw_interface.h:3446

fw_scsi_abrt_cls_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3440

fw_scsi_abrt_cls_wr::tmo_val
__u8 tmo_val
Definition: t4fw_interface.h:3444

fw_scsi_abrt_cls_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3441

fw_scsi_abrt_cls_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3443

fw_scsi_abrt_cls_wr::t_cookie
__be64 t_cookie
Definition: t4fw_interface.h:3447

fw_scsi_cmd_wr::fw_scsi_cmd_priv::fcoe_cmd_priv
Definition: t4fw_interface.h:3388

fw_scsi_cmd_wr::fw_scsi_cmd_priv::fcoe_cmd_priv::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3389

fw_scsi_cmd_wr::fw_scsi_cmd_priv::fcoe_cmd_priv::r4_lo
__u8 r4_lo[2]
Definition: t4fw_interface.h:3391

fw_scsi_cmd_wr::fw_scsi_cmd_priv::fcoe_cmd_priv::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3390

fw_scsi_cmd_wr::fw_scsi_cmd_priv::iscsi_cmd_priv
Definition: t4fw_interface.h:3393

fw_scsi_cmd_wr::fw_scsi_cmd_priv::iscsi_cmd_priv::r4
__u8 r4[4]
Definition: t4fw_interface.h:3394

fw_scsi_cmd_wr
Definition: t4fw_interface.h:3380

fw_scsi_cmd_wr::r6
__be32 r6
Definition: t4fw_interface.h:3400

fw_scsi_cmd_wr::tmo_val
__u8 tmo_val
Definition: t4fw_interface.h:3385

fw_scsi_cmd_wr::rsp_dmalen
__be32 rsp_dmalen
Definition: t4fw_interface.h:3399

fw_scsi_cmd_wr::rsp_dmaaddr
__be64 rsp_dmaaddr
Definition: t4fw_interface.h:3398

fw_scsi_cmd_wr::r5
__u8 r5[8]
Definition: t4fw_interface.h:3397

fw_scsi_cmd_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3382

fw_scsi_cmd_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3384

fw_scsi_cmd_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3383

fw_scsi_cmd_wr::r3
__u8 r3
Definition: t4fw_interface.h:3386

fw_scsi_cmd_wr::u
union fw_scsi_cmd_wr::fw_scsi_cmd_priv u

fw_scsi_cmd_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3381

fw_scsi_read_wr::fw_scsi_read_priv::fcoe_read_priv
Definition: t4fw_interface.h:3328

fw_scsi_read_wr::fw_scsi_read_priv::fcoe_read_priv::r3_lo
__u8 r3_lo[2]
Definition: t4fw_interface.h:3331

fw_scsi_read_wr::fw_scsi_read_priv::fcoe_read_priv::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3330

fw_scsi_read_wr::fw_scsi_read_priv::fcoe_read_priv::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3329

fw_scsi_read_wr::fw_scsi_read_priv::iscsi_read_priv
Definition: t4fw_interface.h:3333

fw_scsi_read_wr::fw_scsi_read_priv::iscsi_read_priv::r3
__u8 r3[4]
Definition: t4fw_interface.h:3334

fw_scsi_read_wr
Definition: t4fw_interface.h:3320

fw_scsi_read_wr::rsp_dmalen
__be32 rsp_dmalen
Definition: t4fw_interface.h:3340

fw_scsi_read_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3323

fw_scsi_read_wr::u
union fw_scsi_read_wr::fw_scsi_read_priv u

fw_scsi_read_wr::rsp_dmaaddr
__be64 rsp_dmaaddr
Definition: t4fw_interface.h:3339

fw_scsi_read_wr::r4
__be32 r4
Definition: t4fw_interface.h:3341

fw_scsi_read_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3324

fw_scsi_read_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3322

fw_scsi_read_wr::tmo_val
__u8 tmo_val
Definition: t4fw_interface.h:3325

fw_scsi_read_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3321

fw_scsi_read_wr::use_xfer_cnt
__u8 use_xfer_cnt
Definition: t4fw_interface.h:3326

fw_scsi_read_wr::xfer_cnt
__be32 xfer_cnt
Definition: t4fw_interface.h:3337

fw_scsi_read_wr::ini_xfer_cnt
__be32 ini_xfer_cnt
Definition: t4fw_interface.h:3338

fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv::fcoe_tgt_acc_priv
Definition: t4fw_interface.h:3508

fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv::fcoe_tgt_acc_priv::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3510

fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv::fcoe_tgt_acc_priv::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3509

fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv::fcoe_tgt_acc_priv::r4_lo
__u8 r4_lo[2]
Definition: t4fw_interface.h:3511

fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv::iscsi_tgt_acc_priv
Definition: t4fw_interface.h:3513

fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv::iscsi_tgt_acc_priv::r4
__u8 r4[4]
Definition: t4fw_interface.h:3514

fw_scsi_tgt_acc_wr
Definition: t4fw_interface.h:3500

fw_scsi_tgt_acc_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3503

fw_scsi_tgt_acc_wr::rel_off
__be32 rel_off
Definition: t4fw_interface.h:3518

fw_scsi_tgt_acc_wr::r6
__be32 r6
Definition: t4fw_interface.h:3520

fw_scsi_tgt_acc_wr::r5
__be64 r5
Definition: t4fw_interface.h:3519

fw_scsi_tgt_acc_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3502

fw_scsi_tgt_acc_wr::u
union fw_scsi_tgt_acc_wr::fw_scsi_tgt_acc_priv u

fw_scsi_tgt_acc_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3501

fw_scsi_tgt_acc_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3504

fw_scsi_tgt_acc_wr::tot_xfer_len
__be32 tot_xfer_len
Definition: t4fw_interface.h:3521

fw_scsi_tgt_acc_wr::r3
__u8 r3
Definition: t4fw_interface.h:3505

fw_scsi_tgt_acc_wr::burst_len
__be32 burst_len
Definition: t4fw_interface.h:3517

fw_scsi_tgt_acc_wr::use_burst_len
__u8 use_burst_len
Definition: t4fw_interface.h:3506

fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv::fcoe_tgt_rsp_priv
Definition: t4fw_interface.h:3628

fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv::fcoe_tgt_rsp_priv::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3629

fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv::fcoe_tgt_rsp_priv::r4_lo
__u8 r4_lo[2]
Definition: t4fw_interface.h:3631

fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv::fcoe_tgt_rsp_priv::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3630

fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv::iscsi_tgt_rsp_priv
Definition: t4fw_interface.h:3633

fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv::iscsi_tgt_rsp_priv::r4
__u8 r4[4]
Definition: t4fw_interface.h:3634

fw_scsi_tgt_rsp_wr
Definition: t4fw_interface.h:3621

fw_scsi_tgt_rsp_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3622

fw_scsi_tgt_rsp_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3623

fw_scsi_tgt_rsp_wr::u
union fw_scsi_tgt_rsp_wr::fw_scsi_tgt_rsp_priv u

fw_scsi_tgt_rsp_wr::r3
__u8 r3[2]
Definition: t4fw_interface.h:3626

fw_scsi_tgt_rsp_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3624

fw_scsi_tgt_rsp_wr::r5
__u8 r5[8]
Definition: t4fw_interface.h:3637

fw_scsi_tgt_rsp_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3625

fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv::fcoe_tgt_xmit_priv
Definition: t4fw_interface.h:3568

fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv::fcoe_tgt_xmit_priv::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3570

fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv::fcoe_tgt_xmit_priv::r3_lo
__u8 r3_lo[2]
Definition: t4fw_interface.h:3571

fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv::fcoe_tgt_xmit_priv::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3569

fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv::iscsi_tgt_xmit_priv
Definition: t4fw_interface.h:3573

fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv::iscsi_tgt_xmit_priv::r3
__u8 r3[4]
Definition: t4fw_interface.h:3574

fw_scsi_tgt_xmit_wr
Definition: t4fw_interface.h:3560

fw_scsi_tgt_xmit_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3562

fw_scsi_tgt_xmit_wr::auto_rsp
__u8 auto_rsp
Definition: t4fw_interface.h:3565

fw_scsi_tgt_xmit_wr::r4
__be32 r4
Definition: t4fw_interface.h:3578

fw_scsi_tgt_xmit_wr::r5
__be64 r5
Definition: t4fw_interface.h:3579

fw_scsi_tgt_xmit_wr::tot_xfer_len
__be32 tot_xfer_len
Definition: t4fw_interface.h:3581

fw_scsi_tgt_xmit_wr::r6
__be32 r6
Definition: t4fw_interface.h:3580

fw_scsi_tgt_xmit_wr::use_xfer_cnt
__u8 use_xfer_cnt
Definition: t4fw_interface.h:3566

fw_scsi_tgt_xmit_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3564

fw_scsi_tgt_xmit_wr::xfer_cnt
__be32 xfer_cnt
Definition: t4fw_interface.h:3577

fw_scsi_tgt_xmit_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3563

fw_scsi_tgt_xmit_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3561

fw_scsi_tgt_xmit_wr::u
union fw_scsi_tgt_xmit_wr::fw_scsi_tgt_xmit_priv u

fw_scsi_write_wr::fw_scsi_write_priv::fcoe_write_priv
Definition: t4fw_interface.h:3268

fw_scsi_write_wr::fw_scsi_write_priv::fcoe_write_priv::r3_lo
__u8 r3_lo[2]
Definition: t4fw_interface.h:3271

fw_scsi_write_wr::fw_scsi_write_priv::fcoe_write_priv::ctl_pri
__u8 ctl_pri
Definition: t4fw_interface.h:3269

fw_scsi_write_wr::fw_scsi_write_priv::fcoe_write_priv::cp_en_class
__u8 cp_en_class
Definition: t4fw_interface.h:3270

fw_scsi_write_wr::fw_scsi_write_priv::iscsi_write_priv
Definition: t4fw_interface.h:3273

fw_scsi_write_wr::fw_scsi_write_priv::iscsi_write_priv::r3
__u8 r3[4]
Definition: t4fw_interface.h:3274

fw_scsi_write_wr
Definition: t4fw_interface.h:3260

fw_scsi_write_wr::xfer_cnt
__be32 xfer_cnt
Definition: t4fw_interface.h:3277

fw_scsi_write_wr::rsp_dmalen
__be32 rsp_dmalen
Definition: t4fw_interface.h:3280

fw_scsi_write_wr::tmo_val
__u8 tmo_val
Definition: t4fw_interface.h:3265

fw_scsi_write_wr::r4
__be32 r4
Definition: t4fw_interface.h:3281

fw_scsi_write_wr::iqid
__be16 iqid
Definition: t4fw_interface.h:3264

fw_scsi_write_wr::op_immdlen
__be32 op_immdlen
Definition: t4fw_interface.h:3261

fw_scsi_write_wr::rsp_dmaaddr
__be64 rsp_dmaaddr
Definition: t4fw_interface.h:3279

fw_scsi_write_wr::u
union fw_scsi_write_wr::fw_scsi_write_priv u

fw_scsi_write_wr::cookie
__be64 cookie
Definition: t4fw_interface.h:3263

fw_scsi_write_wr::use_xfer_cnt
__u8 use_xfer_cnt
Definition: t4fw_interface.h:3266

fw_scsi_write_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3262

fw_scsi_write_wr::ini_xfer_cnt
__be32 ini_xfer_cnt
Definition: t4fw_interface.h:3278

fw_tls_tunnel_ofld_wr
Definition: t4fw_interface.h:4090

fw_tls_tunnel_ofld_wr::op_compl
__be32 op_compl
Definition: t4fw_interface.h:4091

fw_tls_tunnel_ofld_wr::r4
__be32 r4
Definition: t4fw_interface.h:4094

fw_tls_tunnel_ofld_wr::plen
__be32 plen
Definition: t4fw_interface.h:4093

fw_tls_tunnel_ofld_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:4092

fw_tlstx_data_wr
Definition: t4fw_interface.h:3831

fw_tlstx_data_wr::r10
__u8 r10
Definition: t4fw_interface.h:3842

fw_tlstx_data_wr::mfs
__be16 mfs
Definition: t4fw_interface.h:3838

fw_tlstx_data_wr::r5
__be32 r5
Definition: t4fw_interface.h:3836

fw_tlstx_data_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:3832

fw_tlstx_data_wr::expinplenmax_pkd
__be16 expinplenmax_pkd
Definition: t4fw_interface.h:3840

fw_tlstx_data_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:3833

fw_tlstx_data_wr::pdusinplenmax_pkd
__u8 pdusinplenmax_pkd
Definition: t4fw_interface.h:3841

fw_tlstx_data_wr::adjustedplen_pkd
__be16 adjustedplen_pkd
Definition: t4fw_interface.h:3839

fw_tlstx_data_wr::lsodisable_to_flags
__be32 lsodisable_to_flags
Definition: t4fw_interface.h:3835

fw_tlstx_data_wr::ctxloc_to_exp
__be32 ctxloc_to_exp
Definition: t4fw_interface.h:3837

fw_tlstx_data_wr::plen
__be32 plen
Definition: t4fw_interface.h:3834

fw_tp_wr
Definition: t4fw_interface.h:695

fw_tp_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:697

fw_tp_wr::op_to_immdlen
__be32 op_to_immdlen
Definition: t4fw_interface.h:696

fw_tp_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:698

fw_tx_pi_header
Definition: t4fw_interface.h:3727

fw_tx_pi_header::num_pi_dsg
__u8 num_pi_dsg
Definition: t4fw_interface.h:3733

fw_tx_pi_header::app_tag
__be16 app_tag
Definition: t4fw_interface.h:3734

fw_tx_pi_header::pi_start4_pi_end4
__be32 pi_start4_pi_end4
Definition: t4fw_interface.h:3731

fw_tx_pi_header::tag_gen_enabled_pkd
__u8 tag_gen_enabled_pkd
Definition: t4fw_interface.h:3732

fw_tx_pi_header::op_to_inline
__be16 op_to_inline
Definition: t4fw_interface.h:3728

fw_tx_pi_header::pi_interval_tag_type
__u8 pi_interval_tag_type
Definition: t4fw_interface.h:3729

fw_tx_pi_header::ref_tag
__be32 ref_tag
Definition: t4fw_interface.h:3735

fw_tx_pi_header::num_pi
__u8 num_pi
Definition: t4fw_interface.h:3730

fw_ulptx_wr
Definition: t4fw_interface.h:680

fw_ulptx_wr::op_to_compl
__be32 op_to_compl
Definition: t4fw_interface.h:681

fw_ulptx_wr::flowid_len16
__be32 flowid_len16
Definition: t4fw_interface.h:682

fw_ulptx_wr::cookie
__u64 cookie
Definition: t4fw_interface.h:683

fw_vi_cmd
Definition: t4fw_interface.h:6553

fw_vi_cmd::mac
__u8 mac[6]
Definition: t4fw_interface.h:6557

fw_vi_cmd::r9
__be64 r9
Definition: t4fw_interface.h:6567

fw_vi_cmd::nmac1
__u8 nmac1[6]
Definition: t4fw_interface.h:6562

fw_vi_cmd::nmac0
__u8 nmac0[6]
Definition: t4fw_interface.h:6560

fw_vi_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:6554

fw_vi_cmd::nmac3
__u8 nmac3[6]
Definition: t4fw_interface.h:6566

fw_vi_cmd::portid_pkd
__u8 portid_pkd
Definition: t4fw_interface.h:6558

fw_vi_cmd::nmac2
__u8 nmac2[6]
Definition: t4fw_interface.h:6564

fw_vi_cmd::type_to_viid
__be16 type_to_viid
Definition: t4fw_interface.h:6556

fw_vi_cmd::nmac
__u8 nmac
Definition: t4fw_interface.h:6559

fw_vi_cmd::norss_rsssize
__be16 norss_rsssize
Definition: t4fw_interface.h:6561

fw_vi_cmd::idseiq_pkd
__be16 idseiq_pkd
Definition: t4fw_interface.h:6565

fw_vi_cmd::idsiiq_pkd
__be16 idsiiq_pkd
Definition: t4fw_interface.h:6563

fw_vi_cmd::r10
__be64 r10
Definition: t4fw_interface.h:6568

fw_vi_cmd::alloc_to_len16
__be32 alloc_to_len16
Definition: t4fw_interface.h:6555

fw_vi_enable_cmd
Definition: t4fw_interface.h:6880

fw_vi_enable_cmd::ien_to_len16
__be32 ien_to_len16
Definition: t4fw_interface.h:6882

fw_vi_enable_cmd::blinkdur
__be16 blinkdur
Definition: t4fw_interface.h:6883

fw_vi_enable_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6881

fw_vi_enable_cmd::r4
__be32 r4
Definition: t4fw_interface.h:6885

fw_vi_enable_cmd::r3
__be16 r3
Definition: t4fw_interface.h:6884

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_exact
Definition: t4fw_interface.h:6691

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_exact::macaddr
__u8 macaddr[6]
Definition: t4fw_interface.h:6693

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_exact::valid_to_idx
__be16 valid_to_idx
Definition: t4fw_interface.h:6692

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_hash
Definition: t4fw_interface.h:6695

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_hash::hashvec
__be64 hashvec
Definition: t4fw_interface.h:6696

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw
Definition: t4fw_interface.h:6698

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw::data0_pkd
__be32 data0_pkd
Definition: t4fw_interface.h:6700

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw::data1m
__be32 data1m[2]
Definition: t4fw_interface.h:6703

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw::raw_idx_pkd
__be32 raw_idx_pkd
Definition: t4fw_interface.h:6699

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw::data0m_pkd
__be64 data0m_pkd
Definition: t4fw_interface.h:6702

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_raw::data1
__be32 data1[2]
Definition: t4fw_interface.h:6701

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni
Definition: t4fw_interface.h:6705

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni::macaddr
__u8 macaddr[6]
Definition: t4fw_interface.h:6707

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni::valid_to_idx
__be16 valid_to_idx
Definition: t4fw_interface.h:6706

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni::r7
__be16 r7
Definition: t4fw_interface.h:6708

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni::macaddr_mask
__u8 macaddr_mask[6]
Definition: t4fw_interface.h:6709

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni::lookup_type_to_vni
__be32 lookup_type_to_vni
Definition: t4fw_interface.h:6710

fw_vi_mac_cmd::fw_vi_mac::fw_vi_mac_vni::vni_mask_pkd
__be32 vni_mask_pkd
Definition: t4fw_interface.h:6711

fw_vi_mac_cmd
Definition: t4fw_interface.h:6687

fw_vi_mac_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6688

fw_vi_mac_cmd::freemacs_to_len16
__be32 freemacs_to_len16
Definition: t4fw_interface.h:6689

fw_vi_mac_cmd::u
union fw_vi_mac_cmd::fw_vi_mac u

fw_vi_rxmode_cmd
Definition: t4fw_interface.h:6835

fw_vi_rxmode_cmd::r4_lo
__be32 r4_lo
Definition: t4fw_interface.h:6839

fw_vi_rxmode_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:6837

fw_vi_rxmode_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6836

fw_vi_rxmode_cmd::mtu_to_vlanexen
__be32 mtu_to_vlanexen
Definition: t4fw_interface.h:6838

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl
Definition: t4fw_interface.h:6969

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::nstats_ix
__be16 nstats_ix
Definition: t4fw_interface.h:6970

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::stat0
__be64 stat0
Definition: t4fw_interface.h:6973

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::stat2
__be64 stat2
Definition: t4fw_interface.h:6975

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::stat3
__be64 stat3
Definition: t4fw_interface.h:6976

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::r7
__be32 r7
Definition: t4fw_interface.h:6972

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::stat4
__be64 stat4
Definition: t4fw_interface.h:6977

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::r6
__be16 r6
Definition: t4fw_interface.h:6971

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::stat1
__be64 stat1
Definition: t4fw_interface.h:6974

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_ctl::stat5
__be64 stat5
Definition: t4fw_interface.h:6978

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf
Definition: t4fw_interface.h:6980

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_mcast_frames
__be64 rx_mcast_frames
Definition: t4fw_interface.h:6994

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_bcast_bytes
__be64 rx_bcast_bytes
Definition: t4fw_interface.h:6991

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_ucast_frames
__be64 tx_ucast_frames
Definition: t4fw_interface.h:6986

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_mcast_frames
__be64 tx_mcast_frames
Definition: t4fw_interface.h:6984

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_pf_bytes
__be64 rx_pf_bytes
Definition: t4fw_interface.h:6989

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_mcast_bytes
__be64 tx_mcast_bytes
Definition: t4fw_interface.h:6983

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_ucast_bytes
__be64 rx_ucast_bytes
Definition: t4fw_interface.h:6995

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_mcast_bytes
__be64 rx_mcast_bytes
Definition: t4fw_interface.h:6993

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_bcast_frames
__be64 tx_bcast_frames
Definition: t4fw_interface.h:6982

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_offload_bytes
__be64 tx_offload_bytes
Definition: t4fw_interface.h:6987

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_ucast_bytes
__be64 tx_ucast_bytes
Definition: t4fw_interface.h:6985

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_bcast_frames
__be64 rx_bcast_frames
Definition: t4fw_interface.h:6992

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_ucast_frames
__be64 rx_ucast_frames
Definition: t4fw_interface.h:6996

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_err_frames
__be64 rx_err_frames
Definition: t4fw_interface.h:6997

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_bcast_bytes
__be64 tx_bcast_bytes
Definition: t4fw_interface.h:6981

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::rx_pf_frames
__be64 rx_pf_frames
Definition: t4fw_interface.h:6990

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_pf::tx_offload_frames
__be64 tx_offload_frames
Definition: t4fw_interface.h:6988

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf
Definition: t4fw_interface.h:6999

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_mcast_bytes
__be64 rx_mcast_bytes
Definition: t4fw_interface.h:7011

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_bcast_frames
__be64 rx_bcast_frames
Definition: t4fw_interface.h:7010

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_bcast_bytes
__be64 tx_bcast_bytes
Definition: t4fw_interface.h:7000

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_ucast_bytes
__be64 rx_ucast_bytes
Definition: t4fw_interface.h:7013

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_ucast_frames
__be64 tx_ucast_frames
Definition: t4fw_interface.h:7005

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_bcast_bytes
__be64 rx_bcast_bytes
Definition: t4fw_interface.h:7009

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_ucast_bytes
__be64 tx_ucast_bytes
Definition: t4fw_interface.h:7004

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_mcast_frames
__be64 tx_mcast_frames
Definition: t4fw_interface.h:7003

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_bcast_frames
__be64 tx_bcast_frames
Definition: t4fw_interface.h:7001

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_ucast_frames
__be64 rx_ucast_frames
Definition: t4fw_interface.h:7014

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_drop_frames
__be64 tx_drop_frames
Definition: t4fw_interface.h:7006

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_err_frames
__be64 rx_err_frames
Definition: t4fw_interface.h:7015

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_offload_frames
__be64 tx_offload_frames
Definition: t4fw_interface.h:7008

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_mcast_bytes
__be64 tx_mcast_bytes
Definition: t4fw_interface.h:7002

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::rx_mcast_frames
__be64 rx_mcast_frames
Definition: t4fw_interface.h:7012

fw_vi_stats_cmd::fw_vi_stats::fw_vi_stats_vf::tx_offload_bytes
__be64 tx_offload_bytes
Definition: t4fw_interface.h:7007

fw_vi_stats_cmd
Definition: t4fw_interface.h:6965

fw_vi_stats_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:6967

fw_vi_stats_cmd::op_to_viid
__be32 op_to_viid
Definition: t4fw_interface.h:6966

fw_vi_stats_cmd::u
union fw_vi_stats_cmd::fw_vi_stats u

fw_watchdog_cmd
Definition: t4fw_interface.h:8895

fw_watchdog_cmd::action
__be32 action
Definition: t4fw_interface.h:8899

fw_watchdog_cmd::timeout
__be32 timeout
Definition: t4fw_interface.h:8898

fw_watchdog_cmd::retval_len16
__be32 retval_len16
Definition: t4fw_interface.h:8897

fw_watchdog_cmd::op_to_vfn
__be32 op_to_vfn
Definition: t4fw_interface.h:8896

fw_wr_hdr
Definition: t4fw_interface.h:160

fw_wr_hdr::lo
__be32 lo
Definition: t4fw_interface.h:162

fw_wr_hdr::hi
__be32 hi
Definition: t4fw_interface.h:161

sge
Definition: adapter.h:821

fw_pi_error_type
fw_pi_error_type
Definition: t4fw_interface.h:3812

FW_PI_ERROR_GUARD_CHECK_FAILED
@ FW_PI_ERROR_GUARD_CHECK_FAILED
Definition: t4fw_interface.h:3813

fw_port_l2cfg_ctlbf
fw_port_l2cfg_ctlbf
Definition: t4fw_interface.h:7322

FW_PORT_L2_CTLBF_OVLAN2
@ FW_PORT_L2_CTLBF_OVLAN2
Definition: t4fw_interface.h:7325

FW_PORT_L2_CTLBF_TXIPG
@ FW_PORT_L2_CTLBF_TXIPG
Definition: t4fw_interface.h:7328

FW_PORT_L2_CTLBF_OVLAN0
@ FW_PORT_L2_CTLBF_OVLAN0
Definition: t4fw_interface.h:7323

FW_PORT_L2_CTLBF_OVLAN3
@ FW_PORT_L2_CTLBF_OVLAN3
Definition: t4fw_interface.h:7326

FW_PORT_L2_CTLBF_MTU
@ FW_PORT_L2_CTLBF_MTU
Definition: t4fw_interface.h:7329

FW_PORT_L2_CTLBF_IVLAN
@ FW_PORT_L2_CTLBF_IVLAN
Definition: t4fw_interface.h:7327

FW_PORT_L2_CTLBF_OVLAN1
@ FW_PORT_L2_CTLBF_OVLAN1
Definition: t4fw_interface.h:7324

FW_PORT_L2_CTLBF_OVLAN_FILT
@ FW_PORT_L2_CTLBF_OVLAN_FILT
Definition: t4fw_interface.h:7330

fw_eth_tx_eo_type
fw_eth_tx_eo_type
Definition: t4fw_interface.h:792

FW_ETH_TX_EO_TYPE_NVGRESEG
@ FW_ETH_TX_EO_TYPE_NVGRESEG
Definition: t4fw_interface.h:795

FW_ETH_TX_EO_TYPE_VXLANSEG
@ FW_ETH_TX_EO_TYPE_VXLANSEG
Definition: t4fw_interface.h:796

FW_ETH_TX_EO_TYPE_TCPSEG
@ FW_ETH_TX_EO_TYPE_TCPSEG
Definition: t4fw_interface.h:794

FW_ETH_TX_EO_TYPE_GENEVESEG
@ FW_ETH_TX_EO_TYPE_GENEVESEG
Definition: t4fw_interface.h:797

FW_ETH_TX_EO_TYPE_UDPSEG
@ FW_ETH_TX_EO_TYPE_UDPSEG
Definition: t4fw_interface.h:793

fw_iq_type
fw_iq_type
Definition: t4fw_interface.h:5201

FW_IQ_TYPE_VF_CQ
@ FW_IQ_TYPE_VF_CQ
Definition: t4fw_interface.h:5204

FW_IQ_TYPE_NO_FL_INT_CAP
@ FW_IQ_TYPE_NO_FL_INT_CAP
Definition: t4fw_interface.h:5203

FW_IQ_TYPE_FL_INT_CAP
@ FW_IQ_TYPE_FL_INT_CAP
Definition: t4fw_interface.h:5202

fw_retval
fw_retval
Definition: t4fw_interface.h:37

FW_SCSI_CLOSE_REQUESTED
@ FW_SCSI_CLOSE_REQUESTED
Definition: t4fw_interface.h:64

FW_EADDRNOTAVAIL
@ FW_EADDRNOTAVAIL
Definition: t4fw_interface.h:55

FW_ENODEV
@ FW_ENODEV
Definition: t4fw_interface.h:48

FW_EADDRINUSE
@ FW_EADDRINUSE
Definition: t4fw_interface.h:54

FW_ENOMEM
@ FW_ENOMEM
Definition: t4fw_interface.h:44

FW_EINPROGRESS
@ FW_EINPROGRESS
Definition: t4fw_interface.h:60

FW_ERR_LINK_DOWN
@ FW_ERR_LINK_DOWN
Definition: t4fw_interface.h:65

FW_ENOBUFS
@ FW_ENOBUFS
Definition: t4fw_interface.h:58

FW_ENOEXEC
@ FW_ENOEXEC
Definition: t4fw_interface.h:42

FW_SCSI_ABORT_REQUESTED
@ FW_SCSI_ABORT_REQUESTED
Definition: t4fw_interface.h:61

FW_ENETDOWN
@ FW_ENETDOWN
Definition: t4fw_interface.h:56

FW_SCSI_UNDER_FLOW_ERR
@ FW_SCSI_UNDER_FLOW_ERR
Definition: t4fw_interface.h:72

FW_ERR_RDEV_LOGO
@ FW_ERR_RDEV_LOGO
Definition: t4fw_interface.h:68

FW_SCSI_ABORTED
@ FW_SCSI_ABORTED
Definition: t4fw_interface.h:63

FW_ETIMEDOUT
@ FW_ETIMEDOUT
Definition: t4fw_interface.h:59

FW_EINVAL
@ FW_EINVAL
Definition: t4fw_interface.h:49

FW_EIO
@ FW_EIO
Definition: t4fw_interface.h:41

FW_ENOSYS
@ FW_ENOSYS
Definition: t4fw_interface.h:51

FW_EEXIST
@ FW_EEXIST
Definition: t4fw_interface.h:47

FW_ERR_RDEV_LOST
@ FW_ERR_RDEV_LOST
Definition: t4fw_interface.h:67

FW_SUCCESS
@ FW_SUCCESS
Definition: t4fw_interface.h:38

FW_EAGAIN
@ FW_EAGAIN
Definition: t4fw_interface.h:43

FW_SCSI_ABORT_TIMEDOUT
@ FW_SCSI_ABORT_TIMEDOUT
Definition: t4fw_interface.h:62

FW_EPROTO
@ FW_EPROTO
Definition: t4fw_interface.h:53

FW_ENETUNREACH
@ FW_ENETUNREACH
Definition: t4fw_interface.h:57

FW_ENODATA
@ FW_ENODATA
Definition: t4fw_interface.h:52

FW_EPERM
@ FW_EPERM
Definition: t4fw_interface.h:39

FW_EFAULT
@ FW_EFAULT
Definition: t4fw_interface.h:45

FW_SCSI_TASK_ERR
@ FW_SCSI_TASK_ERR
Definition: t4fw_interface.h:75

FW_SCSI_IO_BLOCK
@ FW_SCSI_IO_BLOCK
Definition: t4fw_interface.h:76

FW_FCOE_NO_XCHG
@ FW_FCOE_NO_XCHG
Definition: t4fw_interface.h:69

FW_SCSI_DDP_ERR
@ FW_SCSI_DDP_ERR
Definition: t4fw_interface.h:74

FW_ENOENT
@ FW_ENOENT
Definition: t4fw_interface.h:40

FW_ENOSPC
@ FW_ENOSPC
Definition: t4fw_interface.h:50

FW_SCSI_OVER_FLOW_ERR
@ FW_SCSI_OVER_FLOW_ERR
Definition: t4fw_interface.h:73

FW_EBUSY
@ FW_EBUSY
Definition: t4fw_interface.h:46

FW_SCSI_RSP_ERR
@ FW_SCSI_RSP_ERR
Definition: t4fw_interface.h:70

FW_ERR_RDEV_IMPL_LOGO
@ FW_ERR_RDEV_IMPL_LOGO
Definition: t4fw_interface.h:71

FW_RDEV_NOT_READY
@ FW_RDEV_NOT_READY
Definition: t4fw_interface.h:66

fw_sched_params_unit
fw_sched_params_unit
Definition: t4fw_interface.h:8747

FW_SCHED_PARAMS_UNIT_PKTRATE
@ FW_SCHED_PARAMS_UNIT_PKTRATE
Definition: t4fw_interface.h:8749

FW_SCHED_PARAMS_UNIT_BITRATE
@ FW_SCHED_PARAMS_UNIT_BITRATE
Definition: t4fw_interface.h:8748

fw_port_dcb_cfg_rc
fw_port_dcb_cfg_rc
Definition: t4fw_interface.h:7354

FW_PORT_DCB_CFG_SUCCESS
@ FW_PORT_DCB_CFG_SUCCESS
Definition: t4fw_interface.h:7355

FW_PORT_DCB_CFG_ERROR
@ FW_PORT_DCB_CFG_ERROR
Definition: t4fw_interface.h:7356

fw_ri_data_op
fw_ri_data_op
Definition: t4fw_interface.h:1274

FW_RI_DATA_IMMD
@ FW_RI_DATA_IMMD
Definition: t4fw_interface.h:1275

FW_RI_DATA_DSGL
@ FW_RI_DATA_DSGL
Definition: t4fw_interface.h:1276

FW_RI_DATA_ISGL
@ FW_RI_DATA_ISGL
Definition: t4fw_interface.h:1277

FW_DEVLOG_FMT_PARAMS_NUM
#define FW_DEVLOG_FMT_PARAMS_NUM
Definition: t4fw_interface.h:8796

fw_params_param_dev_diag
fw_params_param_dev_diag
Definition: t4fw_interface.h:4869

FW_PARAM_DEV_DIAG_VDD
@ FW_PARAM_DEV_DIAG_VDD
Definition: t4fw_interface.h:4871

FW_PARAM_DEV_DIAG_TMP
@ FW_PARAM_DEV_DIAG_TMP
Definition: t4fw_interface.h:4870

FW_PARAM_DEV_DIAG_MAXTMPTHRESH
@ FW_PARAM_DEV_DIAG_MAXTMPTHRESH
Definition: t4fw_interface.h:4872

FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR
@ FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR
Definition: t4fw_interface.h:4873

fw_port_link_dn_rc
fw_port_link_dn_rc
Definition: t4fw_interface.h:7855

FW_PORT_LINK_DN_RESERVED7
@ FW_PORT_LINK_DN_RESERVED7
Definition: t4fw_interface.h:7863

FW_PORT_LINK_DN_OVERHEAT
@ FW_PORT_LINK_DN_OVERHEAT
Definition: t4fw_interface.h:7860

FW_PORT_LINK_DN_RC_REMFLT
@ FW_PORT_LINK_DN_RC_REMFLT
Definition: t4fw_interface.h:7857

FW_PORT_LINK_DN_ANEG_F
@ FW_PORT_LINK_DN_ANEG_F
Definition: t4fw_interface.h:7858

FW_PORT_LINK_DN_RESERVED3
@ FW_PORT_LINK_DN_RESERVED3
Definition: t4fw_interface.h:7859

FW_PORT_LINK_DN_RX_LOS
@ FW_PORT_LINK_DN_RX_LOS
Definition: t4fw_interface.h:7862

FW_PORT_LINK_DN_RC_NONE
@ FW_PORT_LINK_DN_RC_NONE
Definition: t4fw_interface.h:7856

FW_PORT_LINK_DN_UNKNOWN
@ FW_PORT_LINK_DN_UNKNOWN
Definition: t4fw_interface.h:7861

fw_params_param_dev_phyfw
fw_params_param_dev_phyfw
Definition: t4fw_interface.h:4864

FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
@ FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD
Definition: t4fw_interface.h:4865

FW_PARAMS_PARAM_DEV_PHYFW_VERSION
@ FW_PARAMS_PARAM_DEV_PHYFW_VERSION
Definition: t4fw_interface.h:4866

fw_caps_config_nic
fw_caps_config_nic
Definition: t4fw_interface.h:4658

FW_CAPS_CONFIG_NIC
@ FW_CAPS_CONFIG_NIC
Definition: t4fw_interface.h:4659

FW_CAPS_CONFIG_NIC_HASHFILTER
@ FW_CAPS_CONFIG_NIC_HASHFILTER
Definition: t4fw_interface.h:4664

FW_CAPS_CONFIG_NIC_UM_ISGL
@ FW_CAPS_CONFIG_NIC_UM_ISGL
Definition: t4fw_interface.h:4663

FW_CAPS_CONFIG_NIC_ETHOFLD
@ FW_CAPS_CONFIG_NIC_ETHOFLD
Definition: t4fw_interface.h:4665

FW_CAPS_CONFIG_NIC_VM
@ FW_CAPS_CONFIG_NIC_VM
Definition: t4fw_interface.h:4660

FW_CAPS_CONFIG_NIC_IDS
@ FW_CAPS_CONFIG_NIC_IDS
Definition: t4fw_interface.h:4661

FW_CAPS_CONFIG_NIC_UM
@ FW_CAPS_CONFIG_NIC_UM
Definition: t4fw_interface.h:4662

fw_filter_wr_cookie
fw_filter_wr_cookie
Definition: t4fw_interface.h:303

FW_FILTER_WR_SMT_TBL_FULL
@ FW_FILTER_WR_SMT_TBL_FULL
Definition: t4fw_interface.h:307

FW_FILTER_WR_SUCCESS
@ FW_FILTER_WR_SUCCESS
Definition: t4fw_interface.h:304

FW_FILTER_WR_EINVAL
@ FW_FILTER_WR_EINVAL
Definition: t4fw_interface.h:308

FW_FILTER_WR_FLT_DELETED
@ FW_FILTER_WR_FLT_DELETED
Definition: t4fw_interface.h:306

FW_FILTER_WR_FLT_ADDED
@ FW_FILTER_WR_FLT_ADDED
Definition: t4fw_interface.h:305

fw_diag_cmd_ofldiag_op
fw_diag_cmd_ofldiag_op
Definition: t4fw_interface.h:9669

FW_DIAG_CMD_OFLDIAG_TEST_START
@ FW_DIAG_CMD_OFLDIAG_TEST_START
Definition: t4fw_interface.h:9671

FW_DIAG_CMD_OFLDIAG_TEST_STATUS
@ FW_DIAG_CMD_OFLDIAG_TEST_STATUS
Definition: t4fw_interface.h:9673

FW_DIAG_CMD_OFLDIAG_TEST_NONE
@ FW_DIAG_CMD_OFLDIAG_TEST_NONE
Definition: t4fw_interface.h:9670

FW_DIAG_CMD_OFLDIAG_TEST_STOP
@ FW_DIAG_CMD_OFLDIAG_TEST_STOP
Definition: t4fw_interface.h:9672

fw_foiscsi_wr_subop
fw_foiscsi_wr_subop
Definition: t4fw_interface.h:2309

FW_FOISCSI_WR_SUBOP_MOD
@ FW_FOISCSI_WR_SUBOP_MOD
Definition: t4fw_interface.h:2312

FW_FOISCSI_WR_SUBOP_ADD
@ FW_FOISCSI_WR_SUBOP_ADD
Definition: t4fw_interface.h:2310

FW_FOISCSI_WR_SUBOP_DEL
@ FW_FOISCSI_WR_SUBOP_DEL
Definition: t4fw_interface.h:2311

fw_filter_wr_nat_mode
fw_filter_wr_nat_mode
Definition: t4fw_interface.h:311

FW_FILTER_WR_NATMODE_FOURTUPLE
@ FW_FILTER_WR_NATMODE_FOURTUPLE
Definition: t4fw_interface.h:319

FW_FILTER_WR_NATMODE_SIPSP
@ FW_FILTER_WR_NATMODE_SIPSP
Definition: t4fw_interface.h:317

FW_FILTER_WR_NATMODE_DIPSIPSP
@ FW_FILTER_WR_NATMODE_DIPSIPSP
Definition: t4fw_interface.h:318

FW_FILTER_WR_NATMODE_DIPDP
@ FW_FILTER_WR_NATMODE_DIPDP
Definition: t4fw_interface.h:314

FW_FILTER_WR_NATMODE_DIP
@ FW_FILTER_WR_NATMODE_DIP
Definition: t4fw_interface.h:313

FW_FILTER_WR_NATMODE_DIPDPSIP
@ FW_FILTER_WR_NATMODE_DIPDPSIP
Definition: t4fw_interface.h:315

FW_FILTER_WR_NATMODE_NONE
@ FW_FILTER_WR_NATMODE_NONE
Definition: t4fw_interface.h:312

FW_FILTER_WR_NATMODE_DIPDPSP
@ FW_FILTER_WR_NATMODE_DIPDPSP
Definition: t4fw_interface.h:316

fw_devlog_level
fw_devlog_level
Definition: t4fw_interface.h:8801

FW_DEVLOG_LEVEL_MAX
@ FW_DEVLOG_LEVEL_MAX
Definition: t4fw_interface.h:8808

FW_DEVLOG_LEVEL_INFO
@ FW_DEVLOG_LEVEL_INFO
Definition: t4fw_interface.h:8806

FW_DEVLOG_LEVEL_DEBUG
@ FW_DEVLOG_LEVEL_DEBUG
Definition: t4fw_interface.h:8807

FW_DEVLOG_LEVEL_NOTICE
@ FW_DEVLOG_LEVEL_NOTICE
Definition: t4fw_interface.h:8805

FW_DEVLOG_LEVEL_EMERG
@ FW_DEVLOG_LEVEL_EMERG
Definition: t4fw_interface.h:8802

FW_DEVLOG_LEVEL_ERR
@ FW_DEVLOG_LEVEL_ERR
Definition: t4fw_interface.h:8804

FW_DEVLOG_LEVEL_CRIT
@ FW_DEVLOG_LEVEL_CRIT
Definition: t4fw_interface.h:8803

fw_ri_wr_flags
fw_ri_wr_flags
Definition: t4fw_interface.h:1227

FW_RI_SOLICITED_EVENT_FLAG
@ FW_RI_SOLICITED_EVENT_FLAG
Definition: t4fw_interface.h:1230

FW_RI_LOCAL_FENCE_FLAG
@ FW_RI_LOCAL_FENCE_FLAG
Definition: t4fw_interface.h:1232

FW_RI_RDMA_READ_INVALIDATE
@ FW_RI_RDMA_READ_INVALIDATE
Definition: t4fw_interface.h:1233

FW_RI_NOTIFICATION_FLAG
@ FW_RI_NOTIFICATION_FLAG
Definition: t4fw_interface.h:1229

FW_RI_READ_FENCE_FLAG
@ FW_RI_READ_FENCE_FLAG
Definition: t4fw_interface.h:1231

FW_RI_COMPLETION_FLAG
@ FW_RI_COMPLETION_FLAG
Definition: t4fw_interface.h:1228

FW_RI_RDMA_WRITE_WITH_IMMEDIATE
@ FW_RI_RDMA_WRITE_WITH_IMMEDIATE
Definition: t4fw_interface.h:1234

fw_chnet_iface_cmd_subop
fw_chnet_iface_cmd_subop
Definition: t4fw_interface.h:8958

FW_CHNET_IFACE_CMD_SUBOP_NOOP
@ FW_CHNET_IFACE_CMD_SUBOP_NOOP
Definition: t4fw_interface.h:8959

FW_CHNET_IFACE_CMD_SUBOP_MAX
@ FW_CHNET_IFACE_CMD_SUBOP_MAX
Definition: t4fw_interface.h:8967

FW_CHNET_IFACE_CMD_SUBOP_LINK_UP
@ FW_CHNET_IFACE_CMD_SUBOP_LINK_UP
Definition: t4fw_interface.h:8961

FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN
@ FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN
Definition: t4fw_interface.h:8962

FW_CHNET_IFACE_CMD_SUBOP_MTU_GET
@ FW_CHNET_IFACE_CMD_SUBOP_MTU_GET
Definition: t4fw_interface.h:8965

FW_CHNET_IFACE_CMD_SUBOP_MTU_SET
@ FW_CHNET_IFACE_CMD_SUBOP_MTU_SET
Definition: t4fw_interface.h:8964

fw_diag_cmd_ofldiag_status
fw_diag_cmd_ofldiag_status
Definition: t4fw_interface.h:9676

FW_DIAG_CMD_OFLDIAG_STATUS_PASSED
@ FW_DIAG_CMD_OFLDIAG_STATUS_PASSED
Definition: t4fw_interface.h:9680

FW_DIAG_CMD_OFLDIAG_STATUS_FAILED
@ FW_DIAG_CMD_OFLDIAG_STATUS_FAILED
Definition: t4fw_interface.h:9679

FW_DIAG_CMD_OFLDIAG_STATUS_IDLE
@ FW_DIAG_CMD_OFLDIAG_STATUS_IDLE
Definition: t4fw_interface.h:9677

FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING
@ FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING
Definition: t4fw_interface.h:9678

fw_memtype_cf
fw_memtype_cf
Definition: t4fw_interface.h:4704

FW_MEMTYPE_CF_EXTMEM1
@ FW_MEMTYPE_CF_EXTMEM1
Definition: t4fw_interface.h:4710

FW_MEMTYPE_CF_FLASH
@ FW_MEMTYPE_CF_FLASH
Definition: t4fw_interface.h:4708

FW_MEMTYPE_CF_EDC0
@ FW_MEMTYPE_CF_EDC0
Definition: t4fw_interface.h:4705

FW_MEMTYPE_CF_EXTMEM
@ FW_MEMTYPE_CF_EXTMEM
Definition: t4fw_interface.h:4707

FW_MEMTYPE_CF_INTERNAL
@ FW_MEMTYPE_CF_INTERNAL
Definition: t4fw_interface.h:4709

FW_MEMTYPE_CF_EDC1
@ FW_MEMTYPE_CF_EDC1
Definition: t4fw_interface.h:4706

pcie_fw_eval
pcie_fw_eval
Definition: t4fw_interface.h:9793

PCIE_FW_EVAL_DEVICESHUTDOWN
@ PCIE_FW_EVAL_DEVICESHUTDOWN
Definition: t4fw_interface.h:9800

PCIE_FW_EVAL_INIT
@ PCIE_FW_EVAL_INIT
Definition: t4fw_interface.h:9797

PCIE_FW_EVAL_PREP
@ PCIE_FW_EVAL_PREP
Definition: t4fw_interface.h:9795

PCIE_FW_EVAL_CRASH
@ PCIE_FW_EVAL_CRASH
Definition: t4fw_interface.h:9794

PCIE_FW_EVAL_CONF
@ PCIE_FW_EVAL_CONF
Definition: t4fw_interface.h:9796

PCIE_FW_EVAL_OVERHEAT
@ PCIE_FW_EVAL_OVERHEAT
Definition: t4fw_interface.h:9799

PCIE_FW_EVAL_UNEXPECTEDEVENT
@ PCIE_FW_EVAL_UNEXPECTEDEVENT
Definition: t4fw_interface.h:9798

fec_supported
static bool fec_supported(uint32_t caps)
Definition: t4fw_interface.h:7286

fw_params_param_chnet
fw_params_param_chnet
Definition: t4fw_interface.h:4992

FW_PARAMS_PARAM_CHNET_FLAGS
@ FW_PARAMS_PARAM_CHNET_FLAGS
Definition: t4fw_interface.h:4993

fw_caps_config_fcoe
fw_caps_config_fcoe
Definition: t4fw_interface.h:4696

FW_CAPS_CONFIG_POFCOE_INITIATOR
@ FW_CAPS_CONFIG_POFCOE_INITIATOR
Definition: t4fw_interface.h:4700

FW_CAPS_CONFIG_FCOE_INITIATOR
@ FW_CAPS_CONFIG_FCOE_INITIATOR
Definition: t4fw_interface.h:4697

FW_CAPS_CONFIG_FCOE_CTRL_OFLD
@ FW_CAPS_CONFIG_FCOE_CTRL_OFLD
Definition: t4fw_interface.h:4699

FW_CAPS_CONFIG_POFCOE_TARGET
@ FW_CAPS_CONFIG_POFCOE_TARGET
Definition: t4fw_interface.h:4701

FW_CAPS_CONFIG_FCOE_TARGET
@ FW_CAPS_CONFIG_FCOE_TARGET
Definition: t4fw_interface.h:4698

fw_caps_config_crypto
fw_caps_config_crypto
Definition: t4fw_interface.h:4689

FW_CAPS_CONFIG_TLS_HW
@ FW_CAPS_CONFIG_TLS_HW
Definition: t4fw_interface.h:4693

FW_CAPS_CONFIG_TLSKEYS
@ FW_CAPS_CONFIG_TLSKEYS
Definition: t4fw_interface.h:4691

FW_CAPS_CONFIG_CRYPTO_LOOKASIDE
@ FW_CAPS_CONFIG_CRYPTO_LOOKASIDE
Definition: t4fw_interface.h:4690

FW_CAPS_CONFIG_IPSEC_INLINE
@ FW_CAPS_CONFIG_IPSEC_INLINE
Definition: t4fw_interface.h:4692

FW_HELLO_CMD_STAGE_POSTOS
@ FW_HELLO_CMD_STAGE_POSTOS
Definition: t4fw_interface.h:4511

FW_HELLO_CMD_STAGE_PREOS0
@ FW_HELLO_CMD_STAGE_PREOS0
Definition: t4fw_interface.h:4509

FW_HELLO_CMD_STAGE_OS
@ FW_HELLO_CMD_STAGE_OS
Definition: t4fw_interface.h:4508

FW_HELLO_CMD_STAGE_PREOS1
@ FW_HELLO_CMD_STAGE_PREOS1
Definition: t4fw_interface.h:4510

fw_ldst_addrspc
fw_ldst_addrspc
Definition: t4fw_interface.h:4237

FW_LDST_ADDRSPC_SGE_INGC
@ FW_LDST_ADDRSPC_SGE_INGC
Definition: t4fw_interface.h:4240

FW_LDST_ADDRSPC_PCIE_CFGS
@ FW_LDST_ADDRSPC_PCIE_CFGS
Definition: t4fw_interface.h:4253

FW_LDST_ADDRSPC_LE
@ FW_LDST_ADDRSPC_LE
Definition: t4fw_interface.h:4251

FW_LDST_ADDRSPC_SGE_CONMC
@ FW_LDST_ADDRSPC_SGE_CONMC
Definition: t4fw_interface.h:4242

FW_LDST_ADDRSPC_SGE_FLMC
@ FW_LDST_ADDRSPC_SGE_FLMC
Definition: t4fw_interface.h:4241

FW_LDST_ADDRSPC_CIM_Q
@ FW_LDST_ADDRSPC_CIM_Q
Definition: t4fw_interface.h:4256

FW_LDST_ADDRSPC_FUNC_I2C
@ FW_LDST_ADDRSPC_FUNC_I2C
Definition: t4fw_interface.h:4250

FW_LDST_ADDRSPC_SGE_EGRC
@ FW_LDST_ADDRSPC_SGE_EGRC
Definition: t4fw_interface.h:4239

FW_LDST_ADDRSPC_MPS
@ FW_LDST_ADDRSPC_MPS
Definition: t4fw_interface.h:4247

FW_LDST_ADDRSPC_MDIO
@ FW_LDST_ADDRSPC_MDIO
Definition: t4fw_interface.h:4246

FW_LDST_ADDRSPC_PCIE_PHY
@ FW_LDST_ADDRSPC_PCIE_PHY
Definition: t4fw_interface.h:4255

FW_LDST_ADDRSPC_TP_TM_PIO
@ FW_LDST_ADDRSPC_TP_TM_PIO
Definition: t4fw_interface.h:4244

FW_LDST_ADDRSPC_FUNC
@ FW_LDST_ADDRSPC_FUNC
Definition: t4fw_interface.h:4248

FW_LDST_ADDRSPC_FUNC_PCIE
@ FW_LDST_ADDRSPC_FUNC_PCIE
Definition: t4fw_interface.h:4249

FW_LDST_ADDRSPC_TP_MIB
@ FW_LDST_ADDRSPC_TP_MIB
Definition: t4fw_interface.h:4245

FW_LDST_ADDRSPC_PCIE_DBG
@ FW_LDST_ADDRSPC_PCIE_DBG
Definition: t4fw_interface.h:4254

FW_LDST_ADDRSPC_TP_PIO
@ FW_LDST_ADDRSPC_TP_PIO
Definition: t4fw_interface.h:4243

FW_LDST_ADDRSPC_FIRMWARE
@ FW_LDST_ADDRSPC_FIRMWARE
Definition: t4fw_interface.h:4238

FW_LDST_ADDRSPC_I2C
@ FW_LDST_ADDRSPC_I2C
Definition: t4fw_interface.h:4252

fw_port_cap
fw_port_cap
Definition: t4fw_interface.h:7129

FW_PORT_CAP_ANEG
@ FW_PORT_CAP_ANEG
Definition: t4fw_interface.h:7138

FW_PORT_CAP_SPEED_100M
@ FW_PORT_CAP_SPEED_100M
Definition: t4fw_interface.h:7130

FW_PORT_CAP_FC_RX
@ FW_PORT_CAP_FC_RX
Definition: t4fw_interface.h:7136

FW_PORT_CAP_SPEED_40G
@ FW_PORT_CAP_SPEED_40G
Definition: t4fw_interface.h:7134

FW_PORT_CAP_SPEED_10G
@ FW_PORT_CAP_SPEED_10G
Definition: t4fw_interface.h:7133

FW_PORT_CAP_802_3_ASM_DIR
@ FW_PORT_CAP_802_3_ASM_DIR
Definition: t4fw_interface.h:7145

FW_PORT_CAP_FEC_BASER_RS
@ FW_PORT_CAP_FEC_BASER_RS
Definition: t4fw_interface.h:7142

FW_PORT_CAP_FC_TX
@ FW_PORT_CAP_FC_TX
Definition: t4fw_interface.h:7137

FW_PORT_CAP_SPEED_1G
@ FW_PORT_CAP_SPEED_1G
Definition: t4fw_interface.h:7131

FW_PORT_CAP_802_3_PAUSE
@ FW_PORT_CAP_802_3_PAUSE
Definition: t4fw_interface.h:7144

FW_PORT_CAP_FORCE_PAUSE
@ FW_PORT_CAP_FORCE_PAUSE
Definition: t4fw_interface.h:7143

FW_PORT_CAP_MDIAUTO
@ FW_PORT_CAP_MDIAUTO
Definition: t4fw_interface.h:7139

FW_PORT_CAP_SPEED_25G
@ FW_PORT_CAP_SPEED_25G
Definition: t4fw_interface.h:7132

FW_PORT_CAP_MDISTRAIGHT
@ FW_PORT_CAP_MDISTRAIGHT
Definition: t4fw_interface.h:7140

FW_PORT_CAP_FEC_RS
@ FW_PORT_CAP_FEC_RS
Definition: t4fw_interface.h:7141

FW_PORT_CAP_SPEED_100G
@ FW_PORT_CAP_SPEED_100G
Definition: t4fw_interface.h:7135

fw_filter_vnic_mode
fw_filter_vnic_mode
Definition: t4fw_interface.h:4881

FW_VNIC_MODE_ENCAP_EN
@ FW_VNIC_MODE_ENCAP_EN
Definition: t4fw_interface.h:4884

FW_VNIC_MODE_PF_VF
@ FW_VNIC_MODE_PF_VF
Definition: t4fw_interface.h:4882

FW_VNIC_MODE_OUTER_VLAN
@ FW_VNIC_MODE_OUTER_VLAN
Definition: t4fw_interface.h:4883

fw_foiscsi_node_type
fw_foiscsi_node_type
Definition: t4fw_interface.h:2280

FW_FOISCSI_NODE_TYPE_TARGET
@ FW_FOISCSI_NODE_TYPE_TARGET
Definition: t4fw_interface.h:2282

FW_FOISCSI_NODE_TYPE_INITIATOR
@ FW_FOISCSI_NODE_TYPE_INITIATOR
Definition: t4fw_interface.h:2281

fw_port_action
fw_port_action
Definition: t4fw_interface.h:7293

FW_PORT_ACTION_DCB_READ_DET
@ FW_PORT_ACTION_DCB_READ_DET
Definition: t4fw_interface.h:7301

FW_PORT_ACTION_PHYXS_RESET
@ FW_PORT_ACTION_PHYXS_RESET
Definition: t4fw_interface.h:7317

FW_PORT_ACTION_AN_RESET
@ FW_PORT_ACTION_AN_RESET
Definition: t4fw_interface.h:7319

FW_PORT_ACTION_GET_PORT_INFO
@ FW_PORT_ACTION_GET_PORT_INFO
Definition: t4fw_interface.h:7296

FW_PORT_ACTION_L2_WOL_MODE_EN
@ FW_PORT_ACTION_L2_WOL_MODE_EN
Definition: t4fw_interface.h:7306

FW_PORT_ACTION_L1_LOW_PWR_EN
@ FW_PORT_ACTION_L1_LOW_PWR_EN
Definition: t4fw_interface.h:7305

FW_PORT_ACTION_L1_CFG32
@ FW_PORT_ACTION_L1_CFG32
Definition: t4fw_interface.h:7302

FW_PORT_ACTION_LOW_PWR_TO_NORMAL
@ FW_PORT_ACTION_LOW_PWR_TO_NORMAL
Definition: t4fw_interface.h:7304

FW_PORT_ACTION_PMA_RESET
@ FW_PORT_ACTION_PMA_RESET
Definition: t4fw_interface.h:7315

FW_PORT_ACTION_DCB_READ_TRANS
@ FW_PORT_ACTION_DCB_READ_TRANS
Definition: t4fw_interface.h:7299

FW_PORT_ACTION_LPBK_TO_NORMAL
@ FW_PORT_ACTION_LPBK_TO_NORMAL
Definition: t4fw_interface.h:7307

FW_PORT_ACTION_PHY_RESET
@ FW_PORT_ACTION_PHY_RESET
Definition: t4fw_interface.h:7314

FW_PORT_ACTION_LPBK_SS_EXT_PHY
@ FW_PORT_ACTION_LPBK_SS_EXT_PHY
Definition: t4fw_interface.h:7313

FW_PORT_ACTION_DCB_READ_RECV
@ FW_PORT_ACTION_DCB_READ_RECV
Definition: t4fw_interface.h:7300

FW_PORT_ACTION_L2_DCB_CFG
@ FW_PORT_ACTION_L2_DCB_CFG
Definition: t4fw_interface.h:7298

FW_PORT_ACTION_LPBK_SS_ASIC
@ FW_PORT_ACTION_LPBK_SS_ASIC
Definition: t4fw_interface.h:7308

FW_PORT_ACTION_L2_PPP_CFG
@ FW_PORT_ACTION_L2_PPP_CFG
Definition: t4fw_interface.h:7297

FW_PORT_ACTION_L1_CFG
@ FW_PORT_ACTION_L1_CFG
Definition: t4fw_interface.h:7294

FW_PORT_ACTION_GET_PORT_INFO32
@ FW_PORT_ACTION_GET_PORT_INFO32
Definition: t4fw_interface.h:7303

FW_PORT_ACTION_LPBK_WS_EXT_PHY
@ FW_PORT_ACTION_LPBK_WS_EXT_PHY
Definition: t4fw_interface.h:7310

FW_PORT_ACTION_DTEXS_REEST
@ FW_PORT_ACTION_DTEXS_REEST
Definition: t4fw_interface.h:7318

FW_PORT_ACTION_L2_CFG
@ FW_PORT_ACTION_L2_CFG
Definition: t4fw_interface.h:7295

FW_PORT_ACTION_LPBK_WS_ASIC
@ FW_PORT_ACTION_LPBK_WS_ASIC
Definition: t4fw_interface.h:7309

FW_PORT_ACTION_LPBK_SS_EXT
@ FW_PORT_ACTION_LPBK_SS_EXT
Definition: t4fw_interface.h:7311

FW_PORT_ACTION_DIAGNOSTICS
@ FW_PORT_ACTION_DIAGNOSTICS
Definition: t4fw_interface.h:7312

FW_PORT_ACTION_PCS_RESET
@ FW_PORT_ACTION_PCS_RESET
Definition: t4fw_interface.h:7316

fw_foiscsi_session_type
fw_foiscsi_session_type
Definition: t4fw_interface.h:2285

FW_FOISCSI_SESSION_TYPE_DISCOVERY
@ FW_FOISCSI_SESSION_TYPE_DISCOVERY
Definition: t4fw_interface.h:2286

FW_FOISCSI_SESSION_TYPE_NORMAL
@ FW_FOISCSI_SESSION_TYPE_NORMAL
Definition: t4fw_interface.h:2287

fw_sched_sc
fw_sched_sc
Definition: t4fw_interface.h:8726

FW_SCHED_SC_PARAMS
@ FW_SCHED_SC_PARAMS
Definition: t4fw_interface.h:8728

FW_SCHED_SC_CONFIG
@ FW_SCHED_SC_CONFIG
Definition: t4fw_interface.h:8727

fw_port_mdi
fw_port_mdi
Definition: t4fw_interface.h:7184

FW_PORT_CAP_MDI_F_STRAIGHT
@ FW_PORT_CAP_MDI_F_STRAIGHT
Definition: t4fw_interface.h:7187

FW_PORT_CAP_MDI_F_CROSSOVER
@ FW_PORT_CAP_MDI_F_CROSSOVER
Definition: t4fw_interface.h:7188

FW_PORT_CAP_MDI_AUTO
@ FW_PORT_CAP_MDI_AUTO
Definition: t4fw_interface.h:7186

FW_PORT_CAP_MDI_UNCHANGED
@ FW_PORT_CAP_MDI_UNCHANGED
Definition: t4fw_interface.h:7185

fw_port_mod_sub_type
fw_port_mod_sub_type
Definition: t4fw_interface.h:7832

FW_PORT_MOD_SUB_TYPE_TWINAX_3
@ FW_PORT_MOD_SUB_TYPE_TWINAX_3
Definition: t4fw_interface.h:7849

FW_PORT_MOD_SUB_TYPE_MV88E114X
@ FW_PORT_MOD_SUB_TYPE_MV88E114X
Definition: t4fw_interface.h:7834

FW_PORT_MOD_SUB_TYPE_BCM84834
@ FW_PORT_MOD_SUB_TYPE_BCM84834
Definition: t4fw_interface.h:7838

FW_PORT_MOD_SUB_TYPE_TWINAX_5
@ FW_PORT_MOD_SUB_TYPE_TWINAX_5
Definition: t4fw_interface.h:7850

FW_PORT_MOD_SUB_TYPE_BCM5482
@ FW_PORT_MOD_SUB_TYPE_BCM5482
Definition: t4fw_interface.h:7839

FW_PORT_MOD_SUB_TYPE_BCM84856
@ FW_PORT_MOD_SUB_TYPE_BCM84856
Definition: t4fw_interface.h:7840

FW_PORT_MOD_SUB_TYPE_TWINAX_1
@ FW_PORT_MOD_SUB_TYPE_TWINAX_1
Definition: t4fw_interface.h:7848

FW_PORT_MOD_SUB_TYPE_BT_VSC8634
@ FW_PORT_MOD_SUB_TYPE_BT_VSC8634
Definition: t4fw_interface.h:7841

FW_PORT_MOD_SUB_TYPE_TN8022
@ FW_PORT_MOD_SUB_TYPE_TN8022
Definition: t4fw_interface.h:7835

FW_PORT_MOD_SUB_TYPE_AQ1202
@ FW_PORT_MOD_SUB_TYPE_AQ1202
Definition: t4fw_interface.h:7836

FW_PORT_MOD_SUB_TYPE_88x3120
@ FW_PORT_MOD_SUB_TYPE_88x3120
Definition: t4fw_interface.h:7837

FW_PORT_MOD_SUB_TYPE_NA
@ FW_PORT_MOD_SUB_TYPE_NA
Definition: t4fw_interface.h:7833

FW_PORT_MOD_SUB_TYPE_TWINAX_7
@ FW_PORT_MOD_SUB_TYPE_TWINAX_7
Definition: t4fw_interface.h:7851

fw_foiscsi_ctrl_state
fw_foiscsi_ctrl_state
Definition: t4fw_interface.h:2322

FW_FOISCSI_CTRL_STATE_REDIRECT
@ FW_FOISCSI_CTRL_STATE_REDIRECT
Definition: t4fw_interface.h:2327

FW_FOISCSI_CTRL_STATE_FAILED
@ FW_FOISCSI_CTRL_STATE_FAILED
Definition: t4fw_interface.h:2325

FW_FOISCSI_CTRL_STATE_ONLINE
@ FW_FOISCSI_CTRL_STATE_ONLINE
Definition: t4fw_interface.h:2324

FW_FOISCSI_CTRL_STATE_IN_RECOVERY
@ FW_FOISCSI_CTRL_STATE_IN_RECOVERY
Definition: t4fw_interface.h:2326

FW_FOISCSI_CTRL_STATE_FREE
@ FW_FOISCSI_CTRL_STATE_FREE
Definition: t4fw_interface.h:2323

fw_chnet_ifconf_wr_subop
fw_chnet_ifconf_wr_subop
Definition: t4fw_interface.h:2173

FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET
@ FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET
Definition: t4fw_interface.h:2191

FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET
@ FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET
Definition: t4fw_interface.h:2192

FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET
@ FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET
Definition: t4fw_interface.h:2183

FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET
@ FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET
Definition: t4fw_interface.h:2182

FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED
@ FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED
Definition: t4fw_interface.h:2199

FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4
@ FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4
Definition: t4fw_interface.h:2201

FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET
@ FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET
Definition: t4fw_interface.h:2180

FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET
@ FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET
Definition: t4fw_interface.h:2186

FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET
@ FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET
Definition: t4fw_interface.h:2195

FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET
@ FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET
Definition: t4fw_interface.h:2198

FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET
@ FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET
Definition: t4fw_interface.h:2177

FW_CHNET_IFCONF_WR_SUBOP_MTU_SET
@ FW_CHNET_IFCONF_WR_SUBOP_MTU_SET
Definition: t4fw_interface.h:2188

FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET
@ FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET
Definition: t4fw_interface.h:2197

FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET
@ FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET
Definition: t4fw_interface.h:2179

FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET
@ FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET
Definition: t4fw_interface.h:2194

FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4
@ FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4
Definition: t4fw_interface.h:2204

FW_CHNET_IFCONF_WR_SUBOP_MAX
@ FW_CHNET_IFCONF_WR_SUBOP_MAX
Definition: t4fw_interface.h:2209

FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6
@ FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6
Definition: t4fw_interface.h:2205

FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6
@ FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6
Definition: t4fw_interface.h:2202

FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET
@ FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET
Definition: t4fw_interface.h:2176

FW_CHNET_IFCONF_WR_SUBOP_NONE
@ FW_CHNET_IFCONF_WR_SUBOP_NONE
Definition: t4fw_interface.h:2174

FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR
@ FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR
Definition: t4fw_interface.h:2207

FW_CHNET_IFCONF_WR_SUBOP_MTU_GET
@ FW_CHNET_IFCONF_WR_SUBOP_MTU_GET
Definition: t4fw_interface.h:2189

FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET
@ FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET
Definition: t4fw_interface.h:2185

fw_caps_config_nbm
fw_caps_config_nbm
Definition: t4fw_interface.h:4642

FW_CAPS_CONFIG_NBM_IPMI
@ FW_CAPS_CONFIG_NBM_IPMI
Definition: t4fw_interface.h:4643

FW_CAPS_CONFIG_NBM_NCSI
@ FW_CAPS_CONFIG_NBM_NCSI
Definition: t4fw_interface.h:4644

fw_port_stats_tx_index
fw_port_stats_tx_index
Definition: t4fw_interface.h:7865

FW_STAT_TX_PORT_ERROR_IX
@ FW_STAT_TX_PORT_ERROR_IX
Definition: t4fw_interface.h:7871

FW_STAT_TX_PORT_MCAST_IX
@ FW_STAT_TX_PORT_MCAST_IX
Definition: t4fw_interface.h:7869

FW_STAT_TX_PORT_PPP1_IX
@ FW_STAT_TX_PORT_PPP1_IX
Definition: t4fw_interface.h:7882

FW_STAT_TX_PORT_65B_127B_IX
@ FW_STAT_TX_PORT_65B_127B_IX
Definition: t4fw_interface.h:7873

FW_STAT_TX_PORT_PPP0_IX
@ FW_STAT_TX_PORT_PPP0_IX
Definition: t4fw_interface.h:7881

FW_STAT_TX_PORT_64B_IX
@ FW_STAT_TX_PORT_64B_IX
Definition: t4fw_interface.h:7872

FW_STAT_TX_PORT_BCAST_IX
@ FW_STAT_TX_PORT_BCAST_IX
Definition: t4fw_interface.h:7868

FW_STAT_TX_PORT_128B_255B_IX
@ FW_STAT_TX_PORT_128B_255B_IX
Definition: t4fw_interface.h:7874

FW_STAT_TX_PORT_512B_1023B_IX
@ FW_STAT_TX_PORT_512B_1023B_IX
Definition: t4fw_interface.h:7876

FW_STAT_TX_PORT_1519B_MAX_IX
@ FW_STAT_TX_PORT_1519B_MAX_IX
Definition: t4fw_interface.h:7878

FW_STAT_TX_PORT_PPP2_IX
@ FW_STAT_TX_PORT_PPP2_IX
Definition: t4fw_interface.h:7883

FW_NUM_PORT_TX_STATS
@ FW_NUM_PORT_TX_STATS
Definition: t4fw_interface.h:7889

FW_STAT_TX_PORT_256B_511B_IX
@ FW_STAT_TX_PORT_256B_511B_IX
Definition: t4fw_interface.h:7875

FW_STAT_TX_PORT_BYTES_IX
@ FW_STAT_TX_PORT_BYTES_IX
Definition: t4fw_interface.h:7866

FW_STAT_TX_PORT_1024B_1518B_IX
@ FW_STAT_TX_PORT_1024B_1518B_IX
Definition: t4fw_interface.h:7877

FW_STAT_TX_PORT_PPP3_IX
@ FW_STAT_TX_PORT_PPP3_IX
Definition: t4fw_interface.h:7884

FW_STAT_TX_PORT_DROP_IX
@ FW_STAT_TX_PORT_DROP_IX
Definition: t4fw_interface.h:7879

FW_STAT_TX_PORT_PPP7_IX
@ FW_STAT_TX_PORT_PPP7_IX
Definition: t4fw_interface.h:7888

FW_STAT_TX_PORT_UCAST_IX
@ FW_STAT_TX_PORT_UCAST_IX
Definition: t4fw_interface.h:7870

FW_STAT_TX_PORT_PPP6_IX
@ FW_STAT_TX_PORT_PPP6_IX
Definition: t4fw_interface.h:7887

FW_STAT_TX_PORT_FRAMES_IX
@ FW_STAT_TX_PORT_FRAMES_IX
Definition: t4fw_interface.h:7867

FW_STAT_TX_PORT_PAUSE_IX
@ FW_STAT_TX_PORT_PAUSE_IX
Definition: t4fw_interface.h:7880

FW_STAT_TX_PORT_PPP5_IX
@ FW_STAT_TX_PORT_PPP5_IX
Definition: t4fw_interface.h:7886

FW_STAT_TX_PORT_PPP4_IX
@ FW_STAT_TX_PORT_PPP4_IX
Definition: t4fw_interface.h:7885

fw_port_dcb_feature_state
fw_port_dcb_feature_state
Definition: t4fw_interface.h:7368

FW_PORT_DCB_FEATURE_STATE_SUCCESS
@ FW_PORT_DCB_FEATURE_STATE_SUCCESS
Definition: t4fw_interface.h:7370

FW_PORT_DCB_FEATURE_STATE_TIMEOUT
@ FW_PORT_DCB_FEATURE_STATE_TIMEOUT
Definition: t4fw_interface.h:7372

FW_PORT_DCB_FEATURE_STATE_ERROR
@ FW_PORT_DCB_FEATURE_STATE_ERROR
Definition: t4fw_interface.h:7371

FW_PORT_DCB_FEATURE_STATE_PENDING
@ FW_PORT_DCB_FEATURE_STATE_PENDING
Definition: t4fw_interface.h:7369

fw_devlog_facility
fw_devlog_facility
Definition: t4fw_interface.h:8814

FW_DEVLOG_FACILITY_RES
@ FW_DEVLOG_FACILITY_RES
Definition: t4fw_interface.h:8819

FW_DEVLOG_FACILITY_ACL
@ FW_DEVLOG_FACILITY_ACL
Definition: t4fw_interface.h:8828

FW_DEVLOG_FACILITY_RI
@ FW_DEVLOG_FACILITY_RI
Definition: t4fw_interface.h:8834

FW_DEVLOG_FACILITY_MAX
@ FW_DEVLOG_FACILITY_MAX
Definition: t4fw_interface.h:8841

FW_DEVLOG_FACILITY_MAC
@ FW_DEVLOG_FACILITY_MAC
Definition: t4fw_interface.h:8824

FW_DEVLOG_FACILITY_FILTER
@ FW_DEVLOG_FACILITY_FILTER
Definition: t4fw_interface.h:8827

FW_DEVLOG_FACILITY_COISCSI
@ FW_DEVLOG_FACILITY_COISCSI
Definition: t4fw_interface.h:8840

FW_DEVLOG_FACILITY_CHNET
@ FW_DEVLOG_FACILITY_CHNET
Definition: t4fw_interface.h:8839

FW_DEVLOG_FACILITY_FLR
@ FW_DEVLOG_FACILITY_FLR
Definition: t4fw_interface.h:8821

FW_DEVLOG_FACILITY_PORT
@ FW_DEVLOG_FACILITY_PORT
Definition: t4fw_interface.h:8825

FW_DEVLOG_FACILITY_DCB
@ FW_DEVLOG_FACILITY_DCB
Definition: t4fw_interface.h:8831

FW_DEVLOG_FACILITY_OFLD
@ FW_DEVLOG_FACILITY_OFLD
Definition: t4fw_interface.h:8833

FW_DEVLOG_FACILITY_SCHED
@ FW_DEVLOG_FACILITY_SCHED
Definition: t4fw_interface.h:8817

FW_DEVLOG_FACILITY_CF
@ FW_DEVLOG_FACILITY_CF
Definition: t4fw_interface.h:8816

FW_DEVLOG_FACILITY_CORE
@ FW_DEVLOG_FACILITY_CORE
Definition: t4fw_interface.h:8815

FW_DEVLOG_FACILITY_TIMER
@ FW_DEVLOG_FACILITY_TIMER
Definition: t4fw_interface.h:8818

FW_DEVLOG_FACILITY_VI
@ FW_DEVLOG_FACILITY_VI
Definition: t4fw_interface.h:8826

FW_DEVLOG_FACILITY_FOISCSI
@ FW_DEVLOG_FACILITY_FOISCSI
Definition: t4fw_interface.h:8837

FW_DEVLOG_FACILITY_PHY
@ FW_DEVLOG_FACILITY_PHY
Definition: t4fw_interface.h:8823

FW_DEVLOG_FACILITY_ISCSI
@ FW_DEVLOG_FACILITY_ISCSI
Definition: t4fw_interface.h:8835

FW_DEVLOG_FACILITY_TM
@ FW_DEVLOG_FACILITY_TM
Definition: t4fw_interface.h:8829

FW_DEVLOG_FACILITY_ETH
@ FW_DEVLOG_FACILITY_ETH
Definition: t4fw_interface.h:8832

FW_DEVLOG_FACILITY_HW
@ FW_DEVLOG_FACILITY_HW
Definition: t4fw_interface.h:8820

FW_DEVLOG_FACILITY_FCOE
@ FW_DEVLOG_FACILITY_FCOE
Definition: t4fw_interface.h:8836

FW_DEVLOG_FACILITY_FOFCOE
@ FW_DEVLOG_FACILITY_FOFCOE
Definition: t4fw_interface.h:8838

FW_DEVLOG_FACILITY_DMAQ
@ FW_DEVLOG_FACILITY_DMAQ
Definition: t4fw_interface.h:8822

FW_DEVLOG_FACILITY_QFC
@ FW_DEVLOG_FACILITY_QFC
Definition: t4fw_interface.h:8830

fw_ldst_func_mod_index
fw_ldst_func_mod_index
Definition: t4fw_interface.h:4278

FW_LDST_FUNC_MPS
@ FW_LDST_FUNC_MPS
Definition: t4fw_interface.h:4279

fw_ri_qp_caps
fw_ri_qp_caps
Definition: t4fw_interface.h:1244

FW_RI_QP_RDMA_WRITE_ENABLE
@ FW_RI_QP_RDMA_WRITE_ENABLE
Definition: t4fw_interface.h:1246

FW_RI_QP_STAG0_ENABLE
@ FW_RI_QP_STAG0_ENABLE
Definition: t4fw_interface.h:1249

FW_RI_QP_RDMA_READ_ENABLE
@ FW_RI_QP_RDMA_READ_ENABLE
Definition: t4fw_interface.h:1245

FW_RI_QP_BIND_ENABLE
@ FW_RI_QP_BIND_ENABLE
Definition: t4fw_interface.h:1247

FW_RI_QP_RDMA_READ_REQ_0B_ENABLE
@ FW_RI_QP_RDMA_READ_REQ_0B_ENABLE
Definition: t4fw_interface.h:1250

FW_RI_QP_FAST_REGISTER_ENABLE
@ FW_RI_QP_FAST_REGISTER_ENABLE
Definition: t4fw_interface.h:1248

fw_cmd_opcodes
fw_cmd_opcodes
Definition: t4fw_interface.h:4121

FW_PORT_LB_STATS_CMD
@ FW_PORT_LB_STATS_CMD
Definition: t4fw_interface.h:4144

FW_PTP_CMD
@ FW_PTP_CMD
Definition: t4fw_interface.h:4164

FW_LDST_CMD
@ FW_LDST_CMD
Definition: t4fw_interface.h:4122

FW_DEBUG_CMD
@ FW_DEBUG_CMD
Definition: t4fw_interface.h:4168

FW_VI_RXMODE_CMD
@ FW_VI_RXMODE_CMD
Definition: t4fw_interface.h:4137

FW_RSS_VI_CONFIG_CMD
@ FW_RSS_VI_CONFIG_CMD
Definition: t4fw_interface.h:4149

FW_CLIP2_CMD
@ FW_CLIP2_CMD
Definition: t4fw_interface.h:4154

FW_DIAG_CMD
@ FW_DIAG_CMD
Definition: t4fw_interface.h:4163

FW_FCOE_VNP_CMD
@ FW_FCOE_VNP_CMD
Definition: t4fw_interface.h:4158

FW_CAPS_CONFIG_CMD
@ FW_CAPS_CONFIG_CMD
Definition: t4fw_interface.h:4127

FW_IQ_CMD
@ FW_IQ_CMD
Definition: t4fw_interface.h:4130

FW_FCOE_LINK_CMD
@ FW_FCOE_LINK_CMD
Definition: t4fw_interface.h:4157

FW_DCB_IEEE_CMD
@ FW_DCB_IEEE_CMD
Definition: t4fw_interface.h:4162

FW_WATCHDOG_CMD
@ FW_WATCHDOG_CMD
Definition: t4fw_interface.h:4152

FW_PORT_CMD
@ FW_PORT_CMD
Definition: t4fw_interface.h:4142

FW_BYE_CMD
@ FW_BYE_CMD
Definition: t4fw_interface.h:4125

FW_CHNET_IFACE_CMD
@ FW_CHNET_IFACE_CMD
Definition: t4fw_interface.h:4155

FW_FCOE_SPARAMS_CMD
@ FW_FCOE_SPARAMS_CMD
Definition: t4fw_interface.h:4159

FW_EQ_MNGT_CMD
@ FW_EQ_MNGT_CMD
Definition: t4fw_interface.h:4131

FW_FCOE_STATS_CMD
@ FW_FCOE_STATS_CMD
Definition: t4fw_interface.h:4160

FW_INITIALIZE_CMD
@ FW_INITIALIZE_CMD
Definition: t4fw_interface.h:4126

FW_ACL_MAC_CMD
@ FW_ACL_MAC_CMD
Definition: t4fw_interface.h:4140

FW_RSS_GLB_CONFIG_CMD
@ FW_RSS_GLB_CONFIG_CMD
Definition: t4fw_interface.h:4148

FW_VI_STATS_CMD
@ FW_VI_STATS_CMD
Definition: t4fw_interface.h:4139

FW_EQ_OFLD_CMD
@ FW_EQ_OFLD_CMD
Definition: t4fw_interface.h:4134

FW_ACL_VLAN_CMD
@ FW_ACL_VLAN_CMD
Definition: t4fw_interface.h:4141

FW_VI_MAC_CMD
@ FW_VI_MAC_CMD
Definition: t4fw_interface.h:4136

FW_PORT_TRACE_CMD
@ FW_PORT_TRACE_CMD
Definition: t4fw_interface.h:4145

FW_FCOE_RES_INFO_CMD
@ FW_FCOE_RES_INFO_CMD
Definition: t4fw_interface.h:4156

FW_HELLO_CMD
@ FW_HELLO_CMD
Definition: t4fw_interface.h:4124

FW_ERROR_CMD
@ FW_ERROR_CMD
Definition: t4fw_interface.h:4167

FW_FCOE_FCF_CMD
@ FW_FCOE_FCF_CMD
Definition: t4fw_interface.h:4161

FW_DEVLOG_CMD
@ FW_DEVLOG_CMD
Definition: t4fw_interface.h:4151

FW_EQ_CTRL_CMD
@ FW_EQ_CTRL_CMD
Definition: t4fw_interface.h:4133

FW_VI_ENABLE_CMD
@ FW_VI_ENABLE_CMD
Definition: t4fw_interface.h:4138

FW_PORT_TRACE_MMAP_CMD
@ FW_PORT_TRACE_MMAP_CMD
Definition: t4fw_interface.h:4146

FW_HMA_CMD
@ FW_HMA_CMD
Definition: t4fw_interface.h:4165

FW_PORT_STATS_CMD
@ FW_PORT_STATS_CMD
Definition: t4fw_interface.h:4143

FW_RESET_CMD
@ FW_RESET_CMD
Definition: t4fw_interface.h:4123

FW_RSS_IND_TBL_CMD
@ FW_RSS_IND_TBL_CMD
Definition: t4fw_interface.h:4147

FW_VI_CMD
@ FW_VI_CMD
Definition: t4fw_interface.h:4135

FW_CLIP_CMD
@ FW_CLIP_CMD
Definition: t4fw_interface.h:4153

FW_SCHED_CMD
@ FW_SCHED_CMD
Definition: t4fw_interface.h:4150

FW_PARAMS_CMD
@ FW_PARAMS_CMD
Definition: t4fw_interface.h:4128

FW_LASTC2E_CMD
@ FW_LASTC2E_CMD
Definition: t4fw_interface.h:4166

FW_PFVF_CMD
@ FW_PFVF_CMD
Definition: t4fw_interface.h:4129

FW_EQ_ETH_CMD
@ FW_EQ_ETH_CMD
Definition: t4fw_interface.h:4132

fw_port_mdi32
fw_port_mdi32
Definition: t4fw_interface.h:7256

FW_PORT_CAP32_MDI_AUTO
@ FW_PORT_CAP32_MDI_AUTO
Definition: t4fw_interface.h:7258

FW_PORT_CAP32_MDI_F_STRAIGHT
@ FW_PORT_CAP32_MDI_F_STRAIGHT
Definition: t4fw_interface.h:7259

FW_PORT_CAP32_MDI_F_CROSSOVER
@ FW_PORT_CAP32_MDI_F_CROSSOVER
Definition: t4fw_interface.h:7260

FW_PORT_CAP32_MDI_UNCHANGED
@ FW_PORT_CAP32_MDI_UNCHANGED
Definition: t4fw_interface.h:7257

M_FW_PORT_CMD_MODTYPE
#define M_FW_PORT_CMD_MODTYPE
Definition: t4fw_interface.h:7626

T6FW_VERSION_MINOR
@ T6FW_VERSION_MINOR
Definition: t4fw_interface.h:10015

T4FW_VERSION_BUILD
@ T4FW_VERSION_BUILD
Definition: t4fw_interface.h:10007

T4FW_VERSION_MAJOR
@ T4FW_VERSION_MAJOR
Definition: t4fw_interface.h:10004

T5FW_VERSION_MICRO
@ T5FW_VERSION_MICRO
Definition: t4fw_interface.h:10011

T6FW_VERSION_MAJOR
@ T6FW_VERSION_MAJOR
Definition: t4fw_interface.h:10014

T4FW_VERSION_MINOR
@ T4FW_VERSION_MINOR
Definition: t4fw_interface.h:10005

T5FW_VERSION_MINOR
@ T5FW_VERSION_MINOR
Definition: t4fw_interface.h:10010

T6FW_VERSION_BUILD
@ T6FW_VERSION_BUILD
Definition: t4fw_interface.h:10017

T5FW_VERSION_MAJOR
@ T5FW_VERSION_MAJOR
Definition: t4fw_interface.h:10009

T4FW_VERSION_MICRO
@ T4FW_VERSION_MICRO
Definition: t4fw_interface.h:10006

T5FW_VERSION_BUILD
@ T5FW_VERSION_BUILD
Definition: t4fw_interface.h:10012

T6FW_VERSION_MICRO
@ T6FW_VERSION_MICRO
Definition: t4fw_interface.h:10016

fw_ri_addr_type
fw_ri_addr_type
Definition: t4fw_interface.h:1253

FW_RI_VA_BASED_TO
@ FW_RI_VA_BASED_TO
Definition: t4fw_interface.h:1255

FW_RI_ZERO_BASED_TO
@ FW_RI_ZERO_BASED_TO
Definition: t4fw_interface.h:1254

FW_PORT_CAP32_SPEED_100G
#define FW_PORT_CAP32_SPEED_100G
Definition: t4fw_interface.h:7203

fw_vi_mac_entry_types
fw_vi_mac_entry_types
Definition: t4fw_interface.h:6680

FW_VI_MAC_TYPE_EXACTMAC_VNI
@ FW_VI_MAC_TYPE_EXACTMAC_VNI
Definition: t4fw_interface.h:6684

FW_VI_MAC_TYPE_HASHVEC
@ FW_VI_MAC_TYPE_HASHVEC
Definition: t4fw_interface.h:6682

FW_VI_MAC_TYPE_EXACTMAC
@ FW_VI_MAC_TYPE_EXACTMAC
Definition: t4fw_interface.h:6681

FW_VI_MAC_TYPE_RAW
@ FW_VI_MAC_TYPE_RAW
Definition: t4fw_interface.h:6683

FW_FOISCSI_NAME_MAX_LEN
#define FW_FOISCSI_NAME_MAX_LEN
Definition: t4fw_interface.h:2166

fw_vi_func
fw_vi_func
Definition: t4fw_interface.h:6542

FW_VI_FUNC_IWARP
@ FW_VI_FUNC_IWARP
Definition: t4fw_interface.h:6545

FW_VI_FUNC_FOFCOE
@ FW_VI_FUNC_FOFCOE
Definition: t4fw_interface.h:6549

FW_VI_FUNC_FW
@ FW_VI_FUNC_FW
Definition: t4fw_interface.h:6550

FW_VI_FUNC_ETH
@ FW_VI_FUNC_ETH
Definition: t4fw_interface.h:6543

FW_VI_FUNC_OPENFCOE
@ FW_VI_FUNC_OPENFCOE
Definition: t4fw_interface.h:6547

FW_VI_FUNC_OFLD
@ FW_VI_FUNC_OFLD
Definition: t4fw_interface.h:6544

FW_VI_FUNC_FOISCSI
@ FW_VI_FUNC_FOISCSI
Definition: t4fw_interface.h:6548

FW_VI_FUNC_OPENISCSI
@ FW_VI_FUNC_OPENISCSI
Definition: t4fw_interface.h:6546

fw_foiscsi_auth_policy
fw_foiscsi_auth_policy
Definition: t4fw_interface.h:2290

FW_FOISCSI_AUTH_POLICY_ONEWAY
@ FW_FOISCSI_AUTH_POLICY_ONEWAY
Definition: t4fw_interface.h:2291

FW_FOISCSI_AUTH_POLICY_MUTUAL
@ FW_FOISCSI_AUTH_POLICY_MUTUAL
Definition: t4fw_interface.h:2292

fw_params_param_chnet_flags
fw_params_param_chnet_flags
Definition: t4fw_interface.h:4996

FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD
@ FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD
Definition: t4fw_interface.h:4998

FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6
@ FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6
Definition: t4fw_interface.h:4997

FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC
@ FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC
Definition: t4fw_interface.h:5000

FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2
@ FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2
Definition: t4fw_interface.h:4999

fw_flowc_mnem_tcpstate
fw_flowc_mnem_tcpstate
Definition: t4fw_interface.h:987

FW_FLOWC_MNEM_TCPSTATE_FINWAIT1
@ FW_FLOWC_MNEM_TCPSTATE_FINWAIT1
Definition: t4fw_interface.h:994

FW_FLOWC_MNEM_TCPSTATE_LISTEN
@ FW_FLOWC_MNEM_TCPSTATE_LISTEN
Definition: t4fw_interface.h:989

FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED
@ FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED
Definition: t4fw_interface.h:992

FW_FLOWC_MNEM_TCPSTATE_CLOSING
@ FW_FLOWC_MNEM_TCPSTATE_CLOSING
Definition: t4fw_interface.h:997

FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT
@ FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT
Definition: t4fw_interface.h:993

FW_FLOWC_MNEM_TCPSTATE_FINWAIT2
@ FW_FLOWC_MNEM_TCPSTATE_FINWAIT2
Definition: t4fw_interface.h:1005

FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED
@ FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED
Definition: t4fw_interface.h:991

FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT
@ FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT
Definition: t4fw_interface.h:1008

FW_FLOWC_MNEM_TCPSTATE_CLOSED
@ FW_FLOWC_MNEM_TCPSTATE_CLOSED
Definition: t4fw_interface.h:988

FW_FLOWC_MNEM_TCPSTATE_LASTACK
@ FW_FLOWC_MNEM_TCPSTATE_LASTACK
Definition: t4fw_interface.h:1001

FW_FLOWC_MNEM_TCPSTATE_SYNSENT
@ FW_FLOWC_MNEM_TCPSTATE_SYNSENT
Definition: t4fw_interface.h:990

fw_error_type
fw_error_type
Definition: t4fw_interface.h:9380

FW_ERROR_TYPE_HWMODULE
@ FW_ERROR_TYPE_HWMODULE
Definition: t4fw_interface.h:9382

FW_ERROR_TYPE_WR
@ FW_ERROR_TYPE_WR
Definition: t4fw_interface.h:9383

FW_ERROR_TYPE_EXCEPTION
@ FW_ERROR_TYPE_EXCEPTION
Definition: t4fw_interface.h:9381

FW_ERROR_TYPE_ACL
@ FW_ERROR_TYPE_ACL
Definition: t4fw_interface.h:9384

fw_port_dcb_versions
fw_port_dcb_versions
Definition: t4fw_interface.h:7340

FW_PORT_DCB_VER_UNKNOWN
@ FW_PORT_DCB_VER_UNKNOWN
Definition: t4fw_interface.h:7341

FW_PORT_DCB_VER_AUTO
@ FW_PORT_DCB_VER_AUTO
Definition: t4fw_interface.h:7345

FW_PORT_DCB_VER_CEE1D01
@ FW_PORT_DCB_VER_CEE1D01
Definition: t4fw_interface.h:7343

FW_PORT_DCB_VER_CEE1D0
@ FW_PORT_DCB_VER_CEE1D0
Definition: t4fw_interface.h:7342

FW_PORT_DCB_VER_IEEE
@ FW_PORT_DCB_VER_IEEE
Definition: t4fw_interface.h:7344

fw_caps_config_link
fw_caps_config_link
Definition: t4fw_interface.h:4647

FW_CAPS_CONFIG_LINK_PPP
@ FW_CAPS_CONFIG_LINK_PPP
Definition: t4fw_interface.h:4648

FW_CAPS_CONFIG_LINK_QFC
@ FW_CAPS_CONFIG_LINK_QFC
Definition: t4fw_interface.h:4649

FW_CAPS_CONFIG_LINK_DCBX
@ FW_CAPS_CONFIG_LINK_DCBX
Definition: t4fw_interface.h:4650

is_bt
static bool is_bt(enum fw_port_type port_type)
Definition: t4fw_interface.h:7808

fw_foiscsi_digest_type
fw_foiscsi_digest_type
Definition: t4fw_interface.h:2302

FW_FOISCSI_DIGEST_TYPE_CRC32_FST
@ FW_FOISCSI_DIGEST_TYPE_CRC32_FST
Definition: t4fw_interface.h:2305

FW_FOISCSI_DIGEST_TYPE_NONE
@ FW_FOISCSI_DIGEST_TYPE_NONE
Definition: t4fw_interface.h:2303

FW_FOISCSI_DIGEST_TYPE_CRC32
@ FW_FOISCSI_DIGEST_TYPE_CRC32
Definition: t4fw_interface.h:2304

FW_FOISCSI_DIGEST_TYPE_CRC32_SEC
@ FW_FOISCSI_DIGEST_TYPE_CRC32_SEC
Definition: t4fw_interface.h:2306

fw_dcb_ieee_locations
fw_dcb_ieee_locations
Definition: t4fw_interface.h:9387

FW_IEEE_LOC_OPERATIONAL
@ FW_IEEE_LOC_OPERATIONAL
Definition: t4fw_interface.h:9390

FW_IEEE_LOC_PEER
@ FW_IEEE_LOC_PEER
Definition: t4fw_interface.h:9389

FW_IEEE_LOC_LOCAL
@ FW_IEEE_LOC_LOCAL
Definition: t4fw_interface.h:9388

fw_ri_wr_opcode
fw_ri_wr_opcode
Definition: t4fw_interface.h:1197

FW_RI_RECEIVE
@ FW_RI_RECEIVE
Definition: t4fw_interface.h:1212

FW_RI_SEND_WITH_INV
@ FW_RI_SEND_WITH_INV
Definition: t4fw_interface.h:1202

FW_RI_SEND_WITH_SE
@ FW_RI_SEND_WITH_SE
Definition: t4fw_interface.h:1203

FW_RI_SEND
@ FW_RI_SEND
Definition: t4fw_interface.h:1201

FW_RI_TERMINATE
@ FW_RI_TERMINATE
Definition: t4fw_interface.h:1205

FW_RI_QP_MODIFY
@ FW_RI_QP_MODIFY
Definition: t4fw_interface.h:1210

FW_RI_RDMA_WRITE
@ FW_RI_RDMA_WRITE
Definition: t4fw_interface.h:1198

FW_RI_BIND_MW
@ FW_RI_BIND_MW
Definition: t4fw_interface.h:1207

FW_RI_FAST_REGISTER
@ FW_RI_FAST_REGISTER
Definition: t4fw_interface.h:1208

FW_RI_LOCAL_INV
@ FW_RI_LOCAL_INV
Definition: t4fw_interface.h:1209

FW_RI_READ_RESP
@ FW_RI_READ_RESP
Definition: t4fw_interface.h:1200

FW_RI_RDMA_INIT
@ FW_RI_RDMA_INIT
Definition: t4fw_interface.h:1206

FW_RI_READ_REQ
@ FW_RI_READ_REQ
Definition: t4fw_interface.h:1199

FW_RI_SEND_WITH_SE_INV
@ FW_RI_SEND_WITH_SE_INV
Definition: t4fw_interface.h:1204

FW_RI_WRITE_IMMEDIATE
@ FW_RI_WRITE_IMMEDIATE
Definition: t4fw_interface.h:1224

FW_RI_BYPASS
@ FW_RI_BYPASS
Definition: t4fw_interface.h:1211

FW_RI_SGE_EC_CR_RETURN
@ FW_RI_SGE_EC_CR_RETURN
Definition: t4fw_interface.h:1223

fw_ri_init_p2ptype
fw_ri_init_p2ptype
Definition: t4fw_interface.h:2083

FW_RI_INIT_P2PTYPE_SEND_WITH_SE
@ FW_RI_INIT_P2PTYPE_SEND_WITH_SE
Definition: t4fw_interface.h:2088

FW_RI_INIT_P2PTYPE_READ_REQ
@ FW_RI_INIT_P2PTYPE_READ_REQ
Definition: t4fw_interface.h:2085

FW_RI_INIT_P2PTYPE_DISABLED
@ FW_RI_INIT_P2PTYPE_DISABLED
Definition: t4fw_interface.h:2090

FW_RI_INIT_P2PTYPE_SEND_WITH_INV
@ FW_RI_INIT_P2PTYPE_SEND_WITH_INV
Definition: t4fw_interface.h:2087

FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV
@ FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV
Definition: t4fw_interface.h:2089

FW_RI_INIT_P2PTYPE_RDMA_WRITE
@ FW_RI_INIT_P2PTYPE_RDMA_WRITE
Definition: t4fw_interface.h:2084

FW_RI_INIT_P2PTYPE_SEND
@ FW_RI_INIT_P2PTYPE_SEND
Definition: t4fw_interface.h:2086

fw_port_lb_stats_index
fw_port_lb_stats_index
Definition: t4fw_interface.h:8028

FW_STAT_LB_PORT_1024B_1518B_IX
@ FW_STAT_LB_PORT_1024B_1518B_IX
Definition: t4fw_interface.h:8040

FW_STAT_LB_PORT_MCAST_IX
@ FW_STAT_LB_PORT_MCAST_IX
Definition: t4fw_interface.h:8032

FW_STAT_LB_PORT_ERROR_IX
@ FW_STAT_LB_PORT_ERROR_IX
Definition: t4fw_interface.h:8034

FW_STAT_LB_PORT_1519B_MAX_IX
@ FW_STAT_LB_PORT_1519B_MAX_IX
Definition: t4fw_interface.h:8041

FW_STAT_LB_PORT_UCAST_IX
@ FW_STAT_LB_PORT_UCAST_IX
Definition: t4fw_interface.h:8033

FW_STAT_LB_PORT_65B_127B_IX
@ FW_STAT_LB_PORT_65B_127B_IX
Definition: t4fw_interface.h:8036

FW_STAT_LB_PORT_BCAST_IX
@ FW_STAT_LB_PORT_BCAST_IX
Definition: t4fw_interface.h:8031

FW_STAT_LB_PORT_512B_1023B_IX
@ FW_STAT_LB_PORT_512B_1023B_IX
Definition: t4fw_interface.h:8039

FW_STAT_LB_PORT_DROP_FRAMES_IX
@ FW_STAT_LB_PORT_DROP_FRAMES_IX
Definition: t4fw_interface.h:8042

FW_STAT_LB_PORT_BYTES_IX
@ FW_STAT_LB_PORT_BYTES_IX
Definition: t4fw_interface.h:8029

FW_STAT_LB_PORT_FRAMES_IX
@ FW_STAT_LB_PORT_FRAMES_IX
Definition: t4fw_interface.h:8030

FW_STAT_LB_PORT_64B_IX
@ FW_STAT_LB_PORT_64B_IX
Definition: t4fw_interface.h:8035

FW_STAT_LB_PORT_256B_511B_IX
@ FW_STAT_LB_PORT_256B_511B_IX
Definition: t4fw_interface.h:8038

FW_STAT_LB_PORT_128B_255B_IX
@ FW_STAT_LB_PORT_128B_255B_IX
Definition: t4fw_interface.h:8037

fw_sched_params_mode
fw_sched_params_mode
Definition: t4fw_interface.h:8742

FW_SCHED_PARAMS_MODE_CLASS
@ FW_SCHED_PARAMS_MODE_CLASS
Definition: t4fw_interface.h:8743

FW_SCHED_PARAMS_MODE_FLOW
@ FW_SCHED_PARAMS_MODE_FLOW
Definition: t4fw_interface.h:8744

fw_hdr_flags
fw_hdr_flags
Definition: t4fw_interface.h:10064

FW_HDR_FLAGS_RESET_HALT
@ FW_HDR_FLAGS_RESET_HALT
Definition: t4fw_interface.h:10065

FW_HDR_FLAGS_SIGNED_FW
@ FW_HDR_FLAGS_SIGNED_FW
Definition: t4fw_interface.h:10066

fw_coiscsi_stats_wr_subop
fw_coiscsi_stats_wr_subop
Definition: t4fw_interface.h:2315

FW_COISCSI_WR_SUBOP_CUR
@ FW_COISCSI_WR_SUBOP_CUR
Definition: t4fw_interface.h:2318

FW_COISCSI_WR_SUBOP_CLR
@ FW_COISCSI_WR_SUBOP_CLR
Definition: t4fw_interface.h:2319

FW_COISCSI_WR_SUBOP_TOT
@ FW_COISCSI_WR_SUBOP_TOT
Definition: t4fw_interface.h:2316

FW_COISCSI_WR_SUBOP_MAX
@ FW_COISCSI_WR_SUBOP_MAX
Definition: t4fw_interface.h:2317

fw_iq_iqtype
fw_iq_iqtype
Definition: t4fw_interface.h:5207

FW_IQ_IQTYPE_OFLD
@ FW_IQ_IQTYPE_OFLD
Definition: t4fw_interface.h:5210

FW_IQ_IQTYPE_OTHER
@ FW_IQ_IQTYPE_OTHER
Definition: t4fw_interface.h:5208

FW_IQ_IQTYPE_NIC
@ FW_IQ_IQTYPE_NIC
Definition: t4fw_interface.h:5209

fw_ri_mpa_attrs
fw_ri_mpa_attrs
Definition: t4fw_interface.h:1237

FW_RI_MPA_IETF_ENABLE
@ FW_RI_MPA_IETF_ENABLE
Definition: t4fw_interface.h:1241

FW_RI_MPA_CRC_ENABLE
@ FW_RI_MPA_CRC_ENABLE
Definition: t4fw_interface.h:1240

FW_RI_MPA_RX_MARKER_ENABLE
@ FW_RI_MPA_RX_MARKER_ENABLE
Definition: t4fw_interface.h:1238

FW_RI_MPA_TX_MARKER_ENABLE
@ FW_RI_MPA_TX_MARKER_ENABLE
Definition: t4fw_interface.h:1239

fw_params_param_dev
fw_params_param_dev
Definition: t4fw_interface.h:4787

FW_PARAMS_PARAM_DEV_RSSINFO
@ FW_PARAMS_PARAM_DEV_RSSINFO
Definition: t4fw_interface.h:4818

FW_PARAMS_PARAM_DEV_TPCHMAP
@ FW_PARAMS_PARAM_DEV_TPCHMAP
Definition: t4fw_interface.h:4825

FW_PARAMS_PARAM_DEV_MAXORDIRD_QP
@ FW_PARAMS_PARAM_DEV_MAXORDIRD_QP
Definition: t4fw_interface.h:4810

FW_PARAMS_PARAM_DEV_BYPASS
@ FW_PARAMS_PARAM_DEV_BYPASS
Definition: t4fw_interface.h:4805

FW_PARAMS_PARAM_DEV_FILTER
@ FW_PARAMS_PARAM_DEV_FILTER
Definition: t4fw_interface.h:4840

FW_PARAMS_PARAM_DEV_PPOD_EDRAM
@ FW_PARAMS_PARAM_DEV_PPOD_EDRAM
Definition: t4fw_interface.h:4829

FW_PARAMS_PARAM_DEV_INTFVER_ISCSI
@ FW_PARAMS_PARAM_DEV_INTFVER_ISCSI
Definition: t4fw_interface.h:4800

FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR
@ FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR
Definition: t4fw_interface.h:4821

FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD
@ FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD
Definition: t4fw_interface.h:4834

FW_PARAMS_PARAM_DEV_FWREV
@ FW_PARAMS_PARAM_DEV_FWREV
Definition: t4fw_interface.h:4802

FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER
@ FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER
Definition: t4fw_interface.h:4812

FW_PARAMS_PARAM_DEV_PORTVEC
@ FW_PARAMS_PARAM_DEV_PORTVEC
Definition: t4fw_interface.h:4789

FW_PARAMS_PARAM_DEV_RING_BACKBONE
@ FW_PARAMS_PARAM_DEV_RING_BACKBONE
Definition: t4fw_interface.h:4828

FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM
@ FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM
Definition: t4fw_interface.h:4827

FW_PARAMS_PARAM_DEV_VPDREV
@ FW_PARAMS_PARAM_DEV_VPDREV
Definition: t4fw_interface.h:4820

FW_PARAMS_PARAM_DEV_TPREV
@ FW_PARAMS_PARAM_DEV_TPREV
Definition: t4fw_interface.h:4803

FW_PARAMS_PARAM_DEV_FWCACHE
@ FW_PARAMS_PARAM_DEV_FWCACHE
Definition: t4fw_interface.h:4817

FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP
@ FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP
Definition: t4fw_interface.h:4844

FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU
@ FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU
Definition: t4fw_interface.h:4814

FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL
@ FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL
Definition: t4fw_interface.h:4816

FW_PARAMS_PARAM_DEV_MPSBGMAP
@ FW_PARAMS_PARAM_DEV_MPSBGMAP
Definition: t4fw_interface.h:4824

FW_PARAMS_PARAM_DEV_SCFGREV
@ FW_PARAMS_PARAM_DEV_SCFGREV
Definition: t4fw_interface.h:4819

FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ
@ FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ
Definition: t4fw_interface.h:4794

FW_PARAMS_PARAM_DEV_PHYFW
@ FW_PARAMS_PARAM_DEV_PHYFW
Definition: t4fw_interface.h:4806

FW_PARAMS_PARAM_DEV_MCINIT
@ FW_PARAMS_PARAM_DEV_MCINIT
Definition: t4fw_interface.h:4815

FW_PARAMS_PARAM_DEV_INTFVER_RI
@ FW_PARAMS_PARAM_DEV_INTFVER_RI
Definition: t4fw_interface.h:4798

FW_PARAMS_PARAM_DEV_INTFVER_OFLD
@ FW_PARAMS_PARAM_DEV_INTFVER_OFLD
Definition: t4fw_interface.h:4797

FW_PARAMS_PARAM_DEV_FILTER2_WR
@ FW_PARAMS_PARAM_DEV_FILTER2_WR
Definition: t4fw_interface.h:4822

FW_PARAMS_PARAM_DEV_INTFVER_VNIC
@ FW_PARAMS_PARAM_DEV_INTFVER_VNIC
Definition: t4fw_interface.h:4796

FW_PARAMS_PARAM_DEV_LOAD
@ FW_PARAMS_PARAM_DEV_LOAD
Definition: t4fw_interface.h:4807

FW_PARAMS_PARAM_DEV_CF
@ FW_PARAMS_PARAM_DEV_CF
Definition: t4fw_interface.h:4804

FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR
@ FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR
Definition: t4fw_interface.h:4830

FW_PARAMS_PARAM_DEV_KTLS_HW
@ FW_PARAMS_PARAM_DEV_KTLS_HW
Definition: t4fw_interface.h:4843

FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU
@ FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU
Definition: t4fw_interface.h:4799

FW_PARAMS_PARAM_DEV_HMA_SIZE
@ FW_PARAMS_PARAM_DEV_HMA_SIZE
Definition: t4fw_interface.h:4826

FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH
@ FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH
Definition: t4fw_interface.h:4839

FW_PARAMS_PARAM_DEV_ADD_SMAC
@ FW_PARAMS_PARAM_DEV_ADD_SMAC
Definition: t4fw_interface.h:4831

FW_PARAMS_PARAM_DEV_CCLK
@ FW_PARAMS_PARAM_DEV_CCLK
Definition: t4fw_interface.h:4788

FW_PARAMS_PARAM_DEV_DEV_512SGL_MR
@ FW_PARAMS_PARAM_DEV_DEV_512SGL_MR
Definition: t4fw_interface.h:4842

FW_PARAMS_PARAM_DEV_INTFVER_FCOE
@ FW_PARAMS_PARAM_DEV_INTFVER_FCOE
Definition: t4fw_interface.h:4801

FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN
@ FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN
Definition: t4fw_interface.h:4833

FW_PARAMS_PARAM_DEV_UCLK
@ FW_PARAMS_PARAM_DEV_UCLK
Definition: t4fw_interface.h:4809

FW_PARAMS_PARAM_DEV_DIAG
@ FW_PARAMS_PARAM_DEV_DIAG
Definition: t4fw_interface.h:4808

FW_PARAMS_PARAM_DEV_DBQ_TIMER
@ FW_PARAMS_PARAM_DEV_DBQ_TIMER
Definition: t4fw_interface.h:4835

FW_PARAMS_PARAM_DEV_NTID
@ FW_PARAMS_PARAM_DEV_NTID
Definition: t4fw_interface.h:4790

FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK
@ FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK
Definition: t4fw_interface.h:4836

FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT
@ FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT
Definition: t4fw_interface.h:4832

FW_PARAMS_PARAM_DEV_NUM_TM_CLASS
@ FW_PARAMS_PARAM_DEV_NUM_TM_CLASS
Definition: t4fw_interface.h:4837

FW_PARAMS_PARAM_DEV_VF_TRVLAN
@ FW_PARAMS_PARAM_DEV_VF_TRVLAN
Definition: t4fw_interface.h:4838

FW_PARAMS_PARAM_DEV_CLIP2_CMD
@ FW_PARAMS_PARAM_DEV_CLIP2_CMD
Definition: t4fw_interface.h:4841

FW_PARAMS_PARAM_DEV_INTFVER_NIC
@ FW_PARAMS_PARAM_DEV_INTFVER_NIC
Definition: t4fw_interface.h:4795

FW_HDR_MAGIC_RUNTIME
@ FW_HDR_MAGIC_RUNTIME
Definition: t4fw_interface.h:10060

FW_HDR_MAGIC_BOOTSTRAP
@ FW_HDR_MAGIC_BOOTSTRAP
Definition: t4fw_interface.h:10061

fw_caps_config_hm
fw_caps_config_hm
Definition: t4fw_interface.h:4593

FW_CAPS_CONFIG_HM_LE
@ FW_CAPS_CONFIG_HM_LE
Definition: t4fw_interface.h:4604

FW_CAPS_CONFIG_HM_NCSI
@ FW_CAPS_CONFIG_HM_NCSI
Definition: t4fw_interface.h:4611

FW_CAPS_CONFIG_HM_I2CM
@ FW_CAPS_CONFIG_HM_I2CM
Definition: t4fw_interface.h:4610

FW_CAPS_CONFIG_HM_SGE
@ FW_CAPS_CONFIG_HM_SGE
Definition: t4fw_interface.h:4596

FW_CAPS_CONFIG_HM_T4DBG
@ FW_CAPS_CONFIG_HM_T4DBG
Definition: t4fw_interface.h:4608

FW_CAPS_CONFIG_HM_PL
@ FW_CAPS_CONFIG_HM_PL
Definition: t4fw_interface.h:4595

FW_CAPS_CONFIG_HM_MA
@ FW_CAPS_CONFIG_HM_MA
Definition: t4fw_interface.h:4613

FW_CAPS_CONFIG_HM_ULPRX
@ FW_CAPS_CONFIG_HM_ULPRX
Definition: t4fw_interface.h:4600

FW_CAPS_CONFIG_HM_PMRX
@ FW_CAPS_CONFIG_HM_PMRX
Definition: t4fw_interface.h:4601

FW_CAPS_CONFIG_HM_SMB
@ FW_CAPS_CONFIG_HM_SMB
Definition: t4fw_interface.h:4612

FW_CAPS_CONFIG_HM_TP
@ FW_CAPS_CONFIG_HM_TP
Definition: t4fw_interface.h:4599

FW_CAPS_CONFIG_HM_MI
@ FW_CAPS_CONFIG_HM_MI
Definition: t4fw_interface.h:4609

FW_CAPS_CONFIG_HM_CIM
@ FW_CAPS_CONFIG_HM_CIM
Definition: t4fw_interface.h:4597

FW_CAPS_CONFIG_HM_XGMAC
@ FW_CAPS_CONFIG_HM_XGMAC
Definition: t4fw_interface.h:4606

FW_CAPS_CONFIG_HM_ULPTX
@ FW_CAPS_CONFIG_HM_ULPTX
Definition: t4fw_interface.h:4598

FW_CAPS_CONFIG_HM_PCIE
@ FW_CAPS_CONFIG_HM_PCIE
Definition: t4fw_interface.h:4594

FW_CAPS_CONFIG_HM_EDRAM
@ FW_CAPS_CONFIG_HM_EDRAM
Definition: t4fw_interface.h:4614

FW_CAPS_CONFIG_HM_MPS
@ FW_CAPS_CONFIG_HM_MPS
Definition: t4fw_interface.h:4605

FW_CAPS_CONFIG_HM_SF
@ FW_CAPS_CONFIG_HM_SF
Definition: t4fw_interface.h:4617

FW_CAPS_CONFIG_HM_MC
@ FW_CAPS_CONFIG_HM_MC
Definition: t4fw_interface.h:4603

FW_CAPS_CONFIG_HM_CPLSWITCH
@ FW_CAPS_CONFIG_HM_CPLSWITCH
Definition: t4fw_interface.h:4607

FW_CAPS_CONFIG_HM_PMU
@ FW_CAPS_CONFIG_HM_PMU
Definition: t4fw_interface.h:4615

FW_CAPS_CONFIG_HM_UART
@ FW_CAPS_CONFIG_HM_UART
Definition: t4fw_interface.h:4616

FW_CAPS_CONFIG_HM_PMTX
@ FW_CAPS_CONFIG_HM_PMTX
Definition: t4fw_interface.h:4602

fw_ri_cqe_rxtx
fw_ri_cqe_rxtx
Definition: t4fw_interface.h:1467

FW_RI_CQE_RXTX_TX
@ FW_RI_CQE_RXTX_TX
Definition: t4fw_interface.h:1469

FW_RI_CQE_RXTX_RX
@ FW_RI_CQE_RXTX_RX
Definition: t4fw_interface.h:1468

fw_ri_mem_perms
fw_ri_mem_perms
Definition: t4fw_interface.h:1258

FW_RI_MEM_ACCESS_REM_WRITE
@ FW_RI_MEM_ACCESS_REM_WRITE
Definition: t4fw_interface.h:1259

FW_RI_MEM_ACCESS_REM_READ
@ FW_RI_MEM_ACCESS_REM_READ
Definition: t4fw_interface.h:1260

FW_RI_MEM_ACCESS_REM
@ FW_RI_MEM_ACCESS_REM
Definition: t4fw_interface.h:1261

FW_RI_MEM_ACCESS_LOCAL_WRITE
@ FW_RI_MEM_ACCESS_LOCAL_WRITE
Definition: t4fw_interface.h:1262

FW_RI_MEM_ACCESS_LOCAL
@ FW_RI_MEM_ACCESS_LOCAL
Definition: t4fw_interface.h:1264

FW_RI_MEM_ACCESS_LOCAL_READ
@ FW_RI_MEM_ACCESS_LOCAL_READ
Definition: t4fw_interface.h:1263

fw_ri_sgl_depth
fw_ri_sgl_depth
Definition: t4fw_interface.h:1280

FW_RI_SGL_DEPTH_MAX_RQ
@ FW_RI_SGL_DEPTH_MAX_RQ
Definition: t4fw_interface.h:1282

FW_RI_SGL_DEPTH_MAX_SQ
@ FW_RI_SGL_DEPTH_MAX_SQ
Definition: t4fw_interface.h:1281

vf_link_states
vf_link_states
Definition: t4fw_interface.h:4965

VF_LINK_STATE_DISABLE
@ VF_LINK_STATE_DISABLE
Definition: t4fw_interface.h:4968

VF_LINK_STATE_AUTO
@ VF_LINK_STATE_AUTO
Definition: t4fw_interface.h:4966

VF_LINK_STATE_ENABLE
@ VF_LINK_STATE_ENABLE
Definition: t4fw_interface.h:4967

fw_ri_atomic_op
fw_ri_atomic_op
Definition: t4fw_interface.h:2035

FW_RI_ATOMIC_OP_CMDSWAP
@ FW_RI_ATOMIC_OP_CMDSWAP
Definition: t4fw_interface.h:2038

FW_RI_ATOMIC_OP_SWAP
@ FW_RI_ATOMIC_OP_SWAP
Definition: t4fw_interface.h:2037

FW_RI_ATOMIC_OP_FETCHADD
@ FW_RI_ATOMIC_OP_FETCHADD
Definition: t4fw_interface.h:2036

T4FW_HDR_INTFVER_FCOE
@ T4FW_HDR_INTFVER_FCOE
Definition: t4fw_interface.h:10030

T6FW_HDR_INTFVER_RI
@ T6FW_HDR_INTFVER_RI
Definition: t4fw_interface.h:10048

T4FW_HDR_INTFVER_VNIC
@ T4FW_HDR_INTFVER_VNIC
Definition: t4fw_interface.h:10024

T5FW_HDR_INTFVER_OFLD
@ T5FW_HDR_INTFVER_OFLD
Definition: t4fw_interface.h:10036

T6FW_HDR_INTFVER_FCOEPDU
@ T6FW_HDR_INTFVER_FCOEPDU
Definition: t4fw_interface.h:10051

T4FW_HDR_INTFVER_ISCSIPDU
@ T4FW_HDR_INTFVER_ISCSIPDU
Definition: t4fw_interface.h:10027

T6FW_HDR_INTFVER_FCOE
@ T6FW_HDR_INTFVER_FCOE
Definition: t4fw_interface.h:10052

T4FW_HDR_INTFVER_RI
@ T4FW_HDR_INTFVER_RI
Definition: t4fw_interface.h:10026

T6FW_HDR_INTFVER_ISCSIPDU
@ T6FW_HDR_INTFVER_ISCSIPDU
Definition: t4fw_interface.h:10049

T4FW_HDR_INTFVER_FCOEPDU
@ T4FW_HDR_INTFVER_FCOEPDU
Definition: t4fw_interface.h:10029

T6FW_HDR_INTFVER_ISCSI
@ T6FW_HDR_INTFVER_ISCSI
Definition: t4fw_interface.h:10050

T4FW_HDR_INTFVER_NIC
@ T4FW_HDR_INTFVER_NIC
Definition: t4fw_interface.h:10023

T5FW_HDR_INTFVER_NIC
@ T5FW_HDR_INTFVER_NIC
Definition: t4fw_interface.h:10034

T5FW_HDR_INTFVER_ISCSIPDU
@ T5FW_HDR_INTFVER_ISCSIPDU
Definition: t4fw_interface.h:10038

T5FW_HDR_INTFVER_RI
@ T5FW_HDR_INTFVER_RI
Definition: t4fw_interface.h:10037

T6FW_HDR_INTFVER_NIC
@ T6FW_HDR_INTFVER_NIC
Definition: t4fw_interface.h:10045

T6FW_HDR_INTFVER_OFLD
@ T6FW_HDR_INTFVER_OFLD
Definition: t4fw_interface.h:10047

T5FW_HDR_INTFVER_ISCSI
@ T5FW_HDR_INTFVER_ISCSI
Definition: t4fw_interface.h:10039

T5FW_HDR_INTFVER_FCOE
@ T5FW_HDR_INTFVER_FCOE
Definition: t4fw_interface.h:10041

T4FW_HDR_INTFVER_ISCSI
@ T4FW_HDR_INTFVER_ISCSI
Definition: t4fw_interface.h:10028

T6FW_HDR_INTFVER_VNIC
@ T6FW_HDR_INTFVER_VNIC
Definition: t4fw_interface.h:10046

T4FW_HDR_INTFVER_OFLD
@ T4FW_HDR_INTFVER_OFLD
Definition: t4fw_interface.h:10025

T5FW_HDR_INTFVER_VNIC
@ T5FW_HDR_INTFVER_VNIC
Definition: t4fw_interface.h:10035

T5FW_HDR_INTFVER_FCOEPDU
@ T5FW_HDR_INTFVER_FCOEPDU
Definition: t4fw_interface.h:10040

fw_ri_type
fw_ri_type
Definition: t4fw_interface.h:2077

FW_RI_TYPE_TERMINATE
@ FW_RI_TYPE_TERMINATE
Definition: t4fw_interface.h:2080

FW_RI_TYPE_FINI
@ FW_RI_TYPE_FINI
Definition: t4fw_interface.h:2079

FW_RI_TYPE_INIT
@ FW_RI_TYPE_INIT
Definition: t4fw_interface.h:2078

fw_ldst_mps_fid
fw_ldst_mps_fid
Definition: t4fw_interface.h:4268

FW_LDST_MPS_ATRB
@ FW_LDST_MPS_ATRB
Definition: t4fw_interface.h:4269

FW_LDST_MPS_RPLC
@ FW_LDST_MPS_RPLC
Definition: t4fw_interface.h:4270

fw_vi_stats_pf_index
fw_vi_stats_pf_index
Definition: t4fw_interface.h:6945

FW_VI_PF_STAT_TX_OFLD_BYTES_IX
@ FW_VI_PF_STAT_TX_OFLD_BYTES_IX
Definition: t4fw_interface.h:6952

FW_VI_PF_STAT_TX_MCAST_FRAMES_IX
@ FW_VI_PF_STAT_TX_MCAST_FRAMES_IX
Definition: t4fw_interface.h:6949

FW_VI_PF_STAT_TX_UCAST_FRAMES_IX
@ FW_VI_PF_STAT_TX_UCAST_FRAMES_IX
Definition: t4fw_interface.h:6951

FW_VI_PF_STAT_TX_UCAST_BYTES_IX
@ FW_VI_PF_STAT_TX_UCAST_BYTES_IX
Definition: t4fw_interface.h:6950

FW_VI_PF_STAT_RX_BCAST_BYTES_IX
@ FW_VI_PF_STAT_RX_BCAST_BYTES_IX
Definition: t4fw_interface.h:6956

FW_VI_PF_STAT_RX_UCAST_BYTES_IX
@ FW_VI_PF_STAT_RX_UCAST_BYTES_IX
Definition: t4fw_interface.h:6960

FW_VI_PF_STAT_TX_MCAST_BYTES_IX
@ FW_VI_PF_STAT_TX_MCAST_BYTES_IX
Definition: t4fw_interface.h:6948

FW_VI_PF_STAT_TX_BCAST_BYTES_IX
@ FW_VI_PF_STAT_TX_BCAST_BYTES_IX
Definition: t4fw_interface.h:6946

FW_VI_PF_STAT_RX_UCAST_FRAMES_IX
@ FW_VI_PF_STAT_RX_UCAST_FRAMES_IX
Definition: t4fw_interface.h:6961

FW_VI_PF_STAT_TX_BCAST_FRAMES_IX
@ FW_VI_PF_STAT_TX_BCAST_FRAMES_IX
Definition: t4fw_interface.h:6947

FW_VI_PF_STAT_RX_MCAST_BYTES_IX
@ FW_VI_PF_STAT_RX_MCAST_BYTES_IX
Definition: t4fw_interface.h:6958

FW_VI_PF_STAT_TX_OFLD_FRAMES_IX
@ FW_VI_PF_STAT_TX_OFLD_FRAMES_IX
Definition: t4fw_interface.h:6953

FW_VI_PF_STAT_RX_MCAST_FRAMES_IX
@ FW_VI_PF_STAT_RX_MCAST_FRAMES_IX
Definition: t4fw_interface.h:6959

FW_VI_PF_STAT_RX_ERR_FRAMES_IX
@ FW_VI_PF_STAT_RX_ERR_FRAMES_IX
Definition: t4fw_interface.h:6962

FW_VI_PF_STAT_RX_BCAST_FRAMES_IX
@ FW_VI_PF_STAT_RX_BCAST_FRAMES_IX
Definition: t4fw_interface.h:6957

FW_VI_PF_STAT_RX_FRAMES_IX
@ FW_VI_PF_STAT_RX_FRAMES_IX
Definition: t4fw_interface.h:6955

FW_VI_PF_STAT_RX_BYTES_IX
@ FW_VI_PF_STAT_RX_BYTES_IX
Definition: t4fw_interface.h:6954

fw_ri_res_op
fw_ri_res_op
Definition: t4fw_interface.h:1534

FW_RI_RES_OP_RESET
@ FW_RI_RES_OP_RESET
Definition: t4fw_interface.h:1536

FW_RI_RES_OP_WRITE
@ FW_RI_RES_OP_WRITE
Definition: t4fw_interface.h:1535

fw_port_module_type
fw_port_module_type
Definition: t4fw_interface.h:7817

FW_PORT_MOD_TYPE_SR
@ FW_PORT_MOD_TYPE_SR
Definition: t4fw_interface.h:7820

FW_PORT_MOD_TYPE_TWINAX_PASSIVE
@ FW_PORT_MOD_TYPE_TWINAX_PASSIVE
Definition: t4fw_interface.h:7822

FW_PORT_MOD_TYPE_UNKNOWN
@ FW_PORT_MOD_TYPE_UNKNOWN
Definition: t4fw_interface.h:7826

FW_PORT_MOD_TYPE_LR
@ FW_PORT_MOD_TYPE_LR
Definition: t4fw_interface.h:7819

FW_PORT_MOD_TYPE_NONE
@ FW_PORT_MOD_TYPE_NONE
Definition: t4fw_interface.h:7828

FW_PORT_MOD_TYPE_TWINAX_ACTIVE
@ FW_PORT_MOD_TYPE_TWINAX_ACTIVE
Definition: t4fw_interface.h:7823

FW_PORT_MOD_TYPE_NOTSUPPORTED
@ FW_PORT_MOD_TYPE_NOTSUPPORTED
Definition: t4fw_interface.h:7827

FW_PORT_MOD_TYPE_LRM
@ FW_PORT_MOD_TYPE_LRM
Definition: t4fw_interface.h:7824

FW_PORT_MOD_TYPE_ERROR
@ FW_PORT_MOD_TYPE_ERROR
Definition: t4fw_interface.h:7825

FW_PORT_MOD_TYPE_NA
@ FW_PORT_MOD_TYPE_NA
Definition: t4fw_interface.h:7818

FW_PORT_MOD_TYPE_ER
@ FW_PORT_MOD_TYPE_ER
Definition: t4fw_interface.h:7821

fw_flowc_mnem
fw_flowc_mnem
Definition: t4fw_interface.h:1022

FW_FLOWC_MNEM_EOSTATE
@ FW_FLOWC_MNEM_EOSTATE
Definition: t4fw_interface.h:1033

FW_FLOWC_MNEM_RCV_SCALE
@ FW_FLOWC_MNEM_RCV_SCALE
Definition: t4fw_interface.h:1037

FW_FLOWC_MNEM_PFNVFN
@ FW_FLOWC_MNEM_PFNVFN
Definition: t4fw_interface.h:1023

FW_FLOWC_MNEM_CH
@ FW_FLOWC_MNEM_CH
Definition: t4fw_interface.h:1024

FW_FLOWC_MNEM_SNDBUF
@ FW_FLOWC_MNEM_SNDBUF
Definition: t4fw_interface.h:1029

FW_FLOWC_MNEM_RCVNXT
@ FW_FLOWC_MNEM_RCVNXT
Definition: t4fw_interface.h:1028

FW_FLOWC_MNEM_MAX
@ FW_FLOWC_MNEM_MAX
Definition: t4fw_interface.h:1039

FW_FLOWC_MNEM_TXDATAPLEN_MAX
@ FW_FLOWC_MNEM_TXDATAPLEN_MAX
Definition: t4fw_interface.h:1031

FW_FLOWC_MNEM_SND_SCALE
@ FW_FLOWC_MNEM_SND_SCALE
Definition: t4fw_interface.h:1036

FW_FLOWC_MNEM_SCHEDCLASS
@ FW_FLOWC_MNEM_SCHEDCLASS
Definition: t4fw_interface.h:1034

FW_FLOWC_MNEM_IQID
@ FW_FLOWC_MNEM_IQID
Definition: t4fw_interface.h:1026

FW_FLOWC_MNEM_TCPSTATE
@ FW_FLOWC_MNEM_TCPSTATE
Definition: t4fw_interface.h:1032

FW_FLOWC_MNEM_DCBPRIO
@ FW_FLOWC_MNEM_DCBPRIO
Definition: t4fw_interface.h:1035

FW_FLOWC_MNEM_ULP_MODE
@ FW_FLOWC_MNEM_ULP_MODE
Definition: t4fw_interface.h:1038

FW_FLOWC_MNEM_SNDNXT
@ FW_FLOWC_MNEM_SNDNXT
Definition: t4fw_interface.h:1027

FW_FLOWC_MNEM_MSS
@ FW_FLOWC_MNEM_MSS
Definition: t4fw_interface.h:1030

FW_FLOWC_MNEM_PORT
@ FW_FLOWC_MNEM_PORT
Definition: t4fw_interface.h:1025

FW_PORT_CAP32_SPEED_50G
#define FW_PORT_CAP32_SPEED_50G
Definition: t4fw_interface.h:7202

fw_params_param_dev_bypass
fw_params_param_dev_bypass
Definition: t4fw_interface.h:4850

FW_PARAMS_PARAM_DEV_BYPASS_NORMAL
@ FW_PARAMS_PARAM_DEV_BYPASS_NORMAL
Definition: t4fw_interface.h:4859

FW_PARAMS_PARAM_DEV_BYPASS_BYPASS
@ FW_PARAMS_PARAM_DEV_BYPASS_BYPASS
Definition: t4fw_interface.h:4861

FW_PARAMS_PARAM_DEV_BYPASS_DROP
@ FW_PARAMS_PARAM_DEV_BYPASS_DROP
Definition: t4fw_interface.h:4860

FW_PARAMS_PARAM_DEV_BYPASS_PFAIL
@ FW_PARAMS_PARAM_DEV_BYPASS_PFAIL
Definition: t4fw_interface.h:4854

FW_PARAMS_PARAM_DEV_BYPASS_CURRENT
@ FW_PARAMS_PARAM_DEV_BYPASS_CURRENT
Definition: t4fw_interface.h:4855

fw_chnet_addr_type
fw_chnet_addr_type
Definition: t4fw_interface.h:2884

FW_CHNET_ADDR_TYPE_IPV4
@ FW_CHNET_ADDR_TYPE_IPV4
Definition: t4fw_interface.h:2886

FW_CHNET_ADDR_TYPE_IPV6
@ FW_CHNET_ADDR_TYPE_IPV6
Definition: t4fw_interface.h:2887

FW_CHNET_ADDD_TYPE_NONE
@ FW_CHNET_ADDD_TYPE_NONE
Definition: t4fw_interface.h:2885

fw_ri_stag_type
fw_ri_stag_type
Definition: t4fw_interface.h:1267

FW_RI_STAG_SMR
@ FW_RI_STAG_SMR
Definition: t4fw_interface.h:1269

FW_RI_STAG_MW
@ FW_RI_STAG_MW
Definition: t4fw_interface.h:1270

FW_RI_STAG_MW_RELAXED
@ FW_RI_STAG_MW_RELAXED
Definition: t4fw_interface.h:1271

FW_RI_STAG_NSMR
@ FW_RI_STAG_NSMR
Definition: t4fw_interface.h:1268

fw_port_diag_ops
fw_port_diag_ops
Definition: t4fw_interface.h:7375

FW_PORT_DIAGS_TEMP
@ FW_PORT_DIAGS_TEMP
Definition: t4fw_interface.h:7376

FW_PORT_DIAGS_TX_POWER
@ FW_PORT_DIAGS_TX_POWER
Definition: t4fw_interface.h:7377

FW_PORT_DIAGS_RX_POWER
@ FW_PORT_DIAGS_RX_POWER
Definition: t4fw_interface.h:7378

FW_PORT_DIAGS_TX_DIS
@ FW_PORT_DIAGS_TX_DIS
Definition: t4fw_interface.h:7379

FW_DEVLOG_FMT_LEN
#define FW_DEVLOG_FMT_LEN
Definition: t4fw_interface.h:8791

fw_msg_wr_type
fw_msg_wr_type
Definition: t4fw_interface.h:2890

FW_MSG_WR_TYPE_RPL
@ FW_MSG_WR_TYPE_RPL
Definition: t4fw_interface.h:2891

FW_MSG_WR_TYPE_PLD
@ FW_MSG_WR_TYPE_PLD
Definition: t4fw_interface.h:2893

FW_MSG_WR_TYPE_ERR
@ FW_MSG_WR_TYPE_ERR
Definition: t4fw_interface.h:2892

fw_vi_mac_result
fw_vi_mac_result
Definition: t4fw_interface.h:6673

FW_VI_MAC_R_SUCCESS
@ FW_VI_MAC_R_SUCCESS
Definition: t4fw_interface.h:6674

FW_VI_MAC_R_F_ACL_CHECK
@ FW_VI_MAC_R_F_ACL_CHECK
Definition: t4fw_interface.h:6677

FW_VI_MAC_R_SMAC_FAIL
@ FW_VI_MAC_R_SMAC_FAIL
Definition: t4fw_interface.h:6676

FW_VI_MAC_R_F_NONEXISTENT_NOMEM
@ FW_VI_MAC_R_F_NONEXISTENT_NOMEM
Definition: t4fw_interface.h:6675

fw_ri_init_rqeqid_srq
fw_ri_init_rqeqid_srq
Definition: t4fw_interface.h:2093

FW_RI_INIT_RQEQID_SRQ
@ FW_RI_INIT_RQEQID_SRQ
Definition: t4fw_interface.h:2094

fw_foiscsi_auth_method
fw_foiscsi_auth_method
Definition: t4fw_interface.h:2295

FW_FOISCSI_AUTH_METHOD_CHAP
@ FW_FOISCSI_AUTH_METHOD_CHAP
Definition: t4fw_interface.h:2297

FW_FOISCSI_AUTH_METHOD_NONE
@ FW_FOISCSI_AUTH_METHOD_NONE
Definition: t4fw_interface.h:2296

FW_FOISCSI_AUTH_METHOD_CHAP_FST
@ FW_FOISCSI_AUTH_METHOD_CHAP_FST
Definition: t4fw_interface.h:2298

FW_FOISCSI_AUTH_METHOD_CHAP_SEC
@ FW_FOISCSI_AUTH_METHOD_CHAP_SEC
Definition: t4fw_interface.h:2299

fw_ldst_func_access_ctl
fw_ldst_func_access_ctl
Definition: t4fw_interface.h:4273

FW_LDST_FUNC_ACC_CTL_FID
@ FW_LDST_FUNC_ACC_CTL_FID
Definition: t4fw_interface.h:4275

FW_LDST_FUNC_ACC_CTL_VIID
@ FW_LDST_FUNC_ACC_CTL_VIID
Definition: t4fw_interface.h:4274

fw_diag_cmd_type
fw_diag_cmd_type
Definition: t4fw_interface.h:9664

FW_DIAG_CMD_TYPE_OFLDIAG
@ FW_DIAG_CMD_TYPE_OFLDIAG
Definition: t4fw_interface.h:9665

FW_DIAG_CMD_TYPE_MEM_TEST_DIAG
@ FW_DIAG_CMD_TYPE_MEM_TEST_DIAG
Definition: t4fw_interface.h:9666

fw_hdr_chip
fw_hdr_chip
Definition: t4fw_interface.h:9969

FW_HDR_CHIP_T5
@ FW_HDR_CHIP_T5
Definition: t4fw_interface.h:9971

FW_HDR_CHIP_T4
@ FW_HDR_CHIP_T4
Definition: t4fw_interface.h:9970

FW_HDR_CHIP_T6
@ FW_HDR_CHIP_T6
Definition: t4fw_interface.h:9972

fw_ri_res_type
fw_ri_res_type
Definition: t4fw_interface.h:1527

FW_RI_RES_TYPE_SRQ
@ FW_RI_RES_TYPE_SRQ
Definition: t4fw_interface.h:1531

FW_RI_RES_TYPE_SQ
@ FW_RI_RES_TYPE_SQ
Definition: t4fw_interface.h:1528

FW_RI_RES_TYPE_RQ
@ FW_RI_RES_TYPE_RQ
Definition: t4fw_interface.h:1529

FW_RI_RES_TYPE_CQ
@ FW_RI_RES_TYPE_CQ
Definition: t4fw_interface.h:1530

fw_cmd_cap
fw_cmd_cap
Definition: t4fw_interface.h:4171

FW_CMD_CAP_PORTPROMISC
@ FW_CMD_CAP_PORTPROMISC
Definition: t4fw_interface.h:4175

FW_CMD_CAP_PORTSTATS
@ FW_CMD_CAP_PORTSTATS
Definition: t4fw_interface.h:4176

FW_CMD_CAP_VF
@ FW_CMD_CAP_VF
Definition: t4fw_interface.h:4177

FW_CMD_CAP_PF
@ FW_CMD_CAP_PF
Definition: t4fw_interface.h:4172

FW_CMD_CAP_PORT
@ FW_CMD_CAP_PORT
Definition: t4fw_interface.h:4174

FW_CMD_CAP_DMAQ
@ FW_CMD_CAP_DMAQ
Definition: t4fw_interface.h:4173

fw_caps_config_switch
fw_caps_config_switch
Definition: t4fw_interface.h:4653

FW_CAPS_CONFIG_SWITCH_EGRESS
@ FW_CAPS_CONFIG_SWITCH_EGRESS
Definition: t4fw_interface.h:4655

FW_CAPS_CONFIG_SWITCH_INGRESS
@ FW_CAPS_CONFIG_SWITCH_INGRESS
Definition: t4fw_interface.h:4654

fw_port_type
fw_port_type
Definition: t4fw_interface.h:7780

FW_PORT_TYPE_BT_XFI
@ FW_PORT_TYPE_BT_XFI
Definition: t4fw_interface.h:7784

FW_PORT_TYPE_NONE
@ FW_PORT_TYPE_NONE
Definition: t4fw_interface.h:7804

FW_PORT_TYPE_KX
@ FW_PORT_TYPE_KX
Definition: t4fw_interface.h:7788

FW_PORT_TYPE_SFP28
@ FW_PORT_TYPE_SFP28
Definition: t4fw_interface.h:7801

FW_PORT_TYPE_QSFP
@ FW_PORT_TYPE_QSFP
Definition: t4fw_interface.h:7795

FW_PORT_TYPE_CR2_QSFP
@ FW_PORT_TYPE_CR2_QSFP
Definition: t4fw_interface.h:7800

FW_PORT_TYPE_BT_SGMII
@ FW_PORT_TYPE_BT_SGMII
Definition: t4fw_interface.h:7783

FW_PORT_TYPE_KR4_100G
@ FW_PORT_TYPE_KR4_100G
Definition: t4fw_interface.h:7797

FW_PORT_TYPE_BP_AP
@ FW_PORT_TYPE_BP_AP
Definition: t4fw_interface.h:7791

FW_PORT_TYPE_FIBER_XFI
@ FW_PORT_TYPE_FIBER_XFI
Definition: t4fw_interface.h:7781

FW_PORT_TYPE_QSFP_10G
@ FW_PORT_TYPE_QSFP_10G
Definition: t4fw_interface.h:7793

FW_PORT_TYPE_KR_SFP28
@ FW_PORT_TYPE_KR_SFP28
Definition: t4fw_interface.h:7802

FW_PORT_TYPE_FIBER_XAUI
@ FW_PORT_TYPE_FIBER_XAUI
Definition: t4fw_interface.h:7782

FW_PORT_TYPE_BP4_AP
@ FW_PORT_TYPE_BP4_AP
Definition: t4fw_interface.h:7792

FW_PORT_TYPE_QSA
@ FW_PORT_TYPE_QSA
Definition: t4fw_interface.h:7794

FW_PORT_TYPE_BT_XAUI
@ FW_PORT_TYPE_BT_XAUI
Definition: t4fw_interface.h:7785

FW_PORT_TYPE_CX4
@ FW_PORT_TYPE_CX4
Definition: t4fw_interface.h:7787

FW_PORT_TYPE_KR
@ FW_PORT_TYPE_KR
Definition: t4fw_interface.h:7789

FW_PORT_TYPE_SFP
@ FW_PORT_TYPE_SFP
Definition: t4fw_interface.h:7790

FW_PORT_TYPE_BP40_BA
@ FW_PORT_TYPE_BP40_BA
Definition: t4fw_interface.h:7796

FW_PORT_TYPE_KR_XLAUI
@ FW_PORT_TYPE_KR_XLAUI
Definition: t4fw_interface.h:7803

FW_PORT_TYPE_CR_QSFP
@ FW_PORT_TYPE_CR_QSFP
Definition: t4fw_interface.h:7799

FW_PORT_TYPE_CR4_QSFP
@ FW_PORT_TYPE_CR4_QSFP
Definition: t4fw_interface.h:7798

FW_PORT_TYPE_KX4
@ FW_PORT_TYPE_KX4
Definition: t4fw_interface.h:7786

fw_port_dcb_type
fw_port_dcb_type
Definition: t4fw_interface.h:7359

FW_PORT_DCB_TYPE_PFC
@ FW_PORT_DCB_TYPE_PFC
Definition: t4fw_interface.h:7363

FW_PORT_DCB_TYPE_CONTROL
@ FW_PORT_DCB_TYPE_CONTROL
Definition: t4fw_interface.h:7365

FW_PORT_DCB_TYPE_PGID
@ FW_PORT_DCB_TYPE_PGID
Definition: t4fw_interface.h:7360

FW_PORT_DCB_TYPE_PRIORATE
@ FW_PORT_DCB_TYPE_PRIORATE
Definition: t4fw_interface.h:7362

FW_PORT_DCB_TYPE_APP_ID
@ FW_PORT_DCB_TYPE_APP_ID
Definition: t4fw_interface.h:7364

FW_PORT_DCB_TYPE_PGRATE
@ FW_PORT_DCB_TYPE_PGRATE
Definition: t4fw_interface.h:7361

fw_dcb_app_tlv_sf
fw_dcb_app_tlv_sf
Definition: t4fw_interface.h:7333

FW_DCB_APP_SF_ETHERTYPE
@ FW_DCB_APP_SF_ETHERTYPE
Definition: t4fw_interface.h:7334

FW_DCB_APP_SF_SOCKET_UDP
@ FW_DCB_APP_SF_SOCKET_UDP
Definition: t4fw_interface.h:7336

FW_DCB_APP_SF_SOCKET_TCP
@ FW_DCB_APP_SF_SOCKET_TCP
Definition: t4fw_interface.h:7335

FW_DCB_APP_SF_SOCKET_ALL
@ FW_DCB_APP_SF_SOCKET_ALL
Definition: t4fw_interface.h:7337

fw_params_param_dev_ktls_hw
fw_params_param_dev_ktls_hw
Definition: t4fw_interface.h:4887

FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE
@ FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE
Definition: t4fw_interface.h:4889

FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE
@ FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE
Definition: t4fw_interface.h:4891

FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE
@ FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE
Definition: t4fw_interface.h:4888

FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE
@ FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE
Definition: t4fw_interface.h:4890

fw_ldst_mdio_vsc8634_aid
fw_ldst_mdio_vsc8634_aid
Definition: t4fw_interface.h:4262

FW_LDST_MDIO_VS_GPIO
@ FW_LDST_MDIO_VS_GPIO
Definition: t4fw_interface.h:4265

FW_LDST_MDIO_VS_EXTENDED
@ FW_LDST_MDIO_VS_EXTENDED
Definition: t4fw_interface.h:4264

FW_LDST_MDIO_VS_STANDARD
@ FW_LDST_MDIO_VS_STANDARD
Definition: t4fw_interface.h:4263

fw_flowc_mnem_eostate
fw_flowc_mnem_eostate
Definition: t4fw_interface.h:1011

FW_FLOWC_MNEM_EOSTATE_CLOSED
@ FW_FLOWC_MNEM_EOSTATE_CLOSED
Definition: t4fw_interface.h:1012

FW_FLOWC_MNEM_EOSTATE_CLOSING
@ FW_FLOWC_MNEM_EOSTATE_CLOSING
Definition: t4fw_interface.h:1014

FW_FLOWC_MNEM_EOSTATE_ABORTING
@ FW_FLOWC_MNEM_EOSTATE_ABORTING
Definition: t4fw_interface.h:1017

FW_FLOWC_MNEM_EOSTATE_ESTABLISHED
@ FW_FLOWC_MNEM_EOSTATE_ESTABLISHED
Definition: t4fw_interface.h:1013

fw_wr_opcodes
fw_wr_opcodes
Definition: t4fw_interface.h:97

FW_RI_RDMA_WRITE_CMPL_WR
@ FW_RI_RDMA_WRITE_CMPL_WR
Definition: t4fw_interface.h:122

FW_COISCSI_TGT_WR
@ FW_COISCSI_TGT_WR
Definition: t4fw_interface.h:147

FW_FRAG_WR
@ FW_FRAG_WR
Definition: t4fw_interface.h:98

FW_FOISCSI_CTRL_WR
@ FW_FOISCSI_CTRL_WR
Definition: t4fw_interface.h:130

FW_RI_SEND_WR
@ FW_RI_SEND_WR
Definition: t4fw_interface.h:116

FW_ULPTX_WR
@ FW_ULPTX_WR
Definition: t4fw_interface.h:100

FW_SCSI_TGT_XMIT_WR
@ FW_SCSI_TGT_XMIT_WR
Definition: t4fw_interface.h:138

FW_ETH_TX_PKTS_WR
@ FW_ETH_TX_PKTS_WR
Definition: t4fw_interface.h:104

FW_POFCOE_TCB_WR
@ FW_POFCOE_TCB_WR
Definition: t4fw_interface.h:140

FW_CRYPTO_LOOKASIDE_WR
@ FW_CRYPTO_LOOKASIDE_WR
Definition: t4fw_interface.h:146

FW_RI_FR_NSMR_TPTE_WR
@ FW_RI_FR_NSMR_TPTE_WR
Definition: t4fw_interface.h:121

FW_PTP_TX_PKT_WR
@ FW_PTP_TX_PKT_WR
Definition: t4fw_interface.h:143

FW_ETH_TX_PKTS2_WR
@ FW_ETH_TX_PKTS2_WR
Definition: t4fw_interface.h:105

FW_SCSI_TGT_RSP_WR
@ FW_SCSI_TGT_RSP_WR
Definition: t4fw_interface.h:139

FW_SCSI_READ_WR
@ FW_SCSI_READ_WR
Definition: t4fw_interface.h:134

FW_POFCOE_ULPTX_WR
@ FW_POFCOE_ULPTX_WR
Definition: t4fw_interface.h:141

FW_FILTER2_WR
@ FW_FILTER2_WR
Definition: t4fw_interface.h:153

FW_ISNS_XMIT_WR
@ FW_ISNS_XMIT_WR
Definition: t4fw_interface.h:152

FW_FILTER_WR
@ FW_FILTER_WR
Definition: t4fw_interface.h:99

FW_RI_RECV_WR
@ FW_RI_RECV_WR
Definition: t4fw_interface.h:118

FW_TLSTX_DATA_WR
@ FW_TLSTX_DATA_WR
Definition: t4fw_interface.h:144

FW_SCSI_TGT_ACC_WR
@ FW_SCSI_TGT_ACC_WR
Definition: t4fw_interface.h:137

FW_ETH_TX_PKTS_VM_WR
@ FW_ETH_TX_PKTS_VM_WR
Definition: t4fw_interface.h:113

FW_OFLD_CONNECTION_WR
@ FW_OFLD_CONNECTION_WR
Definition: t4fw_interface.h:108

FW_OFLD_TX_DATA_WR
@ FW_OFLD_TX_DATA_WR
Definition: t4fw_interface.h:110

FW_RI_SEND_IMMEDIATE_WR
@ FW_RI_SEND_IMMEDIATE_WR
Definition: t4fw_interface.h:124

FW_FCOE_ELS_CT_WR
@ FW_FCOE_ELS_CT_WR
Definition: t4fw_interface.h:132

FW_RI_BIND_MW_WR
@ FW_RI_BIND_MW_WR
Definition: t4fw_interface.h:119

FW_ETH_TX_PKT_WR
@ FW_ETH_TX_PKT_WR
Definition: t4fw_interface.h:102

FW_FLOWC_WR
@ FW_FLOWC_WR
Definition: t4fw_interface.h:109

FW_RI_ATOMIC_WR
@ FW_RI_ATOMIC_WR
Definition: t4fw_interface.h:125

FW_ETH_TX_EO_WR
@ FW_ETH_TX_EO_WR
Definition: t4fw_interface.h:106

FW_FOISCSI_NODE_WR
@ FW_FOISCSI_NODE_WR
Definition: t4fw_interface.h:129

FW_RI_RDMA_READ_WR
@ FW_RI_RDMA_READ_WR
Definition: t4fw_interface.h:117

FW_TLS_TUNNEL_OFLD_WR
@ FW_TLS_TUNNEL_OFLD_WR
Definition: t4fw_interface.h:145

FW_RI_INV_LSTAG_WR
@ FW_RI_INV_LSTAG_WR
Definition: t4fw_interface.h:123

FW_ETH_TX_PKT_VM_WR
@ FW_ETH_TX_PKT_VM_WR
Definition: t4fw_interface.h:112

FW_CMD_WR
@ FW_CMD_WR
Definition: t4fw_interface.h:111

FW_SCSI_ABRT_CLS_WR
@ FW_SCSI_ABRT_CLS_WR
Definition: t4fw_interface.h:136

FW_RI_WR
@ FW_RI_WR
Definition: t4fw_interface.h:126

FW_LASTC2E_WR
@ FW_LASTC2E_WR
Definition: t4fw_interface.h:154

FW_EQ_FLUSH_WR
@ FW_EQ_FLUSH_WR
Definition: t4fw_interface.h:107

FW_RDEV_WR
@ FW_RDEV_WR
Definition: t4fw_interface.h:128

FW_CHNET_IFCONF_WR
@ FW_CHNET_IFCONF_WR
Definition: t4fw_interface.h:127

FW_FOISCSI_CHAP_WR
@ FW_FOISCSI_CHAP_WR
Definition: t4fw_interface.h:131

FW_RI_RDMA_WRITE_WR
@ FW_RI_RDMA_WRITE_WR
Definition: t4fw_interface.h:115

FW_ETH_TX_PKT2_WR
@ FW_ETH_TX_PKT2_WR
Definition: t4fw_interface.h:103

FW_TP_WR
@ FW_TP_WR
Definition: t4fw_interface.h:101

FW_COISCSI_STATS_WR
@ FW_COISCSI_STATS_WR
Definition: t4fw_interface.h:150

FW_ISCSI_TX_DATA_WR
@ FW_ISCSI_TX_DATA_WR
Definition: t4fw_interface.h:142

FW_RI_FR_NSMR_WR
@ FW_RI_FR_NSMR_WR
Definition: t4fw_interface.h:120

FW_RI_RES_WR
@ FW_RI_RES_WR
Definition: t4fw_interface.h:114

FW_ISNS_WR
@ FW_ISNS_WR
Definition: t4fw_interface.h:151

FW_SCSI_CMD_WR
@ FW_SCSI_CMD_WR
Definition: t4fw_interface.h:135

FW_SCSI_WRITE_WR
@ FW_SCSI_WRITE_WR
Definition: t4fw_interface.h:133

FW_COISCSI_TGT_CONN_WR
@ FW_COISCSI_TGT_CONN_WR
Definition: t4fw_interface.h:148

FW_COISCSI_TGT_XMIT_WR
@ FW_COISCSI_TGT_XMIT_WR
Definition: t4fw_interface.h:149

fw_caps_config_toe
fw_caps_config_toe
Definition: t4fw_interface.h:4668

FW_CAPS_CONFIG_TOE
@ FW_CAPS_CONFIG_TOE
Definition: t4fw_interface.h:4669

fw_ri_cqe_err
fw_ri_cqe_err
Definition: t4fw_interface.h:1285

FW_RI_CQE_ERR_OUT_OF_RQE
@ FW_RI_CQE_ERR_OUT_OF_RQE
Definition: t4fw_interface.h:1301

FW_RI_CQE_ERR_RDMA_VERSION
@ FW_RI_CQE_ERR_RDMA_VERSION
Definition: t4fw_interface.h:1303

FW_RI_CQE_ERR_ECC_PSTAG
@ FW_RI_CQE_ERR_ECC_PSTAG
Definition: t4fw_interface.h:1296

FW_RI_CQE_ERR_INTERNAL_ERR
@ FW_RI_CQE_ERR_INTERNAL_ERR
Definition: t4fw_interface.h:1313

FW_RI_CQE_ERR_SUCCESS
@ FW_RI_CQE_ERR_SUCCESS
Definition: t4fw_interface.h:1286

FW_RI_CQE_ERR_STAG
@ FW_RI_CQE_ERR_STAG
Definition: t4fw_interface.h:1287

FW_RI_CQE_ERR_PBL_ADDR_BOUND
@ FW_RI_CQE_ERR_PBL_ADDR_BOUND
Definition: t4fw_interface.h:1297

FW_RI_CQE_ERR_WRAP
@ FW_RI_CQE_ERR_WRAP
Definition: t4fw_interface.h:1291

FW_RI_CQE_ERR_TBIT
@ FW_RI_CQE_ERR_TBIT
Definition: t4fw_interface.h:1307

FW_RI_CQE_ERR_RQE_ADDR_BOUND
@ FW_RI_CQE_ERR_RQE_ADDR_BOUND
Definition: t4fw_interface.h:1312

FW_RI_CQE_ERR_CRC
@ FW_RI_CQE_ERR_CRC
Definition: t4fw_interface.h:1298

FW_RI_CQE_ERR_OPCODE
@ FW_RI_CQE_ERR_OPCODE
Definition: t4fw_interface.h:1304

FW_RI_CQE_ERR_INVALIDATE_SHARED_MR
@ FW_RI_CQE_ERR_INVALIDATE_SHARED_MR
Definition: t4fw_interface.h:1293

FW_RI_CQE_ERR_DDP_QUEUE_NUM
@ FW_RI_CQE_ERR_DDP_QUEUE_NUM
Definition: t4fw_interface.h:1305

FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND
@ FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND
Definition: t4fw_interface.h:1294

FW_RI_CQE_ERR_MARKER
@ FW_RI_CQE_ERR_MARKER
Definition: t4fw_interface.h:1299

FW_RI_CQE_ERR_MSN
@ FW_RI_CQE_ERR_MSN
Definition: t4fw_interface.h:1306

FW_RI_CQE_ERR_PDID
@ FW_RI_CQE_ERR_PDID
Definition: t4fw_interface.h:1288

FW_RI_CQE_ERR_MSN_GAP
@ FW_RI_CQE_ERR_MSN_GAP
Definition: t4fw_interface.h:1309

FW_RI_CQE_ERR_PDU_LEN_ERR
@ FW_RI_CQE_ERR_PDU_LEN_ERR
Definition: t4fw_interface.h:1300

FW_RI_CQE_ERR_MO
@ FW_RI_CQE_ERR_MO
Definition: t4fw_interface.h:1308

FW_RI_CQE_ERR_ACCESS
@ FW_RI_CQE_ERR_ACCESS
Definition: t4fw_interface.h:1290

FW_RI_CQE_ERR_QPID
@ FW_RI_CQE_ERR_QPID
Definition: t4fw_interface.h:1289

FW_RI_CQE_ERR_MSN_RANGE
@ FW_RI_CQE_ERR_MSN_RANGE
Definition: t4fw_interface.h:1310

FW_RI_CQE_ERR_IRD_OVERFLOW
@ FW_RI_CQE_ERR_IRD_OVERFLOW
Definition: t4fw_interface.h:1311

FW_RI_CQE_ERR_DDP_VERSION
@ FW_RI_CQE_ERR_DDP_VERSION
Definition: t4fw_interface.h:1302

FW_RI_CQE_ERR_BOUND
@ FW_RI_CQE_ERR_BOUND
Definition: t4fw_interface.h:1292

FW_RI_CQE_ERR_ECC
@ FW_RI_CQE_ERR_ECC
Definition: t4fw_interface.h:1295

M_FW_PORT_CMD_PTYPE
#define M_FW_PORT_CMD_PTYPE
Definition: t4fw_interface.h:7614

fw_sched_params_level
fw_sched_params_level
Definition: t4fw_interface.h:8736

FW_SCHED_PARAMS_LEVEL_CL_RL
@ FW_SCHED_PARAMS_LEVEL_CL_RL
Definition: t4fw_interface.h:8737

FW_SCHED_PARAMS_LEVEL_CH_RL
@ FW_SCHED_PARAMS_LEVEL_CH_RL
Definition: t4fw_interface.h:8739

FW_SCHED_PARAMS_LEVEL_CL_WRR
@ FW_SCHED_PARAMS_LEVEL_CL_WRR
Definition: t4fw_interface.h:8738

fw_caps_config_rdma
fw_caps_config_rdma
Definition: t4fw_interface.h:4672

FW_CAPS_CONFIG_RDMA_RDDP
@ FW_CAPS_CONFIG_RDMA_RDDP
Definition: t4fw_interface.h:4673

FW_CAPS_CONFIG_RDMA_RDMAC
@ FW_CAPS_CONFIG_RDMA_RDMAC
Definition: t4fw_interface.h:4674

fw_watchdog_actions
fw_watchdog_actions
Definition: t4fw_interface.h:8883

FW_WATCHDOG_ACTION_TMPCHK
@ FW_WATCHDOG_ACTION_TMPCHK
Definition: t4fw_interface.h:8887

FW_WATCHDOG_ACTION_FLR
@ FW_WATCHDOG_ACTION_FLR
Definition: t4fw_interface.h:8885

FW_WATCHDOG_ACTION_SHUTDOWN
@ FW_WATCHDOG_ACTION_SHUTDOWN
Definition: t4fw_interface.h:8884

FW_WATCHDOG_ACTION_MAX
@ FW_WATCHDOG_ACTION_MAX
Definition: t4fw_interface.h:8890

FW_WATCHDOG_ACTION_BYPASS
@ FW_WATCHDOG_ACTION_BYPASS
Definition: t4fw_interface.h:8886

FW_WATCHDOG_ACTION_PAUSEOFF
@ FW_WATCHDOG_ACTION_PAUSEOFF
Definition: t4fw_interface.h:8888

FW_EPHY_HDR_MAGIC
@ FW_EPHY_HDR_MAGIC
Definition: t4fw_interface.h:10086

fw_params_mnem
fw_params_mnem
Definition: t4fw_interface.h:4759

FW_PARAMS_MNEM_DMAQ
@ FW_PARAMS_MNEM_DMAQ
Definition: t4fw_interface.h:4763

FW_PARAMS_MNEM_LAST
@ FW_PARAMS_MNEM_LAST
Definition: t4fw_interface.h:4765

FW_PARAMS_MNEM_DEV
@ FW_PARAMS_MNEM_DEV
Definition: t4fw_interface.h:4760

FW_PARAMS_MNEM_CHNET
@ FW_PARAMS_MNEM_CHNET
Definition: t4fw_interface.h:4764

FW_PARAMS_MNEM_PFVF
@ FW_PARAMS_MNEM_PFVF
Definition: t4fw_interface.h:4761

FW_PARAMS_MNEM_REG
@ FW_PARAMS_MNEM_REG
Definition: t4fw_interface.h:4762

fw_diag_cmd_memdiag_status
fw_diag_cmd_memdiag_status
Definition: t4fw_interface.h:9691

FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING
@ FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING
Definition: t4fw_interface.h:9693

FW_DIAG_CMD_MEMDIAG_STATUS_PASSED
@ FW_DIAG_CMD_MEMDIAG_STATUS_PASSED
Definition: t4fw_interface.h:9695

FW_DIAG_CMD_MEMDIAG_STATUS_NONE
@ FW_DIAG_CMD_MEMDIAG_STATUS_NONE
Definition: t4fw_interface.h:9692

FW_DIAG_CMD_MEMDIAG_STATUS_FAILED
@ FW_DIAG_CMD_MEMDIAG_STATUS_FAILED
Definition: t4fw_interface.h:9694

fw_memtype
fw_memtype
Definition: t4fw_interface.h:83

FW_MEMTYPE_EDC1
@ FW_MEMTYPE_EDC1
Definition: t4fw_interface.h:85

FW_MEMTYPE_HMA
@ FW_MEMTYPE_HMA
Definition: t4fw_interface.h:90

FW_MEMTYPE_EXTMEM1
@ FW_MEMTYPE_EXTMEM1
Definition: t4fw_interface.h:89

FW_MEMTYPE_FLASH
@ FW_MEMTYPE_FLASH
Definition: t4fw_interface.h:87

FW_MEMTYPE_EXTMEM
@ FW_MEMTYPE_EXTMEM
Definition: t4fw_interface.h:86

FW_MEMTYPE_INTERNAL
@ FW_MEMTYPE_INTERNAL
Definition: t4fw_interface.h:88

FW_MEMTYPE_EDC0
@ FW_MEMTYPE_EDC0
Definition: t4fw_interface.h:84

fw_params_param_pfvf
fw_params_param_pfvf
Definition: t4fw_interface.h:4902

FW_PARAMS_PARAM_PFVF_TDDP_START
@ FW_PARAMS_PARAM_PFVF_TDDP_START
Definition: t4fw_interface.h:4912

FW_PARAMS_PARAM_PFVF_SQRQ_START
@ FW_PARAMS_PARAM_PFVF_SQRQ_START
Definition: t4fw_interface.h:4924

FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START
@ FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START
Definition: t4fw_interface.h:4940

FW_PARAMS_PARAM_PFVF_ROUTE_START
@ FW_PARAMS_PARAM_PFVF_ROUTE_START
Definition: t4fw_interface.h:4904

FW_PARAMS_PARAM_PFVF_FILTER_END
@ FW_PARAMS_PARAM_PFVF_FILTER_END
Definition: t4fw_interface.h:4909

FW_PARAMS_PARAM_PFVF_L2T_START
@ FW_PARAMS_PARAM_PFVF_L2T_START
Definition: t4fw_interface.h:4922

FW_PARAMS_PARAM_PFVF_ISCSI_START
@ FW_PARAMS_PARAM_PFVF_ISCSI_START
Definition: t4fw_interface.h:4914

FW_PARAMS_PARAM_PFVF_HPFILTER_START
@ FW_PARAMS_PARAM_PFVF_HPFILTER_START
Definition: t4fw_interface.h:4945

FW_PARAMS_PARAM_PFVF_PBL_END
@ FW_PARAMS_PARAM_PFVF_PBL_END
Definition: t4fw_interface.h:4921

FW_PARAMS_PARAM_PFVF_CLIP_START
@ FW_PARAMS_PARAM_PFVF_CLIP_START
Definition: t4fw_interface.h:4906

FW_PARAMS_PARAM_PFVF_STAG_START
@ FW_PARAMS_PARAM_PFVF_STAG_START
Definition: t4fw_interface.h:4916

FW_PARAMS_PARAM_PFVF_IQFLINT_START
@ FW_PARAMS_PARAM_PFVF_IQFLINT_START
Definition: t4fw_interface.h:4936

FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH
@ FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH
Definition: t4fw_interface.h:4930

FW_PARAMS_PARAM_PFVF_OCQ_END
@ FW_PARAMS_PARAM_PFVF_OCQ_END
Definition: t4fw_interface.h:4934

FW_PARAMS_PARAM_PFVF_SERVER_END
@ FW_PARAMS_PARAM_PFVF_SERVER_END
Definition: t4fw_interface.h:4911

FW_PARAMS_PARAM_PFVF_TLS_START
@ FW_PARAMS_PARAM_PFVF_TLS_START
Definition: t4fw_interface.h:4947

FW_PARAMS_PARAM_PFVF_CPMASK
@ FW_PARAMS_PARAM_PFVF_CPMASK
Definition: t4fw_interface.h:4932

FW_PARAMS_PARAM_PFVF_RSSKEYINFO
@ FW_PARAMS_PARAM_PFVF_RSSKEYINFO
Definition: t4fw_interface.h:4951

FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP
@ FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP
Definition: t4fw_interface.h:4944

FW_PARAMS_PARAM_PFVF_RQ_END
@ FW_PARAMS_PARAM_PFVF_RQ_END
Definition: t4fw_interface.h:4919

FW_PARAMS_PARAM_PFVF_SRQ_END
@ FW_PARAMS_PARAM_PFVF_SRQ_END
Definition: t4fw_interface.h:4929

FW_PARAMS_PARAM_PFVF_STAG_END
@ FW_PARAMS_PARAM_PFVF_STAG_END
Definition: t4fw_interface.h:4917

FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR
@ FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR
Definition: t4fw_interface.h:4956

FW_PARAMS_PARAM_PFVF_TLS_END
@ FW_PARAMS_PARAM_PFVF_TLS_END
Definition: t4fw_interface.h:4948

FW_PARAMS_PARAM_PFVF_ISCSI_END
@ FW_PARAMS_PARAM_PFVF_ISCSI_END
Definition: t4fw_interface.h:4915

FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END
@ FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END
Definition: t4fw_interface.h:4955

FW_PARAMS_PARAM_PFVF_VIID
@ FW_PARAMS_PARAM_PFVF_VIID
Definition: t4fw_interface.h:4931

FW_PARAMS_PARAM_PFVF_ETHOFLD_END
@ FW_PARAMS_PARAM_PFVF_ETHOFLD_END
Definition: t4fw_interface.h:4943

FW_PARAMS_PARAM_PFVF_ROUTE_END
@ FW_PARAMS_PARAM_PFVF_ROUTE_END
Definition: t4fw_interface.h:4905

FW_PARAMS_PARAM_PFVF_GET_SMT_START
@ FW_PARAMS_PARAM_PFVF_GET_SMT_START
Definition: t4fw_interface.h:4957

FW_PARAMS_PARAM_PFVF_CLIP_END
@ FW_PARAMS_PARAM_PFVF_CLIP_END
Definition: t4fw_interface.h:4907

FW_PARAMS_PARAM_PFVF_SQRQ_END
@ FW_PARAMS_PARAM_PFVF_SQRQ_END
Definition: t4fw_interface.h:4925

FW_PARAMS_PARAM_PFVF_RQ_START
@ FW_PARAMS_PARAM_PFVF_RQ_START
Definition: t4fw_interface.h:4918

FW_PARAMS_PARAM_PFVF_OCQ_START
@ FW_PARAMS_PARAM_PFVF_OCQ_START
Definition: t4fw_interface.h:4933

FW_PARAMS_PARAM_PFVF_EQ_START
@ FW_PARAMS_PARAM_PFVF_EQ_START
Definition: t4fw_interface.h:4938

FW_PARAMS_PARAM_PFVF_CQ_START
@ FW_PARAMS_PARAM_PFVF_CQ_START
Definition: t4fw_interface.h:4926

FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END
@ FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END
Definition: t4fw_interface.h:4941

FW_PARAMS_PARAM_PFVF_CQ_END
@ FW_PARAMS_PARAM_PFVF_CQ_END
Definition: t4fw_interface.h:4927

FW_PARAMS_PARAM_PFVF_TDDP_END
@ FW_PARAMS_PARAM_PFVF_TDDP_END
Definition: t4fw_interface.h:4913

FW_PARAMS_PARAM_PFVF_HPFILTER_END
@ FW_PARAMS_PARAM_PFVF_HPFILTER_END
Definition: t4fw_interface.h:4946

FW_PARAMS_PARAM_PFVF_SERVER_START
@ FW_PARAMS_PARAM_PFVF_SERVER_START
Definition: t4fw_interface.h:4910

FW_PARAMS_PARAM_PFVF_IQFLINT_END
@ FW_PARAMS_PARAM_PFVF_IQFLINT_END
Definition: t4fw_interface.h:4937

FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE
@ FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE
Definition: t4fw_interface.h:4958

FW_PARAMS_PARAM_PFVF_CONM_MAP
@ FW_PARAMS_PARAM_PFVF_CONM_MAP
Definition: t4fw_interface.h:4935

FW_PARAMS_PARAM_PFVF_EQ_END
@ FW_PARAMS_PARAM_PFVF_EQ_END
Definition: t4fw_interface.h:4939

FW_PARAMS_PARAM_PFVF_ETHOFLD_START
@ FW_PARAMS_PARAM_PFVF_ETHOFLD_START
Definition: t4fw_interface.h:4942

FW_PARAMS_PARAM_PFVF_FILTER_START
@ FW_PARAMS_PARAM_PFVF_FILTER_START
Definition: t4fw_interface.h:4908

FW_PARAMS_PARAM_PFVF_SRQ_START
@ FW_PARAMS_PARAM_PFVF_SRQ_START
Definition: t4fw_interface.h:4928

FW_PARAMS_PARAM_PFVF_RWXCAPS
@ FW_PARAMS_PARAM_PFVF_RWXCAPS
Definition: t4fw_interface.h:4903

FW_PARAMS_PARAM_PFVF_PORT_CAPS32
@ FW_PARAMS_PARAM_PFVF_PORT_CAPS32
Definition: t4fw_interface.h:4953

FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE
@ FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE
Definition: t4fw_interface.h:4952

FW_PARAMS_PARAM_PFVF_L2T_END
@ FW_PARAMS_PARAM_PFVF_L2T_END
Definition: t4fw_interface.h:4923

FW_PARAMS_PARAM_PFVF_RAWF_END
@ FW_PARAMS_PARAM_PFVF_RAWF_END
Definition: t4fw_interface.h:4950

FW_PARAMS_PARAM_PFVF_PBL_START
@ FW_PARAMS_PARAM_PFVF_PBL_START
Definition: t4fw_interface.h:4920

FW_PARAMS_PARAM_PFVF_LINK_STATE
@ FW_PARAMS_PARAM_PFVF_LINK_STATE
Definition: t4fw_interface.h:4959

FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START
@ FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START
Definition: t4fw_interface.h:4954

FW_PARAMS_PARAM_PFVF_RAWF_START
@ FW_PARAMS_PARAM_PFVF_RAWF_START
Definition: t4fw_interface.h:4949

fw_vi_stats_vf_index
fw_vi_stats_vf_index
Definition: t4fw_interface.h:6924

FW_VI_VF_STAT_RX_MCAST_FRAMES_IX
@ FW_VI_VF_STAT_RX_MCAST_FRAMES_IX
Definition: t4fw_interface.h:6937

FW_VI_VF_STAT_RX_BCAST_BYTES_IX
@ FW_VI_VF_STAT_RX_BCAST_BYTES_IX
Definition: t4fw_interface.h:6934

FW_VI_VF_STAT_RX_UCAST_BYTES_IX
@ FW_VI_VF_STAT_RX_UCAST_BYTES_IX
Definition: t4fw_interface.h:6938

FW_VI_VF_STAT_TX_OFLD_BYTES_IX
@ FW_VI_VF_STAT_TX_OFLD_BYTES_IX
Definition: t4fw_interface.h:6932

FW_VI_VF_STAT_RX_MCAST_BYTES_IX
@ FW_VI_VF_STAT_RX_MCAST_BYTES_IX
Definition: t4fw_interface.h:6936

FW_VI_VF_STAT_TX_UCAST_BYTES_IX
@ FW_VI_VF_STAT_TX_UCAST_BYTES_IX
Definition: t4fw_interface.h:6929

FW_VI_VF_STAT_TX_BCAST_BYTES_IX
@ FW_VI_VF_STAT_TX_BCAST_BYTES_IX
Definition: t4fw_interface.h:6925

FW_VI_VF_STAT_TX_DROP_FRAMES_IX
@ FW_VI_VF_STAT_TX_DROP_FRAMES_IX
Definition: t4fw_interface.h:6931

FW_VI_VF_STAT_RX_ERR_FRAMES_IX
@ FW_VI_VF_STAT_RX_ERR_FRAMES_IX
Definition: t4fw_interface.h:6940

FW_VI_VF_STAT_TX_MCAST_BYTES_IX
@ FW_VI_VF_STAT_TX_MCAST_BYTES_IX
Definition: t4fw_interface.h:6927

FW_VI_VF_STAT_TX_BCAST_FRAMES_IX
@ FW_VI_VF_STAT_TX_BCAST_FRAMES_IX
Definition: t4fw_interface.h:6926

FW_VI_VF_STAT_TX_MCAST_FRAMES_IX
@ FW_VI_VF_STAT_TX_MCAST_FRAMES_IX
Definition: t4fw_interface.h:6928

FW_VI_VF_STAT_RX_BCAST_FRAMES_IX
@ FW_VI_VF_STAT_RX_BCAST_FRAMES_IX
Definition: t4fw_interface.h:6935

FW_VI_VF_STAT_TX_OFLD_FRAMES_IX
@ FW_VI_VF_STAT_TX_OFLD_FRAMES_IX
Definition: t4fw_interface.h:6933

FW_VI_VF_STAT_RX_UCAST_FRAMES_IX
@ FW_VI_VF_STAT_RX_UCAST_FRAMES_IX
Definition: t4fw_interface.h:6939

FW_VI_VF_STAT_TX_UCAST_FRAMES_IX
@ FW_VI_VF_STAT_TX_UCAST_FRAMES_IX
Definition: t4fw_interface.h:6930

fw_diag_cmd_memdiag_op
fw_diag_cmd_memdiag_op
Definition: t4fw_interface.h:9683

FW_DIAG_CMD_MEMDIAG_TEST_STOP
@ FW_DIAG_CMD_MEMDIAG_TEST_STOP
Definition: t4fw_interface.h:9685

FW_DIAG_CMD_MEMDIAG_TEST_STATUS
@ FW_DIAG_CMD_MEMDIAG_TEST_STATUS
Definition: t4fw_interface.h:9686

FW_DIAG_CMD_MEMDIAG_TEST_INIT
@ FW_DIAG_CMD_MEMDIAG_TEST_INIT
Definition: t4fw_interface.h:9687

FW_DIAG_CMD_MEMDIAG_TEST_START
@ FW_DIAG_CMD_MEMDIAG_TEST_START
Definition: t4fw_interface.h:9684

fw_params_param_dev_fwcache
fw_params_param_dev_fwcache
Definition: t4fw_interface.h:4894

FW_PARAM_DEV_FWCACHE_FLUSHINV
@ FW_PARAM_DEV_FWCACHE_FLUSHINV
Definition: t4fw_interface.h:4896

FW_PARAM_DEV_FWCACHE_FLUSH
@ FW_PARAM_DEV_FWCACHE_FLUSH
Definition: t4fw_interface.h:4895

fw_params_param_dmaq
fw_params_param_dmaq
Definition: t4fw_interface.h:4974

FW_PARAMS_PARAM_DMAQ_FLM_DCA
@ FW_PARAMS_PARAM_DMAQ_FLM_DCA
Definition: t4fw_interface.h:4986

FW_PARAMS_PARAM_DMAQ_CONM_CTXT
@ FW_PARAMS_PARAM_DMAQ_CONM_CTXT
Definition: t4fw_interface.h:4985

FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL
@ FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL
Definition: t4fw_interface.h:4980

FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU
@ FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU
Definition: t4fw_interface.h:4975

FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX
@ FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX
Definition: t4fw_interface.h:4984

FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH
@ FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH
Definition: t4fw_interface.h:4976

FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT
@ FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT
Definition: t4fw_interface.h:4979

FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH
@ FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH
Definition: t4fw_interface.h:4982

FW_PARAMS_PARAM_DMAQ_EQ_DCA
@ FW_PARAMS_PARAM_DMAQ_EQ_DCA
Definition: t4fw_interface.h:4983

FW_PARAMS_PARAM_DMAQ_IQ_DCA
@ FW_PARAMS_PARAM_DMAQ_IQ_DCA
Definition: t4fw_interface.h:4978

FW_PARAMS_PARAM_DMAQ_IQ_INTIDX
@ FW_PARAMS_PARAM_DMAQ_IQ_INTIDX
Definition: t4fw_interface.h:4977

FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH
@ FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH
Definition: t4fw_interface.h:4981

fw_sched_params_rate
fw_sched_params_rate
Definition: t4fw_interface.h:8752

FW_SCHED_PARAMS_RATE_REL
@ FW_SCHED_PARAMS_RATE_REL
Definition: t4fw_interface.h:8753

FW_SCHED_PARAMS_RATE_ABS
@ FW_SCHED_PARAMS_RATE_ABS
Definition: t4fw_interface.h:8754

fw_vi_mac_smac
fw_vi_mac_smac
Definition: t4fw_interface.h:6666

FW_VI_MAC_SMT_ONLY
@ FW_VI_MAC_SMT_ONLY
Definition: t4fw_interface.h:6669

FW_VI_MAC_MPS_TCAM_ONLY
@ FW_VI_MAC_MPS_TCAM_ONLY
Definition: t4fw_interface.h:6668

FW_VI_MAC_MPS_TCAM_ENTRY
@ FW_VI_MAC_MPS_TCAM_ENTRY
Definition: t4fw_interface.h:6667

FW_VI_MAC_SMT_AND_MPSTCAM
@ FW_VI_MAC_SMT_AND_MPSTCAM
Definition: t4fw_interface.h:6670

fw_port_stat_rx_index
fw_port_stat_rx_index
Definition: t4fw_interface.h:7892

FW_STAT_RX_PORT_CRC_ERROR_IX
@ FW_STAT_RX_PORT_CRC_ERROR_IX
Definition: t4fw_interface.h:7900

FW_STAT_RX_PORT_PPP0_IX
@ FW_STAT_RX_PORT_PPP0_IX
Definition: t4fw_interface.h:7911

FW_STAT_RX_PORT_1024B_1518B_IX
@ FW_STAT_RX_PORT_1024B_1518B_IX
Definition: t4fw_interface.h:7908

FW_STAT_RX_PORT_PPP4_IX
@ FW_STAT_RX_PORT_PPP4_IX
Definition: t4fw_interface.h:7915

FW_STAT_RX_PORT_PPP3_IX
@ FW_STAT_RX_PORT_PPP3_IX
Definition: t4fw_interface.h:7914

FW_STAT_RX_PORT_MAC_ERROR_IX
@ FW_STAT_RX_PORT_MAC_ERROR_IX
Definition: t4fw_interface.h:7920

FW_STAT_RX_PORT_512B_1023B_IX
@ FW_STAT_RX_PORT_512B_1023B_IX
Definition: t4fw_interface.h:7907

FW_STAT_RX_PORT_256B_511B_IX
@ FW_STAT_RX_PORT_256B_511B_IX
Definition: t4fw_interface.h:7906

FW_STAT_RX_PORT_1519B_MAX_IX
@ FW_STAT_RX_PORT_1519B_MAX_IX
Definition: t4fw_interface.h:7909

FW_NUM_PORT_RX_STATS
@ FW_NUM_PORT_RX_STATS
Definition: t4fw_interface.h:7921

FW_STAT_RX_PORT_PPP1_IX
@ FW_STAT_RX_PORT_PPP1_IX
Definition: t4fw_interface.h:7912

FW_STAT_RX_PORT_BYTES_IX
@ FW_STAT_RX_PORT_BYTES_IX
Definition: t4fw_interface.h:7893

FW_STAT_RX_PORT_PAUSE_IX
@ FW_STAT_RX_PORT_PAUSE_IX
Definition: t4fw_interface.h:7910

FW_STAT_RX_PORT_MTU_CRC_ERROR_IX
@ FW_STAT_RX_PORT_MTU_CRC_ERROR_IX
Definition: t4fw_interface.h:7899

FW_STAT_RX_PORT_MCAST_IX
@ FW_STAT_RX_PORT_MCAST_IX
Definition: t4fw_interface.h:7896

FW_STAT_RX_PORT_65B_127B_IX
@ FW_STAT_RX_PORT_65B_127B_IX
Definition: t4fw_interface.h:7904

FW_STAT_RX_PORT_LESS_64B_IX
@ FW_STAT_RX_PORT_LESS_64B_IX
Definition: t4fw_interface.h:7919

FW_STAT_RX_PORT_PPP6_IX
@ FW_STAT_RX_PORT_PPP6_IX
Definition: t4fw_interface.h:7917

FW_STAT_RX_PORT_SYM_ERROR_IX
@ FW_STAT_RX_PORT_SYM_ERROR_IX
Definition: t4fw_interface.h:7902

FW_STAT_RX_PORT_LEN_ERROR_IX
@ FW_STAT_RX_PORT_LEN_ERROR_IX
Definition: t4fw_interface.h:7901

FW_STAT_RX_PORT_PPP5_IX
@ FW_STAT_RX_PORT_PPP5_IX
Definition: t4fw_interface.h:7916

FW_STAT_RX_PORT_128B_255B_IX
@ FW_STAT_RX_PORT_128B_255B_IX
Definition: t4fw_interface.h:7905

FW_STAT_RX_PORT_MTU_ERROR_IX
@ FW_STAT_RX_PORT_MTU_ERROR_IX
Definition: t4fw_interface.h:7898

FW_STAT_RX_PORT_PPP2_IX
@ FW_STAT_RX_PORT_PPP2_IX
Definition: t4fw_interface.h:7913

FW_STAT_RX_PORT_UCAST_IX
@ FW_STAT_RX_PORT_UCAST_IX
Definition: t4fw_interface.h:7897

FW_STAT_RX_PORT_FRAMES_IX
@ FW_STAT_RX_PORT_FRAMES_IX
Definition: t4fw_interface.h:7894

FW_STAT_RX_PORT_BCAST_IX
@ FW_STAT_RX_PORT_BCAST_IX
Definition: t4fw_interface.h:7895

FW_STAT_RX_PORT_PPP7_IX
@ FW_STAT_RX_PORT_PPP7_IX
Definition: t4fw_interface.h:7918

FW_STAT_RX_PORT_64B_IX
@ FW_STAT_RX_PORT_64B_IX
Definition: t4fw_interface.h:7903

fw_port_dcb_cfg
fw_port_dcb_cfg
Definition: t4fw_interface.h:7348

FW_PORT_DCB_CFG_PG
@ FW_PORT_DCB_CFG_PG
Definition: t4fw_interface.h:7349

FW_PORT_DCB_CFG_PFC
@ FW_PORT_DCB_CFG_PFC
Definition: t4fw_interface.h:7350

FW_PORT_DCB_CFG_APPL
@ FW_PORT_DCB_CFG_APPL
Definition: t4fw_interface.h:7351

fw_caps_config_iscsi
fw_caps_config_iscsi
Definition: t4fw_interface.h:4677

FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD
@ FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD
Definition: t4fw_interface.h:4685

FW_CAPS_CONFIG_ISCSI_T10DIF
@ FW_CAPS_CONFIG_ISCSI_T10DIF
Definition: t4fw_interface.h:4684

FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD
@ FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD
Definition: t4fw_interface.h:4680

FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD
@ FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD
Definition: t4fw_interface.h:4681

FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD
@ FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD
Definition: t4fw_interface.h:4682

FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD
@ FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD
Definition: t4fw_interface.h:4683

FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU
@ FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU
Definition: t4fw_interface.h:4678

FW_CAPS_CONFIG_ISCSI_TARGET_PDU
@ FW_CAPS_CONFIG_ISCSI_TARGET_PDU
Definition: t4fw_interface.h:4679

FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD
@ FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD
Definition: t4fw_interface.h:4686

fw_sched_type
fw_sched_type
Definition: t4fw_interface.h:8731

FW_SCHED_TYPE_STREAMSCHED
@ FW_SCHED_TYPE_STREAMSCHED
Definition: t4fw_interface.h:8733

FW_SCHED_TYPE_PKTSCHED
@ FW_SCHED_TYPE_PKTSCHED
Definition: t4fw_interface.h:8732

FW_PORT_CAP32_SPEED_25G
#define FW_PORT_CAP32_SPEED_25G
Definition: t4fw_interface.h:7200

fw_params_param_dev_filter
fw_params_param_dev_filter
Definition: t4fw_interface.h:4876

FW_PARAM_DEV_FILTER_VNIC_MODE
@ FW_PARAM_DEV_FILTER_VNIC_MODE
Definition: t4fw_interface.h:4877

FW_PARAM_DEV_FILTER_MODE_MASK
@ FW_PARAM_DEV_FILTER_MODE_MASK
Definition: t4fw_interface.h:4878

fw_ptp_subop
fw_ptp_subop
Definition: t4fw_interface.h:8232

FW_PTP_SC_SET_TIME
@ FW_PTP_SC_SET_TIME
Definition: t4fw_interface.h:8248

FW_PTP_SC_INIT_TIMER
@ FW_PTP_SC_INIT_TIMER
Definition: t4fw_interface.h:8235

FW_PTP_SC_TX_TYPE
@ FW_PTP_SC_TX_TYPE
Definition: t4fw_interface.h:8236

FW_PTP_SC_ADJ_FTIME
@ FW_PTP_SC_ADJ_FTIME
Definition: t4fw_interface.h:8245

FW_PTP_SC_WALL_CLOCK
@ FW_PTP_SC_WALL_CLOCK
Definition: t4fw_interface.h:8246

FW_PTP_SC_RXTIME_STAMP
@ FW_PTP_SC_RXTIME_STAMP
Definition: t4fw_interface.h:8239

FW_PTP_SC_RDRX_TYPE
@ FW_PTP_SC_RDRX_TYPE
Definition: t4fw_interface.h:8240

FW_PTP_SC_GET_TIME
@ FW_PTP_SC_GET_TIME
Definition: t4fw_interface.h:8247

FW_PTP_SC_ADJ_TIME
@ FW_PTP_SC_ADJ_TIME
Definition: t4fw_interface.h:8244

FW_PTP_SC_ADJ_FREQ
@ FW_PTP_SC_ADJ_FREQ
Definition: t4fw_interface.h:8243

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type
Definition: t4fw_interface.h:2241

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::ipv6
struct fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv6 ipv6

fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::ipv4
struct fw_chnet_ifconf_wr::fw_chnet_ifconf_params::fw_chnet_ifconf_addr_type::fw_chnet_ifconf_ipv4 ipv4

fw_coiscsi_stats_wr::fw_coiscsi_stats
Definition: t4fw_interface.h:3107

fw_coiscsi_stats_wr::fw_coiscsi_stats::rsrc
struct fw_coiscsi_stats_wr::fw_coiscsi_stats::fw_coiscsi_resource rsrc

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr
Definition: t4fw_interface.h:2909

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::in_addr6
struct fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr6 in_addr6

fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::in_addr
struct fw_coiscsi_tgt_wr::fw_coiscsi_tgt_conn_attr::fw_coiscsi_tgt_conn_attr_addr::fw_coiscsi_tgt_conn_attr_in_addr in_addr

fw_dcb_ieee_cmd::fw_dcbx_stats
Definition: t4fw_interface.h:9396

fw_dcb_ieee_cmd::fw_dcbx_stats::dcbx_pfc_stats
struct fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_pfc_stats_ieee dcbx_pfc_stats

fw_dcb_ieee_cmd::fw_dcbx_stats::dcbx_control
struct fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_control dcbx_control

fw_dcb_ieee_cmd::fw_dcbx_stats::dcbx_app_stats
struct fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_app_stats_ieee dcbx_app_stats

fw_dcb_ieee_cmd::fw_dcbx_stats::dcbx_ets_stats
struct fw_dcb_ieee_cmd::fw_dcbx_stats::fw_dcbx_ets_stats_ieee dcbx_ets_stats

fw_debug_cmd::fw_debug
Definition: t4fw_interface.h:9637

fw_debug_cmd::fw_debug::assert
struct fw_debug_cmd::fw_debug::fw_debug_assert assert

fw_debug_cmd::fw_debug::prt
struct fw_debug_cmd::fw_debug::fw_debug_prt prt

fw_diag_cmd::fw_diag_test
Definition: t4fw_interface.h:9702

fw_diag_cmd::fw_diag_test::memdiag
struct fw_diag_cmd::fw_diag_test::fw_diag_test_memtest_diag memdiag

fw_diag_cmd::fw_diag_test::ofldiag
struct fw_diag_cmd::fw_diag_test::fw_diag_test_ofldiag ofldiag

fw_error_cmd::fw_error
Definition: t4fw_interface.h:9565

fw_error_cmd::fw_error::exception
struct fw_error_cmd::fw_error::fw_error_exception exception

fw_error_cmd::fw_error::wr
struct fw_error_cmd::fw_error::fw_error_wr wr

fw_error_cmd::fw_error::hwmodule
struct fw_error_cmd::fw_error::fw_error_hwmodule hwmodule

fw_error_cmd::fw_error::acl
struct fw_error_cmd::fw_error::fw_error_acl acl

fw_eth_tx_eo_wr::fw_eth_tx_eo
Definition: t4fw_interface.h:804

fw_eth_tx_eo_wr::fw_eth_tx_eo::vxlanseg
struct fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_vxlanseg vxlanseg

fw_eth_tx_eo_wr::fw_eth_tx_eo::nvgreseg
struct fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_nvgreseg nvgreseg

fw_eth_tx_eo_wr::fw_eth_tx_eo::geneveseg
struct fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_geneveseg geneveseg

fw_eth_tx_eo_wr::fw_eth_tx_eo::udpseg
struct fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_udpseg udpseg

fw_eth_tx_eo_wr::fw_eth_tx_eo::tcpseg
struct fw_eth_tx_eo_wr::fw_eth_tx_eo::fw_eth_tx_eo_tcpseg tcpseg

fw_fcoe_stats_cmd::fw_fcoe_stats
Definition: t4fw_interface.h:9164

fw_fcoe_stats_cmd::fw_fcoe_stats::ctl
struct fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_stats_ctl ctl

fw_fcoe_stats_cmd::fw_fcoe_stats::port_stats
struct fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_port_stats port_stats

fw_fcoe_stats_cmd::fw_fcoe_stats::scb_stats
struct fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_scb_stats scb_stats

fw_fcoe_stats_cmd::fw_fcoe_stats::pcb_stats
struct fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_pcb_stats pcb_stats

fw_fcoe_stats_cmd::fw_fcoe_stats::fcf_stats
struct fw_fcoe_stats_cmd::fw_fcoe_stats::fw_fcoe_fcf_stats fcf_stats

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend
Definition: t4fw_interface.h:2861

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::chap
struct fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_chap chap

fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::vend_kv
struct fw_foiscsi_chap_wr::fw_foiscsi_chap_vend::fw_foiscsi_vend_kv vend_kv

fw_foiscsi_chap_wr::fw_foiscsi_len
Definition: t4fw_interface.h:2848

fw_foiscsi_chap_wr::fw_foiscsi_len::vend_kvl
struct fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_vend_kv_lens vend_kvl

fw_foiscsi_chap_wr::fw_foiscsi_len::chapl
struct fw_foiscsi_chap_wr::fw_foiscsi_len::fw_foiscsi_chap_lens chapl

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr
Definition: t4fw_interface.h:2698

fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::ipv6_addr
struct fw_foiscsi_ctrl_wr::fw_foiscsi_conn_attr::fw_foiscsi_conn_attr_addr::fw_foiscsi_conn_attr_ipv6 ipv6_addr

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