FreeBSD kernel CXGBE device code
t4_regs_values.h
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1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32#ifndef __T4_REGS_VALUES_H__
33#define __T4_REGS_VALUES_H__
34
35/*
36 * This file contains definitions for various T4 register value hardware
37 * constants. The types of values encoded here are predominantly those for
38 * register fields which control "modal" behavior. For the most part, we do
39 * not include definitions for register fields which are simple numeric
40 * metrics, etc.
41 *
42 * These new "modal values" use a naming convention which matches the
43 * currently existing macros in t4_reg.h. For register field FOO which would
44 * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE}
45 * definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) ==
46 * X_FOO_MODE).
47 *
48 * Note that this should all be part of t4_regs.h but the toolset used to
49 * generate that file doesn't [yet] have the capability of collecting these
50 * constants.
51 */
52
53/*
54 * SGE definitions.
55 * ================
56 */
57
58/*
59 * SGE register field values.
60 */
61
62/* CONTROL register */
63#define X_FLSPLITMODE_FLSPLITMIN 0
64#define X_FLSPLITMODE_ETHHDR 1
65#define X_FLSPLITMODE_IPHDR 2
66#define X_FLSPLITMODE_TCPHDR 3
67
68#define X_DCASYSTYPE_FSB 0
69#define X_DCASYSTYPE_CSI 1
70
71#define X_EGSTATPAGESIZE_64B 0
72#define X_EGSTATPAGESIZE_128B 1
73
74#define X_RXPKTCPLMODE_DATA 0
75#define X_RXPKTCPLMODE_SPLIT 1
76
77#define X_INGPCIEBOUNDARY_SHIFT 5
78#define X_INGPCIEBOUNDARY_32B 0
79#define X_INGPCIEBOUNDARY_64B 1
80#define X_INGPCIEBOUNDARY_128B 2
81#define X_INGPCIEBOUNDARY_256B 3
82#define X_INGPCIEBOUNDARY_512B 4
83#define X_INGPCIEBOUNDARY_1024B 5
84#define X_INGPCIEBOUNDARY_2048B 6
85#define X_INGPCIEBOUNDARY_4096B 7
86
87#define X_T6_INGPADBOUNDARY_SHIFT 3
88#define X_T6_INGPADBOUNDARY_8B 0
89#define X_T6_INGPADBOUNDARY_16B 1
90#define X_T6_INGPADBOUNDARY_32B 2
91#define X_T6_INGPADBOUNDARY_64B 3
92#define X_T6_INGPADBOUNDARY_128B 4
93#define X_T6_INGPADBOUNDARY_256B 5
94#define X_T6_INGPADBOUNDARY_512B 6
95#define X_T6_INGPADBOUNDARY_1024B 7
96
97#define X_INGPADBOUNDARY_SHIFT 5
98#define X_INGPADBOUNDARY_32B 0
99#define X_INGPADBOUNDARY_64B 1
100#define X_INGPADBOUNDARY_128B 2
101#define X_INGPADBOUNDARY_256B 3
102#define X_INGPADBOUNDARY_512B 4
103#define X_INGPADBOUNDARY_1024B 5
104#define X_INGPADBOUNDARY_2048B 6
105#define X_INGPADBOUNDARY_4096B 7
106
107#define X_EGRPCIEBOUNDARY_SHIFT 5
108#define X_EGRPCIEBOUNDARY_32B 0
109#define X_EGRPCIEBOUNDARY_64B 1
110#define X_EGRPCIEBOUNDARY_128B 2
111#define X_EGRPCIEBOUNDARY_256B 3
112#define X_EGRPCIEBOUNDARY_512B 4
113#define X_EGRPCIEBOUNDARY_1024B 5
114#define X_EGRPCIEBOUNDARY_2048B 6
115#define X_EGRPCIEBOUNDARY_4096B 7
116
117/* CONTROL2 register */
118#define X_INGPACKBOUNDARY_SHIFT 5 // *most* of the values ...
119#define X_INGPACKBOUNDARY_16B 0 // Note weird value!
120#define X_INGPACKBOUNDARY_64B 1
121#define X_INGPACKBOUNDARY_128B 2
122#define X_INGPACKBOUNDARY_256B 3
123#define X_INGPACKBOUNDARY_512B 4
124#define X_INGPACKBOUNDARY_1024B 5
125#define X_INGPACKBOUNDARY_2048B 6
126#define X_INGPACKBOUNDARY_4096B 7
127
128/* GTS register */
129#define SGE_TIMERREGS 6
130#define X_TIMERREG_COUNTER0 0
131#define X_TIMERREG_COUNTER1 1
132#define X_TIMERREG_COUNTER2 2
133#define X_TIMERREG_COUNTER3 3
134#define X_TIMERREG_COUNTER4 4
135#define X_TIMERREG_COUNTER5 5
136#define X_TIMERREG_RESTART_COUNTER 6
137#define X_TIMERREG_UPDATE_CIDX 7
138
139/*
140 * Egress Context field values
141 */
142#define EC_WR_UNITS 16
143
144#define X_FETCHBURSTMIN_SHIFT 4
145#define X_FETCHBURSTMIN_16B 0
146#define X_FETCHBURSTMIN_32B 1
147#define X_FETCHBURSTMIN_64B 2
148#define X_FETCHBURSTMIN_128B 3
149
150/* T6 and later use a single-bit encoding for FetchBurstMin */
151#define X_FETCHBURSTMIN_SHIFT_T6 6
152#define X_FETCHBURSTMIN_64B_T6 0
153#define X_FETCHBURSTMIN_128B_T6 1
154
155#define X_FETCHBURSTMAX_SHIFT 6
156#define X_FETCHBURSTMAX_64B 0
157#define X_FETCHBURSTMAX_128B 1
158#define X_FETCHBURSTMAX_256B 2
159#define X_FETCHBURSTMAX_512B 3
160
161#define X_HOSTFCMODE_NONE 0
162#define X_HOSTFCMODE_INGRESS_QUEUE 1
163#define X_HOSTFCMODE_STATUS_PAGE 2
164#define X_HOSTFCMODE_BOTH 3
165
166#define X_HOSTFCOWNER_UP 0
167#define X_HOSTFCOWNER_SGE 1
168
169#define X_CIDXFLUSHTHRESH_1 0
170#define X_CIDXFLUSHTHRESH_2 1
171#define X_CIDXFLUSHTHRESH_4 2
172#define X_CIDXFLUSHTHRESH_8 3
173#define X_CIDXFLUSHTHRESH_16 4
174#define X_CIDXFLUSHTHRESH_32 5
175#define X_CIDXFLUSHTHRESH_64 6
176#define X_CIDXFLUSHTHRESH_128 7
177
178#define X_IDXSIZE_UNIT 64
179
180#define X_BASEADDRESS_ALIGN 512
181
182/*
183 * Ingress Context field values
184 */
185#define X_UPDATESCHEDULING_TIMER 0
186#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1
187
188#define X_UPDATEDELIVERY_NONE 0
189#define X_UPDATEDELIVERY_INTERRUPT 1
190#define X_UPDATEDELIVERY_STATUS_PAGE 2
191#define X_UPDATEDELIVERY_BOTH 3
192
193#define X_INTERRUPTDESTINATION_PCIE 0
194#define X_INTERRUPTDESTINATION_IQ 1
195
196#define X_QUEUEENTRYSIZE_16B 0
197#define X_QUEUEENTRYSIZE_32B 1
198#define X_QUEUEENTRYSIZE_64B 2
199#define X_QUEUEENTRYSIZE_128B 3
200
201#define IC_SIZE_UNIT 16
202#define IC_BASEADDRESS_ALIGN 512
203
204#define X_RSPD_TYPE_FLBUF 0
205#define X_RSPD_TYPE_CPL 1
206#define X_RSPD_TYPE_INTR 2
207
208/*
209 * Context field definitions. This is by no means a complete list of SGE
210 * Context fields. In the vast majority of cases the firmware initializes
211 * things the way they need to be set up. But in a few small cases, we need
212 * to compute new values and ship them off to the firmware to be applied to
213 * the SGE Conexts ...
214 */
215
216/*
217 * Congestion Manager Definitions.
218 */
219#define S_CONMCTXT_CNGTPMODE 19
220#define M_CONMCTXT_CNGTPMODE 0x3
221#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE)
222#define G_CONMCTXT_CNGTPMODE(x) \
223 (((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)
224#define S_CONMCTXT_CNGCHMAP 0
225#define M_CONMCTXT_CNGCHMAP 0xffff
226#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP)
227#define G_CONMCTXT_CNGCHMAP(x) \
228 (((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)
229
230#define X_CONMCTXT_CNGTPMODE_DISABLE 0
231#define X_CONMCTXT_CNGTPMODE_QUEUE 1
232#define X_CONMCTXT_CNGTPMODE_CHANNEL 2
233#define X_CONMCTXT_CNGTPMODE_BOTH 3
234
235/*
236 * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
237 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
238 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
239 * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
240 * we have a Going To Sleep register at offsets 8x+4.
241 *
242 * As noted above, we have many instances of the Simple Doorbell and Going To
243 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
244 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
245 * avoid buffering of the writes to the Simple Doorbell and we want to use a
246 * non-contiguous offset for the Going To Sleep writes in order to avoid
247 * possible combining between them.
248 */
249#define SGE_UDB_SIZE 128
250#define SGE_UDB_KDOORBELL 8
251#define SGE_UDB_GTS 20
252#define SGE_UDB_WCDOORBELL 64
253
254/*
255 * CIM definitions.
256 * ================
257 */
258
259/*
260 * CIM register field values.
261 */
262#define X_MBOWNER_NONE 0
263#define X_MBOWNER_FW 1
264#define X_MBOWNER_PL 2
265#define X_MBOWNER_FW_DEFERRED 3
266
267/*
268 * PCI-E definitions.
269 * ==================
270 */
271
272#define X_WINDOW_SHIFT 10
273#define X_PCIEOFST_SHIFT 10
274
275/*
276 * TP definitions.
277 * ===============
278 */
279
280/*
281 * TP_VLAN_PRI_MAP controls which subset of fields will be present in the
282 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
283 * selects for a particular field being present. These fields, when present
284 * in the Compressed Filter Tuple, have the following widths in bits.
285 */
286#define S_FT_FIRST S_FCOE
287#define S_FT_LAST S_FRAGMENTATION
288
289#define W_FT_FCOE 1
290#define W_FT_PORT 3
291#define W_FT_VNIC_ID 17
292#define W_FT_VLAN 17
293#define W_FT_TOS 8
294#define W_FT_PROTOCOL 8
295#define W_FT_ETHERTYPE 16
296#define W_FT_MACMATCH 9
297#define W_FT_MPSHITTYPE 3
298#define W_FT_FRAGMENTATION 1
299
300#define M_FT_FCOE ((1ULL << W_FT_FCOE) - 1)
301#define M_FT_PORT ((1ULL << W_FT_PORT) - 1)
302#define M_FT_VNIC_ID ((1ULL << W_FT_VNIC_ID) - 1)
303#define M_FT_VLAN ((1ULL << W_FT_VLAN) - 1)
304#define M_FT_TOS ((1ULL << W_FT_TOS) - 1)
305#define M_FT_PROTOCOL ((1ULL << W_FT_PROTOCOL) - 1)
306#define M_FT_ETHERTYPE ((1ULL << W_FT_ETHERTYPE) - 1)
307#define M_FT_MACMATCH ((1ULL << W_FT_MACMATCH) - 1)
308#define M_FT_MPSHITTYPE ((1ULL << W_FT_MPSHITTYPE) - 1)
309#define M_FT_FRAGMENTATION ((1ULL << W_FT_FRAGMENTATION) - 1)
310
311/*
312 * Some of the Compressed Filter Tuple fields have internal structure. These
313 * bit shifts/masks describe those structures. All shifts are relative to the
314 * base position of the fields within the Compressed Filter Tuple
315 */
316#define S_FT_VLAN_VLD 16
317#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
318#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
319
320#define S_FT_VNID_ID_VF 0
321#define M_FT_VNID_ID_VF 0x7fU
322#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
323#define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF)
324
325#define S_FT_VNID_ID_PF 7
326#define M_FT_VNID_ID_PF 0x7U
327#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
328#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF)
329
330#define S_FT_VNID_ID_VLD 16
331#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
332#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U)
333
334#endif /* __T4_REGS_VALUES_H__ */