37#ifndef _DEV_ATH_ATHVAR_H
38#define _DEV_ATH_ATHVAR_H
40#include <machine/atomic.h>
44#include <net80211/ieee80211_radiotap.h>
51#define ATH_TIMEOUT 1000
59#define ATH_MGMT_TXBUF 32
78#define ATH_TXMAXTRY 11
80#define ATH_TXINTR_PERIOD 5
82#define ATH_BEACON_AIFS_DEFAULT 1
83#define ATH_BEACON_CWMIN_DEFAULT 0
84#define ATH_BEACON_CWMAX_DEFAULT 0
93#define ATH_PCI_CUS198 0x0001
94#define ATH_PCI_CUS230 0x0002
95#define ATH_PCI_CUS217 0x0004
96#define ATH_PCI_CUS252 0x0008
97#define ATH_PCI_WOW 0x0010
98#define ATH_PCI_BT_ANT_DIV 0x0020
99#define ATH_PCI_D3_L1_WAR 0x0040
100#define ATH_PCI_AR9565_1ANT 0x0080
101#define ATH_PCI_AR9565_2ANT 0x0100
102#define ATH_PCI_NO_PLL_PWRSAVE 0x0200
103#define ATH_PCI_KILLER 0x0400
113#define ATH_KEYMAX 128
114#define ATH_KEYBYTES (ATH_KEYMAX/NBBY)
120#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX)
210#define ATH_NODE(ni) ((struct ath_node *)(ni))
211#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
213#define ATH_RSSI_LPF_LEN 10
214#define ATH_RSSI_DUMMY_MARKER 0x127
215#define ATH_EP_MUL(x, mul) ((x) * (mul))
216#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
217#define ATH_LPF_RSSI(x, y, len) \
218 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
219#define ATH_RSSI_LPF(x, y) do { \
221 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
223#define ATH_EP_RND(x,mul) \
224 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
225#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
248#define ATH_MAX_SCATTER ATH_TXDESC
317#define ATH_BUF_MGMT 0x00000001
318#define ATH_BUF_BUSY 0x00000002
319#define ATH_BUF_FIFOEND 0x00000004
320#define ATH_BUF_FIFOPTR 0x00000008
321#define ATH_BUF_TOA_PROBE 0x00000010
323#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT | ATH_BUF_TOA_PROBE)
352#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1)
356#define ATH_TXQ_PUTRUNNING 0x0002
402#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
403 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
404 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
405 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
407#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
408#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
409#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
410#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
411#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \
414#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx)
415#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx)
416#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED)
417#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \
423#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \
424 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
425 (_tq)->axq_depth++; \
427#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
428 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
429 (_tq)->axq_depth++; \
431#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \
432 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
433 (_tq)->axq_depth--; \
435#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q)
436#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field)
441#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \
442 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \
443 (_tq)->axq_depth++; \
444 (_tq)->an->an_swq_depth++; \
446#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \
447 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \
448 (_tq)->axq_depth++; \
449 (_tq)->an->an_swq_depth++; \
451#define ATH_TID_REMOVE(_tq, _elm, _field) do { \
452 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \
453 (_tq)->axq_depth--; \
454 (_tq)->an->an_swq_depth--; \
456#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q)
457#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field)
462#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \
463 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \
464 (_tq)->axq_depth++; \
465 (_tq)->an->an_swq_depth++; \
467#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \
468 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \
469 (_tq)->axq_depth++; \
470 (_tq)->an->an_swq_depth++; \
472#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \
473 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \
474 (_tq)->axq_depth--; \
475 (_tq)->an->an_swq_depth--; \
477#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q)
478#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field)
488 const struct ieee80211_rx_stats *, int, int);
490 enum ieee80211_state, int);
498#define ATH_VAP(vap) ((struct ath_vap *)(vap))
889 struct ieee80211_tx_ampdu *, int, int, int);
891 struct ieee80211_tx_ampdu *, int, int, int);
893 struct ieee80211_tx_ampdu *);
895 (
struct ieee80211_node *,
896 struct ieee80211_tx_ampdu *);
898 struct ieee80211_tx_ampdu *tap,
934#define ATH_LOCK_INIT(_sc) \
935 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
936 NULL, MTX_DEF | MTX_RECURSE)
937#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
938#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
939#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
940#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
941#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
947#define ATH_TX_LOCK_INIT(_sc) do {\
948 snprintf((_sc)->sc_tx_mtx_name, \
949 sizeof((_sc)->sc_tx_mtx_name), \
951 device_get_nameunit((_sc)->sc_dev)); \
952 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \
955#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx)
956#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx)
957#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx)
958#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
960#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
962#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \
963 mtx_trylock(&(_sc)->sc_tx_mtx))
982#define ATH_PCU_LOCK_INIT(_sc) do {\
983 snprintf((_sc)->sc_pcu_mtx_name, \
984 sizeof((_sc)->sc_pcu_mtx_name), \
986 device_get_nameunit((_sc)->sc_dev)); \
987 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \
990#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx)
991#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx)
992#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx)
993#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
995#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
1004#define ATH_RX_LOCK_INIT(_sc) do {\
1005 snprintf((_sc)->sc_rx_mtx_name, \
1006 sizeof((_sc)->sc_rx_mtx_name), \
1008 device_get_nameunit((_sc)->sc_dev)); \
1009 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \
1012#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx)
1013#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx)
1014#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx)
1015#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
1017#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
1020#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
1022#define ATH_TXBUF_LOCK_INIT(_sc) do { \
1023 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
1024 device_get_nameunit((_sc)->sc_dev)); \
1025 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
1027#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
1028#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
1029#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
1030#define ATH_TXBUF_LOCK_ASSERT(_sc) \
1031 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
1032#define ATH_TXBUF_UNLOCK_ASSERT(_sc) \
1033 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED)
1035#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \
1036 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \
1038 device_get_nameunit((_sc)->sc_dev)); \
1039 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \
1042#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock)
1043#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock)
1044#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock)
1045#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \
1046 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED)
1058#define ath_hal_detach(_ah) \
1059 ((*(_ah)->ah_detach)((_ah)))
1060#define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \
1061 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \
1062 (_resettype), (_pstatus)))
1063#define ath_hal_macversion(_ah) \
1064 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
1065#define ath_hal_getratetable(_ah, _mode) \
1066 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
1067#define ath_hal_getmac(_ah, _mac) \
1068 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
1069#define ath_hal_setmac(_ah, _mac) \
1070 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
1071#define ath_hal_getbssidmask(_ah, _mask) \
1072 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
1073#define ath_hal_setbssidmask(_ah, _mask) \
1074 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
1075#define ath_hal_intrset(_ah, _mask) \
1076 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
1077#define ath_hal_intrget(_ah) \
1078 ((*(_ah)->ah_getInterrupts)((_ah)))
1079#define ath_hal_intrpend(_ah) \
1080 ((*(_ah)->ah_isInterruptPending)((_ah)))
1081#define ath_hal_getisr(_ah, _pmask) \
1082 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
1083#define ath_hal_updatetxtriglevel(_ah, _inc) \
1084 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
1085#define ath_hal_setpower(_ah, _mode) \
1086 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
1087#define ath_hal_setselfgenpower(_ah, _mode) \
1088 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE))
1089#define ath_hal_keycachesize(_ah) \
1090 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
1091#define ath_hal_keyreset(_ah, _ix) \
1092 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
1093#define ath_hal_keyset(_ah, _ix, _pk, _mac) \
1094 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
1095#define ath_hal_keyisvalid(_ah, _ix) \
1096 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
1097#define ath_hal_keysetmac(_ah, _ix, _mac) \
1098 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
1099#define ath_hal_getrxfilter(_ah) \
1100 ((*(_ah)->ah_getRxFilter)((_ah)))
1101#define ath_hal_setrxfilter(_ah, _filter) \
1102 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
1103#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
1104 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
1105#define ath_hal_waitforbeacon(_ah, _bf) \
1106 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
1107#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \
1108 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq)))
1110#define AR_TSF_L32 0x804c
1111#define ath_hal_gettsf32(_ah) \
1112 OS_REG_READ(_ah, AR_TSF_L32)
1113#define ath_hal_gettsf64(_ah) \
1114 ((*(_ah)->ah_getTsf64)((_ah)))
1115#define ath_hal_settsf64(_ah, _val) \
1116 ((*(_ah)->ah_setTsf64)((_ah), (_val)))
1117#define ath_hal_resettsf(_ah) \
1118 ((*(_ah)->ah_resetTsf)((_ah)))
1119#define ath_hal_rxena(_ah) \
1120 ((*(_ah)->ah_enableReceive)((_ah)))
1121#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
1122 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
1123#define ath_hal_gettxbuf(_ah, _q) \
1124 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
1125#define ath_hal_numtxpending(_ah, _q) \
1126 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
1127#define ath_hal_getrxbuf(_ah, _rxq) \
1128 ((*(_ah)->ah_getRxDP)((_ah), (_rxq)))
1129#define ath_hal_txstart(_ah, _q) \
1130 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
1131#define ath_hal_setchannel(_ah, _chan) \
1132 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
1133#define ath_hal_calibrate(_ah, _chan, _iqcal) \
1134 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
1135#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
1136 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
1137#define ath_hal_calreset(_ah, _chan) \
1138 ((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
1139#define ath_hal_setledstate(_ah, _state) \
1140 ((*(_ah)->ah_setLedState)((_ah), (_state)))
1141#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
1142 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
1143#define ath_hal_beaconreset(_ah) \
1144 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
1145#define ath_hal_beaconsettimers(_ah, _bt) \
1146 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
1147#define ath_hal_beacontimers(_ah, _bs) \
1148 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
1149#define ath_hal_getnexttbtt(_ah) \
1150 ((*(_ah)->ah_getNextTBTT)((_ah)))
1151#define ath_hal_setassocid(_ah, _bss, _associd) \
1152 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
1153#define ath_hal_phydisable(_ah) \
1154 ((*(_ah)->ah_phyDisable)((_ah)))
1155#define ath_hal_setopmode(_ah) \
1156 ((*(_ah)->ah_setPCUConfig)((_ah)))
1157#define ath_hal_stoptxdma(_ah, _qnum) \
1158 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
1159#define ath_hal_stoppcurecv(_ah) \
1160 ((*(_ah)->ah_stopPcuReceive)((_ah)))
1161#define ath_hal_startpcurecv(_ah, _is_scanning) \
1162 ((*(_ah)->ah_startPcuReceive)((_ah), (_is_scanning)))
1163#define ath_hal_stopdmarecv(_ah) \
1164 ((*(_ah)->ah_stopDmaReceive)((_ah)))
1165#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
1166 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
1167 (_indata), (_insize), (_outdata), (_outsize)))
1168#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
1169 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
1170#define ath_hal_setuptxqueue(_ah, _type, _irq) \
1171 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
1172#define ath_hal_resettxqueue(_ah, _q) \
1173 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
1174#define ath_hal_releasetxqueue(_ah, _q) \
1175 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
1176#define ath_hal_gettxqueueprops(_ah, _q, _qi) \
1177 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
1178#define ath_hal_settxqueueprops(_ah, _q, _qi) \
1179 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
1181#define AR_Q_TXE 0x0840
1182#define ath_hal_txqenabled(_ah, _qnum) \
1183 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
1184#define ath_hal_getrfgain(_ah) \
1185 ((*(_ah)->ah_getRfGain)((_ah)))
1186#define ath_hal_getdefantenna(_ah) \
1187 ((*(_ah)->ah_getDefAntenna)((_ah)))
1188#define ath_hal_setdefantenna(_ah, _ant) \
1189 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
1190#define ath_hal_rxmonitor(_ah, _arg, _chan) \
1191 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
1192#define ath_hal_ani_poll(_ah, _chan) \
1193 ((*(_ah)->ah_aniPoll)((_ah), (_chan)))
1194#define ath_hal_mibevent(_ah, _stats) \
1195 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
1196#define ath_hal_setslottime(_ah, _us) \
1197 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
1198#define ath_hal_getslottime(_ah) \
1199 ((*(_ah)->ah_getSlotTime)((_ah)))
1200#define ath_hal_setacktimeout(_ah, _us) \
1201 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
1202#define ath_hal_getacktimeout(_ah) \
1203 ((*(_ah)->ah_getAckTimeout)((_ah)))
1204#define ath_hal_setctstimeout(_ah, _us) \
1205 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
1206#define ath_hal_getctstimeout(_ah) \
1207 ((*(_ah)->ah_getCTSTimeout)((_ah)))
1208#define ath_hal_getcapability(_ah, _cap, _param, _result) \
1209 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
1210#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
1211 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
1212#define ath_hal_ciphersupported(_ah, _cipher) \
1213 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
1214#define ath_hal_getregdomain(_ah, _prd) \
1215 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
1216#define ath_hal_setregdomain(_ah, _rd) \
1217 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
1218#define ath_hal_getcountrycode(_ah, _pcc) \
1219 (*(_pcc) = (_ah)->ah_countryCode)
1220#define ath_hal_gettkipmic(_ah) \
1221 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
1222#define ath_hal_settkipmic(_ah, _v) \
1223 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
1224#define ath_hal_hastkipsplit(_ah) \
1225 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
1226#define ath_hal_gettkipsplit(_ah) \
1227 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
1228#define ath_hal_settkipsplit(_ah, _v) \
1229 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
1230#define ath_hal_haswmetkipmic(_ah) \
1231 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
1232#define ath_hal_hwphycounters(_ah) \
1233 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
1234#define ath_hal_hasdiversity(_ah) \
1235 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
1236#define ath_hal_getdiversity(_ah) \
1237 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
1238#define ath_hal_setdiversity(_ah, _v) \
1239 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
1240#define ath_hal_getantennaswitch(_ah) \
1241 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
1242#define ath_hal_setantennaswitch(_ah, _v) \
1243 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
1244#define ath_hal_getdiag(_ah, _pv) \
1245 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
1246#define ath_hal_setdiag(_ah, _v) \
1247 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
1248#define ath_hal_getnumtxqueues(_ah, _pv) \
1249 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
1250#define ath_hal_hasveol(_ah) \
1251 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
1252#define ath_hal_hastxpowlimit(_ah) \
1253 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
1254#define ath_hal_settxpowlimit(_ah, _pow) \
1255 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
1256#define ath_hal_gettxpowlimit(_ah, _ppow) \
1257 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
1258#define ath_hal_getmaxtxpow(_ah, _ppow) \
1259 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
1260#define ath_hal_gettpscale(_ah, _scale) \
1261 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
1262#define ath_hal_settpscale(_ah, _v) \
1263 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
1264#define ath_hal_hastpc(_ah) \
1265 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
1266#define ath_hal_gettpc(_ah) \
1267 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
1268#define ath_hal_settpc(_ah, _v) \
1269 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
1270#define ath_hal_hasbursting(_ah) \
1271 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
1272#define ath_hal_setmcastkeysearch(_ah, _v) \
1273 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
1274#define ath_hal_hasmcastkeysearch(_ah) \
1275 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
1276#define ath_hal_getmcastkeysearch(_ah) \
1277 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
1278#define ath_hal_hasfastframes(_ah) \
1279 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
1280#define ath_hal_hasbssidmask(_ah) \
1281 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
1282#define ath_hal_hasbssidmatch(_ah) \
1283 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
1284#define ath_hal_hastsfadjust(_ah) \
1285 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
1286#define ath_hal_gettsfadjust(_ah) \
1287 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
1288#define ath_hal_settsfadjust(_ah, _onoff) \
1289 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
1290#define ath_hal_hasrfsilent(_ah) \
1291 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
1292#define ath_hal_getrfkill(_ah) \
1293 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
1294#define ath_hal_setrfkill(_ah, _onoff) \
1295 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
1296#define ath_hal_getrfsilent(_ah, _prfsilent) \
1297 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
1298#define ath_hal_setrfsilent(_ah, _rfsilent) \
1299 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
1300#define ath_hal_gettpack(_ah, _ptpack) \
1301 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
1302#define ath_hal_settpack(_ah, _tpack) \
1303 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
1304#define ath_hal_gettpcts(_ah, _ptpcts) \
1305 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
1306#define ath_hal_settpcts(_ah, _tpcts) \
1307 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
1308#define ath_hal_hasintmit(_ah) \
1309 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1310 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
1311#define ath_hal_getintmit(_ah) \
1312 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1313 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
1314#define ath_hal_setintmit(_ah, _v) \
1315 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
1316 HAL_CAP_INTMIT_ENABLE, _v, NULL)
1317#define ath_hal_hasmybeacon(_ah) \
1318 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK)
1320#define ath_hal_hasenforcetxop(_ah) \
1321 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK)
1322#define ath_hal_getenforcetxop(_ah) \
1323 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK)
1324#define ath_hal_setenforcetxop(_ah, _v) \
1325 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL)
1327#define ath_hal_hasrxlnamixer(_ah) \
1328 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK)
1330#define ath_hal_hasdivantcomb(_ah) \
1331 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK)
1332#define ath_hal_hasldpc(_ah) \
1333 (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK)
1334#define ath_hal_hasldpcwar(_ah) \
1335 (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK)
1338#define ath_hal_hasedma(_ah) \
1339 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \
1341#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \
1342 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \
1344#define ath_hal_getntxmaps(_ah, _req) \
1345 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \
1347#define ath_hal_gettxdesclen(_ah, _req) \
1348 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \
1350#define ath_hal_gettxstatuslen(_ah, _req) \
1351 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \
1353#define ath_hal_getrxstatuslen(_ah, _req) \
1354 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \
1356#define ath_hal_setrxbufsize(_ah, _req) \
1357 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \
1360#define ath_hal_getchannoise(_ah, _c) \
1361 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
1364#define ath_hal_getrxchainmask(_ah, _prxchainmask) \
1365 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
1366#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \
1367 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
1368#define ath_hal_setrxchainmask(_ah, _rx) \
1369 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL))
1370#define ath_hal_settxchainmask(_ah, _tx) \
1371 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL))
1372#define ath_hal_split4ktrans(_ah) \
1373 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \
1375#define ath_hal_self_linked_final_rxdesc(_ah) \
1376 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \
1378#define ath_hal_gtxto_supported(_ah) \
1379 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
1380#define ath_hal_get_rx_tsf_prec(_ah, _pr) \
1381 (ath_hal_getcapability((_ah), HAL_CAP_RXTSTAMP_PREC, 0, (_pr)) \
1383#define ath_hal_get_tx_tsf_prec(_ah, _pr) \
1384 (ath_hal_getcapability((_ah), HAL_CAP_TXTSTAMP_PREC, 0, (_pr)) \
1386#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
1387 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
1388#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
1389 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
1390#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
1391 _txr0, _txtr0, _keyix, _ant, _flags, \
1392 _rtsrate, _rtsdura) \
1393 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
1394 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
1395 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
1396#define ath_hal_setupxtxdesc(_ah, _ds, \
1397 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
1398 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
1399 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
1400#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \
1401 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \
1402 (_first), (_last), (_ds0)))
1403#define ath_hal_txprocdesc(_ah, _ds, _ts) \
1404 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
1405#define ath_hal_gettxintrtxqs(_ah, _txqs) \
1406 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
1407#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
1408 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
1409#define ath_hal_settxdesclink(_ah, _ds, _link) \
1410 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link)))
1411#define ath_hal_gettxdesclink(_ah, _ds, _link) \
1412 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link)))
1413#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \
1414 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr)))
1415#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \
1416 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \
1418#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \
1419 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus)))
1421#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
1422 _txr0, _txtr0, _antm, _rcr, _rcd) \
1423 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
1424 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
1425#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \
1426 _keyix, _cipher, _delims, _first, _last, _lastaggr) \
1427 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \
1428 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \
1429 (_first), (_last), (_lastaggr)))
1430#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
1431 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
1433#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
1434 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
1435 (_series), (_ns), (_flags)))
1437#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \
1438 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
1439#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \
1440 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
1441#define ath_hal_set11n_aggr_last(_ah, _ds) \
1442 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
1444#define ath_hal_set11nburstduration(_ah, _ds, _dur) \
1445 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
1446#define ath_hal_clr11n_aggr(_ah, _ds) \
1447 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
1448#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \
1449 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v)))
1451#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
1452 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
1453#define ath_hal_gpioset(_ah, _gpio, _b) \
1454 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
1455#define ath_hal_gpioget(_ah, _gpio) \
1456 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
1457#define ath_hal_gpiosetintr(_ah, _gpio, _b) \
1458 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
1463#define ath_hal_enablepcie(_ah, _restore, _poweroff) \
1464 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff)))
1465#define ath_hal_disablepcie(_ah) \
1466 ((*(_ah)->ah_disablePCIE)((_ah)))
1474#define ath_hal_enabledfs(_ah, _param) \
1475 ((*(_ah)->ah_enableDfs)((_ah), (_param)))
1476#define ath_hal_getdfsthresh(_ah, _param) \
1477 ((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1478#define ath_hal_getdfsdefaultthresh(_ah, _param) \
1479 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param)))
1480#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
1481 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1483#define ath_hal_is_fast_clock_enabled(_ah) \
1484 ((*(_ah)->ah_isFastClockEnabled)((_ah)))
1485#define ath_hal_radar_wait(_ah, _chan) \
1486 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
1487#define ath_hal_get_mib_cycle_counts(_ah, _sample) \
1488 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1489#define ath_hal_get_chan_ext_busy(_ah) \
1490 ((*(_ah)->ah_get11nExtBusy)((_ah)))
1491#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \
1492 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
1493#define ath_hal_set_quiet(_ah, _p, _d, _o, _f) \
1494 ((*(_ah)->ah_setQuiet)((_ah), (_p), (_d), (_o), (_f)))
1495#define ath_hal_getnav(_ah) \
1496 ((*(_ah)->ah_getNav)((_ah)))
1497#define ath_hal_setnav(_ah, _val) \
1498 ((*(_ah)->ah_setNav)((_ah), (_val)))
1500#define ath_hal_spectral_supported(_ah) \
1501 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK)
1502#define ath_hal_spectral_get_config(_ah, _p) \
1503 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p)))
1504#define ath_hal_spectral_configure(_ah, _p) \
1505 ((*(_ah)->ah_spectralConfigure)((_ah), (_p)))
1506#define ath_hal_spectral_start(_ah) \
1507 ((*(_ah)->ah_spectralStart)((_ah)))
1508#define ath_hal_spectral_stop(_ah) \
1509 ((*(_ah)->ah_spectralStop)((_ah)))
1511#define ath_hal_btcoex_supported(_ah) \
1512 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK)
1513#define ath_hal_btcoex_set_info(_ah, _info) \
1514 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info)))
1515#define ath_hal_btcoex_set_config(_ah, _cfg) \
1516 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg)))
1517#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \
1518 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid)))
1519#define ath_hal_btcoex_set_weights(_ah, _weight) \
1520 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1521#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \
1522 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr)))
1523#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \
1524 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val)))
1525#define ath_hal_btcoex_enable(_ah) \
1526 ((*(_ah)->ah_btCoexEnable)((_ah)))
1527#define ath_hal_btcoex_disable(_ah) \
1528 ((*(_ah)->ah_btCoexDisable)((_ah)))
1530#define ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \
1531 ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp)))
1532#define ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \
1533 ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt)))
1534#define ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \
1535 ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm)))
1536#define ath_hal_btcoex_mci_state(_ah, _st, _pd) \
1537 ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd)))
1538#define ath_hal_btcoex_mci_detach(_ah) \
1539 ((*(_ah)->ah_btMciDetach)((_ah)))
1541#define ath_hal_div_comb_conf_get(_ah, _conf) \
1542 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf)))
1543#define ath_hal_div_comb_conf_set(_ah, _conf) \
1544 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf)))
#define HAL_NUM_TX_QUEUES
#define HAL_NUM_RX_QUEUES
#define IEEE80211_ADDR_LEN
bus_space_tag_t HAL_BUS_TAG
bus_space_handle_t HAL_BUS_HANDLE
#define ATH_IOCTL_STATS_NUM_TX_ANTENNA
typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead
void ath_shutdown(struct ath_softc *)
void ath_suspend(struct ath_softc *)
void ath_resume(struct ath_softc *)
int ath_detach(struct ath_softc *)
int ath_attach(u_int16_t, struct ath_softc *)
struct ath_desc_status bf_status
void(* bf_comp)(struct ath_softc *sc, struct ath_buf *bf, int fail)
enum ieee80211_protmode bfs_protmode
TAILQ_ENTRY(ath_buf) bf_list
struct ath_desc * bf_lastds
struct ath_desc * bf_desc
struct ath_rc_series bfs_rc[ATH_RC_NUM]
struct ath_buf::@32 bf_state
bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]
struct ieee80211_node * bf_node
u_int32_t bfs_doratelookup
struct ath_desc * dd_desc
struct ath_buf * dd_bufptr
bus_dma_segment_t dd_dseg
struct ath_tid an_tid[IEEE80211_TID_SIZE]
struct ath_buf * an_ff_buf[WME_NUM_AC]
struct ieee80211_node an_node
HAL_NODE_STATS an_node_stats
struct ath_buf * m_holdbf
struct mbuf * m_rxpending
void(* recv_sched_queue)(struct ath_softc *sc, HAL_RX_QUEUE q, int dosched)
int(* recv_teardown)(struct ath_softc *sc)
int(* recv_start)(struct ath_softc *sc)
int(* recv_rxbuf_init)(struct ath_softc *sc, struct ath_buf *bf)
void(* recv_tasklet)(void *arg, int npending)
void(* recv_sched)(struct ath_softc *sc, int dosched)
void(* recv_flush)(struct ath_softc *sc)
void(* recv_stop)(struct ath_softc *sc, int dodelay)
int(* recv_setup)(struct ath_softc *sc)
void(* sc_addba_stop)(struct ieee80211_node *, struct ieee80211_tx_ampdu *)
struct ath_txq * sc_ac2q[5]
u_int8_t sc_keymap[ATH_KEYBYTES]
void(* sc_setdefantenna)(struct ath_softc *, u_int)
const HAL_RATE_TABLE * sc_currates
struct ath_intr_stats sc_intr_stats
HAL_POWER_MODE sc_target_powerstate
enum ieee80211_phymode sc_curmode
HAL_NODE_STATS sc_halstats
struct callout sc_ledtimer
const HAL_RATE_TABLE * sc_rates[IEEE80211_MODE_MAX]
int(* sc_addba_request)(struct ieee80211_node *, struct ieee80211_tx_ampdu *, int, int, int)
HAL_POWER_MODE sc_cur_powerstate
struct ath_rx_status * sc_lastrs
uint32_t wlan_channels[4]
ath_bufhead sc_txbuf_mgmt
int sc_txq_node_psq_maxdepth
uint32_t sc_cur_rxchainmask
struct ath_descdma sc_rxdma
ath_bufhead sc_txbuf_list
int sc_txq_mcastq_maxdepth
struct ath_stats sc_stats
char sc_tx_ic_mtx_name[32]
uint32_t sc_rts_aggr_limit
struct ieee80211vap * sc_bslot[ATH_BCBUF]
u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]
struct ath_tx_radiotap_header sc_tx_th
u_int32_t sc_avgtsfdeltam
struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]
u_int32_t sc_hasenforcetxop
struct ath_tx_aggr_stats sc_aggr_stats
struct ath_descdma sc_txsdma
uint32_t sc_cur_txchainmask
enum ath_softc::@35 sc_updateslot
void(* sc_node_cleanup)(struct ieee80211_node *)
ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]
struct task sc_bstucktask
int(* sc_addba_response)(struct ieee80211_node *, struct ieee80211_tx_ampdu *, int, int, int)
void(* sc_bar_response)(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, int status)
struct ath_descdma sc_txdma_mgmt
struct ath_tx99 * sc_tx99
struct task sc_tsfoortask
struct ath_softc::@34 sc_hwmap[32]
u_int32_t sc_avgtsfdeltap
struct ath_rx_methods sc_rx
struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]
struct ath_descdma sc_bdma
u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]
struct ath_descdma sc_txdma
struct ath_descdma sc_txcompdma
u_int32_t sc_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA]
struct ath_tx_methods sc_tx
struct ieee80211_channel * sc_curchan
struct ath_softc::@36 sc_btcoex
struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]
struct ath_ratectrl * sc_rc
void(* sc_addba_response_timeout)(struct ieee80211_node *, struct ieee80211_tx_ampdu *)
struct ieee80211com sc_ic
struct ath_rx_radiotap_header sc_rx_th
HAL_POWER_MODE sc_target_selfgen_state
void(* sc_node_free)(struct ieee80211_node *)
struct ath_tid::@31 filtq
TAILQ_HEAD(, ath_buf) tid_q
struct ath_buf * tx_buf[ATH_TID_MAX_BUFS]
TAILQ_ENTRY(ath_tid) axq_qelem
void(* xmit_drain)(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
void(* xmit_attach_comp_func)(struct ath_softc *sc)
int(* xmit_setup)(struct ath_softc *sc)
int(* xmit_teardown)(struct ath_softc *sc)
void(* xmit_handoff)(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
void(* xmit_dma_restart)(struct ath_softc *sc, struct ath_txq *txq)
TAILQ_HEAD(axq_q_s, ath_buf) axq_q
struct ath_softc * axq_softc
TAILQ_HEAD(axq_t_s, ath_tid) axq_tidq
struct ath_buf * axq_holdingbf
void(* av_recv_pspoll)(struct ieee80211_node *, struct mbuf *)
void(* av_recv_mgmt)(struct ieee80211_node *, struct mbuf *, int, const struct ieee80211_rx_stats *, int, int)
void(* av_node_ps)(struct ieee80211_node *, int)
int(* av_set_tim)(struct ieee80211_node *, int)
struct ieee80211_quiet_ie quiet_ie
int(* av_newstate)(struct ieee80211vap *, enum ieee80211_state, int)
struct ieee80211vap av_vap
struct ath_buf * av_bcbuf
void(* av_bmiss)(struct ieee80211vap *)