38#include "ar5210/ar5k_0007.ini"
45 9, 9, 0, 0, 0, 0, 0, 2, 2, 6, 6, 6, 6, 6, 6, 2, 2
56#define AR_RC_SETTLE_TIME 20000
59 uint32_t resetMask, u_int delay);
73 struct ieee80211_channel *chan,
HAL_BOOL bChannelChange,
77#define N(a) (sizeof (a) /sizeof (a[0]))
78#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
87 "%s: opmode %u channel %u/0x%x %s channel\n", __func__,
88 opmode, chan->ic_freq, chan->ic_flags,
89 bChannelChange ?
"change" :
"same");
91 if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
102 "%s: invalid channel %u/0x%x; no mapping\n",
103 __func__, chan->ic_freq, chan->ic_flags);
213 if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
220 "%s: error init'ing transmit power\n", __func__);
248 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
249 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
263 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
265 "%s: noise floor calibration failed\n", __func__);
370#define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
394#define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
397 chan && IEEE80211_IS_CHAN_TURBO(chan) ?
398 "enabled" :
"disabled");
453 struct ieee80211_channel *chan, u_int chainMask,
457 uint32_t reg9858, reg985c, reg9868;
554 "%s: Performing 2nd Noise Cal\n", __func__);
557 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
591 uint32_t mask = resetMask ? resetMask : ~0;
627 if (pRD->
pcdac[i] != 63)
628 return pRD->
pcdac[i];
630 }
else if (dBm + 1 ==
AR_I2DBM(i) && i > 0) {
632 if (pRD->
pcdac[i] != 63 && pRD->
pcdac[i-1] != 63) {
633 interp = (350 * (pRD->
pcdac[i] - pRD->
pcdac[i-1])) + 999;
634 interp = (interp / 1000) + pRD->
pcdac[i-1];
638 }
else if (useNextEntry ==
AH_TRUE) {
640 if (pRD->
pcdac[i] != 63)
641 return pRD->
pcdac[i];
647 if (pRD->
pcdac[i] != 63)
648 return pRD->
pcdac[i];
652 ath_hal_printf(ah,
"%s: empty transmit power table?\n", __func__);
662 uint8_t pcdac, uint8_t *dBm)
670 if(pRD->
pcdac[i] == 63)
672 if (pcdac == pRD->
pcdac[i]) {
674 return pRD->
gainF[i];
676 if (pcdac > pRD->
pcdac[i])
678 if (pcdac < pRD->pcdac[i]) {
683 return pRD->
gainF[i];
692 "%s: no valid entries in the pcdac table: %d\n",
700 return pRD->
gainF[low];
703 *dBm = (low + high) + 3;
709 interp = ((pcdac - pRD->
pcdac[low]) * 1000) /
715 interp = ((interp * (pRD->
gainF[high] - pRD->
gainF[low])) + 999) / 1000;
718 return interp + pRD->
gainF[low];
738 uint8_t gainFRD, gainF36, gainF48, gainF54;
739 uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
747 if (freq < 5170 || freq > 5320) {
763 "%s: no calibrated regulatory domain matches the "
764 "current regularly domain (0x%0x)\n", __func__,
769 group = ((freq - 5170) / 10);
788 gainF36 =
getGainF(ah, pRD, cp[9], &dBm36);
789 gainF48 =
getGainF(ah, pRD, cp[8], &dBm48);
790 gainF54 =
getGainF(ah, pRD, cp[7], &dBm54);
794 static const uint16_t tpcScaleReductionTable[5] =
798 tpScale = tpcScaleReductionTable[
AH_PRIVATE(ah)->ah_tpScale];
799 if (dBmRD < tpScale+3)
804 gainFRD =
getGainF(ah, pRD, cp[14], &dontcare);
805 dBm36 =
AH_MIN(dBm36, dBmRD);
807 gainF36 =
getGainF(ah, pRD, cp[9], &dontcare);
808 dBm48 =
AH_MIN(dBm48, dBmRD);
810 gainF48 =
getGainF(ah, pRD, cp[8], &dontcare);
811 dBm54 =
AH_MIN(dBm54, dBmRD);
813 gainF54 =
getGainF(ah, pRD, cp[7], &dontcare);
818 cp[13] = cp[12] = cp[11] = cp[10] = cp[14];
821 cp[0] = gainFRD - gainF54;
822 cp[1] = gainFRD - gainF48;
823 cp[2] = gainFRD - gainF36;
825 cp[3] = cp[4] = cp[5] = cp[6] = 0;
837#define N(a) (sizeof (a) / sizeof (a[0]))
838 static const uint32_t pwr_regs_start[17] = {
839 0x00000000, 0x00000000, 0x00000000,
840 0x00000000, 0x00000000, 0xf0000000,
841 0xcc000000, 0x00000000, 0x00000000,
842 0x00000000, 0x0a000000, 0x000000e2,
843 0x0a000020, 0x01000002, 0x01000018,
844 0x40000000, 0x00000418
848 uint32_t pwr_regs[17];
850 OS_MEMCPY(pwr_regs, pwr_regs_start,
sizeof(pwr_regs));
861 if (cp[15] < 1 || cp[15] > 5) {
868 if (cp[16] < 1 || cp[16] > 5) {
877 for (i = 0; i < 7; i++)
879 for (i = 7; i < 15; i++)
883 pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F);
884 pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) |
885 ((cp[1] >> 3) & 0x03);
886 pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F);
887 pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) |
888 ((cp[4] >> 4) & 0x01);
889 pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07);
890 pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) |
891 ((cp[7] >> 5) & 0x01);
892 pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F);
893 pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07);
894 pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01);
895 pwr_regs[9] |= ((cp[13] << 5) & 0xE0);
896 pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07);
897 pwr_regs[11] |= ((cp[14] >> 5) & 0x01);
907 for (i = 0; i <
N(pwr_regs)-1; i++)
930 data = (data << 1) | 0x41;
944 nf = 0 - ((nf ^ 0x1ff) + 1);
948#define NORMAL_NF_THRESH (-72)
uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n)
HAL_BOOL ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)
#define HAL_NUM_TX_QUEUES
#define AR_TP_SCALING_ENTRIES
#define AR_REG_DOMAINS_MAX
static OS_INLINE HAL_CHANNEL_INTERNAL * ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
static __inline__ int isBigEndian(void)
static OS_INLINE uint16_t ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
#define HALDEBUG(_ah, __m,...)
void ath_hal_printf(struct ath_hal *, const char *,...)
#define OS_REG_WRITE(_ah, _reg, _val)
#define OS_MEMCPY(_d, _s, _n)
#define OS_REG_READ(_ah, _reg)
HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int)
HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest, int setChip)
HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int)
void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val)
void ar5210EnableRfKill(struct ath_hal *)
void ar5210SetRxFilter(struct ath_hal *, uint32_t)
#define AR5210_MAX_RATE_POWER
HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int)
void ar5210WriteAssocid(struct ath_hal *, const uint8_t *bssid, uint16_t assocId)
#define INIT_BCON_CNTRL_REG
#define INIT_CONFIG_STATUS
HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q)
HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int)
static HAL_BOOL ar5210SetResetReg(struct ath_hal *, uint32_t resetMask, u_int delay)
int16_t ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
HAL_BOOL ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
HAL_BOOL ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, HAL_BOOL *isIQdone)
HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
HAL_BOOL ar5210Disable(struct ath_hal *ah)
static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *)
HAL_BOOL ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan)
int16_t ar5210GetNoiseFloor(struct ath_hal *ah)
static uint8_t getGainF(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t pcdac, uint8_t *dBm)
HAL_RFGAIN ar5210GetRfgain(struct ath_hal *ah)
static uint8_t getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm)
static void ar5210SetOperatingMode(struct ath_hal *, int opmode)
void ar5210SetPCUConfig(struct ath_hal *ah)
HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
#define AR_RC_SETTLE_TIME
HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan, u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone)
HAL_BOOL ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_BOOL bChannelChange, HAL_RESET_TYPE resetType, HAL_STATUS *status)
static const REGISTER_VAL ar5k0007_init[]
static const uint8_t ar5k0007_pwrSettings[17]
static HAL_BOOL setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan, uint8_t cp[17])
HAL_BOOL ar5210PhyDisable(struct ath_hal *ah)
#define AR_PHY_TURBO_MODE
#define AR_DIAG_SW_DIS_RX
#define AR_STA_ID1_NO_PSPOLL
#define AR_STA_ID1_PWR_SV
#define AR_BEACON_RESET_TSF
#define AR_PCICFG_LED_BCTL
#define AR_PCICFG_LED_PEND
#define AR_STA_ID1_DESC_ANTENNA
#define AR_DIAG_SW_DIS_TX
#define AR_PCICFG_LED_ACT
#define AR_PCICFG_CLKRUNEN
struct tpcMap ee_tpc[AR_CHANNELS_MAX]
uint8_t ee_regDomain[AR_REG_DOMAINS_MAX]
uint32_t ah_staId1Defaults
uint8_t ah_bssid[IEEE80211_ADDR_LEN]
uint8_t ah_macaddr[IEEE80211_ADDR_LEN]
uint8_t pcdac[AR_TP_SCALING_ENTRIES]
uint8_t regdmn[AR_REG_DOMAINS_MAX]
uint8_t gainF[AR_TP_SCALING_ENTRIES]