FreeBSD kernel pms device code
tdesgl.c
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1/*******************************************************************************
2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
3*
4*Redistribution and use in source and binary forms, with or without modification, are permitted provided
5*that the following conditions are met:
6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7*following disclaimer.
8*2. Redistributions in binary form must reproduce the above copyright notice,
9*this list of conditions and the following disclaimer in the documentation and/or other materials provided
10*with the distribution.
11*
12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20
21**
22********************************************************************************/
23/*******************************************************************************/
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD$");
32#include <dev/pms/config.h>
33
37
41
46
47#ifdef FDS_SM
51#endif
52
53#ifdef FDS_DM
57#endif
58
62
63#ifdef INITIATOR_DRIVER
67#endif
68
69#ifdef TARGET_DRIVER
71#include <dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdxchg.h>
73#endif
74
77
78/* no more esgl related functions */
79#ifdef REMOVED
80/*****************************************************************************
81*! \brief tdsaEsglInit
82*
83* Purpose: This function initializes the linked list of ESGL pool
84*
85* \param tiRoot: Pointer to root data structure.
86*
87* \return: None
88*
89* \note
90*
91*****************************************************************************/
92osGLOBAL void
95 )
96{
97 tdsaRoot_t *tdsaRoot = (tdsaRoot_t *)tiRoot->tdData;
98 tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
99 tdsaEsglAllInfo_t *pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo);
100 tdsaEsglPagePool_t *pEsglPagePool;
101
102 bit32 pageno;
103 bit32 PagePhysAddrUpper;
104 bit32 PagePhysAddrLower;
105 bit32 prev_PagePhysAddrLower;
106 tdsaEsglPageInfo_t *pEsglPageInfo;
107 void *PageVirtAddr;
108 bit32 PageSizeInBytes;
109
110 /* for memory index requirement */
111 agsaRoot_t agRoot;
112 bit32 maxSALocks = 0;
113 bit32 usecsPerTick = 0;
114 agsaSwConfig_t SwConfig;
115 agsaMemoryRequirement_t memRequirement;
116 agsaQueueConfig_t *QueueConfig;
117 bit32 i;
118
119 TI_DBG6(("tdsaEsglInit: start\n"));
120
122 QueueConfig = &tdsaAllShared->QueueConfig;
123
124 for(i=0;i<QueueConfig->numInboundQueues;i++)
125 {
126 QueueConfig->inboundQueues[i].elementCount = tdsaAllShared->InboundQueueSize;
127 QueueConfig->inboundQueues[i].elementSize = tdsaAllShared->InboundQueueEleSize;
128 QueueConfig->inboundQueues[i].priority = tdsaAllShared->InboundQueuePriority[i];
129 QueueConfig->inboundQueues[i].reserved = 0;
130 }
131 for(i=0;i<QueueConfig->numOutboundQueues;i++)
132 {
133 QueueConfig->outboundQueues[i].elementCount = tdsaAllShared->OutboundQueueSize;
134 QueueConfig->outboundQueues[i].elementSize = tdsaAllShared->OutboundQueueEleSize;
135 QueueConfig->outboundQueues[i].interruptDelay = tdsaAllShared->OutboundQueueInterruptDelay[i]; /* default 0; no interrupt delay */
136 QueueConfig->outboundQueues[i].interruptCount = tdsaAllShared->OutboundQueueInterruptCount[i]; /* default 1*/
137 QueueConfig->outboundQueues[i].interruptVectorIndex = 0;
138 }
139
140 /*
141 hardcoded Queue numbers
142 */
143 QueueConfig->sasHwEventQueue = 0;
144 QueueConfig->sataNCQErrorEventQueue = 0;
147 SwConfig.eventLog1Option = 0;
148 SwConfig.eventLog2Option = 0;
149 SwConfig.fatalErrorInterrtuptEnable = 1;
150 SwConfig.fatalErrorInterruptVector = 1;
151 SwConfig.reserved = 0;
152
153
154 SwConfig.param3 = (void *)&(tdsaAllShared->QueueConfig);
155 /* to find out memRequirement */
156 saGetRequirements(&agRoot, &SwConfig, &memRequirement, &usecsPerTick, &maxSALocks);
157
158 /* initializes tdsaEsglAllInfo_t */
159 pEsglAllInfo->physAddrUpper = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].physAddrUpper;
160 pEsglAllInfo->physAddrLower = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].physAddrLower;
161 pEsglAllInfo->virtPtr = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].virtPtr;
162 pEsglAllInfo->NumEsglPages = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].numElements; /* NUM_ESGL_PAGES; number of esgl pages; configurable */
163 pEsglAllInfo->EsglPageSize = tdsaAllShared->loResource.loLevelMem.mem[memRequirement.count].singleElementLength; /* sizeof(agsaEsgl_t) */
164 pEsglAllInfo->NumFreeEsglPages = pEsglAllInfo->NumEsglPages;
165 pEsglPagePool = pEsglAllInfo->EsglPagePool;
166
167 TI_DBG6(("tdsaEsglInit: pEsglPagePool %p\n", pEsglPagePool));
168 TI_DBG6(("tdsaEsglInit: tdsaAllShared->loResource.loLevelMem.mem[18].singleElementLength %d\n", tdsaAllShared->loResource.loLevelMem.mem[18].singleElementLength));
169 TI_DBG6(("tdsaEsglInit: NumEsglPage %d EsglPageSize %d\n", pEsglAllInfo->NumEsglPages, pEsglAllInfo->EsglPageSize)); /* ?, 128 */
170 TI_DBG6(("tdsaEsglInit: NumFreeEsglPages %d\n", pEsglAllInfo->NumFreeEsglPages));
171 /* initialize the linked lists */
172 TDLIST_INIT_HDR(&pEsglAllInfo->freelist);
173
174
175 PageVirtAddr = pEsglAllInfo->virtPtr;
176 PagePhysAddrUpper = pEsglAllInfo->physAddrUpper;
177 PagePhysAddrLower = pEsglAllInfo->physAddrLower;
178 PageSizeInBytes = pEsglAllInfo->EsglPageSize;
179
180 TI_DBG6(("tdsaEsglInit: PageSizeInBytes 0x%x\n", PageSizeInBytes));
181 for (pageno = 0 ; pageno < pEsglAllInfo->NumEsglPages ; pageno++)
182 {
183 pEsglPageInfo = &(pEsglPagePool->EsglPages[pageno]);
184 OSSA_WRITE_LE_32(agRoot, pEsglPageInfo, OSSA_OFFSET_OF(pEsglPageInfo, physAddressUpper), PagePhysAddrUpper);
185 OSSA_WRITE_LE_32(agRoot, pEsglPageInfo, OSSA_OFFSET_OF(pEsglPageInfo, physAddressLower), PagePhysAddrLower);
186 pEsglPageInfo->len = PageSizeInBytes;
187 /* for debugging onlye*/
188 pEsglPageInfo->id = pageno+123;
189 pEsglPageInfo->agEsgl = (agsaEsgl_t *)PageVirtAddr;
190
191 /* for debugging only */
192 TI_DBG6(("tdsaEsglInit: index %d upper 0x%8x lower 0x%8x PageVirtAddr %p\n", pageno, PagePhysAddrUpper, PagePhysAddrLower, PageVirtAddr));
193
194
195 /* updates addresses */
196 prev_PagePhysAddrLower = PagePhysAddrLower;
197 PagePhysAddrLower += pEsglAllInfo->EsglPageSize;
198 /* if lower wraps around, increment upper */
199 if (PagePhysAddrLower <= prev_PagePhysAddrLower)
200 {
201 PagePhysAddrUpper++;
202 }
203
204 if (pageno == pEsglAllInfo->NumEsglPages - 1) /* last page */
205 {
206 pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = 0;
207 /* set bit31 to zero */
209 }
210 else
211 {
212 /* first and so on */
213 pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = PagePhysAddrLower;
214 pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = PagePhysAddrUpper;
215 pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = PageSizeInBytes; /* sizeof (agsaEsgl_t)*/
216 /* set bit31 to one */
218 }
219
220 TDLIST_INIT_ELEMENT(&pEsglPageInfo->tdlist);
221 tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
222 TDLIST_ENQUEUE_AT_TAIL(&pEsglPageInfo->tdlist, &pEsglAllInfo->freelist);
223 tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
224
225 PageVirtAddr = (bit8 *)PageVirtAddr + PageSizeInBytes;
226 } /* end for */
227
228
229
230#ifdef TD_INTERNAL_DEBUG /* for debugging only, for keep now */
231 for (pageno = 0 ; pageno < pEsglAllInfo->NumEsglPages ; pageno++)
232 {
233 TI_DBG6(("tdsaEsglInit: index %d EsglPages %p\n", pageno, &pEsglPagePool->EsglPages[pageno]));
234 TI_DBG6(("tdsaEsglInit: nextupper 0x%8x nextlower 0x%8x\n", pEsglPagePool->EsglPages[pageno].agEsgl->nextPageUpper, pEsglPagePool->EsglPages[pageno].agEsgl->nextPageLower));
235 }
236 TI_DBG6(("tdsaEsglInit: tdsaEsglPageInfo_t size %d 0x%x\n", sizeof(tdsaEsglPageInfo_t), sizeof(tdsaEsglPageInfo_t)));
237 TI_DBG6(("tdsaEsglInit: sizeof(SASG_DESCRIPTOR) %d 0x%x\n", sizeof(SASG_DESCRIPTOR), sizeof(SASG_DESCRIPTOR)));
238#endif
239
240 return;
241}
242
243
244/*****************************************************************************
245*! \brief tdsaGetEsglPages
246*
247* Purpose: This function prepares linked list of ESGL pages from
248* the given scatter-gather list.
249*
250* \param tiRoot: Pointer to root data structure.
251* \param EsglListHdr: pointer to list header where the list needs to be stored.
252* \param ptiSgl: Pointer to scatter-gather list.
253* \param virtSgl: virtual pointer to scatter-gather list.
254*
255* \return None
256*
257* \note -
258* 1. If we are out of ESGL pages, then no pages will be added to the list
259* pointed to by EsglListHdr. The list should be empty before calling
260* this function, so that after returning from this function, the
261* function can check for the emptyness of the list and find out if
262* any pages were added or not.
263*
264*****************************************************************************/
265osGLOBAL void
268 tdList_t *EsglListHdr,
269 tiSgl_t *ptiSgl,
270 tiSgl_t *virtSgl
271 )
272{
273 tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
274 tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
275
276 tdsaEsglAllInfo_t *pEsglAllInfo = &(tdsaAllShared->EsglAllInfo);
277 bit32 numSgElements = ptiSgl->len;
278 bit32 numEntriesPerPage = MAX_ESGL_ENTRIES;
279 bit32 numPagesRequired = ((numSgElements - 1) / numEntriesPerPage) + 1;
280 bit32 i, j;
281 tdList_t *tdlist_to_fill;
282 tdsaEsglPageInfo_t *page_to_fill;
283 tiSgl_t *tmp_tiSgl = (tiSgl_t *)virtSgl;
284 agsaSgl_t *pDesc;
285 agsaEsgl_t *agEsgl, *PrevagEsgl = agNULL;
286
287 TI_DBG6(("tdsaGetEsglPages: start\n"));
288 TI_DBG6(("tdsaGetEsglPages: pEsglPagePool %p\n", pEsglAllInfo->EsglPagePool));
289 TI_DBG6(("tdsaGetEsglPages: &(pEsglAllInfo->freelist) %p\n", &pEsglAllInfo->freelist));
290 TI_DBG6(("tdsaGetEsglPages: numSgElements %d numEntriesPerPage %d\n", numSgElements, numEntriesPerPage)); /* ?, 10 */
291 TI_DBG6(("tdsaGetEsglPages: numPagesRequired %d NumFreeEsglPages %d\n", numPagesRequired, pEsglAllInfo->NumFreeEsglPages)); /* 1, 2 */
292 TI_DBG6(("tdsaGetEsglPages: free Pages %d\n", pEsglAllInfo->NumFreeEsglPages));
293
294 if (numPagesRequired > pEsglAllInfo->NumFreeEsglPages)
295 {
296 TI_DBG1(("tdsaGetEsglPages:don't have enough freepages. required %d free %d\n", numPagesRequired, pEsglAllInfo->NumFreeEsglPages));
297 return;
298 }
299 tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
300 pEsglAllInfo->NumFreeEsglPages -= numPagesRequired;
301 tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
302
303
304
305#ifdef TD_INTERNAL_DEBUG /* for debugging only */
306 for (i=0; i < 2; i++)
307 {
308 /* remove one page from freelist */
309 tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
310 TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist);
311 tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
312
313 /* get the pointer to the page from list pointer */
314 page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill);
315 /* for debugging */
316 TI_DBG6(("tdsaGetEsglPages:page ID %d\n", page_to_fill->id));
317 agEsgl = page_to_fill->agEsgl;
318
319 pDesc = (SASG_DESCRIPTOR *)agEsgl;
320
321 for (j=0; j <numEntriesPerPage; j++)
322 {
323 TI_DBG6(("tdsaGetEsglPages: lower %d upper %d\n", pDesc->sgLower, pDesc->sgUpper));
324 TI_DBG6(("tdsaGetEsglPages: len %d\n", pDesc->len));
325 pDesc++;
326 }
327 TI_DBG6(("tdsaGetEsglPages: next lower %d next upper %d\n", agEsgl->nextPageLower, agEsgl->nextPageUpper));
328
329 }
330#endif /* for debugging only */
331
332 for (i = 0 ; i < numPagesRequired; i++)
333 {
334 /* remove one page from freelist */
335 tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
336 TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_fill, &pEsglAllInfo->freelist);
337 tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
338
339 /* get the pointer to the page from list pointer */
340 page_to_fill = TDLIST_OBJECT_BASE(tdsaEsglPageInfo_t, tdlist, tdlist_to_fill);
341 /* for debugging */
342 TI_DBG6(("tdsaGetEsglPages:page ID %d\n", page_to_fill->id));
343
344 agEsgl = page_to_fill->agEsgl;
345 pDesc = (agsaSgl_t *)agEsgl;
346
347 /*
348 adjust next page's address in the followings so that
349 the last entry must be (0,0,0)
350 */
351 if (i == numPagesRequired - 1) /* only one page of last page */
352 {
353 for (j=0; j < numSgElements; j++)
354 {
355 OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgLower), tmp_tiSgl->lower);
356 OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgUpper), tmp_tiSgl->upper);
357 OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, len), tmp_tiSgl->len);
359 pDesc++;
360 tmp_tiSgl++;
361 }
362 for (j=numSgElements; j < numEntriesPerPage; j++)
363 {
364 /* left over(unused) in the page */
365 pDesc->sgLower = 0x0;
366 pDesc->sgUpper = 0x0;
367 pDesc->len = 0x0;
369 pDesc++;
370 }
371 }
372 else
373 {
374 /* in case of muliple pages, first and later, except one page only or last page */
375 for (j=0; j <numEntriesPerPage - 1; j++) /* else */
376 {
377 /* do this till (last - 1) */
378 OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgLower), tmp_tiSgl->lower);
379 OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, sgUpper), tmp_tiSgl->upper);
380 OSSA_WRITE_LE_32(agRoot, pDesc, OSSA_OFFSET_OF(pDesc, len), tmp_tiSgl->len);
382 pDesc++;
383 tmp_tiSgl++;
384 }
385 numSgElements -= (numEntriesPerPage - 1);
386 }
387 if (PrevagEsgl != agNULL)
388 {
389 /* subsequent pages (second or later pages) */
390 PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = page_to_fill->physAddressLower;
391 PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = page_to_fill->physAddressUpper;
392 PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = numSgElements;
393 /* set bit31 to one */
395 }
396 PrevagEsgl = agEsgl;
397 /* put ESGL onto the EsglListHdr */
398 tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
399 TDLIST_ENQUEUE_AT_TAIL(tdlist_to_fill, EsglListHdr);
400 tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
401
402
403 } /* end for */
404 return;
405}
406
407
408/*****************************************************************************
409*! \brief tdsaFreeEsglPages
410*
411* Purpose: This function frees the ESGL pages pointed to by EsglListHdr
412* and puts them back onto the free list.
413*
414* \param tiRoot: Pointer to root data structure.
415* \param EsglListHdr: pointer to list header where the pages to be freed
416* are stored.
417*
418* \return: None
419*
420* \note -
421* 1. This function removes all the pages from the list until the list
422* empty and chains them at the end of the free list.
423*****************************************************************************/
424osGLOBAL void
427 tdList_t *EsglListHdr
428 )
429{
430 tdsaRoot_t *tdsaRoot = (tdsaRoot_t *) tiRoot->tdData;
431 tdsaContext_t *tdsaAllShared = (tdsaContext_t *)&tdsaRoot->tdsaAllShared;
432 tdsaEsglAllInfo_t *pEsglAllInfo = (tdsaEsglAllInfo_t *)&(tdsaAllShared->EsglAllInfo);
433 tdList_t *tdlist_to_free;
434
435 TI_DBG6(("tdsaFreeEsglPages: start\n"));
436 if (tiRoot == agNULL)
437 {
438 TI_DBG1(("tdsaFreeEsglPages: tiRoot is NULL\n"));
439 return;
440 }
441
442 if (EsglListHdr == agNULL)
443 {
444 TI_DBG1(("tdsaFreeEsglPages: EsglListHdr is NULL\n"));
445 return;
446 }
447
448 TI_DBG6(("tdsaFreeEsglPages: EsglListHdr %p\n", EsglListHdr));
449 tdsaSingleThreadedEnter(tiRoot, TD_ESGL_LOCK);
450 while (TDLIST_NOT_EMPTY(EsglListHdr))
451 {
452 TDLIST_DEQUEUE_FROM_HEAD(&tdlist_to_free, EsglListHdr);
453 TDLIST_ENQUEUE_AT_TAIL(tdlist_to_free, &pEsglAllInfo->freelist);
454 pEsglAllInfo->NumFreeEsglPages++;
455 }
456 tdsaSingleThreadedLeave(tiRoot, TD_ESGL_LOCK);
457 TI_DBG6(("tdsaFreeEsglPages: NumFreeEsglPages %d\n", pEsglAllInfo->NumFreeEsglPages));
458 return;
459}
460
461
462/*****************************************************************************
463*! \brief tdsaGetEsglPagesInfo
464*
465* Purpose: This function gets the information about the size of ESGL pages
466* and number pages to be configured.
467*
468* \param tiRoot: Pointer to root data structure.
469* \param pPageSize: pointer to bit32 where pagesize information is to be
470* stored
471* \param pNumPages: Pointer to bit32 where number of pages information is
472* to be stored
473*
474* \return: None
475*
476* \note -
477*
478*****************************************************************************/
479osGLOBAL void
482 bit32 *pPageSize,
483 bit32 *pNumPages
484 )
485{
486 char *buffer;
487 bit32 buffLen;
488 bit32 lenRecv = 0;
489 char *pLastUsedChar = agNULL;
490 char globalStr[] = "Global";
491 char SwParmsStr[] = "ESGLParms";
492 char tmpBuffer[DEFAULT_KEY_BUFFER_SIZE];
493 /* default value, defined in tdsatypes.h */
494 bit32 NumEsglPages = NUM_ESGL_PAGES;
495 TI_DBG6(("tdsaGetEsglPagesInfo: start \n"));
496
497 /*
498 calls ostiGetTransportParam which parses the configuration file to get
499 parameters.
500 */
501
502 buffer = tmpBuffer;
503 buffLen = sizeof(tmpBuffer);
504
505 osti_memset(buffer, 0, buffLen);
506
507
509 tiRoot,
510 globalStr, /* key */
511 SwParmsStr, /* subkey1 */
512 agNULL, /* subkey2 */
513 agNULL,
514 agNULL,
515 agNULL, /* subkey5 */
516 "NumESGLPg", /* valueName */
517 buffer,
518 buffLen,
519 &lenRecv
520 ) == tiSuccess) && (lenRecv != 0))
521 {
522
523 NumEsglPages = osti_strtoul(buffer, &pLastUsedChar, 10);
524 }
525
526 osti_memset(buffer, 0, buffLen);
527 lenRecv = 0;
528
529 TI_DBG6(("tdsaGetEsglPagesInfo: esgl page number %d\n",NumEsglPages));
530 *pPageSize = ESGL_PAGES_SIZE;/* sizeof(agsaEsgl_t); defined in tdsatypes.h */
531 *pNumPages = NumEsglPages;
532
533 return;
534}
535#endif
536
537
538
539
540
541
542
543
#define DEFAULT_KEY_BUFFER_SIZE
Definition: dmdefs.h:60
U32 ostiGetTransportParam(tiRoot_t *ptiRoot, S08 *key, S08 *subkey1, S08 *subkey2, S08 *subkey3, S08 *subkey4, S08 *subkey5, S08 *valueName, S08 *buffer, U32 bufferLen, U32 *lenReceived)
Definition: lxosapi.c:464
#define osti_strtoul(nptr, endptr, base)
Definition: osstring.h:75
#define osti_memset(s, c, n)
Definition: osstring.h:65
#define osGLOBAL
Definition: ostypes.h:147
#define agNULL
Definition: ostypes.h:151
unsigned int bit32
Definition: ostypes.h:99
unsigned char bit8
Definition: ostypes.h:97
The file defines the constants, data structure, and functions defined by LL API.
#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD)
Definition: sa.h:39
#define MAX_ESGL_ENTRIES
Definition: sa.h:822
The file defines the declaration of tSDK APIs.
GLOBAL void saGetRequirements(agsaRoot_t *agRoot, agsaSwConfig_t *swConfig, agsaMemoryRequirement_t *memoryRequirement, bit32 *usecsPerTick, bit32 *maxNumLocks)
Get the memory and lock requirement from LL layer.
Definition: sainit.c:74
The file defines the declaration of OS APIs.
the data structure describe SG list
Definition: sa.h:2738
data structure stores OS specific and LL specific context
Definition: sa.h:1658
data structure is used to pass information about the extended scatter-gather list (ESGL) to the LL La...
Definition: sa.h:2777
agsaSgl_t descriptor[MAX_ESGL_ENTRIES]
Definition: sa.h:2778
specify the memory allocation requirement for the SAS/SATA LL Layer
Definition: sa.h:2534
agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q]
Definition: sa.h:2441
agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q]
Definition: sa.h:2440
bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2431
bit16 numInboundQueues
Definition: sa.h:2428
bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2430
bit16 numOutboundQueues
Definition: sa.h:2429
bit32 elementCount
Definition: sa.h:2377
bit32 elementSize
Definition: sa.h:2379
bit32 reserved
Definition: sa.h:2385
bit32 priority
Definition: sa.h:2380
bit32 elementCount
Definition: sa.h:2390
bit32 elementSize
Definition: sa.h:2393
bit32 interruptCount
Definition: sa.h:2399
bit32 interruptVectorIndex
Definition: sa.h:2401
bit32 interruptDelay
Definition: sa.h:2394
data structure used to pass information about the scatter-gather list to the LL Layer
Definition: sa.h:2755
bit32 len
Definition: sa.h:2758
bit32 sgLower
Definition: sa.h:2756
bit32 sgUpper
Definition: sa.h:2757
bit32 extReserved
Definition: sa.h:2759
structure describe software configuration
Definition: sa.h:2319
bit32 eventLog1Option
Definition: sa.h:2328
bit32 eventLog2Option
Definition: sa.h:2329
bit32 sizefEventLog2
Definition: sa.h:2327
bit32 sizefEventLog1
Definition: sa.h:2326
void * param3
Definition: sa.h:2346
bit32 fatalErrorInterruptVector
Definition: sa.h:2333
data structure for SAS/SATA context at TD layer
Definition: tdsatypes.h:199
data structure for ESGL pool information
Definition: tdsatypes.h:149
tdList_t freelist
Definition: tdsatypes.h:154
tdsaEsglPagePool_t * EsglPagePool
Definition: tdsatypes.h:161
bit32 NumFreeEsglPages
Definition: tdsatypes.h:156
data structure for ESLG page
Definition: tdsatypes.h:123
bit32 physAddressUpper
Definition: tdsatypes.h:125
agsaEsgl_t * agEsgl
Definition: tdsatypes.h:128
bit32 physAddressLower
Definition: tdsatypes.h:126
data structure for ESLG page pool
Definition: tdsatypes.h:137
tdsaEsglPageInfo_t EsglPages[1]
Definition: tdsatypes.h:138
the root data structure for TD layer
Definition: tdsatypes.h:362
tdsaContext_t tdsaAllShared
Definition: tdsatypes.h:364
Definition: titypes.h:61
void * tdData
Definition: titypes.h:63
bit32 lower
Definition: titypes.h:123
bit32 len
Definition: titypes.h:125
bit32 upper
Definition: titypes.h:124
#define CLEAR_ESGL_EXTEND(val)
Definition: tddefs.h:383
#define SET_ESGL_EXTEND(val)
Definition: tddefs.h:380
#define HOST_EVENT_LOG_SIZE
Definition: tddefs.h:1088
__FBSDID("$FreeBSD$")
#define TDLIST_OBJECT_BASE(baseType, fieldName, fieldPtr)
Definition: tdlist.h:161
#define TDLIST_NOT_EMPTY(listHdr)
Definition: tdlist.h:76
#define TDLIST_ENQUEUE_AT_TAIL(toAddHdr, listHdr)
Definition: tdlist.h:65
#define TDLIST_INIT_ELEMENT(hdr)
Definition: tdlist.h:51
#define TDLIST_DEQUEUE_FROM_HEAD(atHeadHdr, listHdr)
Definition: tdlist.h:93
#define TDLIST_INIT_HDR(hdr)
Definition: tdlist.h:45
void tdsaSingleThreadedEnter(tiRoot_t *ptiRoot, bit32 queueId)
Definition: tdmisc.c:2862
void tdsaSingleThreadedLeave(tiRoot_t *ptiRoot, bit32 queueId)
Definition: tdmisc.c:2875
osGLOBAL void tdsaGetSwConfigParams(tiRoot_t *tiRoot)
Definition: tdport.c:123
osGLOBAL void tdsaGetEsglPages(tiRoot_t *tiRoot, tdList_t *EsglListHdr, tiSgl_t *ptiSgl, tiSgl_t *virtSgl)
osGLOBAL void tdsaEsglInit(tiRoot_t *tiRoot)
osGLOBAL void tdsaGetEsglPagesInfo(tiRoot_t *tiRoot, bit32 *PageSize, bit32 *NumPages)
osGLOBAL void tdsaFreeEsglPages(tiRoot_t *tiRoot, tdList_t *EsglListHdr)
#define ESGL_PAGES_SIZE
Definition: tdsatypes.h:35
#define NUM_ESGL_PAGES
Definition: tdsatypes.h:36
@ tiSuccess
Definition: tidefs.h:67
#define TI_DBG6(a)
Definition: tiglobal.h:53
#define TI_DBG1(a)
Definition: tiglobal.h:48