FreeBSD kernel pms device code
sa.h
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1/*******************************************************************************
2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
3*
4*Redistribution and use in source and binary forms, with or without modification, are permitted provided
5*that the following conditions are met:
6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7*following disclaimer.
8*2. Redistributions in binary form must reproduce the above copyright notice,
9*this list of conditions and the following disclaimer in the documentation and/or other materials provided
10*with the distribution.
11*
12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20*
21* $FreeBSD$
22*
23********************************************************************************/
24/*******************************************************************************/
28/******************************************************************************/
29
30#ifndef __SA_H__
31#define __SA_H__
32
33#include <dev/pms/RefTisa/sallsdk/api/sa_spec.h>
34#include <dev/pms/RefTisa/sallsdk/api/sa_err.h>
35
36/* TestBase needed to have the 'Multi-Data fetch disable' feature */
37#define SA_CONFIG_MDFD_REGISTRY
38
39#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \
40 (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
41
42#if defined(SA_CPU_LITTLE_ENDIAN)
43
44#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
45 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
46
47#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
48 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
49
50#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
51 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
52
53#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
54 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
55
56#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
58 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
59
60#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
64 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
65
66#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
67 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
68 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
69
70#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
71 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
72 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
73 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
74 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
75
76#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
77 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
78
79
80#elif defined(SA_CPU_BIG_ENDIAN)
81
82#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
84 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
85
86#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
90 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
91
92#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
93 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
94 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
95
96#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
97 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
98 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
99 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
100 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
101
102#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
103 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
104
105#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
106 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
107
108#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
109 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
110
111#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
112 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
113
114#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
115 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
116
117#else
118
119#error (Host CPU endianess undefined!!)
120
121#endif
122
123#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \
124 OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \
125 OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \
126 OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \
127 OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved);
128
129
130/**************************************************************************
131 * define byte swap macro *
132 **************************************************************************/
138#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \
139 ((((bit16)(_x))&0xFF00)>>8)))
140
146#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \
147 ((((bit32)(_x))&0x0000FF00)<<8)| \
148 ((((bit32)(_x))&0x00FF0000)>>8)| \
149 ((((bit32)(_x))&0xFF000000)>>24)))
150
151
152#if defined(SA_CPU_LITTLE_ENDIAN)
153
159#ifndef LEBIT16_TO_BIT16
160#define LEBIT16_TO_BIT16(_x) (_x)
161#endif
162
168#ifndef BIT16_TO_LEBIT16
169#define BIT16_TO_LEBIT16(_x) (_x)
170#endif
171
177#ifndef BEBIT16_TO_BIT16
178#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
179#endif
180
186#ifndef BIT16_TO_BEBIT16
187#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
188#endif
189
195#ifndef LEBIT32_TO_BIT32
196#define LEBIT32_TO_BIT32(_x) (_x)
197#endif
198
204#ifndef BIT32_TO_LEBIT32
205#define BIT32_TO_LEBIT32(_x) (_x)
206#endif
207
213#ifndef BEBIT32_TO_BIT32
214#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
215#endif
216
222#ifndef BIT32_TO_BEBIT32
223#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
224#endif
225
226
227/*
228 * bit8 to Byte[x] of bit32
229 */
230#ifndef BIT8_TO_BIT32_B0
231#define BIT8_TO_BIT32_B0(_x) ((bit32)(_x))
232#endif
233
234#ifndef BIT8_TO_BIT32_B1
235#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8)
236#endif
237
238#ifndef BIT8_TO_BIT32_B2
239#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16)
240#endif
241
242#ifndef BIT8_TO_BIT32_B3
243#define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24)
244#endif
245
246/*
247 * Byte[x] of bit32 to bit8
248 */
249#ifndef BIT32_B0_TO_BIT8
250#define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
251#endif
252
253#ifndef BIT32_B1_TO_BIT8
254#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
255#endif
256
257#ifndef BIT32_B2_TO_BIT8
258#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
259#endif
260
261#ifndef BIT32_B3_TO_BIT8
262#define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
263#endif
264
265#elif defined(SA_CPU_BIG_ENDIAN)
266
272#ifndef LEBIT16_TO_BIT16
273#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
274#endif
275
281#ifndef BIT16_TO_LEBIT16
282#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
283#endif
284
290#ifndef BEBIT16_TO_BIT16
291#define BEBIT16_TO_BIT16(_x) (_x)
292#endif
293
299#ifndef BIT16_TO_BEBIT16
300#define BIT16_TO_BEBIT16(_x) (_x)
301#endif
302
308#ifndef LEBIT32_TO_BIT32
309#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
310#endif
311
317#ifndef BIT32_TO_LEBIT32
318#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
319#endif
320
326#ifndef BEBIT32_TO_BIT32
327#define BEBIT32_TO_BIT32(_x) (_x)
328#endif
329
335#ifndef BIT32_TO_BEBIT32
336#define BIT32_TO_BEBIT32(_x) (_x)
337#endif
338
339
340/*
341 * bit8 to Byte[x] of bit32
342 */
343#ifndef BIT8_TO_BIT32_B0
344#define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24)
345#endif
346
347#ifndef BIT8_TO_BIT32_B1
348#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16)
349#endif
350
351#ifndef BIT8_TO_BIT32_B2
352#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8)
353#endif
354
355#ifndef BIT8_TO_BIT32_B3
356#define BIT8_TO_BIT32_B3(_x) ((bit32)(_x))
357#endif
358
359/*
360 * Byte[x] of bit32 to bit8
361 */
362#ifndef BIT32_B0_TO_BIT8
363#define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
364#endif
365
366#ifndef BIT32_B1_TO_BIT8
367#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
368#endif
369
370#ifndef BIT32_B2_TO_BIT8
371#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
372#endif
373
374#ifndef BIT32_B3_TO_BIT8
375#define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
376#endif
377
378#else
379
380#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN
381
382#endif
383
384
385#if defined(SA_DMA_LITTLE_ENDIAN)
386
387/*
388 * ** bit32 to bit32
389 * */
390#ifndef DMA_BIT32_TO_BIT32
391#define DMA_BIT32_TO_BIT32(_x) (_x)
392#endif
393
394#ifndef DMA_LEBIT32_TO_BIT32
395#define DMA_LEBIT32_TO_BIT32(_x) (_x)
396#endif
397
398#ifndef DMA_BEBIT32_TO_BIT32
399#define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
400#endif
401
402#ifndef BIT32_TO_DMA_BIT32
403#define BIT32_TO_DMA_BIT32(_x) (_x)
404#endif
405
406#ifndef BIT32_TO_DMA_LEBIT32
407#define BIT32_TO_DMA_LEBIT32(_x) (_x)
408#endif
409
410#ifndef BIT32_TO_DMA_BEBIT32
411#define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
412#endif
413
414
415/*
416 * ** bit16 to bit16
417 * */
418#ifndef DMA_BIT16_TO_BIT16
419#define DMA_BIT16_TO_BIT16(_x) (_x)
420#endif
421
422#ifndef DMA_LEBIT16_TO_BIT16
423#define DMA_LEBIT16_TO_BIT16(_x) (_x)
424#endif
425
426#ifndef DMA_BEBIT16_TO_BIT16
427#define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
428#endif
429
430#ifndef BIT16_TO_DMA_BIT16
431#define BIT16_TO_DMA_BIT16(_x) (_x)
432#endif
433
434#ifndef BIT16_TO_DMA_LEBIT16
435#define BIT16_TO_DMA_LEBIT16(_x) (_x)
436#endif
437
438#ifndef BIT16_TO_DMA_BEBIT16
439#define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
440#endif
441
442#if defined(SA_CPU_LITTLE_ENDIAN)
443
444#ifndef BEBIT32_TO_DMA_BEBIT32
445#define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
446#endif
447
448#ifndef LEBIT32_TO_DMA_LEBIT32
449#define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
450#endif
451
452#ifndef DMA_LEBIT32_TO_LEBIT32
453#define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
454#endif
455
456#ifndef DMA_BEBIT32_TO_BEBIT32
457#define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
458#endif
459
460/*
461 * ** bit16 to bit16
462 * */
463#ifndef BEBIT16_TO_DMA_BEBIT16
464#define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
465#endif
466
467#ifndef LEBIT16_TO_DMA_LEBIT16
468#define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
469#endif
470
471#ifndef DMA_LEBIT16_TO_LEBIT16
472#define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
473#endif
474
475#ifndef DMA_BEBIT16_TO_BEBIT16
476#define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
477#endif
478
479#else /* defined(SA_CPU_BIG_ENDIAN) */
480
481
482/*
483 * ** bit32 to bit32
484 * */
485#ifndef BEBIT32_TO_DMA_BEBIT32
486#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
487#endif
488
489#ifndef LEBIT32_TO_DMA_LEBIT32
490#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
491#endif
492
493#ifndef DMA_LEBIT32_TO_LEBIT32
494#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
495#endif
496
497#ifndef DMA_BEBIT32_TO_BEBIT32
498#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
499#endif
500
501/*
502 * ** bit16 to bit16
503 * */
504#ifndef BEBIT16_TO_DMA_BEBIT16
505#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
506#endif
507
508#ifndef LEBIT16_TO_DMA_LEBIT16
509#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
510#endif
511
512#ifndef DMA_LEBIT16_TO_LEBIT16
513#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
514#endif
515
516#ifndef DMA_BEBIT16_TO_BEBIT16
517#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
518#endif
519
520#endif
521
522/*
523 * bit8 to Byte[x] of bit32
524 */
525#ifndef BIT8_TO_DMA_BIT32_B0
526#define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x))
527#endif
528
529#ifndef BIT8_TO_DMA_BIT32_B1
530#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8)
531#endif
532
533#ifndef BIT8_TO_DMA_BIT32_B2
534#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16)
535#endif
536
537#ifndef BIT8_TO_DMA_BIT32_B3
538#define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24)
539#endif
540
541/*
542 * Byte[x] of bit32 to bit8
543 */
544#ifndef DMA_BIT32_B0_TO_BIT8
545#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
546#endif
547
548#ifndef DMA_BIT32_B1_TO_BIT8
549#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
550#endif
551
552#ifndef DMA_BIT32_B2_TO_BIT8
553#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
554#endif
555
556#ifndef DMA_BIT32_B3_TO_BIT8
557#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
558#endif
559
560/*| |
561 | end of DMA access macros for LITTLE ENDIAN |
562 ---------------------------------------------------------------------
563 */
564
565#elif defined(SA_DMA_BIG_ENDIAN) /* DMA big endian */
566
567/*--------------------------------------------------------------------
568 | DMA buffer access macros for BIG ENDIAN |
569 | |
570 */
571
572/* bit32 to bit32 */
573#ifndef DMA_BEBIT32_TO_BIT32
574#define DMA_BEBIT32_TO_BIT32(_x) (_x)
575#endif
576
577#ifndef DMA_LEBIT32_TO_BIT32
578#define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
579#endif
580
581#ifndef BIT32_TO_DMA_BIT32
582#define BIT32_TO_DMA_BIT32(_x) (_x)
583#endif
584
585#ifndef BIT32_TO_DMA_LEBIT32
586#define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
587#endif
588
589#ifndef BIT32_TO_DMA_BEBIT32
590#define BIT32_TO_DMA_BEBIT32(_x) (_x)
591#endif
592
593/* bit16 to bit16 */
594#ifndef DMA_BEBIT16_TO_BIT16
595#define DMA_BEBIT16_TO_BIT16(_x) (_x)
596#endif
597
598#ifndef DMA_LEBIT16_TO_BIT16
599#define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
600#endif
601
602#ifndef BIT16_TO_DMA_BIT16
603#define BIT16_TO_DMA_BIT16(_x) (_x)
604#endif
605
606#ifndef BIT16_TO_DMA_LEBIT16
607#define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
608#endif
609
610#ifndef BIT16_TO_DMA_BEBIT16
611#define BIT16_TO_DMA_BEBIT16(_x) (_x)
612#endif
613
614
615#if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */
616
617/* bit32 to bit32 */
618#ifndef BEBIT32_TO_DMA_BEBIT32
619#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
620#endif
621
622#ifndef LEBIT32_TO_DMA_LEBIT32
623#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
624#endif
625
626#ifndef DMA_LEBIT32_TO_LEBIT32
627#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
628#endif
629
630#ifndef DMA_BEBIT32_TO_BEBIT32
631#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
632#endif
633
634/* bit16 to bit16 */
635#ifndef BEBIT16_TO_DMA_BEBIT16
636#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
637#endif
638
639#ifndef LEBIT16_TO_DMA_LEBIT16
640#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
641#endif
642
643#ifndef DMA_LEBIT16_TO_LEBIT16
644#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
645#endif
646
647#ifndef DMA_BEBIT16_TO_BEBIT16
648#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
649#endif
650
651
652#else /* defined(SA_CPU_BIG_ENDIAN) */
653
654/* bit32 to bit32 */
655#ifndef BEBIT32_TO_DMA_BEBIT32
656#define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
657#endif
658
659#ifndef LEBIT32_TO_DMA_LEBIT32
660#define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
661#endif
662
663#ifndef DMA_LEBIT32_TO_LEBIT32
664#define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
665#endif
666
667#ifndef DMA_BEBIT32_TO_BEBIT32
668#define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
669#endif
670
671/* bit16 to bit16 */
672#ifndef BEBIT16_TO_DMA_BEBIT16
673#define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
674#endif
675
676#ifndef LEBIT16_TO_DMA_LEBIT16
677#define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
678#endif
679
680#ifndef DMA_LEBIT16_TO_LEBIT16
681#define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
682#endif
683
684#ifndef DMA_BEBIT16_TO_BEBIT16
685#define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
686#endif
687
688#endif
689
690/*
691 * bit8 to Byte[x] of bit32
692 */
693#ifndef BIT8_TO_DMA_BIT32_B0
694#define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24)
695#endif
696
697#ifndef BIT8_TO_DMA_BIT32_B1
698#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16)
699#endif
700
701#ifndef BIT8_TO_DMA_BIT32_B2
702#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8)
703#endif
704
705#ifndef BIT8_TO_DMA_BIT32_B3
706#define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x))
707#endif
708
709/*
710 * ** Byte[x] of bit32 to bit8
711 * */
712#ifndef DMA_BIT32_B0_TO_BIT8
713#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
714#endif
715
716#ifndef DMA_BIT32_B1_TO_BIT8
717#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
718#endif
719
720#ifndef DMA_BIT32_B2_TO_BIT8
721#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
722#endif
723
724#ifndef DMA_BIT32_B3_TO_BIT8
725#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
726#endif
727
728/*| |
729 | end of DMA access macros for BIG ENDIAN |
730 ---------------------------------------------------------------------
731*/
732#else
733
734#error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN
735
736#endif /* DMA endian */
737/*
738 * End of DMA buffer access macros *
739 * *
740 **********************************************************************
741 */
742
743/************************************************************************************
744 * *
745 * Constants defined for LL Layer starts *
746 * *
747 ************************************************************************************/
748
749/*********************************************************
750 * sTSDK LL revision and Interface revision, FW version
751 *********************************************************/
752
753#define FW_THIS_VERSION_SPC12G 0x03060005
754
755#define FW_THIS_VERSION_SPC6G 0x02092400
756#define FW_THIS_VERSION_SPC 0x01110000
757
758
759#define STSDK_LL_INTERFACE_VERSION 0x20A
760#define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02030401 */
761#define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G
762#define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G
763#define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G
764#define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000
766#define STSDK_LL_12G_INTERFACE_VERSION 0x302
767#define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G
768#define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G
769#define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G
770#define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000
772#define STSDK_LL_SPC_VERSION 0x01100000
773#define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC
774#define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502
776#define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00
777/*************************************************
778 * constants for API return values
779 *************************************************/
780#define AGSA_RC_SUCCESS 0x00
781#define AGSA_RC_FAILURE 0x01
782#define AGSA_RC_BUSY 0x02
783/* current only return from saGetControllerInfo() and saGetControllerStatus() */
784#define AGSA_RC_HDA_NO_FW_RUNNING 0x03
785#define AGSA_RC_FW_NOT_IN_READY_STATE 0x04
786/* current only return from saInitialize() for version checking */
787#define AGSA_RC_VERSION_INCOMPATIBLE 0x05
788#define AGSA_RC_VERSION_UNTESTED 0x06
789#define AGSA_RC_NOT_SUPPORTED 0x07
790#define AGSA_RC_COMPLETE 0x08
791
792/*************************************************
793 * constants for type field in agsaMem_t
794 *************************************************/
795#define AGSA_CACHED_MEM 0x00
796#define AGSA_DMA_MEM 0x01
797#define AGSA_CACHED_DMA_MEM 0x02
799#ifdef SA_ENABLE_TRACE_FUNCTIONS
800#ifdef FAST_IO_TEST
801#define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
802#else
803#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
804#endif
805#else
806#ifdef FAST_IO_TEST
807#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
808#else
809#define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q)
810#endif
811#endif /* END SA_ENABLE_TRACE_FUNCTIONS */
812
813
814/**********************************
815 * default constant for phy count
816 **********************************/
817#define AGSA_MAX_VALID_PHYS 16 /* was 8 for SPC */
819/************************************
820 * default constant for Esgl entries
821 ************************************/
822#define MAX_ESGL_ENTRIES 10
824/*******************************************
825 * constant for max inbound/outbound queues
826 *******************************************/
827#define AGSA_MAX_INBOUND_Q 64
828#define AGSA_MAX_OUTBOUND_Q 64
829#define AGSA_MAX_BEST_INBOUND_Q 16 /* Max inbound Q number with good IO performance */
830
831/****************************
832 * Phy Control constants
833 ****************************/
834#define AGSA_PHY_LINK_RESET 0x01
835#define AGSA_PHY_HARD_RESET 0x02
836#define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyControl */
837#define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */
838#define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */
839#define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10
840#define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12
841#define AGSA_PHY_COMINIT_OOB 0x20
842
843#define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */
844#define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After capturing the errors, the hardware error counters are cleared and restarted. */
845#define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandwidth counters. */
846#define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */
847#define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY specified in the phyID parameter */
848#define AGSA_PHY_SNW3_PAGE 0x06
849#define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */
850#define AGSA_SAS_PHY_MISC_PAGE 0x08
851#define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and backoff threshold parameters. */
852
853/*****************
854 * HW Reset
855 *****************/
856#define AGSA_CHIP_RESET 0x00
857#define AGSA_SOFT_RESET 0x01
859/***************************************
860 * Discovery Types
861 ***************************************/
862#define AG_SA_DISCOVERY_TYPE_SAS 0x00
863#define AG_SA_DISCOVERY_TYPE_SATA 0x01
865/***************************************
866 * Discovery Options
867 ***************************************/
868#define AG_SA_DISCOVERY_OPTION_FULL_START 0x00
869#define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01
870#define AG_SA_DISCOVERY_OPTION_ABORT 0x02
872/****************************************************************
873 * SSP/SMP/SATA Request type
874 ****************************************************************/
875/* bit31-28 - request type
876 bit27-16 - reserved
877 bit15-10 - SATA ATAP
878 bit9-8 - direction
879 bit7 - AUTO
880 bit6 - reserved
881 bit5 - EXT
882 bit4 - MSG
883 bit3-0 - Initiator, target or task mode (1 to 8)
884 */
885#define AGSA_REQTYPE_MASK 0xF0000000
886#define AGSA_REQ_TYPE_UNKNOWN 0x00000000
887#define AGSA_SSP_REQTYPE 0x80000000
888#define AGSA_SMP_REQTYPE 0x40000000
889#define AGSA_SATA_REQTYPE 0x20000000
890
891#define AGSA_DIR_MASK 0x00000300
892#define AGSA_AUTO_MASK 0x00000080
893#define AGSA_SATA_ATAP_MASK 0x0000FC00
894
895#define AGSA_DIR_NONE 0x00000000
896#define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100
897#define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200
899/* bit definition - AUTO mode */
900#define AGSA_AUTO_GOOD_RESPONSE 0x00000080
901
902/* request type - not bit difination */
903#define AGSA_SSP_INIT 0x00000001
904#define AGSA_SSP_TGT_MODE 0x00000003
905#define AGSA_SSP_TASK_MGNT 0x00000005
906#define AGSA_SSP_TGT_RSP 0x00000006
907#define AGSA_SMP_INIT 0x00000007
908#define AGSA_SMP_TGT 0x00000008
909
910/* request type for SSP Initiator and extend */
911#define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT)
912
913/* request type for SSP Initiator and indirect */
914#define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT)
915
916/* bit definition */
917#define AGSA_MSG 0x00000010
918#define AGSA_SSP_EXT_BIT 0x00000020
919#define AGSA_SSP_INDIRECT_BIT 0x00000040
920#define AGSA_MSG_BIT AGSA_MSG >> 2
921
922/* agsaSSPIniEncryptIOStartCmd_t dirMTlr bits*/
923#define AGSA_INDIRECT_CDB_BIT 0x00000008
924#define AGSA_SKIP_MASK_BIT 0x00000010
925#define AGSA_ENCRYPT_BIT 0x00000020
926#define AGSA_DIF_BIT 0x00000040
927#define AGSA_DIF_LA_BIT 0x00000080
928#define AGSA_DIRECTION_BITS 0x00000300
929#define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000
930#define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000
931
932/* agsaSSPTgtIOStartCmd_t INITagAgrDir bits */
933#define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */
934#define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */
935#define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */
936#define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */
937#define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */
938#define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */
939#define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */
940#define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */
941#define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */
942#define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */
943#define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */
944#define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */
945#define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */
946
947
948/* agsaSSPIniEncryptIOStartCmd_t DIF_flags bit definitions */
949#define AGSA_DIF_UPDATE_BITS 0xFC000000
950#define AGSA_DIF_VERIFY_BITS 0x03F00000
951#define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000
952#define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040
953#define AGSA_DIF_CRC_SEED_BIT 0x00000020
954#define AGSA_DIF_CRC_INVERT_BIT 0x00000010
955#define AGSA_DIF_CRC_VERIFY_BIT 0x00000008
956#define AGSA_DIF_OP_BITS 0x00000007
957
958#define AGSA_DIF_OP_INSERT 0x00000000
959#define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001
960#define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002
961#define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003
962#define AGSA_DIF_OP_RESERVED2 0x00000004
963#define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005
964#define AGSA_DIF_OP_RESERVED3 0x00000006
965#define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007
966
967
968/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsLo bit definitions */
969#define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000
970#define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010
971#define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C
972#define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002
973
974/* Cipher mode to be used for this I/O. */
975#define AGSA_ENCRYPT_ECB_Mode 0
976#define AGSA_ENCRYPT_XTS_Mode 0x6
977
978/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsHi bit definitions */
979#define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0
980#define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F
981
982/* defined in the sTSDK spec. */
983#define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT)
984#define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT)
985#define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT)
986#define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE)
987#define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE)
988#define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE)
989#define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE)
990#define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE)
991#define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE)
992#define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT)
993#define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP)
994#define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT)
995#define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT)
996#define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG)
997#define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG)
998#define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG)
999#define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT)
1000#define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT)
1002#define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT)
1003#define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT)
1005#define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG)
1006#define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG)
1007#define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG)
1008#define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG)
1009
1010#define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF
1011
1012#define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400
1013#define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800
1014#define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00
1015#define AGSA_SATA_ATAP_NON_DATA 0x00001000
1016#define AGSA_SATA_ATAP_PIO 0x00001400
1017#define AGSA_SATA_ATAP_DMA 0x00001800
1018#define AGSA_SATA_ATAP_NCQ 0x00001C00
1019#define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000
1020#define AGSA_SATA_ATAP_PKT 0x00002400
1021
1022#define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA)
1023#define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO)
1024#define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA)
1025#define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ)
1026#define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO)
1027#define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA)
1028#define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ)
1029#define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET)
1030#define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT)
1031#define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT)
1032#define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT)
1033#define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT)
1034#define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT)
1035
1036
1037#define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG)
1038#define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG)
1039#define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG)
1040#define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG)
1041#define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG)
1042#define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG)
1043#define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG)
1044#define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1045#define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1046#define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1047/* TestBase */
1048#define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG)
1052#define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF
1054/****************************************************************************
1055** INBOUND Queue related macros
1056****************************************************************************/
1057#define AGSA_IBQ_PRIORITY_NORMAL 0x0
1058#define AGSA_IBQ_PRIORITY_HIGH 0x1
1059
1060/****************************************************************************
1061** Phy properties related macros
1062****************************************************************************/
1063/* link rate */
1064#define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */
1065#define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */
1066#define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */
1067#define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */
1068#define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */
1069
1070/* SAS/SATA mode */
1071#define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */
1072#define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */
1073#define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */
1074
1075/* control spin-up hold */
1076#define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */
1077#define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */
1078#define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */
1079
1080/****************************************************************************
1081** Device Info related macros
1082****************************************************************************/
1083/* S (SAS/SATA) */
1084#define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */
1085#define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */
1086#define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */
1087
1088/* Rate (link-rate) */
1089#define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */
1090#define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */
1091#define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */
1092#define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */
1093#define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */
1094
1095/* devType */
1096#define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */
1097#define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */
1098#define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */
1099#define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */
1100
1101/*****************************************************************************
1102** SAS TM Function definitions see SAS spec p308 Table 105 (Revision 7)
1103*****************************************************************************/
1104#define AGSA_ABORT_TASK 0x01
1105#define AGSA_ABORT_TASK_SET 0x02
1106#define AGSA_CLEAR_TASK_SET 0x04
1107#define AGSA_LOGICAL_UNIT_RESET 0x08
1108#define AGSA_IT_NEXUS_RESET 0x10
1109#define AGSA_CLEAR_ACA 0x40
1110#define AGSA_QUERY_TASK 0x80
1111#define AGSA_QUERY_TASK_SET 0x81
1112#define AGSA_QUERY_UNIT_ATTENTION 0x82
1113
1114/*****************************************************************************
1115** SAS TM Function Response Code see SAS spec p312 Table 111 (Revision 7)
1116*****************************************************************************/
1117#define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
1118#define AGSA_INVALID_FRAME 0x2
1119#define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4
1120#define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
1121#define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
1122#define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9
1123/* SAS spec 9.2.2.5.3 p356 Table 128 (Revision 9e) */
1124#define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA
1125
1126#define AGSA_SATA_BSY_OVERRIDE 0x00080000
1127#define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000
1128
1129#define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40
1130#define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36
1131
1132/* SATA Initiator Request option field defintion */
1133#define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001
1134#define AGSA_SATA_ENABLE_ENCRYPTION 0x000004
1135#define AGSA_SATA_ENABLE_DIF 0x000008
1136#define AGSA_SATA_SKIP_QWORD 0xFFFF00
1137
1138/* SAS Initiator Request flag definitions */
1139/* Bits 0,1 use TLR_MASK */
1140
1141#define AGSA_SAS_ENABLE_ENCRYPTION 0x0004
1142#define AGSA_SAS_ENABLE_DIF 0x0008
1143
1144#ifdef SAFLAG_USE_DIF_ENC_IOMB
1145#define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010
1146#endif /* SAFLAG_USE_DIF_ENC_IOMB */
1147
1148#define AGSA_SAS_ENABLE_SKIP_MASK 0x0010
1149#define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0
1150
1151/****************************************************************************
1152** SMP Phy control Phy Operation field
1153****************************************************************************/
1154#define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1
1155#define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2
1156#define AGSA_PHY_CONTROL_DISABLE 0x3
1157#define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5
1158#define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6
1159#define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7
1160
1161/****************************************************************************
1162** SAS Diagnostic Operation code
1163****************************************************************************/
1164#define AGSA_SAS_DIAG_START 0x1
1165#define AGSA_SAS_DIAG_END 0x0
1166
1167/****************************************************************************
1168** Port Control constants
1169****************************************************************************/
1170#define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1
1171#define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2
1172#define AGSA_PORT_IO_ABORT 0x3
1173#define AGSA_PORT_SET_PORT_RESET_TIME 0x4
1174#define AGSA_PORT_HARD_RESET 0x5
1175#define AGSA_PORT_CLEAN_UP 0x6
1176#define AGSA_STOP_PORT_RECOVERY_TIMER 0x7
1177
1178/* Device State */
1179#define SA_DS_OPERATIONAL 0x1
1180#define SA_DS_PORT_IN_RESET 0x2
1181#define SA_DS_IN_RECOVERY 0x3
1182#define SA_DS_IN_ERROR 0x4
1183#define SA_DS_NON_OPERATIONAL 0x7
1184
1185/************************************************************************************
1186 * *
1187 * Constants defined for LL Layer ends *
1188 * *
1189 ************************************************************************************/
1190
1191/************************************************************************************
1192 * *
1193 * Constants defined for OS Layer starts *
1194 * *
1195 ************************************************************************************/
1196/*****************************************
1197 * ossaXXX return values
1198 ******************************************/
1199/* common for all ossaXXX CB */
1200#define OSSA_SUCCESS 0x00
1201#define OSSA_FAILURE 0x01
1203/* ossaHwCB() */
1204#define OSSA_RESET_PENDING 0x03
1205#define OSSA_CHIP_FAILED 0x04
1206#define OSSA_FREEZE_FAILED 0x05
1208/* ossaLocalPhyControl() */
1209#define OSSA_PHY_CONTROL_FAILURE 0x03
1211/* ossaDeviceRegisterCB() */
1212#define OSSA_FAILURE_OUT_OF_RESOURCE 0x01
1213#define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1214#define OSSA_FAILURE_INVALID_PHY_ID 0x03
1215#define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1216#define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1217#define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06
1218#define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1219#define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020
1220#define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021
1221#define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022
1222
1223#define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027
1224
1225#define OSSA_ERR_PORT_INVALID 0x1041
1226#define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042
1227
1228#define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
1229
1230#define OSSA_ERR_PHY_ID_INVALID 0x1061
1231#define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062
1232
1233
1234
1235/* ossaDeregisterDeviceCB() */
1236#define OSSA_INVALID_HANDLE 0x02
1237#define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The device handle associated with DEVICE_ID does not exist. */
1238#define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outstanding I/Os. */
1239
1240
1241#define OSSA_RC_ACCEPT 0x00
1242#define OSSA_RC_REJECT 0x01
1244/* ossaSetDeviceStateCB() */
1245#define OSSA_INVALID_STATE 0x0001
1246#define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025
1247#define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026
1248#define OSSA_ERR_DEVICE_STATE_INVALID 0x0049
1249
1250/* status of ossaSASDiagExecuteCB() */
1251#define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */
1252#define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */
1253#define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. This is applicable only to the SPCv controller. */
1254#define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is applicable only to the SPC controller. */
1255#define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic command but PHY is not in diagnostic mode */
1256#define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */
1257#define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic. This is applicable only to the SPCv controller. */
1258
1259
1260/* status of ossaSASDiagStartEndCB() */
1261#define OSSA_DIAG_SE_SUCCESS 0x00
1262#define OSSA_DIAG_SE_INVALID_PHY_ID 0x01
1263#define OSSA_DIAG_PHY_NOT_DISABLED 0x02
1264#define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */
1265#define OSSA_DIAG_OPCODE_INVALID 0x03
1266
1267/* status of ossaPortControlCB() */
1268#define OSSA_PORT_CONTROL_FAILURE 0x03
1269
1270#define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004
1271#define OSSA_MPI_ERR_PORT_INVALID 0x1041
1272#define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043
1273#define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044
1274#define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045
1275#define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047
1276
1277/*regDumpNum of agsaRegDumpInfo_t */
1278#define GET_GSM_SM_INFO 0x02
1279#define GET_IOST_RB_INFO 0x03
1280
1281/************************************************************************************
1282 * HW Events
1283 ************************************************************************************/
1284#define OSSA_HW_EVENT_RESET_START 0x01
1285#define OSSA_HW_EVENT_RESET_COMPLETE 0x02
1286#define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03
1287#define OSSA_HW_EVENT_SAS_PHY_UP 0x04
1288#define OSSA_HW_EVENT_SATA_PHY_UP 0x05
1289#define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06
1290#define OSSA_HW_EVENT_PHY_DOWN 0x07
1292#define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09
1293/* not used spcv 0x0A*/
1294#define OSSA_HW_EVENT_PHY_ERROR 0x0A
1295#define OSSA_HW_EVENT_BROADCAST_SES 0x0B
1296#define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C
1297#define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D
1298/* not used spcv 0x0E*/
1299#define OSSA_HW_EVENT_MALFUNCTION 0x0E
1300#define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1301#define OSSA_HW_EVENT_BROADCAST_EXP 0x10
1302/* not used spcv 0x11*/
1303#define OSSA_HW_EVENT_PHY_START_STATUS 0x11
1304#define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12
1305#define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13
1306#define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14
1307#define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15
1308#define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16
1309#define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1310#define OSSA_HW_EVENT_PORT_RECOVER 0x18
1311#define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1312#define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20
1313#define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21
1314#define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22
1316#define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25
1317
1318#define OSSA_HW_EVENT_ENCRYPTION 0x83
1319#define OSSA_HW_EVENT_MODE 0x84
1320#define OSSA_HW_EVENT_SECURITY_MODE 0x85
1323/* port state */
1324#define OSSA_PORT_NOT_ESTABLISHED 0x00
1325#define OSSA_PORT_VALID 0x01
1326#define OSSA_PORT_LOSTCOMM 0x02
1327#define OSSA_PORT_IN_RESET 0x04
1328#define OSSA_PORT_3RDPARTY_RESET 0x07
1329#define OSSA_PORT_INVALID 0x08
1331/* status for agsaHWEventMode_t */
1332#define OSSA_CTL_SUCCESS 0x0000
1333#define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001
1334#define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002
1335#define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1336#define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004
1337#define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005
1338// #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B
1339#define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX
1340
1341
1342
1343/************************************************************************************
1344 * General Events value
1345 ************************************************************************************/
1346#define OSSA_INBOUND_V_BIT_NOT_SET 0x01
1347#define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02
1348#define OSSA_INBOUND_IOMB_INVALID_OBID 0x03
1349
1350/************************************************************************************
1351 * FW Flash Update status values
1352 ************************************************************************************/
1353#define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
1354#define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01
1355#define OSSA_FLASH_UPDATE_HDR_ERR 0x02
1356#define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03
1357#define OSSA_FLASH_UPDATE_CRC_ERR 0x04
1358#define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05
1359#define OSSA_FLASH_UPDATE_HW_ERR 0x06
1360#define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E
1362#define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
1363#define OSSA_FLASH_UPDATE_DISABLED 0x11
1364#define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12
1366/************************************************************************************
1367* Discovery status values
1368************************************************************************************/
1369#define OSSA_DISCOVER_STARTED 0x00
1370#define OSSA_DISCOVER_FOUND_DEVICE 0x01
1371#define OSSA_DISCOVER_REMOVED_DEVICE 0x02
1372#define OSSA_DISCOVER_COMPLETE 0x03
1373#define OSSA_DISCOVER_ABORT 0x04
1374#define OSSA_DISCOVER_ABORT_ERROR_1 0x05
1375#define OSSA_DISCOVER_ABORT_ERROR_2 0x06
1376#define OSSA_DISCOVER_ABORT_ERROR_3 0x07
1377#define OSSA_DISCOVER_ABORT_ERROR_4 0x08
1378#define OSSA_DISCOVER_ABORT_ERROR_5 0x09
1379#define OSSA_DISCOVER_ABORT_ERROR_6 0x0A
1380#define OSSA_DISCOVER_ABORT_ERROR_7 0x0B
1381#define OSSA_DISCOVER_ABORT_ERROR_8 0x0C
1382#define OSSA_DISCOVER_ABORT_ERROR_9 0x0D
1384/***********************************************************************************
1385 * Log Debug Levels
1386 ***********************************************************************************/
1387#define OSSA_DEBUG_LEVEL_0 0x00
1388#define OSSA_DEBUG_LEVEL_1 0x01
1389#define OSSA_DEBUG_LEVEL_2 0x02
1390#define OSSA_DEBUG_LEVEL_3 0x03
1391#define OSSA_DEBUG_LEVEL_4 0x04
1393#define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF
1395#define OSSA_FRAME_TYPE_SSP_CMD 0x06
1396#define OSSA_FRAME_TYPE_SSP_TASK 0x16
1398/* Event Source Type of saRegisterEventCallback() */
1399#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00
1400#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01
1401
1402/* Status of Get Device Info CB */
1403#define OSSA_DEV_INFO_INVALID_HANDLE 0x01
1404#define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02
1405#define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03
1406#define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04
1407
1408/* Diagnostic Command Type */
1409#define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00
1410#define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01
1411#define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02
1412#define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03
1413#define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04
1414#define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05
1415
1416/* Command Description for CMD_TYPE DIAG_OPRN_PERFORM, DIAG_OPRN_STOP, THRESHOLD_SPECIFY */
1417#define AGSA_CMD_DESC_PRBS 0x00
1418#define AGSA_CMD_DESC_CJTPAT 0x01
1419#define AGSA_CMD_DESC_USR_PATTERNS 0x02
1420#define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08
1421#define AGSA_CMD_DESC_PRBS_INVERT 0x09
1422#define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A
1423#define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B
1424#define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C
1425#define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E
1426#define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10
1427#define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11
1428#define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12
1429
1430/* Command Description for CMD_TYPE DIAG_REPORT_GET and ERR_CNT_RESET */
1431#define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00
1432#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01
1433#define AGSA_CMD_DESC_DISP_ERR_CNT 0x02
1434#define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05
1435#define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06
1436#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09
1437#define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A
1438#define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B
1439#define AGSA_CMD_DESC_PHY_RST_CNT 0x0C
1440#define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E
1441
1442#define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19
1443#define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A
1444#define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B
1445#define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C
1446#define AGSA_CMD_DESC_ALL 0x1F
1447
1448/* NVMDevice type */
1449#define AGSA_NVMD_TWI_DEVICES 0x00
1450#define AGSA_NVMD_CONFIG_SEEPROM 0x01
1451#define AGSA_NVMD_VPD_FLASH 0x04
1452#define AGSA_NVMD_AAP1_REG_FLASH 0x05
1453#define AGSA_NVMD_IOP_REG_FLASH 0x06
1454#define AGSA_NVMD_EXPANSION_ROM 0x07
1455#define AGSA_NVMD_REG_FLASH 0x05
1456
1457
1458/* GET/SET NVMD Data Response errors */
1459#define OSSA_NVMD_SUCCESS 0x0000
1460#define OSSA_NVMD_MODE_ERROR 0x0001
1461#define OSSA_NVMD_LENGTH_ERROR 0x0002
1462#define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005
1463#define OSSA_NVMD_TWI_NACK_ERROR 0x2001
1464#define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002
1465#define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021
1466#define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081
1467#define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082
1468#define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF
1469#define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001
1470#define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002
1471#define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003
1472#define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004
1473#define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005
1474#define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006
1475#define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007
1476#define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008
1477#define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009
1478#define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A
1479#define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B
1480#define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C
1481#define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D
1482#define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E
1483
1484/************************************************************
1485* ossaHwCB Encryption encryptOperation of agsaHWEventEncrypt_t
1486************************************************************/
1487#define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000
1488#define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001
1489#define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002
1490#define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003
1491#define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004
1492#define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005
1493#define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006
1494#define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007
1495#define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008
1496
1497
1498/************************************************************
1499* ossaHwCB Encryption status of agsaHWEventEncrypt_t
1500************************************************************/
1501/* KEK and DEK managment status from PM */
1502#define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1503#define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/
1504#define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000
1505#define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001
1506#define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002
1507#define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021
1508#define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022
1509#define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023
1510
1511/*encrypt operator management response status */
1512#define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1513#define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1514#define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1515#define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1516#define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1517
1518/*encrypt saSetOperator() response status */
1519#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005
1520#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B
1521
1522/* agsaEncryptSMX | agsaEncryptCipherMode == cipherMode for saEncryptSetMode()*/
1523/* Make sure all definitions are unique bits */
1524#define agsaEncryptSMF 0x00000000
1525#define agsaEncryptSMA 0x00000100
1526#define agsaEncryptSMB 0x00000200
1527#define agsaEncryptReturnSMF (1 << 12)
1528#define agsaEncryptAuthorize (1 << 13)
1529
1530/*
1531Bits 16-23: Allowable Cipher Mode(ACM)
1532Bit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled.
1533Bit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled.
1534*/
1535#define agsaEncryptAcmMask 0x00ff0000
1536#define agsaEncryptEnableAES_ECB (1 << 16)
1537#define agsaEncryptEnableAES_XTS (1 << 22)
1538
1539
1540
1541#define agsaEncryptCipherModeECB 0x00000001
1542#define agsaEncryptCipherModeXTS 0x00000002
1543
1544
1545
1546#define agsaEncryptStatusNoNVRAM 0x00000001
1547#define agsaEncryptStatusNVRAMErr 0x00000002
1548
1549/*
1550
1551Bin Hex Sector Total
155200000 :0x0 512B 512
155311000 :0x1 520B 520
155400010 :0x2 4K 4096
155500011 :0x3 4K+64B 4160
155600100 :0x4 4K+128B 4224
1557
155811000 :0x18 512+8B 520
155911001 :0x19 520+8B 528
156011010 :0x1A 4K+8B 4104
156111011 :0x1B 4K+64B+8B 4168
156211100 :0x1C 4K+128B+8B 4232
1563
1564*/
1565
1566#define agsaEncryptSectorSize512 0
1567/* define agsaEncryptSectorSize520 1 Not supported */
1568#define agsaEncryptSectorSize4096 2
1569#define agsaEncryptSectorSize4160 3
1570#define agsaEncryptSectorSize4224 4
1571
1572#define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18)
1573#define agsaEncryptDIFSectorSize528 ( 0x19)
1574#define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18)
1575#define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18)
1576#define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18)
1577
1578
1579#define AGSA_ENCRYPT_STORE_NVRAM 1
1580
1581/************************************************************
1582* ossaHwCB Mode page event definitions
1583************************************************************/
1584#define agsaModePageGet 1
1585#define agsaModePageSet 2
1586
1587/************************************************************
1588* saSgpio() SGPIO Function and Register type
1589************************************************************/
1590#define AGSA_READ_SGPIO_REGISTER 0x02
1591#define AGSA_WRITE_SGPIO_REGISTER 0x82
1592
1593#define AGSA_SGPIO_CONFIG_REG 0x0
1594#define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1
1595#define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2
1596#define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3
1597#define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4
1598
1599/************************************************************
1600* ossaSGpioCB() Function result
1601************************************************************/
1602#define OSSA_SGPIO_COMMAND_SUCCESS 0x00
1603#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01
1604#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02
1605#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03
1606#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04
1607#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05
1608#define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06
1609#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19
1610#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81
1611#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A
1612#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82
1613#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83
1614#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D
1615#define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D
1616
1617#define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D
1618#define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C
1619
1620/************************************************************
1621* ossaGetDFEDataCB() status
1622************************************************************/
1623#define OSSA_DFE_MPI_IO_SUCCESS 0x0000
1624#define OSSA_DFE_DATA_OVERFLOW 0x0002
1625#define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004
1626#define OSSA_DFE_CHANNEL_DOWN 0x100E
1627#define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F
1628#define OSSA_DFE_CHANNEL_INVALID 0x1010
1629#define OSSA_DFE_DMA_FAILURE 0x1011
1630
1631/************************************************************************************
1632 * *
1633 * Constants defined for OS Layer ends *
1634 * *
1635 ************************************************************************************/
1636
1637/************************************************************************************
1638 * *
1639 * Data Structures Defined for LL API start *
1640 * *
1641 ************************************************************************************/
1657typedef struct agsaContext_s
1658{
1659 void *osData;
1660 void *sdkData;
1661} agsaContext_t;
1662
1673typedef agsaContext_t agsaRoot_t;
1674
1683typedef agsaContext_t agsaDevHandle_t;
1684
1700typedef agsaContext_t agsaPortContext_t;
1701
1713typedef agsaContext_t agsaIORequest_t;
1714
1719typedef void *agsaFrameHandle_t;
1720
1726typedef struct agsaSASReconfig_s {
1727 bit32 flags; /* flag to indicate a change to the default parameter
1728 bit31-30:reserved
1729 bit29: a change to the default SAS/SATA ports is requested
1730 bit28: the OPEN REJECT (RETRY) in command phase is requested
1731 bit27: the OPEN REJECT (RETRY) in data phase is requested
1732 bit26: REJECT will be mapped into OPEN REJECT
1733 bit25: delay for SATA Head-of-Line blocking detection timeout
1734 bit24-00:reserved */
1735 bit16 reserved0; /* reserved */
1736 bit8 reserved1; /* reserved */
1737 bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */
1738 bit16 openRejectRetriesCmd; /* This field is valid if bit 28 of the flags field is set to 1 */
1739 bit16 openRejectRetriesData; /* This field is valid if bit 27 of the flags field is set to 1.*/
1740 bit16 reserved2; /* reserved */
1741 bit16 sataHolTmo; /* This field is valid if bit 25 of the flags field is set to 1 */
1742} agsaSASReconfig_t;
1743
1749typedef struct agsaPhyAnalogSetupRegisters_s
1750{
1751 bit32 spaRegister0;
1752 bit32 spaRegister1;
1753 bit32 spaRegister2;
1754 bit32 spaRegister3;
1755 bit32 spaRegister4;
1756 bit32 spaRegister5;
1757 bit32 spaRegister6;
1758 bit32 spaRegister7;
1759 bit32 spaRegister8;
1760 bit32 spaRegister9;
1761} agsaPhyAnalogSetupRegisters_t;
1762
1763#define MAX_INDEX 10
1764
1768typedef struct agsaPhyAnalogSetupTable_s
1769{
1770 agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX];
1771} agsaPhyAnalogSetupTable_t;
1772
1778typedef struct agsaPhyAnalogSettingsPage_s
1779{
1780 bit32 Dword0;
1781 bit32 Dword1;
1782 bit32 Dword2;
1783 bit32 Dword3;
1784 bit32 Dword4;
1785 bit32 Dword5;
1786 bit32 Dword6;
1787 bit32 Dword7;
1788 bit32 Dword8;
1789 bit32 Dword9;
1790} agsaPhyAnalogSettingsPage_t;
1791
1792
1798typedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s
1799{
1800 bit32 Dword0;
1801 bit32 Dword1;
1802 bit32 Dword2;
1803 bit32 Dword3;
1804} agsaSASPhyOpenRejectRetryBackOffThresholdPage_t;
1805
1819typedef struct agsaPhyRateControlPage_s
1820{
1821 bit32 Dword0;
1822 bit32 Dword1;
1823 bit32 Dword2;
1824} agsaPhyRateControlPage_t;
1825
1845typedef struct agsaRegDumpInfo_s
1846{
1847 bit8 regDumpSrc;
1848 bit8 regDumpNum;
1849 bit8 reserved[2];
1850 bit32 regDumpOffset;
1851 bit32 directLen;
1852 void *directData;
1853 bit32 indirectAddrUpper32;
1854 bit32 indirectAddrLower32;
1855 bit32 indirectLen;
1856} agsaRegDumpInfo_t;
1857
1858/*
18597 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000]
18608 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000]
18619 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000]
186210: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000]
186311: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000]
186412: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000]
186513: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000]
186614: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000]
186715: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000]
186816: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000]
186917: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
187018: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000]
187119: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
187220: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
187321: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000]
187422: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
187523: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000]
187624: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000]
187725: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000]
187826: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000]
1879*/
1880
1881#define TYPE_GSM_SPACE 1
1882#define TYPE_QUEUE 2
1883#define TYPE_FATAL 3
1884#define TYPE_NON_FATAL 4
1885#define TYPE_INBOUND_QUEUE 5
1886#define TYPE_OUTBOUND_QUEUE 6
1887
1888
1889#define BAR_SHIFT_GSM_OFFSET 0x400000
1890
1891#define ONE_MEGABYTE 0x100000
1892#define SIXTYFOURKBYTE (1024 * 64)
1893
1894
1895
1896#define TYPE_INBOUND 1
1897#define TYPE_OUTBOUND 2
1898
1899typedef struct
1900{
1901 bit32 DataType;
1902 union
1903 {
1904 struct
1905 {
1906 bit32 directLen;
1907 bit32 directOffset;
1908 bit32 readLen;
1909 void *directData;
1910 }gsmBuf;
1911
1912 struct
1913 {
1914 bit16 queueType;
1915 bit16 queueIndex;
1916 bit32 directLen;
1917 void *directData;
1918 }queueBuf;
1919
1920 struct
1921 {
1922 bit32 directLen;
1923 bit32 directOffset;
1924 bit32 readLen;
1925 void *directData;
1926 }dataBuf;
1927 } BufferType;
1928} agsaForensicData_t;
1929
1935typedef struct agsaNVMDData_s
1936{
1937 bit32 indirectPayload :1;
1938 bit32 reserved :7;
1939 bit32 TWIDeviceAddress :8;
1940 bit32 TWIBusNumber :4;
1941 bit32 TWIDevicePageSize :4;
1942 bit32 TWIDeviceAddressSize :4;
1943 bit32 NVMDevice :4;
1944 bit32 directLen :8;
1945 bit32 dataOffsetAddress :24;
1946 void *directData;
1947 bit32 indirectAddrUpper32;
1948 bit32 indirectAddrLower32;
1949 bit32 indirectLen;
1950 bit32 signature;
1951} agsaNVMDData_t;
1952
1953
1954/* status of ossaPCIeDiagExecuteCB() is shared with ossaSASDiagExecuteCB() */
1955#define OSSA_PCIE_DIAG_SUCCESS 0x0000
1956#define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001
1957#define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002
1958#define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006
1959#define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007
1960#define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008
1961#define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009
1962#define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A
1963#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000
1964#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1965#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1966#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1967#define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042
1968#define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1969#define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005
1970
1971
1972typedef struct agsaPCIeDiagExecute_s
1973{
1974 bit32 command;
1975 bit32 flags;
1976 bit16 initialIOSeed;
1977 bit16 reserved;
1978 bit32 rdAddrLower;
1979 bit32 rdAddrUpper;
1980 bit32 wrAddrLower;
1981 bit32 wrAddrUpper;
1982 bit32 len;
1983 bit32 pattern;
1984 bit8 udtArray[6];
1985 bit8 udrtArray[6];
1986} agsaPCIeDiagExecute_t;
1987
1988
1997typedef struct agsaPCIeDiagResponse_s {
1998 bit32 ERR_BLKH;
1999 bit32 ERR_BLKL;
2000 bit32 DWord8;
2001 bit32 DWord9;
2002 bit32 DWord10;
2003 bit32 DWord11;
2004 bit32 DIF_ERR;
2005} agsaPCIeDiagResponse_t;
2006
2007
2013typedef struct agsaFatalErrorInfo_s
2014{
2015 bit32 errorInfo0;
2016 bit32 errorInfo1;
2017 bit32 errorInfo2;
2018 bit32 errorInfo3;
2019 bit32 regDumpBusBaseNum0;
2020 bit32 regDumpOffset0;
2021 bit32 regDumpLen0;
2022 bit32 regDumpBusBaseNum1;
2023 bit32 regDumpOffset1;
2024 bit32 regDumpLen1;
2025} agsaFatalErrorInfo_t;
2026
2032typedef struct agsaEventSource_s
2033{
2034 agsaPortContext_t *agPortContext;
2035 bit32 event;
2036 bit32 param;
2037} agsaEventSource_t;
2038
2044typedef struct agsaControllerInfo_s
2045{
2046 bit32 signature; /* coherent controller information */
2047 bit32 fwInterfaceRev; /* host and controller interface version */
2048 bit32 hwRevision; /* controller HW Revision number */
2049 bit32 fwRevision; /* controller FW Revision number */
2050 bit32 ilaRevision; /* controller ILA Revision number */
2051 bit32 maxPendingIO; /* maximum number of outstanding I/Os supported */
2052 bit32 maxDevices; /* Maximum Device Supported by controller */
2053 bit32 maxSgElements; /* maximum number of SG elements supported */
2054 bit32 queueSupport; /* maximum number of IQ and OQ supported
2055 bit31-19 reserved
2056 bit18 interrupt coalescing
2057 bit17 reserved
2058 bit16 high priority IQ supported
2059 bit15-08 maximum number of OQ
2060 bit07-00 maximum number of IQ */
2061 bit8 phyCount; /* number of phy available in the controller */
2062 bit8 controllerSetting;/* Controller setting
2063 bit07-04 reserved
2064 bit03-00 HDA setting */
2065 bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */
2066 bit8 PCIWidth; /* PCI number of lanes */
2067 bit32 sasSpecsSupport; /* the supported SAS spec. */
2068 bit32 sdkInterfaceRev; /* sdk interface reversion */
2069 bit32 sdkRevision; /* sdk reversion */
2070} agsaControllerInfo_t;
2071
2077typedef struct agsaControllerStatus_s
2078{
2079 agsaFatalErrorInfo_t fatalErrorInfo; /* fatal error information */
2080 bit32 interfaceState; /* host and controller interface state
2081 bit02-00 state of host and controller
2082 bit16-03 reserved
2083 bit31-16 detail of error based on error state */
2084 bit32 iqFreezeState0; /* freeze state of 1st set of IQ */
2085 bit32 iqFreezeState1; /* freeze state of 2nd set of IQ */
2086 bit32 tickCount0; /* tick count in second for internal CPU-0 */
2087 bit32 tickCount1; /* tick count in second for internal CPU-1 */
2088 bit32 tickCount2; /* tick count in second for internal CPU-2 */
2089 bit32 phyStatus[8]; /* status of phy 0 to phy 15 */
2090 bit32 recoverableErrorInfo[8]; /* controller specific recoverable error information */
2091 bit32 bootStatus;
2092 bit16 bootComponentState[8];
2093
2094} agsaControllerStatus_t;
2095
2101typedef struct agsaGpioEventSetupInfo_s
2102{
2103 bit32 gpioPinMask;
2104 bit32 gpioEventLevel;
2105 bit32 gpioEventRisingEdge;
2106 bit32 gpioEventFallingEdge;
2107} agsaGpioEventSetupInfo_t;
2108
2114typedef struct agsaGpioPinSetupInfo_t
2115{
2116 bit32 gpioPinMask;
2117 bit32 gpioInputEnabled;
2118 bit32 gpioTypePart1;
2119 bit32 gpioTypePart2;
2120} agsaGpioPinSetupInfo_t;
2121
2127typedef struct agsaGpioWriteSetupInfo_s
2128{
2129 bit32 gpioWritemask;
2130 bit32 gpioWriteVal;
2131}agsaGpioWriteSetupInfo_t;
2132
2138typedef struct agsaGpioReadInfo_s
2139{
2140 bit32 gpioReadValue;
2141 bit32 gpioInputEnabled; /* GPIOIE */
2142 bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */
2143 bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */
2144 bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */
2145 bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */
2146 bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */
2147 bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */
2148}agsaGpioReadInfo_t;
2149
2155typedef struct agsaSGpioReqResponse_s
2156{
2157 bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/
2158 bit8 function; /* 0x02 for read, 0x82 for write */
2159 bit8 registerType; /* used only in request */
2160 bit8 registerIndex; /* used only in request */
2161 bit8 registerCount; /* used only in request */
2162 bit8 functionResult; /* used only in response */
2163 bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; /* write data for request; read data for response */
2164} agsaSGpioReqResponse_t;
2165
2166
2172typedef struct agsaSGpioCfg0
2173{
2174 bit8 reserved1;
2175 bit8 version:4;
2176 bit8 reserved2:4;
2177 bit8 gpRegisterCount:4;
2178 bit8 cfgRegisterCount:3;
2179 bit8 gpioEnable:1;
2180 bit8 supportedDriveCount;
2181} agsaSGpioCfg0_t;
2182
2188typedef struct agsaSGpioCfg1{
2189 bit8 reserved;
2190 bit8 blinkGenA:4;
2191 bit8 blinkGenB:4;
2192 bit8 maxActOn:4;
2193 bit8 forceActOff:4;
2194 bit8 stretchActOn:4;
2195 bit8 stretchActOff:4;
2196} agsaSGpioCfg1_t;
2197
2203typedef struct agsaPhyConfig_s
2204{
2205 bit32 phyProperties;
2214} agsaPhyConfig_t;
2215
2216
2234typedef struct agsaPhySNW3Page_s
2235{
2236 bit32 LSNW3;
2237 bit32 RSNW3;
2238} agsaPhySNW3Page_t;
2239
2246typedef struct agsaPhyErrCounters_s
2247{
2248 bit32 invalidDword; /* Number of invalid dwords that have been
2249 received outside of phy reset sequences.*/
2250 bit32 runningDisparityError; /* Number of dwords containing running disparity
2251 errors that have been received outside of phy
2252 reset sequences.*/
2253 bit32 lossOfDwordSynch; /* Number of times the phy has restarted the link
2254 reset sequence because it lost dword synchronization.*/
2255 bit32 phyResetProblem; /* Number of times the phy did not obtain dword
2256 synchronization during the final SAS speed
2257 negotiation window.*/
2258 bit32 elasticityBufferOverflow; /* Number of times the phys receive elasticity
2259 buffer has overflowed.*/
2260 bit32 receivedErrorPrimitive; /* Number of times the phy received an ERROR primitive */
2261 bit32 inboundCRCError; /* Number of inbound CRC Error */
2262 bit32 codeViolation; /* Number of code violation */
2263} agsaPhyErrCounters_t;
2264
2265
2269typedef struct agsaPhyErrCountersPage_s
2270{
2271 bit32 invalidDword;
2272 bit32 runningDisparityError;
2273 bit32 codeViolation;
2274 bit32 lossOfDwordSynch;
2275 bit32 phyResetProblem;
2276 bit32 inboundCRCError;
2277} agsaPhyErrCountersPage_t;
2278
2286typedef struct agsaPhyBWCountersPage_s
2287{
2288 bit32 TXBWCounter;
2289 bit32 RXBWCounter;
2290} agsaPhyBWCountersPage_t;
2291
2292
2293
2300typedef struct agsaHwConfig_s
2301{
2302 bit32 phyCount;
2304 bit32 hwInterruptCoalescingTimer;
2305 bit32 hwInterruptCoalescingControl;
2306 bit32 intReassertionOption;
2307 bit32 hwOption;
2309 agsaPhyAnalogSetupTable_t phyAnalogConfig;
2310} agsaHwConfig_t;
2311
2318typedef struct agsaSwConfig_s
2319{
2320 bit32 maxActiveIOs;
2321 bit32 numDevHandles;
2323 bit32 smpReqTimeout;
2324 bit32 numberOfEventRegClients;
2326 bit32 sizefEventLog1;
2327 bit32 sizefEventLog2;
2328 bit32 eventLog1Option;
2329 bit32 eventLog2Option;
2331 bit32 fatalErrorInterruptEnable:1;
2332 bit32 sgpioSupportEnable:1;
2333 bit32 fatalErrorInterruptVector:8;
2334 bit32 max_MSI_InterruptVectors:8;
2335 bit32 max_MSIX_InterruptVectors:8;
2336 bit32 legacyInt_X:1;
2337 bit32 hostDirectAccessSupport:1;
2338 bit32 hostDirectAccessMode:2;
2339 bit32 enableDIF:1;
2340 bit32 enableEncryption:1;
2341#ifdef SA_CONFIG_MDFD_REGISTRY
2342 bit32 disableMDF; /*disable MDF*/
2343#endif
2344 bit32 param1;
2345 bit32 param2;
2346 void *param3;
2347 void *param4;
2348 bit32 stallUsec;
2349 bit32 FWConfig;
2350 bit32 PortRecoveryResetTimer;
2351 void *mpiContextTable;
2357 bit32 mpiContextTablelen;
2359#if defined(SALLSDK_DEBUG)
2360 bit32 sallDebugLevel;
2361#endif
2362
2363#ifdef SA_ENABLE_PCI_TRIGGER
2364 bit32 PCI_trigger;
2365#endif /* SA_ENABLE_PCI_TRIGGER */
2366
2367#ifdef SA_ENABLE_TRACE_FUNCTIONS
2368 bit32 TraceDestination;
2369 bit32 TraceBufferSize;
2370 bit32 TraceMask;
2371#endif /* SA_ENABLE_TRACE_FUNCTIONS */
2372} agsaSwConfig_t;
2373
2374
2375typedef struct agsaQueueInbound_s
2376{
2377 bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth).
2378 A value of zero indicates that the host disabled this queue.*/
2379 bit32 elementSize:16; /* Size of each element in the queue in bytes.*/
2380 bit32 priority:2; /* Queue priority:
2381 00: normal priority
2382 01: high priority
2383 10: reserved
2384 11: reserved */
2385 bit32 reserved:30;
2386} agsaQueueInbound_t;
2387
2388typedef struct agsaQueueOutbound_s
2389{
2390 bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth).
2391 A value of zero indicates that the host disabled
2392 this queue.*/
2393 bit32 elementSize:16; /* Size of each element in the queue in bytes.*/
2394 bit32 interruptDelay:16; /* Time, in usec, to delay interrupts to the host.
2395 Zero means not to delay based on time. An
2396 interrupt is passed to the host when either of
2397 the interruptDelay or interruptCount parameters
2398 is satisfied. Default value is 0.*/
2399 bit32 interruptCount:16; /* Number of interrupts required before passing to
2400 the host. Zero means not to coalesce based on count. */
2401 bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when
2402 Multiple Messages is enabled, this field is the
2403 index to the MSI vectors derived from a single
2404 Message Address and multiple Message Data.
2405 For MSI-X, this field is the index to the
2406 MSI-X Table Structure. */
2407 bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling)
2408 1b: Interrupt enabled */
2409 bit32 reserved:23;
2410
2411} agsaQueueOutbound_t;
2412
2413typedef struct agsaPhyCalibrationTbl_s
2414{
2415 bit32 txPortConfig1; /* transmitter per port configuration 1 SAS_SATA G1 */
2416 bit32 txPortConfig2; /* transmitter per port configuration 2 SAS_SATA G1*/
2417 bit32 txPortConfig3; /* transmitter per port configuration 3 SAS_SATA G1*/
2418 bit32 txConfig1; /* transmitter configuration 1 */
2419 bit32 rvPortConfig1; /* reveiver per port configuration 1 SAS_SATA G1G2 */
2420 bit32 rvPortConfig2; /* reveiver per port configuration 2 SAS_SATA G3 */
2421 bit32 rvConfig1; /* reveiver per configuration 1 */
2422 bit32 rvConfig2; /* reveiver per configuration 2 */
2423 bit32 reserved[2]; /* reserved */
2424} agsaPhyCalibrationTbl_t;
2425
2426typedef struct agsaQueueConfig_s
2427{
2428 bit16 numInboundQueues;
2429 bit16 numOutboundQueues;
2430 bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS];
2431 bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS];
2432 bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS];
2433 bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS];
2434 bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS];
2435 bit8 iqNormalPriorityProcessingDepth;
2436 bit8 iqHighPriorityProcessingDepth;
2437 bit8 generalEventQueue;
2438 bit8 tgtDeviceRemovedEventQueue;
2439 bit32 queueOption;
2440 agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q];
2441 agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q];
2442} agsaQueueConfig_t;
2443
2444#define OQ_SHARE_PATH_BIT 0x00000001
2445
2446typedef struct agsaFwImg_s
2447{
2448 bit8 *aap1Img;
2449 bit32 aap1Len;
2450 bit8 *ilaImg;
2451 bit32 ilaLen;
2452 bit8 *iopImg;
2453 bit32 iopLen;
2454 bit8 *istrImg;
2455 bit32 istrLen;
2456} agsaFwImg_t;
2457
2463typedef struct agsaMem_s
2464{
2465 void *virtPtr;
2466 void *osHandle;
2467 bit32 phyAddrUpper;
2468 bit32 phyAddrLower;
2469 bit32 totalLength;
2470 bit32 numElements;
2471 bit32 singleElementLength;
2472 bit32 alignment;
2474 bit32 type;
2475 bit32 reserved;
2476} agsaMem_t;
2477
2483typedef struct agsaControllerEventLog_s
2484{
2485 agsaMem_t eventLog1;
2486 agsaMem_t eventLog2;
2487 bit32 eventLog1Option;
2488 bit32 eventLog2Option;
2489} agsaControllerEventLog_t;
2490
2491/* Log Option - bit3-0 */
2492#define DISABLE_LOGGING 0x0
2493#define CRITICAL_ERROR 0x1
2494#define WARNING 0x2
2495#define NOTICE 0x3
2496#define INFORMATION 0x4
2497#define DEBUGGING 0x5
2498
2504typedef struct agsaSASDiagExecute_s
2505{
2506 bit32 command;
2507 bit32 param0;
2508 bit32 param1;
2509 bit32 param2;
2510 bit32 param3;
2511 bit32 param4;
2512 bit32 param5;
2513} agsaSASDiagExecute_t;
2514
2515
2521typedef struct agsaSASPhyGeneralStatusPage_s
2522{
2523 bit32 Dword0;
2524 bit32 Dword1;
2525} agsaSASPhyGeneralStatusPage_t;
2526
2527
2533typedef struct agsaMemoryRequirement_s
2534{
2535 bit32 count;
2537 agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS];
2539} agsaMemoryRequirement_t;
2540
2541
2547typedef struct agsaSASAddressID_s
2548{
2549 bit8 sasAddressLo[4];
2550 bit8 sasAddressHi[4];
2551 bit8 phyIdentifier;
2552} agsaSASAddressID_t;
2553
2560typedef struct agsaDeviceInfo_s
2561{
2562 bit16 smpTimeout;
2563 bit16 it_NexusTimeout;
2564 bit16 firstBurstSize;
2565 bit8 reserved;
2566 /* Not Used */
2567 bit8 devType_S_Rate;
2568 /* Bit 6-7: reserved
2569 Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device
2570 00: STP device
2571 01: SSP or SMP device
2572 10: Direct SATA device
2573 Bit 0-3: Connection Rate field when opening the device.
2574 Code Description:
2575 08h: 1.5 Gbps
2576 09h: 3.0 Gbps
2577 0ah: 6.0 Gbps
2578 All others Reserved
2579 */
2580 bit8 sasAddressHi[4];
2581 bit8 sasAddressLo[4];
2582 bit32 flag;
2583/*
2584flag
2585Bit 0: Retry flag.
2586 1b: enable SAS TLR (Transport Layer Retry).
2587 0b: disable SAS TLR (Transport Layer Retry).
2588 When used during device registration, it is recommended that TLR is
2589 enabled, i.e. set the bit to 1.
2590Bit 1: Priority setting for AWT (Arbitration Wait Time) for this device.
2591 0b: Default setting (recommended). Actual AWT value TBD.
2592 1b: Increase priority. Actual AWT value TBD.
2593Bit 2-3: Reserved
2594Bit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set to 10b
2595 which indicates a directly-attached SATA drive.
2596Bit 12-15: Reserved
2597Bit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that
2598 can be established with the device concurrently. This field is set to the lowest port width along the pathway
2599 from the controller to the device. This is applicable only to the SPCv controller.
2600 However, for backward compatibility reasons, if this field is set to zero, it is treated as 1 so that the controller
2601 can establish at least one connection.
2602Bit 20: Initiator Role
2603 This bit indicates whether the device has SSP initiator role capability. This is applicable only to the SPCv controller.
2604 0b : The device has no SSP initiator capability.
2605 1b : The device has SSP initiator capability.
2606Bit 21: ATAPI Device Flag. (Only applies to the SPCv) Flag to indicate ATAPI protocol support
2607 0b : Device does not support ATAPI protocol.
2608 1b : Device supports ATAPI protocol.
2609Bit 22-31: Reserved
2610*/
2611} agsaDeviceInfo_t;
2612
2613
2614#define DEV_INFO_MASK 0xFF
2615#define DEV_INFO_MCN_SHIFT 16
2616#define DEV_INFO_IR_SHIFT 20
2617
2618#define RETRY_DEVICE_FLAG (1 << SHIFT0)
2619#define AWT_DEVICE_FLAG (1 << SHIFT1)
2620#define SSP_DEVICE_FLAG (1 << SHIFT20)
2621#define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */
2622#define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22)
2623
2624
2625#define DEV_LINK_RATE 0x3F
2626
2627#define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \
2628 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo)
2629
2630#define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \
2631 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi)
2632
2633#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \
2634 (((devInfo)->devType_S_Rate & 0xC0) >> 5)
2635
2636#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \
2637 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
2638
2639#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \
2640 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
2641
2648typedef struct agsaSATADeviceInfo_s
2649{
2650 agsaDeviceInfo_t commonDevInfo;
2652 bit8 connection;
2658 bit8 portMultiplierField;
2664 bit8 stpPhyIdentifier;
2667 bit8 reserved;
2668 bit8 signature[8];
2673} agsaSATADeviceInfo_t;
2674
2681typedef struct agsaSASDeviceInfo_s
2682{
2683 agsaDeviceInfo_t commonDevInfo;
2685 bit8 initiator_ssp_stp_smp;
2686 /* b4-7: reserved */
2687 /* b3: SSP initiator port */
2688 /* b2: STP initiator port */
2689 /* b1: SMP initiator port */
2690 /* b0: reserved */
2691 bit8 target_ssp_stp_smp;
2692 /* b4-7: reserved */
2693 /* b3: SSP target port */
2694 /* b2: STP target port */
2695 /* b1: SMP target port */
2696 /* b0: reserved */
2697 bit32 numOfPhys;
2698 bit8 phyIdentifier;
2701} agsaSASDeviceInfo_t;
2702
2703#define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT /* SSP Initiator port */
2704#define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT /* STP Initiator port */
2705#define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT /* SMP Initiator port */
2706#define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT /* SATA device, valid in the discovery response only */
2707
2708#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \
2709 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2710
2711#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \
2712 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2713
2714#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \
2715 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2716
2717#define SA_SASDEV_IS_SSP_TARGET(sasDev) \
2718 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2719
2720#define SA_SASDEV_IS_STP_TARGET(sasDev) \
2721 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2722
2723#define SA_SASDEV_IS_SMP_TARGET(sasDev) \
2724 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2725
2726#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \
2727 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT)
2728
2729
2730
2731
2737typedef struct _SASG_DESCRIPTOR
2738{
2739 bit32 sgLower;
2740 bit32 sgUpper;
2741 bit32 len;
2742} SASG_DESCRIPTOR, * PSASG_DESCRIPTOR;
2743
2754typedef struct agsaSgl_s
2755{
2756 bit32 sgLower;
2757 bit32 sgUpper;
2758 bit32 len;
2759 bit32 extReserved;
2760} agsaSgl_t;
2761
2776typedef struct agsaEsgl_s
2777{
2778 agsaSgl_t descriptor[MAX_ESGL_ENTRIES];
2779} agsaEsgl_t;
2780
2789#define MAX_CDB_LEN 32
2790typedef struct agsaSSPCmdInfoUnitExt_s
2791{
2792 bit8 lun[8];
2793 bit8 reserved1;
2794 bit8 efb_tp_taskAttribute;
2795 bit8 reserved2;
2796 bit8 additionalCdbLen;
2797 bit8 cdb[MAX_CDB_LEN];
2798} agsaSSPCmdInfoUnitExt_t ;
2799
2800#define DIF_UDT_SIZE 6
2801
2802/* difAction in agsaDif_t */
2803#define AGSA_DIF_INSERT 0
2804#define AGSA_DIF_VERIFY_FORWARD 1
2805#define AGSA_DIF_VERIFY_DELETE 2
2806#define AGSA_DIF_VERIFY_REPLACE 3
2807#define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5
2808#define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7
2809
2810#define agsaDIFSectorSize512 0
2811#define agsaDIFSectorSize520 1
2812#define agsaDIFSectorSize4096 2
2813#define agsaDIFSectorSize4160 3
2814
2815
2816
2817typedef struct agsaDif_s
2818{
2819 agBOOLEAN enableDIFPerLA;
2820 bit32 flags;
2821 bit16 initialIOSeed;
2822 bit16 reserved;
2823 bit32 DIFPerLAAddrLo;
2824 bit32 DIFPerLAAddrHi;
2825 bit16 DIFPerLARegion0SecCount;
2826 bit16 Reserved2;
2827 bit8 udtArray[DIF_UDT_SIZE];
2828 bit8 udrtArray[DIF_UDT_SIZE];
2829} agsaDif_t;
2830
2831
2832/* From LL SDK2 */
2833#define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/
2834#define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */
2835#define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */
2836#define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */
2837#define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */
2838#define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */
2839#define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */
2840#define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */
2841#define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/
2842#define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */
2843#define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/
2844#define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */
2845#define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16
2846#define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */
2847#define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */
2848#define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */
2849#define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */
2850#define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */
2851#define DIF_FLAG_BITS_UDTV_SHIFT 20
2852#define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */
2853#define DIF_FLAG_BITS_UDTUPSHIFT 26
2854
2855typedef struct agsaEncryptDek_s
2856{
2857 bit32 dekTable;
2858 bit32 dekIndex;
2859} agsaEncryptDek_t;
2860
2861typedef struct agsaEncrypt_s
2862{
2863 agsaEncryptDek_t dekInfo;
2864 bit32 kekIndex;
2865 agBOOLEAN keyTagCheck;
2866 agBOOLEAN enableEncryptionPerLA; /* new */
2867 bit32 sectorSizeIndex;
2868 bit32 cipherMode;
2869 bit32 keyTag_W0;
2870 bit32 keyTag_W1;
2871 bit32 tweakVal_W0;
2872 bit32 tweakVal_W1;
2873 bit32 tweakVal_W2;
2874 bit32 tweakVal_W3;
2875 bit32 EncryptionPerLAAddrLo; /* new */
2876 bit32 EncryptionPerLAAddrHi; /* new */
2877 bit16 EncryptionPerLRegion0SecCount; /* new */
2878 bit16 reserved;
2879} agsaEncrypt_t;
2880
2891typedef struct agsaSSPInitiatorRequest_s
2892{
2893 agsaSgl_t agSgl;
2896 bit32 dataLength;
2897 bit16 firstBurstSize;
2899 bit16 flag;
2901 agsaSSPCmdInfoUnit_t sspCmdIU;
2903 agsaDif_t dif;
2904 agsaEncrypt_t encrypt;
2905#ifdef SA_TESTBASE_EXTRA
2906 /* Added by TestBase */
2907 bit16 bstIndex;
2908#endif /* SA_TESTBASE_EXTRA */
2909} agsaSSPInitiatorRequest_t;
2910
2921typedef struct agsaSSPInitiatorRequestExt_s
2922{
2923 agsaSgl_t agSgl;
2926 bit32 dataLength;
2927 bit16 firstBurstSize;
2928 bit16 flag;
2929 agsaSSPCmdInfoUnitExt_t sspCmdIUExt;
2930 agsaDif_t dif;
2931 agsaEncrypt_t encrypt;
2932} agsaSSPInitiatorRequestExt_t;
2933
2934
2935typedef struct agsaSSPInitiatorRequestIndirect_s
2936{
2937 agsaSgl_t agSgl;
2940 bit32 dataLength;
2941 bit16 firstBurstSize;
2942 bit16 flag;
2943 bit32 sspInitiatorReqAddrUpper32;
2944 bit32 sspInitiatorReqAddrLower32;
2945 bit32 sspInitiatorReqLen;
2946 agsaDif_t dif;
2947 agsaEncrypt_t encrypt;
2948
2949}agsaSSPInitiatorRequestIndirect_t;
2950
2951
2952
2953
2985typedef struct agsaSSPTargetRequest_s
2986{
2987 agsaSgl_t agSgl;
2989 bit32 dataLength;
2990 bit32 offset;
2992 bit16 agTag;
2993 bit16 sspOption;
2994 agsaDif_t dif;
2995} agsaSSPTargetRequest_t;
2996
2997#define SSP_OPTION_BITS 0x3F
2998#define SSP_OPTION_ODS 0x8000
3000#define SSP_OPTION_OTHR_NO_RETRY 0
3001#define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1
3002#define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2
3003#define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
3004
3005#define SSP_OPTION_DATA_NO_RETRY 0
3006#define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1
3007#define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2
3008#define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
3009
3010#define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4)
3011#define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5)
3012#define SSP_OPTION_ENCRYPT (1 << SHIFT6)
3013#define SSP_OPTION_DIF (1 << SHIFT7)
3014#define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15)
3015
3016
3024typedef struct agsaSSPTargetResponse_s
3025{
3026 bit32 agTag;
3027 void *frameBuf;
3028 bit32 respBufLength;
3029 bit32 respBufUpper;
3033 bit32 respBufLower;
3037 bit32 respOption;
3042} agsaSSPTargetResponse_t;
3043
3044#define RESP_OPTION_BITS 0x3
3045#define RESP_OPTION_ODS 0x8000
3056typedef struct agsaSMPFrame_s
3057{
3058 void *outFrameBuf;
3062 bit32 outFrameAddrUpper32;
3064 bit32 outFrameAddrLower32;
3066 bit32 outFrameLen;
3068 bit32 inFrameAddrUpper32;
3070 bit32 inFrameAddrLower32;
3072 bit32 inFrameLen;
3074 bit32 expectedRespLen;
3075 bit32 flag;
3092} agsaSMPFrame_t;
3093
3094#define smpFrameFlagDirectResponse 0
3095#define smpFrameFlagIndirectResponse 1
3096#define smpFrameFlagDirectPayload 0
3097#define smpFrameFlagIndirectPayload 2
3098
3103typedef union agsaSASRequestBody_u
3104{
3105 agsaSSPInitiatorRequest_t sspInitiatorReq;
3106 agsaSSPInitiatorRequestExt_t sspInitiatorReqExt;
3107 agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect;
3108 agsaSSPTargetRequest_t sspTargetReq;
3109 agsaSSPScsiTaskMgntReq_t sspTaskMgntReq;
3110 agsaSSPTargetResponse_t sspTargetResponse;
3111 agsaSMPFrame_t smpFrame;
3112}agsaSASRequestBody_t;
3113
3114
3115
3116
3128typedef struct agsaSATAInitiatorRequest_s
3129{
3130 agsaSgl_t agSgl;
3134 bit32 dataLength;
3136 bit32 option;
3140 agsaSATAHostFis_t fis;
3141 agsaDif_t dif;
3142 agsaEncrypt_t encrypt;
3143 bit8 scsiCDB[16];
3144#ifdef SA_TESTBASE_EXTRA
3145 /* Added by TestBase */
3146 bit16 bstIndex;
3147#endif /* SA_TESTBASE_EXTRA */
3148} agsaSATAInitiatorRequest_t;
3149
3150
3151/* controller Configuration page */
3152#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
3153#define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05
3154#define AGSA_IO_GENERAL_CONFIG_PAGE 0x06
3155#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20
3156#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21
3157#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22
3158#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23
3159
3160#ifdef HIALEAH_ENCRYPTION
3161typedef struct agsaEncryptGeneralPage_s {
3162 bit32 numberOfKeksPageCode; /* 0x20 */
3163 bit32 KeyCardIdKekIndex;
3164 bit32 KeyCardId3_0;
3165 bit32 KeyCardId7_4;
3166 bit32 KeyCardId11_8;
3167} agsaEncryptGeneralPage_t;
3168#else
3169typedef struct agsaEncryptGeneralPage_s {
3170 bit32 pageCode; /* 0x20 */
3171 bit32 numberOfDeks;
3172} agsaEncryptGeneralPage_t;
3173#endif /* HIALEAH_ENCRYPTION */
3174
3175#define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
3176#define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8
3177
3178/* sTSDK 4.14 */
3179typedef struct agsaEncryptDekConfigPage_s {
3180 bit32 pageCode;
3181 bit32 table0AddrLo;
3182 bit32 table0AddrHi;
3183 bit32 table0Entries;
3184 bit32 table0BFES;
3185 bit32 table1AddrLo;
3186 bit32 table1AddrHi;
3187 bit32 table1Entries;
3188 bit32 table1BFES;
3189} agsaEncryptDekConfigPage_t;
3190
3191#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
3192#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28
3193#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000
3194#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24
3195
3196/*sTSDK 4.18 */
3197/* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */
3198/* NAR, CORCAP and USRCAP are valid only when AUT==1 */
3199typedef struct agsaEncryptControlParamPage_s {
3200 bit32 pageCode; /* 0x22 */
3201 bit32 CORCAP; /* Crypto Officer Role Capabilities */
3202 bit32 USRCAP; /* User Role Capabilities */
3203 bit32 CCS; /* Current Crypto Services */
3204 bit32 NOPR; /* Number of Operators */
3205} agsaEncryptControlParamPage_t;
3206
3207typedef struct agsaEncryptInfo_s {
3208 bit32 encryptionCipherMode;
3209 bit32 encryptionSecurityMode;
3210 bit32 status;
3211 bit32 flag;
3212} agsaEncryptInfo_t;
3213
3214
3215#define OperatorAuthenticationEnable_AUT 1
3216#define ReturnToFactoryMode_ARF 2
3217
3218/*sTSDK 4.19 */
3219typedef struct agsaEncryptSelfTestBitMap_s {
3220 bit32 AES_Test;
3221 bit32 KEY_WRAP_Test;
3222 bit32 HMAC_Test;
3223} agsaEncryptSelfTestBitMap_t;
3224
3225typedef struct agsaEncryptSelfTestStatusBitMap_s{
3226 bit32 AES_Status;
3227 bit32 KEY_WRAP_Status;
3228 bit32 HMAC_Status;
3229} agsaEncryptSelfTestStatusBitMap_t;
3230
3231typedef struct agsaEncryptHMACTestDescriptor_s
3232{
3233 bit32 Dword0;
3234 bit32 MsgAddrLo;
3235 bit32 MsgAddrHi;
3236 bit32 MsgLen;
3237 bit32 DigestAddrLo;
3238 bit32 DigestAddrHi;
3239 bit32 KeyAddrLo;
3240 bit32 KeyAddrHi;
3241 bit32 KeyLen;
3242} agsaEncryptHMACTestDescriptor_t;
3243
3244typedef struct agsaEncryptHMACTestResult_s
3245{
3246 bit32 Dword0;
3247 bit32 Dword[12];
3248} agsaEncryptHMACTestResult_t;
3249
3250typedef struct agsaEncryptSHATestDescriptor_s
3251{
3252 bit32 Dword0;
3253 bit32 MsgAddrLo;
3254 bit32 MsgAddrHi;
3255 bit32 MsgLen;
3256 bit32 DigestAddrLo;
3257 bit32 DigestAddrHi;
3258} agsaEncryptSHATestDescriptor_t;
3259
3260typedef struct agsaEncryptSHATestResult_s
3261{
3262 bit32 Dword0;
3263 bit32 Dword[12];
3264} agsaEncryptSHATestResult_t;
3265
3266/* types of self test */
3267#define AGSA_BIST_TEST 0x1
3268#define AGSA_HMAC_TEST 0x2
3269#define AGSA_SHA_TEST 0x3
3270
3271
3272/*sTSDK 4.13 */
3273typedef struct agsaEncryptDekBlob_s {
3274 bit8 dekBlob[80];
3275} agsaEncryptDekBlob_t;
3276
3277typedef struct agsaEncryptKekBlob_s {
3278 bit8 kekBlob[48];
3279} agsaEncryptKekBlob_t;
3280
3281/*sTSDK 4.45 */
3282typedef struct agsaEncryptHMACConfigPage_s
3283{
3284 bit32 PageCode;
3285 bit32 CustomerTag;
3286 bit32 KeyAddrLo;
3287 bit32 KeyAddrHi;
3288} agsaEncryptHMACConfigPage_t;
3289
3290/*sTSDK 4.38 */
3291#define AGSA_ID_SIZE 31
3292typedef struct agsaID_s {
3293 bit8 ID[AGSA_ID_SIZE];
3294}agsaID_t;
3295
3296
3297#define SA_OPR_MGMNT_FLAG_MASK 0x00003000
3298#define SA_OPR_MGMNT_FLAG_SHIFT 12
3299
3300/* */
3301typedef struct agsaSASPhyMiscPage_s {
3302 bit32 Dword0;
3303 bit32 Dword1;
3304} agsaSASPhyMiscPage_t ;
3305
3306
3307typedef struct agsaHWEventEncrypt_s {
3308 bit32 encryptOperation;
3309 bit32 status;
3310 bit32 eq; /* error qualifier */
3311 bit32 info;
3312 void *handle;
3313 void *param;
3314} agsaHWEventEncrypt_t;
3315
3316/*sTSDK 4.32 */
3317typedef struct agsaHWEventMode_s {
3318 bit32 modePageOperation;
3319 bit32 status;
3320 bit32 modePageLen;
3321 void *modePage;
3322 void *context;
3323} agsaHWEventMode_t;
3324
3325/*sTSDK 4.33 */
3326typedef struct agsaInterruptConfigPage_s {
3327 bit32 pageCode;
3328 bit32 vectorMask0;
3329 bit32 vectorMask1;
3330 bit32 ICTC0;
3331 bit32 ICTC1;
3332 bit32 ICTC2;
3333 bit32 ICTC3;
3334 bit32 ICTC4;
3335 bit32 ICTC5;
3336 bit32 ICTC6;
3337 bit32 ICTC7;
3338} agsaInterruptConfigPage_t;
3339typedef struct agsaIoGeneralPage_s {
3340 bit32 pageCode; /* 0x06 */
3341 bit32 ActiveMask;
3342 bit32 QrntTime;
3343} agsaIoGeneralPage_t;
3344
3345/* \brief data structure defines detail information about Agilent Error
3346* Detection Code (DIF) errors.
3347*
3348* The agsaDifDetails_t data structure defines detail information about
3349* PMC Error Detection Code (DIF) error. Please refer to the latest T10 SBC
3350* and SPC draft/specification for the definition of the Protection
3351* Information.
3352*
3353* This structure is filled by the function saGetDifErrorDetails().
3354*/
3355
3356typedef struct agsaDifDetails_s {
3357 bit32 UpperLBA;
3358 bit32 LowerLBA;
3359 bit8 sasAddressHi[4];
3360 bit8 sasAddressLo[4];
3361 bit32 ExpectedCRCUDT01;
3362 bit32 ExpectedUDT2345;
3363 bit32 ActualCRCUDT01;
3364 bit32 ActualUDT2345;
3365 bit32 DIFErrDevID;
3366 bit32 ErrBoffsetEDataLen;
3367 void * frame;
3368} agsaDifDetails_t;
3369
3373typedef struct agsaSASProtocolTimerConfigurationPage_s{
3374 bit32 pageCode; /* 0 */
3375 bit32 MST_MSI; /* 1 */
3376 bit32 STP_SSP_MCT_TMO; /* 2 */
3377 bit32 STP_FRM_TMO; /* 3 */
3378 bit32 STP_IDLE_TMO; /* 4 */
3379 bit32 OPNRJT_RTRY_INTVL; /* 5 */
3380 bit32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */
3381 bit32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */
3382 bit32 MAX_AIP; /* 8 */
3383} agsaSASProtocolTimerConfigurationPage_t;
3384
3385
3390typedef struct agsaUpdateFwFlash_s
3391{
3392 bit32 currentImageOffset;
3393 bit32 currentImageLen;
3394 bit32 totalImageLen;
3395 agsaSgl_t agSgl;
3396} agsaUpdateFwFlash_t;
3397
3398
3399
3404typedef struct agsaFlashExtExecute_s
3405{
3406 bit32 command;
3407 bit32 partOffset;
3408 bit32 dataLen;
3409 agsaSgl_t *agSgl;
3410} agsaFlashExtExecute_t;
3411
3412
3417typedef struct agsaFlashExtResponse_s
3418{
3419 bit32 epart_size;
3420 bit32 epart_sect_size;
3421} agsaFlashExtResponse_t;
3422
3423
3432typedef struct agsaMPIContext_s
3433{
3434 bit32 MPITableType;
3435 bit32 offset;
3436 bit32 value;
3437} agsaMPIContext_t;
3438
3439#define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1
3440#define AGSA_MPI_GENERAL_STATUS_TABLE 2
3441#define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3
3442#define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4
3443#define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5
3444#define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6
3445#define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7
3446#define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8
3447
3448
3449/************************************************************/
3450/*This flag and datastructure are specific for fw profiling, Now defined as compiler flag*/
3451//#define SPC_ENABLE_PROFILE
3452
3453#ifdef SPC_ENABLE_PROFILE
3454typedef struct agsaFwProfile_s
3455{
3456 bit32 tcid;
3457 bit32 processor;
3458 bit32 cmd;
3459 bit32 len;
3460 bit32 codeStartAdd;
3461 bit32 codeEndAdd;
3462 agsaSgl_t agSgl;
3463} agsaFwProfile_t;
3464#endif
3465/************************************************************/
3469typedef void (*ossaDeviceRegistrationCB_t)(
3470 agsaRoot_t *agRoot,
3471 agsaContext_t *agContext,
3472 bit32 status,
3473 agsaDevHandle_t *agDevHandle,
3474 bit32 deviceID
3475 );
3476
3480typedef void (*ossaDeregisterDeviceHandleCB_t)(
3481 agsaRoot_t *agRoot,
3482 agsaContext_t *agContext,
3483 agsaDevHandle_t *agDevHandle,
3484 bit32 status
3485 );
3486
3490typedef void (*ossaGenericCB_t)(void);
3491
3492
3496typedef void (*ossaGenericAbortCB_t)(
3497 agsaRoot_t *agRoot,
3498 agsaIORequest_t *agIORequest,
3499 bit32 flag,
3500 bit32 status
3501 );
3502
3503
3504typedef void (*ossaLocalPhyControlCB_t)(
3505 agsaRoot_t *agRoot,
3506 agsaContext_t *agContext,
3507 bit32 phyId,
3508 bit32 phyOperation,
3509 bit32 status,
3510 void *parm
3511 );
3512
3513
3517typedef void (*ossaSATACompletedCB_t)(
3518 agsaRoot_t *agRoot,
3519 agsaIORequest_t *agIORequest,
3520 bit32 agIOStatus,
3521 void *agFirstDword,
3522 bit32 agIOInfoLen,
3523 void *agParam
3524 );
3525
3526
3530typedef void (*ossaSMPCompletedCB_t)(
3531 agsaRoot_t *agRoot,
3532 agsaIORequest_t *agIORequest,
3533 bit32 agIOStatus,
3534 bit32 agIOInfoLen,
3535 agsaFrameHandle_t agFrameHandle
3536 );
3537
3538
3542typedef void (*ossaSSPCompletedCB_t)(
3543 agsaRoot_t *agRoot,
3544 agsaIORequest_t *agIORequest,
3545 bit32 agIOStatus,
3546 bit32 agIOInfoLen,
3547 void *agParam,
3548 bit16 sspTag,
3549 bit32 agOtherInfo
3550 );
3551
3555typedef void (*ossaSetDeviceInfoCB_t) (
3556 agsaRoot_t *agRoot,
3557 agsaContext_t *agContext,
3558 agsaDevHandle_t *agDevHandle,
3559 bit32 status,
3560 bit32 option,
3561 bit32 param
3562 );
3563
3564typedef struct agsaOffloadDifDetails_s
3565{
3566 bit32 ExpectedCRCUDT01;
3567 bit32 ExpectedUDT2345;
3568 bit32 ActualCRCUDT01;
3569 bit32 ActualUDT2345;
3570 bit32 DIFErr;
3571 bit32 ErrBoffset;
3572} agsaOffloadDifDetails_t;
3573
3574typedef struct agsaDifEncPayload_s
3575{
3576 agsaSgl_t SrcSgl;
3577 bit32 SrcDL;
3578 agsaSgl_t DstSgl;
3579 bit32 DstDL;
3580 agsaDif_t dif;
3581 agsaEncrypt_t encrypt;
3582} agsaDifEncPayload_t;
3583
3584typedef void (*ossaVhistCaptureCB_t) (
3585 agsaRoot_t *agRoot,
3586 agsaContext_t *agContext,
3587 bit32 status,
3588 bit32 len);
3589
3590typedef void (*ossaDIFEncryptionOffloadStartCB_t) (
3591 agsaRoot_t *agRoot,
3592 agsaContext_t *agContext,
3593 bit32 status,
3594 agsaOffloadDifDetails_t *agsaOffloadDifDetails
3595 );
3596
3597#define SA_RESERVED_REQUEST_COUNT 16
3598
3599#ifdef SA_FW_TIMER_READS_STATUS
3600#define SA_FW_TIMER_READS_STATUS_INTERVAL 20
3601#endif /* SA_FW_TIMER_READS_STATUS */
3602
3603#define SIZE_DW 4
3604#define SIZE_QW 8
3606#define PCIBAR0 0
3607#define PCIBAR1 1
3608#define PCIBAR2 2
3609#define PCIBAR3 3
3610#define PCIBAR4 4
3611#define PCIBAR5 5
3618typedef struct agsaBarOffset_s
3619{
3620 bit32 Generic; /* */
3621 bit32 Bar; /* */
3622 bit32 Offset; /* */
3623 bit32 Length; /* */
3624} agsaBarOffset_t;
3625
3626typedef union agsabit32bit64_U
3627{
3628 bit32 S32[2];
3629 bit64 B64;
3630} agsabit32bit64;
3631
3632/*
3633The agsaIOErrorEventStats_t data structure is used as parameter in ossaGetIOErrorStatsCB(),ossaGetIOEventStatsCB().
3634This data structure contains the number of IO error and event.
3635*/
3636typedef struct agsaIOErrorEventStats_s
3637{
3638 bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS;
3639 bit32 agOSSA_IO_ABORTED;
3640 bit32 agOSSA_IO_OVERFLOW;
3641 bit32 agOSSA_IO_UNDERFLOW;
3642 bit32 agOSSA_IO_FAILED;
3643 bit32 agOSSA_IO_ABORT_RESET;
3644 bit32 agOSSA_IO_NOT_VALID;
3645 bit32 agOSSA_IO_NO_DEVICE;
3646 bit32 agOSSA_IO_ILLEGAL_PARAMETER;
3647 bit32 agOSSA_IO_LINK_FAILURE;
3648 bit32 agOSSA_IO_PROG_ERROR;
3649 bit32 agOSSA_IO_DIF_IN_ERROR;
3650 bit32 agOSSA_IO_DIF_OUT_ERROR;
3651 bit32 agOSSA_IO_ERROR_HW_TIMEOUT;
3652 bit32 agOSSA_IO_XFER_ERROR_BREAK;
3653 bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY;
3654 bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED;
3655 bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION;
3656 bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK;
3657 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS;
3658 bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION;
3659 bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED;
3660 bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY;
3661 bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION;
3662 bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR;
3663 bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED;
3664 bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT;
3665 bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED;
3666 bit32 agOSSA_IO_XFER_ERROR_RX_FRAME;
3667 bit32 agOSSA_IO_XFER_ERROR_DMA;
3668 bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT;
3669 bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT;
3670 bit32 agOSSA_IO_XFER_ERROR_SATA;
3671 bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST;
3672 bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE;
3673 bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE;
3674 bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT;
3675 bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR;
3676 bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE;
3677 bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN;
3678 bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED;
3679 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT;
3680 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK;
3681 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK;
3682 bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH;
3683 bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN;
3684 bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED;
3685 bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE;
3686 bit32 agOSSA_IO_PORT_IN_RESET;
3687 bit32 agOSSA_IO_DS_NON_OPERATIONAL;
3688 bit32 agOSSA_IO_DS_IN_RECOVERY;
3689 bit32 agOSSA_IO_TM_TAG_NOT_FOUND;
3690 bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR;
3691 bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR;
3692 bit32 agOSSA_IO_DS_IN_ERROR;
3693 bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY;
3694 bit32 agOSSA_IO_ABORT_IN_PROGRESS;
3695 bit32 agOSSA_IO_ABORT_DELAYED;
3696 bit32 agOSSA_IO_INVALID_LENGTH;
3697 bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT;
3698 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED;
3699 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO;
3700 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST;
3701 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE;
3702 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED;
3703 bit32 agOSSA_IO_DS_INVALID;
3704 bit32 agOSSA_IO_XFER_READ_COMPL_ERR;
3705 bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR;
3706 bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR;
3707 bit32 agOSSA_MPI_IO_RQE_BUSY_FULL;
3708 bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE;
3709 bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY;
3710 bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS;
3711 bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH;
3712 bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID;
3713 bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH;
3714 bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR;
3715 bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM;
3716 bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH;
3717 bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH;
3718 bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH;
3719 bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH;
3720 bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME;
3721 bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN;
3722 bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS;
3723 bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED;
3724 bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE;
3725 bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR;
3726 bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED;
3727 bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT;
3728 bit32 agOSSA_IO_UNKNOWN_ERROR;
3729} agsaIOErrorEventStats_t;
3730
3731
3732/************************************************************************************
3733 * *
3734 * Data Structures Defined for LL API ends *
3735 * *
3736 ************************************************************************************/
3737#ifdef SALL_API_TEST
3738typedef struct agsaIOCountInfo_s
3739{
3740 bit32 numSSPStarted; // saSSPStart()
3741 bit32 numSSPAborted; // saSSPAbort()
3742 bit32 numSSPAbortedCB; // ossaSSPAbortCB()
3743 bit32 numSSPCompleted; // includes success and aborted IOs
3744 bit32 numSMPStarted; // saSMPStart()
3745 bit32 numSMPAborted; // saSMPAbort()
3746 bit32 numSMPAbortedCB; // ossaSMPAbortCB()
3747 bit32 numSMPCompleted; // includes success and aborted IOs
3748 bit32 numSataStarted; // saSATAStart()
3749 bit32 numSataAborted; // saSATAAbort()
3750 bit32 numSataAbortedCB; // ossaSATAAbortCB()
3751 bit32 numSataCompleted; // includes success and aborted IOs
3752 bit32 numEchoSent; // saEchoCommand()
3753 bit32 numEchoCB; // ossaEchoCB()
3754 bit32 numUNKNWRespIOMB; // unknow Response IOMB received
3755 bit32 numOurIntCount; //InterruptHandler() counter
3756 bit32 numSpuriousInt; //spurious interrupts
3757// bit32 numSpInts[64]; //spuriours interrupts count for each OBQ (PI=CI)
3758// bit32 numSpInts1[64]; //spuriours interrupts count for each OBQ (PI!=CI)
3759} agsaIOCountInfo_t;
3760
3761/* Total IO Counter */
3762#define LL_COUNTERS 17
3763/* Counter Bit Map */
3764#define COUNTER_SSP_START 0x000001
3765#define COUNTER_SSP_ABORT 0x000002
3766#define COUNTER_SSPABORT_CB 0x000004
3767#define COUNTER_SSP_COMPLETEED 0x000008
3768#define COUNTER_SMP_START 0x000010
3769#define COUNTER_SMP_ABORT 0x000020
3770#define COUNTER_SMPABORT_CB 0x000040
3771#define COUNTER_SMP_COMPLETEED 0x000080
3772#define COUNTER_SATA_START 0x000100
3773#define COUNTER_SATA_ABORT 0x000200
3774#define COUNTER_SATAABORT_CB 0x000400
3775#define COUNTER_SATA_COMPLETEED 0x000800
3776#define COUNTER_ECHO_SENT 0x001000
3777#define COUNTER_ECHO_CB 0x002000
3778#define COUNTER_UNKWN_IOMB 0x004000
3779#define COUNTER_OUR_INT 0x008000
3780#define COUNTER_SPUR_INT 0x010000
3781#define ALL_COUNTERS 0xFFFFFF
3782
3783typedef union agsaLLCountInfo_s
3784{
3785 agsaIOCountInfo_t IOCounter;
3786 bit32 arrayIOCounter[LL_COUNTERS];
3787} agsaLLCountInfo_t;
3788
3789#endif /* SALL_API_TEST */
3790
3791#define MAX_IO_DEVICE_ENTRIES 4096
3794#ifdef SA_ENABLE_POISION_TLP
3795#define SA_PTNFE_POISION_TLP 1 /* Enable if one */
3796#else /* SA_ENABLE_POISION_TLP */
3797#define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */
3798#endif /* SA_ENABLE_POISION_TLP */
3799
3800#ifdef SA_DISABLE_MDFD
3801#define SA_MDFD_MULTI_DATA_FETCH 1 /* Disable if one */
3802#else /* SA_DISABLE_MDFD */
3803#define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */
3804#endif /* SA_DISABLE_MDFD */
3805
3806#ifdef SA_ENABLE_ARBTE
3807#define SA_ARBTE 1 /* Enable if one */
3808#else /* SA_ENABLE_ARBTE */
3809#define SA_ARBTE 0 /* Disable if zero default setting */
3810#endif /* SA_ENABLE_ARBTE */
3811
3812#ifdef SA_DISABLE_OB_COAL
3813#define SA_OUTBOUND_COALESCE 0 /* Disable if zero */
3814#else /* SA_DISABLE_OB_COAL */
3815#define SA_OUTBOUND_COALESCE 1 /* Enable if one default setting */
3816#endif /* SA_DISABLE_OB_COAL */
3817
3818
3819/***********************************************************************************
3820 * *
3821 * The OS Layer Functions Declarations start *
3822 * *
3823 ***********************************************************************************/
3824#include "saosapi.h"
3825/***********************************************************************************
3826 * *
3827 * The OS Layer Functions Declarations end *
3828 * *
3829 ***********************************************************************************/
3830
3831/***********************************************************************************
3832 * *
3833 * The LL Layer Functions Declarations start *
3834 * *
3835 ***********************************************************************************/
3836
3837#ifdef FAST_IO_TEST
3838/* needs to be allocated by the xPrepare() caller, one struct per IO */
3839typedef struct agsaFastCBBuf_s
3840{
3841 void *cb;
3842 void *cbArg;
3843 void *pSenseData;
3844 bit8 *senseLen;
3845 /* internal */
3846 void *oneDeviceData; /* tdsaDeviceData_t */
3847} agsaFastCBBuf_t;
3848
3849typedef struct agsaFastCommand_s
3850{
3851 /* in */
3852 void *agRoot;
3853 /* modified by TD tiFastPrepare() */
3854 void *devHandle; /* agsaDevHandle_t* */
3855 void *agSgl; /* agsaSgl_t* */
3856 bit32 dataLength;
3857 bit32 extDataLength;
3858 bit8 additionalCdbLen;
3859 bit8 *cdb;
3860 bit8 *lun;
3861 /* modified by TD tiFastPrepare() */
3862 bit8 taskAttribute; /* TD_xxx */
3863 bit16 flag; /* TLR_MASK */
3864 bit32 agRequestType;
3865 bit32 queueNum;
3866 agsaFastCBBuf_t *safb;
3867} agsaFastCommand_t;
3868#endif
3869
3870
3871
3872/* Enable test by setting bits in gFPGA_TEST */
3873
3874#define EnableFPGA_TEST_ICCcontrol 0x01
3875#define EnableFPGA_TEST_ReadDEV 0x02
3876#define EnableFPGA_TEST_WriteCALAll 0x04
3877#define EnableFPGA_TEST_ReconfigSASParams 0x08
3878#define EnableFPGA_TEST_LocalPhyControl 0x10
3879#define EnableFPGA_TEST_PortControl 0x20
3880
3881
3882/*
3883PM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification
3884SDK2
38853.3 Encryption Status Definitions
3886Encryption engine generated errors.
3887Table 7 Encryption Engine Generated Errors
3888Error Definition
3889*/
3890
3891/*
3892PM 1.01
3893section 4.26.12.6 Encryption Errors
3894Table 51 lists initialization errors related to encryption functionality. For information on errors reported
3895for inbound IOMB commands, refer to the corresponding outbound response sections. The error codes
3896listed in Table 51 are reported in the Scratchpad 3 Register.
3897*/
3898#define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Test */
3899#define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition is reported based on the bootstrap pin setting. */
3900#define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while reading initialization password or Allowable Cipher Modes. */
3901#define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initialization password or Allowable Cipher Modes. */
3902#define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM doesn't match any valid password value. This could also mean SEEPROM is blank. */
3903#define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing initialization password or Allowable Cipher Modes. */
3904#define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */
3905#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing to flash memory. */
3906#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing to flash memory. */
3907#define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */
3908#define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is only detected in Security Mode B. */
3909#define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memory. This error is only detected in Security Mode B. */
3910#define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */
3911#define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */
3912
3913/* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */
3914/* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */
3915/* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */
3916/* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */
3917/* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */
3918/* 0x20:ENC_ERR_FLASH_ACCESS_TMO */
3919/* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */
3920/* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */
3921/* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */
3922/* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */
3923/* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */
3924/* 0x41:ENC_ERR_AES_BIST_FAILURE */
3925/* 0x42:ENC_ERR_KWP_BIST_FAILURE */
3926
3927/*
3928This field indicates self test failure in DIF engine bits [27:24].
3929*/
3930
3931#define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */
3932
3933#define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */
3934#define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */
3935#define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */
3936#define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */
3937
3938#define SA_ROLE_CAPABILITIES_CSP 0x001
3939#define SA_ROLE_CAPABILITIES_OPR 0x002
3940#define SA_ROLE_CAPABILITIES_SCO 0x004
3941#define SA_ROLE_CAPABILITIES_STS 0x008
3942#define SA_ROLE_CAPABILITIES_TST 0x010
3943#define SA_ROLE_CAPABILITIES_KEK 0x020
3944#define SA_ROLE_CAPABILITIES_DEK 0x040
3945#define SA_ROLE_CAPABILITIES_IOS 0x080
3946#define SA_ROLE_CAPABILITIES_FWU 0x100
3947#define SA_ROLE_CAPABILITIES_PRM 0x200
3948
3949
3950#include "saapi.h"
3951/***********************************************************************************
3952 * *
3953 * The LL Layer Functions Declarations end *
3954 * *
3955 ***********************************************************************************/
3956
3957#endif /*__SA_H__ */
lun
bit32 lun
Definition: encrypt_ioctl.h:3
status
bit32 status
Definition: encrypt_ioctl.h:12
bit16
unsigned short bit16
Definition: ostypes.h:98
bit64
unsigned long long bit64
Definition: ostypes.h:104
bit32
unsigned int bit32
Definition: ostypes.h:99
agBOOLEAN
#define agBOOLEAN
Definition: ostypes.h:146
S32
int S32
Definition: ostypes.h:118
bit8
unsigned char bit8
Definition: ostypes.h:97
agsaInterruptConfigPage_t
struct agsaInterruptConfigPage_s agsaInterruptConfigPage_t
agsaHwConfig_t
struct agsaHwConfig_s agsaHwConfig_t
structure describe hardware configuration
agsaFatalErrorInfo_t
struct agsaFatalErrorInfo_s agsaFatalErrorInfo_t
describe a fatal error information for a Controller in the SAS/SATA hardware
ossaSMPCompletedCB_t
void(* ossaSMPCompletedCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 agIOStatus, bit32 agIOInfoLen, agsaFrameHandle_t agFrameHandle)
Callback definition for.
Definition: sa.h:3530
agsaHWEventMode_t
struct agsaHWEventMode_s agsaHWEventMode_t
agsaQueueInbound_t
struct agsaQueueInbound_s agsaQueueInbound_t
agsaEsgl_t
struct agsaEsgl_s agsaEsgl_t
data structure is used to pass information about the extended scatter-gather list (ESGL) to the LL La...
agsaEncryptDek_t
struct agsaEncryptDek_s agsaEncryptDek_t
agsaFrameHandle_t
void * agsaFrameHandle_t
handle to access frame
Definition: sa.h:1719
agsaEncrypt_t
struct agsaEncrypt_s agsaEncrypt_t
DIF_UDT_SIZE
#define DIF_UDT_SIZE
Definition: sa.h:2800
agsaSASRequestBody_t
union agsaSASRequestBody_u agsaSASRequestBody_t
union data structure specifies a request
ossaDeviceRegistrationCB_t
void(* ossaDeviceRegistrationCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, agsaDevHandle_t *agDevHandle, bit32 deviceID)
Callback definition for .ossaDeviceRegistration.
Definition: sa.h:3469
agsaPhyRateControlPage_t
struct agsaPhyRateControlPage_s agsaPhyRateControlPage_t
describe a Phy Rate Control 4.56 agsaPhyRateControlPage_t Description This profile page is used to re...
agsaPhyErrCounters_t
struct agsaPhyErrCounters_s agsaPhyErrCounters_t
structure describe error counters of a PHY in the SAS/SATA
agsaIOErrorEventStats_t
struct agsaIOErrorEventStats_s agsaIOErrorEventStats_t
PSASG_DESCRIPTOR
struct _SASG_DESCRIPTOR * PSASG_DESCRIPTOR
agsaGpioWriteSetupInfo_t
struct agsaGpioWriteSetupInfo_s agsaGpioWriteSetupInfo_t
describe a serial GPIO operation in the SAS/SATA hardware
agsaDifEncPayload_t
struct agsaDifEncPayload_s agsaDifEncPayload_t
ossaDeregisterDeviceHandleCB_t
void(* ossaDeregisterDeviceHandleCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaDevHandle_t *agDevHandle, bit32 status)
Callback definition for.
Definition: sa.h:3480
agsaFwImg_t
struct agsaFwImg_s agsaFwImg_t
agsaEncryptDekConfigPage_t
struct agsaEncryptDekConfigPage_s agsaEncryptDekConfigPage_t
agsaContext_t
struct agsaContext_s agsaContext_t
data structure stores OS specific and LL specific context
agsaSASPhyGeneralStatusPage_t
struct agsaSASPhyGeneralStatusPage_s agsaSASPhyGeneralStatusPage_t
for the SAS/SATA LL Layer
agsaSGpioCfg0_t
struct agsaSGpioCfg0 agsaSGpioCfg0_t
describe a serial GPIO operation response in the SAS/SATA hardware
agsaPhyConfig_t
struct agsaPhyConfig_s agsaPhyConfig_t
describe a configuration for a PHY in the SAS/SATA hardware
agsaPCIeDiagExecute_t
struct agsaPCIeDiagExecute_s agsaPCIeDiagExecute_t
agsaSASDiagExecute_t
struct agsaSASDiagExecute_s agsaSASDiagExecute_t
specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer
agsaSMPFrame_t
struct agsaSMPFrame_s agsaSMPFrame_t
data structure describes a SMP request or response frame to be sent on the SAS port
ossaGenericCB_t
void(* ossaGenericCB_t)(void)
Callback definition for.
Definition: sa.h:3490
agsaDeviceInfo_t
struct agsaDeviceInfo_s agsaDeviceInfo_t
data structure provides some information about a SATA device
agsaControllerStatus_t
struct agsaControllerStatus_s agsaControllerStatus_t
describe a status for a Controller in the SAS/SATA hardware
ossaGenericAbortCB_t
void(* ossaGenericAbortCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 flag, bit32 status)
Callback definition for abort SMP SSP SATA callback.
Definition: sa.h:3496
AGSA_MAX_VALID_PHYS
#define AGSA_MAX_VALID_PHYS
Definition: sa.h:817
agsaGpioEventSetupInfo_t
struct agsaGpioEventSetupInfo_s agsaGpioEventSetupInfo_t
describe a GPIO Event Setup Infomation in the SAS/SATA hardware
agsaSSPInitiatorRequest_t
struct agsaSSPInitiatorRequest_s agsaSSPInitiatorRequest_t
data structure describes a SAS SSP command request to be sent to the target device
agsaEncryptSelfTestStatusBitMap_t
struct agsaEncryptSelfTestStatusBitMap_s agsaEncryptSelfTestStatusBitMap_t
agsaDif_t
struct agsaDif_s agsaDif_t
agsaSSPCmdInfoUnitExt_t
struct agsaSSPCmdInfoUnitExt_s agsaSSPCmdInfoUnitExt_t
agsaEncryptSelfTestBitMap_t
struct agsaEncryptSelfTestBitMap_s agsaEncryptSelfTestBitMap_t
agsaQueueOutbound_t
struct agsaQueueOutbound_s agsaQueueOutbound_t
AGSA_MAX_OUTBOUND_Q
#define AGSA_MAX_OUTBOUND_Q
Definition: sa.h:828
agsaDevHandle_t
agsaContext_t agsaDevHandle_t
holds the pointers to the device data structure used by the LL and OS Layers
Definition: sa.h:1683
AGSA_ID_SIZE
#define AGSA_ID_SIZE
Definition: sa.h:3291
agsaDifDetails_t
struct agsaDifDetails_s agsaDifDetails_t
agsaEncryptSHATestDescriptor_t
struct agsaEncryptSHATestDescriptor_s agsaEncryptSHATestDescriptor_t
agsaSATAInitiatorRequest_t
struct agsaSATAInitiatorRequest_s agsaSATAInitiatorRequest_t
data structure describes an STP or direct connect SATA command
agsaNVMDData_t
struct agsaNVMDData_s agsaNVMDData_t
describe a NVMData for a Controller in the SAS/SATA hardware
ossaSSPCompletedCB_t
void(* ossaSSPCompletedCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 agIOStatus, bit32 agIOInfoLen, void *agParam, bit16 sspTag, bit32 agOtherInfo)
Callback definition for.
Definition: sa.h:3542
agsaHWEventEncrypt_t
struct agsaHWEventEncrypt_s agsaHWEventEncrypt_t
agsaEncryptKekBlob_t
struct agsaEncryptKekBlob_s agsaEncryptKekBlob_t
agsaIoGeneralPage_t
struct agsaIoGeneralPage_s agsaIoGeneralPage_t
agsaEncryptControlParamPage_t
struct agsaEncryptControlParamPage_s agsaEncryptControlParamPage_t
agsaUpdateFwFlash_t
struct agsaUpdateFwFlash_s agsaUpdateFwFlash_t
data structure for firmware flash update saFwFlashUpdate().
ossaSATACompletedCB_t
void(* ossaSATACompletedCB_t)(agsaRoot_t *agRoot, agsaIORequest_t *agIORequest, bit32 agIOStatus, void *agFirstDword, bit32 agIOInfoLen, void *agParam)
Callback definition for.
Definition: sa.h:3517
agsaMPIContext_t
struct agsaMPIContext_s agsaMPIContext_t
data structure for set fields in MPI table. The agsaMPIContext_t data structure is used to set fields...
agsaPhyErrCountersPage_t
struct agsaPhyErrCountersPage_s agsaPhyErrCountersPage_t
used in saGetPhyProfile
AGSA_MAX_INBOUND_Q
#define AGSA_MAX_INBOUND_Q
Definition: sa.h:827
agsaSASAddressID_t
struct agsaSASAddressID_s agsaSASAddressID_t
describe a SAS address and PHY Identifier
MAX_CDB_LEN
#define MAX_CDB_LEN
data structure describes an SSP Command INFORMATION UNIT
Definition: sa.h:2789
agsaEncryptHMACConfigPage_t
struct agsaEncryptHMACConfigPage_s agsaEncryptHMACConfigPage_t
agsaPhyAnalogSettingsPage_t
struct agsaPhyAnalogSettingsPage_s agsaPhyAnalogSettingsPage_t
describe a Phy Analog Setting
agsaFlashExtResponse_t
struct agsaFlashExtResponse_s agsaFlashExtResponse_t
data structure for firmware flash update saFwFlashUpdate().
agsaBarOffset_t
struct agsaBarOffset_s agsaBarOffset_t
describe an element of SPC-SPCV converter
agsaEncryptDekBlob_t
struct agsaEncryptDekBlob_s agsaEncryptDekBlob_t
agsaSGpioCfg1_t
struct agsaSGpioCfg1 agsaSGpioCfg1_t
SGPIO configuration register 1.
agsaEncryptHMACTestDescriptor_t
struct agsaEncryptHMACTestDescriptor_s agsaEncryptHMACTestDescriptor_t
agsaEncryptGeneralPage_t
struct agsaEncryptGeneralPage_s agsaEncryptGeneralPage_t
agsaSASReconfig_t
struct agsaSASReconfig_s agsaSASReconfig_t
describe a SAS ReCofiguration structure in the SAS/SATA hardware
agsaEncryptInfo_t
struct agsaEncryptInfo_s agsaEncryptInfo_t
OSSA_SGPIO_MAX_READ_DATA_COUNT
#define OSSA_SGPIO_MAX_READ_DATA_COUNT
Definition: sa.h:1617
agsaSgl_t
struct agsaSgl_s agsaSgl_t
data structure used to pass information about the scatter-gather list to the LL Layer
agsaGpioPinSetupInfo_t
struct agsaGpioPinSetupInfo_t agsaGpioPinSetupInfo_t
describe a GPIO Pin Setup Infomation in the SAS/SATA hardware
MAX_ESGL_ENTRIES
#define MAX_ESGL_ENTRIES
Definition: sa.h:822
agsaPhyAnalogSetupTable_t
struct agsaPhyAnalogSetupTable_s agsaPhyAnalogSetupTable_t
ossaLocalPhyControlCB_t
void(* ossaLocalPhyControlCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 phyId, bit32 phyOperation, bit32 status, void *parm)
Definition: sa.h:3504
agsaSSPTargetRequest_t
struct agsaSSPTargetRequest_s agsaSSPTargetRequest_t
data structure describes a SAS SSP target read and write request
agsaControllerInfo_t
struct agsaControllerInfo_s agsaControllerInfo_t
describe a information for a Controller in the SAS/SATA hardware
agsaSASDeviceInfo_t
struct agsaSASDeviceInfo_s agsaSASDeviceInfo_t
data structure provides some information about a SAS device
agsaOffloadDifDetails_t
struct agsaOffloadDifDetails_s agsaOffloadDifDetails_t
ossaVhistCaptureCB_t
void(* ossaVhistCaptureCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, bit32 len)
Definition: sa.h:3584
agsaSASPhyMiscPage_t
struct agsaSASPhyMiscPage_s agsaSASPhyMiscPage_t
agsaSASPhyOpenRejectRetryBackOffThresholdPage_t
struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s agsaSASPhyOpenRejectRetryBackOffThresholdPage_t
describe a Open reject retry backoff threshold page
agsaFlashExtExecute_t
struct agsaFlashExtExecute_s agsaFlashExtExecute_t
data structure for extended firmware flash update saFwFlashExtUpdate().
agsaID_t
struct agsaID_s agsaID_t
agsaRoot_t
agsaContext_t agsaRoot_t
hold points to global data structures used by the LL and OS Layers
Definition: sa.h:1673
agsaSATADeviceInfo_t
struct agsaSATADeviceInfo_s agsaSATADeviceInfo_t
data structure provides some information about a SATA device
agsaControllerEventLog_t
struct agsaControllerEventLog_s agsaControllerEventLog_t
specify the controller Event Log for the SAS/SATA LL Layer
agsaPortContext_t
agsaContext_t agsaPortContext_t
holds the pointers to the port data structure used by the LL and OS Layers
Definition: sa.h:1700
agsaPhyBWCountersPage_t
struct agsaPhyBWCountersPage_s agsaPhyBWCountersPage_t
structure describes bandwidth counters of a PHY in the SAS/SATA
agsaEventSource_t
struct agsaEventSource_s agsaEventSource_t
describe a information for a Event in the SAS/SATA hardware
agsaSSPTargetResponse_t
struct agsaSSPTargetResponse_s agsaSSPTargetResponse_t
data structure describes a SAS SSP target response to be issued on the port
ossaDIFEncryptionOffloadStartCB_t
void(* ossaDIFEncryptionOffloadStartCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, bit32 status, agsaOffloadDifDetails_t *agsaOffloadDifDetails)
Definition: sa.h:3590
agsaSGpioReqResponse_t
struct agsaSGpioReqResponse_s agsaSGpioReqResponse_t
describe a serial GPIO request and response in the SAS/SATA hardware
MAX_INDEX
#define MAX_INDEX
Definition: sa.h:1763
agsaIORequest_t
agsaContext_t agsaIORequest_t
data structure pointer to IO request structure
Definition: sa.h:1713
agsaPhyCalibrationTbl_t
struct agsaPhyCalibrationTbl_s agsaPhyCalibrationTbl_t
agsaPhyAnalogSetupRegisters_t
struct agsaPhyAnalogSetupRegisters_s agsaPhyAnalogSetupRegisters_t
describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware
agsaEncryptSHATestResult_t
struct agsaEncryptSHATestResult_s agsaEncryptSHATestResult_t
SASG_DESCRIPTOR
struct _SASG_DESCRIPTOR SASG_DESCRIPTOR
the data structure describe SG list
agsaQueueConfig_t
struct agsaQueueConfig_s agsaQueueConfig_t
agsaSSPInitiatorRequestExt_t
struct agsaSSPInitiatorRequestExt_s agsaSSPInitiatorRequestExt_t
data structure describes a SAS SSP command request Ext to be sent to the target device
agsaMem_t
struct agsaMem_s agsaMem_t
generic memory descriptor
agsaEncryptHMACTestResult_t
struct agsaEncryptHMACTestResult_s agsaEncryptHMACTestResult_t
agsaSASProtocolTimerConfigurationPage_t
struct agsaSASProtocolTimerConfigurationPage_s agsaSASProtocolTimerConfigurationPage_t
data structure for SAS protocol timer configuration page.
agsaPhySNW3Page_t
struct agsaPhySNW3Page_s agsaPhySNW3Page_t
Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter.
agsaMemoryRequirement_t
struct agsaMemoryRequirement_s agsaMemoryRequirement_t
specify the memory allocation requirement for the SAS/SATA LL Layer
AGSA_NUM_MEM_CHUNKS
#define AGSA_NUM_MEM_CHUNKS
Definition: sa.h:809
agsaGpioReadInfo_t
struct agsaGpioReadInfo_s agsaGpioReadInfo_t
describe a GPIO Read Infomation in the SAS/SATA hardware
ossaSetDeviceInfoCB_t
void(* ossaSetDeviceInfoCB_t)(agsaRoot_t *agRoot, agsaContext_t *agContext, agsaDevHandle_t *agDevHandle, bit32 status, bit32 option, bit32 param)
Callback definition for.
Definition: sa.h:3555
agsaSSPInitiatorRequestIndirect_t
struct agsaSSPInitiatorRequestIndirect_s agsaSSPInitiatorRequestIndirect_t
agsaRegDumpInfo_t
struct agsaRegDumpInfo_s agsaRegDumpInfo_t
describe a Register Dump information for a Controller in the SAS/SATA hardware
agsaPCIeDiagResponse_t
struct agsaPCIeDiagResponse_s agsaPCIeDiagResponse_t
agsaPCIeDiagResponse_t
agsabit32bit64
union agsabit32bit64_U agsabit32bit64
agsaSwConfig_t
struct agsaSwConfig_s agsaSwConfig_t
structure describe software configuration
sa_err.h
The file defines the error code constants, defined by LL API.
sa_spec.h
The file defines the constants defined by sas spec.
saapi.h
The file defines the declaration of tSDK APIs.
saosapi.h
The file defines the declaration of OS APIs.
_SASG_DESCRIPTOR
the data structure describe SG list
Definition: sa.h:2738
_SASG_DESCRIPTOR::sgUpper
bit32 sgUpper
Definition: sa.h:2740
_SASG_DESCRIPTOR::sgLower
bit32 sgLower
Definition: sa.h:2739
_SASG_DESCRIPTOR::len
bit32 len
Definition: sa.h:2741
agsaBarOffset_s
describe an element of SPC-SPCV converter
Definition: sa.h:3619
agsaBarOffset_s::Offset
bit32 Offset
Definition: sa.h:3622
agsaBarOffset_s::Generic
bit32 Generic
Definition: sa.h:3620
agsaBarOffset_s::Length
bit32 Length
Definition: sa.h:3623
agsaBarOffset_s::Bar
bit32 Bar
Definition: sa.h:3621
agsaContext_s
data structure stores OS specific and LL specific context
Definition: sa.h:1658
agsaContext_s::osData
void * osData
Definition: sa.h:1659
agsaContext_s::sdkData
void * sdkData
Definition: sa.h:1660
agsaControllerEventLog_s
specify the controller Event Log for the SAS/SATA LL Layer
Definition: sa.h:2484
agsaControllerEventLog_s::eventLog1
agsaMem_t eventLog1
Definition: sa.h:2485
agsaControllerEventLog_s::eventLog2
agsaMem_t eventLog2
Definition: sa.h:2486
agsaControllerEventLog_s::eventLog2Option
bit32 eventLog2Option
Definition: sa.h:2488
agsaControllerEventLog_s::eventLog1Option
bit32 eventLog1Option
Definition: sa.h:2487
agsaControllerInfo_s
describe a information for a Controller in the SAS/SATA hardware
Definition: sa.h:2045
agsaControllerInfo_s::PCILinkRate
bit8 PCILinkRate
Definition: sa.h:2065
agsaControllerInfo_s::fwInterfaceRev
bit32 fwInterfaceRev
Definition: sa.h:2047
agsaControllerInfo_s::maxDevices
bit32 maxDevices
Definition: sa.h:2052
agsaControllerInfo_s::ilaRevision
bit32 ilaRevision
Definition: sa.h:2050
agsaControllerInfo_s::queueSupport
bit32 queueSupport
Definition: sa.h:2054
agsaControllerInfo_s::hwRevision
bit32 hwRevision
Definition: sa.h:2048
agsaControllerInfo_s::controllerSetting
bit8 controllerSetting
Definition: sa.h:2062
agsaControllerInfo_s::maxSgElements
bit32 maxSgElements
Definition: sa.h:2053
agsaControllerInfo_s::PCIWidth
bit8 PCIWidth
Definition: sa.h:2066
agsaControllerInfo_s::maxPendingIO
bit32 maxPendingIO
Definition: sa.h:2051
agsaControllerInfo_s::phyCount
bit8 phyCount
Definition: sa.h:2061
agsaControllerInfo_s::sdkInterfaceRev
bit32 sdkInterfaceRev
Definition: sa.h:2068
agsaControllerInfo_s::sdkRevision
bit32 sdkRevision
Definition: sa.h:2069
agsaControllerInfo_s::fwRevision
bit32 fwRevision
Definition: sa.h:2049
agsaControllerInfo_s::signature
bit32 signature
Definition: sa.h:2046
agsaControllerInfo_s::sasSpecsSupport
bit32 sasSpecsSupport
Definition: sa.h:2067
agsaControllerStatus_s
describe a status for a Controller in the SAS/SATA hardware
Definition: sa.h:2078
agsaControllerStatus_s::bootStatus
bit32 bootStatus
Definition: sa.h:2091
agsaControllerStatus_s::tickCount0
bit32 tickCount0
Definition: sa.h:2086
agsaControllerStatus_s::tickCount2
bit32 tickCount2
Definition: sa.h:2088
agsaControllerStatus_s::iqFreezeState0
bit32 iqFreezeState0
Definition: sa.h:2084
agsaControllerStatus_s::iqFreezeState1
bit32 iqFreezeState1
Definition: sa.h:2085
agsaControllerStatus_s::phyStatus
bit32 phyStatus[8]
Definition: sa.h:2089
agsaControllerStatus_s::tickCount1
bit32 tickCount1
Definition: sa.h:2087
agsaControllerStatus_s::recoverableErrorInfo
bit32 recoverableErrorInfo[8]
Definition: sa.h:2090
agsaControllerStatus_s::interfaceState
bit32 interfaceState
Definition: sa.h:2080
agsaControllerStatus_s::bootComponentState
bit16 bootComponentState[8]
Definition: sa.h:2092
agsaControllerStatus_s::fatalErrorInfo
agsaFatalErrorInfo_t fatalErrorInfo
Definition: sa.h:2079
agsaDeviceInfo_s
data structure provides some information about a SATA device
Definition: sa.h:2561
agsaDeviceInfo_s::sasAddressHi
bit8 sasAddressHi[4]
Definition: sa.h:2580
agsaDeviceInfo_s::reserved
bit8 reserved
Definition: sa.h:2565
agsaDeviceInfo_s::devType_S_Rate
bit8 devType_S_Rate
Definition: sa.h:2567
agsaDeviceInfo_s::firstBurstSize
bit16 firstBurstSize
Definition: sa.h:2564
agsaDeviceInfo_s::smpTimeout
bit16 smpTimeout
Definition: sa.h:2562
agsaDeviceInfo_s::sasAddressLo
bit8 sasAddressLo[4]
Definition: sa.h:2581
agsaDeviceInfo_s::flag
bit32 flag
Definition: sa.h:2582
agsaDeviceInfo_s::it_NexusTimeout
bit16 it_NexusTimeout
Definition: sa.h:2563
agsaDifDetails_s
Definition: sa.h:3356
agsaDifDetails_s::sasAddressHi
bit8 sasAddressHi[4]
Definition: sa.h:3359
agsaDifDetails_s::ExpectedUDT2345
bit32 ExpectedUDT2345
Definition: sa.h:3362
agsaDifDetails_s::LowerLBA
bit32 LowerLBA
Definition: sa.h:3358
agsaDifDetails_s::ErrBoffsetEDataLen
bit32 ErrBoffsetEDataLen
Definition: sa.h:3366
agsaDifDetails_s::frame
void * frame
Definition: sa.h:3367
agsaDifDetails_s::ActualCRCUDT01
bit32 ActualCRCUDT01
Definition: sa.h:3363
agsaDifDetails_s::sasAddressLo
bit8 sasAddressLo[4]
Definition: sa.h:3360
agsaDifDetails_s::ActualUDT2345
bit32 ActualUDT2345
Definition: sa.h:3364
agsaDifDetails_s::UpperLBA
bit32 UpperLBA
Definition: sa.h:3357
agsaDifDetails_s::DIFErrDevID
bit32 DIFErrDevID
Definition: sa.h:3365
agsaDifDetails_s::ExpectedCRCUDT01
bit32 ExpectedCRCUDT01
Definition: sa.h:3361
agsaDifEncPayload_s
Definition: sa.h:3575
agsaDifEncPayload_s::SrcDL
bit32 SrcDL
Definition: sa.h:3577
agsaDifEncPayload_s::DstDL
bit32 DstDL
Definition: sa.h:3579
agsaDifEncPayload_s::SrcSgl
agsaSgl_t SrcSgl
Definition: sa.h:3576
agsaDifEncPayload_s::dif
agsaDif_t dif
Definition: sa.h:3580
agsaDifEncPayload_s::encrypt
agsaEncrypt_t encrypt
Definition: sa.h:3581
agsaDifEncPayload_s::DstSgl
agsaSgl_t DstSgl
Definition: sa.h:3578
agsaDif_s
Definition: sa.h:2818
agsaDif_s::Reserved2
bit16 Reserved2
Definition: sa.h:2826
agsaDif_s::udtArray
bit8 udtArray[DIF_UDT_SIZE]
Definition: sa.h:2827
agsaDif_s::reserved
bit16 reserved
Definition: sa.h:2822
agsaDif_s::DIFPerLAAddrLo
bit32 DIFPerLAAddrLo
Definition: sa.h:2823
agsaDif_s::initialIOSeed
bit16 initialIOSeed
Definition: sa.h:2821
agsaDif_s::flags
bit32 flags
Definition: sa.h:2820
agsaDif_s::DIFPerLARegion0SecCount
bit16 DIFPerLARegion0SecCount
Definition: sa.h:2825
agsaDif_s::DIFPerLAAddrHi
bit32 DIFPerLAAddrHi
Definition: sa.h:2824
agsaDif_s::udrtArray
bit8 udrtArray[DIF_UDT_SIZE]
Definition: sa.h:2828
agsaDif_s::enableDIFPerLA
agBOOLEAN enableDIFPerLA
Definition: sa.h:2819
agsaEncryptControlParamPage_s
Definition: sa.h:3199
agsaEncryptControlParamPage_s::NOPR
bit32 NOPR
Definition: sa.h:3204
agsaEncryptControlParamPage_s::pageCode
bit32 pageCode
Definition: sa.h:3200
agsaEncryptControlParamPage_s::USRCAP
bit32 USRCAP
Definition: sa.h:3202
agsaEncryptControlParamPage_s::CCS
bit32 CCS
Definition: sa.h:3203
agsaEncryptControlParamPage_s::CORCAP
bit32 CORCAP
Definition: sa.h:3201
agsaEncryptDekBlob_s
Definition: sa.h:3273
agsaEncryptDekBlob_s::dekBlob
bit8 dekBlob[80]
Definition: sa.h:3274
agsaEncryptDekConfigPage_s
Definition: sa.h:3179
agsaEncryptDekConfigPage_s::table0AddrHi
bit32 table0AddrHi
Definition: sa.h:3182
agsaEncryptDekConfigPage_s::table1Entries
bit32 table1Entries
Definition: sa.h:3187
agsaEncryptDekConfigPage_s::pageCode
bit32 pageCode
Definition: sa.h:3180
agsaEncryptDekConfigPage_s::table0BFES
bit32 table0BFES
Definition: sa.h:3184
agsaEncryptDekConfigPage_s::table1AddrHi
bit32 table1AddrHi
Definition: sa.h:3186
agsaEncryptDekConfigPage_s::table0AddrLo
bit32 table0AddrLo
Definition: sa.h:3181
agsaEncryptDekConfigPage_s::table1AddrLo
bit32 table1AddrLo
Definition: sa.h:3185
agsaEncryptDekConfigPage_s::table0Entries
bit32 table0Entries
Definition: sa.h:3183
agsaEncryptDekConfigPage_s::table1BFES
bit32 table1BFES
Definition: sa.h:3188
agsaEncryptDek_s
Definition: sa.h:2856
agsaEncryptDek_s::dekTable
bit32 dekTable
Definition: sa.h:2857
agsaEncryptDek_s::dekIndex
bit32 dekIndex
Definition: sa.h:2858
agsaEncryptGeneralPage_s
Definition: sa.h:3169
agsaEncryptGeneralPage_s::numberOfDeks
bit32 numberOfDeks
Definition: sa.h:3171
agsaEncryptGeneralPage_s::pageCode
bit32 pageCode
Definition: sa.h:3170
agsaEncryptHMACConfigPage_s
Definition: sa.h:3283
agsaEncryptHMACConfigPage_s::PageCode
bit32 PageCode
Definition: sa.h:3284
agsaEncryptHMACConfigPage_s::KeyAddrLo
bit32 KeyAddrLo
Definition: sa.h:3286
agsaEncryptHMACConfigPage_s::KeyAddrHi
bit32 KeyAddrHi
Definition: sa.h:3287
agsaEncryptHMACConfigPage_s::CustomerTag
bit32 CustomerTag
Definition: sa.h:3285
agsaEncryptHMACTestDescriptor_s
Definition: sa.h:3232
agsaEncryptHMACTestDescriptor_s::KeyAddrLo
bit32 KeyAddrLo
Definition: sa.h:3239
agsaEncryptHMACTestDescriptor_s::DigestAddrLo
bit32 DigestAddrLo
Definition: sa.h:3237
agsaEncryptHMACTestDescriptor_s::KeyAddrHi
bit32 KeyAddrHi
Definition: sa.h:3240
agsaEncryptHMACTestDescriptor_s::MsgAddrLo
bit32 MsgAddrLo
Definition: sa.h:3234
agsaEncryptHMACTestDescriptor_s::KeyLen
bit32 KeyLen
Definition: sa.h:3241
agsaEncryptHMACTestDescriptor_s::Dword0
bit32 Dword0
Definition: sa.h:3233
agsaEncryptHMACTestDescriptor_s::DigestAddrHi
bit32 DigestAddrHi
Definition: sa.h:3238
agsaEncryptHMACTestDescriptor_s::MsgLen
bit32 MsgLen
Definition: sa.h:3236
agsaEncryptHMACTestDescriptor_s::MsgAddrHi
bit32 MsgAddrHi
Definition: sa.h:3235
agsaEncryptHMACTestResult_s
Definition: sa.h:3245
agsaEncryptHMACTestResult_s::Dword
bit32 Dword[12]
Definition: sa.h:3247
agsaEncryptHMACTestResult_s::Dword0
bit32 Dword0
Definition: sa.h:3246
agsaEncryptInfo_s
Definition: sa.h:3207
agsaEncryptInfo_s::status
bit32 status
Definition: sa.h:3210
agsaEncryptInfo_s::encryptionSecurityMode
bit32 encryptionSecurityMode
Definition: sa.h:3209
agsaEncryptInfo_s::flag
bit32 flag
Definition: sa.h:3211
agsaEncryptInfo_s::encryptionCipherMode
bit32 encryptionCipherMode
Definition: sa.h:3208
agsaEncryptKekBlob_s
Definition: sa.h:3277
agsaEncryptKekBlob_s::kekBlob
bit8 kekBlob[48]
Definition: sa.h:3278
agsaEncryptSHATestDescriptor_s
Definition: sa.h:3251
agsaEncryptSHATestDescriptor_s::MsgAddrHi
bit32 MsgAddrHi
Definition: sa.h:3254
agsaEncryptSHATestDescriptor_s::MsgLen
bit32 MsgLen
Definition: sa.h:3255
agsaEncryptSHATestDescriptor_s::DigestAddrHi
bit32 DigestAddrHi
Definition: sa.h:3257
agsaEncryptSHATestDescriptor_s::Dword0
bit32 Dword0
Definition: sa.h:3252
agsaEncryptSHATestDescriptor_s::DigestAddrLo
bit32 DigestAddrLo
Definition: sa.h:3256
agsaEncryptSHATestDescriptor_s::MsgAddrLo
bit32 MsgAddrLo
Definition: sa.h:3253
agsaEncryptSHATestResult_s
Definition: sa.h:3261
agsaEncryptSHATestResult_s::Dword0
bit32 Dword0
Definition: sa.h:3262
agsaEncryptSHATestResult_s::Dword
bit32 Dword[12]
Definition: sa.h:3263
agsaEncryptSelfTestBitMap_s
Definition: sa.h:3219
agsaEncryptSelfTestBitMap_s::KEY_WRAP_Test
bit32 KEY_WRAP_Test
Definition: sa.h:3221
agsaEncryptSelfTestBitMap_s::AES_Test
bit32 AES_Test
Definition: sa.h:3220
agsaEncryptSelfTestBitMap_s::HMAC_Test
bit32 HMAC_Test
Definition: sa.h:3222
agsaEncryptSelfTestStatusBitMap_s
Definition: sa.h:3225
agsaEncryptSelfTestStatusBitMap_s::KEY_WRAP_Status
bit32 KEY_WRAP_Status
Definition: sa.h:3227
agsaEncryptSelfTestStatusBitMap_s::AES_Status
bit32 AES_Status
Definition: sa.h:3226
agsaEncryptSelfTestStatusBitMap_s::HMAC_Status
bit32 HMAC_Status
Definition: sa.h:3228
agsaEncrypt_s
Definition: sa.h:2862
agsaEncrypt_s::enableEncryptionPerLA
agBOOLEAN enableEncryptionPerLA
Definition: sa.h:2866
agsaEncrypt_s::keyTag_W1
bit32 keyTag_W1
Definition: sa.h:2870
agsaEncrypt_s::reserved
bit16 reserved
Definition: sa.h:2878
agsaEncrypt_s::EncryptionPerLAAddrLo
bit32 EncryptionPerLAAddrLo
Definition: sa.h:2875
agsaEncrypt_s::sectorSizeIndex
bit32 sectorSizeIndex
Definition: sa.h:2867
agsaEncrypt_s::tweakVal_W3
bit32 tweakVal_W3
Definition: sa.h:2874
agsaEncrypt_s::tweakVal_W0
bit32 tweakVal_W0
Definition: sa.h:2871
agsaEncrypt_s::kekIndex
bit32 kekIndex
Definition: sa.h:2864
agsaEncrypt_s::keyTag_W0
bit32 keyTag_W0
Definition: sa.h:2869
agsaEncrypt_s::EncryptionPerLAAddrHi
bit32 EncryptionPerLAAddrHi
Definition: sa.h:2876
agsaEncrypt_s::EncryptionPerLRegion0SecCount
bit16 EncryptionPerLRegion0SecCount
Definition: sa.h:2877
agsaEncrypt_s::keyTagCheck
agBOOLEAN keyTagCheck
Definition: sa.h:2865
agsaEncrypt_s::cipherMode
bit32 cipherMode
Definition: sa.h:2868
agsaEncrypt_s::tweakVal_W2
bit32 tweakVal_W2
Definition: sa.h:2873
agsaEncrypt_s::dekInfo
agsaEncryptDek_t dekInfo
Definition: sa.h:2863
agsaEncrypt_s::tweakVal_W1
bit32 tweakVal_W1
Definition: sa.h:2872
agsaEsgl_s
data structure is used to pass information about the extended scatter-gather list (ESGL) to the LL La...
Definition: sa.h:2777
agsaEsgl_s::descriptor
agsaSgl_t descriptor[MAX_ESGL_ENTRIES]
Definition: sa.h:2778
agsaEventSource_s
describe a information for a Event in the SAS/SATA hardware
Definition: sa.h:2033
agsaEventSource_s::event
bit32 event
Definition: sa.h:2035
agsaEventSource_s::param
bit32 param
Definition: sa.h:2036
agsaEventSource_s::agPortContext
agsaPortContext_t * agPortContext
Definition: sa.h:2034
agsaFatalErrorInfo_s
describe a fatal error information for a Controller in the SAS/SATA hardware
Definition: sa.h:2014
agsaFatalErrorInfo_s::regDumpBusBaseNum0
bit32 regDumpBusBaseNum0
Definition: sa.h:2019
agsaFatalErrorInfo_s::regDumpLen1
bit32 regDumpLen1
Definition: sa.h:2024
agsaFatalErrorInfo_s::regDumpOffset1
bit32 regDumpOffset1
Definition: sa.h:2023
agsaFatalErrorInfo_s::errorInfo3
bit32 errorInfo3
Definition: sa.h:2018
agsaFatalErrorInfo_s::errorInfo0
bit32 errorInfo0
Definition: sa.h:2015
agsaFatalErrorInfo_s::errorInfo1
bit32 errorInfo1
Definition: sa.h:2016
agsaFatalErrorInfo_s::regDumpBusBaseNum1
bit32 regDumpBusBaseNum1
Definition: sa.h:2022
agsaFatalErrorInfo_s::errorInfo2
bit32 errorInfo2
Definition: sa.h:2017
agsaFatalErrorInfo_s::regDumpOffset0
bit32 regDumpOffset0
Definition: sa.h:2020
agsaFatalErrorInfo_s::regDumpLen0
bit32 regDumpLen0
Definition: sa.h:2021
agsaFlashExtExecute_s
data structure for extended firmware flash update saFwFlashExtUpdate().
Definition: sa.h:3405
agsaFlashExtExecute_s::dataLen
bit32 dataLen
Definition: sa.h:3408
agsaFlashExtExecute_s::command
bit32 command
Definition: sa.h:3406
agsaFlashExtExecute_s::agSgl
agsaSgl_t * agSgl
Definition: sa.h:3409
agsaFlashExtExecute_s::partOffset
bit32 partOffset
Definition: sa.h:3407
agsaFlashExtResponse_s
data structure for firmware flash update saFwFlashUpdate().
Definition: sa.h:3418
agsaFlashExtResponse_s::epart_sect_size
bit32 epart_sect_size
Definition: sa.h:3420
agsaFlashExtResponse_s::epart_size
bit32 epart_size
Definition: sa.h:3419
agsaForensicData_t
Definition: sa.h:1900
agsaForensicData_t::readLen
bit32 readLen
Definition: sa.h:1908
agsaForensicData_t::queueType
bit16 queueType
Definition: sa.h:1914
agsaForensicData_t::DataType
bit32 DataType
Definition: sa.h:1901
agsaForensicData_t::directLen
bit32 directLen
Definition: sa.h:1906
agsaForensicData_t::directOffset
bit32 directOffset
Definition: sa.h:1907
agsaForensicData_t::queueIndex
bit16 queueIndex
Definition: sa.h:1915
agsaForensicData_t::directData
void * directData
Definition: sa.h:1909
agsaFwImg_s
Definition: sa.h:2447
agsaFwImg_s::iopImg
bit8 * iopImg
Definition: sa.h:2452
agsaFwImg_s::iopLen
bit32 iopLen
Definition: sa.h:2453
agsaFwImg_s::istrImg
bit8 * istrImg
Definition: sa.h:2454
agsaFwImg_s::istrLen
bit32 istrLen
Definition: sa.h:2455
agsaFwImg_s::ilaLen
bit32 ilaLen
Definition: sa.h:2451
agsaFwImg_s::ilaImg
bit8 * ilaImg
Definition: sa.h:2450
agsaFwImg_s::aap1Img
bit8 * aap1Img
Definition: sa.h:2448
agsaFwImg_s::aap1Len
bit32 aap1Len
Definition: sa.h:2449
agsaGpioEventSetupInfo_s
describe a GPIO Event Setup Infomation in the SAS/SATA hardware
Definition: sa.h:2102
agsaGpioEventSetupInfo_s::gpioEventLevel
bit32 gpioEventLevel
Definition: sa.h:2104
agsaGpioEventSetupInfo_s::gpioEventRisingEdge
bit32 gpioEventRisingEdge
Definition: sa.h:2105
agsaGpioEventSetupInfo_s::gpioEventFallingEdge
bit32 gpioEventFallingEdge
Definition: sa.h:2106
agsaGpioEventSetupInfo_s::gpioPinMask
bit32 gpioPinMask
Definition: sa.h:2103
agsaGpioPinSetupInfo_t
describe a GPIO Pin Setup Infomation in the SAS/SATA hardware
Definition: sa.h:2115
agsaGpioPinSetupInfo_t::gpioPinMask
bit32 gpioPinMask
Definition: sa.h:2116
agsaGpioPinSetupInfo_t::gpioTypePart1
bit32 gpioTypePart1
Definition: sa.h:2118
agsaGpioPinSetupInfo_t::gpioTypePart2
bit32 gpioTypePart2
Definition: sa.h:2119
agsaGpioPinSetupInfo_t::gpioInputEnabled
bit32 gpioInputEnabled
Definition: sa.h:2117
agsaGpioReadInfo_s
describe a GPIO Read Infomation in the SAS/SATA hardware
Definition: sa.h:2139
agsaGpioReadInfo_s::gpioEventRisingEdgePart2
bit32 gpioEventRisingEdgePart2
Definition: sa.h:2145
agsaGpioReadInfo_s::gpioEventLevelChangePart2
bit32 gpioEventLevelChangePart2
Definition: sa.h:2143
agsaGpioReadInfo_s::gpioEventLevelChangePart1
bit32 gpioEventLevelChangePart1
Definition: sa.h:2142
agsaGpioReadInfo_s::gpioEventFallingEdgePart1
bit32 gpioEventFallingEdgePart1
Definition: sa.h:2146
agsaGpioReadInfo_s::gpioInputEnabled
bit32 gpioInputEnabled
Definition: sa.h:2141
agsaGpioReadInfo_s::gpioEventRisingEdgePart1
bit32 gpioEventRisingEdgePart1
Definition: sa.h:2144
agsaGpioReadInfo_s::gpioReadValue
bit32 gpioReadValue
Definition: sa.h:2140
agsaGpioReadInfo_s::gpioEventFallingEdgePart2
bit32 gpioEventFallingEdgePart2
Definition: sa.h:2147
agsaGpioWriteSetupInfo_s
describe a serial GPIO operation in the SAS/SATA hardware
Definition: sa.h:2128
agsaGpioWriteSetupInfo_s::gpioWriteVal
bit32 gpioWriteVal
Definition: sa.h:2130
agsaGpioWriteSetupInfo_s::gpioWritemask
bit32 gpioWritemask
Definition: sa.h:2129
agsaHWEventEncrypt_s
Definition: sa.h:3307
agsaHWEventEncrypt_s::handle
void * handle
Definition: sa.h:3312
agsaHWEventEncrypt_s::encryptOperation
bit32 encryptOperation
Definition: sa.h:3308
agsaHWEventEncrypt_s::param
void * param
Definition: sa.h:3313
agsaHWEventEncrypt_s::info
bit32 info
Definition: sa.h:3311
agsaHWEventEncrypt_s::status
bit32 status
Definition: sa.h:3309
agsaHWEventEncrypt_s::eq
bit32 eq
Definition: sa.h:3310
agsaHWEventMode_s
Definition: sa.h:3317
agsaHWEventMode_s::modePage
void * modePage
Definition: sa.h:3321
agsaHWEventMode_s::modePageLen
bit32 modePageLen
Definition: sa.h:3320
agsaHWEventMode_s::context
void * context
Definition: sa.h:3322
agsaHWEventMode_s::status
bit32 status
Definition: sa.h:3319
agsaHWEventMode_s::modePageOperation
bit32 modePageOperation
Definition: sa.h:3318
agsaHwConfig_s
structure describe hardware configuration
Definition: sa.h:2301
agsaHwConfig_s::hwInterruptCoalescingControl
bit32 hwInterruptCoalescingControl
Definition: sa.h:2305
agsaHwConfig_s::phyAnalogConfig
agsaPhyAnalogSetupTable_t phyAnalogConfig
Definition: sa.h:2309
agsaHwConfig_s::phyCount
bit32 phyCount
Definition: sa.h:2302
agsaHwConfig_s::hwOption
bit32 hwOption
Definition: sa.h:2307
agsaHwConfig_s::intReassertionOption
bit32 intReassertionOption
Definition: sa.h:2306
agsaHwConfig_s::hwInterruptCoalescingTimer
bit32 hwInterruptCoalescingTimer
Definition: sa.h:2304
agsaID_s
Definition: sa.h:3292
agsaID_s::ID
bit8 ID[AGSA_ID_SIZE]
Definition: sa.h:3293
agsaIOErrorEventStats_s
Definition: sa.h:3637
agsaIOErrorEventStats_s::agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS
bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS
Definition: sa.h:3638
agsaIOErrorEventStats_s::agOSSA_IO_XFER_CMD_FRAME_ISSUED
bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED
Definition: sa.h:3684
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT
bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT
Definition: sa.h:3669
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED
bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED
Definition: sa.h:3723
agsaIOErrorEventStats_s::agOSSA_IO_NO_DEVICE
bit32 agOSSA_IO_NO_DEVICE
Definition: sa.h:3645
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
Definition: sa.h:3654
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR
bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR
Definition: sa.h:3705
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_DMA
bit32 agOSSA_IO_XFER_ERROR_DMA
Definition: sa.h:3667
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID
bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID
Definition: sa.h:3712
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR
bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR
Definition: sa.h:3706
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_PEER_ABORTED
bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED
Definition: sa.h:3665
agsaIOErrorEventStats_s::agOSSA_IO_ABORT_IN_PROGRESS
bit32 agOSSA_IO_ABORT_IN_PROGRESS
Definition: sa.h:3694
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY
bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY
Definition: sa.h:3660
agsaIOErrorEventStats_s::agOSSA_IO_DS_NON_OPERATIONAL
bit32 agOSSA_IO_DS_NON_OPERATIONAL
Definition: sa.h:3687
agsaIOErrorEventStats_s::agOSSA_IO_DS_INVALID
bit32 agOSSA_IO_DS_INVALID
Definition: sa.h:3703
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
Definition: sa.h:3693
agsaIOErrorEventStats_s::agOSSA_IO_DIF_IN_ERROR
bit32 agOSSA_IO_DIF_IN_ERROR
Definition: sa.h:3649
agsaIOErrorEventStats_s::agOSSA_IO_DIF_OUT_ERROR
bit32 agOSSA_IO_DIF_OUT_ERROR
Definition: sa.h:3650
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS
bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS
Definition: sa.h:3722
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR
bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR
Definition: sa.h:3662
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DIF_MISMATCH
bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH
Definition: sa.h:3716
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH
bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH
Definition: sa.h:3718
agsaIOErrorEventStats_s::agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED
bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED
Definition: sa.h:3726
agsaIOErrorEventStats_s::agOSSA_IO_DS_IN_RECOVERY
bit32 agOSSA_IO_DS_IN_RECOVERY
Definition: sa.h:3688
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_PHY_NOT_READY
bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY
Definition: sa.h:3653
agsaIOErrorEventStats_s::agOSSA_IO_ILLEGAL_PARAMETER
bit32 agOSSA_IO_ILLEGAL_PARAMETER
Definition: sa.h:3646
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK
bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK
Definition: sa.h:3680
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH
bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH
Definition: sa.h:3717
agsaIOErrorEventStats_s::agOSSA_IO_ABORTED
bit32 agOSSA_IO_ABORTED
Definition: sa.h:3639
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT
bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT
Definition: sa.h:3664
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH
bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH
Definition: sa.h:3719
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
Definition: sa.h:3659
agsaIOErrorEventStats_s::agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE
bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE
Definition: sa.h:3685
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION
bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION
Definition: sa.h:3661
agsaIOErrorEventStats_s::agOSSA_IO_PROG_ERROR
bit32 agOSSA_IO_PROG_ERROR
Definition: sa.h:3648
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_SATA
bit32 agOSSA_IO_XFER_ERROR_SATA
Definition: sa.h:3670
agsaIOErrorEventStats_s::agOSSA_MPI_IO_RQE_BUSY_FULL
bit32 agOSSA_MPI_IO_RQE_BUSY_FULL
Definition: sa.h:3707
agsaIOErrorEventStats_s::agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT
bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT
Definition: sa.h:3674
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE
Definition: sa.h:3701
agsaIOErrorEventStats_s::agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR
bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR
Definition: sa.h:3691
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR
bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR
Definition: sa.h:3725
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED
Definition: sa.h:3702
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_NAK_RECEIVED
bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED
Definition: sa.h:3663
agsaIOErrorEventStats_s::agOSSA_IO_PORT_IN_RESET
bit32 agOSSA_IO_PORT_IN_RESET
Definition: sa.h:3686
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE
bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE
Definition: sa.h:3724
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS
bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS
Definition: sa.h:3710
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT
bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT
Definition: sa.h:3697
agsaIOErrorEventStats_s::agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR
bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR
Definition: sa.h:3675
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH
bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH
Definition: sa.h:3713
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION
bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION
Definition: sa.h:3658
agsaIOErrorEventStats_s::agOSSA_IO_UNKNOWN_ERROR
bit32 agOSSA_IO_UNKNOWN_ERROR
Definition: sa.h:3728
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED
bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED
Definition: sa.h:3678
agsaIOErrorEventStats_s::agOSSA_IO_LINK_FAILURE
bit32 agOSSA_IO_LINK_FAILURE
Definition: sa.h:3647
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN
bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN
Definition: sa.h:3677
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH
bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH
Definition: sa.h:3711
agsaIOErrorEventStats_s::agOSSA_IO_INVALID_LENGTH
bit32 agOSSA_IO_INVALID_LENGTH
Definition: sa.h:3696
agsaIOErrorEventStats_s::agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE
bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE
Definition: sa.h:3708
agsaIOErrorEventStats_s::agOSSA_IO_UNDERFLOW
bit32 agOSSA_IO_UNDERFLOW
Definition: sa.h:3641
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT
bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT
Definition: sa.h:3679
agsaIOErrorEventStats_s::agOSSA_IO_ABORT_DELAYED
bit32 agOSSA_IO_ABORT_DELAYED
Definition: sa.h:3695
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO
Definition: sa.h:3699
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK
bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK
Definition: sa.h:3681
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT
bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT
Definition: sa.h:3668
agsaIOErrorEventStats_s::agOSSA_IO_DS_IN_ERROR
bit32 agOSSA_IO_DS_IN_ERROR
Definition: sa.h:3692
agsaIOErrorEventStats_s::agOSSA_IO_ABORT_RESET
bit32 agOSSA_IO_ABORT_RESET
Definition: sa.h:3643
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_BREAK
bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK
Definition: sa.h:3656
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN
bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN
Definition: sa.h:3683
agsaIOErrorEventStats_s::agOSSA_IO_XFER_PIO_SETUP_ERROR
bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR
Definition: sa.h:3690
agsaIOErrorEventStats_s::agOSSA_IO_NOT_VALID
bit32 agOSSA_IO_NOT_VALID
Definition: sa.h:3644
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT
bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT
Definition: sa.h:3727
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE
bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE
Definition: sa.h:3673
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR
bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR
Definition: sa.h:3714
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
Definition: sa.h:3657
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST
Definition: sa.h:3700
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION
bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION
Definition: sa.h:3655
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN
bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN
Definition: sa.h:3721
agsaIOErrorEventStats_s::agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED
bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED
Definition: sa.h:3698
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE
bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE
Definition: sa.h:3672
agsaIOErrorEventStats_s::agOSSA_IO_OVERFLOW
bit32 agOSSA_IO_OVERFLOW
Definition: sa.h:3640
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_INTERNAL_RAM
bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM
Definition: sa.h:3715
agsaIOErrorEventStats_s::agOSSA_IO_FAILED
bit32 agOSSA_IO_FAILED
Definition: sa.h:3642
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_RX_FRAME
bit32 agOSSA_IO_XFER_ERROR_RX_FRAME
Definition: sa.h:3666
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE
bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE
Definition: sa.h:3676
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST
bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST
Definition: sa.h:3671
agsaIOErrorEventStats_s::agOSSA_IO_ERROR_HW_TIMEOUT
bit32 agOSSA_IO_ERROR_HW_TIMEOUT
Definition: sa.h:3651
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH
bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH
Definition: sa.h:3682
agsaIOErrorEventStats_s::agOSSA_IO_XFER_ERROR_BREAK
bit32 agOSSA_IO_XFER_ERROR_BREAK
Definition: sa.h:3652
agsaIOErrorEventStats_s::agOSSA_IO_TM_TAG_NOT_FOUND
bit32 agOSSA_IO_TM_TAG_NOT_FOUND
Definition: sa.h:3689
agsaIOErrorEventStats_s::agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY
bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY
Definition: sa.h:3709
agsaIOErrorEventStats_s::agOSSA_IO_XFER_READ_COMPL_ERR
bit32 agOSSA_IO_XFER_READ_COMPL_ERR
Definition: sa.h:3704
agsaIOErrorEventStats_s::agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME
bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME
Definition: sa.h:3720
agsaInterruptConfigPage_s
Definition: sa.h:3326
agsaInterruptConfigPage_s::ICTC5
bit32 ICTC5
Definition: sa.h:3335
agsaInterruptConfigPage_s::ICTC4
bit32 ICTC4
Definition: sa.h:3334
agsaInterruptConfigPage_s::ICTC7
bit32 ICTC7
Definition: sa.h:3337
agsaInterruptConfigPage_s::vectorMask1
bit32 vectorMask1
Definition: sa.h:3329
agsaInterruptConfigPage_s::pageCode
bit32 pageCode
Definition: sa.h:3327
agsaInterruptConfigPage_s::ICTC6
bit32 ICTC6
Definition: sa.h:3336
agsaInterruptConfigPage_s::ICTC1
bit32 ICTC1
Definition: sa.h:3331
agsaInterruptConfigPage_s::ICTC0
bit32 ICTC0
Definition: sa.h:3330
agsaInterruptConfigPage_s::ICTC3
bit32 ICTC3
Definition: sa.h:3333
agsaInterruptConfigPage_s::vectorMask0
bit32 vectorMask0
Definition: sa.h:3328
agsaInterruptConfigPage_s::ICTC2
bit32 ICTC2
Definition: sa.h:3332
agsaIoGeneralPage_s
Definition: sa.h:3339
agsaIoGeneralPage_s::pageCode
bit32 pageCode
Definition: sa.h:3340
agsaIoGeneralPage_s::QrntTime
bit32 QrntTime
Definition: sa.h:3342
agsaIoGeneralPage_s::ActiveMask
bit32 ActiveMask
Definition: sa.h:3341
agsaMPIContext_s
data structure for set fields in MPI table. The agsaMPIContext_t data structure is used to set fields...
Definition: sa.h:3433
agsaMPIContext_s::value
bit32 value
Definition: sa.h:3436
agsaMPIContext_s::MPITableType
bit32 MPITableType
Definition: sa.h:3434
agsaMPIContext_s::offset
bit32 offset
Definition: sa.h:3435
agsaMem_s
generic memory descriptor
Definition: sa.h:2464
agsaMem_s::phyAddrUpper
bit32 phyAddrUpper
Definition: sa.h:2467
agsaMem_s::reserved
bit32 reserved
Definition: sa.h:2475
agsaMem_s::singleElementLength
bit32 singleElementLength
Definition: sa.h:2471
agsaMem_s::virtPtr
void * virtPtr
Definition: sa.h:2465
agsaMem_s::osHandle
void * osHandle
Definition: sa.h:2466
agsaMem_s::alignment
bit32 alignment
Definition: sa.h:2472
agsaMem_s::numElements
bit32 numElements
Definition: sa.h:2470
agsaMem_s::phyAddrLower
bit32 phyAddrLower
Definition: sa.h:2468
agsaMem_s::type
bit32 type
Definition: sa.h:2474
agsaMem_s::totalLength
bit32 totalLength
Definition: sa.h:2469
agsaMemoryRequirement_s
specify the memory allocation requirement for the SAS/SATA LL Layer
Definition: sa.h:2534
agsaMemoryRequirement_s::count
bit32 count
Definition: sa.h:2535
agsaMemoryRequirement_s::agMemory
agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS]
Definition: sa.h:2537
agsaNVMDData_s
describe a NVMData for a Controller in the SAS/SATA hardware
Definition: sa.h:1936
agsaNVMDData_s::indirectLen
bit32 indirectLen
Definition: sa.h:1949
agsaNVMDData_s::indirectPayload
bit32 indirectPayload
Definition: sa.h:1937
agsaNVMDData_s::indirectAddrLower32
bit32 indirectAddrLower32
Definition: sa.h:1948
agsaNVMDData_s::dataOffsetAddress
bit32 dataOffsetAddress
Definition: sa.h:1945
agsaNVMDData_s::TWIBusNumber
bit32 TWIBusNumber
Definition: sa.h:1940
agsaNVMDData_s::directLen
bit32 directLen
Definition: sa.h:1944
agsaNVMDData_s::directData
void * directData
Definition: sa.h:1946
agsaNVMDData_s::TWIDevicePageSize
bit32 TWIDevicePageSize
Definition: sa.h:1941
agsaNVMDData_s::signature
bit32 signature
Definition: sa.h:1950
agsaNVMDData_s::TWIDeviceAddress
bit32 TWIDeviceAddress
Definition: sa.h:1939
agsaNVMDData_s::TWIDeviceAddressSize
bit32 TWIDeviceAddressSize
Definition: sa.h:1942
agsaNVMDData_s::NVMDevice
bit32 NVMDevice
Definition: sa.h:1943
agsaNVMDData_s::indirectAddrUpper32
bit32 indirectAddrUpper32
Definition: sa.h:1947
agsaNVMDData_s::reserved
bit32 reserved
Definition: sa.h:1938
agsaOffloadDifDetails_s
Definition: sa.h:3565
agsaOffloadDifDetails_s::ActualCRCUDT01
bit32 ActualCRCUDT01
Definition: sa.h:3568
agsaOffloadDifDetails_s::DIFErr
bit32 DIFErr
Definition: sa.h:3570
agsaOffloadDifDetails_s::ActualUDT2345
bit32 ActualUDT2345
Definition: sa.h:3569
agsaOffloadDifDetails_s::ExpectedUDT2345
bit32 ExpectedUDT2345
Definition: sa.h:3567
agsaOffloadDifDetails_s::ExpectedCRCUDT01
bit32 ExpectedCRCUDT01
Definition: sa.h:3566
agsaOffloadDifDetails_s::ErrBoffset
bit32 ErrBoffset
Definition: sa.h:3571
agsaPCIeDiagExecute_s
Definition: sa.h:1973
agsaPCIeDiagExecute_s::wrAddrUpper
bit32 wrAddrUpper
Definition: sa.h:1981
agsaPCIeDiagExecute_s::reserved
bit16 reserved
Definition: sa.h:1977
agsaPCIeDiagExecute_s::flags
bit32 flags
Definition: sa.h:1975
agsaPCIeDiagExecute_s::rdAddrLower
bit32 rdAddrLower
Definition: sa.h:1978
agsaPCIeDiagExecute_s::udrtArray
bit8 udrtArray[6]
Definition: sa.h:1985
agsaPCIeDiagExecute_s::initialIOSeed
bit16 initialIOSeed
Definition: sa.h:1976
agsaPCIeDiagExecute_s::udtArray
bit8 udtArray[6]
Definition: sa.h:1984
agsaPCIeDiagExecute_s::len
bit32 len
Definition: sa.h:1982
agsaPCIeDiagExecute_s::command
bit32 command
Definition: sa.h:1974
agsaPCIeDiagExecute_s::wrAddrLower
bit32 wrAddrLower
Definition: sa.h:1980
agsaPCIeDiagExecute_s::pattern
bit32 pattern
Definition: sa.h:1983
agsaPCIeDiagExecute_s::rdAddrUpper
bit32 rdAddrUpper
Definition: sa.h:1979
agsaPCIeDiagResponse_s
agsaPCIeDiagResponse_t
Definition: sa.h:1997
agsaPCIeDiagResponse_s::ERR_BLKL
bit32 ERR_BLKL
Definition: sa.h:1999
agsaPCIeDiagResponse_s::DIF_ERR
bit32 DIF_ERR
Definition: sa.h:2004
agsaPCIeDiagResponse_s::DWord9
bit32 DWord9
Definition: sa.h:2001
agsaPCIeDiagResponse_s::DWord10
bit32 DWord10
Definition: sa.h:2002
agsaPCIeDiagResponse_s::DWord11
bit32 DWord11
Definition: sa.h:2003
agsaPCIeDiagResponse_s::ERR_BLKH
bit32 ERR_BLKH
Definition: sa.h:1998
agsaPCIeDiagResponse_s::DWord8
bit32 DWord8
Definition: sa.h:2000
agsaPhyAnalogSettingsPage_s
describe a Phy Analog Setting
Definition: sa.h:1779
agsaPhyAnalogSettingsPage_s::Dword6
bit32 Dword6
Definition: sa.h:1786
agsaPhyAnalogSettingsPage_s::Dword1
bit32 Dword1
Definition: sa.h:1781
agsaPhyAnalogSettingsPage_s::Dword7
bit32 Dword7
Definition: sa.h:1787
agsaPhyAnalogSettingsPage_s::Dword8
bit32 Dword8
Definition: sa.h:1788
agsaPhyAnalogSettingsPage_s::Dword4
bit32 Dword4
Definition: sa.h:1784
agsaPhyAnalogSettingsPage_s::Dword9
bit32 Dword9
Definition: sa.h:1789
agsaPhyAnalogSettingsPage_s::Dword0
bit32 Dword0
Definition: sa.h:1780
agsaPhyAnalogSettingsPage_s::Dword5
bit32 Dword5
Definition: sa.h:1785
agsaPhyAnalogSettingsPage_s::Dword3
bit32 Dword3
Definition: sa.h:1783
agsaPhyAnalogSettingsPage_s::Dword2
bit32 Dword2
Definition: sa.h:1782
agsaPhyAnalogSetupRegisters_s
describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware
Definition: sa.h:1750
agsaPhyAnalogSetupRegisters_s::spaRegister9
bit32 spaRegister9
Definition: sa.h:1760
agsaPhyAnalogSetupRegisters_s::spaRegister7
bit32 spaRegister7
Definition: sa.h:1758
agsaPhyAnalogSetupRegisters_s::spaRegister0
bit32 spaRegister0
Definition: sa.h:1751
agsaPhyAnalogSetupRegisters_s::spaRegister3
bit32 spaRegister3
Definition: sa.h:1754
agsaPhyAnalogSetupRegisters_s::spaRegister1
bit32 spaRegister1
Definition: sa.h:1752
agsaPhyAnalogSetupRegisters_s::spaRegister2
bit32 spaRegister2
Definition: sa.h:1753
agsaPhyAnalogSetupRegisters_s::spaRegister6
bit32 spaRegister6
Definition: sa.h:1757
agsaPhyAnalogSetupRegisters_s::spaRegister5
bit32 spaRegister5
Definition: sa.h:1756
agsaPhyAnalogSetupRegisters_s::spaRegister4
bit32 spaRegister4
Definition: sa.h:1755
agsaPhyAnalogSetupRegisters_s::spaRegister8
bit32 spaRegister8
Definition: sa.h:1759
agsaPhyAnalogSetupTable_s
Definition: sa.h:1769
agsaPhyAnalogSetupTable_s::phyAnalogSetupRegisters
agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX]
Definition: sa.h:1770
agsaPhyBWCountersPage_s
structure describes bandwidth counters of a PHY in the SAS/SATA
Definition: sa.h:2287
agsaPhyBWCountersPage_s::RXBWCounter
bit32 RXBWCounter
Definition: sa.h:2289
agsaPhyBWCountersPage_s::TXBWCounter
bit32 TXBWCounter
Definition: sa.h:2288
agsaPhyCalibrationTbl_s
Definition: sa.h:2414
agsaPhyCalibrationTbl_s::rvConfig2
bit32 rvConfig2
Definition: sa.h:2422
agsaPhyCalibrationTbl_s::txPortConfig1
bit32 txPortConfig1
Definition: sa.h:2415
agsaPhyCalibrationTbl_s::rvPortConfig2
bit32 rvPortConfig2
Definition: sa.h:2420
agsaPhyCalibrationTbl_s::txConfig1
bit32 txConfig1
Definition: sa.h:2418
agsaPhyCalibrationTbl_s::txPortConfig2
bit32 txPortConfig2
Definition: sa.h:2416
agsaPhyCalibrationTbl_s::rvPortConfig1
bit32 rvPortConfig1
Definition: sa.h:2419
agsaPhyCalibrationTbl_s::rvConfig1
bit32 rvConfig1
Definition: sa.h:2421
agsaPhyCalibrationTbl_s::reserved
bit32 reserved[2]
Definition: sa.h:2423
agsaPhyCalibrationTbl_s::txPortConfig3
bit32 txPortConfig3
Definition: sa.h:2417
agsaPhyConfig_s
describe a configuration for a PHY in the SAS/SATA hardware
Definition: sa.h:2204
agsaPhyConfig_s::phyProperties
bit32 phyProperties
Definition: sa.h:2205
agsaPhyErrCountersPage_s
used in saGetPhyProfile
Definition: sa.h:2270
agsaPhyErrCountersPage_s::invalidDword
bit32 invalidDword
Definition: sa.h:2271
agsaPhyErrCountersPage_s::inboundCRCError
bit32 inboundCRCError
Definition: sa.h:2276
agsaPhyErrCountersPage_s::lossOfDwordSynch
bit32 lossOfDwordSynch
Definition: sa.h:2274
agsaPhyErrCountersPage_s::codeViolation
bit32 codeViolation
Definition: sa.h:2273
agsaPhyErrCountersPage_s::phyResetProblem
bit32 phyResetProblem
Definition: sa.h:2275
agsaPhyErrCountersPage_s::runningDisparityError
bit32 runningDisparityError
Definition: sa.h:2272
agsaPhyErrCounters_s
structure describe error counters of a PHY in the SAS/SATA
Definition: sa.h:2247
agsaPhyErrCounters_s::lossOfDwordSynch
bit32 lossOfDwordSynch
Definition: sa.h:2253
agsaPhyErrCounters_s::receivedErrorPrimitive
bit32 receivedErrorPrimitive
Definition: sa.h:2260
agsaPhyErrCounters_s::phyResetProblem
bit32 phyResetProblem
Definition: sa.h:2255
agsaPhyErrCounters_s::runningDisparityError
bit32 runningDisparityError
Definition: sa.h:2250
agsaPhyErrCounters_s::elasticityBufferOverflow
bit32 elasticityBufferOverflow
Definition: sa.h:2258
agsaPhyErrCounters_s::invalidDword
bit32 invalidDword
Definition: sa.h:2248
agsaPhyErrCounters_s::inboundCRCError
bit32 inboundCRCError
Definition: sa.h:2261
agsaPhyErrCounters_s::codeViolation
bit32 codeViolation
Definition: sa.h:2262
agsaPhyRateControlPage_s
describe a Phy Rate Control 4.56 agsaPhyRateControlPage_t Description This profile page is used to re...
Definition: sa.h:1820
agsaPhyRateControlPage_s::Dword0
bit32 Dword0
Definition: sa.h:1821
agsaPhyRateControlPage_s::Dword1
bit32 Dword1
Definition: sa.h:1822
agsaPhyRateControlPage_s::Dword2
bit32 Dword2
Definition: sa.h:1823
agsaPhySNW3Page_s
Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter.
Definition: sa.h:2235
agsaPhySNW3Page_s::RSNW3
bit32 RSNW3
Definition: sa.h:2237
agsaPhySNW3Page_s::LSNW3
bit32 LSNW3
Definition: sa.h:2236
agsaQueueConfig_s
Definition: sa.h:2427
agsaQueueConfig_s::outboundQueues
agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q]
Definition: sa.h:2441
agsaQueueConfig_s::tgtDeviceRemovedEventQueue
bit8 tgtDeviceRemovedEventQueue
Definition: sa.h:2438
agsaQueueConfig_s::tgtITNexusEventQueue
bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2432
agsaQueueConfig_s::inboundQueues
agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q]
Definition: sa.h:2440
agsaQueueConfig_s::iqNormalPriorityProcessingDepth
bit8 iqNormalPriorityProcessingDepth
Definition: sa.h:2435
agsaQueueConfig_s::sataNCQErrorEventQueue
bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2431
agsaQueueConfig_s::iqHighPriorityProcessingDepth
bit8 iqHighPriorityProcessingDepth
Definition: sa.h:2436
agsaQueueConfig_s::tgtSMPEventQueue
bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2434
agsaQueueConfig_s::tgtSSPEventQueue
bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2433
agsaQueueConfig_s::numInboundQueues
bit16 numInboundQueues
Definition: sa.h:2428
agsaQueueConfig_s::sasHwEventQueue
bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS]
Definition: sa.h:2430
agsaQueueConfig_s::queueOption
bit32 queueOption
Definition: sa.h:2439
agsaQueueConfig_s::numOutboundQueues
bit16 numOutboundQueues
Definition: sa.h:2429
agsaQueueConfig_s::generalEventQueue
bit8 generalEventQueue
Definition: sa.h:2437
agsaQueueInbound_s
Definition: sa.h:2376
agsaQueueInbound_s::elementCount
bit32 elementCount
Definition: sa.h:2377
agsaQueueInbound_s::elementSize
bit32 elementSize
Definition: sa.h:2379
agsaQueueInbound_s::reserved
bit32 reserved
Definition: sa.h:2385
agsaQueueInbound_s::priority
bit32 priority
Definition: sa.h:2380
agsaQueueOutbound_s
Definition: sa.h:2389
agsaQueueOutbound_s::elementCount
bit32 elementCount
Definition: sa.h:2390
agsaQueueOutbound_s::elementSize
bit32 elementSize
Definition: sa.h:2393
agsaQueueOutbound_s::reserved
bit32 reserved
Definition: sa.h:2409
agsaQueueOutbound_s::interruptCount
bit32 interruptCount
Definition: sa.h:2399
agsaQueueOutbound_s::interruptEnable
bit32 interruptEnable
Definition: sa.h:2407
agsaQueueOutbound_s::interruptVectorIndex
bit32 interruptVectorIndex
Definition: sa.h:2401
agsaQueueOutbound_s::interruptDelay
bit32 interruptDelay
Definition: sa.h:2394
agsaRegDumpInfo_s
describe a Register Dump information for a Controller in the SAS/SATA hardware
Definition: sa.h:1846
agsaRegDumpInfo_s::directLen
bit32 directLen
Definition: sa.h:1851
agsaRegDumpInfo_s::regDumpOffset
bit32 regDumpOffset
Definition: sa.h:1850
agsaRegDumpInfo_s::indirectAddrLower32
bit32 indirectAddrLower32
Definition: sa.h:1854
agsaRegDumpInfo_s::regDumpNum
bit8 regDumpNum
Definition: sa.h:1848
agsaRegDumpInfo_s::reserved
bit8 reserved[2]
Definition: sa.h:1849
agsaRegDumpInfo_s::indirectAddrUpper32
bit32 indirectAddrUpper32
Definition: sa.h:1853
agsaRegDumpInfo_s::directData
void * directData
Definition: sa.h:1852
agsaRegDumpInfo_s::indirectLen
bit32 indirectLen
Definition: sa.h:1855
agsaRegDumpInfo_s::regDumpSrc
bit8 regDumpSrc
Definition: sa.h:1847
agsaSASAddressID_s
describe a SAS address and PHY Identifier
Definition: sa.h:2548
agsaSASAddressID_s::phyIdentifier
bit8 phyIdentifier
Definition: sa.h:2551
agsaSASAddressID_s::sasAddressLo
bit8 sasAddressLo[4]
Definition: sa.h:2549
agsaSASAddressID_s::sasAddressHi
bit8 sasAddressHi[4]
Definition: sa.h:2550
agsaSASDeviceInfo_s
data structure provides some information about a SAS device
Definition: sa.h:2682
agsaSASDeviceInfo_s::commonDevInfo
agsaDeviceInfo_t commonDevInfo
Definition: sa.h:2683
agsaSASDeviceInfo_s::phyIdentifier
bit8 phyIdentifier
Definition: sa.h:2698
agsaSASDeviceInfo_s::numOfPhys
bit32 numOfPhys
Definition: sa.h:2697
agsaSASDeviceInfo_s::target_ssp_stp_smp
bit8 target_ssp_stp_smp
Definition: sa.h:2691
agsaSASDeviceInfo_s::initiator_ssp_stp_smp
bit8 initiator_ssp_stp_smp
Definition: sa.h:2685
agsaSASDiagExecute_s
specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer
Definition: sa.h:2505
agsaSASDiagExecute_s::param5
bit32 param5
Definition: sa.h:2512
agsaSASDiagExecute_s::param2
bit32 param2
Definition: sa.h:2509
agsaSASDiagExecute_s::param0
bit32 param0
Definition: sa.h:2507
agsaSASDiagExecute_s::param3
bit32 param3
Definition: sa.h:2510
agsaSASDiagExecute_s::param1
bit32 param1
Definition: sa.h:2508
agsaSASDiagExecute_s::param4
bit32 param4
Definition: sa.h:2511
agsaSASDiagExecute_s::command
bit32 command
Definition: sa.h:2506
agsaSASPhyGeneralStatusPage_s
for the SAS/SATA LL Layer
Definition: sa.h:2522
agsaSASPhyGeneralStatusPage_s::Dword1
bit32 Dword1
Definition: sa.h:2524
agsaSASPhyGeneralStatusPage_s::Dword0
bit32 Dword0
Definition: sa.h:2523
agsaSASPhyMiscPage_s
Definition: sa.h:3301
agsaSASPhyMiscPage_s::Dword0
bit32 Dword0
Definition: sa.h:3302
agsaSASPhyMiscPage_s::Dword1
bit32 Dword1
Definition: sa.h:3303
agsaSASPhyOpenRejectRetryBackOffThresholdPage_s
describe a Open reject retry backoff threshold page
Definition: sa.h:1799
agsaSASPhyOpenRejectRetryBackOffThresholdPage_s::Dword3
bit32 Dword3
Definition: sa.h:1803
agsaSASPhyOpenRejectRetryBackOffThresholdPage_s::Dword0
bit32 Dword0
Definition: sa.h:1800
agsaSASPhyOpenRejectRetryBackOffThresholdPage_s::Dword2
bit32 Dword2
Definition: sa.h:1802
agsaSASPhyOpenRejectRetryBackOffThresholdPage_s::Dword1
bit32 Dword1
Definition: sa.h:1801
agsaSASProtocolTimerConfigurationPage_s
data structure for SAS protocol timer configuration page.
Definition: sa.h:3373
agsaSASProtocolTimerConfigurationPage_s::Data_Cmd_OPNRJT_RTRY_TMO
bit32 Data_Cmd_OPNRJT_RTRY_TMO
Definition: sa.h:3380
agsaSASProtocolTimerConfigurationPage_s::STP_IDLE_TMO
bit32 STP_IDLE_TMO
Definition: sa.h:3378
agsaSASProtocolTimerConfigurationPage_s::STP_FRM_TMO
bit32 STP_FRM_TMO
Definition: sa.h:3377
agsaSASProtocolTimerConfigurationPage_s::pageCode
bit32 pageCode
Definition: sa.h:3374
agsaSASProtocolTimerConfigurationPage_s::MST_MSI
bit32 MST_MSI
Definition: sa.h:3375
agsaSASProtocolTimerConfigurationPage_s::STP_SSP_MCT_TMO
bit32 STP_SSP_MCT_TMO
Definition: sa.h:3376
agsaSASProtocolTimerConfigurationPage_s::MAX_AIP
bit32 MAX_AIP
Definition: sa.h:3382
agsaSASProtocolTimerConfigurationPage_s::OPNRJT_RTRY_INTVL
bit32 OPNRJT_RTRY_INTVL
Definition: sa.h:3379
agsaSASProtocolTimerConfigurationPage_s::Data_Cmd_OPNRJT_RTRY_THR
bit32 Data_Cmd_OPNRJT_RTRY_THR
Definition: sa.h:3381
agsaSASReconfig_s
describe a SAS ReCofiguration structure in the SAS/SATA hardware
Definition: sa.h:1726
agsaSASReconfig_s::reserved2
bit16 reserved2
Definition: sa.h:1740
agsaSASReconfig_s::reserved1
bit8 reserved1
Definition: sa.h:1736
agsaSASReconfig_s::flags
bit32 flags
Definition: sa.h:1727
agsaSASReconfig_s::reserved0
bit16 reserved0
Definition: sa.h:1735
agsaSASReconfig_s::maxPorts
bit8 maxPorts
Definition: sa.h:1737
agsaSASReconfig_s::sataHolTmo
bit16 sataHolTmo
Definition: sa.h:1741
agsaSASReconfig_s::openRejectRetriesData
bit16 openRejectRetriesData
Definition: sa.h:1739
agsaSASReconfig_s::openRejectRetriesCmd
bit16 openRejectRetriesCmd
Definition: sa.h:1738
agsaSATADeviceInfo_s
data structure provides some information about a SATA device
Definition: sa.h:2649
agsaSATADeviceInfo_s::connection
bit8 connection
Definition: sa.h:2652
agsaSATADeviceInfo_s::commonDevInfo
agsaDeviceInfo_t commonDevInfo
Definition: sa.h:2650
agsaSATADeviceInfo_s::stpPhyIdentifier
bit8 stpPhyIdentifier
Definition: sa.h:2664
agsaSATADeviceInfo_s::signature
bit8 signature[8]
Definition: sa.h:2668
agsaSATADeviceInfo_s::reserved
bit8 reserved
Definition: sa.h:2667
agsaSATADeviceInfo_s::portMultiplierField
bit8 portMultiplierField
Definition: sa.h:2658
agsaSATAInitiatorRequest_s
data structure describes an STP or direct connect SATA command
Definition: sa.h:3129
agsaSATAInitiatorRequest_s::option
bit32 option
Definition: sa.h:3136
agsaSATAInitiatorRequest_s::dataLength
bit32 dataLength
Definition: sa.h:3134
agsaSATAInitiatorRequest_s::agSgl
agsaSgl_t agSgl
Definition: sa.h:3130
agsaSATAInitiatorRequest_s::dif
agsaDif_t dif
Definition: sa.h:3141
agsaSATAInitiatorRequest_s::scsiCDB
bit8 scsiCDB[16]
Definition: sa.h:3143
agsaSATAInitiatorRequest_s::fis
agsaSATAHostFis_t fis
Definition: sa.h:3140
agsaSATAInitiatorRequest_s::encrypt
agsaEncrypt_t encrypt
Definition: sa.h:3142
agsaSGpioCfg0
describe a serial GPIO operation response in the SAS/SATA hardware
Definition: sa.h:2173
agsaSGpioCfg0::reserved1
bit8 reserved1
Definition: sa.h:2174
agsaSGpioCfg0::gpioEnable
bit8 gpioEnable
Definition: sa.h:2179
agsaSGpioCfg0::gpRegisterCount
bit8 gpRegisterCount
Definition: sa.h:2177
agsaSGpioCfg0::cfgRegisterCount
bit8 cfgRegisterCount
Definition: sa.h:2178
agsaSGpioCfg0::reserved2
bit8 reserved2
Definition: sa.h:2176
agsaSGpioCfg0::supportedDriveCount
bit8 supportedDriveCount
Definition: sa.h:2180
agsaSGpioCfg0::version
bit8 version
Definition: sa.h:2175
agsaSGpioCfg1
SGPIO configuration register 1.
Definition: sa.h:2188
agsaSGpioCfg1::forceActOff
bit8 forceActOff
Definition: sa.h:2193
agsaSGpioCfg1::blinkGenA
bit8 blinkGenA
Definition: sa.h:2190
agsaSGpioCfg1::reserved
bit8 reserved
Definition: sa.h:2189
agsaSGpioCfg1::stretchActOff
bit8 stretchActOff
Definition: sa.h:2195
agsaSGpioCfg1::maxActOn
bit8 maxActOn
Definition: sa.h:2192
agsaSGpioCfg1::blinkGenB
bit8 blinkGenB
Definition: sa.h:2191
agsaSGpioCfg1::stretchActOn
bit8 stretchActOn
Definition: sa.h:2194
agsaSGpioReqResponse_s
describe a serial GPIO request and response in the SAS/SATA hardware
Definition: sa.h:2156
agsaSGpioReqResponse_s::readWriteData
bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]
Definition: sa.h:2163
agsaSGpioReqResponse_s::registerType
bit8 registerType
Definition: sa.h:2159
agsaSGpioReqResponse_s::registerCount
bit8 registerCount
Definition: sa.h:2161
agsaSGpioReqResponse_s::functionResult
bit8 functionResult
Definition: sa.h:2162
agsaSGpioReqResponse_s::registerIndex
bit8 registerIndex
Definition: sa.h:2160
agsaSGpioReqResponse_s::smpFrameType
bit8 smpFrameType
Definition: sa.h:2157
agsaSGpioReqResponse_s::function
bit8 function
Definition: sa.h:2158
agsaSMPFrame_s
data structure describes a SMP request or response frame to be sent on the SAS port
Definition: sa.h:3057
agsaSMPFrame_s::inFrameAddrLower32
bit32 inFrameAddrLower32
Definition: sa.h:3070
agsaSMPFrame_s::inFrameLen
bit32 inFrameLen
Definition: sa.h:3072
agsaSMPFrame_s::flag
bit32 flag
Definition: sa.h:3075
agsaSMPFrame_s::outFrameBuf
void * outFrameBuf
Definition: sa.h:3058
agsaSMPFrame_s::inFrameAddrUpper32
bit32 inFrameAddrUpper32
Definition: sa.h:3068
agsaSMPFrame_s::outFrameAddrLower32
bit32 outFrameAddrLower32
Definition: sa.h:3064
agsaSMPFrame_s::expectedRespLen
bit32 expectedRespLen
Definition: sa.h:3074
agsaSMPFrame_s::outFrameLen
bit32 outFrameLen
Definition: sa.h:3066
agsaSMPFrame_s::outFrameAddrUpper32
bit32 outFrameAddrUpper32
Definition: sa.h:3062
agsaSSPCmdInfoUnitExt_s
Definition: sa.h:2791
agsaSSPCmdInfoUnitExt_s::efb_tp_taskAttribute
bit8 efb_tp_taskAttribute
Definition: sa.h:2794
agsaSSPCmdInfoUnitExt_s::reserved1
bit8 reserved1
Definition: sa.h:2793
agsaSSPCmdInfoUnitExt_s::additionalCdbLen
bit8 additionalCdbLen
Definition: sa.h:2796
agsaSSPCmdInfoUnitExt_s::lun
bit8 lun[8]
Definition: sa.h:2792
agsaSSPCmdInfoUnitExt_s::cdb
bit8 cdb[MAX_CDB_LEN]
Definition: sa.h:2797
agsaSSPCmdInfoUnitExt_s::reserved2
bit8 reserved2
Definition: sa.h:2795
agsaSSPCmdInfoUnit_s
data structure describes an SSP Command INFORMATION UNIT
Definition: sa_spec.h:793
agsaSSPInitiatorRequestExt_s
data structure describes a SAS SSP command request Ext to be sent to the target device
Definition: sa.h:2922
agsaSSPInitiatorRequestExt_s::dataLength
bit32 dataLength
Definition: sa.h:2926
agsaSSPInitiatorRequestExt_s::firstBurstSize
bit16 firstBurstSize
Definition: sa.h:2927
agsaSSPInitiatorRequestExt_s::flag
bit16 flag
Definition: sa.h:2928
agsaSSPInitiatorRequestExt_s::sspCmdIUExt
agsaSSPCmdInfoUnitExt_t sspCmdIUExt
Definition: sa.h:2929
agsaSSPInitiatorRequestExt_s::encrypt
agsaEncrypt_t encrypt
Definition: sa.h:2931
agsaSSPInitiatorRequestExt_s::dif
agsaDif_t dif
Definition: sa.h:2930
agsaSSPInitiatorRequestExt_s::agSgl
agsaSgl_t agSgl
Definition: sa.h:2923
agsaSSPInitiatorRequestIndirect_s
Definition: sa.h:2936
agsaSSPInitiatorRequestIndirect_s::sspInitiatorReqAddrLower32
bit32 sspInitiatorReqAddrLower32
Definition: sa.h:2944
agsaSSPInitiatorRequestIndirect_s::firstBurstSize
bit16 firstBurstSize
Definition: sa.h:2941
agsaSSPInitiatorRequestIndirect_s::flag
bit16 flag
Definition: sa.h:2942
agsaSSPInitiatorRequestIndirect_s::dif
agsaDif_t dif
Definition: sa.h:2946
agsaSSPInitiatorRequestIndirect_s::sspInitiatorReqAddrUpper32
bit32 sspInitiatorReqAddrUpper32
Definition: sa.h:2943
agsaSSPInitiatorRequestIndirect_s::sspInitiatorReqLen
bit32 sspInitiatorReqLen
Definition: sa.h:2945
agsaSSPInitiatorRequestIndirect_s::dataLength
bit32 dataLength
Definition: sa.h:2940
agsaSSPInitiatorRequestIndirect_s::encrypt
agsaEncrypt_t encrypt
Definition: sa.h:2947
agsaSSPInitiatorRequestIndirect_s::agSgl
agsaSgl_t agSgl
Definition: sa.h:2937
agsaSSPInitiatorRequest_s
data structure describes a SAS SSP command request to be sent to the target device
Definition: sa.h:2892
agsaSSPInitiatorRequest_s::agSgl
agsaSgl_t agSgl
Definition: sa.h:2893
agsaSSPInitiatorRequest_s::encrypt
agsaEncrypt_t encrypt
Definition: sa.h:2904
agsaSSPInitiatorRequest_s::dif
agsaDif_t dif
Definition: sa.h:2903
agsaSSPInitiatorRequest_s::sspCmdIU
agsaSSPCmdInfoUnit_t sspCmdIU
Definition: sa.h:2901
agsaSSPInitiatorRequest_s::firstBurstSize
bit16 firstBurstSize
Definition: sa.h:2897
agsaSSPInitiatorRequest_s::dataLength
bit32 dataLength
Definition: sa.h:2896
agsaSSPInitiatorRequest_s::flag
bit16 flag
Definition: sa.h:2899
agsaSSPScsiTaskMgntReq_s
structure describes a SAS SSP Task Management command request
Definition: sa_spec.h:898
agsaSSPTargetRequest_s
data structure describes a SAS SSP target read and write request
Definition: sa.h:2986
agsaSSPTargetRequest_s::dataLength
bit32 dataLength
Definition: sa.h:2989
agsaSSPTargetRequest_s::sspOption
bit16 sspOption
Definition: sa.h:2993
agsaSSPTargetRequest_s::agSgl
agsaSgl_t agSgl
Definition: sa.h:2987
agsaSSPTargetRequest_s::offset
bit32 offset
Definition: sa.h:2990
agsaSSPTargetRequest_s::dif
agsaDif_t dif
Definition: sa.h:2994
agsaSSPTargetRequest_s::agTag
bit16 agTag
Definition: sa.h:2992
agsaSSPTargetResponse_s
data structure describes a SAS SSP target response to be issued on the port
Definition: sa.h:3025
agsaSSPTargetResponse_s::respOption
bit32 respOption
Definition: sa.h:3037
agsaSSPTargetResponse_s::respBufLength
bit32 respBufLength
Definition: sa.h:3028
agsaSSPTargetResponse_s::frameBuf
void * frameBuf
Definition: sa.h:3027
agsaSSPTargetResponse_s::agTag
bit32 agTag
Definition: sa.h:3026
agsaSSPTargetResponse_s::respBufUpper
bit32 respBufUpper
Definition: sa.h:3029
agsaSSPTargetResponse_s::respBufLower
bit32 respBufLower
Definition: sa.h:3033
agsaSgl_s
data structure used to pass information about the scatter-gather list to the LL Layer
Definition: sa.h:2755
agsaSgl_s::len
bit32 len
Definition: sa.h:2758
agsaSgl_s::sgLower
bit32 sgLower
Definition: sa.h:2756
agsaSgl_s::sgUpper
bit32 sgUpper
Definition: sa.h:2757
agsaSgl_s::extReserved
bit32 extReserved
Definition: sa.h:2759
agsaSwConfig_s
structure describe software configuration
Definition: sa.h:2319
agsaSwConfig_s::eventLog1Option
bit32 eventLog1Option
Definition: sa.h:2328
agsaSwConfig_s::smpReqTimeout
bit32 smpReqTimeout
Definition: sa.h:2323
agsaSwConfig_s::max_MSI_InterruptVectors
bit32 max_MSI_InterruptVectors
Definition: sa.h:2334
agsaSwConfig_s::sgpioSupportEnable
bit32 sgpioSupportEnable
Definition: sa.h:2332
agsaSwConfig_s::enableDIF
bit32 enableDIF
Definition: sa.h:2339
agsaSwConfig_s::fatalErrorInterruptEnable
bit32 fatalErrorInterruptEnable
Definition: sa.h:2331
agsaSwConfig_s::disableMDF
bit32 disableMDF
Definition: sa.h:2342
agsaSwConfig_s::legacyInt_X
bit32 legacyInt_X
Definition: sa.h:2336
agsaSwConfig_s::mpiContextTable
void * mpiContextTable
Definition: sa.h:2351
agsaSwConfig_s::eventLog2Option
bit32 eventLog2Option
Definition: sa.h:2329
agsaSwConfig_s::maxActiveIOs
bit32 maxActiveIOs
Definition: sa.h:2320
agsaSwConfig_s::param2
bit32 param2
Definition: sa.h:2345
agsaSwConfig_s::param4
void * param4
Definition: sa.h:2347
agsaSwConfig_s::sizefEventLog2
bit32 sizefEventLog2
Definition: sa.h:2327
agsaSwConfig_s::enableEncryption
bit32 enableEncryption
Definition: sa.h:2340
agsaSwConfig_s::numDevHandles
bit32 numDevHandles
Definition: sa.h:2321
agsaSwConfig_s::stallUsec
bit32 stallUsec
Definition: sa.h:2348
agsaSwConfig_s::sizefEventLog1
bit32 sizefEventLog1
Definition: sa.h:2326
agsaSwConfig_s::PortRecoveryResetTimer
bit32 PortRecoveryResetTimer
Definition: sa.h:2350
agsaSwConfig_s::mpiContextTablelen
bit32 mpiContextTablelen
Definition: sa.h:2357
agsaSwConfig_s::param1
bit32 param1
Definition: sa.h:2344
agsaSwConfig_s::param3
void * param3
Definition: sa.h:2346
agsaSwConfig_s::hostDirectAccessMode
bit32 hostDirectAccessMode
Definition: sa.h:2338
agsaSwConfig_s::max_MSIX_InterruptVectors
bit32 max_MSIX_InterruptVectors
Definition: sa.h:2335
agsaSwConfig_s::hostDirectAccessSupport
bit32 hostDirectAccessSupport
Definition: sa.h:2337
agsaSwConfig_s::fatalErrorInterruptVector
bit32 fatalErrorInterruptVector
Definition: sa.h:2333
agsaSwConfig_s::FWConfig
bit32 FWConfig
Definition: sa.h:2349
agsaSwConfig_s::numberOfEventRegClients
bit32 numberOfEventRegClients
Definition: sa.h:2324
agsaUpdateFwFlash_s
data structure for firmware flash update saFwFlashUpdate().
Definition: sa.h:3391
agsaUpdateFwFlash_s::currentImageLen
bit32 currentImageLen
Definition: sa.h:3393
agsaUpdateFwFlash_s::currentImageOffset
bit32 currentImageOffset
Definition: sa.h:3392
agsaUpdateFwFlash_s::agSgl
agsaSgl_t agSgl
Definition: sa.h:3395
agsaUpdateFwFlash_s::totalImageLen
bit32 totalImageLen
Definition: sa.h:3394
agsaSASRequestBody_u
union data structure specifies a request
Definition: sa.h:3104
agsaSASRequestBody_u::sspTargetResponse
agsaSSPTargetResponse_t sspTargetResponse
Definition: sa.h:3110
agsaSASRequestBody_u::sspInitiatorReq
agsaSSPInitiatorRequest_t sspInitiatorReq
Definition: sa.h:3105
agsaSASRequestBody_u::sspInitiatorReqExt
agsaSSPInitiatorRequestExt_t sspInitiatorReqExt
Definition: sa.h:3106
agsaSASRequestBody_u::sspInitiatorReqIndirect
agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect
Definition: sa.h:3107
agsaSASRequestBody_u::smpFrame
agsaSMPFrame_t smpFrame
Definition: sa.h:3111
agsaSASRequestBody_u::sspTargetReq
agsaSSPTargetRequest_t sspTargetReq
Definition: sa.h:3108
agsaSASRequestBody_u::sspTaskMgntReq
agsaSSPScsiTaskMgntReq_t sspTaskMgntReq
Definition: sa.h:3109
agsaSATAHostFis_u
union data structure specifies a FIS from host software
Definition: sa_spec.h:396
agsabit32bit64_U
Definition: sa.h:3627
agsabit32bit64_U::B64
bit64 B64
Definition: sa.h:3629