38#include <sys/condvar.h>
39#include <sys/kernel.h>
40#include <sys/module.h>
42#include <machine/bus.h>
44#include <dev/fdt/simplebus.h>
46#include <dev/fdt/fdt_common.h>
47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49#include <dev/ofw/ofw_subr.h>
63#include <dev/extres/clk/clk.h>
64#include <dev/extres/phy/phy_usb.h>
79 bus_space_handle_t
bsh;
85#define DWC3_WRITE(_sc, _off, _val) \
86 bus_space_write_4(_sc->bst, _sc->bsh, _off, _val)
87#define DWC3_READ(_sc, _off) \
88 bus_space_read_4(_sc->bst, _sc->bsh, _off)
103 RF_SHAREABLE | RF_ACTIVE);
105 device_printf(
dev,
"Failed to allocate IRQ\n");
111 device_printf(
dev,
"Failed to add USB device\n");
120 err = bus_setup_intr(
dev, sc->
sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
123 device_printf(
dev,
"Failed to setup IRQ, %d\n", err);
130 device_printf(
dev,
"Failed to init XHCI, with error %d\n", err);
136 device_printf(
dev,
"Failed to start XHCI controller, with error %d\n", err);
140 device_printf(sc->
sc_bus.
bdev,
"trying to attach\n");
141 err = device_probe_and_attach(sc->
sc_bus.
bdev);
143 device_printf(
dev,
"Failed to initialize USB, with error %d\n", err);
157 device_printf(sc->
dev,
"GCTL: %x\n",
reg);
159 device_printf(sc->
dev,
"GUCTL1: %x\n",
reg);
161 device_printf(sc->
dev,
"GUSB2PHYCFG0: %x\n",
reg);
163 device_printf(sc->
dev,
"GUSB3PIPECTL0: %x\n",
reg);
165 device_printf(sc->
dev,
"DCFG: %x\n",
reg);
172 uint32_t gctl, phy2, phy3;
193 phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST;
196 phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST;
199 gctl &= ~DWC3_GCTL_CORESOFTRESET;
210 reg &= ~DWC3_GCTL_PRTCAPDIR_MASK;
223 nphy_types = OF_getprop_alloc(sc->
node,
"phy_type", (
void **)&phy_type);
228 if (strncmp(phy_type,
"utmi_wide", 9) == 0) {
238 OF_prop_free(phy_type);
247 if (OF_hasprop(sc->
node,
"snps,dis-u2-freeclk-exists-quirk"))
248 reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS;
251 if (OF_hasprop(sc->
node,
"snps,dis_u2_susphy_quirk"))
252 reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20;
255 if (OF_hasprop(sc->
node,
"snps,dis_enblslpm_quirk"))
256 reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM;
263 if (OF_hasprop(sc->
node,
"snps,dis-tx-ipgap-linecheck-quirk"))
268 if (OF_hasprop(sc->
node,
"snps,dis-del-phy-power-chg-quirk"))
270 if (OF_hasprop(sc->
node,
"snps,dis_rxdet_inp3_quirk"))
281 if (!ofw_bus_status_okay(
dev))
287 sc = device_get_softc(
dev);
288 sc->node = ofw_bus_get_node(
dev);
289 OF_getprop(
sc->node,
"dr_mode",
sc->dr_mode,
sizeof(
sc->dr_mode));
290 if (strcmp(
sc->dr_mode,
"host") != 0) {
291 device_printf(
dev,
"Only host mode is supported\n");
295 device_set_desc(
dev,
"Synopsys Designware DWC3");
296 return (BUS_PROBE_DEFAULT);
305 sc = device_get_softc(
dev);
308 sc->mem_res = bus_alloc_resource_any(
dev, SYS_RES_MEMORY, &
rid,
310 if (
sc->mem_res == NULL) {
311 device_printf(
dev,
"Failed to map memory\n");
314 sc->bst = rman_get_bustag(
sc->mem_res);
315 sc->bsh = rman_get_bushandle(
sc->mem_res);
321 phy_get_by_ofw_name(
dev,
sc->node,
"usb2-phy", &
sc->usb2_phy);
322 phy_get_by_ofw_name(
dev,
sc->node,
"usb3-phy", &
sc->usb3_phy);
329 snsp_dwc3_dump_regs(
sc);
MODULE_DEPEND(snps_dwc3, xhci, 1, 1, 1)
static void snps_dwc3_do_quirks(struct snps_dwc3_softc *sc)
static void snps_dwc3_configure_phy(struct snps_dwc3_softc *sc)
static void snps_dwc3_configure_host(struct snps_dwc3_softc *sc)
static devclass_t snps_dwc3_devclass
static driver_t snps_dwc3_driver
static void snps_dwc3_reset(struct snps_dwc3_softc *sc)
static int snps_dwc3_probe(device_t dev)
static device_method_t snps_dwc3_methods[]
static struct ofw_compat_data compat_data[]
static int snps_dwc3_attach(device_t dev)
static int snps_dwc3_attach_xhci(device_t dev)
#define DWC3_READ(_sc, _off)
DRIVER_MODULE(snps_dwc3, simplebus, snps_dwc3_driver, snps_dwc3_devclass, 0, 0)
#define DWC3_WRITE(_sc, _off, _val)
#define DWC3_GUSB2PHYCFG0_USBTRDTIM(n)
#define DWC3_GUSB3PIPECTL0_DELAYP1TRANS
#define DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS
#define DWC3_GCTL_PRTCAPDIR_HOST
#define DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS
#define DWC3_GUSB2PHYCFG0_PHYIF
#define DWC3_GUSB2PHYCFG0_SUSPENDUSB20
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS
#define DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS
#define DWC3_GUSB3PIPECTL0_PHYSOFTRST
#define DWC3_GCTL_CORESOFTRESET
#define DWC3_GUSB2PHYCFG0
#define DWC3_GUSB2PHYCFG0_ENBLSLPM
#define DWC3_GUSB2PHYCFG0_PHYSOFTRST
#define DWC3_GUSB3PIPECTL0_DISRXDETINP3
#define DWC3_GUSB3PIPECTL0
struct resource * mem_res
bus_space_tag_t sc_io_tag
struct resource * sc_io_res
bus_space_handle_t sc_io_hdl
struct resource * sc_irq_res
usb_error_t xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
usb_error_t xhci_start_controller(struct xhci_softc *sc)
void xhci_interrupt(struct xhci_softc *sc)