45#ifdef USB_GLOBAL_INCLUDE_FILE
46#include USB_GLOBAL_INCLUDE_FILE
48#include <sys/stdint.h>
49#include <sys/stddef.h>
54#include <sys/kernel.h>
56#include <sys/module.h>
59#include <sys/condvar.h>
60#include <sys/sysctl.h>
62#include <sys/unistd.h>
63#include <sys/callout.h>
64#include <sys/malloc.h>
70#define USB_DEBUG_VAR xhcidebug
88#define XHCI_BUS2SC(bus) \
89 __containerof(bus, struct xhci_softc, sc_bus)
91#define XHCI_GET_CTX(sc, which, field, ptr) \
92 ((sc)->sc_ctx_is_64_byte ? \
93 &((struct which##64 *)(ptr))->field.ctx : \
94 &((struct which *)(ptr))->field)
96static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
101 &
xhcistreams, 0,
"Set to enable streams mode support");
105 &
xhcictlquirk, 0,
"Set to enable control endpoint quirk");
109 &
xhcidcepquirk, 0,
"Set to disable endpoint deconfigure command");
114static int xhcipolling;
119 &xhcidebug, 0,
"Debug level");
120SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
121 &
xhciroute, 0,
"Routing bitmap for switching EHCI ports to the XHCI controller");
122SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
123 &xhcipolling, 0,
"Set to enable software interrupt polling for the XHCI controller");
124SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
125 &
xhcidma32, 0,
"Set to only use 32-bit DMA for the XHCI controller");
126SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
127 &
xhcictlstep, 0,
"Set to enable control endpoint status stage stepping");
134#define XHCI_INTR_ENDPT 1
168 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
182 DPRINTFN(5,
"trb = %p\n", trb);
183 DPRINTFN(5,
"qwTrb0 = 0x%016llx\n", (
long long)le64toh(trb->
qwTrb0));
184 DPRINTFN(5,
"dwTrb2 = 0x%08x\n", le32toh(trb->
dwTrb2));
185 DPRINTFN(5,
"dwTrb3 = 0x%08x\n", le32toh(trb->
dwTrb3));
191 DPRINTFN(5,
"pep = %p\n", pep);
192 DPRINTFN(5,
"dwEpCtx0=0x%08x\n", le32toh(pep->
dwEpCtx0));
193 DPRINTFN(5,
"dwEpCtx1=0x%08x\n", le32toh(pep->
dwEpCtx1));
194 DPRINTFN(5,
"qwEpCtx2=0x%016llx\n", (
long long)le64toh(pep->
qwEpCtx2));
195 DPRINTFN(5,
"dwEpCtx4=0x%08x\n", le32toh(pep->
dwEpCtx4));
196 DPRINTFN(5,
"dwEpCtx5=0x%08x\n", le32toh(pep->
dwEpCtx5));
197 DPRINTFN(5,
"dwEpCtx6=0x%08x\n", le32toh(pep->
dwEpCtx6));
198 DPRINTFN(5,
"dwEpCtx7=0x%08x\n", le32toh(pep->
dwEpCtx7));
204 DPRINTFN(5,
"psl = %p\n", psl);
205 DPRINTFN(5,
"dwSctx0=0x%08x\n", le32toh(psl->
dwSctx0));
206 DPRINTFN(5,
"dwSctx1=0x%08x\n", le32toh(psl->
dwSctx1));
207 DPRINTFN(5,
"dwSctx2=0x%08x\n", le32toh(psl->
dwSctx2));
208 DPRINTFN(5,
"dwSctx3=0x%08x\n", le32toh(psl->
dwSctx3));
216 return (xhcipolling != 0);
252 DPRINTF(
"Command ring running\n");
274 DPRINTF(
"Comand ring still running\n");
286 addr = buf_res.physaddr;
290 DPRINTF(
"CRCR=0x%016llx\n", (
unsigned long long)
addr);
326 DPRINTF(
"CONFIG=0x%08x -> 0x%08x\n",
341 memset(pdctxa, 0,
sizeof(*pdctxa));
343 addr = buf_res.physaddr;
352 pdctxa->
qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
355 addr = buf_res.physaddr;
363 DPRINTF(
"ERSTSZ=0x%08x -> 0x%08x\n",
374 addr = buf_res.physaddr;
378 memset(phwr, 0,
sizeof(*phwr));
396 DPRINTF(
"ERDP(0)=0x%016llx\n", (
unsigned long long)
addr);
401 addr = buf_res.physaddr;
403 DPRINTF(
"ERSTBA(0)=0x%016llx\n", (
unsigned long long)
addr);
414 addr = buf_res.physaddr;
417 DPRINTF(
"CRCR=0x%016llx\n", (
unsigned long long)
addr);
430 for (i = 0; i != 100; i++) {
469 for (i = 0; i != 100; i++) {
477 device_printf(sc->
sc_bus.
parent,
"Controller halt timeout.\n");
494 for (i = 0; i != 100; i++) {
548 "not support 4K page size.\n");
554 DPRINTF(
"HCS0 = 0x%08x\n", temp);
567 device_printf(self,
"%d bytes context size, %d-bit DMA\n",
594 DPRINTF(
"HCS2=0x%08x\n", temp);
604 "too many scratchpads\n");
665 DPRINTF(
"Stopping the XHCI\n");
670 DPRINTF(
"Stopping the XHCI\n");
675 DPRINTF(
"Starting the XHCI\n");
703 DPRINTFN(4,
"xfer=%p[%u/%u] rem=%u/%u status=%u\n",
704 xfer, (
unsigned int)xfer->
aframes,
706 (
unsigned int)
len, (
unsigned int)td->
len,
715 DPRINTF(
"Invalid status length, "
716 "0x%04x/0x%04x bytes\n",
len, td->
len);
748 if (td->alt_next != td_alt_next) {
769 DPRINTFN(13,
"xfer=%p endpoint=%p transfer done\n",
861 uint16_t stream_id = 0;
883 DPRINTF(
"slot=%u epno=%u remainder=%u status=%u\n",
892 DPRINTF(
"Invalid endpoint.\n");
905 stream_id == (XHCI_MAX_STREAMS - 1))
909 DPRINTFN(5,
"stream_id=%u\n", stream_id);
918 DPRINTFN(5,
"Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
940 for (i = (
offset / 16) + 1; i < td->
ntrb; i++) {
945 DPRINTFN(5,
"New remainder: %u\n",
remainder);
986 if (td->remainder > 0) {
987 if (td->alt_next == NULL) {
989 "short TD has no alternate next\n");
1010 DPRINTF(
"Following next TD\n");
1022 DPRINTF(
"Received command event\n");
1067 DPRINTFN(10,
"event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1080 DPRINTF(
"Unhandled event = %u\n", event);
1106 addr = buf_res.physaddr;
1120 uint16_t timeout_ms)
1128 uint8_t timeout = 0;
1146 DPRINTFN(10,
"command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1148 (
long long)le64toh(trb->
qwTrb0),
1149 (
long)le32toh(trb->
dwTrb2),
1150 (
long)le32toh(trb->
dwTrb3));
1170 addr = buf_res.physaddr;
1208 DPRINTF(
"Command was completed when polling\n");
1212 DPRINTF(
"Command timeout!\n");
1223 temp = le32toh(trb->
dwTrb3);
1232 DPRINTF(
"Set address timeout\n");
1238 DPRINTF(
"Controller reset!\n");
1271 trb.
dwTrb3 = htole32(temp);
1294 temp = le32toh(trb.
dwTrb3);
1315 trb.
dwTrb3 = htole32(temp);
1322 uint8_t bsr, uint8_t slot_id)
1329 trb.
qwTrb0 = htole64(input_ctx);
1337 trb.
dwTrb3 = htole32(temp);
1369 switch (hdev->
state) {
1382 DPRINTF(
"Could not configure device\n");
1387 switch (udev->
speed) {
1414 DPRINTF(
"Could not configure default endpoint\n");
1433 DPRINTF(
"Could not set address "
1434 "for slot %u.\n",
index);
1446 temp = le32toh(
slot->dwSctx3);
1458 DPRINTF(
"Wrong state for set address.\n");
1472 uint8_t deconfigure, uint8_t slot_id)
1479 trb.
qwTrb0 = htole64(input_ctx);
1490 trb.
dwTrb3 = htole32(temp);
1504 trb.
qwTrb0 = htole64(input_ctx);
1508 trb.
dwTrb3 = htole32(temp);
1515 uint8_t ep_id, uint8_t slot_id)
1531 trb.
dwTrb3 = htole32(temp);
1538 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1545 trb.
qwTrb0 = htole64(dequeue_ptr);
1548 trb.
dwTrb2 = htole32(temp);
1553 trb.
dwTrb3 = htole32(temp);
1560 uint8_t ep_id, uint8_t slot_id)
1576 trb.
dwTrb3 = htole32(temp);
1594 trb.
dwTrb3 = htole32(temp);
1615 DPRINTFN(16,
"real interrupt (status=0x%08x)\n",
status);
1634 printf(
"%s: host controller halted\n",
1639 printf(
"%s: host system error\n",
1644 printf(
"%s: host controller error\n",
1685 uint32_t buf_offset;
1690 uint8_t shortpkt_old;
1697 len_old = temp->
len;
1707 if (temp->
len == 0) {
1719 if (temp->
len < average) {
1723 average = temp->
len;
1728 panic(
"%s: out of XHCI transfer descriptors!", __FUNCTION__);
1740 temp->
len -= average;
1752 temp->
len -= average;
1791 xhci_dump_trb(&td->
td_trb[x]);
1801 memset(&buf_res, 0,
sizeof(buf_res));
1804 buf_offset, &buf_res);
1807 if (buf_res.
length > average)
1808 buf_res.
length = average;
1814 npkt_off += buf_res.
length;
1818 npkt = howmany(len_old - npkt_off,
1828 htole64((uint64_t)buf_res.physaddr);
1842 if (td != td_first) {
1887 average -= buf_res.
length;
1888 buf_offset += buf_res.
length;
1890 xhci_dump_trb(&td->
td_trb[x]);
1894 }
while (average != 0);
1935 xhci_dump_trb(&td->
td_trb[x]);
1953 temp->
len = len_old;
2024 wMaxPacketSize[1] >> 3) & 3;
2056 }
else if (y > 15) {
2057 DPRINTFN(3,
"IST(%d) is too big!\n", temp.
sc->
sc_ist);
2080 DPRINTFN(3,
"start next=%d\n", temp.
isoc_frame);
2144 if (temp.
len == 0) {
2150 temp.
tlbpc = mult - 1;
2170 temp.
tbc = howmany(tdpc, mult) - 1;
2171 temp.
tlbpc = (tdpc % mult);
2173 if (temp.
tlbpc == 0)
2174 temp.
tlbpc = mult - 1;
2242 DPRINTF(
"addr[%u]=0x%016llx\n",
index, (
long long)dev_addr);
2283 for (x = 31; x != 1; x--) {
2284 if (mask & (1 << x))
2298 temp = le32toh(
slot->dwSctx0);
2299 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2301 slot->dwSctx0 = htole32(temp);
2310 uint16_t interval, uint8_t max_packet_count,
2311 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2312 uint16_t max_frame_size, uint8_t ep_mode)
2317 uint64_t ring_addr = pepext->
physaddr;
2338 if (max_packet_count == 0)
2360 ring_addr +=
sizeof(
struct xhci_trb) *
2370 switch (udev->
speed) {
2389 switch (udev->
speed) {
2394 max_packet_count /= mult;
2440 endp->
qwEpCtx2 = htole64(ring_addr);
2460 xhci_dump_endpoint(endp);
2479 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2492 XHCI_MAX_STREAMS) + x].
qwTrb0 = htole64(temp);
2496 XHCI_MAX_STREAMS) + x].
dwTrb2 = 0;
2498 XHCI_MAX_STREAMS) + x].
dwTrb3 = 0;
2540 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->
parent_hub) {
2560 route |= rh_port << (4 * (
depth - 1));
2563 DPRINTF(
"Route=0x%08x\n", route);
2569 switch (udev->
speed) {
2575 DPRINTF(
"Device inherits MTT\n");
2583 DPRINTF(
"HUB supports MTT\n");
2592 DPRINTF(
"Device inherits MTT\n");
2608 slot->dwSctx0 = htole32(temp);
2617 slot->dwSctx1 = htole32(temp);
2629 switch (udev->
speed) {
2632 if (hubdev != NULL) {
2643 slot->dwSctx2 = htole32(temp);
2652 slot->dwSctx3 = htole32(temp);
2655 xhci_dump_device(
slot);
2724 addr = buf_ep.physaddr;
2786 pepext->
physaddr = buf_ep.physaddr;
2852 DPRINTFN(8,
"Already in schedule\n");
2875 if (pepext->
trb_used[
id] >= trb_limit) {
2876 DPRINTFN(8,
"Too many TDs queued.\n");
2883 DPRINTFN(8,
"Reconfigure control endpoint\n");
2894 DPRINTFN(8,
"Not running\n");
2935 xhci_dump_trb(&td_last->
td_trb[td_last->
ntrb]);
2951 xhci_dump_trb(&pepext->
trb[i]);
2964 pepext->
xfer[i] = xfer;
2993 DPRINTF(
"port %d changed\n", i);
3009 DPRINTFN(2,
"xfer=%p, endpoint=%p, error=%d\n",
3117#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3128 .bMaxPacketSize = 9,
3135 .bNumConfigurations = 1,
3144 .bNumDeviceCaps = 3,
3148 .bDescriptorType = 1,
3149 .bDevCapabilityType = 2,
3150 .bmAttributes[0] = 2,
3155 .bDevCapabilityType = 3,
3157 HSETW(.wSpeedsSupported, 0x000C),
3158 .bFunctionalitySupport = 8,
3159 .bU1DevExitLat = 255,
3160 .wU2DevExitLat = { 0x00, 0x08 },
3164 .bDescriptorType = 1,
3165 .bDevCapabilityType = 4,
3178 .bConfigurationValue = 1,
3179 .iConfiguration = 0,
3196 .wMaxPacketSize[0] = 2,
3218 const char *str_ptr;
3239 DPRINTFN(3,
"type=0x%02x request=0x%02x wLen=0x%04x "
3240 "wValue=0x%04x wIndex=0x%04x\n",
3241 req->bmRequestType,
req->bRequest,
3244#define C(x,y) ((x) | ((y) << 8))
3245 switch (
C(
req->bRequest,
req->bmRequestType)) {
3259 switch (
value >> 8) {
3261 if ((
value & 0xff) != 0) {
3270 if ((
value & 0xff) != 0) {
3279 if ((
value & 0xff) != 0) {
3288 switch (
value & 0xff) {
3298 str_ptr =
"XHCI root HUB";
3358 DPRINTFN(9,
"UR_CLEAR_PORT_FEATURE\n");
3367 v =
XREAD4(sc, oper, port);
3369 v &= ~XHCI_PS_CLEAR;
3425 if ((
value & 0xff) != 0) {
3455 DeviceRemovable[j / 8] |= 1U << (j % 8);
3467 DPRINTFN(9,
"UR_GET_STATUS i=%d\n",
index);
3477 DPRINTFN(9,
"port status=0x%08x\n", v);
3549 v =
XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3558 v =
XREAD4(sc, oper, port);
3559 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3569 v =
XREAD4(sc, oper, port);
3570 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3584 DPRINTFN(3,
"set port enable %d\n",
index);
3587 DPRINTFN(6,
"suspend port %u (LPM=%u)\n",
index, i);
3589 if ((j < 1) || (j > 3)) {
3598 DPRINTFN(6,
"reset port %d\n",
index);
3602 DPRINTFN(3,
"set port power %d\n",
index);
3606 DPRINTFN(3,
"set port test %d\n",
index);
3609 DPRINTFN(3,
"set port indicator %d\n",
index);
3611 v &= ~XHCI_PS_PIC_SET(3);
3689 ntd = ((2 * xfer->
nframes) + 1
3707 parm, &pc,
sizeof(
struct xhci_td),
3713 for (
n = 0;
n != ntd;
n++) {
3721 td->
td_self = page_info.physaddr;
3822 DPRINTF(
"Could not reset endpoint %u\n", epno);
3827 DPRINTF(
"Could not stop endpoint %u\n", epno);
3834 stream_id, epno,
index);
3837 DPRINTF(
"Could not set dequeue ptr for endpoint %u\n", epno);
3844 mask = (1U << epno);
3855 DPRINTF(
"Could not configure "
3856 "endpoint %u at slot %u.\n", epno,
index);
3891 TAILQ_FOREACH(xfer, &sc->
sc_bus.
intr_q.head, wait_entry) {
3906 XHCI_MAX_STREAMS); i++) {
3913 if (pepext->
xfer[i] != NULL) {
3951 TAILQ_FOREACH(xfer, &sc->
sc_bus.
intr_q.head, wait_entry) {
3970 DPRINTFN(2,
"endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4062 DPRINTF(
"slot %u already allocated.\n", temp);
4149 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4183 DPRINTF(
"Failed to suspend endpoint "
4184 "%u on slot %u (ignored).\n",
n,
index);
4237 DPRINTF(
"Device reset failed "
4238 "for slot %u.\n",
index);
4256 DPRINTF(
"Failed to deconfigure "
4257 "slot %u.\n",
index);
4267 DPRINTF(
"Failed to deconfigure "
4268 "slot %u.\n",
index);
4285 DPRINTF(
"Could not configure device "
4286 "at slot %u.\n",
index);
4291 DPRINTF(
"Could not evaluate device "
4292 "context at slot %u.\n",
index);
volatile uint32_t td_next
void(* endpoint_init)(struct usb_device *, struct usb_endpoint_descriptor *, struct usb_endpoint *)
const struct usb_bus_methods * methods
struct usb_device ** devices
struct usb_xfer_queue intr_q
enum usb_hc_mode usb_mode
struct usb_device * parent_hs_hub
struct usb_device_descriptor ddesc
uint8_t controller_slot_id
struct usb_device * parent_hub
struct usb_device_flags flags
struct usb_endpoint_descriptor ctrl_ep_desc
struct usb_endpoint_ss_comp_descriptor * ecomp
struct usb_xfer_queue endpoint_q[USB_MAX_EP_STREAMS]
const struct usb_pipe_methods * methods
struct usb_endpoint_descriptor * edesc
uWord wHubCharacteristics
struct usb_dma_parent_tag * tag_parent
void(* open)(struct usb_xfer *)
usb_proc_callback_t * pm_callback
uint32_t hc_max_frame_size
uint8_t hc_max_packet_count
struct usb_xfer * curr_xfer
uint16_t hc_max_packet_size
uint8_t bandwidth_reclaimed
usb_frlength_t * frlengths
usb_frlength_t max_data_length
struct usb_page_cache * frbuffers
struct usb_endpoint * endpoint
struct usb_xfer_flags_int flags_int
struct usb_xfer_flags flags
struct usb_xfer_root * xroot
usb_frlength_t max_hc_frame_size
struct usb_bos_descriptor bosd
struct usb_devcap_container_id_descriptor cidd
struct usb_devcap_ss_descriptor usbdcd
struct usb_devcap_usb2ext_descriptor usb2extd
struct usb_endpoint_descriptor endpd
struct usb_interface_descriptor ifcd
struct usb_endpoint_ss_comp_descriptor endpcd
struct usb_config_descriptor confd
volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES+1]
volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]
volatile uint32_t dwEpCtx6
volatile uint32_t dwEpCtx0
volatile uint32_t dwEpCtx7
volatile uint64_t qwEpCtx2
volatile uint32_t dwEpCtx4
volatile uint32_t dwEpCtx1
volatile uint32_t dwEpCtx5
uint8_t trb_used[XHCI_MAX_STREAMS]
struct usb_page_cache * page_cache
struct usb_xfer * xfer[XHCI_MAX_TRANSFERS *XHCI_MAX_STREAMS]
uint8_t trb_index[XHCI_MAX_STREAMS]
volatile uint32_t dwEvrsTableSize
volatile uint64_t qwEvrsTablePtr
struct usb_page_cache device_pc
struct usb_page device_pg
struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]
struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]
struct usb_page_cache input_pc
struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]
struct xhci_trb hwr_events[XHCI_MAX_EVENTS]
struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]
struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]
struct usb_page_cache ctx_pc
struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]
struct xhci_hw_dev devs[XHCI_MAX_DEVICES+1]
struct usb_page_cache root_pc
struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]
volatile uint32_t dwSctx3
volatile uint32_t dwSctx2
volatile uint32_t dwSctx1
volatile uint32_t dwSctx0
xhci_port_route_t * sc_port_route
union xhci_hub_desc sc_hub_desc
struct usb_bus_msg sc_config_msg[2]
struct usb_device * sc_devices[XHCI_MAX_DEVICES]
uint8_t sc_no_deconfigure
uint32_t sc_cmd_result[2]
struct xhci_hw_softc sc_hw
uint8_t sc_ctx_is_64_byte
struct usb_page_cache * pc
struct xhci_td * alt_next
struct usb_page_cache * page_cache
struct xhci_td * obj_next
struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF+1]
struct usb_hub_ss_descriptor hubd
struct usb_port_status ps
#define UHD_PWR_INDIVIDUAL
#define UPS_C_BH_PORT_RESET
#define UT_WRITE_INTERFACE
#define UR_SET_DESCRIPTOR
#define UT_WRITE_CLASS_OTHER
#define UT_WRITE_CLASS_DEVICE
#define UPS_C_PORT_ENABLED
#define UDESC_DEVICE_CAPABILITY
#define UPS_C_OVERCURRENT_INDICATOR
#define UHF_PORT_LINK_STATE
#define UR_CLEAR_TT_BUFFER
#define UHF_BH_PORT_RESET
#define UHF_C_PORT_SUSPEND
#define UDESC_ENDPOINT_SS_COMP
#define UHF_PORT_U1_TIMEOUT
#define UPS_PORT_LINK_STATE_SET(x)
#define UHF_C_PORT_OVER_CURRENT
#define UPS_C_PORT_CONFIG_ERROR
#define UPS_C_PORT_LINK_STATE
#define UHD_OC_INDIVIDUAL
#define UT_WRITE_ENDPOINT
#define UT_READ_CLASS_DEVICE
#define UHF_C_PORT_CONFIG_ERROR
#define UT_READ_CLASS_OTHER
#define UHF_PORT_INDICATOR
#define UHF_C_PORT_LINK_STATE
#define UE_GET_SS_ISO_MULT(x)
#define UPS_C_CONNECT_STATUS
#define UPS_CURRENT_CONNECT_STATUS
#define UHF_C_PORT_ENABLE
#define UHF_C_BH_PORT_RESET
#define UPS_OVERCURRENT_INDICATOR
#define UT_READ_INTERFACE
#define UR_GET_DESCRIPTOR
#define UHF_C_PORT_CONNECTION
#define UHF_PORT_U2_TIMEOUT
void usbd_get_page(struct usb_page_cache *pc, usb_frlength_t offset, struct usb_page_search *res)
void usbd_copy_out(struct usb_page_cache *cache, usb_frlength_t offset, void *ptr, usb_frlength_t len)
void usb_pc_free_mem(struct usb_page_cache *pc)
void usb_pc_cpu_invalidate(struct usb_page_cache *pc)
void usb_pc_cpu_flush(struct usb_page_cache *pc)
#define USB_GET_DMA_TAG(dev)
uint8_t usb_pc_alloc_mem(struct usb_page_cache *pc, struct usb_page *pg, usb_size_t size, usb_size_t align)
void usb_bus_mem_free_all(struct usb_bus *bus, usb_bus_mem_cb_t *cb)
uint8_t usb_bus_mem_alloc_all(struct usb_bus *bus, bus_dma_tag_t dmat, usb_bus_mem_cb_t *cb)
void usb_bus_reset_async_locked(struct usb_bus *bus)
#define USB_HW_POWER_RESUME
void usb_bus_mem_flush_all(struct usb_bus *bus, usb_bus_mem_cb_t *cb)
#define USB_HW_POWER_SUSPEND
#define USB_HW_POWER_SHUTDOWN
void() usb_bus_mem_sub_cb_t(struct usb_bus *bus, struct usb_page_cache *pc, struct usb_page *pg, usb_size_t size, usb_size_t align)
#define USB_BUS_UNLOCK(_b)
#define USB_BUS_LOCK_ASSERT(_b, _t)
enum usb_dev_speed usbd_get_speed(struct usb_device *udev)
enum usb_dev_state usb_get_device_state(struct usb_device *udev)
void uhub_root_intr(struct usb_bus *bus, const uint8_t *ptr, uint8_t len)
usb_error_t uhub_query_info(struct usb_device *udev, uint8_t *pnports, uint8_t *ptt)
void * usb_proc_msignal(struct usb_process *up, void *_pm0, void *_pm1)
void usbd_transfer_setup_sub(struct usb_setup_params *parm)
void usbd_transfer_done(struct usb_xfer *xfer, usb_error_t error)
void usbd_xfer_set_frame_len(struct usb_xfer *xfer, usb_frcount_t frindex, usb_frlength_t len)
uint8_t usbd_xfer_get_fps_shift(struct usb_xfer *xfer)
void usb_dma_delay_done_cb(struct usb_xfer *xfer)
void usbd_transfer_dequeue(struct usb_xfer *xfer)
void usbd_transfer_enqueue(struct usb_xfer_queue *pq, struct usb_xfer *xfer)
uint8_t usbd_xfer_get_isochronous_start_frame(struct usb_xfer *xfer, uint32_t frame_curr, uint32_t frame_min, uint32_t frame_ms, uint32_t frame_mask, uint32_t *p_frame_start)
void usbd_transfer_timeout_ms(struct usb_xfer *xfer, void(*cb)(void *arg), usb_timeout_t ms)
uint8_t usbd_transfer_setup_sub_malloc(struct usb_setup_params *parm, struct usb_page_cache **ppc, usb_size_t size, usb_size_t align, usb_size_t count)
void usb_pause_mtx(struct mtx *mtx, int timo)
uint8_t usb_make_str_desc(void *ptr, uint16_t max_len, const char *s)
void() usb_proc_callback_t(struct usb_proc_msg *)
uint8_t bInterfaceSubClass
@ USB_ERR_NORMAL_COMPLETION
uint8_t bInterfaceProtocol
#define USB_MS_TO_TICKS(ms)
static void xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
usb_error_t xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
static void xhci_device_suspend(struct usb_device *udev)
static usb_error_t xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, uint8_t bsr, uint8_t slot_id)
static void xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
static usb_error_t xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
static usb_error_t xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, uint8_t deconfigure, uint8_t slot_id)
static void xhci_generic_done(struct usb_xfer *xfer)
static usb_error_t xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
static const struct usb_hub_ss_descriptor xhci_hubd
static usb_error_t xhci_configure_endpoint(struct usb_device *, struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t)
usb_error_t xhci_reset_controller(struct xhci_softc *sc)
static usb_error_t xhci_configure_mask(struct usb_device *, uint32_t, uint8_t)
static void xhci_root_intr(struct xhci_softc *)
static void xhci_timeout(void *arg)
static uint8_t xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno)
static void xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
static usb_error_t xhci_device_init(struct usb_device *udev)
static usb_error_t xhci_configure_device(struct usb_device *)
static const struct xhci_config_desc xhci_confd
SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, &xhcistreams, 0, "Set to enable streams mode support")
static void xhci_skip_transfer(struct usb_xfer *xfer)
static void xhci_set_hw_power(struct usb_bus *bus)
static void xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
static void xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
usb_error_t xhci_halt_controller(struct xhci_softc *sc)
static usb_error_t xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
static void xhci_free_device_ext(struct usb_device *)
static const struct usb_bus_methods xhci_bus_methods
static void xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
static void xhci_device_done(struct usb_xfer *, usb_error_t)
static void xhci_device_generic_close(struct usb_xfer *xfer)
static usb_error_t xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, uint8_t ep_id, uint8_t slot_id)
static int xhci_reset_command_queue_locked(struct xhci_softc *sc)
static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW|CTLFLAG_MPSAFE, 0, "USB XHCI")
static usb_error_t xhci_configure_reset_endpoint(struct usb_xfer *xfer)
#define XHCI_GET_CTX(sc, which, field, ptr)
static usb_error_t xhci_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength)
static void xhci_xfer_unsetup(struct usb_xfer *xfer)
static usb_proc_callback_t xhci_configure_msg
uint8_t xhci_use_polling(void)
static usb_error_t xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, uint8_t ep_id, uint8_t slot_id)
static usb_error_t xhci_transfer_insert(struct usb_xfer *xfer)
void xhci_uninit(struct xhci_softc *sc)
static void xhci_device_state_change(struct usb_device *udev)
static void xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
static void xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
static usb_error_t xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, uint8_t ep_mode)
static int xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
static void xhci_setup_generic_chain(struct usb_xfer *xfer)
static void xhci_do_poll(struct usb_bus *)
static void xhci_xfer_setup(struct usb_setup_params *parm)
static void xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
static usb_error_t xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
static void xhci_endpoint_doorbell(struct usb_xfer *)
static void xhci_device_generic_enter(struct usb_xfer *xfer)
usb_error_t xhci_start_controller(struct xhci_softc *sc)
static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, uint64_t, uint8_t)
static usb_error_t xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
static void xhci_activate_transfer(struct usb_xfer *xfer)
static void xhci_device_uninit(struct usb_device *udev)
static usb_error_t xhci_generic_done_sub(struct usb_xfer *xfer)
static const struct usb_device_descriptor xhci_devd
static void xhci_device_generic_open(struct usb_xfer *xfer)
static int xhci_interrupt_poll(struct xhci_softc *sc)
static void xhci_device_generic_start(struct usb_xfer *xfer)
static usb_error_t xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
static const struct xhci_bos_desc xhci_bosd
static void xhci_device_generic_multi_enter(struct usb_endpoint *ep, usb_stream_t stream_id, struct usb_xfer *enter_xfer)
static const struct usb_pipe_methods xhci_device_generic_methods
void xhci_interrupt(struct xhci_softc *sc)
static usb_error_t xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, uint16_t timeout_ms)
static struct xhci_endpoint_ext * xhci_get_endpoint_ext(struct usb_device *, struct usb_endpoint_descriptor *)
static void xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep)
static void xhci_start_dma_delay(struct usb_xfer *xfer)
static usb_error_t xhci_alloc_device_ext(struct usb_device *udev)
static void xhci_device_resume(struct usb_device *udev)
#define XHCI_EPCTX_0_LSA_SET(x)
#define XHCI_TRB_3_DIR_IN
#define XHCI_TRB_2_BYTES_SET(x)
#define XHCI_TRB_0_WLENGTH_MASK
#define XHCI_SCTX_1_NUM_PORTS_SET(x)
#define XHCI_TRB_TYPE_ENABLE_SLOT
#define XHCI_SCTX_0_MTT_SET(x)
#define XHCI_SCTX_0_SPEED_SET(x)
#define XHCI_TRB_TYPE_SET_TR_DEQUEUE
#define XHCI_TRB_3_IOC_BIT
#define XHCI_TRB_TYPE_DISABLE_SLOT
struct xhci_slot_ctx ctx_slot
#define XHCI_TRB_TYPE_ISOCH
#define XHCI_TRB_3_TLBPC_SET(x)
#define XHCI_EPCTX_1_EPTYPE_SET(x)
#define XHCI_TRB_TYPE_NOOP
#define XHCI_MAX_ENDPOINTS
#define XHCI_SCTX_0_HUB_SET(x)
#define XHCI_SCTX_0_CTX_NUM_SET(x)
#define XHCI_SCTX_0_SCT_SEC_TR_RING
#define XHCI_TRB_TYPE_CONFIGURE_EP
#define XHCI_TRB_TYPE_ADDRESS_DEVICE
#define XHCI_SCTX_2_TT_THINK_TIME_SET(x)
#define XHCI_TRB_2_ERROR_GET(x)
#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x)
#define XHCI_SCTX_3_SLOT_STATE_SET(x)
#define XHCI_CMD_UNLOCK(sc)
#define XHCI_TRB_EVENT_TRANSFER
struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]
#define XHCI_TRB_3_SLOT_GET(x)
#define XHCI_TRB_TYPE_STOP_EP
#define XHCI_TRB_3_BSR_BIT
#define XHCI_TRB_3_TYPE_SET(x)
#define XHCI_TRB_2_STREAM_SET(x)
#define XHCI_SCTX_0_ROUTE_SET(x)
#define XHCI_EPCTX_0_MULT_SET(x)
#define XHCI_TRB_3_FRID_SET(x)
#define XHCI_MAX_SCRATCHPADS
#define XHCI_TRB_ERROR_SUCCESS
#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x)
#define XHCI_TRB_TYPE_RESET_EP
#define XHCI_TRB_TYPE_NORMAL
#define XHCI_TRB_2_IRQ_SET(x)
#define XHCI_TRB_3_IDT_BIT
#define XHCI_CMD_ASSERT_LOCKED(sc)
#define XHCI_TRB_3_CHAIN_BIT
#define XHCI_EPCTX_0_EPSTATE_SET(x)
#define XHCI_SCTX_3_DEV_ADDR_SET(x)
#define XHCI_TRB_0_DIR_IN_MASK
#define XHCI_TRB_3_TRT_IN
#define XHCI_TRB_3_EP_GET(x)
#define XHCI_TD_PAGE_SIZE
#define XHCI_EPNO2EPID(x)
#define XHCI_TRB_EVENT_CMD_COMPLETE
#define XHCI_SCTX_3_DEV_ADDR_GET(x)
#define XHCI_TRB_3_TC_BIT
#define XHCI_TRB_ERROR_STALL
#define XHCI_TRB_3_DCEP_BIT
#define XHCI_CMD_LOCK(sc)
#define XHCI_TRB_3_SLOT_SET(x)
#define XHCI_EPCTX_0_EPSTATE_HALTED
#define XHCI_EPCTX_0_EPSTATE_GET(x)
#define XHCI_TRB_ERROR_SHORT_PKT
#define XHCI_TRB_TYPE_STATUS_STAGE
#define XHCI_TRB_3_ISP_BIT
#define XHCI_EPCTX_0_EPSTATE_STOPPED
#define XHCI_TRB_3_CYCLE_BIT
#define XHCI_SCTX_1_RH_PORT_SET(x)
#define XHCI_EPCTX_0_IVAL_SET(x)
#define XHCI_TRB_2_REM_GET(x)
#define XHCI_TRB_ERROR_LENGTH
#define XHCI_TRB_3_PRSV_BIT
#define XHCI_SCTX_2_TT_HUB_SID_SET(x)
#define XHCI_TRB_3_ISO_SIA_BIT
#define XHCI_TRB_3_SUSP_EP_BIT
#define XHCI_EPCTX_1_CERR_SET(x)
#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x)
#define XHCI_MAX_COMMANDS
#define XHCI_TRB_2_BYTES_GET(x)
#define XHCI_SCTX_2_TT_PORT_NUM_SET(x)
#define XHCI_EPCTX_2_DCS_SET(x)
#define XHCI_TRB_TYPE_LINK
#define XHCI_MAX_TRANSFERS
#define XHCI_TRB_ERROR_PARAMETER
#define XHCI_TRB_TYPE_SETUP_STAGE
#define XHCI_INCTX_NON_CTRL_MASK
#define XHCI_TD_PAYLOAD_MAX
#define XHCI_EPCTX_1_HID_SET(x)
#define XHCI_TRB_3_TRT_OUT
#define XHCI_EPCTX_1_MAXB_SET(x)
#define XHCI_TRB_2_TDSZ_SET(x)
#define XHCI_EPCTX_0_EPSTATE_DISABLED
#define XHCI_EPCTX_1_MAXP_SIZE_SET(x)
#define XHCI_TRB_3_TYPE_GET(x)
#define XHCI_SCTX_2_IRQ_TARGET_SET(x)
#define XHCI_TRB_TYPE_RESET_DEVICE
#define XHCI_TRB_TYPE_EVALUATE_CTX
#define XHCI_TRB_3_EP_SET(x)
#define XHCI_TRB_TYPE_DATA_STAGE
#define XHCI_TRB_3_TBC_SET(x)
#define XHCI_HCS0_PIND(x)
#define XHCI_PM3_U1TO_SET(x)
#define XHCI_IMAN_INTR_PEND
#define XREAD1(sc, what, a)
#define XHCI_HCS2_ERST_MAX(x)
#define XHCI_IMOD_DEFAULT
#define XWRITE4(sc, what, a, x)
#define XHCI_HCS3_U2_DEL(x)
#define XREAD2(sc, what, a)
#define XHCI_HCS0_AC64(x)
#define XHCI_PM3_U2TO_SET(x)
#define XHCI_IMAN_INTR_ENA
#define XHCI_MFINDEX_GET(x)
#define XHCI_PS_PLS_GET(x)
#define XHCI_PS_SPEED_GET(x)
#define XHCI_PS_PLS_SET(x)
#define XHCI_ERSTS_SET(x)
#define XHCI_HCS3_U1_DEL(x)
#define XREAD4(sc, what, a)
#define XHCI_PS_PIC_SET(x)
#define XHCI_DB_SID_SET(x)
#define XHCI_ERSTBA_LO(n)
#define XHCI_ERDP_LO_BUSY
#define XHCI_HCS1_N_PORTS(x)
#define XHCI_HCS1_DEVSLOT_MAX(x)
#define XHCI_ERSTBA_HI(n)
#define XHCI_HCS2_SPB_MAX(x)