46#define EEP_MINOR(_ah) \
47 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
48#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
49#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
52#define BASE_ACTIVATE_DELAY 100
53#define PLL_SETTLE_DELAY 300
54#define RTC_PLL_SETTLE_DELAY 1000
58 const struct ieee80211_channel *chan, int16_t *ratesArray,
59 uint16_t cfgCtl, uint16_t AntennaReduction,
60 uint16_t twiceMaxRegulatoryPower,
64 const struct ieee80211_channel *chan,
65 int16_t *pTxPowerIndexOffset);
68 uint8_t * bChans, uint16_t availPiers,
69 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
70 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
71 uint16_t numXpdGains);
75 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
77#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
78#define N(a) (sizeof (a) / sizeof (a[0]))
82 int16_t txPowerIndexOffset = 0;
87 uint16_t twiceAntennaReduction;
88 uint16_t twiceMaxRegulatoryPower;
95 AH5416(ah)->ah_ht40PowerIncForPdadc = 2;
100 powerLimit = chan->ic_maxregpower * 2;
101 twiceAntennaReduction = chan->ic_maxantgain;
105 __func__,chan->ic_freq, cfgCtl );
112 &
AH5416(ah)->ah_ratesArray[0],cfgCtl,
113 twiceAntennaReduction,
114 twiceMaxRegulatoryPower, powerLimit)) {
116 "%s: unable to set tx power per rate table\n", __func__);
130 if (IEEE80211_IS_CHAN_HT40(chan)) {
142 for (i = 0; i <
N(
AH5416(ah)->ah_ratesArray); i++) {
143 AH5416(ah)->ah_ratesArray[i] = (int16_t)(txPowerIndexOffset +
AH5416(ah)->ah_ratesArray[i]);
148 if (
AH5416(ah)->ah_ratesArray[i] < 0)
149 AH5416(ah)->ah_ratesArray[i] = 0;
153 ar5416PrintPowerPerRate(ah,
AH5416(ah)->ah_ratesArray);
163 if (IEEE80211_IS_CHAN_HT40(chan)) {
165 AH5416(ah)->ah_ht40PowerIncForPdadc;
167 AH5416(ah)->ah_ht40PowerIncForPdadc;
169 AH5416(ah)->ah_ht40PowerIncForPdadc;
171 AH5416(ah)->ah_ht40PowerIncForPdadc;
173 AH5416(ah)->ah_ht40PowerIncForPdadc;
175 AH5416(ah)->ah_ht40PowerIncForPdadc;
177 AH5416(ah)->ah_ht40PowerIncForPdadc;
179 AH5416(ah)->ah_ht40PowerIncForPdadc;
251 uint8_t txRxAttenLocal;
252 uint8_t ob[5], db1[5], db2[5];
267 ob[0] = pModal->
ob_0;
268 ob[1] = pModal->
ob_1;
269 ob[2] = pModal->
ob_2;
270 ob[3] = pModal->
ob_3;
271 ob[4] = pModal->
ob_4;
273 db1[0] = pModal->
db1_0;
274 db1[1] = pModal->
db1_1;
275 db1[2] = pModal->
db1_2;
276 db1[3] = pModal->
db1_3;
277 db1[4] = pModal->
db1_4;
279 db2[0] = pModal->
db2_0;
280 db2[1] = pModal->
db2_1;
281 db2[2] = pModal->
db2_2;
282 db2[3] = pModal->
db2_3;
283 db2[4] = pModal->
db2_4;
284 }
else if (pModal->
version == 1) {
285 ob[0] = pModal->
ob_0;
286 ob[1] = ob[2] = ob[3] = ob[4] = pModal->
ob_1;
287 db1[0] = pModal->
db1_0;
288 db1[1] = db1[2] = db1[3] = db1[4] = pModal->
db1_1;
289 db2[0] = pModal->
db2_0;
290 db2[1] = db2[2] = db2[3] = db2[4] = pModal->
db2_1;
294 for (i = 0; i < 5; i++) {
295 ob[i] = pModal->
ob_0;
296 db1[i] = pModal->
db1_0;
297 db2[i] = pModal->
db1_0;
348 if (IEEE80211_IS_CHAN_HT40(chan))
368 uint32_t pwrctrl, mask, clr;
370 mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25);
371 pwrctrl = mask * bb_desired_scale;
377 mask = (1<<0) | (1<<5) | (1<<15);
378 pwrctrl = mask * bb_desired_scale;
382 mask = (1<<0) | (1<<5);
383 pwrctrl = mask * bb_desired_scale;
399 const struct ieee80211_channel *chan,
400 int16_t *ratesArray, uint16_t cfgCtl,
401 uint16_t AntennaReduction,
402 uint16_t twiceMaxRegulatoryPower,
405#define N(a) (sizeof(a)/sizeof(a[0]))
407#define EXT_ADDITIVE (0x8000)
408#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
409#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
413 int16_t twiceLargestAntenna;
416 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
418 int16_t scaledPower, minCtlPower;
420#define SUB_NUM_CTL_MODES_AT_2G_40 3
421 static const uint16_t ctlModesFor11g[] = {
424 const uint16_t *pCtlMode;
425 uint16_t numCtlModes, ctlMode, freq;
433 twiceLargestAntenna = (int16_t)
AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
442 scaledPower =
AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
447 pCtlMode = ctlModesFor11g;
456 if (IEEE80211_IS_CHAN_HT40(chan)) {
457 numCtlModes =
N(ctlModesFor11g);
477 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
490 uint16_t twiceMinEdgePower;
502 twiceMaxEdgePower =
AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
505 twiceMaxEdgePower = twiceMinEdgePower;
510 minCtlPower = (uint8_t)
AH_MIN(twiceMaxEdgePower, scaledPower);
512 switch(pCtlMode[ctlMode]) {
514 for (i = 0; i <
N(targetPowerCck.
tPow2x); i++) {
520 for (i = 0; i <
N(targetPowerOfdm.
tPow2x); i++) {
526 for (i = 0; i <
N(targetPowerHt20.
tPow2x); i++) {
531 targetPowerCckExt.tPow2x[0] = (uint8_t)
AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
534 targetPowerOfdmExt.
tPow2x[0] = (uint8_t)
AH_MIN(targetPowerOfdmExt.
tPow2x[0], minCtlPower);
538 for (i = 0; i <
N(targetPowerHt40.
tPow2x); i++) {
561#undef SUB_NUM_CTL_MODES_AT_2G_40
567 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
571 uint16_t pdGainOverlap_t2;
574 uint16_t numPiers, i;
575 int16_t tMinCalPower;
576 uint16_t numXpdGain, xpdMask;
577 uint16_t xpdGainValues[4];
578 uint32_t regChainOffset;
580 OS_MEMZERO(xpdGainValues,
sizeof(xpdGainValues));
615 pCalBChans, numPiers,
617 &tMinCalPower, gainBoundaries,
618 pdadcValues, numXpdGain);
633 *pTxPowerIndexOffset = 0;
640 const struct ieee80211_channel *chan,
642 uint8_t * bChans, uint16_t availPiers,
643 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
644 uint8_t * pPDADCValues, uint16_t numXpdGains)
649 uint16_t idxL, idxR, numPiers;
660 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
665 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
667 int16_t minDelta = 0;
673 for (numPiers = 0; numPiers < availPiers; numPiers++) {
681 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR);
685 for (i = 0; i < numXpdGains; i++) {
686 minPwrT4[i] = pRawDataSet[idxL].
pwrPdg[i][0];
687 maxPwrT4[i] = pRawDataSet[idxL].
pwrPdg[i][4];
689 pRawDataSet[idxL].pwrPdg[i],
690 pRawDataSet[idxL].vpdPdg[i],
694 for (i = 0; i < numXpdGains; i++) {
695 pVpdL = pRawDataSet[idxL].
vpdPdg[i];
696 pPwrL = pRawDataSet[idxL].
pwrPdg[i];
697 pVpdR = pRawDataSet[idxR].
vpdPdg[i];
698 pPwrR = pRawDataSet[idxR].
pwrPdg[i];
701 minPwrT4[i] =
AH_MAX(pPwrL[0], pPwrR[0]);
714 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
716 IEEE80211_IS_CHAN_2GHZ(chan)),
717 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
721 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
724 for (i = 0; i < numXpdGains; i++) {
725 if (i == (numXpdGains - 1)) {
726 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
728 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
740 minDelta = pPdGainBoundaries[0] - 23;
741 pPdGainBoundaries[0] = 23;
750 ss = (int16_t)(0 - (minPwrT4[i] / 2));
755 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
757 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
758 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
763 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
764 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
768 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
769 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
770 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
773 pPDADCValues[k++] = vpdTableI[i][ss++];
776 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
777 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
782 if (tgtIndex >= maxIndex) {
784 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
785 (ss - maxIndex +1) * vpdStep));
786 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
799 pPDADCValues[k] = pPDADCValues[k-1];
HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, uint16_t *indexL, uint16_t *indexR)
int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, int16_t targetLeft, int16_t targetRight)
#define AR_EEPROM_VER14_1
#define AR5416_EEP_VER_MINOR_MASK
#define AR5416_PD_GAIN_ICEPTS
#define owl_get_ntxchains(_txchainmask)
#define AR5416_NUM_PDADC_VALUES
#define AR5416_EEP_MINOR_VER_3
#define AR5416_MAX_RATE_POWER
#define AR5416_MAX_PWR_RANGE_IN_HALF_DB
#define AR5416_PWR_TABLE_OFFSET_DB
#define AR5416_MAX_CHAINS
#define AR5416_BCHAN_UNUSED
#define AR5416_EEP_MINOR_VER_2
#define AR5416_PD_GAINS_IN_MASK
#define AR5416_4K_NUM_2G_40_TARGET_POWERS
#define EEP_4K_BB_DESIRED_SCALE_MASK
#define AR5416_4K_NUM_2G_20_TARGET_POWERS
#define AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT
#define AR5416_4K_NUM_CTLS
#define AR5416_4K_NUM_2G_CAL_PIERS
#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS
#define AR5416_4K_NUM_PD_GAINS
u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *)
#define ath_hal_eepromSet(_ah, _param, _val)
#define OS_REG_RMW(_a, _r, _set, _clr)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v)
#define HALDEBUG(_ah, __m,...)
#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v)
void ath_hal_printf(struct ath_hal *, const char *,...)
#define OS_MEMZERO(_a, _n)
#define OS_REG_WRITE(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg)
#define AR_PHY_SETTLING_SWITCH
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
#define AR_PHY_DESIRED_SZ_ADC
#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP
#define AR_PHY_DESIRED_SZ
void ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i, uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[])
void ar5416GetChannelCenters(struct ath_hal *, const struct ieee80211_channel *chan, CHAN_CENTERS *centers)
void ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain, uint16_t xpdGainValues[])
void ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, const struct ieee80211_channel *chan, const int16_t ratesArray[])
void ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[])
void ar5416GetTargetPowersLeg(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, HAL_BOOL isExtTarget)
void ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, HAL_BOOL isHt40Target)
uint16_t ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
void ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah, const struct ieee80211_channel *chan, int16_t *ratesArray, const CAL_TARGET_POWER_LEG *targetPowerCck, const CAL_TARGET_POWER_LEG *targetPowerCckExt, const CAL_TARGET_POWER_LEG *targetPowerOfdm, const CAL_TARGET_POWER_LEG *targetPowerOfdmExt, const CAL_TARGET_POWER_HT *targetPowerHt20, const CAL_TARGET_POWER_HT *targetPowerHt40)
int ar5416GetRegChainOffset(struct ath_hal *ah, int i)
#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB
#define AR9280_PHY_RXGAIN_TXRX_MARGIN
#define AR_PHY_TX_PWRCTRL9
#define AR_PHY_GAIN_2GHZ_XATTEN2_DB
#define AR9280_PHY_RXGAIN_TXRX_ATTEN
#define AR_PHY_SWITCH_CHAIN_0
#define AR_PHY_TX_END_TO_A2_RX_ON
#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
#define AR_PHY_SWITCH_COM
#define AR_PHY_RF_CTL4_FRAME_XPAB_ON
#define AR9280_PHY_CCA_THRESH62
#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF
#define AR_PHY_EXT_CCA0_THRESH62
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON
#define AR_PHY_TX_FRAME_TO_DATA_START
#define AR_PHY_TX_FRAME_TO_PA_ON
#define AR_PHY_TIMING_CTRL4_CHAIN(_i)
#define AR_SREV_5416_V20_OR_LATER(_ah)
#define AR_SREV_KITE(_ah)
#define AR_SREV_MERLIN_20_OR_LATER(_ah)
#define AR_SREV_9271(_ah)
#define AR_PHY_TX_PWRCTRL8
#define AR_PHY_CH0_TX_PWRCTRL12
#define AR_PHY_CH0_TX_PWRCTRL13
#define AR_PHY_TX_PWRCTRL10
#define AR_PHY_CH0_TX_PWRCTRL11
HAL_BOOL ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
static void ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal)
static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, uint8_t *bChans, uint16_t availPiers, uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t *pPdGainBoundaries, uint8_t *pPDADCValues, uint16_t numXpdGains)
static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, const struct ieee80211_channel *chan, int16_t *ratesArray, uint16_t cfgCtl, uint16_t AntennaReduction, uint16_t twiceMaxRegulatoryPower, uint16_t powerLimit)
HAL_BOOL ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
HAL_BOOL ar9285SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
#define IS_EEP_MINOR_V2(_ah)
#define SUB_NUM_CTL_MODES_AT_2G_40
static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
#define AR9285_AN_RF2G4_DB2_2
#define AR9285_AN_RF2G3_DB1_1
#define AR9285_AN_RF2G4_DB2_1
#define AR9285_AN_RF2G4_DB1_4
#define AR9285_AN_RF2G3_OB_1
#define AR9285_AN_RF2G4_DB2_3
#define AR9285_AN_RF2G3_DB1_0
#define AR9285_AN_RF2G3_DB1_2
#define AR9285_AN_RF2G3_OB_3
#define AR9285_AN_RF2G3_OB_4
#define AR9285_AN_RF2G4_DB2_4
#define AR9285_AN_RF2G3_OB_2
#define AR9285_AN_RF2G3_OB_0
#define AR9285_AN_RF2G4_DB1_3
#define AR9285_AN_RF2G4_DB2_0
CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES]
struct ar5416eeprom_4k ee_base
uint8_t ctlIndex[AR5416_4K_NUM_CTLS]
CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS]
BASE_EEP4K_HEADER baseEepHeader
CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS]
CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS]
CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS]
MODAL_EEP4K_HEADER modalHeader
uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS]
CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS]
CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS]
int16_t ah_txPowerIndexOffset
uint32_t ah_tx6PowerInHalfDbm
uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]