FreeBSD kernel usb device Code
xhci_pci.c
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1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010-2022 Hans Petter Selasky
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD$");
30
31#include <sys/stdint.h>
32#include <sys/stddef.h>
33#include <sys/param.h>
34#include <sys/queue.h>
35#include <sys/types.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/bus.h>
39#include <sys/module.h>
40#include <sys/lock.h>
41#include <sys/mutex.h>
42#include <sys/condvar.h>
43#include <sys/sysctl.h>
44#include <sys/sx.h>
45#include <sys/unistd.h>
46#include <sys/callout.h>
47#include <sys/malloc.h>
48#include <sys/priv.h>
49
50#include <dev/usb/usb.h>
51#include <dev/usb/usbdi.h>
52
53#include <dev/usb/usb_core.h>
54#include <dev/usb/usb_busdma.h>
55#include <dev/usb/usb_process.h>
56#include <dev/usb/usb_util.h>
57
59#include <dev/usb/usb_bus.h>
60#include <dev/usb/usb_pci.h>
63#include "usb_if.h"
64
65#define PCI_XHCI_VENDORID_AMD 0x1022
66#define PCI_XHCI_VENDORID_INTEL 0x8086
67
68static device_probe_t xhci_pci_probe;
69static device_detach_t xhci_pci_detach;
70static usb_take_controller_t xhci_pci_take_controller;
71
72static device_method_t xhci_device_methods[] = {
73 /* device interface */
74 DEVMETHOD(device_probe, xhci_pci_probe),
75 DEVMETHOD(device_attach, xhci_pci_attach),
76 DEVMETHOD(device_detach, xhci_pci_detach),
77 DEVMETHOD(device_suspend, bus_generic_suspend),
78 DEVMETHOD(device_resume, bus_generic_resume),
79 DEVMETHOD(device_shutdown, bus_generic_shutdown),
80 DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
81
82 DEVMETHOD_END
83};
84
85DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods,
86 sizeof(struct xhci_softc));
87
88static devclass_t xhci_devclass;
89
90DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL);
91MODULE_DEPEND(xhci, usb, 1, 1, 1);
92
93static const char *
94xhci_pci_match(device_t self)
95{
96 uint32_t device_id = pci_get_devid(self);
97
98 switch (device_id) {
99 case 0x145c1022:
100 return ("AMD KERNCZ USB 3.0 controller");
101 case 0x148c1022:
102 return ("AMD Starship USB 3.0 controller");
103 case 0x149c1022:
104 return ("AMD Matisse USB 3.0 controller");
105 case 0x43ba1022:
106 return ("AMD X399 USB 3.0 controller");
107 case 0x43b91022: /* X370 */
108 case 0x43bb1022: /* B350 */
109 return ("AMD 300 Series USB 3.0 controller");
110 case 0x78121022:
111 case 0x78141022:
112 case 0x79141022:
113 return ("AMD FCH USB 3.0 controller");
114
115 case 0x145f1d94:
116 return ("Hygon USB 3.0 controller");
117
118 case 0x01941033:
119 return ("NEC uPD720200 USB 3.0 controller");
120 case 0x00151912:
121 return ("NEC uPD720202 USB 3.0 controller");
122
123 case 0x10001b73:
124 return ("Fresco Logic FL1000G USB 3.0 controller");
125 case 0x11001b73:
126 return ("Fresco Logic FL1100 USB 3.0 controller");
127
128 case 0x10421b21:
129 return ("ASMedia ASM1042 USB 3.0 controller");
130 case 0x11421b21:
131 return ("ASMedia ASM1042A USB 3.0 controller");
132 case 0x13431b21:
133 return ("ASMedia ASM1143 USB 3.1 controller");
134 case 0x32421b21:
135 return ("ASMedia ASM3242 USB 3.2 controller");
136
137 case 0x0b278086:
138 return ("Intel Goshen Ridge Thunderbolt 4 USB controller");
139 case 0x0f358086:
140 return ("Intel BayTrail USB 3.0 controller");
141 case 0x11388086:
142 return ("Intel Maple Ridge Thunderbolt 4 USB controller");
143 case 0x15c18086:
144 case 0x15d48086:
145 case 0x15db8086:
146 return ("Intel Alpine Ridge Thunderbolt 3 USB controller");
147 case 0x15e98086:
148 case 0x15ec8086:
149 case 0x15f08086:
150 return ("Intel Titan Ridge Thunderbolt 3 USB controller");
151 case 0x19d08086:
152 return ("Intel Denverton USB 3.0 controller");
153 case 0x9c318086:
154 case 0x1e318086:
155 return ("Intel Panther Point USB 3.0 controller");
156 case 0x22b58086:
157 return ("Intel Braswell USB 3.0 controller");
158 case 0x31a88086:
159 return ("Intel Gemini Lake USB 3.0 controller");
160 case 0x34ed8086:
161 return ("Intel Ice Lake-LP USB 3.1 controller");
162 case 0x43ed8086:
163 return ("Intel Tiger Lake-H USB 3.2 controller");
164 case 0x461e8086:
165 return ("Intel Alder Lake-P Thunderbolt 4 USB controller");
166 case 0x51ed8086:
167 return ("Intel Alder Lake USB 3.2 controller");
168 case 0x5aa88086:
169 return ("Intel Apollo Lake USB 3.0 controller");
170 case 0x7ae08086:
171 return ("Intel Alder Lake USB 3.2 controller");
172 case 0x8a138086:
173 return ("Intel Ice Lake Thunderbolt 3 USB controller");
174 case 0x8c318086:
175 return ("Intel Lynx Point USB 3.0 controller");
176 case 0x8cb18086:
177 return ("Intel Wildcat Point USB 3.0 controller");
178 case 0x8d318086:
179 return ("Intel Wellsburg USB 3.0 controller");
180 case 0x9a138086:
181 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller");
182 case 0x9a178086:
183 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller");
184 case 0x9cb18086:
185 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller");
186 case 0x9d2f8086:
187 return ("Intel Sunrise Point-LP USB 3.0 controller");
188 case 0xa0ed8086:
189 return ("Intel Tiger Lake-LP USB 3.2 controller");
190 case 0xa12f8086:
191 return ("Intel Sunrise Point USB 3.0 controller");
192 case 0xa1af8086:
193 return ("Intel Lewisburg USB 3.0 controller");
194 case 0xa2af8086:
195 return ("Intel Union Point USB 3.0 controller");
196 case 0xa36d8086:
197 return ("Intel Cannon Lake USB 3.1 controller");
198
199 case 0xa01b177d:
200 return ("Cavium ThunderX USB 3.0 controller");
201
202 case 0x1ada10de:
203 return ("NVIDIA TU106 USB 3.1 controller");
204
205 default:
206 break;
207 }
208
209 if ((pci_get_class(self) == PCIC_SERIALBUS)
210 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
211 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
212 return ("XHCI (generic) USB 3.0 controller");
213 }
214 return (NULL); /* dunno */
215}
216
217static int
218xhci_pci_probe(device_t self)
219{
220 const char *desc = xhci_pci_match(self);
221
222 if (desc) {
223 device_set_desc(self, desc);
224 return (BUS_PROBE_DEFAULT);
225 } else {
226 return (ENXIO);
227 }
228}
229
230static int xhci_use_msi = 1;
231TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
232static int xhci_use_msix = 1;
233TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix);
234
235static void
237{
238 struct xhci_softc *sc = _sc;
240 xhci_interrupt(sc);
241 USB_BUS_LOCK(&sc->sc_bus);
242 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
243}
244
245static int
246xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
247{
248 uint32_t temp;
249 uint32_t usb3_mask;
250 uint32_t usb2_mask;
251
252 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
253 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
254
255 temp |= set;
256 temp &= ~clear;
257
258 /* Don't set bits which the hardware doesn't support */
259 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
260 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
261
262 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
263 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
264
265 device_printf(self, "Port routing mask set to 0x%08x\n", temp);
266
267 return (0);
268}
269
270int
271xhci_pci_attach(device_t self)
272{
273 struct xhci_softc *sc = device_get_softc(self);
274 int count, err, msix_table, rid;
275 uint8_t usemsi = 1;
276 uint8_t usedma32 = 0;
277
279 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
280 RF_ACTIVE);
281 if (!sc->sc_io_res) {
282 device_printf(self, "Could not map memory\n");
283 return (ENOMEM);
284 }
285 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
286 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
287 sc->sc_io_size = rman_get_size(sc->sc_io_res);
288
289 switch (pci_get_devid(self)) {
290 case 0x10091b73: /* Fresco Logic FL1009 USB3.0 xHCI Controller */
291 case 0x8241104c: /* TUSB73x0 USB3.0 xHCI Controller */
292 sc->sc_no_deconfigure = 1;
293 break;
294 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */
295 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */
296 /* Don't use 64-bit DMA on these controllers. */
297 usedma32 = 1;
298 break;
299 case 0x10001b73: /* FL1000G */
300 /* Fresco Logic host doesn't support MSI. */
301 usemsi = 0;
302 break;
303 case 0x0f358086: /* BayTrail */
304 case 0x9c318086: /* Panther Point */
305 case 0x1e318086: /* Panther Point */
306 case 0x8c318086: /* Lynx Point */
307 case 0x8cb18086: /* Wildcat Point */
308 case 0x9cb18086: /* Broadwell Mobile Integrated */
309 /*
310 * On Intel chipsets, reroute ports from EHCI to XHCI
311 * controller and use a different IMOD value.
312 */
315 sc->sc_ctlstep = 1;
316 break;
317 default:
318 break;
319 }
320
321 if (xhci_init(sc, self, usedma32)) {
322 device_printf(self, "Could not initialize softc\n");
323 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
324 sc->sc_io_res);
325 return (ENXIO);
326 }
327
328 pci_enable_busmaster(self);
329
331
332 rid = 0;
333 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) {
334 if (msix_table == PCI_XHCI_CBMEM) {
335 sc->sc_msix_res = sc->sc_io_res;
336 } else {
337 sc->sc_msix_res = bus_alloc_resource_any(self,
338 SYS_RES_MEMORY, &msix_table, RF_ACTIVE);
339 if (sc->sc_msix_res == NULL) {
340 /* May not be enabled */
341 device_printf(self,
342 "Unable to map MSI-X table\n");
343 }
344 }
345 if (sc->sc_msix_res != NULL) {
346 count = 1;
347 if (pci_alloc_msix(self, &count) == 0) {
348 if (bootverbose)
349 device_printf(self, "MSI-X enabled\n");
350 rid = 1;
351 } else {
352 if (sc->sc_msix_res != sc->sc_io_res) {
353 bus_release_resource(self,
354 SYS_RES_MEMORY,
355 msix_table, sc->sc_msix_res);
356 }
357 sc->sc_msix_res = NULL;
358 }
359 }
360 }
361 if (rid == 0 && xhci_use_msi && usemsi) {
362 count = 1;
363 if (pci_alloc_msi(self, &count) == 0) {
364 if (bootverbose)
365 device_printf(self, "MSI enabled\n");
366 rid = 1;
367 }
368 }
369 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
370 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
371 if (sc->sc_irq_res == NULL) {
372 pci_release_msi(self);
373 device_printf(self, "Could not allocate IRQ\n");
374 /* goto error; FALLTHROUGH - use polling */
375 }
376 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
377 if (sc->sc_bus.bdev == NULL) {
378 device_printf(self, "Could not add USB device\n");
379 goto error;
380 }
381 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
382
383 switch (pci_get_vendor(self)) {
385 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor));
386 break;
388 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor));
389 break;
390 default:
391 if (bootverbose)
392 device_printf(self, "(New XHCI DeviceId=0x%08x)\n",
393 pci_get_devid(self));
394 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor),
395 "(0x%04x)", pci_get_vendor(self));
396 break;
397 }
398
399 if (sc->sc_irq_res != NULL) {
400 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
401 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
402 if (err != 0) {
403 bus_release_resource(self, SYS_RES_IRQ,
404 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
405 sc->sc_irq_res = NULL;
406 pci_release_msi(self);
407 device_printf(self, "Could not setup IRQ, err=%d\n", err);
408 sc->sc_intr_hdl = NULL;
409 }
410 }
411 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
412 if (xhci_use_polling() != 0) {
413 device_printf(self, "Interrupt polling at %dHz\n", hz);
414 USB_BUS_LOCK(&sc->sc_bus);
417 } else
418 goto error;
419 }
420
422
423 err = xhci_halt_controller(sc);
424
425 if (err == 0)
426 err = xhci_start_controller(sc);
427
428 if (err == 0)
429 err = device_probe_and_attach(sc->sc_bus.bdev);
430
431 if (err) {
432 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
433 goto error;
434 }
435 return (0);
436
437error:
438 xhci_pci_detach(self);
439 return (ENXIO);
440}
441
442static int
443xhci_pci_detach(device_t self)
444{
445 struct xhci_softc *sc = device_get_softc(self);
446
447 /* during module unload there are lots of children leftover */
448 device_delete_children(self);
449
453
454 pci_disable_busmaster(self);
455
456 if (sc->sc_irq_res && sc->sc_intr_hdl) {
457 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
458 sc->sc_intr_hdl = NULL;
459 }
460 if (sc->sc_irq_res) {
461 bus_release_resource(self, SYS_RES_IRQ,
462 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
463 sc->sc_irq_res = NULL;
464 pci_release_msi(self);
465 }
466 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) {
467 bus_release_resource(self, SYS_RES_MEMORY,
468 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res);
469 sc->sc_msix_res = NULL;
470 }
471 if (sc->sc_io_res) {
472 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
473 sc->sc_io_res);
474 sc->sc_io_res = NULL;
475 }
476
477 xhci_uninit(sc);
478
479 return (0);
480}
481
482static int
484{
485 struct xhci_softc *sc = device_get_softc(self);
486 uint32_t cparams;
487 uint32_t eecp;
488 uint32_t eec;
489 uint16_t to;
490 uint8_t bios_sem;
491
492 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
493
494 eec = -1;
495
496 /* Synchronise with the BIOS if it owns the controller. */
497 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
498 eecp += XHCI_XECP_NEXT(eec) << 2) {
499 eec = XREAD4(sc, capa, eecp);
500
502 continue;
503 bios_sem = XREAD1(sc, capa, eecp +
505 if (bios_sem == 0)
506 continue;
507 device_printf(sc->sc_bus.bdev, "waiting for BIOS "
508 "to give up control\n");
509 XWRITE1(sc, capa, eecp +
511 to = 500;
512 while (1) {
513 bios_sem = XREAD1(sc, capa, eecp +
515 if (bios_sem == 0)
516 break;
517
518 if (--to == 0) {
519 device_printf(sc->sc_bus.bdev,
520 "timed out waiting for BIOS\n");
521 break;
522 }
523 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */
524 }
525 }
526 return (0);
527}
struct @109 error
uint16_t rid
int * count
#define PCIP_SERIALBUS_USB_XHCI
#define PCIS_SERIALBUS_USB
#define PCIC_SERIALBUS
device_t bdev
Definition: usb_bus.h:101
struct mtx bus_mtx
Definition: usb_bus.h:95
char sc_vendor[16]
Definition: xhci.h:565
bus_space_tag_t sc_io_tag
Definition: xhci.h:513
xhci_port_route_t * sc_port_route
Definition: xhci.h:499
uint8_t sc_ctlstep
Definition: xhci.h:551
struct usb_bus sc_bus
Definition: xhci.h:493
void * sc_intr_hdl
Definition: xhci.h:511
struct resource * sc_io_res
Definition: xhci.h:507
uint8_t sc_no_deconfigure
Definition: xhci.h:559
bus_space_handle_t sc_io_hdl
Definition: xhci.h:514
uint16_t sc_imod_default
Definition: xhci.h:537
struct usb_callout sc_callout
Definition: xhci.h:497
bus_size_t sc_io_size
Definition: xhci.h:512
struct resource * sc_irq_res
Definition: xhci.h:508
struct resource * sc_msix_res
Definition: xhci.h:509
#define USB_BUS_LOCK(_b)
Definition: usb_core.h:45
#define USB_BUS_UNLOCK(_b)
Definition: usb_core.h:46
struct usb_endpoint_descriptor desc
Definition: usb_device.h:0
INTERFACE usb
Definition: usb_if.m:35
void usb_pause_mtx(struct mtx *mtx, int timo)
Definition: usb_util.c:135
#define usb_callout_init_mtx(c, m, f)
Definition: usbdi.h:480
#define usb_callout_reset(c,...)
Definition: usbdi.h:481
#define usb_callout_drain(c)
Definition: usbdi.h:497
usb_error_t xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
Definition: xhci.c:511
usb_error_t xhci_reset_controller(struct xhci_softc *sc)
Definition: xhci.c:484
usb_error_t xhci_halt_controller(struct xhci_softc *sc)
Definition: xhci.c:454
uint8_t xhci_use_polling(void)
Definition: xhci.c:213
void xhci_uninit(struct xhci_softc *sc)
Definition: xhci.c:644
usb_error_t xhci_start_controller(struct xhci_softc *sc)
Definition: xhci.c:304
void xhci_interrupt(struct xhci_softc *sc)
Definition: xhci.c:1603
static devclass_t xhci_devclass
Definition: xhci_pci.c:88
DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, sizeof(struct xhci_softc))
static void xhci_interrupt_poll(void *_sc)
Definition: xhci_pci.c:236
#define PCI_XHCI_VENDORID_AMD
Definition: xhci_pci.c:65
static int xhci_use_msix
Definition: xhci_pci.c:232
int xhci_pci_attach(device_t self)
Definition: xhci_pci.c:271
static const char * xhci_pci_match(device_t self)
Definition: xhci_pci.c:94
static device_probe_t xhci_pci_probe
Definition: xhci_pci.c:68
TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi)
static usb_take_controller_t xhci_pci_take_controller
Definition: xhci_pci.c:70
#define PCI_XHCI_VENDORID_INTEL
Definition: xhci_pci.c:66
MODULE_DEPEND(xhci, usb, 1, 1, 1)
__FBSDID("$FreeBSD$")
static device_detach_t xhci_pci_detach
Definition: xhci_pci.c:69
static int xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
Definition: xhci_pci.c:246
DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL)
static int xhci_use_msi
Definition: xhci_pci.c:230
static device_method_t xhci_device_methods[]
Definition: xhci_pci.c:72
#define XREAD1(sc, what, a)
Definition: xhcireg.h:207
#define PCI_XHCI_INTEL_XUSB2PR
Definition: xhcireg.h:39
#define XHCI_XECP_OS_SEM
Definition: xhcireg.h:196
#define XHCI_HCSPARAMS0
Definition: xhcireg.h:62
#define XHCI_XECP_NEXT(x)
Definition: xhcireg.h:194
#define XHCI_HCS0_XECP(x)
Definition: xhcireg.h:72
#define PCI_XHCI_INTEL_USB3PRM
Definition: xhcireg.h:42
#define XREAD4(sc, what, a)
Definition: xhcireg.h:213
#define XWRITE1(sc, what, a, x)
Definition: xhcireg.h:216
#define XHCI_IMOD_DEFAULT_LP
Definition: xhcireg.h:174
#define PCI_XHCI_CBMEM
Definition: xhcireg.h:34
#define XHCI_ID_USB_LEGACY
Definition: xhcireg.h:199
#define PCI_XHCI_INTEL_USB3_PSSEN
Definition: xhcireg.h:41
#define PCI_XHCI_INTEL_USB2PRM
Definition: xhcireg.h:40
#define XHCI_XECP_BIOS_SEM
Definition: xhcireg.h:195
#define XHCI_XECP_ID(x)
Definition: xhcireg.h:193