94 u16 sum = add1 + add2;
96 sum = (sum & 0xFF) + (sum >> 8);
122 reg_high = ((reg >> 7) & 0xFE) | 1;
160 *val = (high_bits << 8) | low_bits;
167 if (retry < max_retry)
168 DEBUGOUT(
"I2C byte read combined error - Retrying.\n");
170 DEBUGOUT(
"I2C byte read combined error.\n");
172 }
while (retry <= max_retry);
196 reg_high = (reg >> 7) & 0xFE;
232 if (retry < max_retry)
233 DEBUGOUT(
"I2C byte write combined error - Retrying.\n");
235 DEBUGOUT(
"I2C byte write combined error.\n");
237 }
while (retry <= max_retry);
292 DEBUGOUT1(
"Unable to validate PHY address 0x%04X\n",
388 "MNG_VETO bit detected.\n");
412 if (phy_id != 0xFFFF && phy_id != 0x0)
415 DEBUGOUT1(
"PHY ID HIGH is 0x%04X\n", phy_id);
438 hw->
phy.
id = (
u32)(phy_id_high << 16);
445 DEBUGOUT2(
"PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
446 phy_id_high, phy_id_low);
532 for (i = 0; i < 30; i++) {
564 "PHY reset polling failed to complete.\n");
602 u32 i, data, command;
628 DEBUGOUT(
"PHY address command did not complete, returning IXGBE_ERR_PHY\n");
658 DEBUGOUT(
"PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
668 *phy_data = (
u16)(data);
682 u32 device_type,
u16 *phy_data)
708 u32 device_type,
u16 phy_data)
782 u32 device_type,
u16 phy_data)
787 DEBUGFUNC(
"ixgbe_write_phy_reg_generic");
810 bool autoneg =
false;
813 DEBUGFUNC(
"ixgbe_setup_phy_link_generic");
822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
887 bool autoneg_wait_to_complete)
891 DEBUGFUNC(
"ixgbe_setup_phy_link_speed_generic");
976 DEBUGFUNC(
"ixgbe_get_copper_link_capabilities_generic");
1000 u32 max_time_out = 10;
1016 for (time_out = 0; time_out < max_time_out; time_out++) {
1047 bool autoneg =
false;
1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1109 u16 *firmware_version)
1113 DEBUGFUNC(
"ixgbe_get_phy_firmware_version_tnx");
1128 u16 *firmware_version)
1132 DEBUGFUNC(
"ixgbe_get_phy_firmware_version_generic");
1147 u16 phy_offset, control, eword, edata, block_crc;
1148 bool end_data =
false;
1149 u16 list_offset, data_offset;
1168 for (i = 0; i < 100; i++) {
1177 DEBUGOUT(
"PHY reset did not complete.\n");
1214 for (i = 0; i < edata; i++) {
1221 DEBUGOUT2(
"Wrote %4.4x to %4.4x\n", eword,
1253 "eeprom read at offset %d failed", data_offset);
1267 DEBUGFUNC(
"ixgbe_identify_module_generic");
1299 u8 comp_codes_1g = 0;
1300 u8 comp_codes_10g = 0;
1301 u8 oui_bytes[3] = {0, 0, 0};
1304 u16 enforce_sfp = 0;
1306 DEBUGFUNC(
"ixgbe_identify_sfp_module_generic");
1322 goto err_read_i2c_eeprom;
1333 goto err_read_i2c_eeprom;
1340 goto err_read_i2c_eeprom;
1346 goto err_read_i2c_eeprom;
1397 }
else if (comp_codes_10g &
1445 hw->
phy.
id = identifier;
1451 goto err_read_i2c_eeprom;
1458 goto err_read_i2c_eeprom;
1465 goto err_read_i2c_eeprom;
1472 switch (vendor_oui) {
1508 if (comp_codes_10g == 0 &&
1540 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1541 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1542 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1545 DEBUGOUT(
"SFP+ module not supported\n");
1577 u8 comp_codes_10g = 0;
1578 u8 comp_codes_1g = 0;
1580 DEBUGFUNC(
"ixgbe_get_supported_phy_sfp_layer_generic");
1584 return physical_layer;
1627 return physical_layer;
1642 u8 comp_codes_1g = 0;
1643 u8 comp_codes_10g = 0;
1644 u8 oui_bytes[3] = {0, 0, 0};
1645 u16 enforce_sfp = 0;
1647 u8 cable_length = 0;
1649 bool active_cable =
false;
1651 DEBUGFUNC(
"ixgbe_identify_qsfp_module_generic");
1666 goto err_read_i2c_eeprom;
1674 hw->
phy.
id = identifier;
1680 goto err_read_i2c_eeprom;
1686 goto err_read_i2c_eeprom;
1702 active_cable =
true;
1704 if (!active_cable) {
1721 (cable_length > 0) &&
1722 ((device_tech >> 4) ==
1724 active_cable =
true;
1762 goto err_read_i2c_eeprom;
1769 goto err_read_i2c_eeprom;
1776 goto err_read_i2c_eeprom;
1796 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1797 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1798 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1801 DEBUGOUT(
"QSFP module not supported\n");
1839 DEBUGFUNC(
"ixgbe_get_sfp_init_sequence_offsets");
1869 "eeprom read at offset %d failed",
1874 if ((!*list_offset) || (*list_offset == 0xFFFF))
1892 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1893 DEBUGOUT(
"SFP+ module not supported\n");
1899 (*list_offset) += 2;
1906 DEBUGOUT(
"No matching SFP+ module found\n");
1914 "eeprom read at offset %d failed", *list_offset);
1929 DEBUGFUNC(
"ixgbe_read_i2c_eeprom_generic");
1963 DEBUGFUNC(
"ixgbe_write_i2c_eeprom_generic");
1997 u8 dev_addr,
u8 *data,
bool lock)
2006 DEBUGFUNC(
"ixgbe_read_i2c_byte_generic");
2064 if (retry < max_retry)
2065 DEBUGOUT(
"I2C byte read error - Retrying.\n");
2067 DEBUGOUT(
"I2C byte read error.\n");
2069 }
while (retry <= max_retry);
2085 u8 dev_addr,
u8 *data)
2102 u8 dev_addr,
u8 *data)
2120 u8 dev_addr,
u8 data,
bool lock)
2127 DEBUGFUNC(
"ixgbe_write_i2c_byte_generic");
2167 if (retry < max_retry)
2168 DEBUGOUT(
"I2C byte write error - Retrying.\n");
2170 DEBUGOUT(
"I2C byte write error.\n");
2172 }
while (retry <= max_retry);
2191 u8 dev_addr,
u8 data)
2208 u8 dev_addr,
u8 data)
2277 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2278 i2cctl &= ~bb_en_bit;
2279 i2cctl |= data_oe_bit | clk_oe_bit;
2300 for (i = 7; i >= 0; i--) {
2322 for (i = 7; i >= 0; i--) {
2323 bit = (data >> i) & 0x1;
2359 i2cctl |= data_oe_bit;
2370 for (i = 0; i < timeout; i++) {
2380 DEBUGOUT(
"I2C ack was not received.\n");
2408 i2cctl |= data_oe_bit;
2456 "I2C data was not set to %X\n", data);
2480 *i2cctl |= clk_oe_bit;
2484 for (i = 0; i < timeout; i++) {
2511 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2540 *i2cctl &= ~data_oe_bit;
2551 *i2cctl |= data_oe_bit;
2561 "Error - I2C data was not set to %X.\n",
2584 *i2cctl |= data_oe_bit;
2617 for (i = 0; i < 9; i++) {
2684 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
bool ixgbe_mng_present(struct ixgbe_hw *hw)
#define IXGBE_READ_REG(a, reg)
#define DEBUGOUT2(S, A, B)
#define ERROR_REPORT1(S, A)
#define UNREFERENCED_1PARAMETER(_p)
#define IXGBE_WRITE_FLUSH(a)
#define IXGBE_WRITE_REG(a, reg, val)
#define ERROR_REPORT2(S, A, B)
@ IXGBE_ERROR_INVALID_STATE
s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data)
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data)
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, u16 *list_offset, u16 *data_offset)
static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version)
enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 *sff8472_data)
static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up)
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
static void ixgbe_i2c_start(struct ixgbe_hw *hw)
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data, bool lock)
s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val, bool lock)
s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data)
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data)
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, u16 *firmware_version)
static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data, bool lock)
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val, bool lock)
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data)
#define IXGBE_SFF_1GBASELX_CAPABLE
#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE
#define IXGBE_SFF_QSFP_DEVICE_TECH
#define IXGBE_SFF_VENDOR_OUI_BYTE2
#define IXGBE_SFF_VENDOR_OUI_TYCO
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT
#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE
#define IXGBE_SFF_VENDOR_OUI_BYTE1
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1
#define IXGBE_SFF_VENDOR_OUI_AVAGO
#define IXGBE_SFF_IDENTIFIER
#define IXGBE_SFF_VENDOR_OUI_INTEL
#define IXGBE_SFF_VENDOR_OUI_BYTE0
#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS
#define IXGBE_SFF_DA_PASSIVE_CABLE
#define IXGBE_SFF_CABLE_TECHNOLOGY
#define IXGBE_I2C_T_HD_STA
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2
#define IXGBE_TN_LASI_STATUS_REG
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT
#define IXGBE_SFP_DETECT_RETRIES
#define IXGBE_SFF_QSFP_CABLE_LENGTH
#define IXGBE_SFF_VENDOR_OUI_FTL
#define IXGBE_I2C_T_SU_DATA
#define IXGBE_SFF_10GBASELR_CAPABLE
#define IXGBE_SFF_QSFP_10GBE_COMP
#define IXGBE_SFF_QSFP_1GBE_COMP
#define IXGBE_SFF_DA_ACTIVE_CABLE
#define IXGBE_I2C_EEPROM_DEV_ADDR
#define IXGBE_I2C_EEPROM_DEV_ADDR2
#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING
#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT
#define IXGBE_SFF_IDENTIFIER_SFP
#define IXGBE_SFF_10GBE_COMP_CODES
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0
#define IXGBE_SFF_QSFP_CONNECTOR
#define IXGBE_SFF_CABLE_SPEC_COMP
#define IXGBE_TN_LASI_STATUS_TEMP_ALARM
#define IXGBE_I2C_T_SU_STO
#define IXGBE_SFF_1GBE_COMP_CODES
#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE
#define IXGBE_SFF_1GBASET_CAPABLE
#define IXGBE_I2C_T_SU_STA
#define IXGBE_SFF_10GBASESR_CAPABLE
#define IXGBE_SFF_1GBASESX_CAPABLE
#define IXGBE_PHYSICAL_LAYER_10GBASE_SR
#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)
#define IXGBE_MSCA_NP_ADDR_SHIFT
#define IXGBE_MDIO_PHY_1000BASET_ABILITY
#define IXGBE_ERR_SWFW_SYNC
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
#define IXGBE_MMNGC_MNG_VETO
#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG
#define IXGBE_MDIO_PHY_EXT_ABILITY
#define IXGBE_M88E1500_E_PHY_ID
#define IXGBE_MDIO_PHY_SPEED_10G
#define IXGBE_MII_AUTONEG_REG
#define IXGBE_MSCA_PHY_ADDR_SHIFT
#define IXGBE_MII_2_5GBASE_T_ADVERTISE
#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP
#define IXGBE_MII_10GBASE_T_ADVERTISE
#define IXGBE_DEV_ID_82599_T3_LOM
#define IXGBE_DATA_MASK_NL
#define IXGBE_PHYSICAL_LAYER_UNKNOWN
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS
#define IXGBE_PHYSICAL_LAYER_1000BASE_SX
#define IXGBE_GSSR_PHY1_SM
#define IXGBE_LINK_SPEED_5GB_FULL
#define IXGBE_MDIO_PHY_ID_HIGH
#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
#define IXGBE_MDIO_PHY_SPEED_1G
#define IXGBE_ERR_PHY_ADDR_INVALID
@ ixgbe_phy_sfp_ftl_active
@ ixgbe_phy_qsfp_active_unknown
@ ixgbe_phy_sfp_active_unknown
@ ixgbe_phy_sfp_passive_tyco
@ ixgbe_phy_sfp_passive_unknown
@ ixgbe_phy_sfp_unsupported
@ ixgbe_phy_qsfp_passive_unknown
#define IXGBE_M88E1543_E_PHY_ID
#define IXGBE_MDIO_PHY_10GBASET_ABILITY
#define IXGBE_MSCA_MDI_COMMAND
#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)
#define IXGBE_PHY_REVISION_MASK
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS
@ ixgbe_media_type_fiber_qsfp
#define IXGBE_GSSR_PHY0_SM
#define IXGBE_MDIO_PHY_XS_RESET
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT
@ ixgbe_sfp_type_1g_sx_core1
@ ixgbe_sfp_type_da_cu_core1
@ ixgbe_sfp_type_1g_cu_core1
@ ixgbe_sfp_type_da_act_lmt_core1
@ ixgbe_sfp_type_1g_lx_core0
@ ixgbe_sfp_type_srlr_core1
@ ixgbe_sfp_type_da_act_lmt_core0
@ ixgbe_sfp_type_1g_cu_core0
@ ixgbe_sfp_type_da_cu_core0
@ ixgbe_sfp_type_1g_lx_core1
@ ixgbe_sfp_type_not_present
@ ixgbe_sfp_type_1g_sx_core0
@ ixgbe_sfp_type_srlr_core0
#define IXGBE_MDIO_PHY_SPEED_100M
#define IXGBE_MDIO_PHY_XS_DEV_TYPE
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE
#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL
#define IXGBE_LINK_SPEED_10_FULL
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD
#define IXGBE_ERR_OVERTEMP
#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT
#define IXGBE_I2CCTL_BY_MAC(_hw)
#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG
#define IXGBE_CONTROL_MASK_NL
#define IXGBE_MDIO_AUTO_NEG_CONTROL
#define IXGBE_CONTROL_SOL_NL
#define IXGBE_CONTROL_EOL_NL
#define IXGBE_MDIO_TX_VENDOR_ALARMS_3
#define IXGBE_MII_5GBASE_T_ADVERTISE
#define IXGBE_MDIO_PHY_XS_CONTROL
#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw)
#define IXGBE_MII_100BASE_T_ADVERTISE
#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
#define IXGBE_MDIO_PHY_ID_LOW
#define IXGBE_LINK_SPEED_100_FULL
#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE
#define IXGBE_LINK_SPEED_1GB_FULL
#define IXGBE_MDIO_PHY_SPEED_ABILITY
#define IXGBE_MII_AUTONEG_ADVERTISE_REG
#define IXGBE_MDIO_COMMAND_TIMEOUT
#define IXGBE_I2C_BB_EN_BY_MAC(_hw)
#define IXGBE_MSCA_DEV_TYPE_SHIFT
#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw)
#define IXGBE_MSRWD_READ_DATA_SHIFT
#define IXGBE_LINK_SPEED_2_5GB_FULL
#define IXGBE_MII_100BASE_T_ADVERTISE_HALF
#define IXGBE_PHY_INIT_OFFSET_NL
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT
#define IXGBE_LINK_SPEED_10GB_FULL
#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)
#define IXGBE_PHY_INIT_END_NL
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS
#define IXGBE_MII_1GBASE_T_ADVERTISE
#define IXGBE_MAX_PHY_ADDR
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR
#define IXGBE_MII_RESTART
#define IXGBE_MSCA_ADDR_CYCLE
#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)
#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
#define IXGBE_ERR_SFP_NOT_PRESENT
#define IXGBE_PHYSICAL_LAYER_1000BASE_T
#define IXGBE_CONTROL_SHIFT_NL
#define IXGBE_ERR_SFP_NOT_SUPPORTED
#define IXGBE_MII_AUTONEG_XNP_TX_REG
#define IXGBE_ERR_RESET_FAILED
ixgbe_link_speed phy_speed
struct ixgbe_eeprom_operations ops
s32(* read)(struct ixgbe_hw *, u16, u16 *)
struct ixgbe_mac_info mac
struct ixgbe_bus_info bus
bool allow_unsupported_sfp
struct ixgbe_eeprom_info eeprom
struct ixgbe_phy_info phy
struct ixgbe_mac_operations ops
s32(* acquire_swfw_sync)(struct ixgbe_hw *, u32)
void(* release_swfw_sync)(struct ixgbe_hw *, u32)
void(* set_lan_id)(struct ixgbe_hw *)
enum ixgbe_media_type(* get_media_type)(struct ixgbe_hw *)
ixgbe_link_speed speeds_supported
ixgbe_autoneg_advertised autoneg_advertised
struct ixgbe_phy_operations ops
enum ixgbe_sfp_type sfp_type
s32(* read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, u8 *value)
s32(* read_i2c_eeprom)(struct ixgbe_hw *, u8, u8 *)
s32(* setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool)
s32(* write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8)
s32(* read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *)
s32(* check_overtemp)(struct ixgbe_hw *)
s32(* write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, u8 value)
s32(* get_firmware_version)(struct ixgbe_hw *, u16 *)
s32(* reset)(struct ixgbe_hw *)
s32(* identify)(struct ixgbe_hw *)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
s32(* read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *)
void(* i2c_bus_clear)(struct ixgbe_hw *)
s32(* write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16)
s32(* read_reg)(struct ixgbe_hw *, u32, u32, u16 *)
s32(* setup_link)(struct ixgbe_hw *)
s32(* read_i2c_sff8472)(struct ixgbe_hw *, u8, u8 *)
s32(* write_i2c_eeprom)(struct ixgbe_hw *, u8, u8)
s32(* write_reg)(struct ixgbe_hw *, u32, u32, u16)
s32(* identify_sfp)(struct ixgbe_hw *)