147 "port expander access failed with %d\n", status);
166 "port expander access failed with %d\n", status);
196 reg &= ~IXGBE_PE_BIT1;
204 reg &= ~IXGBE_PE_BIT1;
231 "CS4227 reset did not complete.");
239 "CS4227 EEPROM did not load successfully.");
261 "semaphore failed with %d", status);
287 "semaphore failed with %d", status);
296 "CS4227 reset failed: %d", status);
310 "semaphore failed with %d", status);
413 memset(&hic, 0,
sizeof(hic));
428 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
436 }
while (retries > 0);
483 hw->
phy.
revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
523 u32 device_type,
u16 *phy_data)
530 u32 device_type,
u16 phy_data)
715 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
891 u32 reg, high_pri_tc;
897 reg &= ~IXGBE_DMACR_DMAC_EN;
910 reg &= ~IXGBE_DMACR_DMACWT_MASK;
913 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
939 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
963 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
965 if (tc < hw->mac.dmac_config.num_tcs) {
972 if (rx_pb_size > pb_headroom)
973 rx_pb_size = rx_pb_size - pb_headroom;
978 reg |= (rx_pb_size > maxframe_size_kb) ?
979 rx_pb_size : maxframe_size_kb;
1000 reg &= ~IXGBE_DMACR_DMAC_EN;
1026 DEBUGFUNC(
"ixgbe_init_eeprom_params_X550");
1038 DEBUGOUT2(
"Eeprom params: type = %d, size = %d\n",
1064 pfflp |= (1ULL << pool);
1066 pfflp &= ~(1ULL << pool);
1080 bool enable,
int vf)
1082 int vf_target_reg = vf >> 3;
1086 DEBUGFUNC(
"ixgbe_set_ethertype_anti_spoofing_X550");
1090 pfvfspoof |= (1 << vf_target_shift);
1092 pfvfspoof &= ~(1 << vf_target_shift);
1139 u32 device_type,
u32 data)
1168 "Failed to write, error %x\n", error);
1185 u32 device_type,
u32 *data)
1211 "Failed to read, error %x\n", error);
1245 DEBUGOUT1(
"Issuing host interface command failed with Status = %d\n",
1252 DEBUGOUT1(
"Host interface command returned 0x%08x , returning IXGBE_ERR_FW_RESP_INVALID\n",
1257 DEBUGOUT(
"Returning IXGBE_ERR_TOKEN_RETRY\n");
1287 DEBUGOUT(
"Put PHY Token host interface command failed");
1300 u32 device_type,
u32 data)
1306 memset(&write_cmd, 0,
sizeof(write_cmd));
1330 u32 device_type,
u32 *data)
1339 memset(&hic, 0,
sizeof(hic));
1412 u32 idx, reg, num_qs, start_q, bitmask;
1421 bitmask = 0x000000FF;
1426 bitmask = 0x0000000F;
1430 bitmask = 0x00000003;
1433 start_q = vf * num_qs;
1438 reg |= (bitmask << (start_q % 32));
1453 u32 i, j, reg, q, shift, vf, idx;
1473 for (i = 0; i < 4; i++) {
1481 for (j = 0; j < 32 && wqbr; j++) {
1483 if (!(wqbr & (1 << j)))
1494 vf_bitmap[idx] |= (1 << (vf % 32));
1510 DEBUGFUNC(
"ixgbe_get_media_type_X550em");
1556 DEBUGFUNC(
"ixgbe_supported_sfp_modules_X550em");
1596 DEBUGFUNC(
"ixgbe_identify_sfp_module_X550em");
1618 DEBUGFUNC(
"ixgbe_setup_sfp_modules_X550em");
1648 DEBUGOUT(
"Auto-negotiation did not complete\n");
1666 DEBUGOUT(
"Auto-negotiation did not complete\n");
1689 u32 lval, sval, flx_val;
1698 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1699 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1729 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1731 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1758 u32 lval, sval, flx_val;
1767 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1768 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1771 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1784 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1785 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1804 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1806 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1829 DEBUGFUNC(
"ixgbe_init_mac_link_ops_X550em");
1889 DEBUGFUNC(
"ixgbe_get_link_capabilities_X550em");
2189 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2192 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2193 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2218 memset(store, 0,
sizeof(store));
2412 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2441 bool link_up =
false;
2449 DEBUGOUT1(
"Failed to stop adapter, STATUS = %d\n", status);
2461 DEBUGOUT1(
"Failed to initialize PHY ops, STATUS = %d\n",
2466 DEBUGOUT(
"Returning from reset HW due to PHY init failure\n");
2474 DEBUGOUT1(
"Failed to start the external PHY, STATUS = %d\n",
2511 "semaphore failed with %d", status);
2520 for (i = 0; i < 10; i++) {
2529 DEBUGOUT(
"Reset polling failed to complete.\n");
2539 hw->
mac.
flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2559 DEBUGOUT1(
"Reset HW failed, STATUS = %d\n", status);
2593 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2633 bool autoneg_wait_to_complete)
2636 u16 reg_slice, reg_val;
2637 bool setup_linear =
false;
2689 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2690 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2691 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2692 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2727 bool autoneg_wait_to_complete)
2731 bool setup_linear =
false;
2732 u32 reg_slice, reg_phy_int, slice_offset;
2776 DEBUGOUT(
"Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2853 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2854 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2855 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2866 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2867 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2868 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2916 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2917 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3069 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3070 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3177 u32 current_word = 0;
3182 DEBUGFUNC(
"ixgbe_read_ee_hostif_buffer_X550");
3187 DEBUGOUT(
"EEPROM read buffer - semaphore failed\n");
3195 words_to_read = words;
3213 DEBUGOUT(
"Host interface command failed\n");
3217 for (i = 0; i < words_to_read; i++) {
3222 data[current_word] = (
u16)(value & 0xffff);
3225 if (i < words_to_read) {
3227 data[current_word] = (
u16)(value & 0xffff);
3231 words -= words_to_read;
3253 DEBUGFUNC(
"ixgbe_write_ee_hostif_data_X550");
3269 DEBUGOUT2(
"for offset %04x failed with status %d\n",
3275 DEBUGOUT2(
"for offset %04x host interface return status %02x\n",
3296 DEBUGFUNC(
"ixgbe_write_ee_hostif_X550");
3303 DEBUGOUT(
"write ee hostif failed to get semaphore");
3325 DEBUGFUNC(
"ixgbe_write_ee_hostif_buffer_X550");
3330 DEBUGOUT(
"EEPROM write buffer - semaphore failed\n");
3334 for (i = 0; i < words; i++) {
3339 DEBUGOUT(
"Eeprom buffered write failed\n");
3370 bufsz =
sizeof(buf) /
sizeof(buf[0]);
3376 DEBUGOUT(
"Failed to read EEPROM image\n");
3381 if (buffer_size < ptr)
3383 local_buffer = &buffer[ptr];
3391 length = local_buffer[0];
3399 if (buffer && ((
u32)start + (
u32)
length > buffer_size))
3403 if (i == bufsz && !buffer) {
3413 DEBUGOUT(
"Failed to read EEPROM image\n");
3417 *csum += local_buffer[i];
3436 u16 pointer, i, size;
3438 DEBUGFUNC(
"ixgbe_calc_eeprom_checksum_X550");
3448 DEBUGOUT(
"Failed to read EEPROM image\n");
3451 local_buffer = eeprom_ptrs;
3455 local_buffer = buffer;
3464 checksum += local_buffer[i];
3474 pointer = local_buffer[i];
3477 if (pointer == 0xFFFF || pointer == 0 ||
3495 buffer, buffer_size);
3502 return (
s32)checksum;
3528 u16 read_checksum = 0;
3530 DEBUGFUNC(
"ixgbe_validate_eeprom_checksum_X550");
3546 checksum = (
u16)(status & 0xffff);
3556 if (read_checksum != checksum) {
3559 "Invalid EEPROM checksum");
3564 *checksum_val = checksum;
3582 DEBUGFUNC(
"ixgbe_update_eeprom_checksum_X550");
3598 checksum = (
u16)(status & 0xffff);
3644 u16 ext_ability = 0;
3646 DEBUGFUNC(
"ixgbe_get_supported_physical_layer_X550em");
3704 return physical_layer;
3735 u32 rxctrl, pfdtxgswc;
3745 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3765 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3782 u16 an_10g_cntl_reg, autoneg_reg, speed;
3927 u32 pause, asm_dir, reg_val;
3934 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3970 "Flow control param set incorrectly\n");
4016 u32 link_s1, lp_an_page_low, an_cntl_1;
4028 "Flow control autoneg is disabled");
4045 DEBUGOUT(
"Auto-Negotiation did not complete\n");
4058 DEBUGOUT(
"Auto-Negotiation did not complete\n");
4067 DEBUGOUT(
"Auto-Negotiation did not complete\n");
4117 "Flow control autoneg is disabled");
4131 DEBUGOUT(
"Auto-Negotiation did not complete\n");
4163 DEBUGFUNC(
"ixgbe_setup_fc_backplane_x550em_a");
4168 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4184 DEBUGOUT(
"Auto-Negotiation did not complete\n");
4208 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4226 "Flow control param set incorrectly\n");
4255 esdp &= ~IXGBE_ESDP_SDP1;
4271 DEBUGFUNC(
"ixgbe_acquire_swfw_sync_X550em");
4292 DEBUGFUNC(
"ixgbe_release_swfw_sync_X550em");
4309 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4313 DEBUGFUNC(
"ixgbe_acquire_swfw_sync_X550a");
4320 DEBUGOUT1(
"Could not acquire SWFW semaphore, Status = %d\n",
4329 DEBUGOUT1(
"Could not acquire PHY token, Status = %d\n",
4339 DEBUGOUT1(
"Unable to retry acquiring the PHY token, Status = %d\n",
4345 DEBUGOUT1(
"Semaphore acquisition retries failed!: PHY ID = 0x%08X\n",
4359 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4361 DEBUGFUNC(
"ixgbe_release_swfw_sync_X550a");
4382 u32 device_type,
u16 *phy_data)
4410 u32 device_type,
u16 phy_data)
4468 bool autoneg_wait_to_complete)
4473 bool link_up =
false;
4475 DEBUGFUNC(
"ixgbe_setup_mac_link_t_X550em");
4495 for (i = 0; i < 10; i++) {
4521 bool *link_up,
bool link_up_wait_to_complete)
4524 u16 i, autoneg_status = 0;
4530 link_up_wait_to_complete);
4541 for (i = 0; i < 2; i++) {
4616 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4640 u8 build,
u8 sub,
u16 len,
const char *driver_ver)
4648 if ((len == 0) || (driver_ver == NULL) ||
4673 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 data)
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data)
s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
bool ixgbe_mng_present(struct ixgbe_hw *hw)
s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, u32 timeout)
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, u32 length, u32 timeout, bool return_data)
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
#define IXGBE_READ_REG(a, reg)
#define IXGBE_BE32_TO_CPU
#define IXGBE_READ_REG_ARRAY(a, reg, offset)
#define IXGBE_CPU_TO_BE32
#define DEBUGOUT2(S, A, B)
#define ERROR_REPORT1(S, A)
#define UNREFERENCED_1PARAMETER(_p)
#define IXGBE_WRITE_FLUSH(a)
#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
#define IXGBE_WRITE_REG(a, reg, val)
#define IXGBE_CPU_TO_LE16
#define IXGBE_CPU_TO_BE16
#define ERROR_REPORT2(S, A, B)
@ IXGBE_ERROR_INVALID_STATE
@ IXGBE_ERROR_UNSUPPORTED
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val, bool lock)
s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val, bool lock)
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
#define IXGBE_CS4227_EDC_MODE_SR
#define IXGBE_CS4227_RESET_HOLD
#define IXGBE_CS4227_EEPROM_LOAD_OK
#define IXGBE_CS4227_RESET_PENDING
#define IXGBE_CS4227_RETRIES
#define IXGBE_CS4227_SCRATCH
#define IXGBE_CS4227_CHECK_DELAY
#define IXGBE_CS4227_EFUSE_PDF_SKU
#define IXGBE_CS4227_EFUSE_STATUS
#define IXGBE_CS4227_EEPROM_STATUS
#define IXGBE_CS4227_EDC_MODE_CX1
#define IXGBE_CS4227_LINE_SPARE24_LSB
#define IXGBE_CS4227_RESET_COMPLETE
#define IXGBE_CS4223_SKU_ID
#define IXGBE_CS4227_RESET_DELAY
#define FW_WRITE_SHADOW_RAM_CMD
#define IXGBE_SB_IOSF_INDIRECT_CTRL
#define FW_CEM_RESP_STATUS_SUCCESS
#define FW_READ_SHADOW_RAM_CMD
#define IXGBE_DEV_ID_X550EM_A_SFP
#define FW_INT_PHY_REQ_READ
#define FW_PHY_ACT_LINK_SPEED_100
#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT
#define IXGBE_MDIO_PHY_1000BASET_ABILITY
#define FW_PHY_ACT_GET_LINK_INFO_FC_RX
#define IXGBE_ERR_SWFW_SYNC
#define IXGBE_RXCTRL_RXEN
#define IXGBE_DMACRXT_100M
#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK
#define FW_PHY_ACT_GET_LINK_INFO
#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN
#define IXGBE_KRM_TX_COEFF_CTRL_1(P)
#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG
#define IXGBE_MDIO_PHY_EXT_ABILITY
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX
#define FW_PHY_ACT_INIT_PHY
#define IXGBE_MDIO_ZERO_DEV_TYPE
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK
#define FW_PHY_INFO_ID_LO_MASK
#define IXGBE_ESDP_SDP1_NATIVE
#define IXGBE_RDRXCTL_MBINTEN
#define FW_PHY_INFO_SPEED_MASK
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G
#define IXGBE_RXPBSIZE_SHIFT
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN
#define FW_PHY_ACT_REQ_CMD
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P)
#define IXGBE_X557_MAX_LED_INDEX
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT
#define IXGBE_PHYSICAL_LAYER_10GBASE_T
#define IXGBE_DEV_ID_X550EM_A_QSFP
#define IXGBE_DEV_ID_X550EM_A_KR
#define IXGBE_DEV_ID_X550EM_A_SGMII
#define IXGBE_EEPROM_LAST_WORD
#define IXGBE_PHYSICAL_LAYER_100BASE_TX
#define IXGBE_HI_COMMAND_TIMEOUT
@ ixgbe_bus_type_internal
#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX
#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF
#define IXGBE_GSSR_I2C_MASK
#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK
#define IXGBE_DEV_ID_X550EM_A_1G_T_L
#define IXGBE_PCIE_CONFIG0_PTR
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)
#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE
#define IXGBE_MHADD_MFS_SHIFT
#define IXGBE_OPTION_ROM_PTR
#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D
#define FW_PHY_ACT_GET_LINK_INFO_TEMP
#define IXGBE_DCB_MAX_TRAFFIC_CLASS
#define IXGBE_PHYSICAL_LAYER_10BASE_T
#define IXGBE_DEV_ID_X550EM_X_10G_T
#define IXGBE_MRQC_VMDQRT4TCEN
#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX
#define IXGBE_ERR_TOKEN_RETRY
#define FW_WRITE_SHADOW_RAM_LEN
#define FW_CEM_MAX_RETRIES
#define IXGBE_PHYSICAL_LAYER_UNKNOWN
#define FW_PHY_ACT_GET_LINK_INFO_FC_TX
#define IXGBE_PCIE_ANALOG_PTR_X550
#define IXGBE_PCIE_CONFIG1_PTR
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL
#define FW_SHADOW_RAM_DUMP_LEN
#define IXGBE_GSSR_PHY1_SM
#define IXGBE_LINK_SPEED_5GB_FULL
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G
#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX
#define FW_READ_SHADOW_RAM_LEN
#define IXGBE_DMACRXT_10G
#define IXGBE_PHYSICAL_LAYER_10GBASE_KR
#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK
#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP
#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN
#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
#define IXGBE_KRM_LINK_CTRL_1(P)
#define IXGBE_HLREG0_MDCSPD
#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT
#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN
@ ixgbe_bus_speed_unknown
#define IXGBE_RXPBSIZE(_i)
#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN
#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG
#define IXGBE_DMACR_EN_MNG_IND
#define IXGBE_ERR_HOST_INTERFACE_COMMAND
#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN
#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
#define IXGBE_DMATXCTL_MBINTEN
#define IXGBE_LINK_SPEED_UNKNOWN
#define IXGBE_ERR_PHY_ADDR_INVALID
#define IXGBE_ERR_INVALID_LINK_SETTINGS
#define IXGBE_DEV_ID_X550EM_A_1G_T
#define IXGBE_FUSES0_REV_MASK
#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS
#define FW_PHY_TOKEN_REQ_CMD
#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX
#define FW_PHY_ACT_SETUP_LINK_HP
#define IXGBE_MDIO_PHY_10GBASET_ABILITY
#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB
#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN
#define IXGBE_KRM_PMD_FLX_MASK_ST20(P)
#define FW_PHY_ACT_RETRIES
#define IXGBE_NOT_IMPLEMENTED
@ ixgbe_eeprom_uninitialized
#define FW_PHY_ACT_LINK_SPEED_2_5G
#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2
#define FW_PHY_ACT_LINK_SPEED_10
#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK
#define IXGBE_MRQC_VMDQRT8TCEN
#define FW_PHY_ACT_REQ_LEN
#define IXGBE_DEV_ID_X550EM_A_SFP_N
#define IXGBE_WQBR_RX(_i)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN
#define IXGBE_ESDP_SDP0_NATIVE
#define IXGBE_MDIO_AUTO_NEG_STATUS
#define IXGBE_AUTO_NEG_LP_STATUS
#define IXGBE_DEV_ID_X550EM_X_SFP
#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA
#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART
#define IXGBE_GSSR_EEP_SM
#define IXGBE_GSSR_TOKEN_SM
#define IXGBE_KRM_LINK_S1(P)
#define FW_PHY_ACT_DATA_COUNT
#define IXGBE_PHY_REVISION_MASK
#define IXGBE_ESDP_SDP0_DIR
@ ixgbe_media_type_unknown
@ ixgbe_media_type_copper
@ ixgbe_media_type_backplane
#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL
#define IXGBE_GSSR_PHY0_SM
#define IXGBE_KRM_AN_CNTL_1(P)
#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE
#define FW_PHY_ACT_LINK_SPEED_10G
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B
#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN
#define FW_PHY_ACT_GET_PHY_INFO
@ ixgbe_sfp_type_1g_sx_core1
@ ixgbe_sfp_type_da_cu_core1
@ ixgbe_sfp_type_1g_cu_core1
@ ixgbe_sfp_type_da_act_lmt_core1
@ ixgbe_sfp_type_1g_lx_core0
@ ixgbe_sfp_type_srlr_core1
@ ixgbe_sfp_type_da_act_lmt_core0
@ ixgbe_sfp_type_1g_cu_core0
@ ixgbe_sfp_type_da_cu_core0
@ ixgbe_sfp_type_1g_lx_core1
@ ixgbe_sfp_type_not_present
@ ixgbe_sfp_type_1g_sx_core0
@ ixgbe_sfp_type_srlr_core0
#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT
#define IXGBE_EEPROM_WORD_SIZE_SHIFT
#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN
#define FW_PHY_ACT_SETUP_LINK_AN
#define IXGBE_GSSR_SW_MNG_SM
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT
#define IXGBE_RDRXCTL_MDP_EN
#define IXGBE_KRM_SGMII_CTRL(P)
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE
#define FW_PHY_TOKEN_RETRY
#define IXGBE_ERR_FW_RESP_INVALID
#define IXGBE_PHYSICAL_LAYER_2500BASE_KX
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G
#define IXGBE_DEV_ID_X550EM_A_SGMII_L
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G
#define IXGBE_LINK_SPEED_10_FULL
#define IXGBE_PCIE_CONFIG_SIZE
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD
#define IXGBE_ERR_FC_NOT_NEGOTIATED
#define IXGBE_ERR_OVERTEMP
#define IXGBE_MDIO_GLOBAL_INT_MASK
#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN
#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK
#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG
#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT
#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT
#define IXGBE_ESDP_SDP1_DIR
#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE
#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P)
#define IXGBE_DEV_ID_X550EM_X_KR
#define IXGBE_IXGBE_PCIE_GENERAL_SIZE
#define NVM_INIT_CTRL_3_D10GMP_PORT1
#define IXGBE_MDIO_TX_VENDOR_ALARMS_3
#define FW_PHY_ACT_SETUP_LINK
#define IXGBE_DEV_ID_X550EM_X_KX4
#define FW_PHY_ACT_PHY_SW_RESET
#define IXGBE_LINK_SPEED_100_FULL
#define FW_PHY_TOKEN_REQ_LEN
#define IXGBE_MRQC_VMDQRSS32EN
#define FW_NVM_DATA_OFFSET
#define FW_CEM_CMD_RESERVED
#define FW_INT_PHY_REQ_CMD
#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN
#define FW_INT_PHY_REQ_WRITE
#define IXGBE_ERR_INVALID_ARGUMENT
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
#define FW_INT_PHY_REQ_LEN
#define IXGBE_SB_IOSF_INDIRECT_DATA
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE
#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE
#define NVM_INIT_CTRL_3_LPLU
#define IXGBE_PFVFSPOOF(_i)
#define IXGBE_LINK_SPEED_1GB_FULL
#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK
#define IXGBE_KRM_PMD_DFX_BURNIN(P)
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS
#define IXGBE_MDIO_GLOBAL_ALARM_1_INT
#define IXGBE_MDIO_COMMAND_TIMEOUT
#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4
#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P)
#define IXGBE_SB_IOSF_TARGET_KR_PHY
#define IXGBE_MDIO_GLOBAL_ALARM_1
#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL
#define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE
#define IXGBE_ERR_LINK_SETUP
#define FW_PHY_ACT_LINK_SPEED_1G
#define FW_DEFAULT_CHECKSUM
#define IXGBE_EEPROM_CHECKSUM
#define IXGBE_X557_LED_PROVISIONING
#define IXGBE_DEV_ID_X550EM_A_KR_L
#define FW_SHADOW_RAM_DUMP_CMD
#define IXGBE_FWSM_FW_NVM_RECOVERY_MODE
#define IXGBE_LINK_SPEED_2_5GB_FULL
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT
#define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE
#define IXGBE_NW_MNG_IF_SEL
#define IXGBE_LINK_SPEED_10GB_FULL
#define IXGBE_DMACR_HIGH_PRI_TC_MASK
#define FW_PHY_ACT_SETUP_LINK_EEE
#define FW_CEM_CMD_DRIVER_INFO
#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR
#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK
#define IXGBE_FUSES0_GROUP(_i)
#define FW_PHY_ACT_LINK_SPEED_5G
#define IXGBE_FWSM_BY_MAC(_hw)
#define FW_MAX_READ_BUFFER_SIZE
#define IXGBE_DMACR_DMAC_EN
#define IXGBE_MDIO_GLOBAL_FAULT_MSG
#define IXGBE_PFDTXGSWC_VT_LBEN
#define FW_CEM_CMD_DRIVER_INFO_LEN
#define IXGBE_DEV_ID_X550EM_A_10G_T
#define FW_DISABLE_RXEN_LEN
#define IXGBE_RXPBSIZE_MASK
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR
#define IXGBE_MDIO_AUTO_NEG_VEN_LSC
#define FW_PHY_INFO_ID_HI_MASK
#define FW_PHY_ACT_FORCE_LINK_DOWN
#define IXGBE_WQBR_TX(_i)
#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS
#define IXGBE_PCIE_GENERAL_PTR
#define IXGBE_GSSR_SHARED_I2C_SM
#define IXGBE_DEV_ID_X550EM_X_1G_T
#define IXGBE_SB_IOSF_CTRL_BUSY
#define IXGBE_DEV_ID_X550EM_A_QSFP_N
#define IXGBE_CTRL_LNK_RST
#define IXGBE_MRQC_MRQE_MASK
#define IXGBE_CTRL_RST_MASK
#define FW_PHY_TOKEN_RETRIES
#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM
#define NVM_INIT_CTRL_3_D10GMP_PORT0
#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX
@ ixgbe_bus_width_unknown
#define IXGBE_DMATXCTL_MDP_EN
#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT
#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN
#define IXGBE_MDIO_GLOBAL_RES_PR_10
#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT
#define IXGBE_ERR_SFP_NOT_PRESENT
#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D
#define IXGBE_PHYSICAL_LAYER_1000BASE_T
#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT
#define IXGBE_EEC_SIZE_SHIFT
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL
#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG
#define IXGBE_DEV_ID_X550EM_X_XFI
#define IXGBE_ERR_SFP_NOT_SUPPORTED
#define IXGBE_ERR_RESET_FAILED
#define IXGBE_X557_LED_MANUAL_SET_MASK
#define IXGBE_AUTO_NEG_LP_1000BASE_CAP
#define FW_DISABLE_RXEN_CMD
#define IXGBE_ERR_EEPROM_CHECKSUM
s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
static s32 ixgbe_setup_eee_fw(struct ixgbe_hw *hw, bool enable_eee)
s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 data)
s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
static s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, u16 size, u16 *csum, u16 *buffer, u32 buffer_size)
s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 *data)
s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, unsigned int pool)
void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask)
static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 data)
ixgbe_link_speed phy_speed
s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data)
s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, u16 offset, u16 words, u16 *data)
s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, u8 sub, u16 len, const char *driver_ver)
enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
static s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
static s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, ixgbe_link_speed speed)
static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait)
s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 *data)
static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, bool enable, int vf)
static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait)
static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
static const struct @21 ixgbe_fw_map[]
s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, u32(*data)[FW_PHY_ACT_DATA_COUNT])
s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data)
static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask)
static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
enum ixgbe_bus_width width
enum ixgbe_bus_speed speed
enum ixgbe_eeprom_type type
struct ixgbe_eeprom_operations ops
s32(* read_buffer)(struct ixgbe_hw *, u16, u16, u16 *)
s32(* write_buffer)(struct ixgbe_hw *, u16, u16, u16 *)
s32(* update_checksum)(struct ixgbe_hw *)
s32(* init_params)(struct ixgbe_hw *)
s32(* write)(struct ixgbe_hw *, u16, u16)
s32(* read)(struct ixgbe_hw *, u16, u16 *)
s32(* calc_checksum)(struct ixgbe_hw *)
s32(* validate_checksum)(struct ixgbe_hw *, u16 *)
enum ixgbe_fc_mode current_mode
enum ixgbe_fc_mode requested_mode
char driver_string[FW_CEM_DRIVER_VERSION_SIZE]
union ixgbe_hic_hdr::@3 cmd_or_resp
__be32 data[FW_PHY_ACT_DATA_COUNT]
struct ixgbe_mac_info mac
struct ixgbe_link_info link
struct ixgbe_bus_info bus
struct ixgbe_eeprom_info eeprom
struct ixgbe_phy_info phy
struct ixgbe_link_operations ops
s32(* read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val)
s32(* write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val)
s32(* write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val)
s32(* read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val)
u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
bool thermal_sensor_enabled
struct ixgbe_dmac_config dmac_config
struct ixgbe_mac_operations ops
s32(* get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *)
s32(* reset_hw)(struct ixgbe_hw *)
s32(* prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *)
s32(* dmac_config_tcs)(struct ixgbe_hw *hw)
s32(* acquire_swfw_sync)(struct ixgbe_hw *, u32)
s32(* set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, const char *)
s32(* led_off)(struct ixgbe_hw *, u32)
s32(* get_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* init_rx_addrs)(struct ixgbe_hw *)
s32(* setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool)
void(* release_swfw_sync)(struct ixgbe_hw *, u32)
s32(* setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool)
void(* set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed)
s32(* init_thermal_sensor_thresh)(struct ixgbe_hw *hw)
s32(* write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool)
void(* get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map)
s32(* get_thermal_sensor_data)(struct ixgbe_hw *)
s32(* prot_autoc_write)(struct ixgbe_hw *, u32, bool)
s32(* setup_sfp)(struct ixgbe_hw *)
bool(* fw_recovery_mode)(struct ixgbe_hw *hw)
s32(* disable_sec_rx_path)(struct ixgbe_hw *)
s32(* enable_sec_rx_path)(struct ixgbe_hw *)
s32(* init_led_link_act)(struct ixgbe_hw *)
s32(* bypass_set)(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action)
void(* enable_mdd)(struct ixgbe_hw *hw)
s32(* get_san_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* setup_eee)(struct ixgbe_hw *hw, bool enable_eee)
void(* disable_rx)(struct ixgbe_hw *hw)
void(* disable_tx_laser)(struct ixgbe_hw *)
void(* fc_autoneg)(struct ixgbe_hw *)
s32(* led_on)(struct ixgbe_hw *, u32)
s32(* setup_fc)(struct ixgbe_hw *)
s32(* dmac_config)(struct ixgbe_hw *hw)
s32(* get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
void(* set_lan_id)(struct ixgbe_hw *)
void(* disable_mdd)(struct ixgbe_hw *hw)
s32(* read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *)
void(* enable_tx_laser)(struct ixgbe_hw *)
void(* flap_tx_laser)(struct ixgbe_hw *)
enum ixgbe_media_type(* get_media_type)(struct ixgbe_hw *)
s32(* set_san_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* get_bus_info)(struct ixgbe_hw *)
s32(* get_fcoe_boot_status)(struct ixgbe_hw *, u16 *)
void(* set_source_address_pruning)(struct ixgbe_hw *, bool, unsigned int)
bool(* bypass_valid_rd)(u32 in_reg, u32 out_reg)
void(* set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int)
s32(* stop_adapter)(struct ixgbe_hw *)
s32(* bypass_rd_eep)(struct ixgbe_hw *hw, u32 addr, u8 *value)
void(* restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf)
void(* mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap)
u64(* get_supported_physical_layer)(struct ixgbe_hw *)
s32(* dmac_update_tcs)(struct ixgbe_hw *hw)
s32(* bypass_rw)(struct ixgbe_hw *hw, u32 cmd, u32 *status)
enum ixgbe_media_type media_type
ixgbe_link_speed eee_speeds_advertised
ixgbe_link_speed speeds_supported
ixgbe_autoneg_advertised autoneg_advertised
struct ixgbe_phy_operations ops
ixgbe_link_speed eee_speeds_supported
enum ixgbe_sfp_type sfp_type
s32(* setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool)
s32(* check_overtemp)(struct ixgbe_hw *)
s32(* init)(struct ixgbe_hw *)
s32(* get_firmware_version)(struct ixgbe_hw *, u16 *)
s32(* handle_lasi)(struct ixgbe_hw *hw)
s32(* reset)(struct ixgbe_hw *)
s32(* identify)(struct ixgbe_hw *)
s32(* set_phy_power)(struct ixgbe_hw *, bool on)
s32(* read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *)
s32(* write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16)
s32(* read_reg)(struct ixgbe_hw *, u32, u32, u16 *)
s32(* setup_link)(struct ixgbe_hw *)
s32(* enter_lplu)(struct ixgbe_hw *)
s32(* setup_internal_link)(struct ixgbe_hw *)
s32(* write_reg)(struct ixgbe_hw *, u32, u32, u16)
s32(* identify_sfp)(struct ixgbe_hw *)
struct ixgbe_hic_hdr2_req req
struct ixgbe_hic_hdr2_rsp rsp