42#define IXGBE_82598_MAX_TX_QUEUES 32
43#define IXGBE_82598_MAX_RX_QUEUES 64
44#define IXGBE_82598_RAR_ENTRIES 16
45#define IXGBE_82598_MC_TBL_SIZE 128
46#define IXGBE_82598_VFT_TBL_SIZE 128
47#define IXGBE_82598_RX_PB_SIZE 512
54 bool autoneg_wait_to_complete);
57 bool link_up_wait_to_complete);
60 bool autoneg_wait_to_complete);
63 bool autoneg_wait_to_complete);
68 u32 headroom,
int strategy);
109 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
197 u16 list_offset, data_offset;
271 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
304 DEBUGFUNC(
"ixgbe_get_link_capabilities_82598");
434 DEBUGOUT(
"Invalid water mark configuration\n");
512 DEBUGOUT(
"Flow control param set incorrectly\n");
559 bool autoneg_wait_to_complete)
574 if (autoneg_wait_to_complete) {
588 DEBUGOUT(
"Autonegotiation did not complete.\n");
627 DEBUGOUT(
"Link was indicated but link is down\n");
645 bool link_up_wait_to_complete)
649 u16 link_reg, adapt_comp_reg;
664 if (link_up_wait_to_complete) {
666 if ((link_reg & 1) &&
667 ((adapt_comp_reg & 1) == 0)) {
682 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
688 if (*link_up ==
false)
693 if (link_up_wait_to_complete) {
734 bool autoneg_wait_to_complete)
736 bool autoneg =
false;
740 u32 autoc = curr_autoc;
747 speed &= link_capabilities;
755 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
760 if (autoc != curr_autoc)
771 autoneg_wait_to_complete);
788 bool autoneg_wait_to_complete)
792 DEBUGFUNC(
"ixgbe_setup_copper_link_82598");
796 autoneg_wait_to_complete);
838 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
844 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
850 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
856 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
885 for (i = 0; i < 10; i++) {
893 DEBUGOUT(
"Reset polling failed to complete.\n");
904 hw->
mac.
flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
909 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
955 if (rar >= rar_entries) {
956 DEBUGOUT1(
"RAR index %d is out of range.\n", rar);
961 rar_high &= ~IXGBE_RAH_VIND_MASK;
981 if (rar >= rar_entries) {
982 DEBUGOUT1(
"RAR index %d is out of range.\n", rar);
988 rar_high &= ~IXGBE_RAH_VIND_MASK;
1006 bool vlan_on,
bool vlvf_bypass)
1021 regindex = (vlan >> 5) & 0x7F;
1024 vftabyte = ((vlan >> 3) & 0x03);
1025 bitindex = (vlan & 0x7) << 2;
1029 bits &= (~(0x0F << bitindex));
1030 bits |= (vind << bitindex);
1034 bitindex = vlan & 0x1F;
1039 bits |= (1 << bitindex);
1042 bits &= ~(1 << bitindex);
1061 for (offset = 0; offset < hw->
mac.
vft_size; offset++)
1064 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1065 for (offset = 0; offset < hw->
mac.
vft_size; offset++)
1084 DEBUGFUNC(
"ixgbe_read_analog_reg8_82598");
1091 *val = (
u8)atlas_ctl;
1108 DEBUGFUNC(
"ixgbe_write_analog_reg8_82598");
1110 atlas_ctl = (reg << 8) | val;
1128 u8 byte_offset,
u8 *eeprom_data)
1153 sfp_addr = (dev_addr << 8) + byte_offset;
1161 for (i = 0; i < 100; i++) {
1173 DEBUGOUT(
"EEPROM read did not pass.\n");
1182 *eeprom_data = (
u8)(sfp_data >> 8);
1204 byte_offset, eeprom_data);
1219 byte_offset, sff8472_data);
1234 u16 ext_ability = 0;
1236 DEBUGFUNC(
"ixgbe_get_supported_physical_layer_82598");
1321 return physical_layer;
1338 DEBUGFUNC(
"ixgbe_set_lan_id_multi_port_pcie_82598");
1344 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1368 DEBUGFUNC(
"ixgbe_enable_relaxed_ordering_82598");
1396 u32 headroom,
int strategy)
static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom, int strategy)
#define IXGBE_82598_MC_TBL_SIZE
void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)
static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, bool vlvf_bypass)
s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, bool autoneg_wait_to_complete)
#define IXGBE_82598_MAX_TX_QUEUES
static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
#define IXGBE_82598_VFT_TBL_SIZE
s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
#define IXGBE_82598_RX_PB_SIZE
static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete)
static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, u8 byte_offset, u8 *eeprom_data)
static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
#define IXGBE_82598_RAR_ENTRIES
void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
#define IXGBE_82598_MAX_RX_QUEUES
static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, u8 *sff8472_data)
void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
#define IXGBE_RXPBSIZE_48KB
#define IXGBE_RXPBSIZE_80KB
#define IXGBE_TXPBSIZE_40KB
#define IXGBE_RXPBSIZE_64KB
#define IXGBE_READ_REG(a, reg)
#define IXGBE_READ_PCIE_WORD
#define IXGBE_WRITE_PCIE_WORD
#define UNREFERENCED_1PARAMETER(_p)
#define IXGBE_WRITE_FLUSH(a)
#define IXGBE_WRITE_REG(a, reg, val)
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *autoneg)
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, u16 *list_offset, u16 *data_offset)
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version)
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up)
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
#define IXGBE_I2C_EEPROM_STATUS_PASS
#define IXGBE_I2C_EEPROM_DEV_ADDR
#define IXGBE_I2C_EEPROM_STATUS_MASK
#define IXGBE_I2C_EEPROM_DEV_ADDR2
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS
#define IXGBE_I2C_EEPROM_READ_MASK
#define IXGBE_PHYSICAL_LAYER_10GBASE_SR
#define IXGBE_DEV_ID_82598EB_CX4
#define IXGBE_MDIO_PHY_1000BASET_ABILITY
#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4
#define IXGBE_ERR_SWFW_SYNC
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
#define IXGBE_MDIO_PHY_EXT_ABILITY
#define IXGBE_AUTOC_LMS_1G_AN
#define IXGBE_LINKS_KX_AN_COMP
#define IXGBE_AUTOC_10G_KX4
#define IXGBE_AUTO_NEG_TIME
#define IXGBE_RMCS_TFCE_PRIORITY
#define IXGBE_PHYSICAL_LAYER_10GBASE_T
#define IXGBE_PHYSICAL_LAYER_100BASE_TX
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX
#define IXGBE_GCR_CAP_VER2
#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT
#define IXGBE_DEV_ID_82598EB_SFP_LOM
#define IXGBE_DCB_MAX_TRAFFIC_CLASS
#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN
#define IXGBE_MII_AUTONEG_LINK_UP
#define IXGBE_PHYSICAL_LAYER_UNKNOWN
#define IXGBE_DCA_MAX_QUEUES_82598
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT
#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN
#define IXGBE_STATUS_LAN_ID_1
#define IXGBE_ATLAS_PDN_1G
#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN
#define IXGBE_GSSR_PHY1_SM
#define IXGBE_DEV_ID_82598AF_DUAL_PORT
#define IXGBE_RMCS_TFCE_802_3X
#define IXGBE_ATLAS_PDN_10G
#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
#define IXGBE_DCA_TXCTRL(_i)
#define IXGBE_RXPBSIZE(_i)
#define IXGBE_PCIE_CTRL2_DISABLE_SELECT
#define IXGBE_TXPBSIZE(_i)
#define IXGBE_LINK_SPEED_UNKNOWN
#define IXGBE_AUTOC_KX4_SUPP
#define IXGBE_ERR_INVALID_LINK_SETTINGS
#define IXGBE_AUTOC_LMS_MASK
#define IXGBE_VFTAVIND(_j, _i)
#define IXGBE_MDIO_PHY_10GBASET_ABILITY
#define IXGBE_DEV_ID_82598AT2
#define IXGBE_MDIO_AUTO_NEG_STATUS
#define IXGBE_AUTOC_10G_PMA_PMD_MASK
@ ixgbe_media_type_unknown
@ ixgbe_media_type_copper
@ ixgbe_media_type_backplane
#define IXGBE_FCTRL_RPFCE
#define IXGBE_GSSR_PHY0_SM
#define IXGBE_DCA_RXCTRL(_i)
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE
#define IXGBE_DEV_ID_82598_DA_DUAL_PORT
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR
#define IXGBE_AUTOC_AN_RESTART
#define IXGBE_MII_AUTONEG_COMPLETE
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA
#define IXGBE_LINKS_SPEED
#define IXGBE_ATLAS_PDN_LPBK
#define IXGBE_DEV_ID_82598EB_XF_LR
#define IXGBE_RAH_VIND_MASK
#define IXGBE_AUTOC_1G_KX
#define IXGBE_PHYSICAL_LAYER_1000BASE_BX
#define IXGBE_MAX_PACKET_BUFFERS
#define IXGBE_AUTOC_10G_CX4
#define IXGBE_MDIO_PHY_100BASETX_ABILITY
#define IXGBE_ERR_INVALID_ARGUMENT
#define IXGBE_GCR_CMPL_TMOUT_MASK
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE
#define IXGBE_AUTOC_LMS_KX4_AN
#define IXGBE_ATLAS_PDN_AN
#define IXGBE_LINK_SPEED_1GB_FULL
#define IXGBE_AUTOC_KX_SUPP
#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4
#define IXGBE_DEV_ID_82598AF_SINGLE_PORT
#define IXGBE_DCA_TXCTRL_DESC_WRO_EN
#define IXGBE_ERR_LINK_SETUP
#define IXGBE_PCI_DEVICE_CONTROL2
#define IXGBE_LINK_SPEED_10GB_FULL
#define IXGBE_VALIDATE_LINK_READY_TIMEOUT
#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE
#define IXGBE_DCA_RXCTRL_DATA_WRO_EN
#define IXGBE_DEV_ID_82598AT
#define IXGBE_PCI_DEVICE_CONTROL2_16ms
#define IXGBE_ATLASCTL_WRITE_CMD
#define IXGBE_PCIE_GENERAL_PTR
#define IXGBE_AUTOC_1G_PMA_PMD_MASK
#define IXGBE_GCR_CMPL_TMOUT_10ms
#define IXGBE_DEV_ID_82598_BX
#define IXGBE_RAH_VIND_SHIFT
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR
#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
#define IXGBE_ERR_SFP_NOT_PRESENT
#define IXGBE_PCIE_CTRL2_LAN_DISABLE
#define IXGBE_PHYSICAL_LAYER_1000BASE_T
#define IXGBE_ERR_AUTONEG_NOT_COMPLETE
#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN
#define IXGBE_DEV_ID_82598
#define IXGBE_ATLAS_PDN_TX_REG_EN
#define IXGBE_ERR_SFP_NOT_SUPPORTED
#define IXGBE_ERR_RESET_FAILED
struct ixgbe_eeprom_operations ops
s32(* read)(struct ixgbe_hw *, u16, u16 *)
enum ixgbe_fc_mode current_mode
u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]
u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]
enum ixgbe_fc_mode requested_mode
struct ixgbe_mac_info mac
struct ixgbe_bus_info bus
struct ixgbe_eeprom_info eeprom
struct ixgbe_phy_info phy
bool orig_link_settings_stored
u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
struct ixgbe_mac_operations ops
s32(* set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32, bool)
s32(* reset_hw)(struct ixgbe_hw *)
s32(* acquire_swfw_sync)(struct ixgbe_hw *, u32)
s32(* fc_enable)(struct ixgbe_hw *)
s32(* set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, const char *)
s32(* get_mac_addr)(struct ixgbe_hw *, u8 *)
s32(* init_rx_addrs)(struct ixgbe_hw *)
s32(* enable_rx_dma)(struct ixgbe_hw *, u32)
s32(* setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool)
void(* release_swfw_sync)(struct ixgbe_hw *, u32)
s32(* read_analog_reg8)(struct ixgbe_hw *, u32, u8 *)
s32(* clear_vmdq)(struct ixgbe_hw *, u32, u32)
s32(* clear_vfta)(struct ixgbe_hw *)
void(* setup_rxpba)(struct ixgbe_hw *, int, u32, int)
s32(* set_vmdq)(struct ixgbe_hw *, u32, u32)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool)
void(* get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map)
s32(* set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool)
s32(* write_analog_reg8)(struct ixgbe_hw *, u32, u8)
void(* enable_relaxed_ordering)(struct ixgbe_hw *)
s32(* get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
void(* set_lan_id)(struct ixgbe_hw *)
void(* flap_tx_laser)(struct ixgbe_hw *)
enum ixgbe_media_type(* get_media_type)(struct ixgbe_hw *)
s32(* start_hw)(struct ixgbe_hw *)
s32(* stop_adapter)(struct ixgbe_hw *)
u64(* get_supported_physical_layer)(struct ixgbe_hw *)
enum ixgbe_media_type media_type
struct ixgbe_phy_operations ops
enum ixgbe_sfp_type sfp_type
s32(* read_i2c_eeprom)(struct ixgbe_hw *, u8, u8 *)
s32(* setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool)
s32(* init)(struct ixgbe_hw *)
s32(* get_firmware_version)(struct ixgbe_hw *, u16 *)
s32(* reset)(struct ixgbe_hw *)
s32(* identify)(struct ixgbe_hw *)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *)
s32(* read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *)
s32(* write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16)
s32(* read_reg)(struct ixgbe_hw *, u32, u32, u16 *)
s32(* setup_link)(struct ixgbe_hw *)
s32(* read_i2c_sff8472)(struct ixgbe_hw *, u8, u8 *)
s32(* identify_sfp)(struct ixgbe_hw *)